module_content
stringlengths 18
1.05M
|
|---|
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P,
parameter els_p = `ELS_P,
parameter reset_cycles_lo_p=0,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d", width_p);
$display("ELS_P : %d\n", els_p);
end
logic [els_p-1:0][width_p-1:0] test_input_data;
logic [`BSG_SAFE_CLOG2(els_p)-1:0] test_input_sel;
logic [width_p-1:0] test_output;
genvar i;
generate
for(i=0; i<els_p; ++i)
assign test_input_data[i] = width_p'(i);
endgenerate
always_ff @(posedge clk)
begin
if(reset)
test_input_sel <= `BSG_SAFE_CLOG2(els_p) ' (1'b0);
else
test_input_sel <= test_input_sel + 1;
end
always_ff @(posedge clk)
begin
/*$display("\ntest_input_data[sel] : %b, test_output: %b"
, width_p'(test_input_sel), test_output);*////
if(!reset)
assert (test_output==width_p'(test_input_sel))
else $error("mismatch on input %x", test_input_sel);
if(test_input_sel==(els_p-1))
begin
$display("===============================================================\n");
$finish;
end
end
bsg_mux #( .width_p (width_p)
, .els_p (els_p)
, .lg_els_lp()
) DUT
( .data_i(test_input_data)
, .sel_i (test_input_sel)
, .data_o(test_output)
);
/*logic [(2*width_p)-1:0] log;
assign log = {test_output,
width_p'(test_input_sel)};
bsg_nonsynth_ascii_writer #( .width_p (width_p)
, .values_p (2)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%b")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i (log)
);*/
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule |
module instance
fifo #(
.DATA_WIDTH(DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH)
) fifo (
.wr_data(wr_data),
.wr_clk(wr_clk),
.wr_en(wr_en),
.rd_data(rd_data),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rd_valid(rd_valid),
.full(full),
.empty(empty),
.reset(reset)
);
// Write Clock Generation
always
#5 wr_clk = !wr_clk;
// Write Data Generation
always
#10 wr_data = !wr_data;
// Read Clock Generation
always
#3 rd_clk = !rd_clk & !full;
// Reset Generation
initial begin
#2 reset = 1;
#2 reset = 0;
end
endmodule |
module mig_7series_v2_0_qdr_rld_phy_rdlvl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter MEMORY_IO_DIR = "UNIDIR",
parameter CPT_CLK_CQ_ONLY = "TRUE",
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter REFCLK_FREQ = 300.0, // Indicates the IDELAYCTRL reference clock frequency
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter RANKS = 1, // # of DRAM ranks
parameter PI_ADJ_GAP = 7, // Time to wait between PI adjustments
parameter RTR_CALIBRATION = "OFF", // Read-Training Register Calibration
parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk,
input rst,
// Calibration status, control signals
input rdlvl_stg1_start,
output reg rdlvl_stg1_done,
output rdlvl_stg1_rnk_done,
output reg rdlvl_stg1_err,
output reg rdlvl_prech_req,
input prech_done,
input rtr_cal_done,
// Captured data in fabric clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Stage 1 calibration outputs
output reg pi_en_stg2_f,
output reg pi_stg2_f_incdec,
output reg pi_stg2_load,
output reg [5:0] pi_stg2_reg_l,
//output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt,
output [DQS_CNT_WIDTH-1:0] pi_stg2_rdlvl_cnt,
output reg po_en_stg2_f,
output reg po_stg2_f_incdec,
output reg po_stg2_load,
output reg [5:0] po_stg2_reg_l,
//output [DQS_CNT_WIDTH:0] po_stg2_rdlvl_cnt,
output [DQS_CNT_WIDTH-1:0] po_stg2_rdlvl_cnt,
// output reg idelay_ce,
// output reg idelay_inc,
// Only output if Per-bit de-skew enabled
output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// Debug Port
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
input dbg_SM_en,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl
);
// minimum time (in IDELAY taps) for which capture data must be stable for
// algorithm to consider a valid data eye to be found. The read leveling
// logic will ignore any window found smaller than this value. Limitations
// on how small this number can be is determined by: (1) the algorithmic
// limitation of how many taps wide the data eye can be (3 taps), and (2)
// how wide regions of "instability" that occur around the edges of the
// read valid window can be (i.e. need to be able to filter out "false"
// windows that occur for a short # of taps around the edges of the true
// data window, although with multi-sampling during read leveling, this is
// not as much a concern) - the larger the value, the more protection
// against "false" windows
localparam MIN_EYE_SIZE = 5;
// minimum idelay taps of valid window to be seen, to help differentiate any false positives
// while the clock samples the uncertainty region.
localparam MIN_Q_VALID_TAPS = 3;
// # of clock cycles to wait after changing IDELAY value or read data MUX
// to allow both IDELAY chain to settle, and for delayed input to
// propagate thru ISERDES
localparam PIPE_WAIT_CNT = 24;
// Length of calibration sequence (in # of words)
localparam CAL_PAT_LEN = (nCK_PER_CLK == 2) ? 4 : 8;
// Read data shift register length
localparam RD_SHIFT_LEN = CAL_PAT_LEN/(nCK_PER_CLK);
// # of read data samples to examine when detecting whether an edge has
// occured during stage 1 calibration. Width of local param must be
// changed as appropriate. Note that there are two counters used, each
// counter can be changed independently of the other - they are used in
// cascade to create a larger counter
localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF;
localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h000; //12'h001;
// # of taps in IDELAY chain. When the phase detector taps are reserved
// before the start of calibration, reduce half that amount from the
// total available taps.
// clogb2 function - ceiling of log base 2
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam DQ_CNT_WIDTH = clogb2(DQ_WIDTH);
localparam DRAM_WIDTH_P2 = clogb2(DRAM_WIDTH-1);
localparam DRAM_WIDTH_R2 = ( DRAM_WIDTH % 2 );
localparam [5:0] CAL1_IDLE = 6'h00;
localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01;
localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02;
localparam [5:0] CAL1_DETECT_EDGE = 6'h03;
localparam [5:0] CAL1_IDEL_STORE_OLD = 6'h04;
localparam [5:0] CAL1_IDEL_INC_CPT = 6'h05;
localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h06;
localparam [5:0] CAL1_CALC_IDEL = 6'h07;
localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h08;
localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h09;
localparam [5:0] CAL1_NEXT_DQS = 6'h0A;
localparam [5:0] CAL1_DONE = 6'h0B;
localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h0C;
localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h0D;
localparam [5:0] CAL1_PB_INC_CPT = 6'h0E;
localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h0F;
localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h10;
localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h11;
localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h12;
localparam [5:0] CAL1_PB_INC_DQ = 6'h13;
localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h14;
localparam [5:0] CAL1_PB_DEC_CPT = 6'h15;
localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h16;
localparam [5:0] CAL1_DETECT_EDGE_Q = 6'h17;
localparam [5:0] CAL1_IDEL_INC_Q = 6'h18;
localparam [5:0] CAL1_IDEL_INC_Q_WAIT = 6'h19;
localparam [5:0] CAL1_IDEL_STORE_OLD_Q = 6'h1A;
localparam [5:0] CAL1_REGL_LOAD = 6'h1B;
localparam [5:0] CAL1_IDEL_DEC_Q = 6'h1C;
localparam [5:0] CAL1_IDEL_DEC_Q_WAIT = 6'h1D;
localparam [5:0] CAL1_IDEL_DEC_Q_ALL = 6'h1E;
localparam [5:0] CAL1_IDEL_DEC_Q_ALL_WAIT = 6'h1F;
localparam [5:0] CAL1_CALC_IDEL_WAIT = 6'h20;
localparam [5:0] CAL1_FALL_DETECT_EDGE = 6'h21;
localparam [5:0] CAL1_FALL_IDEL_STORE_OLD = 6'h22;
localparam [5:0] CAL1_FALL_INC_CPT = 6'h23;
localparam [5:0] CAL1_FALL_INC_CPT_WAIT = 6'h24;
localparam [5:0] CAL1_FALL_CALC_DELAY = 6'h25;
localparam [5:0] CAL1_FALL_FINAL_DEC_TAP = 6'h26;
localparam [5:0] CAL1_FALL_FINAL_DEC_TAP_WAIT = 6'h27;
localparam [5:0] CAL1_FALL_DETECT_EDGE_WAIT = 6'h28;
localparam [5:0] CAL1_IDEL_FALL_DEC_CPT = 6'h29;
localparam [5:0] CAL1_IDEL_FALL_DEC_CPT_WAIT = 6'h30;
localparam [5:0] CAL1_FALL_IDEL_INC_Q = 6'h31;
localparam [5:0] CAL1_FALL_IDEL_INC_Q_WAIT = 6'h32;
localparam [5:0] CAL1_FALL_IDEL_RESTORE_Q = 6'h33;
localparam [5:0] CAL1_FALL_IDEL_RESTORE_Q_WAIT = 6'h34;
//Work around for now, RLD3 numbers at 533MHz for simple setup using nCK_PER_CLK == 4
localparam [5:0] SKIP_DLY_VAL = (nCK_PER_CLK == 2) ? 6'd31 : 6'd25;//(CLK_PERIOD > 2500) ? 6'd31 : 6'd00; //edited by RA
localparam [4:0] SKIP_DLY_VAL_DQ = (nCK_PER_CLK == 2) ? 5'd13 : (CLK_PERIOD < 1250) ? 5'd15 : 5'd2;
localparam [7:0] DATA_WIDTH = DRAM_WIDTH;
//localparam [DATA_WIDTH*8-1:0] DATA_STAGE1 =
// {{DATA_WIDTH{1'b0}}, {DATA_WIDTH{1'b1}},
// {DATA_WIDTH{1'b0}}, {DATA_WIDTH{1'b1}},
// {DATA_WIDTH{1'b1}}, {DATA_WIDTH{1'b0}},
// {DATA_WIDTH{1'b0}}, {DATA_WIDTH{1'b1}}};
localparam integer IODELAY_TAP_RES = 1000000 / (REFCLK_FREQ * 64); // IDELAY tap resolution in ps
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, DIV4: MemRefClk < 200 MHz - //DIV4 not supported
localparam PHY_FREQ_REF_MODE = CLK_PERIOD > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = PHY_FREQ_REF_MODE == "DIV2" ? 2 : 1;
//FreqRefClk (MHz) is 1,2,4 times faster than MemRefClk
localparam real FREQ_REF_MHZ = 1.0/((CLK_PERIOD/FREQ_REF_DIV/1000.0) / 1000) ;
localparam integer PHASER_TAP_RES = 1000000 / (FREQ_REF_MHZ * 128) ;
//localparam DELAY_CENTER_MODE = CLK_DATA; //CLK_DATA - look for window by delaying clk and data, use only data taps if needed.
// CLK - use data delay on the data to only align clk and data. centering is done only using Phaser taps on the clock.
// expected data could be one of the two depending on the iserdes clkdiv alignment
// R0 0-1-0-1 (OR) 0-0-0-0
// F0 1-0-1-0 1-1-1-1
// R1 0-0-0-0 0-1-0-1
// F1 1-1-1-1 1-0-1-0
integer i;
integer j;
integer k;
integer l;
integer m;
integer n;
integer r;
integer p;
integer q;
genvar x;
genvar z;
reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r;
reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_2r;
wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing;
reg cal1_dlyce_cpt_r;
reg cal1_dlyinc_cpt_r;
reg cal1_dlyce_dq_r;
reg cal1_dlyinc_dq_r;
reg cal1_wait_cnt_en_r;
reg [4:0] cal1_wait_cnt_r;
reg cal1_wait_r;
reg [DQ_WIDTH-1:0] dlyce_dq_r;
reg dlyinc_dq_r;
reg [5*DQ_WIDTH*RANKS-1:0] dlyval_dq_reg_r;
reg cal1_prech_req_r;
reg [5:0] cal1_state_r;
reg [5:0] cal1_state_r1;
reg [5:0] cnt_idel_dec_cpt_r; // capture how many taps need to decrement down to PI's final tap position
reg [5:0] fall_dec_taps_r;
reg [5:0] cnt_rise_center_taps;
reg [5:0] fall_win_det_end_taps_r;
reg [5:0] fall_win_det_start_taps_r;
reg phaser_taps_meet_fall_window;
reg [2:0] pi_gap_enforcer;
reg [5:0] idel_dec_cntr;
reg [5:0] idelay_inc_taps_r;
reg [11:0] idelay_tap_delay;
wire [11:0] idelay_tap_delay_sl_clk;
wire [11:0] phaser_tap_delay;
reg [11:0] phaser_tap_delay_sl_clk;
reg [3:0] cnt_shift_r;
reg detect_edge_done_r;
reg [5:0] first_edge_taps_r; // first edge tap position during rising bit window
reg found_edge_r;
reg found_first_edge_r;
reg found_second_edge_r;
reg found_stable_eye_r;
reg found_stable_eye_last_r;
reg found_edge_all_r;
reg [5:0] tap_cnt_cpt_r;
reg tap_limit_cpt_r;
reg cqn_tap_limit_cpt_r;
reg [4:0] idel_tap_cnt_dq_pb_r;
reg idel_tap_limit_dq_pb_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg new_cnt_cpt_r;
reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0];
wire [3:0] rd_window [DRAM_WIDTH-1:0];
wire [3:0] fd_window [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] rise_data_valid_r;
reg [DRAM_WIDTH-1:0] fall_data_valid_r;
wire rise_data_valid;
//wire fall_data_valid;
wire data_valid;
reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r;
reg [2:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r;
reg [DRAM_WIDTH-1:0] pb_found_edge_last_r;
reg [DRAM_WIDTH-1:0] pb_found_edge_r;
reg [DRAM_WIDTH-1:0] pb_found_first_edge_r;
reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r;
reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
reg [DRAM_WIDTH-1:0] prev_sr_diff_r;
reg [DRAM_WIDTH-1:0] prev_rise_sr_diff_r;
reg [DRAM_WIDTH-1:0] prev_fall_sr_diff_r;
reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r;
reg [DRAM_WIDTH-1:0] prev_rise_sr_match_cyc2_r;
reg [DRAM_WIDTH-1:0] prev_fall_sr_match_cyc2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r;
wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_rise3 [3:0];
reg pat0_data_match_r;
reg pat1_data_match_r;
reg pat2_data_match_r;
reg pat3_data_match_r;
reg pat0_data_rise_match_r;
reg pat1_data_rise_match_r;
reg pat2_data_rise_match_r;
reg pat3_data_rise_match_r;
reg pat0_data_fall_match_r;
reg pat1_data_fall_match_r;
reg pat2_data_fall_match_r;
reg pat3_data_fall_match_r;
wire rise_match;
wire fall_match;
wire pat_match;
wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat3_fall3 [3:0];
reg [DRAM_WIDTH-1:0] pat0_match_fall0_r;
reg pat0_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall1_r;
reg pat0_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall2_r;
reg pat0_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall3_r;
reg pat0_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise0_r;
reg pat0_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise1_r;
reg pat0_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise2_r;
reg pat0_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise3_r;
reg pat0_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg pat1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg pat1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall2_r;
reg pat1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall3_r;
reg pat1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg pat1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg pat1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise2_r;
reg pat1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise3_r;
reg pat1_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg pat2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall2_r;
reg pat2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall3_r;
reg pat2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg pat2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg pat2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise2_r;
reg pat2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise3_r;
reg pat2_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_fall0_r;
reg pat3_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_fall1_r;
reg pat3_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_fall2_r;
reg pat3_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_fall3_r;
reg pat3_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_rise0_r;
reg pat3_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_rise1_r;
reg pat3_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_rise2_r;
reg pat3_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat3_match_rise3_r;
reg pat3_match_rise3_and_r;
reg [DQ_WIDTH-1:0] rd_data_rise0;
reg [DQ_WIDTH-1:0] rd_data_fall0;
reg [DQ_WIDTH-1:0] rd_data_rise1;
reg [DQ_WIDTH-1:0] rd_data_fall1;
reg [DQ_WIDTH-1:0] rd_data_rise2;
reg [DQ_WIDTH-1:0] rd_data_fall2;
reg [DQ_WIDTH-1:0] rd_data_rise3;
reg [DQ_WIDTH-1:0] rd_data_fall3;
// reg [4:0] right_edge_taps_r;
reg samp_cnt_done_r;
reg samp_edge_cnt0_en_r;
reg [11:0] samp_edge_cnt0_r;
reg samp_edge_cnt1_en_r;
reg [11:0] samp_edge_cnt1_r;
// reg [4:0] second_edge_dq_taps_r;
reg [5:0] second_edge_taps_r;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
/*reg [DRAM_WIDTH-1 :0] sr0_rise0_r; //Not used, remove
reg [DRAM_WIDTH-1 :0] sr0_fall0_r;
reg [DRAM_WIDTH-1 :0] sr0_rise1_r;
reg [DRAM_WIDTH-1 :0] sr0_fall1_r;
reg [DRAM_WIDTH-1 :0] sr0_rise2_r;
reg [DRAM_WIDTH-1 :0] sr0_fall2_r;
reg [DRAM_WIDTH-1 :0] sr0_rise3_r;
reg [DRAM_WIDTH-1 :0] sr0_fall3_r;
reg [DRAM_WIDTH-1 :0] sr1_rise0_r;
reg [DRAM_WIDTH-1 :0] sr1_fall0_r;
reg [DRAM_WIDTH-1 :0] sr1_rise1_r;
reg [DRAM_WIDTH-1 :0] sr1_fall1_r;
reg [DRAM_WIDTH-1 :0] sr1_rise2_r;
reg [DRAM_WIDTH-1 :0] sr1_fall2_r;
reg [DRAM_WIDTH-1 :0] sr1_rise3_r;
reg [DRAM_WIDTH-1 :0] sr1_fall3_r; */
reg store_sr_done_r;
reg store_sr_r;
reg store_sr_req_r;
reg sr_valid_r;
reg sr_valid_r1;
reg sr_valid_r2;
reg [DRAM_WIDTH-1:0] old_sr_diff_r;
reg [DRAM_WIDTH-1:0] old_rise_sr_diff_r;
reg [DRAM_WIDTH-1:0] old_fall_sr_diff_r;
reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r;
//reg [DRAM_WIDTH-1:0] old_rise_sr_match_cyc2_r;
//reg [DRAM_WIDTH-1:0] old_fall_sr_match_cyc2_r;
reg [6*DQS_WIDTH*RANKS-1:0] pi_rdlvl_dqs_tap_cnt_r;
reg [6*DQS_WIDTH*RANKS-1:0] po_rdlvl_dqs_tap_cnt_r;
reg [DRAM_WIDTH-1:0] old_rise_sr_match_cyc2_r;
reg [DRAM_WIDTH-1:0] old_fall_sr_match_cyc2_r;
reg [6*DQS_WIDTH*RANKS-1:0] rdlvl_dqs_tap_cnt_r;
reg [1:0] rnk_cnt_r;
reg rdlvl_rank_done_r;
reg [3:0] done_cnt;
reg [1:0] regl_rank_cnt;
reg [DQS_CNT_WIDTH:0] regl_dqs_cnt;
wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing;
reg regl_rank_done_r;
reg [23:0] rdlvl_start_r ;
reg set_fall_capture_clock_at_tap0;
/*reg rdlvl_start_2r ;
reg rdlvl_start_3r ;
reg rdlvl_start_4r ;
reg rdlvl_start_5r ;
reg rdlvl_start_6r ;
reg rdlvl_start_7r ;
reg rdlvl_start_8r ;
reg rdlvl_start_9r ;
reg rdlvl_start_10r;
reg rdlvl_start_11r;
reg rdlvl_start_12r;
reg rdlvl_start_13r;
reg rdlvl_start_14r;
reg rdlvl_start_15r;
reg rdlvl_start_16r;
reg rdlvl_start_17r;
reg rdlvl_start_18r;
reg rdlvl_start_19r;
reg rdlvl_start_20r;
reg rdlvl_start_21r;
reg rdlvl_start_22r;
reg rdlvl_start_23r;
reg rdlvl_start_24r;*/
wire rdlvl_start;
reg cal1_dlyce_q_r;
reg cal1_dlyinc_q_r;
reg [5:0] idel_tap_cnt_cpt_r;
reg [5:0] stored_idel_tap_cnt_cpt_r;
reg idel_tap_limit_cpt_r;
reg qdly_inc_done_r;
reg start_win_detect;
reg end_win_detect;
reg [5:0] start_win_taps;
reg [5:0] end_win_taps;
reg [5:0] idelay_taps;
reg clk_in_vld_win;
reg idelay_ce;
reg idelay_inc;
reg idel_gt_phaser_delay;
reg [11:0] idel_minus_phaser_delay;
reg [11:0] phaser_minus_idel_delay;
reg [5:0] phaser_dec_taps;
reg cal1_dec_cnt;
reg rise_detect_done;
reg fall_first_edge_det_done; // assert fall_first_edge_det_done if window is valid for at least some taps,
// continue to increment until edge found
(* KEEP = "TRUE" *) reg [DQ_CNT_WIDTH:0] rd_mux_sel_r_mult_r /* synthesis syn_keep=1 */;
(* KEEP = "TRUE" *) reg [DQ_CNT_WIDTH:0] rd_mux_sel_r_mult_f /* synthesis syn_keep=1 */;
wire [DQ_CNT_WIDTH:0] rd_mux_sel_r_p2;
// Debug
reg [4:0] dbg_cpt_first_edge_taps [0:DQS_WIDTH-1];
reg [4:0] dbg_cpt_second_edge_taps [0:DQS_WIDTH-1];
reg [3:0] dbg_stg1_calc_edge;
reg [DQS_WIDTH-1:0] dbg_phy_rdlvl_err;
wire pb_detect_edge_setup;
wire pb_detect_edge;
//***************************************************************************
// Debug
//***************************************************************************
assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; //72
assign dbg_phy_rdlvl[1] = rdlvl_start;
assign dbg_phy_rdlvl[2] = found_edge_r;
assign dbg_phy_rdlvl[3] = pat0_data_match_r;
assign dbg_phy_rdlvl[4] = pat1_data_match_r;
assign dbg_phy_rdlvl[5] = data_valid;
assign dbg_phy_rdlvl[6] = cal1_wait_r;
assign dbg_phy_rdlvl[7] = rise_match;
assign dbg_phy_rdlvl[13:8] = cal1_state_r[5:0]; //85:81
assign dbg_phy_rdlvl[20:14] = cnt_idel_dec_cpt_r;// 92:86
assign dbg_phy_rdlvl[21] = found_first_edge_r;
assign dbg_phy_rdlvl[22] = found_second_edge_r;//94
assign dbg_phy_rdlvl[23] = fall_match;
assign dbg_phy_rdlvl[24] = store_sr_r;//96
assign dbg_phy_rdlvl[32:25] = {sr_fall1_r[0][1:0], sr_rise1_r[0][1:0],
sr_fall0_r[0][1:0], sr_rise0_r[0][1:0]}; //104:
assign dbg_phy_rdlvl[40:33] = {old_sr_fall1_r[0][1:0],
old_sr_rise1_r[0][1:0],
old_sr_fall0_r[0][1:0],
old_sr_rise0_r[0][1:0]}; // 112:105
assign dbg_phy_rdlvl[41] = sr_valid_r;
assign dbg_phy_rdlvl[42] = found_stable_eye_r;
assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; // 120:115
assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; // 126:121
assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; //132:127
assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_r; // 136:133
assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r;
assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r;
assign dbg_phy_rdlvl[67] = rise_detect_done;
assign dbg_phy_rdlvl[68] = found_stable_eye_last_r; //140
assign dbg_phy_rdlvl[74:69] = idelay_taps[5:0]; //146:141
assign dbg_phy_rdlvl[80:75] = start_win_taps[5:0];
assign dbg_phy_rdlvl[81] = idel_tap_limit_cpt_r;
assign dbg_phy_rdlvl[82] = qdly_inc_done_r;
assign dbg_phy_rdlvl[83] = start_win_detect;
assign dbg_phy_rdlvl[84] = detect_edge_done_r;
assign dbg_phy_rdlvl[90:85] = idel_tap_cnt_cpt_r[5:0];
assign dbg_phy_rdlvl[96:91] = idelay_inc_taps_r[5:0];
assign dbg_phy_rdlvl[102:97] = idel_dec_cntr[5:0];
assign dbg_phy_rdlvl[103] = tap_limit_cpt_r;
assign dbg_phy_rdlvl[115:104] = idelay_tap_delay[11:0];
assign dbg_phy_rdlvl[127:116] = phaser_tap_delay[11:0];
assign dbg_phy_rdlvl[128 +: 6] = fall_win_det_start_taps_r[5:0]; //398
assign dbg_phy_rdlvl[134 +: 6] = fall_win_det_end_taps_r[5:0];
assign dbg_phy_rdlvl[140 +: 24]= dbg_cpt_first_edge_cnt; //270 410
assign dbg_phy_rdlvl[164 +: 20]= dbg_cpt_second_edge_cnt;
assign dbg_phy_rdlvl[187:184] = dbg_stg1_calc_edge;
assign dbg_phy_rdlvl[195:188] = dbg_phy_rdlvl_err;
assign dbg_phy_rdlvl[255:196] = 'b0;
always @(posedge clk ) begin
//only reset if we are skipping calibration. Reset doesn't last long enough
//to clear these registers when we are re-starting
if ((SIM_CAL_OPTION == "SKIP_CAL") && rst) begin
rdlvl_start_r <= #TCQ 'b0;
end else begin
rdlvl_start_r[0] <= #TCQ rdlvl_stg1_start;
rdlvl_start_r[23:1] <= #TCQ {rdlvl_start_r[22:1], rdlvl_start_r[0]};
end
end
assign rdlvl_start = rdlvl_start_r[23];
generate
if (CLK_PERIOD > 2500) begin : clk_less_than_400_MHz
assign idelay_tap_delay_sl_clk = { 6'h0, idelay_taps };
//always @ (posedge clk) begin
always @ (*) begin
case (first_edge_taps_r)
6'h 0_0 : phaser_tap_delay_sl_clk = (0 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_1 : phaser_tap_delay_sl_clk = (1 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_2 : phaser_tap_delay_sl_clk = (2 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_3 : phaser_tap_delay_sl_clk = (3 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_4 : phaser_tap_delay_sl_clk = (4 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_5 : phaser_tap_delay_sl_clk = (5 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_6 : phaser_tap_delay_sl_clk = (6 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_7 : phaser_tap_delay_sl_clk = (7 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_8 : phaser_tap_delay_sl_clk = (8 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_9 : phaser_tap_delay_sl_clk = (9 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_A : phaser_tap_delay_sl_clk = (10 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_B : phaser_tap_delay_sl_clk = (11 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_C : phaser_tap_delay_sl_clk = (12 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_D : phaser_tap_delay_sl_clk = (13 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_E : phaser_tap_delay_sl_clk = (14 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 0_F : phaser_tap_delay_sl_clk = (15 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_0 : phaser_tap_delay_sl_clk = (16 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_1 : phaser_tap_delay_sl_clk = (17 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_2 : phaser_tap_delay_sl_clk = (18 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_3 : phaser_tap_delay_sl_clk = (19 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_4 : phaser_tap_delay_sl_clk = (20 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_5 : phaser_tap_delay_sl_clk = (21 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_6 : phaser_tap_delay_sl_clk = (22 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_7 : phaser_tap_delay_sl_clk = (23 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_8 : phaser_tap_delay_sl_clk = (24 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_9 : phaser_tap_delay_sl_clk = (25 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_A : phaser_tap_delay_sl_clk = (26 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_B : phaser_tap_delay_sl_clk = (27 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_C : phaser_tap_delay_sl_clk = (28 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_D : phaser_tap_delay_sl_clk = (29 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_E : phaser_tap_delay_sl_clk = (30 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 1_F : phaser_tap_delay_sl_clk = (31 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_0 : phaser_tap_delay_sl_clk = (32 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_1 : phaser_tap_delay_sl_clk = (33 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_2 : phaser_tap_delay_sl_clk = (34 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_3 : phaser_tap_delay_sl_clk = (35 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_4 : phaser_tap_delay_sl_clk = (36 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_5 : phaser_tap_delay_sl_clk = (37 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_6 : phaser_tap_delay_sl_clk = (38 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_7 : phaser_tap_delay_sl_clk = (39 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_8 : phaser_tap_delay_sl_clk = (40 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_9 : phaser_tap_delay_sl_clk = (41 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_A : phaser_tap_delay_sl_clk = (42 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_B : phaser_tap_delay_sl_clk = (43 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_C : phaser_tap_delay_sl_clk = (44 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_D : phaser_tap_delay_sl_clk = (45 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_E : phaser_tap_delay_sl_clk = (46 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 2_F : phaser_tap_delay_sl_clk = (47 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_0 : phaser_tap_delay_sl_clk = (48 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_1 : phaser_tap_delay_sl_clk = (49 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_2 : phaser_tap_delay_sl_clk = (50 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_3 : phaser_tap_delay_sl_clk = (51 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_4 : phaser_tap_delay_sl_clk = (52 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_5 : phaser_tap_delay_sl_clk = (53 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_6 : phaser_tap_delay_sl_clk = (54 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_7 : phaser_tap_delay_sl_clk = (55 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_8 : phaser_tap_delay_sl_clk = (56 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_9 : phaser_tap_delay_sl_clk = (57 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_A : phaser_tap_delay_sl_clk = (58 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_B : phaser_tap_delay_sl_clk = (59 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_C : phaser_tap_delay_sl_clk = (60 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_D : phaser_tap_delay_sl_clk = (61 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_E : phaser_tap_delay_sl_clk = (62 * PHASER_TAP_RES)/IODELAY_TAP_RES;
6'h 3_F : phaser_tap_delay_sl_clk = (63 * PHASER_TAP_RES)/IODELAY_TAP_RES;
default : phaser_tap_delay_sl_clk = 'b0;
endcase
end
always @ (posedge clk) begin
idel_minus_phaser_delay <= (idelay_tap_delay_sl_clk - phaser_tap_delay_sl_clk);
end
end
endgenerate
//always @ (posedge clk) begin
always @ (*) begin
case (idelay_taps)
6'h 0_0 : idelay_tap_delay = (0 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_1 : idelay_tap_delay = (1 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_2 : idelay_tap_delay = (2 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_3 : idelay_tap_delay = (3 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_4 : idelay_tap_delay = (4 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_5 : idelay_tap_delay = (5 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_6 : idelay_tap_delay = (6 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_7 : idelay_tap_delay = (7 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_8 : idelay_tap_delay = (8 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_9 : idelay_tap_delay = (9 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_A : idelay_tap_delay = (10 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_B : idelay_tap_delay = (11 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_C : idelay_tap_delay = (12 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_D : idelay_tap_delay = (13 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_E : idelay_tap_delay = (14 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 0_F : idelay_tap_delay = (15 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_0 : idelay_tap_delay = (16 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_1 : idelay_tap_delay = (17 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_2 : idelay_tap_delay = (18 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_3 : idelay_tap_delay = (19 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_4 : idelay_tap_delay = (20 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_5 : idelay_tap_delay = (21 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_6 : idelay_tap_delay = (22 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_7 : idelay_tap_delay = (23 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_8 : idelay_tap_delay = (24 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_9 : idelay_tap_delay = (25 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_A : idelay_tap_delay = (26 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_B : idelay_tap_delay = (27 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_C : idelay_tap_delay = (28 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_D : idelay_tap_delay = (29 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_E : idelay_tap_delay = (30 * IODELAY_TAP_RES)/PHASER_TAP_RES;
6'h 1_F : idelay_tap_delay = (31 * IODELAY_TAP_RES)/PHASER_TAP_RES;
default : idelay_tap_delay = 'b0;
endcase
end
assign phaser_tap_delay = { 6'h0, first_edge_taps_r };
always @ (posedge clk) begin
idel_gt_phaser_delay <= (idelay_tap_delay > phaser_tap_delay) ? 1'b1 : 1'b0;
phaser_dec_taps <= (phaser_tap_delay - idelay_tap_delay)>>1;
end
// assign idelay_tap_delay = idelay_taps * IODELAY_TAP_RES;
// assign phaser_tap_delay = first_edge_taps_r * PHASER_TAP_RES;
assign po_stg2_rdlvl_cnt = pi_stg2_rdlvl_cnt;
//***************************************************************************
// Debug output
//***************************************************************************
// Record first and second edges found during CPT calibration
generate
genvar ce_i;
for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge
assign dbg_cpt_first_edge_cnt[(5*ce_i)+4:(5*ce_i)]
= dbg_cpt_first_edge_taps[ce_i];
assign dbg_cpt_second_edge_cnt[(5*ce_i)+4:(5*ce_i)]
= dbg_cpt_second_edge_taps[ce_i];
always @(posedge clk)
if (rst) begin
dbg_cpt_first_edge_taps[ce_i] <= #TCQ 'b0;
dbg_cpt_second_edge_taps[ce_i] <= #TCQ 'b0;
end else begin
// Record tap counts of first and second edge edges during
// CPT calibration for each DQS group. If neither edge has
// been found, then those taps will remain 0
if (cal1_state_r == CAL1_CALC_IDEL) begin
if (found_first_edge_r && (cal1_cnt_cpt_r == ce_i))
dbg_cpt_first_edge_taps[ce_i]
<= #TCQ first_edge_taps_r;
if (found_second_edge_r && (cal1_cnt_cpt_r == ce_i))
dbg_cpt_second_edge_taps[ce_i]
<= #TCQ second_edge_taps_r;
end
end
end
endgenerate
assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r ;//|| regl_rank_done_r;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
assign pi_stg2_rdlvl_cnt = (cal1_state_r == CAL1_REGL_LOAD) ? regl_dqs_cnt : cal1_cnt_cpt_r;
//***************************************************************************
// Data mux to route appropriate bit to calibration logic - i.e. calibration
// is done sequentially, one bit (or DQS group) at a time
//***************************************************************************
// generate
// if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
// assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
// assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
// assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
// assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
// assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
// assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
// assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
// assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
// end else begin: rd_data_div2_logic_clk
// assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
// assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
// assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
// assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
// assign rd_data_rise2 = 'b0;
// assign rd_data_fall2 = 'b0;
// assign rd_data_rise3 = 'b0;
// assign rd_data_fall3 = 'b0;
//
//
// end
// endgenerate
generate
if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
always @ (posedge clk) begin
rd_data_rise0 <= #TCQ rd_data[DQ_WIDTH-1:0];
rd_data_fall0 <= #TCQ rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
rd_data_rise1 <= #TCQ rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
rd_data_fall1 <= #TCQ rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
rd_data_rise2 <= #TCQ rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
rd_data_fall2 <= #TCQ rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
rd_data_rise3 <= #TCQ rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
rd_data_fall3 <= #TCQ rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end
end else begin: rd_datadiv2_logic_clk
always @ (posedge clk) begin
rd_data_rise0 <= #TCQ rd_data[DQ_WIDTH-1:0];
rd_data_fall0 <= #TCQ rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
rd_data_rise1 <= #TCQ rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
rd_data_fall1 <= #TCQ rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
rd_data_rise2 <= #TCQ 'b0;
rd_data_fall2 <= #TCQ 'b0;
rd_data_rise3 <= #TCQ 'b0;
rd_data_fall3 <= #TCQ 'b0;
end
end
endgenerate
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
assign rd_mux_sel_r_p2 = cal1_cnt_cpt_r << DRAM_WIDTH_P2;
always @(posedge clk) begin
rd_mux_sel_r_mult_r <= #TCQ rd_mux_sel_r_p2 + cal1_cnt_cpt_r;
rd_mux_sel_r_mult_f <= #TCQ rd_mux_sel_r_p2 + cal1_cnt_cpt_r;
end
generate
genvar mux_i;
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[rd_mux_sel_r_mult_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[rd_mux_sel_r_mult_f + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[rd_mux_sel_r_mult_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[rd_mux_sel_r_mult_f + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[rd_mux_sel_r_mult_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[rd_mux_sel_r_mult_f + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[rd_mux_sel_r_mult_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[rd_mux_sel_r_mult_f + mux_i];
end
end
endgenerate
//***************************************************************************
// Demultiplexor to control Phaser_IN delay values
//***************************************************************************
// Read DQS
always @(posedge clk) begin
if (rst) begin
pi_en_stg2_f <= #TCQ 'b0;
pi_stg2_f_incdec <= #TCQ 'b0;
end else if (cal1_dlyce_cpt_r && ~rise_detect_done) begin
if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
// Change only specified DQS
pi_en_stg2_f <= #TCQ 1'b1;
pi_stg2_f_incdec <= #TCQ cal1_dlyinc_cpt_r;
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
// if simulating, and "shortcuts" for calibration enabled, apply
// results to all DQSs (i.e. assume same delay on all
// DQSs).
pi_en_stg2_f <= #TCQ 1'b1;
pi_stg2_f_incdec <= #TCQ cal1_dlyinc_cpt_r;
end
end else begin
pi_en_stg2_f <= #TCQ 'b0;
pi_stg2_f_incdec <= #TCQ 'b0;
end
end // always @ (posedge clk)
// Read DQS
always @(posedge clk) begin
if (rst) begin
po_en_stg2_f <= #TCQ 'b0;
po_stg2_f_incdec <= #TCQ 'b0;
end else if (cal1_dlyce_cpt_r && rise_detect_done ) begin
if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
// Change only specified DQS
po_en_stg2_f <= #TCQ 1'b1;
po_stg2_f_incdec <= #TCQ cal1_dlyinc_cpt_r;
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
// if simulating, and "shortcuts" for calibration enabled, apply
// results to all DQSs (i.e. assume same delay on all
// DQSs).
po_en_stg2_f <= #TCQ 1'b1;
po_stg2_f_incdec <= #TCQ cal1_dlyinc_cpt_r;
end
end else begin
po_en_stg2_f <= #TCQ 'b0;
po_stg2_f_incdec <= #TCQ 'b0;
end
//end else if (DEBUG_PORT == "ON") begin
// // simultaneously inc/dec all DQSs
// if (dbg_idel_up_all || dbg_idel_down_all || dbg_sel_all_idel_cpt) begin
// pi_en_stg2_f <= #TCQ {DQS_WIDTH{dbg_idel_up_all | dbg_idel_down_all |
// dbg_idel_up_cpt | dbg_idel_down_cpt}};
// pi_stg2_f_incdec <= #TCQ dbg_idel_up_all | dbg_idel_up_cpt;
// end else begin
// // select specific DQS for adjustment
// pi_en_stg2_f[dbg_sel_idel_cpt] <= #TCQ dbg_idel_up_cpt |
// dbg_idel_down_cpt;
// pi_stg2_f_incdec[dbg_sel_idel_cpt] <= #TCQ dbg_idel_up_cpt;
// end
//end
end
// Read Q idelay tap
always @(posedge clk) begin
if (rst) begin
idelay_ce <= #TCQ 'b0;
idelay_inc <= #TCQ 'b0;
end else if (cal1_dlyce_q_r) begin
if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
// Change only specified DQS
idelay_ce <= #TCQ 1'b1;
idelay_inc <= #TCQ cal1_dlyinc_q_r;
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
// if simulating, and "shortcuts" for calibration enabled, apply
// results to all DQSs (i.e. assume same delay on all
// DQSs).
idelay_ce <= #TCQ cal1_dlyce_q_r;
idelay_inc <= #TCQ cal1_dlyinc_q_r;
end
end else begin
idelay_ce <= #TCQ 'b0;
idelay_inc <= #TCQ 'b0;
end
end
// This counter used to implement settling time between
// Phaser_IN rank register loads to different DQSs
always @(posedge clk) begin
if (rst)
done_cnt <= #TCQ 'b0;
else if ( ((cal1_state_r == CAL1_REGL_LOAD) && (cal1_state_r1 == CAL1_IDLE) && (SIM_CAL_OPTION == "SKIP_CAL")) ||
((cal1_state_r == CAL1_REGL_LOAD) && (cal1_state_r1 == CAL1_NEXT_DQS) && (SIM_CAL_OPTION != "SKIP_CAL")) ||
((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE)) )
done_cnt <= #TCQ 4'b1010;
else if (done_cnt > 'b0)
done_cnt <= #TCQ done_cnt - 1;
end
// During rank register loading the rank count must be sent to
// Phaser_IN via the phy_ctl_wd?? If so phy_init will have to
// issue NOPs during rank register loading with the appropriate
// rank count
always @(posedge clk) begin
if (rst || (regl_rank_done_r == 1'b1))
regl_rank_done_r <= #TCQ 1'b0;
else if ((regl_dqs_cnt == DQS_WIDTH-1) &&
(regl_rank_cnt != RANKS-1) &&
(done_cnt == 4'd1))
regl_rank_done_r <= #TCQ 1'b1;
end
// Temp wire for timing.
// The following in the always block below causes timing issues
// due to DSP block inference
// 6*regl_dqs_cnt.
// replacing this with two left shifts + 1 left shift to avoid
// DSP multiplier.
assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt};
// Load Phaser_OUT rank register with rdlvl delay value
// for each DQS per rank.
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0)) begin
pi_stg2_load <= #TCQ 'b0;
pi_stg2_reg_l <= #TCQ 'b0;
end else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
pi_stg2_load <= #TCQ 'b1;
pi_stg2_reg_l <= #TCQ
pi_rdlvl_dqs_tap_cnt_r[(((regl_dqs_cnt_timing<<2) + (regl_dqs_cnt_timing<<1))
+(rnk_cnt_r*DQS_WIDTH*6))+:6];
end else begin
pi_stg2_load <= #TCQ 'b0;
pi_stg2_reg_l <= #TCQ 'b0;
end
end
// Load Phaser_OUT rank register with rdlvl delay value
// for each DQS per rank.
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0)) begin
po_stg2_load <= #TCQ 'b0;
po_stg2_reg_l <= #TCQ 'b0;
end else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
po_stg2_load <= #TCQ 'b1;
po_stg2_reg_l <= #TCQ //6'h1B;
po_rdlvl_dqs_tap_cnt_r[(((regl_dqs_cnt_timing<<2) + (regl_dqs_cnt_timing<<1))
+(rnk_cnt_r*DQS_WIDTH*6))+:6];
//3;
end else begin
po_stg2_load <= #TCQ 'b0;
po_stg2_reg_l <= #TCQ 'b0;
end
end
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0))
regl_rank_cnt <= #TCQ 2'b00;
else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
if (regl_rank_cnt == RANKS-1)
regl_rank_cnt <= #TCQ regl_rank_cnt;
else
regl_rank_cnt <= #TCQ regl_rank_cnt + 1;
end
end
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0))
regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
if (regl_rank_cnt == RANKS-1)
regl_dqs_cnt <= #TCQ regl_dqs_cnt;
else
regl_dqs_cnt <= #TCQ 'b0;
end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1)
&& (done_cnt == 4'd1))
regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1;
else
regl_dqs_cnt <= #TCQ regl_dqs_cnt;
end
//*****************************************************************
// DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC:
// The actual IDELAY elements for each of the DQ bits is set via the
// DLYVAL parallel load port. However, the stage 1 calibration
// algorithm (well most of it) only needs to increment or decrement the DQ
// IDELAY value by 1 at any one time.
//*****************************************************************
// Chip-select generation for each of the individual counters tracking
// IDELAY tap values for each DQ
generate
for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq
always @(posedge clk)
if (rst)
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
else
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skipping calibration altogether (only for simulation), no
// need to set DQ IODELAY values - they are hardcoded
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
else if (SIM_CAL_OPTION == "FAST_CAL")
// If fast calibration option (simulation only) selected, DQ
// IODELAYs across all bytes are updated simultaneously
// (although per-bit deskew within DQS[0] is still supported)
//dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ cal1_dlyce_dq_r;
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ {DRAM_WIDTH{idelay_ce}}; //idelay_ce; {BW_WIDTH{PATTERN_A}}
else if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
if (cal1_cnt_cpt_r == z)
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH]
<= #TCQ {DRAM_WIDTH{idelay_ce}}; //idelay_ce; //cal1_dlyce_dq_r;
else
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
end
end
endgenerate
// Also delay increment/decrement control to match delay on DLYCE
always @(posedge clk)
if (rst)
dlyinc_dq_r <= #TCQ 1'b0;
else
dlyinc_dq_r <= #TCQ idelay_inc; //cal1_dlyinc_dq_r;
// // Each DQ has a counter associated with it to record current read-leveling
// // delay value
// always @(posedge clk)
// // Reset or skipping calibration all together
// if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin
// dlyval_dq_reg_r <= #TCQ 'b0;
// end else if (SIM_CAL_OPTION == "FAST_CAL") begin
// for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk
// for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg
// if (dlyce_dq_r[r]) begin
// if (dlyinc_dq_r)
// dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5]
// <= #TCQ dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5] + 1;
// else
// dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5]
// <= #TCQ dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5] - 1;
// end
// end
// end
// end else begin
// if (dlyce_dq_r[cal1_cnt_cpt_r]) begin
// if (dlyinc_dq_r)
// dlyval_dq_reg_r[((5*cal1_cnt_cpt_r)+(rnk_cnt_r*5*DQ_WIDTH))+:5]
// <= #TCQ
// dlyval_dq_reg_r[((5*cal1_cnt_cpt_r)+(rnk_cnt_r*5*DQ_WIDTH))+:5] + 1;
// else
// dlyval_dq_reg_r[((5*cal1_cnt_cpt_r)+(rnk_cnt_r*5*DQ_WIDTH))+:5]
// <= #TCQ
// dlyval_dq_reg_r[((5*cal1_cnt_cpt_r)+(rnk_cnt_r*5*DQ_WIDTH))+:5] - 1;
// end
// end
// Each DQ has a counter associated with it to record current read-leveling
// delay value
always @(posedge clk)
// Reset or skipping calibration all together
if (rst) begin
dlyval_dq_reg_r <= #TCQ 'b0;
end else if (SIM_CAL_OPTION == "SKIP_CAL") begin
dlyval_dq_reg_r <= #TCQ {5*RANKS*DQ_WIDTH{SKIP_DLY_VAL_DQ}};
end else begin
for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk
for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg
if (dlyce_dq_r[r]) begin
if (dlyinc_dq_r)
dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5]
<= #TCQ dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5] + 1;
else
dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5]
<= #TCQ dlyval_dq_reg_r[((5*r)+(n*DQ_WIDTH*5))+:5] - 1;
end
end
end
end
// Register for timing (help with logic placement)
always @(posedge clk) begin
dlyval_dq <= #TCQ dlyval_dq_reg_r;
end
//***************************************************************************
// Generate signal used to delay calibration state machine - used when:
// (1) IDELAY value changed
// (2) RD_MUX_SEL value changed
// Use when a delay is necessary to give the change time to propagate
// through the data pipeline (through IDELAY and ISERDES, and fabric
// pipeline stages)
//***************************************************************************
// List all the stage 1 calibration wait states here.
always @(posedge clk)
begin
case (cal1_state_r)
CAL1_NEW_DQS_WAIT,
CAL1_PB_STORE_FIRST_WAIT,
CAL1_PB_INC_CPT_WAIT,
CAL1_PB_DEC_CPT_LEFT_WAIT,
CAL1_PB_INC_DQ_WAIT,
CAL1_PB_DEC_CPT_WAIT,
CAL1_IDEL_INC_CPT_WAIT,
CAL1_IDEL_INC_Q_WAIT,
CAL1_IDEL_DEC_Q_WAIT,
CAL1_IDEL_DEC_Q_ALL_WAIT,
CAL1_CALC_IDEL_WAIT,
CAL1_STORE_FIRST_WAIT,
CAL1_FALL_IDEL_INC_Q_WAIT,
CAL1_FALL_IDEL_RESTORE_Q_WAIT,
CAL1_FALL_INC_CPT_WAIT,
CAL1_FALL_FINAL_DEC_TAP_WAIT: begin
cal1_wait_cnt_en_r <= #TCQ 1'b1;
end
default: begin
cal1_wait_cnt_en_r <= #TCQ 1'b0;
end
endcase
end
always @(posedge clk)
if (!cal1_wait_cnt_en_r) begin
cal1_wait_cnt_r <= #TCQ 5'b00000;
cal1_wait_r <= #TCQ 1'b1;
end else begin
if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin
cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1;
cal1_wait_r <= #TCQ 1'b1;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
cal1_wait_cnt_r <= #TCQ 5'b00000;
cal1_wait_r <= #TCQ 1'b0;
end
end
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
rdlvl_prech_req <= #TCQ 1'b0;
else
rdlvl_prech_req <= #TCQ cal1_prech_req_r;
//***************************************************************************
// Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of
// data from ISERDES. The value of this register is also stored, so that
// previous and current values of the ISERDES data can be compared while
// varying the IODELAY taps to see if an "edge" of the data valid window
// has been encountered since the last IODELAY tap adjustment
//***************************************************************************
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall1_r[rd_i]};
sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise2_r[rd_i]};
sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall2_r[rd_i]};
sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise3_r[rd_i]};
sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall3_r[rd_i]};
end
end
endgenerate
/*generate //NOT USED, remove
genvar rd0_i;
for (rd0_i = 0; rd0_i < DRAM_WIDTH; rd0_i = rd0_i + 1) begin: gen_sr0
always @(posedge clk) begin
sr0_rise0_r[rd0_i] <= #TCQ mux_rd_rise0_r[rd0_i];
sr0_fall0_r[rd0_i] <= #TCQ mux_rd_fall0_r[rd0_i];
sr0_rise1_r[rd0_i] <= #TCQ mux_rd_rise1_r[rd0_i];
sr0_fall1_r[rd0_i] <= #TCQ mux_rd_fall1_r[rd0_i];
sr0_rise2_r[rd0_i] <= #TCQ mux_rd_rise2_r[rd0_i];
sr0_fall2_r[rd0_i] <= #TCQ mux_rd_fall2_r[rd0_i];
sr0_rise3_r[rd0_i] <= #TCQ mux_rd_rise3_r[rd0_i];
sr0_fall3_r[rd0_i] <= #TCQ mux_rd_fall3_r[rd0_i];
end
end
endgenerate
generate
genvar rd1_i;
for (rd1_i = 0; rd1_i < DRAM_WIDTH; rd1_i = rd1_i + 1) begin: gen_sr1
always @(posedge clk) begin
sr1_rise0_r[rd1_i] <= #TCQ sr0_rise0_r[rd1_i];
sr1_fall0_r[rd1_i] <= #TCQ sr0_fall0_r[rd1_i];
sr1_rise1_r[rd1_i] <= #TCQ sr0_rise1_r[rd1_i];
sr1_fall1_r[rd1_i] <= #TCQ sr0_fall1_r[rd1_i];
sr1_rise2_r[rd1_i] <= #TCQ sr0_rise2_r[rd1_i];
sr1_fall2_r[rd1_i] <= #TCQ sr0_fall2_r[rd1_i];
sr1_rise3_r[rd1_i] <= #TCQ sr0_rise3_r[rd1_i];
sr1_fall3_r[rd1_i] <= #TCQ sr0_fall3_r[rd1_i];
end
end
endgenerate*/
// assign rd_window = { sr0_rise0_r, sr0_rise1_r, sr1_rise0_r, sr1_rise1_r};
// assign fd_window = { sr0_fall0_r, sr0_fall1_r, sr1_fall0_r, sr1_fall1_r};
//*****************************************************************
// Expected data pattern when properly aligned through bitslip
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Examining only the LSb of each DQS group, pattern is =
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
// expected data pattern : bit 3:0 for 2 clkdiv cycles is
//R0 - 0000 (OR) R0 - 0000
//F0 - 1111 F0 - 1111
//R1 - 0000 R1 - 0000
//F1 - 1111 F1 - 1111
//R0 - 1111 R0 - 0000
//F0 - 0000 F0 - 1111
//R1 - 0000 R1 - 1111
//F1 - 1111 F1 - 0000
generate
if (nCK_PER_CLK == 2) begin : gen_pat_div2
assign pat0_rise0[3] = 2'b00;
assign pat0_fall0[3] = 2'b11;
assign pat0_rise1[3] = 2'b10;
assign pat0_fall1[3] = 2'b01;
assign pat0_rise0[2] = 2'b00;
assign pat0_fall0[2] = 2'b11;
assign pat0_rise1[2] = 2'b10;
assign pat0_fall1[2] = 2'b01;
assign pat0_rise0[1] = 2'b00;
assign pat0_fall0[1] = 2'b11;
assign pat0_rise1[1] = 2'b10;
assign pat0_fall1[1] = 2'b01;
assign pat0_rise0[0] = 2'b00;
assign pat0_fall0[0] = 2'b11;
assign pat0_rise1[0] = 2'b10;
assign pat0_fall1[0] = 2'b01;
assign pat1_rise0[3] = 2'b10;
assign pat1_fall0[3] = 2'b01;
assign pat1_rise1[3] = 2'b00;
assign pat1_fall1[3] = 2'b11;
assign pat1_rise0[2] = 2'b10;
assign pat1_fall0[2] = 2'b01;
assign pat1_rise1[2] = 2'b00;
assign pat1_fall1[2] = 2'b11;
assign pat1_rise0[1] = 2'b10;
assign pat1_fall0[1] = 2'b01;
assign pat1_rise1[1] = 2'b00;
assign pat1_fall1[1] = 2'b11;
assign pat1_rise0[0] = 2'b10;
assign pat1_fall0[0] = 2'b01;
assign pat1_rise1[0] = 2'b00;
assign pat1_fall1[0] = 2'b11;
end else begin : gen_pat_div4
//Due to later doing bitslip our pattern can be only of 4 possabilities.
//Just make sure we are properly set for rise/fall and using the correct edge.
assign pat0_rise0[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b00 : 2'b00;//2'b11;
assign pat0_fall0[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b11 : 2'b11;//2'b00;
assign pat0_rise1[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b00 : 2'b00;//2'b11;
assign pat0_fall1[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b11 : 2'b11;//2'b00;
assign pat0_rise2[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b00 : 2'b00;
assign pat0_fall2[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b11 : 2'b11;
assign pat0_rise3[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b00 : 2'b11;
assign pat0_fall3[3] = (RTR_CALIBRATION == "ON" && !rtr_cal_done) ? 2'b11 : 2'b00;
assign pat0_rise0[2] = pat0_rise0[3];
assign pat0_fall0[2] = pat0_fall0[3];
assign pat0_rise1[2] = pat0_rise1[3];
assign pat0_fall1[2] = pat0_fall1[3];
assign pat0_rise2[2] = pat0_rise2[3];
assign pat0_fall2[2] = pat0_fall2[3];
assign pat0_rise3[2] = pat0_rise3[3];
assign pat0_fall3[2] = pat0_fall3[3];
assign pat0_rise0[1] = pat0_rise0[3];
assign pat0_fall0[1] = pat0_fall0[3];
assign pat0_rise1[1] = pat0_rise1[3];
assign pat0_fall1[1] = pat0_fall1[3];
assign pat0_rise2[1] = pat0_rise2[3];
assign pat0_fall2[1] = pat0_fall2[3];
assign pat0_rise3[1] = pat0_rise3[3];
assign pat0_fall3[1] = pat0_fall3[3];
assign pat0_rise0[0] = pat0_rise0[3];
assign pat0_fall0[0] = pat0_fall0[3];
assign pat0_rise1[0] = pat0_rise1[3];
assign pat0_fall1[0] = pat0_fall1[3];
assign pat0_rise2[0] = pat0_rise2[3];
assign pat0_fall2[0] = pat0_fall2[3];
assign pat0_rise3[0] = pat0_rise3[3];
assign pat0_fall3[0] = pat0_fall3[3];
assign pat1_rise0[3] = 2'b11;//2'b11;
assign pat1_fall0[3] = 2'b00;//2'b00;
assign pat1_rise1[3] = 2'b00;//2'b11;
assign pat1_fall1[3] = 2'b11;//2'b00;
assign pat1_rise2[3] = 2'b00;//2'b11;
assign pat1_fall2[3] = 2'b11;//2'b00;
assign pat1_rise3[3] = 2'b00;//2'b00;
assign pat1_fall3[3] = 2'b11;//2'b11;
assign pat1_rise0[2] = pat1_rise0[3];
assign pat1_fall0[2] = pat1_fall0[3];
assign pat1_rise1[2] = pat1_rise1[3];
assign pat1_fall1[2] = pat1_fall1[3];
assign pat1_rise2[2] = pat1_rise2[3];
assign pat1_fall2[2] = pat1_fall2[3];
assign pat1_rise3[2] = pat1_rise3[3];
assign pat1_fall3[2] = pat1_fall3[3];
assign pat1_rise0[1] = pat1_rise0[3];
assign pat1_fall0[1] = pat1_fall0[3];
assign pat1_rise1[1] = pat1_rise1[3];
assign pat1_fall1[1] = pat1_fall1[3];
assign pat1_rise2[1] = pat1_rise2[3];
assign pat1_fall2[1] = pat1_fall2[3];
assign pat1_rise3[1] = pat1_rise3[3];
assign pat1_fall3[1] = pat1_fall3[3];
assign pat1_rise0[0] = pat1_rise0[3];
assign pat1_fall0[0] = pat1_fall0[3];
assign pat1_rise1[0] = pat1_rise1[3];
assign pat1_fall1[0] = pat1_fall1[3];
assign pat1_rise2[0] = pat1_rise2[3];
assign pat1_fall2[0] = pat1_fall2[3];
assign pat1_rise3[0] = pat1_rise3[3];
assign pat1_fall3[0] = pat1_fall3[3];
assign pat2_rise0[3] = 2'b00;//2'b00;
assign pat2_fall0[3] = 2'b11;//2'b11;
assign pat2_rise1[3] = 2'b11;//2'b11;
assign pat2_fall1[3] = 2'b00;//2'b00;
assign pat2_rise2[3] = 2'b00;//2'b11;
assign pat2_fall2[3] = 2'b11;//2'b00;
assign pat2_rise3[3] = 2'b00;//2'b11;
assign pat2_fall3[3] = 2'b11;//2'b00;
assign pat2_rise0[2] = pat2_rise0[3];
assign pat2_fall0[2] = pat2_fall0[3];
assign pat2_rise1[2] = pat2_rise1[3];
assign pat2_fall1[2] = pat2_fall1[3];
assign pat2_rise2[2] = pat2_rise2[3];
assign pat2_fall2[2] = pat2_fall2[3];
assign pat2_rise3[2] = pat2_rise3[3];
assign pat2_fall3[2] = pat2_fall3[3];
assign pat2_rise0[1] = pat2_rise0[3];
assign pat2_fall0[1] = pat2_fall0[3];
assign pat2_rise1[1] = pat2_rise1[3];
assign pat2_fall1[1] = pat2_fall1[3];
assign pat2_rise2[1] = pat2_rise2[3];
assign pat2_fall2[1] = pat2_fall2[3];
assign pat2_rise3[1] = pat2_rise3[3];
assign pat2_fall3[1] = pat2_fall3[3];
assign pat2_rise0[0] = pat2_rise0[3];
assign pat2_fall0[0] = pat2_fall0[3];
assign pat2_rise1[0] = pat2_rise1[3];
assign pat2_fall1[0] = pat2_fall1[3];
assign pat2_rise2[0] = pat2_rise2[3];
assign pat2_fall2[0] = pat2_fall2[3];
assign pat2_rise3[0] = pat2_rise3[3];
assign pat2_fall3[0] = pat2_fall3[3];
assign pat3_rise0[3] = 2'b00;//2'b11;
assign pat3_fall0[3] = 2'b11;//2'b00;
assign pat3_rise1[3] = 2'b00;//2'b00;
assign pat3_fall1[3] = 2'b11;//2'b11;
assign pat3_rise2[3] = 2'b11;//2'b11;
assign pat3_fall2[3] = 2'b00;//2'b00;
assign pat3_rise3[3] = 2'b00;//2'b11;
assign pat3_fall3[3] = 2'b11;//2'b00;
assign pat3_rise0[2] = pat3_rise0[3];
assign pat3_fall0[2] = pat3_fall0[3];
assign pat3_rise1[2] = pat3_rise1[3];
assign pat3_fall1[2] = pat3_fall1[3];
assign pat3_rise2[2] = pat3_rise2[3];
assign pat3_fall2[2] = pat3_fall2[3];
assign pat3_rise3[2] = pat3_rise3[3];
assign pat3_fall3[2] = pat3_fall3[3];
assign pat3_rise0[1] = pat3_rise0[3];
assign pat3_fall0[1] = pat3_fall0[3];
assign pat3_rise1[1] = pat3_rise1[3];
assign pat3_fall1[1] = pat3_fall1[3];
assign pat3_rise2[1] = pat3_rise2[3];
assign pat3_fall2[1] = pat3_fall2[3];
assign pat3_rise3[1] = pat3_rise3[3];
assign pat3_fall3[1] = pat3_fall3[3];
assign pat3_rise0[0] = pat3_rise0[3];
assign pat3_fall0[0] = pat3_fall0[3];
assign pat3_rise1[0] = pat3_rise1[3];
assign pat3_fall1[0] = pat3_fall1[3];
assign pat3_rise2[0] = pat3_rise2[3];
assign pat3_fall2[0] = pat3_fall2[3];
assign pat3_rise3[0] = pat3_rise3[3];
assign pat3_fall3[0] = pat3_fall3[3];
end
endgenerate
generate
genvar pt_i;
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
//Pattern 0 ------------------------------------------------------------
if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])
pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])
pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if ((sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) ||
(nCK_PER_CLK == 2 && sr_rise1_r[pt_i] == pat0_fall1[pt_i%4]) )
pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if ((sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) ||
(nCK_PER_CLK == 2 && sr_fall1_r[pt_i] == pat0_rise1[pt_i%4]))
pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
//The following only used for nCK_PER_CLK == 4
if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4])
pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4])
pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4])
pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4])
pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;
//Pattern 1 ------------------------------------------------------------
if ((sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) ||
(nCK_PER_CLK == 2 && sr_rise0_r[pt_i] == pat1_fall0[pt_i%4]) )
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if ((sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) ||
(nCK_PER_CLK == 2 && sr_fall0_r[pt_i] == pat1_rise0[pt_i%4]))
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
//The following only used for nCK_PER_CLK == 4
if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4])
pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4])
pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4])
pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4])
pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;
//Pattern 2 ------------------------------------------------------------
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
//The following only used for nCK_PER_CLK == 4
if (sr_rise2_r[pt_i] == pat2_rise2[pt_i%4])
pat2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat2_fall2[pt_i%4])
pat2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat2_rise3[pt_i%4])
pat2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat2_fall3[pt_i%4])
pat2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall3_r[pt_i] <= #TCQ 1'b0;
//Pattern 3 ------------------------------------------------------------
if (sr_rise0_r[pt_i] == pat3_rise0[pt_i%4])
pat3_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat3_fall0[pt_i%4])
pat3_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat3_rise1[pt_i%4])
pat3_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat3_fall1[pt_i%4])
pat3_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_fall1_r[pt_i] <= #TCQ 1'b0;
//The following only used for nCK_PER_CLK == 4
if (sr_rise2_r[pt_i] == pat3_rise2[pt_i%4])
pat3_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat3_fall2[pt_i%4])
pat3_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat3_rise3[pt_i%4])
pat3_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat3_fall3[pt_i%4])
pat3_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat3_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
endgenerate
//Pattern 0 ------------------------------------------------------------
always @(posedge clk) begin
pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;
pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;
pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;
pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;
pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r;
pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r;
pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r;
pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r;
if (nCK_PER_CLK == 2) begin
pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_fall0_and_r &&
pat0_match_rise1_and_r &&
pat0_match_fall1_and_r);
pat0_data_rise_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_rise1_and_r);
pat0_data_fall_match_r <= #TCQ (pat0_match_fall0_and_r &&
pat0_match_fall1_and_r);
end else begin
pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_fall0_and_r &&
pat0_match_rise1_and_r &&
pat0_match_fall1_and_r &&
pat0_match_rise2_and_r &&
pat0_match_fall2_and_r &&
pat0_match_rise3_and_r &&
pat0_match_fall3_and_r);
pat0_data_rise_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_rise1_and_r &&
pat0_match_rise2_and_r &&
pat0_match_rise3_and_r);
pat0_data_fall_match_r <= #TCQ (pat0_match_fall0_and_r &&
pat0_match_fall1_and_r &&
pat0_match_fall2_and_r &&
pat0_match_fall3_and_r);
end
end
//Pattern 1 ------------------------------------------------------------
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r;
pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r;
pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r;
pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r;
if (nCK_PER_CLK == 2) begin
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_rise_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_rise1_and_r);
pat1_data_fall_match_r <= #TCQ (pat1_match_fall0_and_r &&
pat1_match_fall1_and_r);
end else begin
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r &&
pat1_match_rise2_and_r &&
pat1_match_fall2_and_r &&
pat1_match_rise3_and_r &&
pat1_match_fall3_and_r);
pat1_data_rise_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_rise2_and_r &&
pat1_match_rise3_and_r);
pat1_data_fall_match_r <= #TCQ (pat1_match_fall0_and_r &&
pat1_match_fall1_and_r &&
pat1_match_fall2_and_r &&
pat1_match_fall3_and_r);
end
end
//Pattern 2 ------------------------------------------------------------
always @(posedge clk) begin
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r;
pat2_match_rise2_and_r <= #TCQ &pat2_match_rise2_r;
pat2_match_fall2_and_r <= #TCQ &pat2_match_fall2_r;
pat2_match_rise3_and_r <= #TCQ &pat2_match_rise3_r;
pat2_match_fall3_and_r <= #TCQ &pat2_match_fall3_r;
if (nCK_PER_CLK == 2) begin
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
pat2_data_rise_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_rise1_and_r);
pat2_data_fall_match_r <= #TCQ (pat2_match_fall0_and_r &&
pat2_match_fall1_and_r);
end else begin
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r &&
pat2_match_rise2_and_r &&
pat2_match_fall2_and_r &&
pat2_match_rise3_and_r &&
pat2_match_fall3_and_r);
pat2_data_rise_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_rise2_and_r &&
pat2_match_rise3_and_r);
pat2_data_fall_match_r <= #TCQ (pat2_match_fall0_and_r &&
pat2_match_fall1_and_r &&
pat2_match_fall2_and_r &&
pat2_match_fall3_and_r);
end
end
//Pattern 3 ------------------------------------------------------------
always @(posedge clk) begin
pat3_match_rise0_and_r <= #TCQ &pat3_match_rise0_r;
pat3_match_fall0_and_r <= #TCQ &pat3_match_fall0_r;
pat3_match_rise1_and_r <= #TCQ &pat3_match_rise1_r;
pat3_match_fall1_and_r <= #TCQ &pat3_match_fall1_r;
pat3_match_rise2_and_r <= #TCQ &pat3_match_rise2_r;
pat3_match_fall2_and_r <= #TCQ &pat3_match_fall2_r;
pat3_match_rise3_and_r <= #TCQ &pat3_match_rise3_r;
pat3_match_fall3_and_r <= #TCQ &pat3_match_fall3_r;
if (nCK_PER_CLK == 2) begin
pat3_data_match_r <= #TCQ (pat3_match_rise0_and_r &&
pat3_match_fall0_and_r &&
pat3_match_rise1_and_r &&
pat3_match_fall1_and_r);
pat3_data_rise_match_r <= #TCQ (pat3_match_rise0_and_r &&
pat3_match_rise1_and_r);
pat3_data_fall_match_r <= #TCQ (pat3_match_fall0_and_r &&
pat3_match_fall1_and_r);
end else begin
pat3_data_match_r <= #TCQ (pat3_match_rise0_and_r &&
pat3_match_fall0_and_r &&
pat3_match_rise1_and_r &&
pat3_match_fall1_and_r &&
pat3_match_rise2_and_r &&
pat3_match_fall2_and_r &&
pat3_match_rise3_and_r &&
pat3_match_fall3_and_r);
pat3_data_rise_match_r <= #TCQ (pat3_match_rise0_and_r &&
pat3_match_rise1_and_r &&
pat3_match_rise2_and_r &&
pat3_match_rise3_and_r);
pat3_data_fall_match_r <= #TCQ (pat3_match_fall0_and_r &&
pat3_match_fall1_and_r &&
pat3_match_fall2_and_r &&
pat3_match_fall3_and_r);
end
end
//Following used to check both rise/fall together
assign pat_match = (nCK_PER_CLK == 2) ?
(pat0_data_match_r || pat1_data_match_r) :
(pat0_data_match_r || pat1_data_match_r ||
pat2_data_match_r || pat3_data_match_r);
//seperate out rise/fall for seperate checking (QDR2+)
assign rise_match = (nCK_PER_CLK == 2) ?
(pat0_data_rise_match_r || pat1_data_rise_match_r) :
(pat0_data_rise_match_r || pat1_data_rise_match_r ||
pat2_data_rise_match_r || pat3_data_rise_match_r);
assign fall_match = (nCK_PER_CLK == 2) ?
(pat0_data_fall_match_r || pat1_data_fall_match_r) :
(pat0_data_fall_match_r || pat1_data_fall_match_r ||
pat2_data_fall_match_r || pat3_data_fall_match_r);
assign data_valid = (MEMORY_IO_DIR != "UNIDIR")? pat_match :
(~rise_detect_done)? rise_match:fall_match;
// generate
// genvar nd_i;
// for (nd_i = 0; nd_i < DRAM_WIDTH; nd_i = nd_i + 1) begin: gen_valid
//
// assign rd_window[nd_i] = { sr0_rise0_r[nd_i], sr0_rise1_r[nd_i], sr1_rise0_r[nd_i], sr1_rise1_r[nd_i]};
// assign fd_window[nd_i] = { sr0_fall0_r[nd_i], sr0_fall1_r[nd_i], sr1_fall0_r[nd_i], sr1_fall1_r[nd_i]};
//
// always @(posedge clk) begin
// if ((rd_window[nd_i] == 4'b0010) || (rd_window[nd_i] == 4'b1000) || (rd_window[nd_i] == 4'b0100) || (rd_window[nd_i] == 4'b0001)) begin
// rise_data_valid_r[nd_i] <= #TCQ 1'b1;
// end else begin
// rise_data_valid_r[nd_i] <= #TCQ 1'b0;
// end
//
// if ((fd_window[nd_i] == 4'b1101) || (fd_window[nd_i] == 4'b0111) || (fd_window[nd_i] == 4'b1110) || (fd_window[nd_i] == 4'b1011)) begin
// fall_data_valid_r[nd_i] <= #TCQ 1'b1;
// end else begin
// fall_data_valid_r[nd_i] <= #TCQ 1'b0;
// end
//
// end
// end
// endgenerate
//
// assign rise_data_valid = &rise_data_valid_r;
// assign fall_data_valid = &fall_data_valid_r;
//***************************************************************************
// First stage calibration: Capture clock
//***************************************************************************
//*****************************************************************
// Free-running counter to keep track of when to do parallel load of
// data from memory
//*****************************************************************
always @(posedge clk)
//if (rst) begin
if (rst || ~rdlvl_stg1_start) begin
cnt_shift_r <= #TCQ 'b0;
sr_valid_r <= #TCQ 1'b0;
end else begin
if (cnt_shift_r == RD_SHIFT_LEN-1) begin
sr_valid_r <= #TCQ 1'b1;
cnt_shift_r <= #TCQ 'b0;
end else begin
sr_valid_r <= #TCQ 1'b0;
cnt_shift_r <= #TCQ cnt_shift_r + 1;
end
end
//*****************************************************************
// Logic to determine when either edge of the data eye encountered
// Pre- and post-IDELAY update data pattern is compared, if they
// differ, than an edge has been encountered. Currently no attempt
// made to determine if the data pattern itself is "correct", only
// whether it changes after incrementing the IDELAY (possible
// future enhancement)
//*****************************************************************
// Simple handshaking - when CAL1 state machine wants the OLD SR
// value to get loaded, it requests for it to be loaded. On the
// next sr_valid_r pulse, it does get loaded, and store_sr_done_r
// is then pulsed asserted to indicate this, and we all go on our
// merry way
always @(posedge clk)
if (rst) begin
store_sr_done_r <= #TCQ 1'b0;
store_sr_r <= #TCQ 1'b0;
end else begin
store_sr_done_r <= sr_valid_r & store_sr_r;
if (store_sr_req_r)
store_sr_r <= #TCQ 1'b1;
else if (sr_valid_r && store_sr_r)
store_sr_r <= #TCQ 1'b0;
end
// Transfer current data to old data, prior to incrementing delay
// Also store data from current sampling window - so that we can detect
// if the current delay tap yields data that is "jittery"
generate
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr
always @(posedge clk) begin
if (sr_valid_r) begin
// Load last sample (i.e. from current sampling interval)
prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
end
if (sr_valid_r && store_sr_r) begin
old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
end
end
end
endgenerate
//*******************************************************
// Match determination occurs over 3 cycles - pipelined for better timing
//*******************************************************
// Match valid with # of cycles of pipelining in match determination
always @(posedge clk) begin
sr_valid_r1 <= #TCQ sr_valid_r;
sr_valid_r2 <= #TCQ sr_valid_r1;
end
generate
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match
always @(posedge clk) begin
// CYCLE1: Compare all bits in DQS grp, generate separate term for
// each bit over four bit times. For example, if there are 8-bits
// per DQS group, 32 terms are generated on cycle 1
// NOTE: Structure HDL such that X on data bus will result in a
// mismatch. This is required for memory models that can drive the
// bus with X's to model uncertainty regions (e.g. Denali)
if (data_valid && sr_rise0_r[z] == old_sr_rise0_r[z])
old_sr_match_rise0_r[z] <= #TCQ 1'b1;
else
old_sr_match_rise0_r[z] <= #TCQ 1'b0;
if (data_valid && sr_fall0_r[z] == old_sr_fall0_r[z])
old_sr_match_fall0_r[z] <= #TCQ 1'b1;
else
old_sr_match_fall0_r[z] <= #TCQ 1'b0;
if (data_valid && sr_rise1_r[z] == old_sr_rise1_r[z])
old_sr_match_rise1_r[z] <= #TCQ 1'b1;
else
old_sr_match_rise1_r[z] <= #TCQ 1'b0;
if (data_valid && sr_fall1_r[z] == old_sr_fall1_r[z])
old_sr_match_fall1_r[z] <= #TCQ 1'b1;
else
old_sr_match_fall1_r[z] <= #TCQ 1'b0;
if (sr_rise2_r[z] == old_sr_rise2_r[z])
old_sr_match_rise2_r[z] <= #TCQ 1'b1;
else
old_sr_match_rise2_r[z] <= #TCQ 1'b0;
if (sr_fall2_r[z] == old_sr_fall2_r[z])
old_sr_match_fall2_r[z] <= #TCQ 1'b1;
else
old_sr_match_fall2_r[z] <= #TCQ 1'b0;
if (sr_rise3_r[z] == old_sr_rise3_r[z])
old_sr_match_rise3_r[z] <= #TCQ 1'b1;
else
old_sr_match_rise3_r[z] <= #TCQ 1'b0;
if (sr_fall3_r[z] == old_sr_fall3_r[z])
old_sr_match_fall3_r[z] <= #TCQ 1'b1;
else
old_sr_match_fall3_r[z] <= #TCQ 1'b0;
if (data_valid && sr_rise0_r[z] == prev_sr_rise0_r[z])
prev_sr_match_rise0_r[z] <= #TCQ 1'b1;
else
prev_sr_match_rise0_r[z] <= #TCQ 1'b0;
if (data_valid && sr_fall0_r[z] == prev_sr_fall0_r[z])
prev_sr_match_fall0_r[z] <= #TCQ 1'b1;
else
prev_sr_match_fall0_r[z] <= #TCQ 1'b0;
if (data_valid && sr_rise1_r[z] == prev_sr_rise1_r[z])
prev_sr_match_rise1_r[z] <= #TCQ 1'b1;
else
prev_sr_match_rise1_r[z] <= #TCQ 1'b0;
if (data_valid && sr_fall1_r[z] == prev_sr_fall1_r[z])
prev_sr_match_fall1_r[z] <= #TCQ 1'b1;
else
prev_sr_match_fall1_r[z] <= #TCQ 1'b0;
if (sr_rise2_r[z] == prev_sr_rise2_r[z])
prev_sr_match_rise2_r[z] <= #TCQ 1'b1;
else
prev_sr_match_rise2_r[z] <= #TCQ 1'b0;
if (sr_fall2_r[z] == prev_sr_fall2_r[z])
prev_sr_match_fall2_r[z] <= #TCQ 1'b1;
else
prev_sr_match_fall2_r[z] <= #TCQ 1'b0;
if (sr_rise3_r[z] == prev_sr_rise3_r[z])
prev_sr_match_rise3_r[z] <= #TCQ 1'b1;
else
prev_sr_match_rise3_r[z] <= #TCQ 1'b0;
if (sr_fall3_r[z] == prev_sr_fall3_r[z])
prev_sr_match_fall3_r[z] <= #TCQ 1'b1;
else
prev_sr_match_fall3_r[z] <= #TCQ 1'b0;
// CYCLE2: Combine all the comparisons for every 8 words (rise0,
// fall0,rise1, fall1) in the calibration sequence. Now we're down
// to DRAM_WIDTH terms
if (nCK_PER_CLK == 2) begin
//Only check rise0/fall0
//Our pattern is such that we only need to check one of the outputs
old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] &
old_sr_match_fall0_r[z];
prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] &
prev_sr_match_fall0_r[z];
old_rise_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z];
old_fall_sr_match_cyc2_r[z] <= #TCQ old_sr_match_fall0_r[z];
prev_rise_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z];
prev_fall_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_fall0_r[z];// &
end else begin
old_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] &
old_sr_match_fall0_r[z] &
old_sr_match_rise1_r[z] &
old_sr_match_fall1_r[z] &
old_sr_match_rise2_r[z] &
old_sr_match_fall2_r[z] &
old_sr_match_rise3_r[z] &
old_sr_match_fall3_r[z];
prev_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] &
prev_sr_match_fall0_r[z] &
prev_sr_match_rise1_r[z] &
prev_sr_match_fall1_r[z] &
prev_sr_match_rise2_r[z] &
prev_sr_match_fall2_r[z] &
prev_sr_match_rise3_r[z] &
prev_sr_match_fall3_r[z];
old_rise_sr_match_cyc2_r[z] <= #TCQ old_sr_match_rise0_r[z] &
old_sr_match_rise1_r[z] &
old_sr_match_rise2_r[z] &
old_sr_match_rise3_r[z];
old_fall_sr_match_cyc2_r[z] <= #TCQ old_sr_match_fall0_r[z] &
old_sr_match_fall1_r[z] &
old_sr_match_fall2_r[z] &
old_sr_match_fall3_r[z];
prev_rise_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_rise0_r[z] &
prev_sr_match_rise1_r[z] &
prev_sr_match_rise2_r[z] &
prev_sr_match_rise3_r[z];
prev_fall_sr_match_cyc2_r[z] <= #TCQ prev_sr_match_fall0_r[z] &
prev_sr_match_fall1_r[z] &
prev_sr_match_fall2_r[z] &
prev_sr_match_fall3_r[z];
end
// CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),
// and qualify with pipelined valid signal) - probably don't need
// a cycle just do do this....
if (sr_valid_r2) begin
old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z];
prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];
old_rise_sr_diff_r[z] <= #TCQ ~old_rise_sr_match_cyc2_r[z];
prev_rise_sr_diff_r[z] <= #TCQ ~prev_rise_sr_match_cyc2_r[z];
old_fall_sr_diff_r[z] <= #TCQ ~old_fall_sr_match_cyc2_r[z];
prev_fall_sr_diff_r[z] <= #TCQ ~prev_fall_sr_match_cyc2_r[z];
end else begin
old_sr_diff_r[z] <= #TCQ 'b0;
prev_sr_diff_r[z] <= #TCQ 'b0;
old_rise_sr_diff_r[z] <= #TCQ 'b0;
prev_rise_sr_diff_r[z] <= #TCQ 'b0;
old_fall_sr_diff_r[z] <= #TCQ 'b0;
prev_fall_sr_diff_r[z] <= #TCQ 'b0;
end
end
end
endgenerate
//***************************************************************************
// First stage calibration: DQS Capture
//***************************************************************************
//*******************************************************
// Counters for tracking # of samples compared
// For each comparision point (i.e. to determine if an edge has
// occurred after each IODELAY increment when read leveling),
// multiple samples are compared in order to average out the effects
// of jitter. If any one of these samples is different than the "old"
// sample corresponding to the previous IODELAY value, then an edge
// is declared to be detected.
//*******************************************************
// Two cascaded counters are used to keep track of # of samples compared,
// in order to make it easier to meeting timing on these paths. Once
// optimal sampling interval is determined, it may be possible to remove
// the second counter
always @(posedge clk)
samp_edge_cnt0_en_r <= #TCQ
(cal1_state_r == CAL1_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE) ||
(cal1_state_r == CAL1_DETECT_EDGE_Q) || //added for Q delay
(cal1_state_r == CAL1_FALL_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);
// || (cal1_state_r == CAL1_LF_DETECT_EDGE);
// First counter counts the number of samples directly
// MIG 3.3: Change this to increment every clock cycle, rather than once
// every RD_SHIFT_LEN clock cycles, because of the changes to the
// comparison logic. In order to make this comparable to MIG 3.2, the
// counter width must be increased by 1-bit (for MIG 3.2, RD_SHIFT_LEN = 2)
always @(posedge clk)
if (rst)
samp_edge_cnt0_r <= #TCQ 'b0;
else
if (!samp_edge_cnt0_en_r)
samp_edge_cnt0_r <= #TCQ 'b0;
else
samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1;
always @(posedge clk)
if (rst)
samp_edge_cnt1_en_r <= #TCQ 1'b0;
else begin
if (((SIM_CAL_OPTION == "FAST_CAL") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) &&
(samp_edge_cnt0_r == 12'h003))
// Bypass multi-sampling for stage 1 when simulating with
// either fast calibration option, or with multi-sampling
// disabled
samp_edge_cnt1_en_r <= #TCQ 1'b1;
else if (samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0)
samp_edge_cnt1_en_r <= #TCQ 1'b1;
else
samp_edge_cnt1_en_r <= #TCQ 1'b0;
end
// Counter #2
always @(posedge clk)
if (rst)
samp_edge_cnt1_r <= #TCQ 'b0;
else
if (!samp_edge_cnt0_en_r)
samp_edge_cnt1_r <= #TCQ 'b0;
else if (samp_edge_cnt1_en_r)
samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1;
always @(posedge clk)
if (rst)
samp_cnt_done_r <= #TCQ 1'b0;
else begin
if (!samp_edge_cnt0_en_r)
samp_cnt_done_r <= #TCQ 'b0;
else if (((SIM_CAL_OPTION == "FAST_CAL") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) &&
(samp_edge_cnt1_r == 12'h003))
// Bypass multi-sampling for stage 1 when simulating with
// either fast calibration option, or with multi-sampling
// disabled
samp_cnt_done_r <= #TCQ 1'b1;
else if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1)
samp_cnt_done_r <= #TCQ 1'b1;
end
//*****************************************************************
// Logic to keep track of (on per-bit basis):
// 1. When a region of stability preceded by a known edge occurs
// 2. If for the current tap, the read data jitters
// 3. If an edge occured between the current and previous tap
// 4. When the current edge detection/sampling interval can end
// Essentially, these are a series of status bits - the stage 1
// calibration FSM monitors these to determine when an edge is
// found. Additional information is provided to help the FSM
// determine if a left or right edge has been found.
//****************************************************************
/* assign pb_detect_edge_setup
= (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) ||
(cal1_state_r == CAL1_IDEL_DEC_Q_WAIT) ||(cal1_state_r == CAL1_IDEL_DEC_Q_ALL_WAIT) ; // added for Q delay
assign pb_detect_edge
= (cal1_state_r == CAL1_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE_DQ) ||
(cal1_state_r == CAL1_DETECT_EDGE_Q); // added for Q delay
*/
assign pb_detect_edge_setup
= (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) ||
(cal1_state_r == CAL1_IDEL_DEC_Q_WAIT) ||(cal1_state_r == CAL1_IDEL_DEC_Q_ALL_WAIT)|| (cal1_state_r == CAL1_FALL_INC_CPT_WAIT) || (cal1_state_r == CAL1_IDEL_FALL_DEC_CPT) ||
(cal1_state_r == CAL1_FALL_DETECT_EDGE_WAIT) ; // added for Q delay
assign pb_detect_edge
= (cal1_state_r == CAL1_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE_DQ) ||
(cal1_state_r == CAL1_DETECT_EDGE_Q)|| // added for Q delay
(cal1_state_r == CAL1_FALL_DETECT_EDGE);
generate
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge
always @(posedge clk) begin
if (pb_detect_edge_setup) begin
// Reset eye size, stable eye marker, and jitter marker before
// starting new edge detection iteration
pb_cnt_eye_size_r[z] <= #TCQ 3'b111;
pb_detect_edge_done_r[z] <= #TCQ 1'b0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_last_tap_jitter_r[z] <= #TCQ 1'b0;
pb_found_edge_last_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b0;
pb_found_first_edge_r[z] <= #TCQ 1'b0;
end else if (pb_detect_edge) begin
// Save information on which DQ bits are already out of the
// data valid window - those DQ bits will later not have their
// IDELAY tap value incremented
pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z];
if (!pb_detect_edge_done_r[z]) begin
if (samp_cnt_done_r) begin
// If we've reached end of sampling interval, no jitter on
// current tap has been found (although an edge could have
// been found between the current and previous taps), and
// the sampling interval is complete. Increment the stable
// eye counter if no edge found, and always clear the jitter
// flag in preparation for the next tap.
pb_last_tap_jitter_r[z] <= #TCQ 1'b0;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin
// If the data was completely stable during this tap and
// no edge was found between this and the previous tap
// then increment the stable eye counter "as appropriate"
if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1)
pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1;
else if (pb_found_first_edge_r[z])
// We've reached minimum stable eye width
pb_found_stable_eye_r[z] <= #TCQ 1'b1;
end else begin
// Otherwise, an edge was found, either because of a
// difference between this and the previous tap's read
// data, and/or because the previous tap's data jittered
// (but not the current tap's data), then just set the
// edge found flag, and enable the stable eye counter
pb_cnt_eye_size_r[z] <= #TCQ 3'b000;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
end
end else if ((prev_sr_diff_r[z] && MEMORY_IO_DIR != "UNIDIR") ||
(prev_rise_sr_diff_r[z] && MEMORY_IO_DIR == "UNIDIR")) begin
// If we find that the current tap read data jitters, then
// set edge and jitter found flags, "enable" the eye size
// counter, and stop sampling interval for this bit
pb_cnt_eye_size_r[z] <= #TCQ 3'b000;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_last_tap_jitter_r[z] <= #TCQ 1'b1;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_found_first_edge_r[z] <= #TCQ 1'b1;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
end else if ( ((old_sr_diff_r[z] && MEMORY_IO_DIR != "UNIDIR") ||
(old_rise_sr_diff_r[z] && MEMORY_IO_DIR == "UNIDIR")) ||
pb_last_tap_jitter_r[z]) begin
// If either an edge was found (i.e. difference between
// current tap and previous tap read data), or the previous
// tap exhibited jitter (which means by definition that the
// current tap cannot match the previous tap because the
// previous tap gave unstable data), then set the edge found
// flag, and "enable" eye size counter. But do not stop
// sampling interval - we still need to check if the current
// tap exhibits jitter
pb_cnt_eye_size_r[z] <= #TCQ 3'b000;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_found_first_edge_r[z] <= #TCQ 1'b1;
end
end
end else begin
// Before every edge detection interval, reset "intra-tap" flags
pb_found_edge_r[z] <= #TCQ 1'b0;
pb_detect_edge_done_r[z] <= #TCQ 1'b0;
end
end
end
endgenerate
// Combine the above per-bit status flags into combined terms when
// performing deskew on the aggregate data window
always @(posedge clk) begin
detect_edge_done_r <= #TCQ &pb_detect_edge_done_r;
found_edge_r <= #TCQ |pb_found_edge_r;
found_edge_all_r <= #TCQ &pb_found_edge_r;
found_stable_eye_r <= #TCQ &pb_found_stable_eye_r;
end
// last IODELAY "stable eye" indicator is updated only after
// detect_edge_done_r is asserted - so that when we do find the "right edge"
// of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1
// when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates
// immediately, then it never possible to have found_stable_eye_r = 1
// when we detect an edge - and we'll never know whether we've found
// a "right edge")
always @(posedge clk)
if (pb_detect_edge_setup)
found_stable_eye_last_r <= #TCQ 1'b0;
else if (detect_edge_done_r)
found_stable_eye_last_r <= #TCQ found_stable_eye_r;
//*****************************************************************
// keep track of edge tap counts found, and current capture clock
// tap count
//*****************************************************************
always @(posedge clk)
if (rst || new_cnt_cpt_r)
tap_cnt_cpt_r <= #TCQ 'b0;
else if (cal1_dlyce_cpt_r) begin
if (cal1_dlyinc_cpt_r)
tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1;
else
tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1;
end
always @(posedge clk)
begin
if (rst)
phaser_taps_meet_fall_window <= #TCQ 1'b0;
else if (tap_cnt_cpt_r - fall_win_det_start_taps_r >= 14) begin
if (cal1_dlyce_cpt_r && cal1_dlyinc_cpt_r)
phaser_taps_meet_fall_window <= #TCQ 1'b1;
end else
phaser_taps_meet_fall_window <= #TCQ 1'b0;
end
always @(posedge clk)
if (rst || new_cnt_cpt_r)
tap_limit_cpt_r <= #TCQ 1'b0;
else if (tap_cnt_cpt_r == 6'd63)
// (cal1_state_r == CAL1_IDEL_STORE_OLD))
tap_limit_cpt_r <= #TCQ 1'b1;
always @(posedge clk)
if (rst || new_cnt_cpt_r)
cqn_tap_limit_cpt_r <= #TCQ 1'b0;
else if (tap_cnt_cpt_r == 6'd63 && rise_detect_done)
// (cal1_state_r == CAL1_IDEL_STORE_OLD))
cqn_tap_limit_cpt_r <= #TCQ 1'b1;
always @(posedge clk)
if (rst || new_cnt_cpt_r)
idel_tap_cnt_cpt_r <= #TCQ 'b0;
else if (cal1_dlyce_q_r) begin
if (cal1_dlyinc_q_r)
idel_tap_cnt_cpt_r <= #TCQ idel_tap_cnt_cpt_r + 1;
else
idel_tap_cnt_cpt_r <= #TCQ idel_tap_cnt_cpt_r - 1;
end
always @(posedge clk)
if (rst || new_cnt_cpt_r)
idel_tap_limit_cpt_r <= #TCQ 1'b0;
else if (idel_tap_cnt_cpt_r == 6'd31)
// (cal1_state_r == CAL1_IDEL_STORE_OLD))
idel_tap_limit_cpt_r <= #TCQ 1'b1;
always @(posedge clk)
if (rst || new_cnt_cpt_r)
cnt_rise_center_taps <= #TCQ 'b0;
else if (cal1_state_r == CAL1_FALL_DETECT_EDGE_WAIT) begin
cnt_rise_center_taps <= #TCQ tap_cnt_cpt_r;
end
always @(posedge clk)
if (rst)
cal1_cnt_cpt_2r <= #TCQ 'b0;
else
cal1_cnt_cpt_2r <= #TCQ cal1_cnt_cpt_r;
// Temp wire for timing.
// The following in the always block below causes timing issues
// due to DSP block inference
// 6*cal1_cnt_cpt_r.
// replacing this with two left shifts + one left shift to avoid
// DSP multiplier.
assign cal1_cnt_cpt_timing = {2'd0, cal1_cnt_cpt_2r};
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
pi_rdlvl_dqs_tap_cnt_r <= #TCQ 'b0;
end else if (
(SIM_CAL_OPTION == "FAST_CAL") &
( ((MEMORY_IO_DIR == "UNIDIR") && (cal1_state_r1 == CAL1_FALL_DETECT_EDGE_WAIT)) ||
((MEMORY_IO_DIR == "BIDIR") && (cal1_state_r1 == CAL1_NEXT_DQS)))) begin
for (p = 0; p < RANKS; p = p +1) begin: pi_rdlvl_dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt
pi_rdlvl_dqs_tap_cnt_r[((6*q)+(p*DQS_WIDTH*6))+:6] <= #TCQ tap_cnt_cpt_r;
end
end
end else if (SIM_CAL_OPTION == "SKIP_CAL") begin
for (j = 0; j < RANKS; j = j +1) begin: pi_rdlvl_dqs_tap_rnk_cnt
for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt
pi_rdlvl_dqs_tap_cnt_r[((6*i)+(j*DQS_WIDTH*6))+:6] <= #TCQ SKIP_DLY_VAL ; //6'd31;
end
end
end else if ( ((MEMORY_IO_DIR == "UNIDIR") && (cal1_state_r1 == CAL1_FALL_DETECT_EDGE_WAIT)) ||
((MEMORY_IO_DIR == "BIDIR") && (cal1_state_r1 == CAL1_NEXT_DQS)) ) begin
//end else if (cal1_state_r1 == CAL1_FALL_DETECT_EDGE_WAIT) begin
pi_rdlvl_dqs_tap_cnt_r[(((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))
+(rnk_cnt_r*DQS_WIDTH*6))+:6]
<= #TCQ tap_cnt_cpt_r;
end
end
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
po_rdlvl_dqs_tap_cnt_r <= #TCQ 'b0;
end else if ((SIM_CAL_OPTION == "FAST_CAL") && (cal1_state_r1 == CAL1_NEXT_DQS)) begin
for (p = 0; p < RANKS; p = p +1) begin: po_rdlvl_dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt
po_rdlvl_dqs_tap_cnt_r[((6*q)+(p*DQS_WIDTH*6))+:6] <= #TCQ tap_cnt_cpt_r;
end
end
end else if (SIM_CAL_OPTION == "SKIP_CAL") begin
for (j = 0; j < RANKS; j = j +1) begin: po_rdlvl_dqs_tap_rnk_cnt
for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt
po_rdlvl_dqs_tap_cnt_r[((6*i)+(j*DQS_WIDTH*6))+:6] <= #TCQ SKIP_DLY_VAL ; //6'd31;
end
end
end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin
po_rdlvl_dqs_tap_cnt_r[(((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))
+(rnk_cnt_r*DQS_WIDTH*6))+:6]
<= #TCQ tap_cnt_cpt_r ;
end
end // always @ (posedge clk)
/*
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
rdlvl_dqs_tap_cnt_r <= #TCQ 'b0;
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin
for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt
rdlvl_dqs_tap_cnt_r[((6*q)+(p*DQS_WIDTH*6))+:6] <= #TCQ tap_cnt_cpt_r;
end
end
end else if (SIM_CAL_OPTION == "SKIP_CAL") begin
for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt
for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt
rdlvl_dqs_tap_cnt_r[((6*i)+(j*DQS_WIDTH*6))+:6] <= #TCQ SKIP_DLY_VAL ; //6'd31;
end
end
end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin
rdlvl_dqs_tap_cnt_r[(((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))
+(rnk_cnt_r*DQS_WIDTH*6))+:6]
<= #TCQ tap_cnt_cpt_r;
end
end
*/
// Counter to track maximum DQ IODELAY tap usage during the per-bit
// deskew portion of stage 1 calibration
always @(posedge clk)
if (rst) begin
idel_tap_cnt_dq_pb_r <= #TCQ 'b0;
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end else
if (new_cnt_cpt_r) begin
idel_tap_cnt_dq_pb_r <= #TCQ 'b0;
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end else if (|cal1_dlyce_dq_r) begin
if (cal1_dlyinc_dq_r)
idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1;
else
idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1;
if (idel_tap_cnt_dq_pb_r == 31)
idel_tap_limit_dq_pb_r <= #TCQ 1'b1;
else
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end
//*****************************************************************
always @(posedge clk)
cal1_state_r1 <= #TCQ cal1_state_r;
always @(posedge clk)
if (rst) begin
cal1_cnt_cpt_r <= #TCQ 'b0;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_IDLE;
cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx;
found_first_edge_r <= #TCQ 1'b0;
found_second_edge_r <= #TCQ 1'b0;
first_edge_taps_r <= #TCQ 6'bxxxxx;
new_cnt_cpt_r <= #TCQ 1'b0;
rdlvl_stg1_done <= #TCQ 1'b0;
rdlvl_stg1_err <= #TCQ 1'b0;
second_edge_taps_r <= #TCQ 6'bxxxxx;
store_sr_req_r <= #TCQ 1'b0;
rnk_cnt_r <= #TCQ 2'b00;
rdlvl_rank_done_r <= #TCQ 1'b0;
start_win_detect <= #TCQ 1'b0;
end_win_detect <= #TCQ 1'b0;
qdly_inc_done_r <= #TCQ 1'b0;
idelay_taps <= #TCQ 'b0;
start_win_taps <= #TCQ 'b0;
end_win_taps <= #TCQ 'b0;
idelay_inc_taps_r <= #TCQ 'b0;
clk_in_vld_win <= #TCQ 1'b0;
idel_dec_cntr <= #TCQ 'b0;
rise_detect_done <= #TCQ 'b0;
set_fall_capture_clock_at_tap0 <=#TCQ 1'b0;
fall_first_edge_det_done <= 1'b0;
fall_win_det_start_taps_r <= #TCQ 'b0;
fall_win_det_end_taps_r <= #TCQ 'b0;
//cnt_rise_center_taps <= #TCQ 'b0;
dbg_stg1_calc_edge <= #TCQ 'b0;
end else begin
case (cal1_state_r)
CAL1_IDLE: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
pi_gap_enforcer <= #TCQ PI_ADJ_GAP;
if (rdlvl_start) begin
if (SIM_CAL_OPTION == "SKIP_CAL") begin
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end else begin
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;
end
end
end
// Wait for the new DQS group to change
// also gives time for the read data IN_FIFO to
// output the updated data for the new DQS group
CAL1_NEW_DQS_WAIT: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
if (!cal1_wait_r) begin
// Store "previous tap" read data. Technically there is no
// "previous" read data, since we are starting a new DQS
// group, so we'll never find an edge at tap 0 unless the
// data is fluctuating/jittering
store_sr_req_r <= #TCQ 1'b1;
// If per-bit deskew is disabled, then skip the first
// portion of stage 1 calibration
if (PER_BIT_DESKEW == "OFF")
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
else if (PER_BIT_DESKEW == "ON")
cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT;
end
end
//*****************************************************************
// Per-bit deskew states
//*****************************************************************
//
// // Wait state following storage of initial read data
// CAL1_PB_STORE_FIRST_WAIT:
// if (!cal1_wait_r)
// cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
//
// // Look for an edge on all DQ bits in current DQS group
// CAL1_PB_DETECT_EDGE:
// if (detect_edge_done_r) begin
// if (found_stable_eye_r) begin
// // If we've found the left edge for all bits (or more precisely,
// // we've found the left edge, and then part of the stable
// // window thereafter), then proceed to positioning the CPT clock
// // right before the left margin
// cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1;
// cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT;
// end else begin
// // If we've reached the end of the sampling time, and haven't
// // yet found the left margin of all the DQ bits, then:
// if (!tap_limit_cpt_r) begin
// // If we still have taps left to use, then store current value
// // of read data, increment the capture clock, and continue to
// // look for (left) edges
// store_sr_req_r <= #TCQ 1'b1;
// cal1_state_r <= #TCQ CAL1_PB_INC_CPT;
// end else begin
// // If we ran out of taps moving the capture clock, and we
// // haven't finished edge detection, then reset the capture
// // clock taps to 0 (gradually, gradually, one tap at a time...
// // we don't want to piss anybody off), then exit the per-bit
// // portion of the algorithm - i.e. proceed to adjust the
// // capture clock and DQ IODELAYs as
// cnt_idel_dec_cpt_r <= #TCQ 6'd63;
// cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
// end
// end
// end
//
// // Increment delay for DQS
// CAL1_PB_INC_CPT: begin
// cal1_dlyce_cpt_r <= #TCQ 1'b1;
// cal1_dlyinc_cpt_r <= #TCQ 1'b1;
// cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT;
// end
//
// // Wait for IODELAY for both capture and internal nodes within
// // ISERDES to settle, before checking again for an edge
// CAL1_PB_INC_CPT_WAIT: begin
// cal1_dlyce_cpt_r <= #TCQ 1'b0;
// cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// if (!cal1_wait_r)
// cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
// end
// // We've found the left edges of the windows for all DQ bits
// // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture
// // clock IDELAY to position just outside left edge of data window
// CAL1_PB_DEC_CPT_LEFT:
// if (cnt_idel_dec_cpt_r == 6'b000000)
// cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT;
// else begin
// cal1_dlyce_cpt_r <= #TCQ 1'b1;
// cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
// end
//
// CAL1_PB_DEC_CPT_LEFT_WAIT:
// if (!cal1_wait_r)
// cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
//
// // If there is skew between individual DQ bits, then after we've
// // positioned the CPT clock, we will be "in the window" for some
// // DQ bits ("early" DQ bits), and "out of the window" for others
// // ("late" DQ bits). Increase DQ taps until we are out of the
// // window for all DQ bits
// CAL1_PB_DETECT_EDGE_DQ:
// if (detect_edge_done_r)
// if (found_edge_all_r) begin
// // We're out of the window for all DQ bits in this DQS group
// // We're done with per-bit deskew for this group - now decr
// // capture clock IODELAY tap count back to 0, and proceed
// // with the rest of stage 1 calibration for this DQS group
// cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
// cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
// end else
// if (!idel_tap_limit_dq_pb_r)
// // If we still have DQ taps available for deskew, keep
// // incrementing IODELAY tap count for the appropriate DQ bits
// cal1_state_r <= #TCQ CAL1_PB_INC_DQ;
// else begin
// // Otherwise, stop immediately (we've done the best we can)
// // and proceed with rest of stage 1 calibration
// cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
// cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
// end
//
// CAL1_PB_INC_DQ: begin
// // Increment only those DQ for which an edge hasn't been found yet
// cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r;
// cal1_dlyinc_dq_r <= #TCQ 1'b1;
// cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT;
// end
//
// CAL1_PB_INC_DQ_WAIT:
// if (!cal1_wait_r)
// cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
//
// // Decrement capture clock taps back to initial value
// CAL1_PB_DEC_CPT:
// if (cnt_idel_dec_cpt_r == 6'b000000)
// cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT;
// else begin
// cal1_dlyce_cpt_r <= #TCQ 1'b1;
// cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
// end
//
// // Wait for capture clock to settle, then proceed to rest of
// // state 1 calibration for this DQS group
// CAL1_PB_DEC_CPT_WAIT:
// if (!cal1_wait_r) begin
// store_sr_req_r <= #TCQ 1'b1;
// cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
// end
//
// When first starting calibration for a DQS group, save the
// current value of the read data shift register, and use this
// as a reference. Note that for the first iteration of the
// edge detection loop, we will in effect be checking for an edge
// at IODELAY taps = 0 - normally, we are comparing the read data
// for IODELAY taps = N, with the read data for IODELAY taps = N-1
// An edge can only be found at IODELAY taps = 0 if the read data
// is changing during this time (possible due to jitter)
CAL1_STORE_FIRST_WAIT: //0x02
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_DETECT_EDGE_Q;
// look for data window using Q IDELAY taps
CAL1_DETECT_EDGE_Q: begin //0x17
//if (detect_edge_done_r) begin
if (detect_edge_done_r && (idelay_taps > MIN_Q_VALID_TAPS) && (CLK_PERIOD > 2500) && (start_win_taps > 0) && idel_tap_limit_cpt_r ) begin
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q_ALL; // decrement to the center of the start_win_taps and end_win_taps
//clk_in_vld_win <= 1'b1;
idel_dec_cntr <= #TCQ ((idel_tap_cnt_cpt_r-1) - start_win_taps) >>1;
end_win_taps <= #TCQ idel_tap_cnt_cpt_r-1;
qdly_inc_done_r <= #TCQ 1;
end else if (idel_tap_limit_cpt_r)
// Only one edge detected and ran out of taps since only one
// bit time worth of taps available for window detection. This
// can happen if at tap 0 DQS is in previous window which results
// in only left edge being detected. Or at tap 0 DQS is in the
// current window resulting in only right edge being detected.
// Depending on the frequency this case can also happen if at
// tap 0 DQS is in the left noise region resulting in only left
// edge being detected.
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q; //0x1C
else if (qdly_inc_done_r)
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q;
else if (~qdly_inc_done_r)
// start for valid window check
if (data_valid && ~start_win_detect) begin
start_win_detect <= #TCQ 1'b1;
start_win_taps <= #TCQ idel_tap_cnt_cpt_r;
idelay_taps <= #TCQ idelay_taps +1; // only computes no. of data taps in valid window
cal1_state_r <= #TCQ CAL1_IDEL_STORE_OLD_Q;
// if in the valid window region, continue to increment idelay taps until an edge is detected
end else if (start_win_detect && data_valid && ~detect_edge_done_r) begin
cal1_state_r <= #TCQ CAL1_IDEL_STORE_OLD_Q;
idelay_taps <= #TCQ idelay_taps + 1;
// when edge is detected : case where clock was in valid window to begin with
end else if (detect_edge_done_r && (idelay_taps > MIN_Q_VALID_TAPS) && (CLK_PERIOD > 2500) && (start_win_taps == 0) ) begin
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q_ALL;
idel_dec_cntr <= #TCQ idel_tap_cnt_cpt_r; // decrement all the data taps to 0, proceed to find clk taps
end_win_taps <= #TCQ idel_tap_cnt_cpt_r-1;
qdly_inc_done_r <= #TCQ 1;
// when edge is detected : case where clock was in invalid window at start
end else if (detect_edge_done_r && (idelay_taps > MIN_Q_VALID_TAPS) && (CLK_PERIOD > 2500) && (start_win_taps > 0) ) begin
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q_ALL; // decrement to the center of the start_win_taps and end_win_taps
//clk_in_vld_win <= 1'b1;
idel_dec_cntr <= #TCQ ((idel_tap_cnt_cpt_r-1) - start_win_taps) >>1;
end_win_taps <= #TCQ idel_tap_cnt_cpt_r-1;
qdly_inc_done_r <= #TCQ 1;
// when edge is detected
end else if (detect_edge_done_r && idelay_taps > MIN_Q_VALID_TAPS) begin
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q; //1C
end_win_taps <= #TCQ idel_tap_cnt_cpt_r-1;
qdly_inc_done_r <= #TCQ 1;
// when edge is detected, but possibly in the uncertainty region, reset start of window, continue to increment
end else if (~data_valid && idelay_taps <= MIN_Q_VALID_TAPS) begin
cal1_state_r <= #TCQ CAL1_IDEL_STORE_OLD_Q; //0x1A
start_win_detect <= #TCQ 1'b0;
idelay_taps <= #TCQ 0;
// if rising edge falls in the fall window, continue to increment idelay taps
end else if (~data_valid && ~start_win_detect ) begin
cal1_state_r <= #TCQ CAL1_IDEL_STORE_OLD_Q;
idelay_taps <= #TCQ 0;
end
end
// Store the current read data into the read data shift register
// before incrementing the tap count and doing this again
CAL1_IDEL_STORE_OLD_Q: begin
store_sr_req_r <= #TCQ 1'b1;
if (store_sr_done_r)begin
cal1_state_r <= #TCQ CAL1_IDEL_INC_Q;
new_cnt_cpt_r <= #TCQ 1'b0;
end
end
// Increment Idelay
CAL1_IDEL_INC_Q: begin //0x18
cal1_state_r <= #TCQ CAL1_IDEL_INC_Q_WAIT;
if (~idel_tap_limit_cpt_r) begin
cal1_dlyce_q_r <= #TCQ 1'b1;
cal1_dlyinc_q_r <= #TCQ 1'b1;
end else begin
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_IDEL_INC_Q_WAIT: begin //0x19
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
if (!cal1_wait_r)
if (idelay_inc_taps_r > 0) begin // case where idelay taps sufficient to center clock and data.
if (idel_tap_cnt_cpt_r == idelay_inc_taps_r)
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; // 0x08 idelay tap increment is done, proceed to decrement phaser taps to 0.
else
cal1_state_r <= #TCQ CAL1_IDEL_INC_Q;
end else begin
cal1_state_r <= #TCQ CAL1_DETECT_EDGE_Q; //0x17
end
end
// Increment Phaser_IN delay for DQS
CAL1_IDEL_DEC_Q_ALL: begin
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q_ALL_WAIT;
idel_dec_cntr <= idel_dec_cntr -1;
cal1_dlyce_q_r <= #TCQ 1'b1;
cal1_dlyinc_q_r <= #TCQ 1'b0;
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_IDEL_DEC_Q_ALL_WAIT: begin
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
if (!cal1_wait_r) begin
if ((idel_dec_cntr == 6'h00) && (start_win_taps == 0))
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
else if ((idel_dec_cntr == 6'h00) && (start_win_taps > 0))
cal1_state_r <= #TCQ CAL1_NEXT_DQS;
else
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q_ALL;
end
end
// Increment Phaser_IN delay for DQS
// CQ_CQB capturing scheme in QDR2+
CAL1_IDEL_DEC_Q: begin
cal1_state_r <= #TCQ CAL1_IDEL_DEC_Q_WAIT;
cal1_dlyce_q_r <= #TCQ 1'b1;
cal1_dlyinc_q_r <= #TCQ 1'b0;
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_IDEL_DEC_Q_WAIT: begin
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
end
// Check for presence of data eye edge
CAL1_DETECT_EDGE: begin//0x03
if (detect_edge_done_r) begin
if (tap_limit_cpt_r) begin
if (~found_first_edge_r) begin
first_edge_taps_r <= #TCQ tap_cnt_cpt_r; // if no edge previously detected, treat this as an edge,inorder to calculate tap delays.
end
cal1_state_r <= #TCQ CAL1_CALC_IDEL_WAIT; //0x20
end else if (found_edge_r && ~data_valid) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
found_first_edge_r <= #TCQ 1'b1;
// Both edges of data valid window found:
// If we've found a second edge after a region of stability
// then we must have just passed the second ("right" edge of
// the window. Record this second_edge_taps = current tap-1,
// because we're one past the actual second edge tap, where
// the edge taps represent the extremes of the data valid
// window (i.e. smallest & largest taps where data still valid
if (found_first_edge_r && found_stable_eye_last_r) begin
found_second_edge_r <= #TCQ 1'b1;
second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1;
cal1_state_r <= #TCQ CAL1_CALC_IDEL_WAIT;
end else if ((CLK_PERIOD <= 2500) && (tap_cnt_cpt_r < MIN_EYE_SIZE)) begin
first_edge_taps_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_IDEL_STORE_OLD;
end else begin
first_edge_taps_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_CALC_IDEL_WAIT; //0x20
end
end else begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
cal1_state_r <= #TCQ CAL1_IDEL_STORE_OLD;
end
end
end
// Store the current read data into the read data shift register
// before incrementing the tap count and doing this again
CAL1_IDEL_STORE_OLD: begin
store_sr_req_r <= #TCQ 1'b1;
if (store_sr_done_r)begin
cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT;
new_cnt_cpt_r <= #TCQ 1'b0;
end
end
// Increment Phaser_IN delay for DQS
// for both PI and PO in QDR+
CAL1_IDEL_INC_CPT: begin //0x5
cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT;
if (~tap_limit_cpt_r) begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b1;
end else begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_IDEL_INC_CPT_WAIT: begin //0x6
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
end
// allow for delay calculations to settle down.
CAL1_CALC_IDEL_WAIT: begin //0x20
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_CALC_IDEL;
end
// Calculate final value of Phaser_IN taps. At this point, one or both
// edges of data eye have been found, and/or all taps have been
// exhausted looking for the edges
// NOTE: We're calculating the amount to decrement by, not the
// absolute setting for DQS.
CAL1_CALC_IDEL: begin //0x07
if (CLK_PERIOD > 2500 && (start_win_taps == 0) ) begin
// if clk was in the correct window, but setup margin > hold margin, add delay to data to center. Make sure the delay difference is not within the per idelay tap delay range,
// when q taps increments are not needed.
//if (idelay_tap_delay > phaser_tap_delay) begin
if (idel_gt_phaser_delay) begin
// Divided both sides of the condition by IODELAY_TAP_RES
// if ((idel_minus_phaser_delay) < (2*IODELAY_TAP_RES)) begin
if (idel_minus_phaser_delay < 2) begin
idelay_inc_taps_r <= #TCQ 0;
cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; // reset the clock taps back
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
end else begin
//idelay_inc_taps_r <= ((idel_minus_phaser_delay >>1 )/IODELAY_TAP_RES);
idelay_inc_taps_r <= (idel_minus_phaser_delay >> 1);
cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; // reset the clock taps back
cal1_state_r <= #TCQ CAL1_IDEL_INC_Q;
end
//if clk was in the correct window, but setup margin < hold margin , add delay to clock.
end else begin
// no idelay tap increments
// for frequencies greater than 400 Mhz, no taps to decrement. 64 taps of fine delay should place the clock close to the center of the window
idelay_inc_taps_r <= #TCQ 0;
cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r - phaser_dec_taps;
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
end
//end
// CASE1: If 2 edges found.
end else begin
if (found_second_edge_r) begin
cnt_idel_dec_cpt_r <= #TCQ ((second_edge_taps_r - first_edge_taps_r)>>1) + 1;
dbg_stg1_calc_edge[2] <= #TCQ 'b1;
// first_edge_taps_r is indeed the start of the window
end else if (first_edge_taps_r <= MIN_EYE_SIZE) begin
cnt_idel_dec_cpt_r <= #TCQ (32 - first_edge_taps_r);
dbg_stg1_calc_edge[0] <= #TCQ 'b1;
// firs edge detected is not the start but instead the end of the window.. THis can only happen when the initial data alignment ends up positioning
// the lock inside the valid window.
end else if (first_edge_taps_r > MIN_EYE_SIZE) begin
cnt_idel_dec_cpt_r <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r) + (first_edge_taps_r)>>1) ;
dbg_stg1_calc_edge[1] <= #TCQ 'b1;
end else begin
// No edges detected
cnt_idel_dec_cpt_r <= #TCQ ((tap_cnt_cpt_r)>>1) + 1;
dbg_stg1_calc_edge[3] <= #TCQ 'b1;
end
// Now use the value we just calculated to decrement CPT taps
// to the desired calibration point
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; //0x08
end
end
// decrement capture clock for final adjustment - center
// capture clock in middle of data eye. This adjustment will occur
// only when both the edges are found usign CPT taps. Must do this
// incrementally to avoid clock glitching (since CPT drives clock
// divider within each ISERDES)
CAL1_IDEL_DEC_CPT: begin //0x08
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
pi_gap_enforcer <= #TCQ PI_ADJ_GAP;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
if ((cnt_idel_dec_cpt_r == 6'b000001) &&
((MEMORY_IO_DIR == "BIDIR") || ((MEMORY_IO_DIR == "UNIDIR") && (CLK_PERIOD > 2500)))) begin
if (CPT_CLK_CQ_ONLY == "FALSE") // this only apply to QDR2 memory.
cal1_state_r <= #TCQ CAL1_FALL_DETECT_EDGE_WAIT;
else
cal1_state_r <= #TCQ CAL1_NEXT_DQS;// CAL1_NEXT_DQS; //0x0A
//CAL1_FALL_DETECT_EDGE_WAIT for CQ_CQB
rise_detect_done <= #TCQ 1'b1;
end else if ((cnt_idel_dec_cpt_r == 6'b000001) && (CLK_PERIOD <= 2500)) begin
// finish decrement PI's tap to its final calculated position; jump to deal with FALL data bit window.
rise_detect_done <= #TCQ 1'b1;
//fall_win_det_start_taps_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_FALL_DETECT_EDGE_WAIT; //0x28
end else begin
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; //0x09
end end
/* if (cnt_idel_dec_cpt_r == 6'b000001)
cal1_state_r <= #TCQ CAL1_NEXT_DQS;
else
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT;
end*/
CAL1_IDEL_DEC_CPT_WAIT: begin //0x09
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
//Decrement our counter, then once it hits zero we can move on
if (pi_gap_enforcer != 'b0)
pi_gap_enforcer <= #TCQ pi_gap_enforcer - 1;
else
pi_gap_enforcer <= #TCQ pi_gap_enforcer;
if (pi_gap_enforcer == 'b0)
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
else
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT;
end
// wait state to determine cq center taps.
CAL1_FALL_DETECT_EDGE_WAIT: begin //0x28
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
//Decrement our counter, then once it hits zero we can move on
if (pi_gap_enforcer != 'b0)
pi_gap_enforcer <= #TCQ pi_gap_enforcer - 1;
else
pi_gap_enforcer <= #TCQ pi_gap_enforcer;
if (pi_gap_enforcer == 'b0)
cal1_state_r <= #TCQ CAL1_IDEL_FALL_DEC_CPT;
else
cal1_state_r <= #TCQ CAL1_FALL_DETECT_EDGE_WAIT;
end
CAL1_IDEL_FALL_DEC_CPT: begin //0x29
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
pi_gap_enforcer <= #TCQ PI_ADJ_GAP;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
//cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
if (tap_cnt_cpt_r == 6'h03)
cal1_state_r <= CAL1_FALL_DETECT_EDGE;
else
cal1_state_r <= #TCQ CAL1_IDEL_FALL_DEC_CPT_WAIT;
end
CAL1_IDEL_FALL_DEC_CPT_WAIT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
//Decrement our counter, then once it hits zero we can move on
if (pi_gap_enforcer != 'b0)
pi_gap_enforcer <= #TCQ pi_gap_enforcer - 1;
else
pi_gap_enforcer <= #TCQ pi_gap_enforcer;
if (pi_gap_enforcer == 'b0)
cal1_state_r <= #TCQ CAL1_IDEL_FALL_DEC_CPT;
else
cal1_state_r <= #TCQ CAL1_IDEL_FALL_DEC_CPT_WAIT;
end
// since cq# is always delayed along with cq so far, the cq# phaser taps should be non-zero and it should be in the fall window to begin with.
// if the data is not in the valid window, then continue to decrement the cq# phaser taps.
CAL1_FALL_DETECT_EDGE : begin //0x21
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (detect_edge_done_r) begin
if (cqn_tap_limit_cpt_r) begin
fall_win_det_end_taps_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_FALL_CALC_DELAY;
// second edge of fall window - stop incrementing
//end else if (fall_first_edge_det_done && found_edge_r && ~data_valid && found_stable_eye_last_r && ((tap_cnt_cpt_r - fall_win_det_start_taps_r) > 6'h10)) begin
end else if (fall_first_edge_det_done && ~data_valid && ((tap_cnt_cpt_r - fall_win_det_start_taps_r) > 8)) begin
// decide if the rising edge of falling capture clock is close to PO's tap 0.
// Assume PI found 32 bits tap window for rising bit, ideally PO should also find 32 bits tap window for falling bit.
//
//
// PO's tap 0 16 32
// |........:........:........:........:........:........:
//
// Fall bit valid window
//case 1 : X--------:--------:--------:--------X detect edge when PO taps is at 16
//
//case 2 : X--------:--------:--------:--------X detect edge when PO taps is at 20
//
//
//case 3: X--------:--------:--------:--------X detect edge when PO taps is at 28
//
//case 4: X--------:--------:--------:--------X detect edges when PO taps is at 4 and 36
//
// "first_edge_taps_r" latches the rising edge window size.
//if ((first_edge_taps_r - tap_cnt_cpt_r) > 10) begin
if ((tap_cnt_cpt_r - 4 ) <= first_edge_taps_r[5:1]) begin
cal1_state_r <= #TCQ CAL1_FALL_IDEL_INC_Q;
stored_idel_tap_cnt_cpt_r <= idel_tap_cnt_cpt_r;
end
else begin
cal1_state_r <= #TCQ CAL1_FALL_CALC_DELAY;
end
fall_win_det_end_taps_r <= #TCQ tap_cnt_cpt_r - 1;
// first edge detection - the first valid data, continue to increment
end else if (~fall_first_edge_det_done && data_valid && fall_win_det_start_taps_r == 6'h00) begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
fall_win_det_start_taps_r <= #TCQ tap_cnt_cpt_r;
fall_first_edge_det_done <= 1'b0;
cal1_state_r <= #TCQ CAL1_FALL_IDEL_STORE_OLD; //0x22
// assert fall_first_edge_det_done if window is valid for atleast 15 taps, continue to increment until edge found
// was F
end else if (~fall_first_edge_det_done && data_valid && ((tap_cnt_cpt_r - fall_win_det_start_taps_r) >= 6'h0A)) begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
fall_first_edge_det_done <= 1'b1;
cal1_state_r <= #TCQ CAL1_FALL_IDEL_STORE_OLD; //0x22
// smaller window seen, reset flag and start again.
end else if (~fall_first_edge_det_done && ~data_valid && ((tap_cnt_cpt_r - fall_win_det_start_taps_r) < 6'h0A)) begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
fall_win_det_start_taps_r <= #TCQ 6'h00;// reset start of window.
fall_first_edge_det_done <= 1'b0;
cal1_state_r <= #TCQ CAL1_FALL_IDEL_STORE_OLD; //0x22
end else begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
cal1_state_r <= #TCQ CAL1_FALL_IDEL_STORE_OLD; //0x22
end
end
end
CAL1_FALL_IDEL_STORE_OLD : begin
store_sr_req_r <= #TCQ 1'b1;
if (store_sr_done_r)begin
cal1_state_r <= #TCQ CAL1_FALL_INC_CPT;
new_cnt_cpt_r <= #TCQ 1'b0;
end
end
CAL1_FALL_INC_CPT: begin //0x23
cal1_state_r <= #TCQ CAL1_FALL_INC_CPT_WAIT;
if (~cqn_tap_limit_cpt_r) begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b1;
end else begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_FALL_INC_CPT_WAIT: begin //0x24
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_FALL_DETECT_EDGE;
end
CAL1_FALL_CALC_DELAY: begin //0x25 cnt_rise_center_taps
// if (( fall_win_det_end_taps_r - fall_win_det_start_taps_r) > cnt_rise_center_taps) begin
// //fall_dec_taps_r <= tap_cnt_cpt_r - ( fall_win_det_end_taps_r - (fall_win_det_start_taps_r + cnt_rise_center_taps)); // no. of taps to increment cq# by
// fall_dec_taps_r <= tap_cnt_cpt_r - ( fall_win_det_end_taps_r - cnt_rise_center_taps); // no. of taps to increment cq# by
// cal1_state_r <= #TCQ CAL1_FALL_FINAL_DEC_TAP;
// end else if (( fall_win_det_end_taps_r - fall_win_det_start_taps_r) < cnt_rise_center_taps) begin
// fall_dec_taps_r <= tap_cnt_cpt_r - cnt_rise_center_taps;// no. of taps to decrement cq# by
// cal1_state_r <= #TCQ CAL1_FALL_FINAL_DEC_TAP;
// end else begin
// fall_dec_taps_r <= 'b0;
// cal1_state_r <= #TCQ CAL1_NEXT_DQS;
// end
// if (fall_win_det_start_taps_r > 6'd54) // ??? **** is this a good assumption
if (fall_win_det_start_taps_r > 6'h28)
fall_dec_taps_r <= 6'h01;
else if (set_fall_capture_clock_at_tap0)
fall_dec_taps_r <= #TCQ fall_win_det_end_taps_r;
else begin
fall_dec_taps_r <= ( fall_win_det_end_taps_r - fall_win_det_start_taps_r) >> 1;
end
cal1_state_r <= #TCQ CAL1_FALL_FINAL_DEC_TAP;
end
CAL1_FALL_FINAL_DEC_TAP: begin //0x26
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
pi_gap_enforcer <= #TCQ PI_ADJ_GAP;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
fall_dec_taps_r <= #TCQ fall_dec_taps_r - 1;
if (fall_dec_taps_r == 6'b000001) begin
cal1_state_r <= #TCQ CAL1_NEXT_DQS; //0xA
end else begin
cal1_state_r <= #TCQ CAL1_FALL_FINAL_DEC_TAP_WAIT; //0x27
end
end
CAL1_FALL_FINAL_DEC_TAP_WAIT: begin //0x27
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
//Decrement our counter, then once it hits zero we can move on
if (pi_gap_enforcer != 'b0)
pi_gap_enforcer <= #TCQ pi_gap_enforcer - 1;
else
pi_gap_enforcer <= #TCQ pi_gap_enforcer;
if (pi_gap_enforcer == 'b0)
cal1_state_r <= #TCQ CAL1_FALL_FINAL_DEC_TAP;
else
cal1_state_r <= #TCQ CAL1_FALL_FINAL_DEC_TAP_WAIT;
end
// STATE 31,32,33 and 34 are new added states for case that the falling data capture clock edge is far away
// from rising data capture clock edge. There is variation of skew between PHASERS.
// Rising window taps could have enough taps e.g. 36 taps. And the falling bit time has valid data at tap 0 of
// PO and end at e.g. 14 taps. In this case, the tap 0 is roughly actual center of the falling bit time. And the
// PO tap should set to zero. The new added states is to adjust the IDELAY taps temporary when we detects
// end tap of falling data . If valid data appears again for two IDELAY taps, for sure tap 0 is not
// left edge of falling bit data. We can safely set the PO tap at ZERO.
CAL1_FALL_IDEL_INC_Q: begin //0x31m he
cal1_state_r <= #TCQ CAL1_FALL_IDEL_INC_Q_WAIT;
if (~idel_tap_limit_cpt_r) begin
cal1_dlyce_q_r <= #TCQ 1'b1;
cal1_dlyinc_q_r <= #TCQ 1'b1;
end else begin
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_FALL_IDEL_INC_Q_WAIT: begin //0x32
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
if (!cal1_wait_r)
// For 400 MHz and above design, each idelay tap is equivalent about 80 ps.
// Temporary move the idelay taps for the Q input and test if getting valid
// falling valid data pattern. After the test, the idelay tap value is restored.
if (fall_match && ( idel_tap_cnt_cpt_r - stored_idel_tap_cnt_cpt_r) < 2 ) begin //
//
cal1_state_r <= #TCQ CAL1_FALL_IDEL_INC_Q; //31
end else begin
if (fall_match)
set_fall_capture_clock_at_tap0 <= 1'b1;
else
set_fall_capture_clock_at_tap0 <= 1'b0;
cal1_state_r <= #TCQ CAL1_FALL_IDEL_RESTORE_Q; //0x33
end
end
CAL1_FALL_IDEL_RESTORE_Q: begin //0x33
cal1_state_r <= #TCQ CAL1_FALL_IDEL_RESTORE_Q_WAIT;
if (~idel_tap_limit_cpt_r) begin
cal1_dlyce_q_r <= #TCQ 1'b1;
cal1_dlyinc_q_r <= #TCQ 1'b0;
end else begin
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
end
end
CAL1_FALL_IDEL_RESTORE_Q_WAIT: begin //0x34
cal1_dlyce_q_r <= #TCQ 1'b0;
cal1_dlyinc_q_r <= #TCQ 1'b0;
if (!cal1_wait_r)
if (idel_tap_cnt_cpt_r != stored_idel_tap_cnt_cpt_r) begin // case where idelay taps sufficient to center clock and data.
cal1_state_r <= #TCQ CAL1_FALL_IDEL_RESTORE_Q; //19
end else begin
cal1_state_r <= #TCQ CAL1_FALL_CALC_DELAY; //0x25
end
end
// Determine whether we're done, or have more DQS's to calibrate
// Also request precharge after every byte, as appropriate
CAL1_NEXT_DQS: begin
cal1_prech_req_r <= #TCQ 1'b1;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// Prepare for another iteration with next DQS group
found_first_edge_r <= #TCQ 1'b0;
found_second_edge_r <= #TCQ 1'b0;
first_edge_taps_r <= #TCQ 'd0;
second_edge_taps_r <= #TCQ 'd0;
// Wait until precharge that occurs in between calibration of
// DQS groups is finished
if (prech_done) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
//rdlvl_rank_done_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin
// All DQS groups in a rank done
rdlvl_rank_done_r <= #TCQ 1'b1;
if (rnk_cnt_r == RANKS-1) begin
// All DQS groups in all ranks done
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end else begin
// Process DQS groups in next rank
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_cnt_cpt_r <= #TCQ 'b0;
cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;
end
end else begin
// Process next DQS group
new_cnt_cpt_r <= #TCQ 1'b1;
qdly_inc_done_r <= #TCQ 1'b0;
start_win_taps <= #TCQ 'b0;
end_win_taps <= #TCQ 'b0;
idelay_taps <= #TCQ 'b0;
idelay_inc_taps_r <= #TCQ 'b0;
idel_dec_cntr <= #TCQ 'b0;
rise_detect_done <= #TCQ 'b0;
fall_first_edge_det_done <= 1'b0;
fall_win_det_start_taps_r <= #TCQ 'b0;
fall_win_det_end_taps_r <= #TCQ 'b0;
cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1;
dbg_stg1_calc_edge <= #TCQ 0; //clear our flag for each byte
cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;
end
end
end
// Load rank registers in Phaser_IN
CAL1_REGL_LOAD: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
rnk_cnt_r <= #TCQ 2'b00;
if ((regl_rank_cnt == RANKS-1) &&
((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)))
cal1_state_r <= #TCQ CAL1_DONE;
else
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end
// Done with this stage of calibration
// if used, allow DEBUG_PORT to control taps
CAL1_DONE: begin
rdlvl_stg1_done <= #TCQ 1'b1;
end
default : begin
cal1_state_r <= #TCQ CAL1_IDLE;
end
endcase
end
// generate an error signal for each byte lane in the event no window found
genvar nd_i;
generate
for (nd_i=0; nd_i < DQS_WIDTH; nd_i=nd_i+1) begin : nd_rdlvl_err
always @ (posedge clk)
begin
if (rst)
dbg_phy_rdlvl_err[nd_i] <= #TCQ 'b0;
else if (nd_i == cal1_cnt_cpt_r)
dbg_phy_rdlvl_err[nd_i] <= #TCQ dbg_stg1_calc_edge[0];
else
dbg_phy_rdlvl_err[nd_i] <= #TCQ dbg_phy_rdlvl_err[nd_i];
end
end
endgenerate
endmodule |
module siete_segmentos_principal(
input wire bitA,
input wire bitB,
input wire bitC,
input wire bitD,
input wire en1,
input wire en2,
input wire en3,
input wire en4,
output seg_a,
output seg_b,
output seg_c,
output seg_d,
output seg_e,
output seg_f,
output seg_g,
output s_seg1,
output s_seg2,
output s_seg3,
output s_seg4
);
assign s_seg1 = !en1;
assign s_seg2 = !en2;
assign s_seg3 = !en3;
assign s_seg4 = !en4;
assign seg_a = !((!bitB&!bitD)|(!bitA&bitC)|(!bitA&bitB&bitD)|(bitB&bitC)|(bitA&!bitD)|(bitA&!bitB&!bitC));
assign seg_b = !((bitA&!bitC&bitD)|(!bitB&!bitD)|(!bitA&!bitC&!bitD)|(!bitA&bitC&bitD)|(!bitA&!bitB));
assign seg_c = !((!bitC&bitD)|(!bitA&bitB)|(bitA&!bitB)|(!bitA&!bitC)|(!bitA&bitD));
assign seg_d = !((bitB&!bitC&bitD)|(!bitB&bitC&bitD)|(bitB&bitC&!bitD)|(bitA&!bitC)|(!bitA&!bitB&!bitD));
assign seg_e = !((!bitB&!bitD)|(bitC&!bitD)|(bitA&bitC)|(bitA&bitB));
assign seg_f = !((!bitC&!bitD)|(bitB&!bitD)|(!bitA&bitB&!bitC)|(bitA&!bitB)|(bitA&bitC));
assign seg_g = !((!bitB&bitC)|(bitA&!bitB)|(bitA&bitD)|(bitC&!bitD)|(!bitA&bitB&!bitC));
endmodule |
module sky130_fd_sc_lp__a21bo_lp (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__a21bo_lp (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule |
module MAX6682 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/max6682.v:135" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/max6682.v:137" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/max6682.v:139" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/max6682.v:141" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/max6682.v:143" *)
output MAX6682CS_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataOut", src = "../../verilog/max6682.v:145" *)
input[7:0] SPI_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Write", src = "../../verilog/max6682.v:147" *)
output SPI_Write_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_ReadNext", src = "../../verilog/max6682.v:149" *)
output SPI_ReadNext_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataIn", src = "../../verilog/max6682.v:151" *)
output[7:0] SPI_Data_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOFull", src = "../../verilog/max6682.v:153" *)
input SPI_FIFOFull_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOEmpty", src = "../../verilog/max6682.v:155" *)
input SPI_FIFOEmpty_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Transmission", src = "../../verilog/max6682.v:157" *)
input SPI_Transmission_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetH_i", src = "../../verilog/max6682.v:159" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetL_i", src = "../../verilog/max6682.v:161" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/max6682.v:163" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/max6682.v:165" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPOL", src = "../../verilog/max6682.v:167" *)
output SPI_CPOL_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPHA", src = "../../verilog/max6682.v:169" *)
output SPI_CPHA_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_LSBFE", src = "../../verilog/max6682.v:171" *)
output SPI_LSBFE_o
);
(* src = "../../verilog/max6682.v:297" *)
wire [31:0] \$0\SensorFSM_Timer[31:0] ;
(* src = "../../verilog/max6682.v:327" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SPI_FSM_Start[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$732 ;
wire \$procmux$118_CMP ;
wire \$procmux$123_CMP ;
wire \$procmux$126_CMP ;
wire [31:0] \$procmux$449_Y ;
(* src = "../../verilog/max6682.v:311" *)
wire [31:0] \$sub$../../verilog/max6682.v:311$18_Y ;
(* src = "../../verilog/max6682.v:111" *)
wire [7:0] \$techmap\MAX6682_SPI_FSM_1.$0\Byte0[7:0] ;
(* src = "../../verilog/max6682.v:111" *)
wire [7:0] \$techmap\MAX6682_SPI_FSM_1.$0\Byte1[7:0] ;
(* src = "../../verilog/max6682.v:50" *)
wire \$techmap\MAX6682_SPI_FSM_1.$2\MAX6682CS_n_o[0:0] ;
(* src = "../../verilog/max6682.v:50" *)
wire \$techmap\MAX6682_SPI_FSM_1.$2\SPI_FSM_Wr1[0:0] ;
wire \$techmap\MAX6682_SPI_FSM_1.$auto$opt_reduce.cc:126:opt_mux$736 ;
wire \$techmap\MAX6682_SPI_FSM_1.$procmux$553_CMP ;
wire \$techmap\MAX6682_SPI_FSM_1.$procmux$554_CMP ;
wire \$techmap\MAX6682_SPI_FSM_1.$procmux$558_CMP ;
wire \$techmap\MAX6682_SPI_FSM_1.$procmux$559_CMP ;
wire \$techmap\MAX6682_SPI_FSM_1.$procmux$560_CMP ;
wire \$techmap\MAX6682_SPI_FSM_1.$procmux$563_CMP ;
(* src = "../../verilog/max6682.v:323" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682.v:184" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682.v:185" *)
wire [7:0] Byte1;
(* src = "../../verilog/max6682.v:342" *)
wire [16:0] DiffAB;
(* src = "../../verilog/max6682.v:343" *)
wire [15:0] DiffBA;
(* src = "../../verilog/max6682.v:11" *)
wire [7:0] \MAX6682_SPI_FSM_1.Byte0 ;
(* src = "../../verilog/max6682.v:12" *)
wire [7:0] \MAX6682_SPI_FSM_1.Byte1 ;
(* src = "../../verilog/max6682.v:3" *)
wire \MAX6682_SPI_FSM_1.Clk_i ;
(* src = "../../verilog/max6682.v:6" *)
wire \MAX6682_SPI_FSM_1.MAX6682CS_n_o ;
(* src = "../../verilog/max6682.v:2" *)
wire \MAX6682_SPI_FSM_1.Reset_n_i ;
(* src = "../../verilog/max6682.v:10" *)
wire [7:0] \MAX6682_SPI_FSM_1.SPI_Data_i ;
(* src = "../../verilog/max6682.v:9" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Done ;
(* src = "../../verilog/max6682.v:4" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Start ;
(* src = "../../verilog/max6682.v:24" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/max6682.v:23" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ;
(* src = "../../verilog/max6682.v:8" *)
wire \MAX6682_SPI_FSM_1.SPI_ReadNext_o ;
(* src = "../../verilog/max6682.v:5" *)
wire \MAX6682_SPI_FSM_1.SPI_Transmission_i ;
(* src = "../../verilog/max6682.v:7" *)
wire \MAX6682_SPI_FSM_1.SPI_Write_o ;
(* src = "../../verilog/max6682.v:183" *)
wire SPI_FSM_Done;
(* src = "../../verilog/max6682.v:182" *)
wire SPI_FSM_Start;
(* src = "../../verilog/max6682.v:215" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/max6682.v:216" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/max6682.v:295" *)
wire [31:0] SensorFSM_Timer;
(* src = "../../verilog/max6682.v:214" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682.v:212" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682.v:213" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682.v:321" *)
wire [15:0] SensorValue;
(* src = "../../verilog/max6682.v:322" *)
wire [15:0] Word0;
wire SPIFSM_1_Out7_s;
wire SPIFSM_1_Out8_s;
wire SPIFSM_1_Out9_s;
wire SPIFSM_1_Out10_s;
wire SPIFSM_1_Out11_s;
wire SPIFSM_1_Out12_s;
wire SPIFSM_1_Out13_s;
wire SPIFSM_1_Out14_s;
wire SPIFSM_1_CfgMode_s;
wire SPIFSM_1_CfgClk_s;
wire SPIFSM_1_CfgShift_s;
wire SPIFSM_1_CfgDataIn_s;
wire SPIFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out3_s;
wire SensorFSM_1_Out4_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$auto$opt_reduce.cc:130:opt_mux$733 (
.A({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$732 )
);
(* src = "../../verilog/max6682.v:316" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(32),
.B_SIGNED(0),
.B_WIDTH(32),
.Y_WIDTH(1)
) \$eq$../../verilog/max6682.v:316$19 (
.A(SensorFSM_Timer),
.B(0),
.Y(SensorFSM_TimerOvfl)
);
SensorFSM SensorFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(SPI_FSM_Done),
.In2_i(SensorFSM_DiffTooLarge),
.In3_i(SensorFSM_TimerOvfl),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\$procmux$118_CMP ),
.Out1_o(\$procmux$123_CMP ),
.Out2_o(\$procmux$126_CMP ),
.Out3_o(SensorFSM_1_Out3_s),
.Out4_o(SensorFSM_1_Out4_s),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/max6682.v:348" *)
\$gt #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$gt$../../verilog/max6682.v:348$26 (
.A(AbsDiffResult),
.B(Threshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/max6682.v:297" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(0),
.CLK_POLARITY(1'b1),
.WIDTH(32)
) \$procdff$727 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[31:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/max6682.v:327" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$procdff$728 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$117 (
.A(\$auto$opt_reduce.cc:126:opt_mux$732 ),
.Y(CpuIntr_o)
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$137 (
.A(\$procmux$123_CMP ),
.B(\$2\SPI_FSM_Start[0:0] ),
.Y(SPI_FSM_Start)
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$147 (
.A(\$procmux$118_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$procmux$177 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$procmux$192 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(SensorFSM_TimerPreset)
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$230 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$259 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\SPI_FSM_Start[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$336 (
.A(SPI_FSM_Done),
.B(SensorFSM_DiffTooLarge),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(1)
) \$procmux$368 (
.A(1'b1),
.B(\$4\SensorFSM_TimerPreset[0:0] ),
.S(SPI_FSM_Done),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$400 (
.A(SensorFSM_DiffTooLarge),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32)
) \$procmux$449 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/max6682.v:311$18_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$449_Y )
);
\$mux #(
.WIDTH(32)
) \$procmux$452 (
.A(\$procmux$449_Y ),
.B({ PeriodCounterPresetH_i, PeriodCounterPresetL_i }),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[31:0] )
);
\$mux #(
.WIDTH(16)
) \$procmux$455 (
.A(Word0),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
(* src = "../../verilog/max6682.v:311" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(32),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(32)
) \$sub$../../verilog/max6682.v:311$18 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/max6682.v:311$18_Y )
);
(* src = "../../verilog/max6682.v:344" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(17),
.B_SIGNED(0),
.B_WIDTH(17),
.Y_WIDTH(17)
) \$sub$../../verilog/max6682.v:344$23 (
.A({ 6'b000000, Byte1, Byte0[7:5] }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/max6682.v:345" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(16)
) \$sub$../../verilog/max6682.v:345$24 (
.A(Word0),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.Y(DiffBA)
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(2),
.Y_WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$auto$opt_reduce.cc:130:opt_mux$735 (
.A({ \$techmap\MAX6682_SPI_FSM_1.$procmux$554_CMP , \$techmap\MAX6682_SPI_FSM_1.$procmux$553_CMP }),
.Y(\MAX6682_SPI_FSM_1.SPI_FSM_Done )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(4),
.Y_WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$auto$opt_reduce.cc:130:opt_mux$737 (
.A({ \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 , \$techmap\MAX6682_SPI_FSM_1.$procmux$560_CMP , \$techmap\MAX6682_SPI_FSM_1.$procmux$559_CMP , \$techmap\MAX6682_SPI_FSM_1.$procmux$558_CMP }),
.Y(\$techmap\MAX6682_SPI_FSM_1.$auto$opt_reduce.cc:126:opt_mux$736 )
);
SPIFSM SPIFSM_1 (
.Reset_n_i(\MAX6682_SPI_FSM_1.Reset_n_i ),
.Clk_i(\MAX6682_SPI_FSM_1.Clk_i ),
.In0_i(\MAX6682_SPI_FSM_1.SPI_FSM_Start ),
.In1_i(\MAX6682_SPI_FSM_1.SPI_Transmission_i ),
.In2_i(1'b0),
.In3_i(1'b0),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\MAX6682_SPI_FSM_1.$procmux$553_CMP ),
.Out1_o(\$techmap\MAX6682_SPI_FSM_1.$procmux$554_CMP ),
.Out2_o(\$techmap\MAX6682_SPI_FSM_1.$procmux$558_CMP ),
.Out3_o(\$techmap\MAX6682_SPI_FSM_1.$procmux$559_CMP ),
.Out4_o(\$techmap\MAX6682_SPI_FSM_1.$procmux$560_CMP ),
.Out5_o(\$techmap\MAX6682_SPI_FSM_1.$procmux$563_CMP ),
.Out6_o(\MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ),
.Out7_o(SPIFSM_1_Out7_s),
.Out8_o(SPIFSM_1_Out8_s),
.Out9_o(SPIFSM_1_Out9_s),
.Out10_o(SPIFSM_1_Out10_s),
.Out11_o(SPIFSM_1_Out11_s),
.Out12_o(SPIFSM_1_Out12_s),
.Out13_o(SPIFSM_1_Out13_s),
.Out14_o(SPIFSM_1_Out14_s),
.CfgMode_i(SPIFSM_1_CfgMode_s),
.CfgClk_i(SPIFSM_1_CfgClk_s),
.CfgShift_i(SPIFSM_1_CfgShift_s),
.CfgDataIn_i(SPIFSM_1_CfgDataIn_s),
.CfgDataOut_o(SPIFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/max6682.v:111" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\MAX6682_SPI_FSM_1.$procdff$729 (
.ARST(\MAX6682_SPI_FSM_1.Reset_n_i ),
.CLK(\MAX6682_SPI_FSM_1.Clk_i ),
.D(\$techmap\MAX6682_SPI_FSM_1.$0\Byte0[7:0] ),
.Q(\MAX6682_SPI_FSM_1.Byte0 )
);
(* src = "../../verilog/max6682.v:111" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\MAX6682_SPI_FSM_1.$procdff$730 (
.ARST(\MAX6682_SPI_FSM_1.Reset_n_i ),
.CLK(\MAX6682_SPI_FSM_1.Clk_i ),
.D(\$techmap\MAX6682_SPI_FSM_1.$0\Byte1[7:0] ),
.Q(\MAX6682_SPI_FSM_1.Byte1 )
);
\$mux #(
.WIDTH(8)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$458 (
.A(\MAX6682_SPI_FSM_1.Byte0 ),
.B(\MAX6682_SPI_FSM_1.SPI_Data_i ),
.S(\MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ),
.Y(\$techmap\MAX6682_SPI_FSM_1.$0\Byte0[7:0] )
);
\$mux #(
.WIDTH(8)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$465 (
.A(\MAX6682_SPI_FSM_1.Byte1 ),
.B(\MAX6682_SPI_FSM_1.SPI_Data_i ),
.S(\MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ),
.Y(\$techmap\MAX6682_SPI_FSM_1.$0\Byte1[7:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$583 (
.A(\$techmap\MAX6682_SPI_FSM_1.$procmux$558_CMP ),
.B(\$techmap\MAX6682_SPI_FSM_1.$2\SPI_FSM_Wr1[0:0] ),
.Y(\MAX6682_SPI_FSM_1.SPI_FSM_Wr1 )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$593 (
.A(1'b0),
.B({ \$techmap\MAX6682_SPI_FSM_1.$2\SPI_FSM_Wr1[0:0] , 1'b1 }),
.S({ \$techmap\MAX6682_SPI_FSM_1.$procmux$558_CMP , \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 }),
.Y(\MAX6682_SPI_FSM_1.SPI_ReadNext_o )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$606 (
.A(1'b1),
.B({ \$techmap\MAX6682_SPI_FSM_1.$2\MAX6682CS_n_o[0:0] , 1'b0 }),
.S({ \$techmap\MAX6682_SPI_FSM_1.$procmux$563_CMP , \$techmap\MAX6682_SPI_FSM_1.$auto$opt_reduce.cc:126:opt_mux$736 }),
.Y(\MAX6682_SPI_FSM_1.MAX6682CS_n_o )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$637 (
.A(1'b0),
.B({ \MAX6682_SPI_FSM_1.SPI_FSM_Start , 1'b1 }),
.S({ \$techmap\MAX6682_SPI_FSM_1.$procmux$563_CMP , \$techmap\MAX6682_SPI_FSM_1.$procmux$560_CMP }),
.Y(\MAX6682_SPI_FSM_1.SPI_Write_o )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$666 (
.A(\MAX6682_SPI_FSM_1.SPI_FSM_Start ),
.Y(\$techmap\MAX6682_SPI_FSM_1.$2\MAX6682CS_n_o[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\MAX6682_SPI_FSM_1.$procmux$703 (
.A(\MAX6682_SPI_FSM_1.SPI_Transmission_i ),
.Y(\$techmap\MAX6682_SPI_FSM_1.$2\SPI_FSM_Wr1[0:0] )
);
(* src = "../../verilog/max6682.v:346" *)
\$mux #(
.WIDTH(16)
) \$ternary$../../verilog/max6682.v:346$25 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SensorValue = { 5'b00000, Byte1, Byte0[7:5] };
assign SensorValue_o = Word0;
assign Byte0 = \MAX6682_SPI_FSM_1.Byte0 ;
assign Byte1 = \MAX6682_SPI_FSM_1.Byte1 ;
assign \MAX6682_SPI_FSM_1.Clk_i = Clk_i;
assign MAX6682CS_n_o = \MAX6682_SPI_FSM_1.MAX6682CS_n_o ;
assign \MAX6682_SPI_FSM_1.Reset_n_i = Reset_n_i;
assign \MAX6682_SPI_FSM_1.SPI_Data_i = SPI_Data_i;
assign SPI_FSM_Done = \MAX6682_SPI_FSM_1.SPI_FSM_Done ;
assign \MAX6682_SPI_FSM_1.SPI_FSM_Start = SPI_FSM_Start;
assign SPI_ReadNext_o = \MAX6682_SPI_FSM_1.SPI_ReadNext_o ;
assign \MAX6682_SPI_FSM_1.SPI_Transmission_i = SPI_Transmission_i;
assign SPI_Write_o = \MAX6682_SPI_FSM_1.SPI_Write_o ;
assign SPIFSM_1_CfgMode_s = 1'b0;
assign SPIFSM_1_CfgClk_s = 1'b0;
assign SPIFSM_1_CfgShift_s = 1'b0;
assign SPIFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule |
module rca110_memory(i_clk, i_rst, mm_adr, mm_we, mm_idat, mm_odat);
input i_clk;
input i_rst;
input [11:0] mm_adr;
input mm_we;
output reg [23:0] mm_idat;
input [23:0] mm_odat;
reg [24:0] m_memory [4095:0];
integer i;
always @(posedge i_clk) begin
if(i_rst) begin
mm_idat <= 0;
for(i = 0; i < 4095; i = i + 1)
m_memory[i] = 0;
m_memory[64] = {9'b011010000, 3'b010, 12'b000000000010}; // STP
m_memory[65] = {9'o400, 15'h0};
m_memory[66] = {12'b0, 12'b100000000000};
end
else begin
if(mm_we)
m_memory[mm_adr] <= mm_odat;
else
mm_idat <= m_memory[mm_adr];
end
end
endmodule |
module rca110(i_clk, i_rst,
mm_adr, mm_we, mm_idat, mm_odat);
input i_clk;
input i_rst;
output reg [11:0] mm_adr;
output reg mm_we;
input [23:0] mm_idat;
output reg [23:0] mm_odat;
// Instruction decode
reg [23:0] r_inst;
wire [8:0] w_inst_OP;
wire [2:0] w_inst_T;
wire [10:0] w_inst_Y;
assign w_inst_OP = r_inst[23:15];
assign w_inst_T = r_inst[14:12];
assign w_inst_Y = r_inst[11:0];
// Registers
reg [23:0] r_L;
reg [23:0] r_R;
reg [11:0] r_PC;
reg [7:0] r_JR;
reg [7:0] r_JS;
reg [11:0] r_XR [6:0];
integer i;
wire w_do_Y_offset;
reg [11:0] w_Y_wrap;
// assign w_Y_wrap = (|w_inst_T & w_do_Y_offset) ?
// w_inst_Y - m_XR[w_inst_T-1] : w_inst_Y;
assign w_do_Y_offset = (w_inst_OP == 9'o400) ? 1'b0 : 1'b1;
wire [23:0] w_store1_data;
assign w_store1_data = (w_inst_OP == `RCA110_OP_STZ) ? 24'h00 :
(w_inst_OP == `RCA110_OP_STL) ? r_L :
(w_inst_OP == `RCA110_OP_STR) ? r_R : 24'h00;
reg [2:0] r_state;
reg [2:0] r_state_next;
localparam SFETCH1 = 3'b000; // Fetch I
localparam SFETCH2 = 3'b001; // Decode
localparam SEXEC1 = 3'b010; // Execute single operations
localparam SEXEC2 = 3'b011; // Memory Writeback
// Index register update
always @(posedge i_clk) begin
if(i_rst) begin
for(i = 0; i < 7; i = i + 1)
r_XR[i] <= 0;
end
else begin
if(mm_we && (mm_adr >= 12'o0001 && mm_adr <= 12'o0007)) begin
$display("r_XR[%d] <= %h", mm_adr, mm_odat);
r_XR[mm_adr[2:0] - 1] = mm_odat;
end
end
end
always @(posedge i_clk) begin
if(i_rst) begin
mm_adr <= 0;
mm_we <= 0;
mm_odat <= 0;
r_L <= 0;
r_R <= 0;
r_PC <= 64;
r_JR <= 0;
r_JS <= 0;
r_state <= SFETCH1;
r_state_next <= SFETCH1;
r_inst <= 0;
end
else begin
case(r_state)
SFETCH1:
begin
mm_adr <= r_PC;
mm_we <= 0;
mm_odat <= 0;
r_state <= SFETCH2;
r_PC = r_PC+1;
end
SFETCH2:
begin
r_inst <= mm_idat;
r_state <= SEXEC1;
if(|mm_idat[14:12])
w_Y_wrap <= mm_idat[11:0] - r_XR[mm_idat[14:12]-1];
else
w_Y_wrap <= mm_idat[11:0];
end
SEXEC1:
begin
r_state = SFETCH1;
case(w_inst_OP)
// Load & Store
`RCA110_OP_STP:
begin
mm_adr <= w_Y_wrap;
mm_we <= 1'b1;
mm_odat[11:0] <= ~(r_PC-1);
mm_odat[23:12] <= 0;
end
`RCA110_OP_LDZ:
begin
r_L <= 0;
end
`RCA110_OP_LDL,
`RCA110_OP_LDR,
`RCA110_OP_LDB,
`RCA110_OP_ADD,
`RCA110_OP_LDA:
begin
mm_adr <= w_Y_wrap;
mm_we <= 0;
r_state = SEXEC2;
r_state_next = SEXEC2; // Used as flag
end
`RCA110_OP_STZ,
`RCA110_OP_STL,
`RCA110_OP_STR:
begin
mm_adr <= w_Y_wrap;
mm_odat <= w_store1_data;
mm_we <= 1;
r_state <= SFETCH1;
end
`RCA110_OP_STB:
begin
mm_adr <= w_Y_wrap;
mm_odat <= r_R;
mm_we <= 1;
r_state <= SEXEC2;
end
`RCA110_OP_STA:
// First fetch than save since it only affects bit 11:0
begin
mm_adr <= w_Y_wrap;
r_state <= SEXEC2;
end
endcase // case (w_inst_OP)
end // case: SEXEC1
SEXEC2:
begin
case(w_inst_OP)
`RCA110_OP_LDL:
begin
r_L <= mm_idat;
end
`RCA110_OP_LDR:
begin
r_R <= mm_idat;
end
`RCA110_OP_LDB:
begin
if(r_state_next == SEXEC2) begin
r_R <= mm_idat;
mm_adr <= w_Y_wrap+1;
r_state_next <= SFETCH1;
end
else begin
r_L <= mm_idat;
r_state <= SFETCH1;
end
end // case: `RCA110_OP_LDB
`RCA110_OP_LDA:
begin
r_L[11:0] <= mm_idat[11:0];
r_state <= SFETCH1;
end
`RCA110_OP_STB:
begin
mm_adr <= w_Y_wrap+1;
mm_odat <= r_L;
r_state <= SFETCH1;
end
`RCA110_OP_STA:
begin
mm_adr <= w_Y_wrap;
mm_odat[23:12] <= mm_idat[23:12];
mm_odat[11:0] <= r_L[11:0];
mm_we <= 1;
end
`RCA110_OP_ADD,
`RCA110_OP_ADR:
begin
r_L = r_L + mm_idat;
mm_odat <= r_L + mm_idat;
mm_we <= 1'b1;
mm_adr <= w_Y_wrap;
end
endcase // case (w_inst_OP)
end
endcase // case (r_state)
end
end
endmodule |
module tb;
reg clk = 0;
reg rst = 1;
wire [11:0] mm_adr;
wire mm_we;
wire [23:0] mm_idat;
wire [23:0] mm_odat;
rca110_memory mem(clk, rst, mm_adr, mm_we, mm_idat, mm_odat);
rca110 cpu(clk, rst,
mm_adr, mm_we, mm_idat, mm_odat);
always #10 clk = ~clk;
always @(posedge clk) begin
rst <= 0;
end
initial begin
$dumpfile("rca110.vcd");
$dumpvars(0, mem);
$dumpvars(0, cpu);
#500 $finish();
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(D,
gpio_io_o,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_t,
bus2ip_rnw_i_reg,
s_axi_aclk,
SS,
bus2ip_rnw,
bus2ip_cs,
E,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
rst_reg);
output [7:0]D;
output [7:0]gpio_io_o;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [7:0]gpio_io_t;
input bus2ip_rnw_i_reg;
input s_axi_aclk;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [0:0]E;
input [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
input [0:0]rst_reg;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [0:0]rst_reg;
wire s_axi_aclk;
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[7]),
.Q(D[7]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[6]),
.Q(D[6]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[5]),
.Q(D[5]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[4]),
.Q(D[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[3]),
.Q(D[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[2]),
.Q(D[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[1]),
.Q(D[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[0]),
.Q(D[0]),
.R(bus2ip_rnw_i_reg));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_aclk,
rst_reg,
Q,
bus2ip_rnw_i_reg,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
s_axi_wdata,
start2_reg,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
input s_axi_aclk;
input rst_reg;
input [2:0]Q;
input bus2ip_rnw_i_reg;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input [15:0]s_axi_wdata;
input start2_reg;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [2:0]Q;
wire bus2ip_rnw_i_reg;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire start2_reg;
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2_reg),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT4 #(
.INIT(16'hFFF7))
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAABAAAA))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(rst_reg),
.I1(Q[1]),
.I2(bus2ip_rnw_i_reg),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(E));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[7]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[15]),
.O(D[7]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[6]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[14]),
.O(D[6]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[5]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[13]),
.O(D[5]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[4]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[12]),
.O(D[4]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[3]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[11]),
.O(D[3]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[5]_i_1
(.I0(s_axi_wdata[2]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[10]),
.O(D[2]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[6]_i_1
(.I0(s_axi_wdata[1]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[9]),
.O(D[1]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[7]_i_1
(.I0(s_axi_wdata[0]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[8]),
.O(D[0]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
\Not_Dual.gpio_OE[0]_i_1
(.I0(rst_reg),
.I1(Q[0]),
.I2(Q[1]),
.I3(bus2ip_rnw_i_reg),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(\Not_Dual.gpio_OE_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_6;
wire AXI_LITE_IPIF_I_n_7;
wire [0:7]DBus_Reg;
wire GPIO_xferAck_i;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_core_1_n_19;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [24:31]ip2bus_data;
wire [24:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_17),
.\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
.Q({ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31:24],s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.D({ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_17),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_19),
.rst_reg(AXI_LITE_IPIF_I_n_7),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_19),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q(Q),
.SR(bus2ip_reset),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(SR,
\Not_Dual.gpio_Data_Out_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output SR;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire SR;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i06_out;
wire clear;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [7:0]s_axi_rdata;
wire \s_axi_rdata_i[7]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_Data_Out_reg[0] ),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(SR),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2_reg(start2));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h10))
bus2ip_rnw_i_i_1
(.I0(state[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_Data_Out_reg[0] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[7]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(p_0_out[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(SR));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_o);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [7:0]gpio_io_o;
wire [7:0]gpio_io_o;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [7:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio_io_o(gpio_io_o),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[7:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module oh_standby #( parameter PD = 5, // cycles to stay awake after "wakeup"
parameter N = 5) // project name
(
input clkin, //clock input
input nreset,//async active low reset
input [N-1:0] wakeup, //wake up event vector
input idle, //core is in idle
output clkout //clock output
);
//Wire declarations
reg [PD-1:0] wakeup_pipe;
reg idle_reg;
wire state_change;
wire clk_en;
wire [N-1:0] wakeup_pulse;
wire wakeup_now;
// Wake up on any external event change
oh_edge2pulse #(.DW(N))
oh_edge2pulse (.out (wakeup_pulse[N-1:0]),
.clk (clkin),
.nreset (nreset),
.in (wakeup[N-1:0]));
assign wakeup_now = |(wakeup_pulse[N-1:0]);
// Stay away for PD cycles
always @ (posedge clkin)
wakeup_pipe[PD-1:0] <= {wakeup_pipe[PD-2:0], wakeup_now};
// Clock enable
assign clk_en = wakeup_now | //immediate wakeup
(|wakeup_pipe[PD-1:0]) | //anything in pipe
~idle; //core not in idle
// Clock gating cell
oh_clockgate oh_clockgate (.eclk(clkout),
.clk(clkin),
.en(clk_en),
.te(1'b0));
endmodule |
module sky130_fd_sc_lp__o2111ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module fifo_36x128 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [35:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [35:0] q;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [35:0] sub_wire3;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [35:0] q = sub_wire3[35:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 36,
scfifo_component.lpm_widthu = 7,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module MEMORYTEST;
reg [15:0] w, a, d;
wire [15:0] out;
Memory m (w, a, d, out);
initial begin
$dumpfile("Memory.vcd");
$dumpvars(0, MEMORYTEST);
$monitor("%t: write:%d, address:%d, data:%d, out = %d",
$time, w, a, d, out);
w = 1; a = 0; d = 5;
#10 w = 1; a = 4; d = 6;
#10 w = 1; a = 3; d = 7;
#10 w = 1; a = 8; d = 8;
#10 w = 0; a = 0; d = 0;
#10 w = 0; a = 1; d = 0;
#10 w = 0; a = 2; d = 0;
#10 w = 0; a = 3; d = 0;
#10 w = 0; a = 4; d = 0;
#10 w = 0; a = 5; d = 0;
#10 w = 0; a = 6; d = 0;
#10 w = 0; a = 7; d = 0;
#10 w = 0; a = 8; d = 0;
#10 w = 0; a = 9; d = 0;
#10 w = 1; a = 4; d = 9;
#10 w = 1; a = 5; d = 9;
#10 w = 0; a = 0; d = 0;
#10 w = 0; a = 1; d = 0;
#10 w = 0; a = 2; d = 0;
#10 w = 0; a = 3; d = 0;
#10 w = 0; a = 4; d = 0;
#10 w = 0; a = 5; d = 0;
#10 w = 0; a = 6; d = 0;
#10 w = 0; a = 7; d = 0;
#10 w = 0; a = 8; d = 0;
#10 w = 0; a = 9; d = 0;
#10 $finish;
end
endmodule |
module sky130_fd_sc_lp__a32o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__a32o_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule |
module sky130_fd_sc_hvl__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule |
module spi_data_reader
(
input clk,
input calib_done,
input sclk_posedge,
input sclk_negedge,
input [6:0] block_addr,
input en,
input in,
output reg error,
output done,
// Signals for writing to RAM
output reg mem_cmd_en,
output [2:0] mem_cmd_instr,
output [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error
);
// Initialize outputs
initial begin
error = 0;
mem_cmd_en = 0;
mem_wr_en = 0;
end
// Our interface with RAM is write-only, so always give the
// write command (000)
assign mem_cmd_instr = 3'b000;
// We always want to write 128-byte blocks to RAM, so always
// use a burst length of 32 32-bit words
assign mem_cmd_bl = 6'b011111;
// We also always want to write 32-bit words, so don't mask
// any bytes
assign mem_wr_mask = 4'b0000;
// Keep track of which bit we are on, so that we always
// start at bit 7 for synchonous byte-oriented communication
reg [2:0] bit_counter = 7;
always @ (posedge clk) begin
if (sclk_negedge) begin
bit_counter <= bit_counter - 1;
end
end
// Keep track of the current byte. Once 8 bits have been read in,
// the valid flag goes high for one cycle
reg [7:0] cur_byte = 8'hFF;
reg cur_byte_valid = 0;
always @ (posedge clk) begin
cur_byte_valid <= 0;
if (sclk_posedge) begin
cur_byte[bit_counter] <= in;
if (0 == bit_counter) begin
cur_byte_valid <= 1;
end
end
end
// State machine logic
localparam STATE_IDLE = 0;
localparam STATE_TOKEN = 1;
localparam STATE_BLOCK = 2;
localparam STATE_CRC = 3;
localparam STATE_FLUSH = 4;
localparam STATE_ERROR = 5;
reg [2:0] state = STATE_IDLE;
reg [8:0] byte_counter = 0;
reg crc_counter = 0;
reg [6:0] block_addr_reg = 0;
assign done = (STATE_IDLE == state) && !en;
always @ (posedge clk) begin
// Default to disabled signals
mem_cmd_en <= 0;
mem_wr_en <= 0;
case (state)
// Wait here until we get the enabled signal
STATE_IDLE: begin
if (en) begin
state <= STATE_TOKEN;
byte_counter <= 0;
crc_counter <= 0;
block_addr_reg <= block_addr;
end
end
// Wait until we see 0xFE to start the data, or an error token
// (error tokens start with 0b000)
STATE_TOKEN: begin
if (cur_byte_valid) begin
if (8'hFE == cur_byte) begin
state <= STATE_BLOCK;
end else if (3'b000 == cur_byte[7:5]) begin
state <= STATE_ERROR;
end
end
end
// Consume the data block and store it in RAM
STATE_BLOCK: begin
if (cur_byte_valid) begin
mem_wr_data <= { mem_wr_data[23:0], cur_byte };
// Check if we have read a 4-byte chunk
if (3 == byte_counter[1:0]) begin
mem_wr_en <= 1;
end
// Check if we have read 128 bytes and are ready to write
// to RAM
if (127 == byte_counter[6:0]) begin
mem_cmd_en <= 1;
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, block_addr_reg,
byte_counter[8:7], 7'b0 };
end
// Increment the byte counter, or move onto the next state if
// we've read all 512 bytes
if (511 == byte_counter) begin
state <= STATE_CRC;
end else begin
byte_counter <= byte_counter + 1;
end
end
end
// Consume the 2-byte CRC, but don't do any verification
STATE_CRC: begin
if (cur_byte_valid) begin
if (crc_counter) begin
state <= STATE_FLUSH;
end
crc_counter <= ~crc_counter;
end
end
// Wait until the write FIFO is empty
STATE_FLUSH: begin
if (mem_wr_empty) begin
state <= STATE_IDLE;
end
end
// An error occurred - no recovery mechanism right now.
STATE_ERROR: begin
error <= 1;
end
endcase
// If we have a memory write error or underrun, go to the error state
if (calib_done && (mem_wr_error || mem_wr_underrun)) begin
state <= STATE_ERROR;
end
end
endmodule |
module sky130_fd_sc_lp__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module cyclone2_dmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule |
module sky130_fd_sc_lp__lsbuf (
X ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, DESTPWR, VGND);
endmodule |
module sky130_fd_sc_ls__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module TX_BITSLICE_TRI #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer DATA_WIDTH = 8,
parameter DELAY_FORMAT = "TIME",
parameter DELAY_TYPE = "FIXED",
parameter integer DELAY_VALUE = 0,
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter NATIVE_ODELAY_BYPASS = "FALSE",
parameter OUTPUT_PHASE_90 = "FALSE",
parameter real REFCLK_FREQUENCY = 300.0,
parameter SIM_DEVICE = "ULTRASCALE",
parameter real SIM_VERSION = 2.0,
parameter UPDATE_MODE = "ASYNC"
)(
output [39:0] BIT_CTRL_OUT,
output [8:0] CNTVALUEOUT,
output TRI_OUT,
input [39:0] BIT_CTRL_IN,
input CE,
input CLK,
input [8:0] CNTVALUEIN,
input EN_VTC,
input INC,
input LOAD,
input RST,
input RST_DLY
);
// define constants
localparam MODULE_NAME = "TX_BITSLICE_TRI";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "TX_BITSLICE_TRI_dr.v"
`else
localparam [31:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [40:1] DELAY_FORMAT_REG = DELAY_FORMAT;
localparam [64:1] DELAY_TYPE_REG = DELAY_TYPE;
localparam [31:0] DELAY_VALUE_REG = DELAY_VALUE;
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_DLY_INVERTED_REG = IS_RST_DLY_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [40:1] NATIVE_ODELAY_BYPASS_REG = NATIVE_ODELAY_BYPASS;
localparam [40:1] OUTPUT_PHASE_90_REG = OUTPUT_PHASE_90;
localparam real REFCLK_FREQUENCY_REG = REFCLK_FREQUENCY;
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam real SIM_VERSION_REG = SIM_VERSION;
localparam [48:1] UPDATE_MODE_REG = UPDATE_MODE;
`endif
localparam [0:0] DC_ADJ_EN_REG = 1'b0;
localparam [2:0] FDLY_REG = 3'b010;
localparam [2:0] SPARE_REG = 3'b000;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_DLY_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire [63:0] REFCLK_FREQUENCY_BIN;
wire [63:0] SIM_VERSION_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire CDATAOUT_out;
wire TRI_OUT_out;
wire [39:0] BIT_CTRL_OUT_out;
wire [8:0] CNTVALUEOUT_out;
wire TRI_OUT_delay;
wire [39:0] BIT_CTRL_OUT_delay;
wire [8:0] CNTVALUEOUT_delay;
wire CDATAIN0_in;
wire CDATAIN1_in;
wire CE_in;
wire CLK_in;
wire EN_VTC_in;
wire INC_in;
wire LOAD_in;
wire OFD_CE_in;
wire RST_DLY_in;
wire RST_in;
wire [39:0] BIT_CTRL_IN_in;
wire [8:0] CNTVALUEIN_in;
wire CE_delay;
wire CLK_delay;
wire EN_VTC_delay;
wire INC_delay;
wire LOAD_delay;
wire RST_DLY_delay;
wire RST_delay;
wire [39:0] BIT_CTRL_IN_delay;
wire [8:0] CNTVALUEIN_delay;
assign #(out_delay) BIT_CTRL_OUT = BIT_CTRL_OUT_delay;
assign #(out_delay) CNTVALUEOUT = CNTVALUEOUT_delay;
assign #(out_delay) TRI_OUT = TRI_OUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLK_delay = CLK;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) CNTVALUEIN_delay = CNTVALUEIN;
assign #(in_delay) INC_delay = INC;
assign #(in_delay) LOAD_delay = LOAD;
`endif
// inputs with no timing checks
assign #(in_delay) BIT_CTRL_IN_delay = BIT_CTRL_IN;
assign #(in_delay) EN_VTC_delay = EN_VTC;
assign #(in_delay) RST_DLY_delay = RST_DLY;
assign #(in_delay) RST_delay = RST;
assign BIT_CTRL_OUT_delay = BIT_CTRL_OUT_out;
assign CNTVALUEOUT_delay = CNTVALUEOUT_out;
assign TRI_OUT_delay = TRI_OUT_out;
assign BIT_CTRL_IN_in = BIT_CTRL_IN_delay;
assign CE_in = CE_delay;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign CNTVALUEIN_in = CNTVALUEIN_delay;
assign EN_VTC_in = EN_VTC_delay;
assign INC_in = INC_delay;
assign LOAD_in = LOAD_delay;
assign RST_DLY_in = RST_DLY_delay ^ IS_RST_DLY_INVERTED_BIN;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_DLY_INVERTED_BIN = IS_RST_DLY_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign REFCLK_FREQUENCY_BIN = REFCLK_FREQUENCY_REG * 1000;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 4))) begin
$display("Error: [Unisim %s-101] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DELAY_FORMAT_REG != "TIME") &&
(DELAY_FORMAT_REG != "COUNT"))) begin
$display("Error: [Unisim %s-103] DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DELAY_TYPE_REG != "FIXED") &&
(DELAY_TYPE_REG != "VAR_LOAD") &&
(DELAY_TYPE_REG != "VARIABLE"))) begin
$display("Error: [Unisim %s-104] DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG == "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1250)))) begin
$display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG != "ULTRASCALE" && ((DELAY_VALUE_REG < 0) || (DELAY_VALUE_REG > 1100)))) begin
$display("Error: [Unisim %s-105] DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NATIVE_ODELAY_BYPASS_REG != "FALSE") &&
(NATIVE_ODELAY_BYPASS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] NATIVE_ODELAY_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, NATIVE_ODELAY_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OUTPUT_PHASE_90_REG != "FALSE") &&
(OUTPUT_PHASE_90_REG != "TRUE"))) begin
$display("Error: [Unisim %s-112] OUTPUT_PHASE_90 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OUTPUT_PHASE_90_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 300.0 || REFCLK_FREQUENCY_REG > 2667.0))) begin
$display("Error: [Unisim %s-113] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (REFCLK_FREQUENCY_REG < 200.0 || REFCLK_FREQUENCY_REG > 2400.0))) begin
$display("Error: [Unisim %s-113] REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-114] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-115] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((UPDATE_MODE_REG != "ASYNC") &&
(UPDATE_MODE_REG != "MANUAL") &&
(UPDATE_MODE_REG != "SYNC"))) begin
$display("Error: [Unisim %s-116] UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, UPDATE_MODE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign CDATAIN0_in = 1'b1; // tie off
assign CDATAIN1_in = 1'b1; // tie off
assign OFD_CE_in = 1'b0; // tie off
generate
if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1
SIP_TX_BITSLICE_TRI_D1 SIP_TX_BITSLICE_TRI_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DELAY_FORMAT (DELAY_FORMAT_REG),
.DELAY_TYPE (DELAY_TYPE_REG),
.DELAY_VALUE (DELAY_VALUE_REG),
.FDLY (FDLY_REG),
.SPARE (SPARE_REG),
.INIT (INIT_REG),
.NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG),
.OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN),
.UPDATE_MODE (UPDATE_MODE_REG),
.BIT_CTRL_OUT (BIT_CTRL_OUT_out),
.CDATAOUT (CDATAOUT_out),
.CNTVALUEOUT (CNTVALUEOUT_out),
.TRI_OUT (TRI_OUT_out),
.BIT_CTRL_IN (BIT_CTRL_IN_in),
.CDATAIN0 (CDATAIN0_in),
.CDATAIN1 (CDATAIN1_in),
.CE (CE_in),
.CLK (CLK_in),
.CNTVALUEIN (CNTVALUEIN_in),
.EN_VTC (EN_VTC_in),
.INC (INC_in),
.LOAD (LOAD_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.RST_DLY (RST_DLY_in),
.GSR (glblGSR)
);
end
else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1
SIP_TX_BITSLICE_TRI_K2 SIP_TX_BITSLICE_TRI_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.DC_ADJ_EN (DC_ADJ_EN_REG),
.DELAY_FORMAT (DELAY_FORMAT_REG),
.DELAY_TYPE (DELAY_TYPE_REG),
.DELAY_VALUE (DELAY_VALUE_REG),
.FDLY (FDLY_REG),
.INIT (INIT_REG),
.NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG),
.OUTPUT_PHASE_90 (OUTPUT_PHASE_90_REG),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY_BIN),
.SIM_VERSION (SIM_VERSION_BIN),
.UPDATE_MODE (UPDATE_MODE_REG),
.BIT_CTRL_OUT (BIT_CTRL_OUT_out),
.CDATAOUT (CDATAOUT_out),
.CNTVALUEOUT (CNTVALUEOUT_out),
.TRI_OUT (TRI_OUT_out),
.BIT_CTRL_IN (BIT_CTRL_IN_in),
.CDATAIN0 (CDATAIN0_in),
.CDATAIN1 (CDATAIN1_in),
.CE (CE_in),
.CLK (CLK_in),
.CNTVALUEIN (CNTVALUEIN_in),
.EN_VTC (EN_VTC_in),
.INC (INC_in),
.LOAD (LOAD_in),
.OFD_CE (OFD_CE_in),
.RST (RST_in),
.RST_DLY (RST_DLY_in),
.GSR (glblGSR)
);
end
endgenerate
`ifdef XIL_TIMING
reg notifier;
wire clk_en_n;
wire clk_en_p;
assign clk_en_n = IS_CLK_INVERTED_BIN;
assign clk_en_p = ~IS_CLK_INVERTED_BIN;
`endif
specify
(CLK => CNTVALUEOUT[0]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[1]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[2]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[3]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[4]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[5]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[6]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[7]) = (100:100:100, 100:100:100);
(CLK => CNTVALUEOUT[8]) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay);
$setuphold (negedge CLK, negedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[0]);
$setuphold (negedge CLK, negedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[1]);
$setuphold (negedge CLK, negedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[2]);
$setuphold (negedge CLK, negedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[3]);
$setuphold (negedge CLK, negedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[4]);
$setuphold (negedge CLK, negedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[5]);
$setuphold (negedge CLK, negedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[6]);
$setuphold (negedge CLK, negedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[7]);
$setuphold (negedge CLK, negedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[8]);
$setuphold (negedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay);
$setuphold (negedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CE_delay);
$setuphold (negedge CLK, posedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[0]);
$setuphold (negedge CLK, posedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[1]);
$setuphold (negedge CLK, posedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[2]);
$setuphold (negedge CLK, posedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[3]);
$setuphold (negedge CLK, posedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[4]);
$setuphold (negedge CLK, posedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[5]);
$setuphold (negedge CLK, posedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[6]);
$setuphold (negedge CLK, posedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[7]);
$setuphold (negedge CLK, posedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CNTVALUEIN_delay[8]);
$setuphold (negedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INC_delay);
$setuphold (negedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay);
$setuphold (posedge CLK, negedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[0]);
$setuphold (posedge CLK, negedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[1]);
$setuphold (posedge CLK, negedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[2]);
$setuphold (posedge CLK, negedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[3]);
$setuphold (posedge CLK, negedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[4]);
$setuphold (posedge CLK, negedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[5]);
$setuphold (posedge CLK, negedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[6]);
$setuphold (posedge CLK, negedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[7]);
$setuphold (posedge CLK, negedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[8]);
$setuphold (posedge CLK, negedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay);
$setuphold (posedge CLK, negedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CE_delay);
$setuphold (posedge CLK, posedge CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[0]);
$setuphold (posedge CLK, posedge CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[1]);
$setuphold (posedge CLK, posedge CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[2]);
$setuphold (posedge CLK, posedge CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[3]);
$setuphold (posedge CLK, posedge CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[4]);
$setuphold (posedge CLK, posedge CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[5]);
$setuphold (posedge CLK, posedge CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[6]);
$setuphold (posedge CLK, posedge CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[7]);
$setuphold (posedge CLK, posedge CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CNTVALUEIN_delay[8]);
$setuphold (posedge CLK, posedge INC, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INC_delay);
$setuphold (posedge CLK, posedge LOAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, LOAD_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module assertionFabric(
clk, rst, enable,
bakedInAssertions,
routingInput,
routingBlock_0_inputSelect,
routingBlock_1_inputSelect,
routingBlock_2_inputSelect,
routingBlock_3_inputSelect,
routingBlock_4_inputSelect,
routingBlock_5_inputSelect,
routingBlock_6_inputSelect,
routingBlock_7_inputSelect,
routingBlock_8_inputSelect,
routingBlock_9_inputSelect,
routingBlock_10_inputSelect,
routingBlock_11_inputSelect,
routingBlock_12_inputSelect,
routingBlock_13_inputSelect,
routingBlock_14_inputSelect,
routingBlock_15_inputSelect,
routingBlock_16_inputSelect,
routingBlock_17_inputSelect,
routingBlock_18_inputSelect,
routingBlock_19_inputSelect,
logicBlock_0_maskA,
logicBlock_0_maskB,
logicBlock_0_constant,
logicBlock_0_opBMux,
logicBlock_0_resultMux,
logicBlock_1_maskA,
logicBlock_1_maskB,
logicBlock_1_constant,
logicBlock_1_opBMux,
logicBlock_1_resultMux,
logicBlock_2_maskA,
logicBlock_2_maskB,
logicBlock_2_constant,
logicBlock_2_opBMux,
logicBlock_2_resultMux,
logicBlock_3_maskA,
logicBlock_3_maskB,
logicBlock_3_constant,
logicBlock_3_opBMux,
logicBlock_3_resultMux,
logicBlock_4_maskA,
logicBlock_4_maskB,
logicBlock_4_constant,
logicBlock_4_opBMux,
logicBlock_4_resultMux,
logicBlock_5_maskA,
logicBlock_5_maskB,
logicBlock_5_constant,
logicBlock_5_opBMux,
logicBlock_5_resultMux,
logicBlock_6_maskA,
logicBlock_6_maskB,
logicBlock_6_constant,
logicBlock_6_opBMux,
logicBlock_6_resultMux,
logicBlock_7_maskA,
logicBlock_7_maskB,
logicBlock_7_constant,
logicBlock_7_opBMux,
logicBlock_7_resultMux,
logicBlock_8_maskA,
logicBlock_8_maskB,
logicBlock_8_constant,
logicBlock_8_opBMux,
logicBlock_8_resultMux,
logicBlock_9_maskA,
logicBlock_9_maskB,
logicBlock_9_constant,
logicBlock_9_opBMux,
logicBlock_9_resultMux,
assertionBlock_0_num_cks,
assertionBlock_0_select,
assertionBlock_0_res_sel,
assertionBlock_1_num_cks,
assertionBlock_1_select,
assertionBlock_1_res_sel,
assertionBlock_2_num_cks,
assertionBlock_2_select,
assertionBlock_2_res_sel,
assertionBlock_3_num_cks,
assertionBlock_3_select,
assertionBlock_3_res_sel,
assertionBlock_4_num_cks,
assertionBlock_4_select,
assertionBlock_4_res_sel,
assertionViolated,
assertionsViolated
);
input clk;
input rst;
input enable;
input [31:0] bakedInAssertions;
input [`ROUTING_INPUT_BITS-1:0] routingInput;
input [4:0] routingBlock_0_inputSelect;
input [4:0] routingBlock_1_inputSelect;
input [4:0] routingBlock_2_inputSelect;
input [4:0] routingBlock_3_inputSelect;
input [4:0] routingBlock_4_inputSelect;
input [4:0] routingBlock_5_inputSelect;
input [4:0] routingBlock_6_inputSelect;
input [4:0] routingBlock_7_inputSelect;
input [4:0] routingBlock_8_inputSelect;
input [4:0] routingBlock_9_inputSelect;
input [4:0] routingBlock_10_inputSelect;
input [4:0] routingBlock_11_inputSelect;
input [4:0] routingBlock_12_inputSelect;
input [4:0] routingBlock_13_inputSelect;
input [4:0] routingBlock_14_inputSelect;
input [4:0] routingBlock_15_inputSelect;
input [4:0] routingBlock_16_inputSelect;
input [4:0] routingBlock_17_inputSelect;
input [4:0] routingBlock_18_inputSelect;
input [4:0] routingBlock_19_inputSelect;
input [31:0] logicBlock_0_maskA;
input [31:0] logicBlock_0_maskB;
input [31:0] logicBlock_0_constant;
input logicBlock_0_opBMux;
input [2:0] logicBlock_0_resultMux;
input [31:0] logicBlock_1_maskA;
input [31:0] logicBlock_1_maskB;
input [31:0] logicBlock_1_constant;
input logicBlock_1_opBMux;
input [2:0] logicBlock_1_resultMux;
input [31:0] logicBlock_2_maskA;
input [31:0] logicBlock_2_maskB;
input [31:0] logicBlock_2_constant;
input logicBlock_2_opBMux;
input [2:0] logicBlock_2_resultMux;
input [31:0] logicBlock_3_maskA;
input [31:0] logicBlock_3_maskB;
input [31:0] logicBlock_3_constant;
input logicBlock_3_opBMux;
input [2:0] logicBlock_3_resultMux;
input [31:0] logicBlock_4_maskA;
input [31:0] logicBlock_4_maskB;
input [31:0] logicBlock_4_constant;
input logicBlock_4_opBMux;
input [2:0] logicBlock_4_resultMux;
input [31:0] logicBlock_5_maskA;
input [31:0] logicBlock_5_maskB;
input [31:0] logicBlock_5_constant;
input logicBlock_5_opBMux;
input [2:0] logicBlock_5_resultMux;
input [31:0] logicBlock_6_maskA;
input [31:0] logicBlock_6_maskB;
input [31:0] logicBlock_6_constant;
input logicBlock_6_opBMux;
input [2:0] logicBlock_6_resultMux;
input [31:0] logicBlock_7_maskA;
input [31:0] logicBlock_7_maskB;
input [31:0] logicBlock_7_constant;
input logicBlock_7_opBMux;
input [2:0] logicBlock_7_resultMux;
input [31:0] logicBlock_8_maskA;
input [31:0] logicBlock_8_maskB;
input [31:0] logicBlock_8_constant;
input logicBlock_8_opBMux;
input [2:0] logicBlock_8_resultMux;
input [31:0] logicBlock_9_maskA;
input [31:0] logicBlock_9_maskB;
input [31:0] logicBlock_9_constant;
input logicBlock_9_opBMux;
input [2:0] logicBlock_9_resultMux;
input [2:0] assertionBlock_0_num_cks;
input [1:0] assertionBlock_0_select;
input assertionBlock_0_res_sel;
input [2:0] assertionBlock_1_num_cks;
input [1:0] assertionBlock_1_select;
input assertionBlock_1_res_sel;
input [2:0] assertionBlock_2_num_cks;
input [1:0] assertionBlock_2_select;
input assertionBlock_2_res_sel;
input [2:0] assertionBlock_3_num_cks;
input [1:0] assertionBlock_3_select;
input assertionBlock_3_res_sel;
input [2:0] assertionBlock_4_num_cks;
input [1:0] assertionBlock_4_select;
input assertionBlock_4_res_sel;
output assertionViolated;
output [31:0] assertionsViolated;
wire routingBlock_0_configInvalid;
wire [31:0] routingBlock_0_result;
routingBlock routingBlock_0(
.inputState(routingInput),
.inputSelect(routingBlock_0_inputSelect),
.out(routingBlock_0_result),
.configInvalid(routingBlock_0_configInvalid)
);
wire routingBlock_1_configInvalid;
wire [31:0] routingBlock_1_result;
routingBlock routingBlock_1(
.inputState(routingInput),
.inputSelect(routingBlock_1_inputSelect),
.out(routingBlock_1_result),
.configInvalid(routingBlock_1_configInvalid)
);
wire routingBlock_2_configInvalid;
wire [31:0] routingBlock_2_result;
routingBlock routingBlock_2(
.inputState(routingInput),
.inputSelect(routingBlock_2_inputSelect),
.out(routingBlock_2_result),
.configInvalid(routingBlock_2_configInvalid)
);
wire routingBlock_3_configInvalid;
wire [31:0] routingBlock_3_result;
routingBlock routingBlock_3(
.inputState(routingInput),
.inputSelect(routingBlock_3_inputSelect),
.out(routingBlock_3_result),
.configInvalid(routingBlock_3_configInvalid)
);
wire routingBlock_4_configInvalid;
wire [31:0] routingBlock_4_result;
routingBlock routingBlock_4(
.inputState(routingInput),
.inputSelect(routingBlock_4_inputSelect),
.out(routingBlock_4_result),
.configInvalid(routingBlock_4_configInvalid)
);
wire routingBlock_5_configInvalid;
wire [31:0] routingBlock_5_result;
routingBlock routingBlock_5(
.inputState(routingInput),
.inputSelect(routingBlock_5_inputSelect),
.out(routingBlock_5_result),
.configInvalid(routingBlock_5_configInvalid)
);
wire routingBlock_6_configInvalid;
wire [31:0] routingBlock_6_result;
routingBlock routingBlock_6(
.inputState(routingInput),
.inputSelect(routingBlock_6_inputSelect),
.out(routingBlock_6_result),
.configInvalid(routingBlock_6_configInvalid)
);
wire routingBlock_7_configInvalid;
wire [31:0] routingBlock_7_result;
routingBlock routingBlock_7(
.inputState(routingInput),
.inputSelect(routingBlock_7_inputSelect),
.out(routingBlock_7_result),
.configInvalid(routingBlock_7_configInvalid)
);
wire routingBlock_8_configInvalid;
wire [31:0] routingBlock_8_result;
routingBlock routingBlock_8(
.inputState(routingInput),
.inputSelect(routingBlock_8_inputSelect),
.out(routingBlock_8_result),
.configInvalid(routingBlock_8_configInvalid)
);
wire routingBlock_9_configInvalid;
wire [31:0] routingBlock_9_result;
routingBlock routingBlock_9(
.inputState(routingInput),
.inputSelect(routingBlock_9_inputSelect),
.out(routingBlock_9_result),
.configInvalid(routingBlock_9_configInvalid)
);
wire routingBlock_10_configInvalid;
wire [31:0] routingBlock_10_result;
routingBlock routingBlock_10(
.inputState(routingInput),
.inputSelect(routingBlock_10_inputSelect),
.out(routingBlock_10_result),
.configInvalid(routingBlock_10_configInvalid)
);
wire routingBlock_11_configInvalid;
wire [31:0] routingBlock_11_result;
routingBlock routingBlock_11(
.inputState(routingInput),
.inputSelect(routingBlock_11_inputSelect),
.out(routingBlock_11_result),
.configInvalid(routingBlock_11_configInvalid)
);
wire routingBlock_12_configInvalid;
wire [31:0] routingBlock_12_result;
routingBlock routingBlock_12(
.inputState(routingInput),
.inputSelect(routingBlock_12_inputSelect),
.out(routingBlock_12_result),
.configInvalid(routingBlock_12_configInvalid)
);
wire routingBlock_13_configInvalid;
wire [31:0] routingBlock_13_result;
routingBlock routingBlock_13(
.inputState(routingInput),
.inputSelect(routingBlock_13_inputSelect),
.out(routingBlock_13_result),
.configInvalid(routingBlock_13_configInvalid)
);
wire routingBlock_14_configInvalid;
wire [31:0] routingBlock_14_result;
routingBlock routingBlock_14(
.inputState(routingInput),
.inputSelect(routingBlock_14_inputSelect),
.out(routingBlock_14_result),
.configInvalid(routingBlock_14_configInvalid)
);
wire routingBlock_15_configInvalid;
wire [31:0] routingBlock_15_result;
routingBlock routingBlock_15(
.inputState(routingInput),
.inputSelect(routingBlock_15_inputSelect),
.out(routingBlock_15_result),
.configInvalid(routingBlock_15_configInvalid)
);
wire routingBlock_16_configInvalid;
wire [31:0] routingBlock_16_result;
routingBlock routingBlock_16(
.inputState(routingInput),
.inputSelect(routingBlock_16_inputSelect),
.out(routingBlock_16_result),
.configInvalid(routingBlock_16_configInvalid)
);
wire routingBlock_17_configInvalid;
wire [31:0] routingBlock_17_result;
routingBlock routingBlock_17(
.inputState(routingInput),
.inputSelect(routingBlock_17_inputSelect),
.out(routingBlock_17_result),
.configInvalid(routingBlock_17_configInvalid)
);
wire routingBlock_18_configInvalid;
wire [31:0] routingBlock_18_result;
routingBlock routingBlock_18(
.inputState(routingInput),
.inputSelect(routingBlock_18_inputSelect),
.out(routingBlock_18_result),
.configInvalid(routingBlock_18_configInvalid)
);
wire routingBlock_19_configInvalid;
wire [31:0] routingBlock_19_result;
routingBlock routingBlock_19(
.inputState(routingInput),
.inputSelect(routingBlock_19_inputSelect),
.out(routingBlock_19_result),
.configInvalid(routingBlock_19_configInvalid)
);
wire logicBlock_0_configInvalid;
wire logicBlock_0_result;
logicBlock logicBlock_0(
.stateA(routingBlock_0_result),
.maskA(logicBlock_0_maskA),
.stateB(routingBlock_1_result),
.maskB(logicBlock_0_maskB),
.constant(logicBlock_0_constant),
.opBMux(logicBlock_0_opBMux),
.prevConfigInvalid(routingBlock_0_configInvalid | routingBlock_1_configInvalid),
.resultMux(logicBlock_0_resultMux),
.out(logicBlock_0_result),
.configInvalid(logicBlock_0_configInvalid)
);
wire logicBlock_1_configInvalid;
wire logicBlock_1_result;
logicBlock logicBlock_1(
.stateA(routingBlock_2_result),
.maskA(logicBlock_1_maskA),
.stateB(routingBlock_3_result),
.maskB(logicBlock_1_maskB),
.constant(logicBlock_1_constant),
.opBMux(logicBlock_1_opBMux),
.prevConfigInvalid(routingBlock_2_configInvalid | routingBlock_3_configInvalid),
.resultMux(logicBlock_1_resultMux),
.out(logicBlock_1_result),
.configInvalid(logicBlock_1_configInvalid)
);
wire logicBlock_2_configInvalid;
wire logicBlock_2_result;
logicBlock logicBlock_2(
.stateA(routingBlock_4_result),
.maskA(logicBlock_2_maskA),
.stateB(routingBlock_5_result),
.maskB(logicBlock_2_maskB),
.constant(logicBlock_2_constant),
.opBMux(logicBlock_2_opBMux),
.prevConfigInvalid(routingBlock_4_configInvalid | routingBlock_5_configInvalid),
.resultMux(logicBlock_2_resultMux),
.out(logicBlock_2_result),
.configInvalid(logicBlock_2_configInvalid)
);
wire logicBlock_3_configInvalid;
wire logicBlock_3_result;
logicBlock logicBlock_3(
.stateA(routingBlock_6_result),
.maskA(logicBlock_3_maskA),
.stateB(routingBlock_7_result),
.maskB(logicBlock_3_maskB),
.constant(logicBlock_3_constant),
.opBMux(logicBlock_3_opBMux),
.prevConfigInvalid(routingBlock_6_configInvalid | routingBlock_7_configInvalid),
.resultMux(logicBlock_3_resultMux),
.out(logicBlock_3_result),
.configInvalid(logicBlock_3_configInvalid)
);
wire logicBlock_4_configInvalid;
wire logicBlock_4_result;
logicBlock logicBlock_4(
.stateA(routingBlock_8_result),
.maskA(logicBlock_4_maskA),
.stateB(routingBlock_9_result),
.maskB(logicBlock_4_maskB),
.constant(logicBlock_4_constant),
.opBMux(logicBlock_4_opBMux),
.prevConfigInvalid(routingBlock_8_configInvalid | routingBlock_9_configInvalid),
.resultMux(logicBlock_4_resultMux),
.out(logicBlock_4_result),
.configInvalid(logicBlock_4_configInvalid)
);
wire logicBlock_5_configInvalid;
wire logicBlock_5_result;
logicBlock logicBlock_5(
.stateA(routingBlock_10_result),
.maskA(logicBlock_5_maskA),
.stateB(routingBlock_11_result),
.maskB(logicBlock_5_maskB),
.constant(logicBlock_5_constant),
.opBMux(logicBlock_5_opBMux),
.prevConfigInvalid(routingBlock_10_configInvalid | routingBlock_11_configInvalid),
.resultMux(logicBlock_5_resultMux),
.out(logicBlock_5_result),
.configInvalid(logicBlock_5_configInvalid)
);
wire logicBlock_6_configInvalid;
wire logicBlock_6_result;
logicBlock logicBlock_6(
.stateA(routingBlock_12_result),
.maskA(logicBlock_6_maskA),
.stateB(routingBlock_13_result),
.maskB(logicBlock_6_maskB),
.constant(logicBlock_6_constant),
.opBMux(logicBlock_6_opBMux),
.prevConfigInvalid(routingBlock_12_configInvalid | routingBlock_13_configInvalid),
.resultMux(logicBlock_6_resultMux),
.out(logicBlock_6_result),
.configInvalid(logicBlock_6_configInvalid)
);
wire logicBlock_7_configInvalid;
wire logicBlock_7_result;
logicBlock logicBlock_7(
.stateA(routingBlock_14_result),
.maskA(logicBlock_7_maskA),
.stateB(routingBlock_15_result),
.maskB(logicBlock_7_maskB),
.constant(logicBlock_7_constant),
.opBMux(logicBlock_7_opBMux),
.prevConfigInvalid(routingBlock_14_configInvalid | routingBlock_15_configInvalid),
.resultMux(logicBlock_7_resultMux),
.out(logicBlock_7_result),
.configInvalid(logicBlock_7_configInvalid)
);
wire logicBlock_8_configInvalid;
wire logicBlock_8_result;
logicBlock logicBlock_8(
.stateA(routingBlock_16_result),
.maskA(logicBlock_8_maskA),
.stateB(routingBlock_17_result),
.maskB(logicBlock_8_maskB),
.constant(logicBlock_8_constant),
.opBMux(logicBlock_8_opBMux),
.prevConfigInvalid(routingBlock_16_configInvalid | routingBlock_17_configInvalid),
.resultMux(logicBlock_8_resultMux),
.out(logicBlock_8_result),
.configInvalid(logicBlock_8_configInvalid)
);
wire logicBlock_9_configInvalid;
wire logicBlock_9_result;
logicBlock logicBlock_9(
.stateA(routingBlock_18_result),
.maskA(logicBlock_9_maskA),
.stateB(routingBlock_19_result),
.maskB(logicBlock_9_maskB),
.constant(logicBlock_9_constant),
.opBMux(logicBlock_9_opBMux),
.prevConfigInvalid(routingBlock_18_configInvalid | routingBlock_19_configInvalid),
.resultMux(logicBlock_9_resultMux),
.out(logicBlock_9_result),
.configInvalid(logicBlock_9_configInvalid)
);
wire assertionBlock_0_result;
wire assertionBlock_0_result_comb;
wire assertionBlock_0_result_delayed;
wire assertionBlock_0_configInvalid;
ovl_combo_wrapped assertionBlock_0(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(assertionBlock_0_num_cks),
.start_event(logicBlock_0_result),
.test_expr(logicBlock_1_result),
.prevConfigInvalid(logicBlock_0_configInvalid | logicBlock_1_configInvalid),
.select(assertionBlock_0_select),
.out(assertionBlock_0_result_comb),
.out_delayed(assertionBlock_0_result_delayed),
.configInvalid(assertionBlock_0_configInvalid)
);
assign assertionBlock_0_result = assertionBlock_0_res_sel ? assertionBlock_0_result_delayed : assertionBlock_0_result_comb;
wire assertionBlock_1_result;
wire assertionBlock_1_result_comb;
wire assertionBlock_1_result_delayed;
wire assertionBlock_1_configInvalid;
ovl_combo_wrapped assertionBlock_1(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(assertionBlock_1_num_cks),
.start_event(logicBlock_2_result),
.test_expr(logicBlock_3_result),
.prevConfigInvalid(logicBlock_2_configInvalid | logicBlock_3_configInvalid),
.select(assertionBlock_1_select),
.out(assertionBlock_1_result_comb),
.out_delayed(assertionBlock_1_result_delayed),
.configInvalid(assertionBlock_1_configInvalid)
);
assign assertionBlock_1_result = assertionBlock_1_res_sel ? assertionBlock_1_result_delayed : assertionBlock_1_result_comb;
wire assertionBlock_2_result;
wire assertionBlock_2_result_comb;
wire assertionBlock_2_result_delayed;
wire assertionBlock_2_configInvalid;
ovl_combo_wrapped assertionBlock_2(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(assertionBlock_2_num_cks),
.start_event(logicBlock_4_result),
.test_expr(logicBlock_5_result),
.prevConfigInvalid(logicBlock_4_configInvalid | logicBlock_5_configInvalid),
.select(assertionBlock_2_select),
.out(assertionBlock_2_result_comb),
.out_delayed(assertionBlock_2_result_delayed),
.configInvalid(assertionBlock_2_configInvalid)
);
assign assertionBlock_2_result = assertionBlock_2_res_sel ? assertionBlock_2_result_delayed : assertionBlock_2_result_comb;
wire assertionBlock_3_result;
wire assertionBlock_3_result_comb;
wire assertionBlock_3_result_delayed;
wire assertionBlock_3_configInvalid;
ovl_combo_wrapped assertionBlock_3(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(assertionBlock_3_num_cks),
.start_event(logicBlock_6_result),
.test_expr(logicBlock_7_result),
.prevConfigInvalid(logicBlock_6_configInvalid | logicBlock_7_configInvalid),
.select(assertionBlock_3_select),
.out(assertionBlock_3_result_comb),
.out_delayed(assertionBlock_3_result_delayed),
.configInvalid(assertionBlock_3_configInvalid)
);
assign assertionBlock_3_result = assertionBlock_3_res_sel ? assertionBlock_3_result_delayed : assertionBlock_3_result_comb;
wire assertionBlock_4_result;
wire assertionBlock_4_result_comb;
wire assertionBlock_4_result_delayed;
wire assertionBlock_4_configInvalid;
ovl_combo_wrapped assertionBlock_4(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(assertionBlock_4_num_cks),
.start_event(logicBlock_8_result),
.test_expr(logicBlock_9_result),
.prevConfigInvalid(logicBlock_8_configInvalid | logicBlock_9_configInvalid),
.select(assertionBlock_4_select),
.out(assertionBlock_4_result_comb),
.out_delayed(assertionBlock_4_result_delayed),
.configInvalid(assertionBlock_4_configInvalid)
);
assign assertionBlock_4_result = assertionBlock_4_res_sel ? assertionBlock_4_result_delayed : assertionBlock_4_result_comb;
wire anyConfigInvalid =
assertionBlock_0_configInvalid |
assertionBlock_1_configInvalid |
assertionBlock_2_configInvalid |
assertionBlock_3_configInvalid |
assertionBlock_4_configInvalid;
assign assertionsViolated = {
assertionBlock_0_result,
assertionBlock_1_result,
assertionBlock_2_result,
assertionBlock_3_result,
assertionBlock_4_result};
wire mergeBlock_0_0_result;
mergeBlock mergeBlock_0_0(
.assert1(assertionBlock_0_result),
.assert2(assertionBlock_1_result),
.assert3(assertionBlock_2_result),
.assert4(assertionBlock_3_result),
.assert5(assertionBlock_4_result),
.assert6(1'b0),
.out(mergeBlock_0_0_result)
);
assign assertionViolated = mergeBlock_0_0_result & ~anyConfigInvalid;
endmodule |
module
CoreAPB3
#
(
parameter
[
5
:
0
]
APB_DWIDTH
=
32
,
parameter
IADDR_OPTION
=
0
,
parameter
[
0
:
0
]
APBSLOT0ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT1ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT2ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT3ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT4ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT5ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT6ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT7ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT8ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT9ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT10ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT11ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT12ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT13ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT14ENABLE
=
1
,
parameter
[
0
:
0
]
APBSLOT15ENABLE
=
1
,
parameter
[
0
:
0
]
SC_0
=
0
,
parameter
[
0
:
0
]
SC_1
=
0
,
parameter
[
0
:
0
]
SC_2
=
0
,
parameter
[
0
:
0
]
SC_3
=
0
,
parameter
[
0
:
0
]
SC_4
=
0
,
parameter
[
0
:
0
]
SC_5
=
0
,
parameter
[
0
:
0
]
SC_6
=
0
,
parameter
[
0
:
0
]
SC_7
=
0
,
parameter
[
0
:
0
]
SC_8
=
0
,
parameter
[
0
:
0
]
SC_9
=
0
,
parameter
[
0
:
0
]
SC_10
=
0
,
parameter
[
0
:
0
]
SC_11
=
0
,
parameter
[
0
:
0
]
SC_12
=
0
,
parameter
[
0
:
0
]
SC_13
=
0
,
parameter
[
0
:
0
]
SC_14
=
0
,
parameter
[
0
:
0
]
SC_15
=
0
,
parameter
[
5
:
0
]
MADDR_BITS
=
32
,
parameter
[
3
:
0
]
UPR_NIBBLE_POSN
=
7
)
(
input
[
31
:
0
]
IADDR,
input
PRESETN,
input
PCLK,
input
[
31
:
0
]
PADDR,
input
PWRITE,
input
PENABLE,
input
PSEL,
input
[
31
:
0
]
PWDATA,
output
wire
[
31
:
0
]
PRDATA,
output
wire
PREADY,
output
wire
PSLVERR,
output
reg
[
31
:
0
]
PADDRS,
output
wire
PWRITES,
output
wire
PENABLES,
output
wire
[
31
:
0
]
PWDATAS,
output
wire
PSELS0,
output
wire
PSELS1,
output
wire
PSELS2,
output
wire
PSELS3,
output
wire
PSELS4,
output
wire
PSELS5,
output
wire
PSELS6,
output
wire
PSELS7,
output
wire
PSELS8,
output
wire
PSELS9,
output
wire
PSELS10,
output
wire
PSELS11,
output
wire
PSELS12,
output
wire
PSELS13,
output
wire
PSELS14,
output
wire
PSELS15,
output
reg
PSELS16,
input
[
31
:
0
]
PRDATAS0,
input
[
31
:
0
]
PRDATAS1,
input
[
31
:
0
]
PRDATAS2,
input
[
31
:
0
]
PRDATAS3,
input
[
31
:
0
]
PRDATAS4,
input
[
31
:
0
]
PRDATAS5,
input
[
31
:
0
]
PRDATAS6,
input
[
31
:
0
]
PRDATAS7,
input
[
31
:
0
]
PRDATAS8,
input
[
31
:
0
]
PRDATAS9,
input
[
31
:
0
]
PRDATAS10,
input
[
31
:
0
]
PRDATAS11,
input
[
31
:
0
]
PRDATAS12,
input
[
31
:
0
]
PRDATAS13,
input
[
31
:
0
]
PRDATAS14,
input
[
31
:
0
]
PRDATAS15,
input
[
31
:
0
]
PRDATAS16,
input
PREADYS0,
input
PREADYS1,
input
PREADYS2,
input
PREADYS3,
input
PREADYS4,
input
PREADYS5,
input
PREADYS6,
input
PREADYS7,
input
PREADYS8,
input
PREADYS9,
input
PREADYS10,
input
PREADYS11,
input
PREADYS12,
input
PREADYS13,
input
PREADYS14,
input
PREADYS15,
input
PREADYS16,
input
PSLVERRS0,
input
PSLVERRS1,
input
PSLVERRS2,
input
PSLVERRS3,
input
PSLVERRS4,
input
PSLVERRS5,
input
PSLVERRS6,
input
PSLVERRS7,
input
PSLVERRS8,
input
PSLVERRS9,
input
PSLVERRS10,
input
PSLVERRS11,
input
PSLVERRS12,
input
PSLVERRS13,
input
PSLVERRS14,
input
PSLVERRS15,
input
PSLVERRS16
)
;
localparam
CAPB3I1I
=
0
;
localparam
CAPB3l1I
=
1
;
localparam
CAPB3OOl
=
2
;
localparam
CAPB3IOl
=
3
;
localparam
CAPB3lOl
=
4
;
localparam
CAPB3OIl
=
5
;
localparam
CAPB3IIl
=
6
;
localparam
CAPB3lIl
=
7
;
localparam
CAPB3Oll
=
8
;
localparam
CAPB3Ill
=
9
;
localparam
CAPB3lll
=
10
;
localparam
CAPB3O0l
=
11
;
localparam
CAPB3I0l
=
12
;
localparam
CAPB3l0l
=
13
;
localparam
CAPB3O1l
=
14
;
localparam
CAPB3I1l
=
15
;
localparam
CAPB3l1l
=
16
;
localparam
CAPB3OO0
=
17
;
localparam
[
15
:
0
]
CAPB3IO0
=
(
APBSLOT0ENABLE
||
SC_0
||
(
IADDR_OPTION
==
CAPB3OOl
)
)
*
(
2
**
0
)
;
localparam
[
15
:
0
]
CAPB3lO0
=
(
APBSLOT1ENABLE
||
SC_1
||
(
IADDR_OPTION
==
CAPB3IOl
)
)
*
(
2
**
1
)
;
localparam
[
15
:
0
]
CAPB3OI0
=
(
APBSLOT2ENABLE
||
SC_2
||
(
IADDR_OPTION
==
CAPB3lOl
)
)
*
(
2
**
2
)
;
localparam
[
15
:
0
]
CAPB3II0
=
(
APBSLOT3ENABLE
||
SC_3
||
(
IADDR_OPTION
==
CAPB3OIl
)
)
*
(
2
**
3
)
;
localparam
[
15
:
0
]
CAPB3lI0
=
(
APBSLOT4ENABLE
||
SC_4
||
(
IADDR_OPTION
==
CAPB3IIl
)
)
*
(
2
**
4
)
;
localparam
[
15
:
0
]
CAPB3Ol0
=
(
APBSLOT5ENABLE
||
SC_5
||
(
IADDR_OPTION
==
CAPB3lIl
)
)
*
(
2
**
5
)
;
localparam
[
15
:
0
]
CAPB3Il0
=
(
APBSLOT6ENABLE
||
SC_6
||
(
IADDR_OPTION
==
CAPB3Oll
)
)
*
(
2
**
6
)
;
localparam
[
15
:
0
]
CAPB3ll0
=
(
APBSLOT7ENABLE
||
SC_7
||
(
IADDR_OPTION
==
CAPB3Ill
)
)
*
(
2
**
7
)
;
localparam
[
15
:
0
]
CAPB3O00
=
(
APBSLOT8ENABLE
||
SC_8
||
(
IADDR_OPTION
==
CAPB3lll
)
)
*
(
2
**
8
)
;
localparam
[
15
:
0
]
CAPB3I00
=
(
APBSLOT9ENABLE
||
SC_9
||
(
IADDR_OPTION
==
CAPB3O0l
)
)
*
(
2
**
9
)
;
localparam
[
15
:
0
]
CAPB3l00
=
(
APBSLOT10ENABLE
||
SC_10
||
(
IADDR_OPTION
==
CAPB3I0l
)
)
*
(
2
**
10
)
;
localparam
[
15
:
0
]
CAPB3O10
=
(
APBSLOT11ENABLE
||
SC_11
||
(
IADDR_OPTION
==
CAPB3l0l
)
)
*
(
2
**
11
)
;
localparam
[
15
:
0
]
CAPB3I10
=
(
APBSLOT12ENABLE
||
SC_12
||
(
IADDR_OPTION
==
CAPB3O1l
)
)
*
(
2
**
12
)
;
localparam
[
15
:
0
]
CAPB3l10
=
(
APBSLOT13ENABLE
||
SC_13
||
(
IADDR_OPTION
==
CAPB3I1l
)
)
*
(
2
**
13
)
;
localparam
[
15
:
0
]
CAPB3OO1
=
(
APBSLOT14ENABLE
||
SC_14
||
(
IADDR_OPTION
==
CAPB3l1l
)
)
*
(
2
**
14
)
;
localparam
[
15
:
0
]
CAPB3IO1
=
(
APBSLOT15ENABLE
||
SC_15
||
(
IADDR_OPTION
==
CAPB3OO0
)
)
*
(
2
**
15
)
;
localparam
[
15
:
0
]
CAPB3lO1
=
{
SC_15
,
SC_14
,
SC_13
,
SC_12
,
SC_11
,
SC_10
,
SC_9
,
SC_8
,
SC_7
,
SC_6
,
SC_5
,
SC_4
,
SC_3
,
SC_2
,
SC_1
,
SC_0
}
;
localparam
[
15
:
0
]
CAPB3OI1
=
CAPB3lO1
&
{
(
IADDR_OPTION
!=
CAPB3OO0
)
,
(
IADDR_OPTION
!=
CAPB3l1l
)
,
(
IADDR_OPTION
!=
CAPB3I1l
)
,
(
IADDR_OPTION
!=
CAPB3O1l
)
,
(
IADDR_OPTION
!=
CAPB3l0l
)
,
(
IADDR_OPTION
!=
CAPB3I0l
)
,
(
IADDR_OPTION
!=
CAPB3O0l
)
,
(
IADDR_OPTION
!=
CAPB3lll
)
,
(
IADDR_OPTION
!=
CAPB3Ill
)
,
(
IADDR_OPTION
!=
CAPB3Oll
)
,
(
IADDR_OPTION
!=
CAPB3lIl
)
,
(
IADDR_OPTION
!=
CAPB3IIl
)
,
(
IADDR_OPTION
!=
CAPB3OIl
)
,
(
IADDR_OPTION
!=
CAPB3lOl
)
,
(
IADDR_OPTION
!=
CAPB3IOl
)
,
(
IADDR_OPTION
!=
CAPB3OOl
)
}
;
wire
[
31
:
0
]
CAPB3I0I
;
wire
[
31
:
0
]
CAPB3II1
;
wire
[
31
:
0
]
CAPB3lI1
;
wire
[
31
:
0
]
CAPB3Ol1
;
wire
[
31
:
0
]
CAPB3Il1
;
wire
[
31
:
0
]
CAPB3ll1
;
wire
[
31
:
0
]
CAPB3O01
;
wire
[
31
:
0
]
CAPB3I01
;
wire
[
31
:
0
]
CAPB3l01
;
wire
[
31
:
0
]
CAPB3O11
;
wire
[
31
:
0
]
CAPB3I11
;
wire
[
31
:
0
]
CAPB3l11
;
wire
[
31
:
0
]
CAPB3OOOI
;
wire
[
31
:
0
]
CAPB3IOOI
;
wire
[
31
:
0
]
CAPB3lOOI
;
wire
[
31
:
0
]
CAPB3OIOI
;
wire
[
31
:
0
]
CAPB3IIOI
;
wire
[
31
:
0
]
CAPB3lIOI
;
wire
[
15
:
0
]
CAPB3OlOI
;
wire
[
15
:
0
]
CAPB3IlOI
;
reg
[
15
:
0
]
CAPB3llOI
;
reg
[
15
:
0
]
CAPB3O0OI
;
wire
[
3
:
0
]
CAPB3I0OI
;
wire
[
31
:
0
]
CAPB3I
;
wire
[
31
:
0
]
CAPB3l0OI
;
wire
[
31
:
0
]
CAPB3O1OI
;
wire
[
31
:
0
]
CAPB3I1OI
;
wire
CAPB3l1OI
;
wire
CAPB3OOII
;
assign
CAPB3I1OI
=
32
'b
0
;
assign
CAPB3l1OI
=
1
'b
1
;
assign
CAPB3OOII
=
1
'b
0
;
assign
PWRITES
=
PWRITE
;
assign
PENABLES
=
PENABLE
;
assign
PWDATAS
=
PWDATA
[
31
:
0
]
;
assign
CAPB3I0OI
=
PADDR
[
MADDR_BITS
-
1
:
MADDR_BITS
-
4
]
;
always
@(*)
begin
if
(
PSEL
==
1
'b
1
)
begin
case
(
CAPB3I0OI
)
4
'b
0000
:
CAPB3llOI
=
CAPB3IO0
;
4
'b
0001
:
CAPB3llOI
=
CAPB3lO0
;
4
'b
0010
:
CAPB3llOI
=
CAPB3OI0
;
4
'b
0011
:
CAPB3llOI
=
CAPB3II0
;
4
'b
0100
:
CAPB3llOI
=
CAPB3lI0
;
4
'b
0101
:
CAPB3llOI
=
CAPB3Ol0
;
4
'b
0110
:
CAPB3llOI
=
CAPB3Il0
;
4
'b
0111
:
CAPB3llOI
=
CAPB3ll0
;
4
'b
1000
:
CAPB3llOI
=
CAPB3O00
;
4
'b
1001
:
CAPB3llOI
=
CAPB3I00
;
4
'b
1010
:
CAPB3llOI
=
CAPB3l00
;
4
'b
1011
:
CAPB3llOI
=
CAPB3O10
;
4
'b
1100
:
CAPB3llOI
=
CAPB3I10
;
4
'b
1101
:
CAPB3llOI
=
CAPB3l10
;
4
'b
1110
:
CAPB3llOI
=
CAPB3OO1
;
4
'b
1111
:
CAPB3llOI
=
CAPB3IO1
;
default
:
CAPB3llOI
=
16
'b
0000000000000000
;
endcase
CAPB3O0OI
[
15
:
0
]
=
CAPB3llOI
&
~
CAPB3OI1
;
PSELS16
=
|
(
CAPB3llOI
&
CAPB3OI1
)
;
end
else
begin
CAPB3O0OI
=
16
'b
0000000000000000
;
PSELS16
=
1
'b
0
;
end
end
generate
begin
:
CAPB3IOII
if
(
IADDR_OPTION
==
CAPB3OOl
)
assign
CAPB3II1
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT0ENABLE
)
assign
CAPB3II1
[
31
:
0
]
=
PRDATAS0
[
31
:
0
]
;
else
assign
CAPB3II1
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3IOl
)
assign
CAPB3lI1
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT1ENABLE
)
assign
CAPB3lI1
[
31
:
0
]
=
PRDATAS1
[
31
:
0
]
;
else
assign
CAPB3lI1
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3lOl
)
assign
CAPB3Ol1
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT2ENABLE
)
assign
CAPB3Ol1
[
31
:
0
]
=
PRDATAS2
[
31
:
0
]
;
else
assign
CAPB3Ol1
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3OIl
)
assign
CAPB3Il1
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT3ENABLE
)
assign
CAPB3Il1
[
31
:
0
]
=
PRDATAS3
[
31
:
0
]
;
else
assign
CAPB3Il1
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3IIl
)
assign
CAPB3ll1
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT4ENABLE
)
assign
CAPB3ll1
[
31
:
0
]
=
PRDATAS4
[
31
:
0
]
;
else
assign
CAPB3ll1
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3lIl
)
assign
CAPB3O01
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT5ENABLE
)
assign
CAPB3O01
[
31
:
0
]
=
PRDATAS5
[
31
:
0
]
;
else
assign
CAPB3O01
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3Oll
)
assign
CAPB3I01
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT6ENABLE
)
assign
CAPB3I01
[
31
:
0
]
=
PRDATAS6
[
31
:
0
]
;
else
assign
CAPB3I01
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3Ill
)
assign
CAPB3l01
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT7ENABLE
)
assign
CAPB3l01
[
31
:
0
]
=
PRDATAS7
[
31
:
0
]
;
else
assign
CAPB3l01
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3lll
)
assign
CAPB3O11
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT8ENABLE
)
assign
CAPB3O11
[
31
:
0
]
=
PRDATAS8
[
31
:
0
]
;
else
assign
CAPB3O11
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3O0l
)
assign
CAPB3I11
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT9ENABLE
)
assign
CAPB3I11
[
31
:
0
]
=
PRDATAS9
[
31
:
0
]
;
else
assign
CAPB3I11
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3I0l
)
assign
CAPB3l11
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT10ENABLE
)
assign
CAPB3l11
[
31
:
0
]
=
PRDATAS10
[
31
:
0
]
;
else
assign
CAPB3l11
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3l0l
)
assign
CAPB3OOOI
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT11ENABLE
)
assign
CAPB3OOOI
[
31
:
0
]
=
PRDATAS11
[
31
:
0
]
;
else
assign
CAPB3OOOI
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3O1l
)
assign
CAPB3IOOI
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT12ENABLE
)
assign
CAPB3IOOI
[
31
:
0
]
=
PRDATAS12
[
31
:
0
]
;
else
assign
CAPB3IOOI
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3I1l
)
assign
CAPB3lOOI
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT13ENABLE
)
assign
CAPB3lOOI
[
31
:
0
]
=
PRDATAS13
[
31
:
0
]
;
else
assign
CAPB3lOOI
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3l1l
)
assign
CAPB3OIOI
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT14ENABLE
)
assign
CAPB3OIOI
[
31
:
0
]
=
PRDATAS14
[
31
:
0
]
;
else
assign
CAPB3OIOI
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3OO0
)
assign
CAPB3IIOI
[
31
:
0
]
=
CAPB3lIOI
[
31
:
0
]
;
else
if
(
APBSLOT15ENABLE
)
assign
CAPB3IIOI
[
31
:
0
]
=
PRDATAS15
[
31
:
0
]
;
else
assign
CAPB3IIOI
[
31
:
0
]
=
CAPB3I1OI
;
if
(
IADDR_OPTION
==
CAPB3OOl
)
assign
CAPB3OlOI
[
0
]
=
CAPB3l1OI
;
else
if
(
APBSLOT0ENABLE
)
assign
CAPB3OlOI
[
0
]
=
PREADYS0
;
else
assign
CAPB3OlOI
[
0
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3IOl
)
assign
CAPB3OlOI
[
1
]
=
CAPB3l1OI
;
else
if
(
APBSLOT1ENABLE
)
assign
CAPB3OlOI
[
1
]
=
PREADYS1
;
else
assign
CAPB3OlOI
[
1
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3lOl
)
assign
CAPB3OlOI
[
2
]
=
CAPB3l1OI
;
else
if
(
APBSLOT2ENABLE
)
assign
CAPB3OlOI
[
2
]
=
PREADYS2
;
else
assign
CAPB3OlOI
[
2
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3OIl
)
assign
CAPB3OlOI
[
3
]
=
CAPB3l1OI
;
else
if
(
APBSLOT3ENABLE
)
assign
CAPB3OlOI
[
3
]
=
PREADYS3
;
else
assign
CAPB3OlOI
[
3
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3IIl
)
assign
CAPB3OlOI
[
4
]
=
CAPB3l1OI
;
else
if
(
APBSLOT4ENABLE
)
assign
CAPB3OlOI
[
4
]
=
PREADYS4
;
else
assign
CAPB3OlOI
[
4
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3lIl
)
assign
CAPB3OlOI
[
5
]
=
CAPB3l1OI
;
else
if
(
APBSLOT5ENABLE
)
assign
CAPB3OlOI
[
5
]
=
PREADYS5
;
else
assign
CAPB3OlOI
[
5
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3Oll
)
assign
CAPB3OlOI
[
6
]
=
CAPB3l1OI
;
else
if
(
APBSLOT6ENABLE
)
assign
CAPB3OlOI
[
6
]
=
PREADYS6
;
else
assign
CAPB3OlOI
[
6
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3Ill
)
assign
CAPB3OlOI
[
7
]
=
CAPB3l1OI
;
else
if
(
APBSLOT7ENABLE
)
assign
CAPB3OlOI
[
7
]
=
PREADYS7
;
else
assign
CAPB3OlOI
[
7
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3lll
)
assign
CAPB3OlOI
[
8
]
=
CAPB3l1OI
;
else
if
(
APBSLOT8ENABLE
)
assign
CAPB3OlOI
[
8
]
=
PREADYS8
;
else
assign
CAPB3OlOI
[
8
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3O0l
)
assign
CAPB3OlOI
[
9
]
=
CAPB3l1OI
;
else
if
(
APBSLOT9ENABLE
)
assign
CAPB3OlOI
[
9
]
=
PREADYS9
;
else
assign
CAPB3OlOI
[
9
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3I0l
)
assign
CAPB3OlOI
[
10
]
=
CAPB3l1OI
;
else
if
(
APBSLOT10ENABLE
)
assign
CAPB3OlOI
[
10
]
=
PREADYS10
;
else
assign
CAPB3OlOI
[
10
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3l0l
)
assign
CAPB3OlOI
[
11
]
=
CAPB3l1OI
;
else
if
(
APBSLOT11ENABLE
)
assign
CAPB3OlOI
[
11
]
=
PREADYS11
;
else
assign
CAPB3OlOI
[
11
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3O1l
)
assign
CAPB3OlOI
[
12
]
=
CAPB3l1OI
;
else
if
(
APBSLOT12ENABLE
)
assign
CAPB3OlOI
[
12
]
=
PREADYS12
;
else
assign
CAPB3OlOI
[
12
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3I1l
)
assign
CAPB3OlOI
[
13
]
=
CAPB3l1OI
;
else
if
(
APBSLOT13ENABLE
)
assign
CAPB3OlOI
[
13
]
=
PREADYS13
;
else
assign
CAPB3OlOI
[
13
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3l1l
)
assign
CAPB3OlOI
[
14
]
=
CAPB3l1OI
;
else
if
(
APBSLOT14ENABLE
)
assign
CAPB3OlOI
[
14
]
=
PREADYS14
;
else
assign
CAPB3OlOI
[
14
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3OO0
)
assign
CAPB3OlOI
[
15
]
=
CAPB3l1OI
;
else
if
(
APBSLOT15ENABLE
)
assign
CAPB3OlOI
[
15
]
=
PREADYS15
;
else
assign
CAPB3OlOI
[
15
]
=
CAPB3l1OI
;
if
(
IADDR_OPTION
==
CAPB3OOl
)
assign
CAPB3IlOI
[
0
]
=
CAPB3OOII
;
else
if
(
APBSLOT0ENABLE
)
assign
CAPB3IlOI
[
0
]
=
PSLVERRS0
;
else
assign
CAPB3IlOI
[
0
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3IOl
)
assign
CAPB3IlOI
[
1
]
=
CAPB3OOII
;
else
if
(
APBSLOT1ENABLE
)
assign
CAPB3IlOI
[
1
]
=
PSLVERRS1
;
else
assign
CAPB3IlOI
[
1
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3lOl
)
assign
CAPB3IlOI
[
2
]
=
CAPB3OOII
;
else
if
(
APBSLOT2ENABLE
)
assign
CAPB3IlOI
[
2
]
=
PSLVERRS2
;
else
assign
CAPB3IlOI
[
2
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3OIl
)
assign
CAPB3IlOI
[
3
]
=
CAPB3OOII
;
else
if
(
APBSLOT3ENABLE
)
assign
CAPB3IlOI
[
3
]
=
PSLVERRS3
;
else
assign
CAPB3IlOI
[
3
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3IIl
)
assign
CAPB3IlOI
[
4
]
=
CAPB3OOII
;
else
if
(
APBSLOT4ENABLE
)
assign
CAPB3IlOI
[
4
]
=
PSLVERRS4
;
else
assign
CAPB3IlOI
[
4
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3lIl
)
assign
CAPB3IlOI
[
5
]
=
CAPB3OOII
;
else
if
(
APBSLOT5ENABLE
)
assign
CAPB3IlOI
[
5
]
=
PSLVERRS5
;
else
assign
CAPB3IlOI
[
5
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3Oll
)
assign
CAPB3IlOI
[
6
]
=
CAPB3OOII
;
else
if
(
APBSLOT6ENABLE
)
assign
CAPB3IlOI
[
6
]
=
PSLVERRS6
;
else
assign
CAPB3IlOI
[
6
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3Ill
)
assign
CAPB3IlOI
[
7
]
=
CAPB3OOII
;
else
if
(
APBSLOT7ENABLE
)
assign
CAPB3IlOI
[
7
]
=
PSLVERRS7
;
else
assign
CAPB3IlOI
[
7
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3lll
)
assign
CAPB3IlOI
[
8
]
=
CAPB3OOII
;
else
if
(
APBSLOT8ENABLE
)
assign
CAPB3IlOI
[
8
]
=
PSLVERRS8
;
else
assign
CAPB3IlOI
[
8
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3O0l
)
assign
CAPB3IlOI
[
9
]
=
CAPB3OOII
;
else
if
(
APBSLOT9ENABLE
)
assign
CAPB3IlOI
[
9
]
=
PSLVERRS9
;
else
assign
CAPB3IlOI
[
9
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3I0l
)
assign
CAPB3IlOI
[
10
]
=
CAPB3OOII
;
else
if
(
APBSLOT10ENABLE
)
assign
CAPB3IlOI
[
10
]
=
PSLVERRS10
;
else
assign
CAPB3IlOI
[
10
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3l0l
)
assign
CAPB3IlOI
[
11
]
=
CAPB3OOII
;
else
if
(
APBSLOT11ENABLE
)
assign
CAPB3IlOI
[
11
]
=
PSLVERRS11
;
else
assign
CAPB3IlOI
[
11
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3O1l
)
assign
CAPB3IlOI
[
12
]
=
CAPB3OOII
;
else
if
(
APBSLOT12ENABLE
)
assign
CAPB3IlOI
[
12
]
=
PSLVERRS12
;
else
assign
CAPB3IlOI
[
12
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3I1l
)
assign
CAPB3IlOI
[
13
]
=
CAPB3OOII
;
else
if
(
APBSLOT13ENABLE
)
assign
CAPB3IlOI
[
13
]
=
PSLVERRS13
;
else
assign
CAPB3IlOI
[
13
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3l1l
)
assign
CAPB3IlOI
[
14
]
=
CAPB3OOII
;
else
if
(
APBSLOT14ENABLE
)
assign
CAPB3IlOI
[
14
]
=
PSLVERRS14
;
else
assign
CAPB3IlOI
[
14
]
=
CAPB3OOII
;
if
(
IADDR_OPTION
==
CAPB3OO0
)
assign
CAPB3IlOI
[
15
]
=
CAPB3OOII
;
else
if
(
APBSLOT15ENABLE
)
assign
CAPB3IlOI
[
15
]
=
PSLVERRS15
;
else
assign
CAPB3IlOI
[
15
]
=
CAPB3OOII
;
end
endgenerate
CAPB3l
CAPB3lOII
(
.CAPB3OI
(
{
PSELS16
,
CAPB3O0OI
[
15
:
0
]
}
)
,
.PRDATAS0
(
CAPB3II1
[
31
:
0
]
)
,
.PRDATAS1
(
CAPB3lI1
[
31
:
0
]
)
,
.PRDATAS2
(
CAPB3Ol1
[
31
:
0
]
)
,
.PRDATAS3
(
CAPB3Il1
[
31
:
0
]
)
,
.PRDATAS4
(
CAPB3ll1
[
31
:
0
]
)
,
.PRDATAS5
(
CAPB3O01
[
31
:
0
]
)
,
.PRDATAS6
(
CAPB3I01
[
31
:
0
]
)
,
.PRDATAS7
(
CAPB3l01
[
31
:
0
]
)
,
.PRDATAS8
(
CAPB3O11
[
31
:
0
]
)
,
.PRDATAS9
(
CAPB3I11
[
31
:
0
]
)
,
.PRDATAS10
(
CAPB3l11
[
31
:
0
]
)
,
.PRDATAS11
(
CAPB3OOOI
[
31
:
0
]
)
,
.PRDATAS12
(
CAPB3IOOI
[
31
:
0
]
)
,
.PRDATAS13
(
CAPB3lOOI
[
31
:
0
]
)
,
.PRDATAS14
(
CAPB3OIOI
[
31
:
0
]
)
,
.PRDATAS15
(
CAPB3IIOI
[
31
:
0
]
)
,
.PRDATAS16
(
PRDATAS16
[
31
:
0
]
)
,
.CAPB3II
(
{
PREADYS16
,
CAPB3OlOI
[
15
:
0
]
}
)
,
.CAPB3lI
(
{
PSLVERRS16
,
CAPB3IlOI
[
15
:
0
]
}
)
,
.PREADY
(
PREADY
)
,
.PSLVERR
(
PSLVERR
)
,
.PRDATA
(
CAPB3I0I
[
31
:
0
]
)
)
;
assign
PRDATA
[
31
:
0
]
=
CAPB3I0I
[
31
:
0
]
;
generate
begin
:
CAPB3OIII
if
(
IADDR_OPTION
==
CAPB3OOl
)
assign
PSELS0
=
1
'b
0
;
else
assign
PSELS0
=
CAPB3O0OI
[
0
]
;
if
(
IADDR_OPTION
==
CAPB3IOl
)
assign
PSELS1
=
1
'b
0
;
else
assign
PSELS1
=
CAPB3O0OI
[
1
]
;
if
(
IADDR_OPTION
==
CAPB3lOl
)
assign
PSELS2
=
1
'b
0
;
else
assign
PSELS2
=
CAPB3O0OI
[
2
]
;
if
(
IADDR_OPTION
==
CAPB3OIl
)
assign
PSELS3
=
1
'b
0
;
else
assign
PSELS3
=
CAPB3O0OI
[
3
]
;
if
(
IADDR_OPTION
==
CAPB3IIl
)
assign
PSELS4
=
1
'b
0
;
else
assign
PSELS4
=
CAPB3O0OI
[
4
]
;
if
(
IADDR_OPTION
==
CAPB3lIl
)
assign
PSELS5
=
1
'b
0
;
else
assign
PSELS5
=
CAPB3O0OI
[
5
]
;
if
(
IADDR_OPTION
==
CAPB3Oll
)
assign
PSELS6
=
1
'b
0
;
else
assign
PSELS6
=
CAPB3O0OI
[
6
]
;
if
(
IADDR_OPTION
==
CAPB3Ill
)
assign
PSELS7
=
1
'b
0
;
else
assign
PSELS7
=
CAPB3O0OI
[
7
]
;
if
(
IADDR_OPTION
==
CAPB3lll
)
assign
PSELS8
=
1
'b
0
;
else
assign
PSELS8
=
CAPB3O0OI
[
8
]
;
if
(
IADDR_OPTION
==
CAPB3O0l
)
assign
PSELS9
=
1
'b
0
;
else
assign
PSELS9
=
CAPB3O0OI
[
9
]
;
if
(
IADDR_OPTION
==
CAPB3I0l
)
assign
PSELS10
=
1
'b
0
;
else
assign
PSELS10
=
CAPB3O0OI
[
10
]
;
if
(
IADDR_OPTION
==
CAPB3l0l
)
assign
PSELS11
=
1
'b
0
;
else
assign
PSELS11
=
CAPB3O0OI
[
11
]
;
if
(
IADDR_OPTION
==
CAPB3O1l
)
assign
PSELS12
=
1
'b
0
;
else
assign
PSELS12
=
CAPB3O0OI
[
12
]
;
if
(
IADDR_OPTION
==
CAPB3I1l
)
assign
PSELS13
=
1
'b
0
;
else
assign
PSELS13
=
CAPB3O0OI
[
13
]
;
if
(
IADDR_OPTION
==
CAPB3l1l
)
assign
PSELS14
=
1
'b
0
;
else
assign
PSELS14
=
CAPB3O0OI
[
14
]
;
if
(
IADDR_OPTION
==
CAPB3OO0
)
assign
PSELS15
=
1
'b
0
;
else
assign
PSELS15
=
CAPB3O0OI
[
15
]
;
end
endgenerate
generate
begin
:
CAPB3IIII
if
(
IADDR_OPTION
==
CAPB3I1I
)
assign
CAPB3I
=
32
'b
0
;
if
(
IADDR_OPTION
==
CAPB3l1I
)
assign
CAPB3I
=
32
'b
0
;
if
(
IADDR_OPTION
==
CAPB3OOl
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
0
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3IOl
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
1
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3lOl
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
2
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3OIl
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
3
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3IIl
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
4
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3lIl
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
5
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3Oll
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
6
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3Ill
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
7
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3lll
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
8
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3O0l
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
9
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3I0l
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
10
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3l0l
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
11
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3O1l
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
12
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3I1l
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
13
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3l1l
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
14
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
if
(
IADDR_OPTION
==
CAPB3OO0
)
CAPB3O
#
(
APB_DWIDTH
,
MADDR_BITS
)
CAPB3lIII
(
PCLK
,
PRESETN
,
PENABLE
,
CAPB3O0OI
[
15
]
,
PADDR
,
PWRITE
,
PWDATA
,
CAPB3lIOI
,
CAPB3I
)
;
end
endgenerate
generate
begin
if
(
IADDR_OPTION
==
CAPB3I1I
)
begin
assign
CAPB3O1OI
=
PADDR
;
assign
CAPB3l0OI
=
32
'b
0
;
end
else
if
(
IADDR_OPTION
==
CAPB3l1I
)
begin
assign
CAPB3O1OI
=
IADDR
;
assign
CAPB3l0OI
=
IADDR
;
end
else
begin
assign
CAPB3O1OI
=
CAPB3I
;
assign
CAPB3l0OI
=
CAPB3I
;
end
end
endgenerate
generate
if
(
MADDR_BITS
==
12
)
begin
always
@(*)
case
(
UPR_NIBBLE_POSN
)
2
:
PADDRS
=
{
CAPB3O1OI
[
31
:
12
]
,
PADDR
[
11
:
0
]
}
;
3
:
PADDRS
=
{
CAPB3O1OI
[
31
:
16
]
,
PADDR
[
11
:
8
]
,
CAPB3l0OI
[
11
:
8
]
,
PADDR
[
7
:
0
]
}
;
4
:
PADDRS
=
{
CAPB3O1OI
[
31
:
20
]
,
PADDR
[
11
:
8
]
,
CAPB3l0OI
[
15
:
8
]
,
PADDR
[
7
:
0
]
}
;
5
:
PADDRS
=
{
CAPB3O1OI
[
31
:
24
]
,
PADDR
[
11
:
8
]
,
CAPB3l0OI
[
19
:
8
]
,
PADDR
[
7
:
0
]
}
;
6
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
11
:
8
]
,
CAPB3l0OI
[
23
:
8
]
,
PADDR
[
7
:
0
]
}
;
7
:
PADDRS
=
{
PADDR
[
11
:
8
]
,
CAPB3l0OI
[
27
:
8
]
,
PADDR
[
7
:
0
]
}
;
8
:
PADDRS
=
{
CAPB3l0OI
[
31
:
8
]
,
PADDR
[
7
:
0
]
}
;
endcase
end
endgenerate
generate
if
(
MADDR_BITS
==
16
)
begin
always
@(*)
case
(
UPR_NIBBLE_POSN
)
2
:
PADDRS
=
{
CAPB3O1OI
[
31
:
16
]
,
PADDR
[
15
:
0
]
}
;
3
:
PADDRS
=
{
CAPB3O1OI
[
31
:
16
]
,
PADDR
[
15
:
0
]
}
;
4
:
PADDRS
=
{
CAPB3O1OI
[
31
:
20
]
,
PADDR
[
15
:
12
]
,
CAPB3l0OI
[
15
:
12
]
,
PADDR
[
11
:
0
]
}
;
5
:
PADDRS
=
{
CAPB3O1OI
[
31
:
24
]
,
PADDR
[
15
:
12
]
,
CAPB3l0OI
[
19
:
12
]
,
PADDR
[
11
:
0
]
}
;
6
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
15
:
12
]
,
CAPB3l0OI
[
23
:
12
]
,
PADDR
[
11
:
0
]
}
;
7
:
PADDRS
=
{
PADDR
[
15
:
12
]
,
CAPB3l0OI
[
27
:
12
]
,
PADDR
[
11
:
0
]
}
;
8
:
PADDRS
=
{
CAPB3l0OI
[
31
:
12
]
,
PADDR
[
11
:
0
]
}
;
endcase
end
endgenerate
generate
if
(
MADDR_BITS
==
20
)
begin
always
@(*)
case
(
UPR_NIBBLE_POSN
)
2
:
PADDRS
=
{
CAPB3O1OI
[
31
:
20
]
,
PADDR
[
19
:
0
]
}
;
3
:
PADDRS
=
{
CAPB3O1OI
[
31
:
20
]
,
PADDR
[
19
:
0
]
}
;
4
:
PADDRS
=
{
CAPB3O1OI
[
31
:
20
]
,
PADDR
[
19
:
0
]
}
;
5
:
PADDRS
=
{
CAPB3O1OI
[
31
:
24
]
,
PADDR
[
19
:
16
]
,
CAPB3l0OI
[
19
:
16
]
,
PADDR
[
15
:
0
]
}
;
6
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
19
:
16
]
,
CAPB3l0OI
[
23
:
16
]
,
PADDR
[
15
:
0
]
}
;
7
:
PADDRS
=
{
PADDR
[
19
:
16
]
,
CAPB3l0OI
[
27
:
16
]
,
PADDR
[
15
:
0
]
}
;
8
:
PADDRS
=
{
CAPB3l0OI
[
31
:
16
]
,
PADDR
[
15
:
0
]
}
;
endcase
end
endgenerate
generate
if
(
MADDR_BITS
==
24
)
begin
always
@(*)
case
(
UPR_NIBBLE_POSN
)
2
:
PADDRS
=
{
CAPB3O1OI
[
31
:
24
]
,
PADDR
[
23
:
0
]
}
;
3
:
PADDRS
=
{
CAPB3O1OI
[
31
:
24
]
,
PADDR
[
23
:
0
]
}
;
4
:
PADDRS
=
{
CAPB3O1OI
[
31
:
24
]
,
PADDR
[
23
:
0
]
}
;
5
:
PADDRS
=
{
CAPB3O1OI
[
31
:
24
]
,
PADDR
[
23
:
0
]
}
;
6
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
23
:
20
]
,
CAPB3l0OI
[
23
:
20
]
,
PADDR
[
19
:
0
]
}
;
7
:
PADDRS
=
{
PADDR
[
23
:
20
]
,
CAPB3l0OI
[
27
:
20
]
,
PADDR
[
19
:
0
]
}
;
8
:
PADDRS
=
{
CAPB3l0OI
[
31
:
20
]
,
PADDR
[
19
:
0
]
}
;
endcase
end
endgenerate
generate
if
(
MADDR_BITS
==
28
)
begin
always
@(*)
case
(
UPR_NIBBLE_POSN
)
2
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
27
:
0
]
}
;
3
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
27
:
0
]
}
;
4
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
27
:
0
]
}
;
5
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
27
:
0
]
}
;
6
:
PADDRS
=
{
CAPB3O1OI
[
31
:
28
]
,
PADDR
[
27
:
0
]
}
;
7
:
PADDRS
=
{
PADDR
[
27
:
24
]
,
CAPB3l0OI
[
27
:
24
]
,
PADDR
[
23
:
0
]
}
;
8
:
PADDRS
=
{
CAPB3l0OI
[
31
:
24
]
,
PADDR
[
23
:
0
]
}
;
endcase
end
endgenerate
generate
if
(
MADDR_BITS
==
32
)
begin
always
@(*)
PADDRS
=
PADDR
[
31
:
0
]
;
end
endgenerate
endmodule |
module qadd #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
reg [N-1:0] res;
assign c = res;
always @(a,b) begin
// both negative or both positive
if(a[N-1] == b[N-1]) begin // Since they have the same sign, absolute magnitude increases
res[N-2:0] = a[N-2:0] + b[N-2:0]; // So we just add the two numbers
res[N-1] = a[N-1]; // and set the sign appropriately... Doesn't matter which one we use,
// they both have the same sign
// Do the sign last, on the off-chance there was an overflow...
end // Not doing any error checking on this...
// one of them is negative...
else if(a[N-1] == 0 && b[N-1] == 1) begin // subtract a-b
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // then just subtract b from a
res[N-1] = 0; // and manually set the sign to positive
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // we'll actually subtract a from b to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
end
else begin // subtract b-a (a negative, b positive)
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // we'll actually subtract b from a to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // then just subtract a from b
res[N-1] = 0; // and manually set the sign to positive
end
end
end
endmodule |
module sky130_fd_sc_hs__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sky130_fd_sc_lp__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule |
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0,
parameter C_GP0_EN_MODIFIABLE_TXN=0,
parameter C_GP1_EN_MODIFIABLE_TXN=0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire [3:0] M_AXI_GP0_ARCACHE_t;
wire [3:0] M_AXI_GP1_ARCACHE_t;
wire [3:0] M_AXI_GP0_AWCACHE_t;
wire [3:0] M_AXI_GP1_AWCACHE_t;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_tester_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule |
module blk_mem_LUT
(clka,
ena,
addra,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [3:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [15:0]douta;
wire [3:0]addra;
wire clka;
wire [15:0]douta;
wire ena;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [15:0]NLW_U0_doutb_UNCONNECTED;
wire [3:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [15:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "4" *)
(* C_ADDRB_WIDTH = "4" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.7096 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "blk_mem_LUT.mem" *)
(* C_INIT_FILE_NAME = "blk_mem_LUT.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "3" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16" *)
(* C_READ_DEPTH_B = "16" *)
(* C_READ_WIDTH_A = "16" *)
(* C_READ_WIDTH_B = "16" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "16" *)
(* C_WRITE_DEPTH_B = "16" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "16" *)
(* C_WRITE_WIDTH_B = "16" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* KEEP_HIERARCHY = "true" *)
(* downgradeipidentifiedwarnings = "yes" *)
blk_mem_LUT_blk_mem_gen_v8_3_3 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[15:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[3:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[3:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[15:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(1'b0),
.web(1'b0));
endmodule |
module blk_mem_LUT_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra);
output [15:0]douta;
input clka;
input ena;
input [3:0]addra;
wire [3:0]addra;
wire clka;
wire [15:0]douta;
wire ena;
blk_mem_LUT_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.douta(douta),
.ena(ena));
endmodule |
module blk_mem_LUT_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra);
output [15:0]douta;
input clka;
input ena;
input [3:0]addra;
wire [3:0]addra;
wire clka;
wire [15:0]douta;
wire ena;
blk_mem_LUT_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta),
.ena(ena));
endmodule |
module blk_mem_LUT_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra);
output [15:0]douta;
input clka;
input ena;
input [3:0]addra;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ;
wire [3:0]addra;
wire clka;
wire [15:0]douta;
wire ena;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0D0E0A0D0F0E0E0D0C0C0D0D0A0A0B0B0F0E040505000500000A000A00000000),
.INIT_01(256'h0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B0E0E0F),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,1'b0,1'b0,1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ,douta[7:4],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ,douta[3:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ,douta[15:12],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ,douta[11:8]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(ena),
.ENBWREN(ena),
.REGCEAREGCE(ena),
.REGCEB(ena),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule |
module blk_mem_LUT_blk_mem_gen_top
(douta,
clka,
ena,
addra);
output [15:0]douta;
input clka;
input ena;
input [3:0]addra;
wire [3:0]addra;
wire clka;
wire [15:0]douta;
wire ena;
blk_mem_LUT_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.douta(douta),
.ena(ena));
endmodule |
module blk_mem_LUT_blk_mem_gen_v8_3_3
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [3:0]addra;
input [15:0]dina;
output [15:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [3:0]addrb;
input [15:0]dinb;
output [15:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [3:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [15:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [15:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [3:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [3:0]addra;
wire clka;
wire [15:0]douta;
wire ena;
assign dbiterr = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
blk_mem_LUT_blk_mem_gen_v8_3_3_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta),
.ena(ena));
endmodule |
module blk_mem_LUT_blk_mem_gen_v8_3_3_synth
(douta,
clka,
ena,
addra);
output [15:0]douta;
input clka;
input ena;
input [3:0]addra;
wire [3:0]addra;
wire clka;
wire [15:0]douta;
wire ena;
blk_mem_LUT_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta),
.ena(ena));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module ztex_ufm1_15y1 (fxclk_in, reset, select, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, select, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
// Configure cores here since using `ifdef rather than generate (lazy)
//`define PROTOCOL80 // Select 80 or 76 byte protocol (NB use 76 for current cgminer)
localparam LOCAL_MINERS = 1; // One or two cores (configures ADDRBITS automatically)
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS); // Automatically selects largest RAM that will fit LX150
localparam SBITS = 8; // Shift data path width
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1 = 0, reset_buf = 0, reset_buf_d = 0, clk_reset_buf = 1, pll_stop_buf = 1, select_buf = 0;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [3:0] wr_delay;
reg [127:0] outbuf;
reg [7:0] read_buf, write_buf;
reg [31:0] golden_nonce_a = 32'd0, golden_nonce_b = 32'd0;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce_1, hash_1;
wire [31:0] golden_nonce_2, hash_2;
wire [31:0] golden_nonce, nonce_a, hash_a;
wire gn_match_1, gn_match_2;
BUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
DCM_CLKGEN #(
.CLKFX_DIVIDE(4), /* 1mhz */
.CLKFX_MULTIPLY(8), /* 150mhz 166mhz */
.CLKFXDV_DIVIDE(2), /* n/a */
.CLKIN_PERIOD(26.8)
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset_buf)
);
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(6),
.CLKOUT0_DIVIDE(1),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.CLKIN_PERIOD(26.8),
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
assign write = select ? write_buf : 8'bz; // This actually does tristate the outputs
assign pll_reset = pll_stop_buf | ~dcm_locked | clk_reset_buf | dcm_status[2];
`ifdef SIM
// Test hash - final hash at 672,780ns
`ifdef PROTOCOL80
// 80 byte protocol includes nonce
reg [639:0] inbuf_tmp = {
128'h0000318f7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`else
// 76 byte protocol excludes nonce
reg [607:0] inbuf_tmp = {
96'h7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`endif
`else // SIM
`ifdef PROTOCOL80
reg [639:0] inbuf_tmp;
`else
reg [639:0] inbuf_tmp;
`endif
`endif // SIM
`ifdef PROTOCOL80
reg [639:0] inbuf; // 80 byte protocol
`else
reg [607:0] inbuf; // 76 byte protocol
`endif
wire [31:0] mod_target = 32'h000007ff; // Hard coded for diff=32
wire [255:0] data1 = inbuf[255:0];
wire [255:0] data2 = inbuf[511:256];
`ifdef PROTOCOL80
wire [127:0] data3 = inbuf[639:512];
`else
`ifdef SIM
wire [127:0] data3 = { 32'h0000318f, inbuf[607:512] };
`else
wire [127:0] data3 = { 32'd0, inbuf[607:512] };
`endif
`endif
// Generate loadnonce strobe for new work (NB this initiates a full engine reset)
reg loadnonce = 1'b0; // Strobe generated loading work
reg loadnonce_d = 1'b0; // Delay by one since extra register stage inbuf
// NB For now using same clk for both P and S
wire [31:0] nonce_out_1;
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
// Single core
assign nonce_a = nonce_out_1;
assign hash_a = hash_1;
assign gn_match = gn_match_1;
assign golden_nonce = golden_nonce_1;
always @ (posedge clk)
begin
loadnonce <= 1'b0; // For pbkdfengine
loadnonce_d <= loadnonce; // Delay by one since extra register stage inbuf
// KRAMBLE not sure I understand this, it does not seem to be conventional clock-crossing as the comparison is the wrong
// end of the shift register, so perhaps its a de-bounce on the rd_clk (which is sort of clock-crossing too) ??
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) && select_buf )
begin
`ifdef PROTOCOL80
inbuf_tmp[639:632] <= read_buf;
inbuf_tmp[631:0] <= inbuf_tmp[639:8];
`else
inbuf_tmp[607:600] <= read_buf;
inbuf_tmp[599:0] <= inbuf_tmp[607:8];
`endif
// Nonce will be loaded (or reset to 0 in 76 byte protocol) every byte since there is no signal
// that indicates when work is completely loaded (this means hashes generated during loading
// are invalid, so we also reset golden_nonce_a/b below)
loadnonce <= 1'b1; // For pbkdfengine (single clock cycle strobe)
end
inbuf <= inbuf_tmp; // due to TIG's
if ( wr_start_b1 )
begin
wr_delay <= 4'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[3:1] <= wr_delay[2:0];
end
if ( ! wr_delay[3] )
begin
outbuf <= { golden_nonce_b, hash_a, nonce_a, golden_nonce_a };
end else
begin
// KRAMBLE see note above for rd_clk
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[119:0] <= outbuf[127:8];
end
if ( reset_buf | loadnonce ) // Also reset on loadnonce since hashes are invalid
begin
golden_nonce_a <= 32'd0;
golden_nonce_b <= 32'd0;
end else if ( gn_match )
begin
golden_nonce_b <= golden_nonce_a;
golden_nonce_a <= golden_nonce;
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
select_buf <= select;
if ( select )
begin
reset_buf <= reset;
end
reset_buf_d <= reset_buf;
if (reset_buf_d & ~reset_buf) // Executes on trailing edge of reset
begin
end
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen & select;
if ( select )
begin
clk_reset_buf <= clk_reset;
pll_stop_buf <= pll_stop;
end
end
endmodule |
module sky130_fd_sc_ms__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule |
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule |
module third_step(
/*Control signals input*/
input wire aluSrc,
input wire [5:0] ALUOp,
input wire regDst,
input wire [1:0] ForwardAE,
input wire [1:0] ForwardBE,
/*Data signals input*/
//input wire [31:0] pcPlusFour,
input wire [31:0] reg1,
input wire [31:0] reg2,
input wire [31:0] signExtend,
input wire [4:0] regDst1,
input wire [4:0] regDst2,
input wire [31:0] reg_muxes_b,
input wire [31:0] reg_muxes_d,
/*Signal output*/
//output wire [31:0] addResult,
//output wire zero,
output wire [31:0] aluResult,
output wire [31:0] reg2Out,
output wire [4:0] muxRegDstOut
);
mux #(5) muxRegDst (
.select(regDst),
.item_a(regDst1),
.item_b(regDst2),
.signal(muxRegDstOut)
);
//For hazards
wire [31:0] ALUoperator1;
mux4 mux_reg1
(
.sel(ForwardAE),
.item_a(reg1),
.item_b(reg_muxes_b),
.item_c(reg_muxes_d),
.item_d(),
.signal(ALUoperator1)
);
wire [31:0] ALUoperator2;
mux4 mux_reg2
(
.sel(ForwardBE),
.item_a(reg2),
.item_b(reg_muxes_b),
.item_c(reg_muxes_d),
.item_d(),
.signal(ALUoperator2)
);
wire [31:0] muxAluSrc2Out;
mux muxAluSrc2 (
.select(aluSrc),
.item_a(ALUoperator2),
.item_b(signExtend),
.signal(muxAluSrc2Out)
);
wire [3:0] ALUcontrolOut;
alu_control aluControl (
.ALUOp(ALUOp), //TODO: conectar la seal de control correspondiente de la unidad de control
.funct(signExtend[5:0]),
.ALUcontrolOut(ALUcontrolOut)
);
alu aluModule (
.op1(ALUoperator1),
.op2(muxAluSrc2Out),
.alu_control(ALUcontrolOut),
.result(aluResult),
.zero()
);
wire [31:0] shiftLeftOut;
/*
shift_left shiftModule(
.shift_in(signExtend),
.shift_out(shiftLeftOut)
);
adder #(32) adderModule(
.value1(pcPlusFour),
.value2(shiftLeftOut),
.result(addResult)
);
*/
assign reg2Out = ALUoperator2;
endmodule |
module ZC706_Gen2x4If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 4,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [3:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
wire pcie_refclk;
wire pcie_reset_n;
wire user_clk;
wire user_reset;
wire user_lnk_up;
wire user_app_rdy;
wire s_axis_tx_tready;
wire [C_PCI_DATA_WIDTH-1 : 0] s_axis_tx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire [`SIG_XIL_TX_TUSER_W : 0] s_axis_tx_tuser;
wire [C_PCI_DATA_WIDTH-1 : 0] m_axis_rx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
wire tx_cfg_gnt;
wire rx_np_ok;
wire rx_np_req;
wire cfg_turnoff_ok;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [63:0] cfg_dsn;
wire [11 : 0] fc_cpld;
wire [7 : 0] fc_cplh;
wire [11 : 0] fc_npd;
wire [7 : 0] fc_nph;
wire [11 : 0] fc_pd;
wire [7 : 0] fc_ph;
wire [2 : 0] fc_sel;
wire [15 : 0] cfg_status;
wire [15 : 0] cfg_command;
wire [15 : 0] cfg_dstatus;
wire [15 : 0] cfg_dcommand;
wire [15 : 0] cfg_lstatus;
wire [15 : 0] cfg_lcommand;
wire [15 : 0] cfg_dcommand2;
wire [2 : 0] cfg_pcie_link_state;
wire cfg_pmcsr_pme_en;
wire [1 : 0] cfg_pmcsr_powerstate;
wire cfg_pmcsr_pme_status;
wire cfg_received_func_lvl_rst;
wire [4 : 0] cfg_pciecap_interrupt_msgnum;
wire cfg_to_turnoff;
wire [7 : 0] cfg_bus_number;
wire [4 : 0] cfg_device_number;
wire [2 : 0] cfg_function_number;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7 : 0] cfg_interrupt_di;
wire [7 : 0] cfg_interrupt_do;
wire [2 : 0] cfg_interrupt_mmenable;
wire cfg_interrupt_msien;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
assign cfg_turnoff_ok = 0;
assign cfg_trn_pending = 0;
assign cfg_pm_halt_aspm_l0s = 0;
assign cfg_pm_halt_aspm_l1 = 0;
assign cfg_pm_force_state_en = 0;
assign cfg_pm_force_state = 0;
assign cfg_dsn = 0;
assign cfg_interrupt_assert = 0;
assign cfg_interrupt_di = 0;
assign cfg_interrupt_stat = 0;
assign cfg_pciecap_interrupt_msgnum = 0;
assign cfg_turnoff_ok = 0;
assign cfg_pm_wake = 0;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
// Core Top Level Wrapper
PCIeGen2x4If128 PCIeGen2x4If128_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
// Tx
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
// Rx
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI-S Interface
//---------------------------------------------------------------------
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( user_app_rdy ),
// TX
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
//---------------------------------------------------------------------
// Flow Control Interface
//---------------------------------------------------------------------
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.cfg_device_number ( cfg_device_number ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_status ( cfg_status ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msien ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
//---------------------------------------------------------------------
// System (SYS) Interface
//---------------------------------------------------------------------
.sys_clk ( pcie_refclk ),
.sys_rst_n ( pcie_reset_n )
);
riffa_wrapper_zc706
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.CFG_INTERRUPT (cfg_interrupt),
.M_AXIS_RX_TREADY (m_axis_rx_tready),
.S_AXIS_TX_TDATA (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (s_axis_tx_tlast),
.S_AXIS_TX_TVALID (s_axis_tx_tvalid),
.S_AXIS_TX_TUSER (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
.FC_SEL (fc_sel[`SIG_FC_SEL_W-1:0]),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_RX_TDATA (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (m_axis_rx_tlast),
.M_AXIS_RX_TVALID (m_axis_rx_tvalid),
.M_AXIS_RX_TUSER (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (s_axis_tx_tready),
.CFG_BUS_NUMBER (cfg_bus_number[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (cfg_device_number[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (cfg_function_number[`SIG_FNID_W-1:0]),
.CFG_COMMAND (cfg_command[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (cfg_dcommand[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (cfg_lstatus[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (cfg_lcommand[`SIG_CFGREG_W-1:0]),
.FC_CPLD (fc_cpld[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (fc_cplh[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (cfg_interrupt_msien),
.CFG_INTERRUPT_RDY (cfg_interrupt_rdy),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
.RX_NP_OK (rx_np_ok),
.RX_NP_REQ (rx_np_req),
.TX_CFG_GNT (tx_cfg_gnt)
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
);
end
endgenerate
endmodule |
module sky130_fd_sc_hdll__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule |
module sky130_fd_sc_ls__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule |
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv5sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
module UART (
input rst,
// IO ports
input clk,
input rx,
output tx,
// Tx data port
input tx_data_ready,
input [7:0] tx_data,
output tx_data_accepted,
// Rx data port
output [7:0] rx_data,
output rx_data_ready,
output rx_framing_error
);
// COUNTER*OVERSAMPLE == effective baud rate.
//
// So given a 100 MHz clock (100000000), an 8x oversample and a counter
// of 25, (100000000/(8*25)) => 500000 baud.
//
// BAUDGEN generates an edge COUNTER clock cycles.
// Two BAUDGEN's are used, one for the Tx which is at the baudrate, and
// one for the Rx which is at OVERSAMPLE times the baudrate.
parameter COUNTER = 25;
parameter OVERSAMPLE = 8;
wire tx_baud_edge;
wire rx_baud_edge;
BAUDGEN #(.COUNTER(COUNTER*OVERSAMPLE)) tx_baud (
.clk(clk),
.rst(rst),
.baud_edge(tx_baud_edge)
);
UART_TX tx_gen(
.rst(rst),
.clk(clk),
.baud_edge(tx_baud_edge),
.data_ready(tx_data_ready),
.data(tx_data),
.tx(tx),
.data_accepted(tx_data_accepted)
);
BAUDGEN #(.COUNTER(COUNTER)) rx_baud (
.clk(clk),
.rst(rst),
.baud_edge(rx_baud_edge)
);
UART_RX rx_gen(
.rst(rst),
.clk(clk),
.baud_edge(rx_baud_edge),
.rx(rx),
.data(rx_data),
.data_ready(rx_data_ready),
.framing_error(rx_framing_error)
);
endmodule |
module spll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module timer_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [2:1] COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 2;
genvar count_gen;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
timer clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]));
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen]) begin
if (reset_int) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule |
module sky130_fd_sc_hd__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule |
module ram_16x512_dp (
address_a,
address_b,
byteena_a,
byteena_b,
clock_a,
clock_b,
data_a,
data_b,
enable_a,
enable_b,
wren_a,
wren_b,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input [1:0] byteena_a;
input [1:0] byteena_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input enable_a;
input enable_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 [1:0] byteena_b;
tri1 clock_a;
tri1 enable_a;
tri1 enable_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.byteena_b (byteena_b),
.clock0 (clock_a),
.clock1 (clock_b),
.clocken0 (enable_a),
.clocken1 (enable_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byteena_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_input_b = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.width_byteena_b = 2,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule |
module sky130_fd_sc_ls__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_ls__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule |
module axi_ad9467_channel(
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
// instantiations
axi_ad9467_pnmon i_axi_ad9467_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
ad_datafmt #(.DATA_WIDTH(16)) i_datafmt (
.clk(adc_clk),
.valid(1'b1),
.data(adc_data),
.valid_out(),
.data_out(adc_dfmt_data),
.dfmt_enable(adc_dfmt_enable_s),
.dfmt_type(adc_dfmt_type_s),
.dfmt_se(adc_dfmt_se_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule |
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
reg [8:0] uart_buf;
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
`ifdef DBGUART
init_socket();
`endif
end
final begin
`ifdef DBGUART
close_socket();
`endif
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_buf[8] && ~cs)
uart_buf <= recuart();
ff<=ffold;
if (uart_buf[8] && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
senduart(bus_wr_val[7:0]);
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
if (bus_addr[3:0] == 4'b1100) begin
inter<=1'b1;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= (uart_buf[8] ? 32'b10 : 32'b0);
end
end
end
bus_ack <= cs;
end
endmodule |
module pll1 (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "208",
altpll_component.clk1_divide_by = 2,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule |
module decode_tb();
reg [11:0] story_to;
reg fault_to;
reg clk_i, reset_i, inst_en_i;
reg [31:0] inst_i;
reg [63:0] rs1val_i, rs2val_i, ex_q_i, mem_q_i;
reg [4:0] ex_rd_i, mem_rd_i;
wire [63:0] inpa_o, inpb_o;
wire invB_o, cflag_o, lsh_en_o, rsh_en_o;
wire ltu_en_o, lts_en_o, sum_en_o;
wire and_en_o, xor_en_o;
wire [4:0] rd_o, rs1_o, rs2_o;
wire we_o, nomem_o, mem_o;
wire [63:0] dat_o;
wire [2:0] xrs_rwe_o;
wire illegal_o;
always begin
#10 clk_i <= ~clk_i;
end
decode decode(
.clk_i(clk_i),
.reset_i(reset_i),
.inst_i(inst_i),
.inst_en_i(inst_en_i),
.rs1val_i(rs1val_i),
.rs2val_i(rs2val_i),
.ex_rd_i(ex_rd_i),
.mem_rd_i(mem_rd_i),
.ex_q_i(ex_q_i),
.mem_q_i(mem_q_i),
.inpa_o(inpa_o),
.inpb_o(inpb_o),
.invB_o(invB_o),
.cflag_o(cflag_o),
.lsh_en_o(lsh_en_o),
.rsh_en_o(rsh_en_o),
.ltu_en_o(ltu_en_o),
.lts_en_o(lts_en_o),
.sum_en_o(sum_en_o),
.and_en_o(and_en_o),
.xor_en_o(xor_en_o),
.rd_o(rd_o),
.rs1_o(rs1_o),
.rs2_o(rs2_o),
.we_o(we_o),
.nomem_o(nomem_o),
.mem_o(mem_o),
.dat_o(dat_o),
.xrs_rwe_o(xrs_rwe_o),
.illegal_o(illegal_o)
);
task zero;
begin
{
ex_rd_i, mem_rd_i, ex_q_i, mem_q_i,
reset_i, inst_i, rs1val_i, rs2val_i, inst_en_i,
story_to, fault_to
} <= 0;
end
endtask
`STANDARD_FAULT
`DEFASSERT(inpa, 63, o)
`DEFASSERT(inpb, 63, o)
`DEFASSERT0(invB, o)
`DEFASSERT0(cflag, o)
`DEFASSERT0(lsh_en, o)
`DEFASSERT0(rsh_en, o)
`DEFASSERT0(ltu_en, o)
`DEFASSERT0(lts_en, o)
`DEFASSERT0(sum_en, o)
`DEFASSERT0(and_en, o)
`DEFASSERT0(xor_en, o)
`DEFASSERT(rd, 4, o)
`DEFASSERT(rs1, 4, o)
`DEFASSERT(rs2, 4, o)
`DEFASSERT0(we, o)
`DEFASSERT0(nomem, o)
`DEFASSERT0(mem, o)
`DEFASSERT(dat, 63, o)
`DEFASSERT(xrs_rwe, 2, o)
`DEFASSERT0(illegal, o)
initial begin
$dumpfile("decode.vcd");
$dumpvars;
zero;
ex_q_i <= 64'hFACE0BADC0FFEE00;
mem_q_i <= 64'hFEEDFACE0BADC0DE;
clk_i <= 0;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 1;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 0;
assert_inpa(0);
assert_inpb(0);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
assert_rd(0);
assert_rs1(0);
// assert_rs2(0);
assert_we(0);
assert_nomem(1);
assert_mem(0);
assert_dat(0);
assert_xrs_rwe(`XRS_RWE_S64);
assert_illegal(0);
// ADDI X1, X0, $800
// SLLI X1, X1, 52
story_to <= 12'h010;
inst_en_i <= 1;
inst_i <= 32'b100000000000_00000_000_00001_0010011;
wait(~clk_i); wait(clk_i); #1;
assert_inpa(0);
assert_inpb(64'hFFFF_FFFF_FFFF_F800);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
assert_rd(1);
assert_rs1(0);
// assert_rs2(0);
assert_we(0);
assert_nomem(1);
assert_mem(0);
assert_dat(0);
assert_xrs_rwe(`XRS_RWE_S64);
assert_illegal(0);
story_to <= 12'h018;
inst_i <= 32'b000000110100_00001_001_00001_0010011;
wait(~clk_i); wait(clk_i); #1;
#10 rs1val_i <= 64'hFFFF_FFFF_FFFF_F800;
rs2val_i <= 64'hDEAD_BEEF_FEED_FACE;
#1;
assert_inpa(64'hFFFF_FFFF_FFFF_F800);
assert_inpb(52);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(1);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(0);
assert_and_en(0);
assert_xor_en(0);
assert_rd(1);
assert_rs1(1);
// assert_rs2(0);
assert_we(0);
assert_nomem(1);
assert_mem(0);
assert_dat(0);
assert_xrs_rwe(`XRS_RWE_S64);
assert_illegal(0);
// SB X1, 1(X2) 0000000_00001_00010_000_00001_0100011
// SH X2, 2(X3) 0000000_00010_00011_001_00010_0100011
// SW X3, 3(X4) 0000000_00011_00100_010_00011_0100011
// SD X4, 4(X5) 0000000_00100_00101_011_00100_0100011
story_to <= 12'h020;
inst_en_i <= 1;
inst_i <= 32'b0000000_00001_00010_000_00001_0100011;
wait(~clk_i); wait(clk_i); #1;
#10 rs1val_i <= 64'd1;
rs2val_i <= 64'hDEAD_BEEF_FEED_FACE;
#1;
assert_inpa(64'd1);
assert_inpb(1);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
// assert_rd(1);
assert_rs1(2);
assert_rs2(1);
assert_we(1);
assert_nomem(0);
assert_mem(1);
assert_dat(64'hDEAD_BEEF_FEED_FACE);
assert_xrs_rwe(`XRS_RWE_S8);
assert_illegal(0);
story_to <= 12'h024;
inst_i <= 32'b0000000_00010_00011_001_00010_0100011;
wait(~clk_i); wait(clk_i); #1;
#10 rs1val_i <= 64'd2;
rs2val_i <= 64'hDEAD_BEEF_FEED_FACE;
#1;
assert_inpa(64'd2);
assert_inpb(2);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
// assert_rd(1);
assert_rs1(3);
assert_rs2(2);
assert_we(1);
assert_nomem(0);
assert_mem(1);
assert_dat(64'hDEAD_BEEF_FEED_FACE);
assert_xrs_rwe(`XRS_RWE_S16);
assert_illegal(0);
story_to <= 12'h028;
inst_i <= 32'b0000000_00011_00100_010_00011_0100011;
wait(~clk_i); wait(clk_i); #1;
#10 rs1val_i <= 64'd1;
rs2val_i <= 64'hDEAD_BEEF_FEED_FACE;
#1;
assert_inpa(64'd1);
assert_inpb(3);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
// assert_rd(1);
assert_rs1(4);
assert_rs2(3);
assert_we(1);
assert_nomem(0);
assert_mem(1);
assert_dat(64'hDEAD_BEEF_FEED_FACE);
assert_xrs_rwe(`XRS_RWE_S32);
assert_illegal(0);
story_to <= 12'h02C;
inst_i <= 32'b0000000_00100_00101_011_00100_0100011;
wait(~clk_i); wait(clk_i); #1;
#10 rs1val_i <= 64'd4;
rs2val_i <= 64'hDEAD_BEEF_FEED_FACE;
#1;
assert_inpa(64'd4);
assert_inpb(4);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
// assert_rd(1);
assert_rs1(5);
assert_rs2(4);
assert_we(1);
assert_nomem(0);
assert_mem(1);
assert_dat(64'hDEAD_BEEF_FEED_FACE);
assert_xrs_rwe(`XRS_RWE_S64);
assert_illegal(0);
// ADDI X1, X2, 3
// X2 feedback from EX
story_to <= 12'h030;
inst_en_i <= 1;
inst_i <= 32'b000000000011_00010_000_00001_0010011;
ex_rd_i <= 2;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
assert_inpa(64'hFACE_0BAD_C0FF_EE00);
assert_inpb(64'h0000_0000_0000_0003);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
assert_rd(1);
assert_rs1(2);
// assert_rs2(0);
assert_we(0);
assert_nomem(1);
assert_mem(0);
assert_dat(0);
assert_xrs_rwe(`XRS_RWE_S64);
assert_illegal(0);
// SB X1, 1(X2) 0000000_00001_00010_000_00001_0100011
story_to <= 12'h038;
inst_en_i <= 1;
inst_i <= 32'b0000000_00001_00010_000_00001_0100011;
ex_rd_i <= 0;
mem_rd_i <= 1;
wait(~clk_i); wait(clk_i); #1;
#10 rs1val_i <= 64'd1;
rs2val_i <= 64'hDEAD_BEEF_FEED_FACE;
#1;
assert_inpa(64'd1);
assert_inpb(1);
assert_invB(0);
assert_cflag(0);
assert_lsh_en(0);
assert_rsh_en(0);
assert_ltu_en(0);
assert_lts_en(0);
assert_sum_en(1);
assert_and_en(0);
assert_xor_en(0);
// assert_rd(1);
assert_rs1(2);
assert_rs2(1);
assert_we(1);
assert_nomem(0);
assert_mem(1);
assert_dat(64'hFEEDFACE0BADC0DE);
assert_xrs_rwe(`XRS_RWE_S8);
assert_illegal(0);
#100;
$display("@Done.");
$stop;
end
endmodule |
module alu( input [7:0] ctrl,
input [31:0] A,
input [31:0] B,
input [4:0] SH,
output [31:0] Y );
// ctrl [7]: Signed operation (e.g. SLT/SLTU)
// ctrl [6]: SHIFT SRC (1 - reg, 0 - shamt)
// ctrl[5:4]: SHIFT OP
// ctrl [3]: NEGATE B
// ctrl[2:0]: ALU OP
//sign or zero-extension bits:
wire AE_bit = ctrl[7] ? A[31] : 1'b0;
wire BE_bit = ctrl[7] ? B[31] : 1'b0;
wire [32:0] op_A = {AE_bit, A};
wire [32:0] op_B = {BE_bit, B};
wire Cin = ctrl[3]; //carry in. Equals 1 when B = NEGATE(B)
wire [32:0] op_BN = Cin ? ~op_B : op_B; //inverted or not B
wire [32:0] Sum = op_A + op_BN + Cin;
wire [4:0] shamt;
mux2 #(5) shift_in_mux( .S (ctrl[6]),
.D0(SH),
.D1(A[4:0]),
.Y (shamt));
wire[31:0] sh_out;
shifter shifter_unit( .S(ctrl[5:4]),
.N( shamt ),
.A( B ),
.Y( sh_out ) );
wire [31:0] Zero_extend = {31'b0, Sum[32]};
mux8 out_mux( .S ( ctrl[2:0] ),
.D0( A & B ),
.D1( A | B ),
.D2( A ^ B ),
.D3(~(A | B) ),
.D4( Sum[31:0] ),
.D5( 0 ), //mul?
.D6( sh_out ),
.D7( Zero_extend ),
.Y ( Y ) );
endmodule |
module shifter( input [1:0] S,
input [4:0] N,
input signed [31:0] A,
output [31:0] Y );
//sel[1]: 0 -- logical, 1 -- arithmetic
//sel[0]: 0 -- left, 1 --right
assign Y = S[1] ? (S[0] ? A >>> N : A <<< N) :
(S[0] ? A >> N : A << N);
endmodule |
module qqq_sum( input[31:0] A, B,
output[31:0] R,
input Cin );
//assign {Cout, R} = A + B + Cin;
assign R = A + B + Cin;
endmodule |
module rca_sum( input[31:0] A, B,
output[31:0] R,
input Cin,
output Cout );
wire c0, c1, c2, c3, c4, c5, c6, c7,
c8, c9, c10, c11, c12, c13, c14, c15,
c16, c17, c18, c19, c20, c21, c22, c23,
c24, c25, c26, c27, c28, c29, c30;
full_adder fa0(A[ 0], B[ 0], R[ 0], Cin, c0);
full_adder fa1(A[ 1], B[ 1], R[ 1], c0, c1);
full_adder fa2(A[ 2], B[ 2], R[ 2], c1, c2);
full_adder fa3(A[ 3], B[ 3], R[ 3], c2, c3);
full_adder fa4(A[ 4], B[ 4], R[ 4], c3, c4);
full_adder fa5(A[ 5], B[ 5], R[ 5], c4, c5);
full_adder fa6(A[ 6], B[ 6], R[ 6], c5, c6);
full_adder fa7(A[ 7], B[ 7], R[ 7], c6, c7);
full_adder fa8(A[ 8], B[ 8], R[ 8], c7, c8);
full_adder fa9(A[ 9], B[ 9], R[ 9], c8, c9);
full_adder fa10(A[10], B[10], R[10], c9, c10);
full_adder fa11(A[11], B[11], R[11], c10, c11);
full_adder fa12(A[12], B[12], R[12], c11, c12);
full_adder fa13(A[13], B[13], R[13], c12, c13);
full_adder fa14(A[14], B[14], R[14], c13, c14);
full_adder fa15(A[15], B[15], R[15], c14, c15);
full_adder fa16(A[16], B[16], R[16], c15, c16);
full_adder fa17(A[17], B[17], R[17], c16, c17);
full_adder fa18(A[18], B[18], R[18], c17, c18);
full_adder fa19(A[19], B[19], R[19], c18, c19);
full_adder fa20(A[20], B[20], R[20], c19, c20);
full_adder fa21(A[21], B[21], R[21], c20, c21);
full_adder fa22(A[22], B[22], R[22], c21, c22);
full_adder fa23(A[23], B[23], R[23], c22, c23);
full_adder fa24(A[24], B[24], R[24], c23, c24);
full_adder fa25(A[25], B[25], R[25], c24, c25);
full_adder fa26(A[26], B[26], R[26], c25, c26);
full_adder fa27(A[27], B[27], R[27], c26, c27);
full_adder fa28(A[28], B[28], R[28], c27, c28);
full_adder fa29(A[29], B[29], R[29], c28, c29);
full_adder fa30(A[30], B[30], R[30], c29, c30);
full_adder fa31(A[31], B[31], R[31], c30, Cout);
endmodule |
module full_adder( input A, B,
output S,
input Cin,
output Cout );
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule |
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
reg [31:0] reg_out;
assign avs_s0_readdata = reg_out;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] reg_value[8:0];
reg led_out;
reg [31:0] reg_res;
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read&Reg_Status_Write;
assign LEDR = led_out;
reg reg_module_caculation_end;
reg reg_modue_caculating_start;
reg reg_module_end;
reg reg_module_start;
convolution_core instance_convolution(.clk(clock_clk),
.reset(reset_reset),
.value0(reg_value[0]),
.value1(reg_value[1]),
.value2(reg_value[2]),
.value3(reg_value[3]),
.value4(reg_value[4]),
.value5(reg_value[5]),
.value6(reg_value[6]),
.value7(reg_value[7]),
.value8(reg_value[8]),
.caculating_start(reg_modue_caculating_start),
.caculating_done(reg_module_caculation_end),
.res_done(reg_module_end),
.ret(reg_res)
);
reg [3:0] reg_current_status, reg_next_status;
parameter IDLE = 4'b0001;
parameter CALCULATING = 4'b0010;
parameter WAITTING = 4'b0100;
parameter FINISH = 4'b1000;
// machine status
always@(posedge clock_clk)
begin
if(reset_reset)
reg_current_status <= IDLE;
else
reg_current_status <= reg_next_status;
end
// machine's next status
always@(reg_current_status or reg_read_done or reg_module_caculation_end or reg_write_done or reset_reset)
begin
if(reset_reset)
reg_next_status = IDLE;
else
begin
case(reg_current_status)
IDLE:reg_next_status = reg_read_done?CALCULATING:IDLE;
CALCULATING:reg_next_status = reg_module_caculation_end?WAITTING:CALCULATING;
WAITTING:reg_next_status = reg_write_done?FINISH:WAITTING;
FINISH: reg_next_status = IDLE;
default: reg_next_status = IDLE;
endcase
end
end
always@(posedge clock_clk) begin
if (reset_reset) begin
led_out <= 1'b0;
end else begin
case(reg_current_status)
IDLE: begin
reg_module_start<= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
end
CALCULATING: begin
led_out <= 1'b1;
reg_module_start <= 1'b1;
reg_modue_caculating_start <= 1'b1;
end
WAITTING:begin
reg_modue_caculating_start <= 1'b0;
reg_module_end <= 1'b1;
end
FINISH:begin
reg_module_start <= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
led_out <= 1'b0;
end
default:begin
end
endcase
end
end
// WRITE LOGIC
//
reg reg_read_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Write <= 1'b1;
reg_value[0] <= 32'h00000000;
reg_value[1] <= 32'h00000000;
reg_value[2] <= 32'h00000000;
reg_value[3] <= 32'h00000000;
reg_value[4] <= 32'h00000000;
reg_value[5] <= 32'h00000000;
reg_value[6] <= 32'h00000000;
reg_value[7] <= 32'h00000000;
reg_value[8] <= 32'h00000000;
reg_read_done <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
case (avs_s0_address[3:0])
4'b0000: reg_value[0] <= avs_s0_writedata;
4'b0001: reg_value[1] <= avs_s0_writedata;
4'b0010: reg_value[2] <= avs_s0_writedata;
4'b0011: reg_value[3] <= avs_s0_writedata;
4'b0100: reg_value[4] <= avs_s0_writedata;
4'b0101: reg_value[5] <= avs_s0_writedata;
4'b0110: reg_value[6] <= avs_s0_writedata;
4'b0111: reg_value[7] <= avs_s0_writedata;
4'b1000:begin
reg_value[8] <= avs_s0_writedata;
reg_read_done <= 1'b1; // read done;
end
endcase
Reg_Status_Write <= 1'b1;
end else if (avs_s0_waitrequest && avs_s0_write && reg_module_start == 1'b0)begin
Reg_Status_Write <= 1'b0;
end else begin
//revert reg_read_done to 0 at here when it's done /
if(reg_module_end) begin
reg_read_done <= 1'b0;
end
Reg_Status_Write <= 1'b1;
end
//
// x and z values are don't-care's
// READ LOGIC
reg reg_write_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b1;
reg_write_done <= 1'b1;
end else if(avs_s0_waitrequest && avs_s0_read && reg_module_caculation_end) begin
case (avs_s0_address[3:0])
4'b0000: reg_out <= reg_value[0];
4'b0001: reg_out <= reg_value[1];
4'b0010: reg_out <= reg_value[2];
4'b0011: reg_out <= reg_value[3];
4'b0100: reg_out <= reg_value[4];
4'b0101: reg_out <= reg_value[5];
4'b0110: reg_out <= reg_value[6];
4'b0111: reg_out <= reg_value[7];
4'b1000: reg_out <= reg_value[8];
4'b1001: reg_out <= reg_res;
default:reg_out <= 32'hffffffff;
endcase
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b1;
if (reg_module_end) begin
reg_write_done <= 1'b0;
end
end
endmodule |
module sky130_fd_sc_hdll__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule |
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_lp__dlrbn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule |
module GeAr_N8_R1_P6 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire intadd_29_CI, intadd_29_n5, intadd_29_n4, intadd_29_n3, intadd_29_n2,
intadd_29_n1, n2, n3, n4, n5, n6, n7, n8, n9, n10;
CMPR32X2TS intadd_29_U6 ( .A(in2[1]), .B(in1[1]), .C(intadd_29_CI), .CO(
intadd_29_n5), .S(res[1]) );
CMPR32X2TS intadd_29_U5 ( .A(in2[2]), .B(in1[2]), .C(intadd_29_n5), .CO(
intadd_29_n4), .S(res[2]) );
CMPR32X2TS intadd_29_U4 ( .A(in2[3]), .B(in1[3]), .C(intadd_29_n4), .CO(
intadd_29_n3), .S(res[3]) );
CMPR32X2TS intadd_29_U3 ( .A(in2[4]), .B(in1[4]), .C(intadd_29_n3), .CO(
intadd_29_n2), .S(res[4]) );
CMPR32X2TS intadd_29_U2 ( .A(in2[5]), .B(in1[5]), .C(intadd_29_n2), .CO(
intadd_29_n1), .S(res[5]) );
OAI211XLTS U2 ( .A0(in1[2]), .A1(in2[2]), .B0(in2[1]), .C0(in1[1]), .Y(n2)
);
CLKAND2X2TS U3 ( .A(in2[0]), .B(in1[0]), .Y(intadd_29_CI) );
XOR2XLTS U4 ( .A(n10), .B(in1[6]), .Y(res[6]) );
XOR2XLTS U5 ( .A(intadd_29_n1), .B(in2[6]), .Y(n10) );
OAI2BB2XLTS U6 ( .B0(n8), .B1(n7), .A0N(in1[6]), .A1N(in2[6]), .Y(n9) );
AOI222X1TS U7 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[5]), .B1(n6), .C0(in1[5]),
.C1(n6), .Y(n8) );
OAI2BB2X1TS U8 ( .B0(n5), .B1(n4), .A0N(in1[4]), .A1N(in2[4]), .Y(n6) );
OAI2BB1X1TS U9 ( .A0N(in2[2]), .A1N(in1[2]), .B0(n2), .Y(n3) );
AOI222X1TS U10 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[3]), .B1(n3), .C0(in1[3]),
.C1(n3), .Y(n5) );
NOR2XLTS U11 ( .A(in1[4]), .B(in2[4]), .Y(n4) );
NOR2XLTS U12 ( .A(in1[6]), .B(in2[6]), .Y(n7) );
CMPR32X2TS U13 ( .A(in1[7]), .B(in2[7]), .C(n9), .CO(res[8]), .S(res[7]) );
AOI2BB1XLTS U14 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_29_CI), .Y(res[0])
);
initial $sdf_annotate("GeAr_N8_R1_P6_syn.sdf");
endmodule |
module */
if (init_i)
next_state_s = WARMUP_e;
else
next_state_s = IDLE_e;
WARMUP_e:
/* Warm up the cipher */
if (cntr_r == 1151)
next_state_s = WAIT_PROC_e;
else
next_state_s = WARMUP_e;
WAIT_PROC_e:
if (proc_i) /* Calculation for current settings is being started */
next_state_s = PROC_e;
else if (init_i) /* Warmup phase, probably for new key o */
next_state_s = WARMUP_e;
else
next_state_s = WAIT_PROC_e;
PROC_e:
/* Process all 32 input data bits */
if (cntr_r == 31)
next_state_s = WAIT_PROC_e;
else
next_state_s = PROC_e;
default:
next_state_s = cur_state_r;
endcase
end
//////////////////////////////////////////////////////////////////////////////////
// State save and output logic of the FSM
//////////////////////////////////////////////////////////////////////////////////
always @(posedge clk_i or negedge n_rst_i) begin
if (!n_rst_i) begin
/* Reset registers driven here */
cntr_r <= 0;
cur_state_r <= IDLE_e;
cphr_en_r <= 1'b0;
dat_o <= 0;
dat_r <= 0;
end
else begin
/* State save logic */
cur_state_r <= next_state_s;
/* Output logic */
case (cur_state_r)
IDLE_e: begin
if (next_state_s == WARMUP_e) begin
/* Enable cipher and initialize */
cphr_en_r <= 1'b1;
end
end
WARMUP_e: begin
if (next_state_s == WAIT_PROC_e) begin
cntr_r <= 0;
cphr_en_r <= 1'b0;
end
else begin
/* Increment the warm-up phase counter */
cntr_r <= cntr_r + 1;
end
end
WAIT_PROC_e: begin
/* Wait until data to encrypt/decrypt is being presented */
if (next_state_s == PROC_e) begin
cphr_en_r <= 1'b1;
dat_r <= dat_i;
end
else if (next_state_s == WARMUP_e)
cphr_en_r <= 1'b1;
end
PROC_e: begin
if (next_state_s == WAIT_PROC_e) begin
cphr_en_r <= 1'b0;
cntr_r <= 0;
end
else
cntr_r <= cntr_r + 1;
/* Shift the input data register */
dat_r <= {1'b0, dat_r[31:1]};
/* Shift the output bits into the output register */
dat_o <= {bit_out_s, dat_o[31:1]};
end
endcase
end
end
endmodule |
module FIFO_SUM_IN_SQUARED (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [25:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [25:0] q;
endmodule |
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
reg [31:0] runnerm1;
reg [59:0] runnerq;
reg [89:0] runnerw;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
if (runner != 0) $stop; // Initial settlement failed
`endif
end
if (cyc==2) begin
runner = 20;
runnerq = 60'h0;
runnerw = 90'h0;
end
if (cyc==3) begin
if (runner != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but ensures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
runner = runnerm1;
runnerq = runnerq - 60'd1;
runnerw = runnerw - 90'd1;
$write ("[%0t] runner=%d\n", $time, runner);
end
end
endmodule |
module _4bit_mod8_counter_tb(
);
parameter COUNT = 100;
parameter DELAY = 10;
parameter TIME = COUNT*DELAY;
reg CP,reset,M;
wire [3:0] Q;
wire Qcc_n;
integer i;
_4bit_mod8_counter DUT (.CP(CP), .reset(reset), .M(M), .Q(Q), .Qcc_n(Qcc_n));
initial begin
#TIME $finish;
end
initial begin
CP = 0;
for (i = 0; i < COUNT; i = i + 1) begin
#DELAY CP = ~CP;
end
end
initial begin
reset = 1;
#(2*DELAY) reset = 0;
#(COUNT*DELAY/5) reset = 1;
#(COUNT*DELAY/5) reset = 0;
#(COUNT*DELAY/4) reset = 1;
#(2*DELAY) reset = 0;
end
initial begin
M = 1;
#(COUNT*DELAY/2) M = 0;
end
endmodule |
module sky130_fd_sc_hd__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule |
module regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);
input [31:0] Aselect;
input [31:0] Bselect;
input [31:0] Dselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
output [31:0] dbus;
input [2:0] S;
input Cin;
regfile reggie(
.Aselect(Aselect),
.Bselect(Bselect),
.Dselect(Dselect),
.dbus(dbus),
.bbus(bbus),
.abus(abus),
.clk(clk)
);
alupipe alup(
.S(S),
.Cin(Cin),
.clk(clk),
.abus(abus),
.bbus(bbus),
.dbus(dbus)
);
endmodule |
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
/*
Register index 0 is always supposed to be a 0 output, and only one select for
A, B, and D will be high at a time. Therefore, if the A or Bselect at index 0
is high, it means we can write all 0's to the corresponding bus. Otherwize
write z (don't touch it)
*/
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
//31 wide register (don't need one for index 0
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule |
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for dbus
input Bselect;//the select read bit for bbus
input Aselect;//the select read bit for abus
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;//wire for connectitng the clock to the dselect input
reg [31:0] data;
assign wireclk = clk & Dselect;//wireclk will only be high if both are high
always @(negedge wireclk) begin
data = dbus;
end
//only write to the output bus of it's select is high, otherwise write z
//(don't actually write anything)
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule |
module sky130_fd_sc_ms__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule |
module lcd_write_number_test
(
input CLK_50MHZ,
input ball_live,
output LCD_E,
output LCD_RS,
output LCD_RW,
output [3:0] LCD_D
);
wire if_ready;
reg if_write;
reg [31:0] if_data;
reg [1:0] state;
reg [31:0] cntr;
reg [31:0] cnt;
reg [7:0] hour, min, sec;
parameter IDLE = 2'b00,
IF_WRITE_1 = 2'b01,
SET_IF_WRITE_0 = 2'b10,
WAIT = 2'b11;
// Instantiate the Unit Under Test (UUT)
lcd_write_number uut
(
.CLK_50MHZ(CLK_50MHZ),
.LCD_E(LCD_E),
.LCD_RS(LCD_RS),
.LCD_RW(LCD_RW),
.LCD_D(LCD_D),
.if_data(if_data),
.if_write(if_write),
.if_ready(if_ready)
);
initial begin
if_data <= {8'haa,hour,min,sec};
state <= IDLE;
if_write <= 1'b0;
cntr <= 32'b0;
cnt <= 28'b0;
hour <= 0;
min <= 0;
sec <= 0;
end
always@ (posedge CLK_50MHZ) begin
case (state)
IDLE:
if (if_ready) begin
if_data <= {8'haa,hour,min,sec};
if_write <= 1'b1;
state <= IF_WRITE_1;
cntr <= 32'b0;
end
IF_WRITE_1: // this state to keep if_write up for 2 cycles
state <= SET_IF_WRITE_0;
SET_IF_WRITE_0: // set if_write 0 and start the counter
begin
if_write <= 1'b0;
state <= WAIT;
cntr <= 32'b0;
end
WAIT:
if (cntr < 25000000) // wait for 0.5 seconds
cntr <= cntr + 32'b1;
else
state <= IDLE;
endcase
end
always @ (posedge CLK_50MHZ)
if (cnt == 32'd49999999 || ball_live == 0)
cnt <= 0;
else cnt <= cnt+1;
always @ (posedge CLK_50MHZ)
if (cnt == 32'd49999999 && ball_live)
if (sec != 8'h59)
if (sec[3:0] == 4'h9)
sec <= sec +4'h7;
else sec <= sec+1'b1;
else begin
sec <= 8'b0;
if (min != 8'd59)
if (min[3:0] == 4'h9)
min <= min +4'h7;
else min <= min+1'b1;
else begin
min <= 8'b0;
hour <= hour +1'b1;
end
end
else if (~ball_live)begin
hour <= 0;
min <= 0;
sec <= 0;
end
endmodule |
module outputs
wire [4 : 0] input_arbs_0_select,
input_arbs_1_select,
input_arbs_2_select,
input_arbs_3_select,
input_arbs_4_select;
// value method input_arbs_0_select
assign input_arbs_0_select =
{ input_arbs_0_select_requests[4],
!input_arbs_0_select_requests[4] &&
input_arbs_0_select_requests[3],
!input_arbs_0_select_requests[4] &&
!input_arbs_0_select_requests[3] &&
input_arbs_0_select_requests[2],
!input_arbs_0_select_requests[4] &&
!input_arbs_0_select_requests[3] &&
!input_arbs_0_select_requests[2] &&
input_arbs_0_select_requests[1],
!input_arbs_0_select_requests[4] &&
!input_arbs_0_select_requests[3] &&
!input_arbs_0_select_requests[2] &&
!input_arbs_0_select_requests[1] &&
input_arbs_0_select_requests[0] } ;
// value method input_arbs_1_select
assign input_arbs_1_select =
{ !input_arbs_1_select_requests[0] &&
input_arbs_1_select_requests[4],
!input_arbs_1_select_requests[0] &&
!input_arbs_1_select_requests[4] &&
input_arbs_1_select_requests[3],
!input_arbs_1_select_requests[0] &&
!input_arbs_1_select_requests[4] &&
!input_arbs_1_select_requests[3] &&
input_arbs_1_select_requests[2],
!input_arbs_1_select_requests[0] &&
!input_arbs_1_select_requests[4] &&
!input_arbs_1_select_requests[3] &&
!input_arbs_1_select_requests[2] &&
input_arbs_1_select_requests[1],
input_arbs_1_select_requests[0] } ;
// value method input_arbs_2_select
assign input_arbs_2_select =
{ !input_arbs_2_select_requests[1] &&
!input_arbs_2_select_requests[0] &&
input_arbs_2_select_requests[4],
!input_arbs_2_select_requests[1] &&
!input_arbs_2_select_requests[0] &&
!input_arbs_2_select_requests[4] &&
input_arbs_2_select_requests[3],
!input_arbs_2_select_requests[1] &&
!input_arbs_2_select_requests[0] &&
!input_arbs_2_select_requests[4] &&
!input_arbs_2_select_requests[3] &&
input_arbs_2_select_requests[2],
input_arbs_2_select_requests[1],
!input_arbs_2_select_requests[1] &&
input_arbs_2_select_requests[0] } ;
// value method input_arbs_3_select
assign input_arbs_3_select =
{ !input_arbs_3_select_requests[2] &&
!input_arbs_3_select_requests[1] &&
!input_arbs_3_select_requests[0] &&
input_arbs_3_select_requests[4],
!input_arbs_3_select_requests[2] &&
!input_arbs_3_select_requests[1] &&
!input_arbs_3_select_requests[0] &&
!input_arbs_3_select_requests[4] &&
input_arbs_3_select_requests[3],
input_arbs_3_select_requests[2],
!input_arbs_3_select_requests[2] &&
input_arbs_3_select_requests[1],
!input_arbs_3_select_requests[2] &&
!input_arbs_3_select_requests[1] &&
input_arbs_3_select_requests[0] } ;
// value method input_arbs_4_select
assign input_arbs_4_select =
{ !input_arbs_4_select_requests[3] &&
!input_arbs_4_select_requests[2] &&
!input_arbs_4_select_requests[1] &&
!input_arbs_4_select_requests[0] &&
input_arbs_4_select_requests[4],
input_arbs_4_select_requests[3],
!input_arbs_4_select_requests[3] &&
input_arbs_4_select_requests[2],
!input_arbs_4_select_requests[3] &&
!input_arbs_4_select_requests[2] &&
input_arbs_4_select_requests[1],
!input_arbs_4_select_requests[3] &&
!input_arbs_4_select_requests[2] &&
!input_arbs_4_select_requests[1] &&
input_arbs_4_select_requests[0] } ;
endmodule |
module system_rgb888_to_g8_0_0_rgb888_to_g8
(g8,
clk,
rgb888);
output [7:0]g8;
input clk;
input [23:0]rgb888;
wire _carry__0_i_1_n_0;
wire _carry__0_i_2_n_0;
wire _carry__0_i_3_n_0;
wire _carry__0_i_4_n_0;
wire _carry__0_n_0;
wire _carry__0_n_1;
wire _carry__0_n_2;
wire _carry__0_n_3;
wire _carry__1_i_1_n_0;
wire _carry__1_n_2;
wire _carry_i_1_n_0;
wire _carry_i_2_n_0;
wire _carry_i_3_n_0;
wire _carry_i_4_n_0;
wire _carry_i_5_n_0;
wire _carry_n_0;
wire _carry_n_1;
wire _carry_n_2;
wire _carry_n_3;
wire clk;
wire [7:0]g8;
wire [7:0]g810_in;
wire g81__120_carry__0_i_1_n_0;
wire g81__120_carry__0_i_2_n_0;
wire g81__120_carry__0_i_3_n_0;
wire g81__120_carry__0_i_4_n_0;
wire g81__120_carry__0_n_0;
wire g81__120_carry__0_n_1;
wire g81__120_carry__0_n_2;
wire g81__120_carry__0_n_3;
wire g81__120_carry__0_n_4;
wire g81__120_carry__0_n_5;
wire g81__120_carry__0_n_6;
wire g81__120_carry__0_n_7;
wire g81__120_carry__1_i_1_n_0;
wire g81__120_carry__1_i_2_n_0;
wire g81__120_carry__1_i_3_n_0;
wire g81__120_carry__1_i_4_n_0;
wire g81__120_carry__1_n_0;
wire g81__120_carry__1_n_1;
wire g81__120_carry__1_n_2;
wire g81__120_carry__1_n_3;
wire g81__120_carry__1_n_4;
wire g81__120_carry__1_n_5;
wire g81__120_carry__1_n_6;
wire g81__120_carry__1_n_7;
wire g81__120_carry__2_i_1_n_0;
wire g81__120_carry__2_i_2_n_0;
wire g81__120_carry__2_n_1;
wire g81__120_carry__2_n_3;
wire g81__120_carry__2_n_6;
wire g81__120_carry__2_n_7;
wire g81__120_carry_i_1_n_0;
wire g81__120_carry_i_2_n_0;
wire g81__120_carry_i_3_n_0;
wire g81__120_carry_i_4_n_0;
wire g81__120_carry_i_5_n_0;
wire g81__120_carry_i_6_n_0;
wire g81__120_carry_n_0;
wire g81__120_carry_n_1;
wire g81__120_carry_n_2;
wire g81__120_carry_n_3;
wire g81__120_carry_n_4;
wire g81__120_carry_n_5;
wire g81__120_carry_n_6;
wire g81__149_carry__0_i_1_n_0;
wire g81__149_carry__0_i_2_n_0;
wire g81__149_carry__0_i_3_n_0;
wire g81__149_carry__0_i_4_n_0;
wire g81__149_carry__0_i_5_n_0;
wire g81__149_carry__0_i_6_n_0;
wire g81__149_carry__0_i_7_n_0;
wire g81__149_carry__0_i_8_n_0;
wire g81__149_carry__0_n_0;
wire g81__149_carry__0_n_1;
wire g81__149_carry__0_n_2;
wire g81__149_carry__0_n_3;
wire g81__149_carry__1_i_1_n_0;
wire g81__149_carry__1_i_2_n_0;
wire g81__149_carry__1_i_3_n_0;
wire g81__149_carry__1_i_4_n_0;
wire g81__149_carry__1_i_5_n_0;
wire g81__149_carry__1_i_6_n_0;
wire g81__149_carry__1_i_7_n_0;
wire g81__149_carry__1_i_8_n_0;
wire g81__149_carry__1_n_0;
wire g81__149_carry__1_n_1;
wire g81__149_carry__1_n_2;
wire g81__149_carry__1_n_3;
wire g81__149_carry__2_i_1_n_0;
wire g81__149_carry__2_i_2_n_0;
wire g81__149_carry__2_i_3_n_0;
wire g81__149_carry__2_i_4_n_0;
wire g81__149_carry__2_i_5_n_0;
wire g81__149_carry__2_i_6_n_0;
wire g81__149_carry__2_i_7_n_0;
wire g81__149_carry__2_i_8_n_0;
wire g81__149_carry__2_n_0;
wire g81__149_carry__2_n_1;
wire g81__149_carry__2_n_2;
wire g81__149_carry__2_n_3;
wire g81__149_carry__2_n_4;
wire g81__149_carry__2_n_5;
wire g81__149_carry__2_n_6;
wire g81__149_carry__2_n_7;
wire g81__149_carry__3_i_1_n_0;
wire g81__149_carry__3_i_2_n_0;
wire g81__149_carry__3_i_3_n_0;
wire g81__149_carry__3_i_4_n_0;
wire g81__149_carry__3_i_5_n_0;
wire g81__149_carry__3_n_0;
wire g81__149_carry__3_n_1;
wire g81__149_carry__3_n_2;
wire g81__149_carry__3_n_3;
wire g81__149_carry__3_n_4;
wire g81__149_carry__3_n_5;
wire g81__149_carry__3_n_6;
wire g81__149_carry__3_n_7;
wire g81__149_carry__4_i_1_n_0;
wire g81__149_carry__4_i_2_n_0;
wire g81__149_carry__4_i_3_n_0;
wire g81__149_carry__4_n_0;
wire g81__149_carry__4_n_2;
wire g81__149_carry__4_n_3;
wire g81__149_carry__4_n_5;
wire g81__149_carry__4_n_6;
wire g81__149_carry__4_n_7;
wire g81__149_carry_i_1_n_0;
wire g81__149_carry_i_2_n_0;
wire g81__149_carry_i_3_n_0;
wire g81__149_carry_i_4_n_0;
wire g81__149_carry_i_5_n_0;
wire g81__149_carry_i_6_n_0;
wire g81__149_carry_i_7_n_0;
wire g81__149_carry_n_0;
wire g81__149_carry_n_1;
wire g81__149_carry_n_2;
wire g81__149_carry_n_3;
wire g81__206_carry__0_i_1_n_0;
wire g81__206_carry__0_i_2_n_0;
wire g81__206_carry__0_i_3_n_0;
wire g81__206_carry__0_i_4_n_0;
wire g81__206_carry__0_i_5_n_0;
wire g81__206_carry__0_i_6_n_0;
wire g81__206_carry__0_i_7_n_0;
wire g81__206_carry__0_i_8_n_0;
wire g81__206_carry__0_n_0;
wire g81__206_carry__0_n_1;
wire g81__206_carry__0_n_2;
wire g81__206_carry__0_n_3;
wire g81__206_carry__1_i_1_n_0;
wire g81__206_carry__1_i_2_n_0;
wire g81__206_carry__1_i_3_n_0;
wire g81__206_carry__1_i_4_n_0;
wire g81__206_carry__1_i_5_n_0;
wire g81__206_carry__1_i_6_n_0;
wire g81__206_carry__1_i_7_n_0;
wire g81__206_carry__1_i_8_n_0;
wire g81__206_carry__1_n_0;
wire g81__206_carry__1_n_1;
wire g81__206_carry__1_n_2;
wire g81__206_carry__1_n_3;
wire g81__206_carry__2_i_1_n_0;
wire g81__206_carry__2_i_2_n_0;
wire g81__206_carry__2_i_3_n_0;
wire g81__206_carry__2_i_4_n_0;
wire g81__206_carry__2_i_5_n_0;
wire g81__206_carry__2_i_6_n_0;
wire g81__206_carry__2_i_7_n_0;
wire g81__206_carry__2_i_8_n_0;
wire g81__206_carry__2_n_0;
wire g81__206_carry__2_n_1;
wire g81__206_carry__2_n_2;
wire g81__206_carry__2_n_3;
wire g81__206_carry__2_n_4;
wire g81__206_carry__2_n_5;
wire g81__206_carry__2_n_6;
wire g81__206_carry__2_n_7;
wire g81__206_carry__3_i_1_n_0;
wire g81__206_carry__3_i_2_n_0;
wire g81__206_carry__3_i_3_n_0;
wire g81__206_carry__3_i_4_n_0;
wire g81__206_carry__3_i_5_n_0;
wire g81__206_carry__3_i_6_n_0;
wire g81__206_carry__3_i_7_n_0;
wire g81__206_carry__3_i_8_n_0;
wire g81__206_carry__3_n_0;
wire g81__206_carry__3_n_1;
wire g81__206_carry__3_n_2;
wire g81__206_carry__3_n_3;
wire g81__206_carry__3_n_4;
wire g81__206_carry__3_n_5;
wire g81__206_carry__3_n_6;
wire g81__206_carry__3_n_7;
wire g81__206_carry__4_i_1_n_0;
wire g81__206_carry__4_i_2_n_0;
wire g81__206_carry__4_i_3_n_0;
wire g81__206_carry__4_i_4_n_0;
wire g81__206_carry__4_i_5_n_0;
wire g81__206_carry__4_i_6_n_0;
wire g81__206_carry__4_n_0;
wire g81__206_carry__4_n_2;
wire g81__206_carry__4_n_3;
wire g81__206_carry__4_n_5;
wire g81__206_carry__4_n_6;
wire g81__206_carry__4_n_7;
wire g81__206_carry_i_1_n_0;
wire g81__206_carry_i_2_n_0;
wire g81__206_carry_i_3_n_0;
wire g81__206_carry_i_4_n_0;
wire g81__206_carry_i_5_n_0;
wire g81__206_carry_i_6_n_0;
wire g81__206_carry_i_7_n_0;
wire g81__206_carry_n_0;
wire g81__206_carry_n_1;
wire g81__206_carry_n_2;
wire g81__206_carry_n_3;
wire g81__22_carry__0_i_1_n_0;
wire g81__22_carry__0_i_2_n_0;
wire g81__22_carry__0_i_3_n_0;
wire g81__22_carry__0_i_4_n_0;
wire g81__22_carry__0_n_0;
wire g81__22_carry__0_n_1;
wire g81__22_carry__0_n_2;
wire g81__22_carry__0_n_3;
wire g81__22_carry__0_n_4;
wire g81__22_carry__0_n_5;
wire g81__22_carry__0_n_6;
wire g81__22_carry__0_n_7;
wire g81__22_carry__1_i_1_n_0;
wire g81__22_carry__1_i_2_n_0;
wire g81__22_carry__1_i_3_n_0;
wire g81__22_carry__1_i_4_n_0;
wire g81__22_carry__1_n_0;
wire g81__22_carry__1_n_1;
wire g81__22_carry__1_n_2;
wire g81__22_carry__1_n_3;
wire g81__22_carry__1_n_4;
wire g81__22_carry__1_n_5;
wire g81__22_carry__1_n_6;
wire g81__22_carry__1_n_7;
wire g81__22_carry__2_i_1_n_0;
wire g81__22_carry__2_i_2_n_0;
wire g81__22_carry__2_n_1;
wire g81__22_carry__2_n_3;
wire g81__22_carry__2_n_6;
wire g81__22_carry__2_n_7;
wire g81__22_carry_i_1_n_0;
wire g81__22_carry_i_2_n_0;
wire g81__22_carry_i_3_n_0;
wire g81__22_carry_i_4_n_0;
wire g81__22_carry_i_5_n_0;
wire g81__22_carry_i_6_n_0;
wire g81__22_carry_n_0;
wire g81__22_carry_n_1;
wire g81__22_carry_n_2;
wire g81__22_carry_n_3;
wire g81__22_carry_n_4;
wire g81__22_carry_n_5;
wire g81__22_carry_n_6;
wire g81__261_carry__0_i_1_n_0;
wire g81__261_carry__0_i_2_n_0;
wire g81__261_carry__0_i_3_n_0;
wire g81__261_carry__0_i_4_n_0;
wire g81__261_carry__0_n_0;
wire g81__261_carry__0_n_1;
wire g81__261_carry__0_n_2;
wire g81__261_carry__0_n_3;
wire g81__261_carry__0_n_4;
wire g81__261_carry__0_n_5;
wire g81__261_carry__0_n_6;
wire g81__261_carry__0_n_7;
wire g81__261_carry__1_i_1_n_0;
wire g81__261_carry__1_i_2_n_0;
wire g81__261_carry__1_i_3_n_0;
wire g81__261_carry__1_i_4_n_0;
wire g81__261_carry__1_n_0;
wire g81__261_carry__1_n_1;
wire g81__261_carry__1_n_2;
wire g81__261_carry__1_n_3;
wire g81__261_carry__1_n_4;
wire g81__261_carry__1_n_5;
wire g81__261_carry__1_n_6;
wire g81__261_carry__1_n_7;
wire g81__261_carry__2_i_1_n_0;
wire g81__261_carry__2_i_2_n_0;
wire g81__261_carry__2_n_1;
wire g81__261_carry__2_n_3;
wire g81__261_carry__2_n_6;
wire g81__261_carry__2_n_7;
wire g81__261_carry_i_1_n_0;
wire g81__261_carry_i_2_n_0;
wire g81__261_carry_i_3_n_0;
wire g81__261_carry_i_4_n_0;
wire g81__261_carry_n_0;
wire g81__261_carry_n_1;
wire g81__261_carry_n_2;
wire g81__261_carry_n_3;
wire g81__261_carry_n_4;
wire g81__261_carry_n_5;
wire g81__261_carry_n_6;
wire g81__261_carry_n_7;
wire g81__301_carry__0_i_1_n_0;
wire g81__301_carry__0_i_2_n_0;
wire g81__301_carry__0_i_3_n_0;
wire g81__301_carry__0_i_4_n_0;
wire g81__301_carry__0_i_5_n_0;
wire g81__301_carry__0_i_6_n_0;
wire g81__301_carry__0_i_7_n_0;
wire g81__301_carry__0_i_8_n_0;
wire g81__301_carry__0_n_0;
wire g81__301_carry__0_n_1;
wire g81__301_carry__0_n_2;
wire g81__301_carry__0_n_3;
wire g81__301_carry__1_i_1_n_0;
wire g81__301_carry__1_i_2_n_0;
wire g81__301_carry__1_i_3_n_0;
wire g81__301_carry__1_i_4_n_0;
wire g81__301_carry__1_i_5_n_0;
wire g81__301_carry__1_i_6_n_0;
wire g81__301_carry__1_i_7_n_0;
wire g81__301_carry__1_i_8_n_0;
wire g81__301_carry__1_i_9_n_0;
wire g81__301_carry__1_n_0;
wire g81__301_carry__1_n_1;
wire g81__301_carry__1_n_2;
wire g81__301_carry__1_n_3;
wire g81__301_carry__2_i_1_n_0;
wire g81__301_carry__2_i_2_n_0;
wire g81__301_carry__2_i_3_n_0;
wire g81__301_carry__2_i_4_n_0;
wire g81__301_carry__2_i_5_n_0;
wire g81__301_carry__2_i_6_n_0;
wire g81__301_carry__2_i_7_n_0;
wire g81__301_carry__2_i_8_n_0;
wire g81__301_carry__2_n_0;
wire g81__301_carry__2_n_1;
wire g81__301_carry__2_n_2;
wire g81__301_carry__2_n_3;
wire g81__301_carry__3_i_1_n_0;
wire g81__301_carry__3_i_2_n_0;
wire g81__301_carry__3_i_3_n_0;
wire g81__301_carry__3_i_4_n_0;
wire g81__301_carry__3_i_5_n_0;
wire g81__301_carry__3_i_6_n_0;
wire g81__301_carry__3_i_7_n_0;
wire g81__301_carry__3_i_8_n_0;
wire g81__301_carry__3_n_0;
wire g81__301_carry__3_n_1;
wire g81__301_carry__3_n_2;
wire g81__301_carry__3_n_3;
wire g81__301_carry__4_i_1_n_0;
wire g81__301_carry__4_i_2_n_0;
wire g81__301_carry__4_i_3_n_0;
wire g81__301_carry__4_i_4_n_0;
wire g81__301_carry__4_i_5_n_0;
wire g81__301_carry__4_i_6_n_0;
wire g81__301_carry__4_i_7_n_0;
wire g81__301_carry__4_i_8_n_0;
wire g81__301_carry__4_n_0;
wire g81__301_carry__4_n_1;
wire g81__301_carry__4_n_2;
wire g81__301_carry__4_n_3;
wire g81__301_carry__5_i_1_n_0;
wire g81__301_carry__5_i_2_n_0;
wire g81__301_carry__5_i_3_n_0;
wire g81__301_carry__5_i_4_n_0;
wire g81__301_carry__5_i_5_n_0;
wire g81__301_carry__5_i_6_n_0;
wire g81__301_carry__5_i_7_n_0;
wire g81__301_carry__5_i_8_n_0;
wire g81__301_carry__5_n_0;
wire g81__301_carry__5_n_1;
wire g81__301_carry__5_n_2;
wire g81__301_carry__5_n_3;
wire g81__301_carry__6_i_1_n_0;
wire g81__301_carry__6_i_2_n_0;
wire g81__301_carry__6_i_3_n_0;
wire g81__301_carry__6_i_4_n_0;
wire g81__301_carry__6_i_5_n_0;
wire g81__301_carry__6_i_6_n_0;
wire g81__301_carry__6_n_1;
wire g81__301_carry__6_n_2;
wire g81__301_carry__6_n_3;
wire g81__301_carry_i_1_n_0;
wire g81__301_carry_i_2_n_0;
wire g81__301_carry_i_3_n_0;
wire g81__301_carry_i_4_n_0;
wire g81__301_carry_i_5_n_0;
wire g81__301_carry_i_6_n_0;
wire g81__301_carry_i_7_n_0;
wire g81__301_carry_n_0;
wire g81__301_carry_n_1;
wire g81__301_carry_n_2;
wire g81__301_carry_n_3;
wire g81__347_carry__0_i_1_n_0;
wire g81__347_carry__0_i_2_n_0;
wire g81__347_carry__0_i_3_n_0;
wire g81__347_carry__0_i_4_n_0;
wire g81__347_carry__0_n_1;
wire g81__347_carry__0_n_2;
wire g81__347_carry__0_n_3;
wire g81__347_carry__0_n_4;
wire g81__347_carry__0_n_5;
wire g81__347_carry__0_n_6;
wire g81__347_carry__0_n_7;
wire g81__347_carry_i_1_n_0;
wire g81__347_carry_i_2_n_0;
wire g81__347_carry_i_3_n_0;
wire g81__347_carry_i_4_n_0;
wire g81__347_carry_n_0;
wire g81__347_carry_n_1;
wire g81__347_carry_n_2;
wire g81__347_carry_n_3;
wire g81__347_carry_n_4;
wire g81__347_carry_n_5;
wire g81__347_carry_n_6;
wire g81__347_carry_n_7;
wire g81__53_carry__0_i_1_n_0;
wire g81__53_carry__0_i_2_n_0;
wire g81__53_carry__0_i_3_n_0;
wire g81__53_carry__0_i_4_n_0;
wire g81__53_carry__0_n_0;
wire g81__53_carry__0_n_1;
wire g81__53_carry__0_n_2;
wire g81__53_carry__0_n_3;
wire g81__53_carry__0_n_4;
wire g81__53_carry__0_n_5;
wire g81__53_carry__0_n_6;
wire g81__53_carry__0_n_7;
wire g81__53_carry__1_i_1_n_0;
wire g81__53_carry__1_i_2_n_0;
wire g81__53_carry__1_i_3_n_0;
wire g81__53_carry__1_i_4_n_0;
wire g81__53_carry__1_n_0;
wire g81__53_carry__1_n_1;
wire g81__53_carry__1_n_2;
wire g81__53_carry__1_n_3;
wire g81__53_carry__1_n_4;
wire g81__53_carry__1_n_5;
wire g81__53_carry__1_n_6;
wire g81__53_carry__1_n_7;
wire g81__53_carry__2_i_1_n_0;
wire g81__53_carry__2_i_2_n_0;
wire g81__53_carry__2_n_1;
wire g81__53_carry__2_n_3;
wire g81__53_carry__2_n_6;
wire g81__53_carry__2_n_7;
wire g81__53_carry_i_1_n_0;
wire g81__53_carry_i_2_n_0;
wire g81__53_carry_i_3_n_0;
wire g81__53_carry_i_4_n_0;
wire g81__53_carry_i_5_n_0;
wire g81__53_carry_i_6_n_0;
wire g81__53_carry_n_0;
wire g81__53_carry_n_1;
wire g81__53_carry_n_2;
wire g81__53_carry_n_3;
wire g81__53_carry_n_4;
wire g81__53_carry_n_5;
wire g81__53_carry_n_6;
wire g81__92_carry__0_i_1_n_0;
wire g81__92_carry__0_i_2_n_0;
wire g81__92_carry__0_i_3_n_0;
wire g81__92_carry__0_i_4_n_0;
wire g81__92_carry__0_n_0;
wire g81__92_carry__0_n_1;
wire g81__92_carry__0_n_2;
wire g81__92_carry__0_n_3;
wire g81__92_carry__0_n_4;
wire g81__92_carry__0_n_5;
wire g81__92_carry__0_n_6;
wire g81__92_carry__0_n_7;
wire g81__92_carry__1_i_1_n_0;
wire g81__92_carry__1_i_2_n_0;
wire g81__92_carry__1_i_3_n_0;
wire g81__92_carry__1_i_4_n_0;
wire g81__92_carry__1_n_0;
wire g81__92_carry__1_n_1;
wire g81__92_carry__1_n_2;
wire g81__92_carry__1_n_3;
wire g81__92_carry__1_n_4;
wire g81__92_carry__1_n_5;
wire g81__92_carry__1_n_6;
wire g81__92_carry__1_n_7;
wire g81__92_carry__2_i_1_n_0;
wire g81__92_carry__2_i_2_n_0;
wire g81__92_carry__2_n_1;
wire g81__92_carry__2_n_3;
wire g81__92_carry__2_n_6;
wire g81__92_carry__2_n_7;
wire g81__92_carry_i_1_n_0;
wire g81__92_carry_i_2_n_0;
wire g81__92_carry_i_3_n_0;
wire g81__92_carry_i_4_n_0;
wire g81__92_carry_i_5_n_0;
wire g81__92_carry_i_6_n_0;
wire g81__92_carry_n_0;
wire g81__92_carry_n_1;
wire g81__92_carry_n_2;
wire g81__92_carry_n_3;
wire g81__92_carry_n_4;
wire g81__92_carry_n_5;
wire g81__92_carry_n_6;
wire g81_carry__0_i_10_n_0;
wire g81_carry__0_i_11_n_0;
wire g81_carry__0_i_12_n_0;
wire g81_carry__0_i_13_n_0;
wire g81_carry__0_i_14_n_0;
wire g81_carry__0_i_15_n_0;
wire g81_carry__0_i_1_n_0;
wire g81_carry__0_i_2_n_0;
wire g81_carry__0_i_3_n_0;
wire g81_carry__0_i_4_n_0;
wire g81_carry__0_i_5_n_0;
wire g81_carry__0_i_6_n_0;
wire g81_carry__0_i_7_n_0;
wire g81_carry__0_i_8_n_0;
wire g81_carry__0_i_9_n_0;
wire g81_carry__0_n_0;
wire g81_carry__0_n_1;
wire g81_carry__0_n_2;
wire g81_carry__0_n_3;
wire g81_carry__0_n_4;
wire g81_carry__0_n_5;
wire g81_carry__0_n_6;
wire g81_carry__1_i_1_n_0;
wire g81_carry__1_i_2_n_0;
wire g81_carry__1_i_3_n_0;
wire g81_carry__1_i_4_n_0;
wire g81_carry__1_i_5_n_0;
wire g81_carry__1_i_6_n_0;
wire g81_carry__1_i_7_n_0;
wire g81_carry__1_i_8_n_0;
wire g81_carry__1_i_9_n_0;
wire g81_carry__1_n_0;
wire g81_carry__1_n_1;
wire g81_carry__1_n_2;
wire g81_carry__1_n_3;
wire g81_carry__1_n_4;
wire g81_carry__1_n_5;
wire g81_carry__1_n_6;
wire g81_carry__1_n_7;
wire g81_carry__2_i_1_n_0;
wire g81_carry__2_i_2_n_0;
wire g81_carry__2_i_3_n_0;
wire g81_carry__2_n_1;
wire g81_carry__2_n_3;
wire g81_carry__2_n_6;
wire g81_carry__2_n_7;
wire g81_carry_i_1_n_0;
wire g81_carry_i_2_n_0;
wire g81_carry_i_3_n_0;
wire g81_carry_i_4_n_0;
wire g81_carry_i_5_n_0;
wire g81_carry_i_6_n_0;
wire g81_carry_i_7_n_0;
wire g81_carry_n_0;
wire g81_carry_n_1;
wire g81_carry_n_2;
wire g81_carry_n_3;
wire g81_carry_n_7;
wire [9:1]g83;
wire g83__0_carry__0_i_1_n_0;
wire g83__0_carry__0_i_2_n_0;
wire g83__0_carry__0_i_3_n_0;
wire g83__0_carry__0_i_4_n_0;
wire g83__0_carry__0_i_5_n_0;
wire g83__0_carry__0_i_6_n_0;
wire g83__0_carry__0_i_7_n_0;
wire g83__0_carry__0_i_8_n_0;
wire g83__0_carry__0_n_0;
wire g83__0_carry__0_n_1;
wire g83__0_carry__0_n_2;
wire g83__0_carry__0_n_3;
wire g83__0_carry__0_n_4;
wire g83__0_carry__0_n_5;
wire g83__0_carry__0_n_6;
wire g83__0_carry__0_n_7;
wire g83__0_carry__1_i_1_n_0;
wire g83__0_carry__1_n_2;
wire g83__0_carry__1_n_7;
wire g83__0_carry_i_1_n_0;
wire g83__0_carry_i_2_n_0;
wire g83__0_carry_i_3_n_0;
wire g83__0_carry_i_4_n_0;
wire g83__0_carry_i_5_n_0;
wire g83__0_carry_i_6_n_0;
wire g83__0_carry_i_7_n_0;
wire g83__0_carry_n_0;
wire g83__0_carry_n_1;
wire g83__0_carry_n_2;
wire g83__0_carry_n_3;
wire g83__0_carry_n_4;
wire g83__0_carry_n_5;
wire g83__0_carry_n_6;
wire g83__0_carry_n_7;
wire g84;
wire g84_carry__0_i_1_n_0;
wire g84_carry__0_i_2_n_0;
wire g84_carry_i_1_n_0;
wire g84_carry_i_2_n_0;
wire g84_carry_i_3_n_0;
wire g84_carry_i_4_n_0;
wire g84_carry_i_5_n_0;
wire g84_carry_i_6_n_0;
wire g84_carry_i_7_n_0;
wire g84_carry_i_8_n_0;
wire g84_carry_n_0;
wire g84_carry_n_1;
wire g84_carry_n_2;
wire g84_carry_n_3;
wire [23:0]rgb888;
wire [3:0]NLW__carry__1_CO_UNCONNECTED;
wire [3:1]NLW__carry__1_O_UNCONNECTED;
wire [0:0]NLW_g81__120_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__120_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__120_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g81__149_carry_O_UNCONNECTED;
wire [3:0]NLW_g81__149_carry__0_O_UNCONNECTED;
wire [3:0]NLW_g81__149_carry__1_O_UNCONNECTED;
wire [2:2]NLW_g81__149_carry__4_CO_UNCONNECTED;
wire [3:3]NLW_g81__149_carry__4_O_UNCONNECTED;
wire [3:0]NLW_g81__206_carry_O_UNCONNECTED;
wire [3:0]NLW_g81__206_carry__0_O_UNCONNECTED;
wire [3:0]NLW_g81__206_carry__1_O_UNCONNECTED;
wire [2:2]NLW_g81__206_carry__4_CO_UNCONNECTED;
wire [3:3]NLW_g81__206_carry__4_O_UNCONNECTED;
wire [0:0]NLW_g81__22_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__22_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__22_carry__2_O_UNCONNECTED;
wire [3:1]NLW_g81__261_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__261_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__0_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__1_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__3_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__4_O_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__5_O_UNCONNECTED;
wire [3:3]NLW_g81__301_carry__6_CO_UNCONNECTED;
wire [3:0]NLW_g81__301_carry__6_O_UNCONNECTED;
wire [3:3]NLW_g81__347_carry__0_CO_UNCONNECTED;
wire [0:0]NLW_g81__53_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__53_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__53_carry__2_O_UNCONNECTED;
wire [0:0]NLW_g81__92_carry_O_UNCONNECTED;
wire [3:1]NLW_g81__92_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81__92_carry__2_O_UNCONNECTED;
wire [3:1]NLW_g81_carry_O_UNCONNECTED;
wire [0:0]NLW_g81_carry__0_O_UNCONNECTED;
wire [3:1]NLW_g81_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_g81_carry__2_O_UNCONNECTED;
wire [3:0]NLW_g83__0_carry__1_CO_UNCONNECTED;
wire [3:1]NLW_g83__0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_g84_carry_O_UNCONNECTED;
wire [3:1]NLW_g84_carry__0_CO_UNCONNECTED;
wire [3:0]NLW_g84_carry__0_O_UNCONNECTED;
CARRY4 _carry
(.CI(1'b0),
.CO({_carry_n_0,_carry_n_1,_carry_n_2,_carry_n_3}),
.CYINIT(_carry_i_1_n_0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(g83[4:1]),
.S({_carry_i_2_n_0,_carry_i_3_n_0,_carry_i_4_n_0,_carry_i_5_n_0}));
CARRY4 _carry__0
(.CI(_carry_n_0),
.CO({_carry__0_n_0,_carry__0_n_1,_carry__0_n_2,_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(g83[8:5]),
.S({_carry__0_i_1_n_0,_carry__0_i_2_n_0,_carry__0_i_3_n_0,_carry__0_i_4_n_0}));
LUT1 #(
.INIT(2'h1))
_carry__0_i_1
(.I0(g83__0_carry__1_n_7),
.O(_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h1))
_carry__0_i_2
(.I0(g83__0_carry__0_n_4),
.O(_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h1))
_carry__0_i_3
(.I0(g83__0_carry__0_n_5),
.O(_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h1))
_carry__0_i_4
(.I0(g83__0_carry__0_n_6),
.O(_carry__0_i_4_n_0));
CARRY4 _carry__1
(.CI(_carry__0_n_0),
.CO({NLW__carry__1_CO_UNCONNECTED[3:2],_carry__1_n_2,NLW__carry__1_CO_UNCONNECTED[0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__carry__1_O_UNCONNECTED[3:1],g83[9]}),
.S({1'b0,1'b0,1'b1,_carry__1_i_1_n_0}));
LUT1 #(
.INIT(2'h1))
_carry__1_i_1
(.I0(g83__0_carry__1_n_2),
.O(_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_1
(.I0(g83__0_carry_n_7),
.O(_carry_i_1_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_2
(.I0(g83__0_carry__0_n_7),
.O(_carry_i_2_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_3
(.I0(g83__0_carry_n_4),
.O(_carry_i_3_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_4
(.I0(g83__0_carry_n_5),
.O(_carry_i_4_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_5
(.I0(g83__0_carry_n_6),
.O(_carry_i_5_n_0));
CARRY4 g81__120_carry
(.CI(1'b0),
.CO({g81__120_carry_n_0,g81__120_carry_n_1,g81__120_carry_n_2,g81__120_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__120_carry_i_1_n_0,g81__120_carry_i_2_n_0,1'b0}),
.O({g81__120_carry_n_4,g81__120_carry_n_5,g81__120_carry_n_6,NLW_g81__120_carry_O_UNCONNECTED[0]}),
.S({g81__120_carry_i_3_n_0,g81__120_carry_i_4_n_0,g81__120_carry_i_5_n_0,g81__120_carry_i_6_n_0}));
CARRY4 g81__120_carry__0
(.CI(g81__120_carry_n_0),
.CO({g81__120_carry__0_n_0,g81__120_carry__0_n_1,g81__120_carry__0_n_2,g81__120_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__120_carry__0_n_4,g81__120_carry__0_n_5,g81__120_carry__0_n_6,g81__120_carry__0_n_7}),
.S({g81__120_carry__0_i_1_n_0,g81__120_carry__0_i_2_n_0,g81__120_carry__0_i_3_n_0,g81__120_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__120_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__120_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__120_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__120_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__120_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__120_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__120_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__120_carry__0_i_4_n_0));
CARRY4 g81__120_carry__1
(.CI(g81__120_carry__0_n_0),
.CO({g81__120_carry__1_n_0,g81__120_carry__1_n_1,g81__120_carry__1_n_2,g81__120_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__120_carry__1_n_4,g81__120_carry__1_n_5,g81__120_carry__1_n_6,g81__120_carry__1_n_7}),
.S({g81__120_carry__1_i_1_n_0,g81__120_carry__1_i_2_n_0,g81__120_carry__1_i_3_n_0,g81__120_carry__1_i_4_n_0}));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h369C))
g81__120_carry__1_i_1
(.I0(g84),
.I1(g81_carry__1_i_1_n_0),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__120_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__120_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__120_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__120_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__120_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__120_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__120_carry__1_i_4_n_0));
CARRY4 g81__120_carry__2
(.CI(g81__120_carry__1_n_0),
.CO({NLW_g81__120_carry__2_CO_UNCONNECTED[3],g81__120_carry__2_n_1,NLW_g81__120_carry__2_CO_UNCONNECTED[1],g81__120_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__120_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__120_carry__2_O_UNCONNECTED[3:2],g81__120_carry__2_n_6,g81__120_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__120_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__120_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__120_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__120_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__120_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__120_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__120_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__120_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__120_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__120_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__120_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__120_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__120_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__120_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__120_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__120_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__120_carry_i_6_n_0));
CARRY4 g81__149_carry
(.CI(1'b0),
.CO({g81__149_carry_n_0,g81__149_carry_n_1,g81__149_carry_n_2,g81__149_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__149_carry_i_1_n_0,g81__149_carry_i_2_n_0,g81__149_carry_i_3_n_0,1'b0}),
.O(NLW_g81__149_carry_O_UNCONNECTED[3:0]),
.S({g81__149_carry_i_4_n_0,g81__149_carry_i_5_n_0,g81__149_carry_i_6_n_0,g81__149_carry_i_7_n_0}));
CARRY4 g81__149_carry__0
(.CI(g81__149_carry_n_0),
.CO({g81__149_carry__0_n_0,g81__149_carry__0_n_1,g81__149_carry__0_n_2,g81__149_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__149_carry__0_i_1_n_0,g81__149_carry__0_i_2_n_0,g81__149_carry__0_i_3_n_0,g81__149_carry__0_i_4_n_0}),
.O(NLW_g81__149_carry__0_O_UNCONNECTED[3:0]),
.S({g81__149_carry__0_i_5_n_0,g81__149_carry__0_i_6_n_0,g81__149_carry__0_i_7_n_0,g81__149_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__0_i_1
(.I0(g83__0_carry_n_7),
.I1(g81__22_carry__0_n_6),
.I2(g81_carry__1_n_4),
.O(g81__149_carry__0_i_1_n_0));
(* HLUTNM = "lutpair27" *)
LUT2 #(
.INIT(4'h8))
g81__149_carry__0_i_2
(.I0(g81__22_carry__0_n_7),
.I1(g81_carry__1_n_5),
.O(g81__149_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry__0_i_3
(.I0(g81_carry__1_n_6),
.I1(g81__22_carry_n_4),
.O(g81__149_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry__0_i_4
(.I0(g81_carry__1_n_7),
.I1(g81__22_carry_n_5),
.O(g81__149_carry__0_i_4_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__0_i_5
(.I0(g81_carry__0_i_11_n_0),
.I1(g81__22_carry__0_n_5),
.I2(g81_carry__2_n_7),
.I3(g81__149_carry__0_i_1_n_0),
.O(g81__149_carry__0_i_5_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__0_i_6
(.I0(g83__0_carry_n_7),
.I1(g81__22_carry__0_n_6),
.I2(g81_carry__1_n_4),
.I3(g81__149_carry__0_i_2_n_0),
.O(g81__149_carry__0_i_6_n_0));
(* HLUTNM = "lutpair27" *)
LUT4 #(
.INIT(16'h9666))
g81__149_carry__0_i_7
(.I0(g81__22_carry__0_n_7),
.I1(g81_carry__1_n_5),
.I2(g81_carry__1_n_6),
.I3(g81__22_carry_n_4),
.O(g81__149_carry__0_i_7_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry__0_i_8
(.I0(g81_carry__1_n_7),
.I1(g81__22_carry_n_5),
.I2(g81__22_carry_n_4),
.I3(g81_carry__1_n_6),
.O(g81__149_carry__0_i_8_n_0));
CARRY4 g81__149_carry__1
(.CI(g81__149_carry__0_n_0),
.CO({g81__149_carry__1_n_0,g81__149_carry__1_n_1,g81__149_carry__1_n_2,g81__149_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81__149_carry__1_i_1_n_0,g81__149_carry__1_i_2_n_0,g81__149_carry__1_i_3_n_0,g81__149_carry__1_i_4_n_0}),
.O(NLW_g81__149_carry__1_O_UNCONNECTED[3:0]),
.S({g81__149_carry__1_i_5_n_0,g81__149_carry__1_i_6_n_0,g81__149_carry__1_i_7_n_0,g81__149_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__1_i_1
(.I0(g81__53_carry_n_4),
.I1(g81__22_carry__1_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__1_i_1_n_0));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__1_i_2
(.I0(g81__53_carry_n_5),
.I1(g81__22_carry__1_n_7),
.I2(g81_carry__2_n_1),
.O(g81__149_carry__1_i_2_n_0));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__1_i_3
(.I0(g81__53_carry_n_6),
.I1(g81__22_carry__0_n_4),
.I2(g81_carry__2_n_6),
.O(g81__149_carry__1_i_3_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hE8))
g81__149_carry__1_i_4
(.I0(g81_carry__0_i_11_n_0),
.I1(g81__22_carry__0_n_5),
.I2(g81_carry__2_n_7),
.O(g81__149_carry__1_i_4_n_0));
(* HLUTNM = "lutpair13" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__1_i_5
(.I0(g81__53_carry__0_n_7),
.I1(g81__22_carry__1_n_5),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__1_i_1_n_0),
.O(g81__149_carry__1_i_5_n_0));
(* HLUTNM = "lutpair12" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__1_i_6
(.I0(g81__53_carry_n_4),
.I1(g81__22_carry__1_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__1_i_2_n_0),
.O(g81__149_carry__1_i_6_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__1_i_7
(.I0(g81__53_carry_n_5),
.I1(g81__22_carry__1_n_7),
.I2(g81_carry__2_n_1),
.I3(g81__149_carry__1_i_3_n_0),
.O(g81__149_carry__1_i_7_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h6996))
g81__149_carry__1_i_8
(.I0(g81__53_carry_n_6),
.I1(g81__22_carry__0_n_4),
.I2(g81_carry__2_n_6),
.I3(g81__149_carry__1_i_4_n_0),
.O(g81__149_carry__1_i_8_n_0));
CARRY4 g81__149_carry__2
(.CI(g81__149_carry__1_n_0),
.CO({g81__149_carry__2_n_0,g81__149_carry__2_n_1,g81__149_carry__2_n_2,g81__149_carry__2_n_3}),
.CYINIT(1'b0),
.DI({g81__149_carry__2_i_1_n_0,g81__149_carry__2_i_2_n_0,g81__149_carry__2_i_3_n_0,g81__149_carry__2_i_4_n_0}),
.O({g81__149_carry__2_n_4,g81__149_carry__2_n_5,g81__149_carry__2_n_6,g81__149_carry__2_n_7}),
.S({g81__149_carry__2_i_5_n_0,g81__149_carry__2_i_6_n_0,g81__149_carry__2_i_7_n_0,g81__149_carry__2_i_8_n_0}));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_1
(.I0(g81__53_carry__0_n_4),
.I1(g81__22_carry__2_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_1_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_2
(.I0(g81__53_carry__0_n_5),
.I1(g81__22_carry__2_n_7),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_2_n_0));
(* HLUTNM = "lutpair14" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_3
(.I0(g81__53_carry__0_n_6),
.I1(g81__22_carry__1_n_4),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_3_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__2_i_4
(.I0(g81__53_carry__0_n_7),
.I1(g81__22_carry__1_n_5),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__2_i_4_n_0));
(* HLUTNM = "lutpair17" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_5
(.I0(g81__53_carry__1_n_7),
.I1(g81__22_carry__2_n_1),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_1_n_0),
.O(g81__149_carry__2_i_5_n_0));
(* HLUTNM = "lutpair16" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_6
(.I0(g81__53_carry__0_n_4),
.I1(g81__22_carry__2_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_2_n_0),
.O(g81__149_carry__2_i_6_n_0));
(* HLUTNM = "lutpair15" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_7
(.I0(g81__53_carry__0_n_5),
.I1(g81__22_carry__2_n_7),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_3_n_0),
.O(g81__149_carry__2_i_7_n_0));
(* HLUTNM = "lutpair14" *)
LUT5 #(
.INIT(32'h99966669))
g81__149_carry__2_i_8
(.I0(g81__53_carry__0_n_6),
.I1(g81__22_carry__1_n_4),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__149_carry__2_i_4_n_0),
.O(g81__149_carry__2_i_8_n_0));
CARRY4 g81__149_carry__3
(.CI(g81__149_carry__2_n_0),
.CO({g81__149_carry__3_n_0,g81__149_carry__3_n_1,g81__149_carry__3_n_2,g81__149_carry__3_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__2_i_2_n_0,g81_carry__2_i_2_n_0,g81_carry__2_i_2_n_0,g81__149_carry__3_i_1_n_0}),
.O({g81__149_carry__3_n_4,g81__149_carry__3_n_5,g81__149_carry__3_n_6,g81__149_carry__3_n_7}),
.S({g81__149_carry__3_i_2_n_0,g81__149_carry__3_i_3_n_0,g81__149_carry__3_i_4_n_0,g81__149_carry__3_i_5_n_0}));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h888E))
g81__149_carry__3_i_1
(.I0(g81__53_carry__1_n_7),
.I1(g81__22_carry__2_n_1),
.I2(_carry__1_n_2),
.I3(g84),
.O(g81__149_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__2_n_7),
.O(g81__149_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_3
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__1_n_4),
.O(g81__149_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_4
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__1_n_5),
.O(g81__149_carry__3_i_4_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__3_i_5
(.I0(g81__149_carry__3_i_1_n_0),
.I1(g81__53_carry__1_n_6),
.O(g81__149_carry__3_i_5_n_0));
CARRY4 g81__149_carry__4
(.CI(g81__149_carry__3_n_0),
.CO({g81__149_carry__4_n_0,NLW_g81__149_carry__4_CO_UNCONNECTED[2],g81__149_carry__4_n_2,g81__149_carry__4_n_3}),
.CYINIT(1'b0),
.DI({1'b0,g81__149_carry__4_i_1_n_0,g81_carry__2_i_2_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__149_carry__4_O_UNCONNECTED[3],g81__149_carry__4_n_5,g81__149_carry__4_n_6,g81__149_carry__4_n_7}),
.S({1'b1,1'b0,g81__149_carry__4_i_2_n_0,g81__149_carry__4_i_3_n_0}));
LUT2 #(
.INIT(4'h1))
g81__149_carry__4_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__149_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__4_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__2_n_1),
.O(g81__149_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry__4_i_3
(.I0(g81_carry__2_i_2_n_0),
.I1(g81__53_carry__2_n_6),
.O(g81__149_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry_i_1
(.I0(g81_carry__0_n_4),
.I1(g81__22_carry_n_6),
.O(g81__149_carry_i_1_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry_i_2
(.I0(g81_carry__0_n_5),
.I1(g81_carry__0_i_11_n_0),
.O(g81__149_carry_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__149_carry_i_3
(.I0(g81_carry__0_n_6),
.I1(g83__0_carry_n_7),
.O(g81__149_carry_i_3_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry_i_4
(.I0(g81_carry__0_n_4),
.I1(g81__22_carry_n_6),
.I2(g81__22_carry_n_5),
.I3(g81_carry__1_n_7),
.O(g81__149_carry_i_4_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry_i_5
(.I0(g81_carry__0_n_5),
.I1(g81_carry__0_i_11_n_0),
.I2(g81__22_carry_n_6),
.I3(g81_carry__0_n_4),
.O(g81__149_carry_i_5_n_0));
LUT4 #(
.INIT(16'h8778))
g81__149_carry_i_6
(.I0(g81_carry__0_n_6),
.I1(g83__0_carry_n_7),
.I2(g81_carry__0_i_11_n_0),
.I3(g81_carry__0_n_5),
.O(g81__149_carry_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__149_carry_i_7
(.I0(g81_carry__0_n_6),
.I1(g83__0_carry_n_7),
.O(g81__149_carry_i_7_n_0));
CARRY4 g81__206_carry
(.CI(1'b0),
.CO({g81__206_carry_n_0,g81__206_carry_n_1,g81__206_carry_n_2,g81__206_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry_i_1_n_0,g81__206_carry_i_2_n_0,g81__206_carry_i_3_n_0,1'b0}),
.O(NLW_g81__206_carry_O_UNCONNECTED[3:0]),
.S({g81__206_carry_i_4_n_0,g81__206_carry_i_5_n_0,g81__206_carry_i_6_n_0,g81__206_carry_i_7_n_0}));
CARRY4 g81__206_carry__0
(.CI(g81__206_carry_n_0),
.CO({g81__206_carry__0_n_0,g81__206_carry__0_n_1,g81__206_carry__0_n_2,g81__206_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__0_i_1_n_0,g81__206_carry__0_i_2_n_0,g81__206_carry__0_i_3_n_0,g81__206_carry__0_i_4_n_0}),
.O(NLW_g81__206_carry__0_O_UNCONNECTED[3:0]),
.S({g81__206_carry__0_i_5_n_0,g81__206_carry__0_i_6_n_0,g81__206_carry__0_i_7_n_0,g81__206_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__0_i_1
(.I0(g81__149_carry__3_n_5),
.I1(g83__0_carry_n_7),
.I2(g81__92_carry__0_n_6),
.O(g81__206_carry__0_i_1_n_0));
(* HLUTNM = "lutpair28" *)
LUT2 #(
.INIT(4'h8))
g81__206_carry__0_i_2
(.I0(g81__149_carry__3_n_6),
.I1(g81__92_carry__0_n_7),
.O(g81__206_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry__0_i_3
(.I0(g81__92_carry_n_4),
.I1(g81__149_carry__3_n_7),
.O(g81__206_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry__0_i_4
(.I0(g81__92_carry_n_5),
.I1(g81__149_carry__2_n_4),
.O(g81__206_carry__0_i_4_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__0_i_5
(.I0(g81__149_carry__3_n_4),
.I1(g81_carry__0_i_11_n_0),
.I2(g81__92_carry__0_n_5),
.I3(g81__206_carry__0_i_1_n_0),
.O(g81__206_carry__0_i_5_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__0_i_6
(.I0(g81__149_carry__3_n_5),
.I1(g83__0_carry_n_7),
.I2(g81__92_carry__0_n_6),
.I3(g81__206_carry__0_i_2_n_0),
.O(g81__206_carry__0_i_6_n_0));
(* HLUTNM = "lutpair28" *)
LUT4 #(
.INIT(16'h9666))
g81__206_carry__0_i_7
(.I0(g81__149_carry__3_n_6),
.I1(g81__92_carry__0_n_7),
.I2(g81__92_carry_n_4),
.I3(g81__149_carry__3_n_7),
.O(g81__206_carry__0_i_7_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry__0_i_8
(.I0(g81__92_carry_n_5),
.I1(g81__149_carry__2_n_4),
.I2(g81__149_carry__3_n_7),
.I3(g81__92_carry_n_4),
.O(g81__206_carry__0_i_8_n_0));
CARRY4 g81__206_carry__1
(.CI(g81__206_carry__0_n_0),
.CO({g81__206_carry__1_n_0,g81__206_carry__1_n_1,g81__206_carry__1_n_2,g81__206_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__1_i_1_n_0,g81__206_carry__1_i_2_n_0,g81__206_carry__1_i_3_n_0,g81__206_carry__1_i_4_n_0}),
.O(NLW_g81__206_carry__1_O_UNCONNECTED[3:0]),
.S({g81__206_carry__1_i_5_n_0,g81__206_carry__1_i_6_n_0,g81__206_carry__1_i_7_n_0,g81__206_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_1
(.I0(g81__149_carry__4_n_5),
.I1(g81__120_carry_n_4),
.I2(g81__92_carry__1_n_6),
.O(g81__206_carry__1_i_1_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_2
(.I0(g81__149_carry__4_n_6),
.I1(g81__120_carry_n_5),
.I2(g81__92_carry__1_n_7),
.O(g81__206_carry__1_i_2_n_0));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_3
(.I0(g81__149_carry__4_n_7),
.I1(g81__120_carry_n_6),
.I2(g81__92_carry__0_n_4),
.O(g81__206_carry__1_i_3_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__1_i_4
(.I0(g81__149_carry__3_n_4),
.I1(g81_carry__0_i_11_n_0),
.I2(g81__92_carry__0_n_5),
.O(g81__206_carry__1_i_4_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_5
(.I0(g81__149_carry__4_n_0),
.I1(g81__120_carry__0_n_7),
.I2(g81__92_carry__1_n_5),
.I3(g81__206_carry__1_i_1_n_0),
.O(g81__206_carry__1_i_5_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_6
(.I0(g81__149_carry__4_n_5),
.I1(g81__120_carry_n_4),
.I2(g81__92_carry__1_n_6),
.I3(g81__206_carry__1_i_2_n_0),
.O(g81__206_carry__1_i_6_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_7
(.I0(g81__149_carry__4_n_6),
.I1(g81__120_carry_n_5),
.I2(g81__92_carry__1_n_7),
.I3(g81__206_carry__1_i_3_n_0),
.O(g81__206_carry__1_i_7_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h6996))
g81__206_carry__1_i_8
(.I0(g81__149_carry__4_n_7),
.I1(g81__120_carry_n_6),
.I2(g81__92_carry__0_n_4),
.I3(g81__206_carry__1_i_4_n_0),
.O(g81__206_carry__1_i_8_n_0));
CARRY4 g81__206_carry__2
(.CI(g81__206_carry__1_n_0),
.CO({g81__206_carry__2_n_0,g81__206_carry__2_n_1,g81__206_carry__2_n_2,g81__206_carry__2_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__2_i_1_n_0,g81__206_carry__2_i_2_n_0,g81__206_carry__2_i_3_n_0,g81__206_carry__2_i_4_n_0}),
.O({g81__206_carry__2_n_4,g81__206_carry__2_n_5,g81__206_carry__2_n_6,g81__206_carry__2_n_7}),
.S({g81__206_carry__2_i_5_n_0,g81__206_carry__2_i_6_n_0,g81__206_carry__2_i_7_n_0,g81__206_carry__2_i_8_n_0}));
(* HLUTNM = "lutpair29" *)
LUT2 #(
.INIT(4'h8))
g81__206_carry__2_i_1
(.I0(g81__120_carry__0_n_4),
.I1(g81__92_carry__2_n_6),
.O(g81__206_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry__2_i_2
(.I0(g81__92_carry__2_n_7),
.I1(g81__120_carry__0_n_5),
.O(g81__206_carry__2_i_2_n_0));
LUT4 #(
.INIT(16'hF110))
g81__206_carry__2_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__120_carry__0_n_6),
.I3(g81__92_carry__1_n_4),
.O(g81__206_carry__2_i_3_n_0));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hE8))
g81__206_carry__2_i_4
(.I0(g81__149_carry__4_n_0),
.I1(g81__120_carry__0_n_7),
.I2(g81__92_carry__1_n_5),
.O(g81__206_carry__2_i_4_n_0));
LUT5 #(
.INIT(32'h99966669))
g81__206_carry__2_i_5
(.I0(g81__206_carry__2_i_1_n_0),
.I1(g81__120_carry__1_n_7),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__92_carry__2_n_1),
.O(g81__206_carry__2_i_5_n_0));
(* HLUTNM = "lutpair29" *)
LUT4 #(
.INIT(16'h9666))
g81__206_carry__2_i_6
(.I0(g81__120_carry__0_n_4),
.I1(g81__92_carry__2_n_6),
.I2(g81__92_carry__2_n_7),
.I3(g81__120_carry__0_n_5),
.O(g81__206_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h888E77717771888E))
g81__206_carry__2_i_7
(.I0(g81__92_carry__1_n_4),
.I1(g81__120_carry__0_n_6),
.I2(g84),
.I3(_carry__1_n_2),
.I4(g81__120_carry__0_n_5),
.I5(g81__92_carry__2_n_7),
.O(g81__206_carry__2_i_7_n_0));
LUT5 #(
.INIT(32'h99966669))
g81__206_carry__2_i_8
(.I0(g81__206_carry__2_i_4_n_0),
.I1(g81__120_carry__0_n_6),
.I2(_carry__1_n_2),
.I3(g84),
.I4(g81__92_carry__1_n_4),
.O(g81__206_carry__2_i_8_n_0));
CARRY4 g81__206_carry__3
(.CI(g81__206_carry__2_n_0),
.CO({g81__206_carry__3_n_0,g81__206_carry__3_n_1,g81__206_carry__3_n_2,g81__206_carry__3_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__3_i_1_n_0,g81__206_carry__3_i_2_n_0,g81__206_carry__3_i_3_n_0,g81__206_carry__3_i_4_n_0}),
.O({g81__206_carry__3_n_4,g81__206_carry__3_n_5,g81__206_carry__3_n_6,g81__206_carry__3_n_7}),
.S({g81__206_carry__3_i_5_n_0,g81__206_carry__3_i_6_n_0,g81__206_carry__3_i_7_n_0,g81__206_carry__3_i_8_n_0}));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'h02))
g81__206_carry__3_i_1
(.I0(g81__120_carry__1_n_4),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__206_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h1))
g81__206_carry__3_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__3_i_2_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'h02))
g81__206_carry__3_i_3
(.I0(g81__120_carry__1_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__206_carry__3_i_3_n_0));
LUT4 #(
.INIT(16'hF110))
g81__206_carry__3_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__120_carry__1_n_7),
.I3(g81__92_carry__2_n_1),
.O(g81__206_carry__3_i_4_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry__3_i_5
(.I0(g81__206_carry__3_i_1_n_0),
.I1(g81__120_carry__2_n_7),
.O(g81__206_carry__3_i_5_n_0));
(* HLUTNM = "lutpair25" *)
LUT1 #(
.INIT(2'h2))
g81__206_carry__3_i_6
(.I0(g81__120_carry__1_n_4),
.O(g81__206_carry__3_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry__3_i_7
(.I0(g81__206_carry__3_i_3_n_0),
.I1(g81__120_carry__1_n_5),
.O(g81__206_carry__3_i_7_n_0));
(* HLUTNM = "lutpair24" *)
LUT5 #(
.INIT(32'h56AAAAA9))
g81__206_carry__3_i_8
(.I0(g81__120_carry__1_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.I3(g81__92_carry__2_n_1),
.I4(g81__120_carry__1_n_7),
.O(g81__206_carry__3_i_8_n_0));
CARRY4 g81__206_carry__4
(.CI(g81__206_carry__3_n_0),
.CO({g81__206_carry__4_n_0,NLW_g81__206_carry__4_CO_UNCONNECTED[2],g81__206_carry__4_n_2,g81__206_carry__4_n_3}),
.CYINIT(1'b0),
.DI({1'b0,g81__206_carry__4_i_1_n_0,g81__206_carry__4_i_2_n_0,g81__206_carry__4_i_3_n_0}),
.O({NLW_g81__206_carry__4_O_UNCONNECTED[3],g81__206_carry__4_n_5,g81__206_carry__4_n_6,g81__206_carry__4_n_7}),
.S({1'b1,g81__206_carry__4_i_4_n_0,g81__206_carry__4_i_5_n_0,g81__206_carry__4_i_6_n_0}));
LUT2 #(
.INIT(4'h1))
g81__206_carry__4_i_1
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__4_i_1_n_0));
(* HLUTNM = "lutpair26" *)
LUT3 #(
.INIT(8'h02))
g81__206_carry__4_i_2
(.I0(g81__120_carry__2_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__206_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h1))
g81__206_carry__4_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h1))
g81__206_carry__4_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.O(g81__206_carry__4_i_4_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry__4_i_5
(.I0(g81__206_carry__4_i_2_n_0),
.I1(g81__120_carry__2_n_1),
.O(g81__206_carry__4_i_5_n_0));
(* HLUTNM = "lutpair26" *)
LUT1 #(
.INIT(2'h2))
g81__206_carry__4_i_6
(.I0(g81__120_carry__2_n_6),
.O(g81__206_carry__4_i_6_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry_i_1
(.I0(g81__92_carry_n_6),
.I1(g81__149_carry__2_n_5),
.O(g81__206_carry_i_1_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry_i_2
(.I0(g81_carry_n_7),
.I1(g81__149_carry__2_n_6),
.O(g81__206_carry_i_2_n_0));
LUT2 #(
.INIT(4'h8))
g81__206_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g81__149_carry__2_n_7),
.O(g81__206_carry_i_3_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry_i_4
(.I0(g81__92_carry_n_6),
.I1(g81__149_carry__2_n_5),
.I2(g81__149_carry__2_n_4),
.I3(g81__92_carry_n_5),
.O(g81__206_carry_i_4_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry_i_5
(.I0(g81_carry_n_7),
.I1(g81__149_carry__2_n_6),
.I2(g81__149_carry__2_n_5),
.I3(g81__92_carry_n_6),
.O(g81__206_carry_i_5_n_0));
LUT4 #(
.INIT(16'h8778))
g81__206_carry_i_6
(.I0(g83__0_carry_n_7),
.I1(g81__149_carry__2_n_7),
.I2(g81__149_carry__2_n_6),
.I3(g81_carry_n_7),
.O(g81__206_carry_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__206_carry_i_7
(.I0(g83__0_carry_n_7),
.I1(g81__149_carry__2_n_7),
.O(g81__206_carry_i_7_n_0));
CARRY4 g81__22_carry
(.CI(1'b0),
.CO({g81__22_carry_n_0,g81__22_carry_n_1,g81__22_carry_n_2,g81__22_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__22_carry_i_1_n_0,g81__22_carry_i_2_n_0,1'b0}),
.O({g81__22_carry_n_4,g81__22_carry_n_5,g81__22_carry_n_6,NLW_g81__22_carry_O_UNCONNECTED[0]}),
.S({g81__22_carry_i_3_n_0,g81__22_carry_i_4_n_0,g81__22_carry_i_5_n_0,g81__22_carry_i_6_n_0}));
CARRY4 g81__22_carry__0
(.CI(g81__22_carry_n_0),
.CO({g81__22_carry__0_n_0,g81__22_carry__0_n_1,g81__22_carry__0_n_2,g81__22_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__22_carry__0_n_4,g81__22_carry__0_n_5,g81__22_carry__0_n_6,g81__22_carry__0_n_7}),
.S({g81__22_carry__0_i_1_n_0,g81__22_carry__0_i_2_n_0,g81__22_carry__0_i_3_n_0,g81__22_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__22_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__22_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__22_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__22_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__22_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__22_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__22_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__22_carry__0_i_4_n_0));
CARRY4 g81__22_carry__1
(.CI(g81__22_carry__0_n_0),
.CO({g81__22_carry__1_n_0,g81__22_carry__1_n_1,g81__22_carry__1_n_2,g81__22_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__22_carry__1_n_4,g81__22_carry__1_n_5,g81__22_carry__1_n_6,g81__22_carry__1_n_7}),
.S({g81__22_carry__1_i_1_n_0,g81__22_carry__1_i_2_n_0,g81__22_carry__1_i_3_n_0,g81__22_carry__1_i_4_n_0}));
LUT4 #(
.INIT(16'h569A))
g81__22_carry__1_i_1
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__22_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__22_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__22_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__22_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__22_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__22_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__22_carry__1_i_4_n_0));
CARRY4 g81__22_carry__2
(.CI(g81__22_carry__1_n_0),
.CO({NLW_g81__22_carry__2_CO_UNCONNECTED[3],g81__22_carry__2_n_1,NLW_g81__22_carry__2_CO_UNCONNECTED[1],g81__22_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__22_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__22_carry__2_O_UNCONNECTED[3:2],g81__22_carry__2_n_6,g81__22_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__22_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__22_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__22_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__22_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__22_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__22_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__22_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__22_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__22_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__22_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__22_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__22_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__22_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__22_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__22_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__22_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__22_carry_i_6_n_0));
CARRY4 g81__261_carry
(.CI(1'b0),
.CO({g81__261_carry_n_0,g81__261_carry_n_1,g81__261_carry_n_2,g81__261_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__2_n_6,g81__206_carry__2_n_7,1'b0,1'b1}),
.O({g81__261_carry_n_4,g81__261_carry_n_5,g81__261_carry_n_6,g81__261_carry_n_7}),
.S({g81__261_carry_i_1_n_0,g81__261_carry_i_2_n_0,g81__261_carry_i_3_n_0,g81__261_carry_i_4_n_0}));
CARRY4 g81__261_carry__0
(.CI(g81__261_carry_n_0),
.CO({g81__261_carry__0_n_0,g81__261_carry__0_n_1,g81__261_carry__0_n_2,g81__261_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__3_n_6,g81__206_carry__3_n_7,g81__206_carry__2_n_4,g81__206_carry__2_n_5}),
.O({g81__261_carry__0_n_4,g81__261_carry__0_n_5,g81__261_carry__0_n_6,g81__261_carry__0_n_7}),
.S({g81__261_carry__0_i_1_n_0,g81__261_carry__0_i_2_n_0,g81__261_carry__0_i_3_n_0,g81__261_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_1
(.I0(g81__206_carry__3_n_6),
.I1(g81__206_carry__3_n_4),
.O(g81__261_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_2
(.I0(g81__206_carry__3_n_7),
.I1(g81__206_carry__3_n_5),
.O(g81__261_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_3
(.I0(g81__206_carry__2_n_4),
.I1(g81__206_carry__3_n_6),
.O(g81__261_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__0_i_4
(.I0(g81__206_carry__2_n_5),
.I1(g81__206_carry__3_n_7),
.O(g81__261_carry__0_i_4_n_0));
CARRY4 g81__261_carry__1
(.CI(g81__261_carry__0_n_0),
.CO({g81__261_carry__1_n_0,g81__261_carry__1_n_1,g81__261_carry__1_n_2,g81__261_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81__206_carry__4_n_6,g81__206_carry__4_n_7,g81__206_carry__3_n_4,g81__206_carry__3_n_5}),
.O({g81__261_carry__1_n_4,g81__261_carry__1_n_5,g81__261_carry__1_n_6,g81__261_carry__1_n_7}),
.S({g81__261_carry__1_i_1_n_0,g81__261_carry__1_i_2_n_0,g81__261_carry__1_i_3_n_0,g81__261_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_1
(.I0(g81__206_carry__4_n_6),
.I1(g81__206_carry__4_n_0),
.O(g81__261_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_2
(.I0(g81__206_carry__4_n_7),
.I1(g81__206_carry__4_n_5),
.O(g81__261_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_3
(.I0(g81__206_carry__3_n_4),
.I1(g81__206_carry__4_n_6),
.O(g81__261_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry__1_i_4
(.I0(g81__206_carry__3_n_5),
.I1(g81__206_carry__4_n_7),
.O(g81__261_carry__1_i_4_n_0));
CARRY4 g81__261_carry__2
(.CI(g81__261_carry__1_n_0),
.CO({NLW_g81__261_carry__2_CO_UNCONNECTED[3],g81__261_carry__2_n_1,NLW_g81__261_carry__2_CO_UNCONNECTED[1],g81__261_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__206_carry__4_n_0,g81__206_carry__4_n_5}),
.O({NLW_g81__261_carry__2_O_UNCONNECTED[3:2],g81__261_carry__2_n_6,g81__261_carry__2_n_7}),
.S({1'b0,1'b1,g81__261_carry__2_i_1_n_0,g81__261_carry__2_i_2_n_0}));
LUT3 #(
.INIT(8'h56))
g81__261_carry__2_i_1
(.I0(g81__206_carry__4_n_0),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__261_carry__2_i_1_n_0));
LUT1 #(
.INIT(2'h1))
g81__261_carry__2_i_2
(.I0(g81__206_carry__4_n_5),
.O(g81__261_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry_i_1
(.I0(g81__206_carry__2_n_6),
.I1(g81__206_carry__2_n_4),
.O(g81__261_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
g81__261_carry_i_2
(.I0(g81__206_carry__2_n_7),
.I1(g81__206_carry__2_n_5),
.O(g81__261_carry_i_2_n_0));
LUT1 #(
.INIT(2'h1))
g81__261_carry_i_3
(.I0(g81__206_carry__2_n_6),
.O(g81__261_carry_i_3_n_0));
LUT1 #(
.INIT(2'h2))
g81__261_carry_i_4
(.I0(g81__206_carry__2_n_7),
.O(g81__261_carry_i_4_n_0));
CARRY4 g81__301_carry
(.CI(1'b0),
.CO({g81__301_carry_n_0,g81__301_carry_n_1,g81__301_carry_n_2,g81__301_carry_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry_i_1_n_0,g81__301_carry_i_2_n_0,g81__301_carry_i_3_n_0,1'b0}),
.O(NLW_g81__301_carry_O_UNCONNECTED[3:0]),
.S({g81__301_carry_i_4_n_0,g81__301_carry_i_5_n_0,g81__301_carry_i_6_n_0,g81__301_carry_i_7_n_0}));
CARRY4 g81__301_carry__0
(.CI(g81__301_carry_n_0),
.CO({g81__301_carry__0_n_0,g81__301_carry__0_n_1,g81__301_carry__0_n_2,g81__301_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry__0_i_1_n_0,g81__301_carry__0_i_2_n_0,g81__301_carry__0_i_3_n_0,g81__301_carry__0_i_4_n_0}),
.O(NLW_g81__301_carry__0_O_UNCONNECTED[3:0]),
.S({g81__301_carry__0_i_5_n_0,g81__301_carry__0_i_6_n_0,g81__301_carry__0_i_7_n_0,g81__301_carry__0_i_8_n_0}));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_1
(.I0(g81__261_carry__0_n_5),
.I1(g84),
.I2(g83[6]),
.I3(g83__0_carry__0_n_5),
.O(g81__301_carry__0_i_1_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_2
(.I0(g81__261_carry__0_n_6),
.I1(g84),
.I2(g83[5]),
.I3(g83__0_carry__0_n_6),
.O(g81__301_carry__0_i_2_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_3
(.I0(g81__261_carry__0_n_7),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.O(g81__301_carry__0_i_3_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__0_i_4
(.I0(g81__261_carry_n_4),
.I1(g84),
.I2(g83[3]),
.I3(g83__0_carry_n_4),
.O(g81__301_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__0_i_5
(.I0(g83__0_carry__0_n_5),
.I1(g83[6]),
.I2(g84),
.I3(g81__261_carry__0_n_5),
.I4(g81__261_carry__0_n_4),
.I5(g81_carry__1_i_9_n_0),
.O(g81__301_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__0_i_6
(.I0(g83__0_carry__0_n_6),
.I1(g83[5]),
.I2(g84),
.I3(g81__261_carry__0_n_6),
.I4(g81__261_carry__0_n_5),
.I5(g81_carry__0_i_12_n_0),
.O(g81__301_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__0_i_7
(.I0(g83__0_carry__0_n_7),
.I1(g83[4]),
.I2(g84),
.I3(g81__261_carry__0_n_7),
.I4(g81__261_carry__0_n_6),
.I5(g81_carry__0_i_14_n_0),
.O(g81__301_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hB44BB44BB4B44B4B))
g81__301_carry__0_i_8
(.I0(g81_carry__0_i_9_n_0),
.I1(g81__261_carry_n_4),
.I2(g81__261_carry__0_n_7),
.I3(g83__0_carry__0_n_7),
.I4(g83[4]),
.I5(g84),
.O(g81__301_carry__0_i_8_n_0));
CARRY4 g81__301_carry__1
(.CI(g81__301_carry__0_n_0),
.CO({g81__301_carry__1_n_0,g81__301_carry__1_n_1,g81__301_carry__1_n_2,g81__301_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry__1_i_1_n_0,g81__301_carry__1_i_2_n_0,g81__301_carry__1_i_3_n_0,g81__301_carry__1_i_4_n_0}),
.O(NLW_g81__301_carry__1_O_UNCONNECTED[3:0]),
.S({g81__301_carry__1_i_5_n_0,g81__301_carry__1_i_6_n_0,g81__301_carry__1_i_7_n_0,g81__301_carry__1_i_8_n_0}));
LUT3 #(
.INIT(8'hA8))
g81__301_carry__1_i_1
(.I0(g81__261_carry__1_n_5),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__301_carry__1_i_1_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__1_i_2
(.I0(g81__261_carry__1_n_6),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__301_carry__1_i_2_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__1_i_3
(.I0(g81__261_carry__1_n_7),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__301_carry__1_i_3_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry__1_i_4
(.I0(g81__261_carry__0_n_4),
.I1(g84),
.I2(g83[7]),
.I3(g83__0_carry__0_n_4),
.O(g81__301_carry__1_i_4_n_0));
LUT4 #(
.INIT(16'h999C))
g81__301_carry__1_i_5
(.I0(g81__261_carry__1_n_5),
.I1(g81__261_carry__1_n_4),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h50AF30CF50AFCF30))
g81__301_carry__1_i_6
(.I0(g83__0_carry__1_n_2),
.I1(g83[9]),
.I2(g81__261_carry__1_n_6),
.I3(g81__261_carry__1_n_5),
.I4(g84),
.I5(_carry__1_n_2),
.O(g81__301_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry__1_i_7
(.I0(g83__0_carry__1_n_7),
.I1(g83[8]),
.I2(g84),
.I3(g81__261_carry__1_n_7),
.I4(g81__261_carry__1_n_6),
.I5(g81__301_carry__1_i_9_n_0),
.O(g81__301_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hB44BB44BB4B44B4B))
g81__301_carry__1_i_8
(.I0(g81_carry__1_i_9_n_0),
.I1(g81__261_carry__0_n_4),
.I2(g81__261_carry__1_n_7),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__301_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'hAC))
g81__301_carry__1_i_9
(.I0(g83__0_carry__1_n_2),
.I1(g83[9]),
.I2(g84),
.O(g81__301_carry__1_i_9_n_0));
CARRY4 g81__301_carry__2
(.CI(g81__301_carry__1_n_0),
.CO({g81__301_carry__2_n_0,g81__301_carry__2_n_1,g81__301_carry__2_n_2,g81__301_carry__2_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry__2_i_1_n_0,g81__301_carry__2_i_2_n_0,g81__301_carry__2_i_3_n_0,g81__301_carry__2_i_4_n_0}),
.O(NLW_g81__301_carry__2_O_UNCONNECTED[3:0]),
.S({g81__301_carry__2_i_5_n_0,g81__301_carry__2_i_6_n_0,g81__301_carry__2_i_7_n_0,g81__301_carry__2_i_8_n_0}));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__2_i_1
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__2_i_1_n_0));
LUT3 #(
.INIT(8'hA8))
g81__301_carry__2_i_2
(.I0(g81__261_carry__2_n_6),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__301_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hA8))
g81__301_carry__2_i_3
(.I0(g81__261_carry__2_n_7),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__301_carry__2_i_3_n_0));
LUT3 #(
.INIT(8'hA8))
g81__301_carry__2_i_4
(.I0(g81__261_carry__1_n_4),
.I1(_carry__1_n_2),
.I2(g84),
.O(g81__301_carry__2_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__2_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__2_i_5_n_0));
LUT4 #(
.INIT(16'h6663))
g81__301_carry__2_i_6
(.I0(g81__261_carry__2_n_6),
.I1(g81__261_carry__2_n_1),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__2_i_6_n_0));
LUT4 #(
.INIT(16'h999C))
g81__301_carry__2_i_7
(.I0(g81__261_carry__2_n_7),
.I1(g81__261_carry__2_n_6),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__2_i_7_n_0));
LUT4 #(
.INIT(16'h999C))
g81__301_carry__2_i_8
(.I0(g81__261_carry__1_n_4),
.I1(g81__261_carry__2_n_7),
.I2(g84),
.I3(_carry__1_n_2),
.O(g81__301_carry__2_i_8_n_0));
CARRY4 g81__301_carry__3
(.CI(g81__301_carry__2_n_0),
.CO({g81__301_carry__3_n_0,g81__301_carry__3_n_1,g81__301_carry__3_n_2,g81__301_carry__3_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry__3_i_1_n_0,g81__301_carry__3_i_2_n_0,g81__301_carry__3_i_3_n_0,g81__301_carry__3_i_4_n_0}),
.O(NLW_g81__301_carry__3_O_UNCONNECTED[3:0]),
.S({g81__301_carry__3_i_5_n_0,g81__301_carry__3_i_6_n_0,g81__301_carry__3_i_7_n_0,g81__301_carry__3_i_8_n_0}));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_1
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__3_i_1_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__3_i_2_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__3_i_3_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__3_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__3_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_5_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_6
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_6_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_7
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_7_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__3_i_8
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__3_i_8_n_0));
CARRY4 g81__301_carry__4
(.CI(g81__301_carry__3_n_0),
.CO({g81__301_carry__4_n_0,g81__301_carry__4_n_1,g81__301_carry__4_n_2,g81__301_carry__4_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry__4_i_1_n_0,g81__301_carry__4_i_2_n_0,g81__301_carry__4_i_3_n_0,g81__301_carry__4_i_4_n_0}),
.O(NLW_g81__301_carry__4_O_UNCONNECTED[3:0]),
.S({g81__301_carry__4_i_5_n_0,g81__301_carry__4_i_6_n_0,g81__301_carry__4_i_7_n_0,g81__301_carry__4_i_8_n_0}));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_1
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_1_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_2_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_3_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__4_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__4_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_5_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_6
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_6_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_7
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_7_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__4_i_8
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__4_i_8_n_0));
CARRY4 g81__301_carry__5
(.CI(g81__301_carry__4_n_0),
.CO({g81__301_carry__5_n_0,g81__301_carry__5_n_1,g81__301_carry__5_n_2,g81__301_carry__5_n_3}),
.CYINIT(1'b0),
.DI({g81__301_carry__5_i_1_n_0,g81__301_carry__5_i_2_n_0,g81__301_carry__5_i_3_n_0,g81__301_carry__5_i_4_n_0}),
.O(NLW_g81__301_carry__5_O_UNCONNECTED[3:0]),
.S({g81__301_carry__5_i_5_n_0,g81__301_carry__5_i_6_n_0,g81__301_carry__5_i_7_n_0,g81__301_carry__5_i_8_n_0}));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_1
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__5_i_1_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__5_i_2_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__5_i_3_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__5_i_4
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__5_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__5_i_5_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_6
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__5_i_6_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_7
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__5_i_7_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__5_i_8
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__5_i_8_n_0));
CARRY4 g81__301_carry__6
(.CI(g81__301_carry__5_n_0),
.CO({NLW_g81__301_carry__6_CO_UNCONNECTED[3],g81__301_carry__6_n_1,g81__301_carry__6_n_2,g81__301_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,g81__301_carry__6_i_1_n_0,g81__301_carry__6_i_2_n_0,g81__301_carry__6_i_3_n_0}),
.O(NLW_g81__301_carry__6_O_UNCONNECTED[3:0]),
.S({1'b0,g81__301_carry__6_i_4_n_0,g81__301_carry__6_i_5_n_0,g81__301_carry__6_i_6_n_0}));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__6_i_1
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__6_i_1_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__6_i_2
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__6_i_2_n_0));
LUT3 #(
.INIT(8'h0E))
g81__301_carry__6_i_3
(.I0(_carry__1_n_2),
.I1(g84),
.I2(g81__261_carry__2_n_1),
.O(g81__301_carry__6_i_3_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__6_i_4
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__6_i_4_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__6_i_5
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__6_i_5_n_0));
LUT3 #(
.INIT(8'hFD))
g81__301_carry__6_i_6
(.I0(g81__261_carry__2_n_1),
.I1(g84),
.I2(_carry__1_n_2),
.O(g81__301_carry__6_i_6_n_0));
LUT4 #(
.INIT(16'h028A))
g81__301_carry_i_1
(.I0(g81__261_carry_n_5),
.I1(g84),
.I2(g83[2]),
.I3(g83__0_carry_n_5),
.O(g81__301_carry_i_1_n_0));
LUT4 #(
.INIT(16'hABEF))
g81__301_carry_i_2
(.I0(g81__261_carry_n_6),
.I1(g84),
.I2(g83[1]),
.I3(g83__0_carry_n_6),
.O(g81__301_carry_i_2_n_0));
LUT2 #(
.INIT(4'hB))
g81__301_carry_i_3
(.I0(g81__261_carry_n_7),
.I1(g83__0_carry_n_7),
.O(g81__301_carry_i_3_n_0));
LUT6 #(
.INIT(64'hACFF53005300ACFF))
g81__301_carry_i_4
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.I3(g81__261_carry_n_5),
.I4(g81__261_carry_n_4),
.I5(g81_carry__0_i_9_n_0),
.O(g81__301_carry_i_4_n_0));
LUT6 #(
.INIT(64'h2DD22DD22D2DD2D2))
g81__301_carry_i_5
(.I0(g81_carry__0_i_11_n_0),
.I1(g81__261_carry_n_6),
.I2(g81__261_carry_n_5),
.I3(g83__0_carry_n_5),
.I4(g83[2]),
.I5(g84),
.O(g81__301_carry_i_5_n_0));
LUT6 #(
.INIT(64'hD22DD22DD2D22D2D))
g81__301_carry_i_6
(.I0(g83__0_carry_n_7),
.I1(g81__261_carry_n_7),
.I2(g81__261_carry_n_6),
.I3(g83__0_carry_n_6),
.I4(g83[1]),
.I5(g84),
.O(g81__301_carry_i_6_n_0));
LUT2 #(
.INIT(4'h6))
g81__301_carry_i_7
(.I0(g83__0_carry_n_7),
.I1(g81__261_carry_n_7),
.O(g81__301_carry_i_7_n_0));
CARRY4 g81__347_carry
(.CI(1'b0),
.CO({g81__347_carry_n_0,g81__347_carry_n_1,g81__347_carry_n_2,g81__347_carry_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({g81__347_carry_n_4,g81__347_carry_n_5,g81__347_carry_n_6,g81__347_carry_n_7}),
.S({g81__347_carry_i_1_n_0,g81__347_carry_i_2_n_0,g81__347_carry_i_3_n_0,g81__347_carry_i_4_n_0}));
CARRY4 g81__347_carry__0
(.CI(g81__347_carry_n_0),
.CO({NLW_g81__347_carry__0_CO_UNCONNECTED[3],g81__347_carry__0_n_1,g81__347_carry__0_n_2,g81__347_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({g81__347_carry__0_n_4,g81__347_carry__0_n_5,g81__347_carry__0_n_6,g81__347_carry__0_n_7}),
.S({g81__347_carry__0_i_1_n_0,g81__347_carry__0_i_2_n_0,g81__347_carry__0_i_3_n_0,g81__347_carry__0_i_4_n_0}));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_1
(.I0(g81__206_carry__3_n_4),
.O(g81__347_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_2
(.I0(g81__206_carry__3_n_5),
.O(g81__347_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_3
(.I0(g81__206_carry__3_n_6),
.O(g81__347_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry__0_i_4
(.I0(g81__206_carry__3_n_7),
.O(g81__347_carry__0_i_4_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry_i_1
(.I0(g81__206_carry__2_n_4),
.O(g81__347_carry_i_1_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry_i_2
(.I0(g81__206_carry__2_n_5),
.O(g81__347_carry_i_2_n_0));
LUT1 #(
.INIT(2'h2))
g81__347_carry_i_3
(.I0(g81__206_carry__2_n_6),
.O(g81__347_carry_i_3_n_0));
LUT1 #(
.INIT(2'h1))
g81__347_carry_i_4
(.I0(g81__206_carry__2_n_7),
.O(g81__347_carry_i_4_n_0));
CARRY4 g81__53_carry
(.CI(1'b0),
.CO({g81__53_carry_n_0,g81__53_carry_n_1,g81__53_carry_n_2,g81__53_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__53_carry_i_1_n_0,g81__53_carry_i_2_n_0,1'b0}),
.O({g81__53_carry_n_4,g81__53_carry_n_5,g81__53_carry_n_6,NLW_g81__53_carry_O_UNCONNECTED[0]}),
.S({g81__53_carry_i_3_n_0,g81__53_carry_i_4_n_0,g81__53_carry_i_5_n_0,g81__53_carry_i_6_n_0}));
CARRY4 g81__53_carry__0
(.CI(g81__53_carry_n_0),
.CO({g81__53_carry__0_n_0,g81__53_carry__0_n_1,g81__53_carry__0_n_2,g81__53_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__53_carry__0_n_4,g81__53_carry__0_n_5,g81__53_carry__0_n_6,g81__53_carry__0_n_7}),
.S({g81__53_carry__0_i_1_n_0,g81__53_carry__0_i_2_n_0,g81__53_carry__0_i_3_n_0,g81__53_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__53_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__53_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__53_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__53_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__53_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__53_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__53_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__53_carry__0_i_4_n_0));
CARRY4 g81__53_carry__1
(.CI(g81__53_carry__0_n_0),
.CO({g81__53_carry__1_n_0,g81__53_carry__1_n_1,g81__53_carry__1_n_2,g81__53_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__53_carry__1_n_4,g81__53_carry__1_n_5,g81__53_carry__1_n_6,g81__53_carry__1_n_7}),
.S({g81__53_carry__1_i_1_n_0,g81__53_carry__1_i_2_n_0,g81__53_carry__1_i_3_n_0,g81__53_carry__1_i_4_n_0}));
LUT4 #(
.INIT(16'h569A))
g81__53_carry__1_i_1
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__53_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__53_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__53_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__53_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__53_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__53_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__53_carry__1_i_4_n_0));
CARRY4 g81__53_carry__2
(.CI(g81__53_carry__1_n_0),
.CO({NLW_g81__53_carry__2_CO_UNCONNECTED[3],g81__53_carry__2_n_1,NLW_g81__53_carry__2_CO_UNCONNECTED[1],g81__53_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__53_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__53_carry__2_O_UNCONNECTED[3:2],g81__53_carry__2_n_6,g81__53_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__53_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__53_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__53_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__53_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__53_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__53_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__53_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__53_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__53_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__53_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__53_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__53_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__53_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__53_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__53_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__53_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__53_carry_i_6_n_0));
CARRY4 g81__92_carry
(.CI(1'b0),
.CO({g81__92_carry_n_0,g81__92_carry_n_1,g81__92_carry_n_2,g81__92_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81__92_carry_i_1_n_0,g81__92_carry_i_2_n_0,1'b0}),
.O({g81__92_carry_n_4,g81__92_carry_n_5,g81__92_carry_n_6,NLW_g81__92_carry_O_UNCONNECTED[0]}),
.S({g81__92_carry_i_3_n_0,g81__92_carry_i_4_n_0,g81__92_carry_i_5_n_0,g81__92_carry_i_6_n_0}));
CARRY4 g81__92_carry__0
(.CI(g81__92_carry_n_0),
.CO({g81__92_carry__0_n_0,g81__92_carry__0_n_1,g81__92_carry__0_n_2,g81__92_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81__92_carry__0_n_4,g81__92_carry__0_n_5,g81__92_carry__0_n_6,g81__92_carry__0_n_7}),
.S({g81__92_carry__0_i_1_n_0,g81__92_carry__0_i_2_n_0,g81__92_carry__0_i_3_n_0,g81__92_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h6996699669699696))
g81__92_carry__0_i_1
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81__92_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__92_carry__0_i_2
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81__92_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81__92_carry__0_i_3
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81__92_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81__92_carry__0_i_4
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81__92_carry__0_i_4_n_0));
CARRY4 g81__92_carry__1
(.CI(g81__92_carry__0_n_0),
.CO({g81__92_carry__1_n_0,g81__92_carry__1_n_1,g81__92_carry__1_n_2,g81__92_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81__92_carry__1_n_4,g81__92_carry__1_n_5,g81__92_carry__1_n_6,g81__92_carry__1_n_7}),
.S({g81__92_carry__1_i_1_n_0,g81__92_carry__1_i_2_n_0,g81__92_carry__1_i_3_n_0,g81__92_carry__1_i_4_n_0}));
LUT4 #(
.INIT(16'h569A))
g81__92_carry__1_i_1
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81__92_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__92_carry__1_i_2
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81__92_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81__92_carry__1_i_3
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81__92_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81__92_carry__1_i_4
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81__92_carry__1_i_4_n_0));
CARRY4 g81__92_carry__2
(.CI(g81__92_carry__1_n_0),
.CO({NLW_g81__92_carry__2_CO_UNCONNECTED[3],g81__92_carry__2_n_1,NLW_g81__92_carry__2_CO_UNCONNECTED[1],g81__92_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81__92_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81__92_carry__2_O_UNCONNECTED[3:2],g81__92_carry__2_n_6,g81__92_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81__92_carry__2_i_2_n_0}));
LUT2 #(
.INIT(4'h1))
g81__92_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81__92_carry__2_i_1_n_0));
LUT4 #(
.INIT(16'h569A))
g81__92_carry__2_i_2
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81__92_carry__2_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81__92_carry_i_1
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81__92_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81__92_carry_i_2
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81__92_carry_i_2_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81__92_carry_i_3
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81__92_carry_i_3_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81__92_carry_i_4
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81__92_carry_i_4_n_0));
LUT4 #(
.INIT(16'h35CA))
g81__92_carry_i_5
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81__92_carry_i_5_n_0));
LUT3 #(
.INIT(8'hAC))
g81__92_carry_i_6
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81__92_carry_i_6_n_0));
CARRY4 g81_carry
(.CI(1'b0),
.CO({g81_carry_n_0,g81_carry_n_1,g81_carry_n_2,g81_carry_n_3}),
.CYINIT(1'b0),
.DI({g81_carry_i_1_n_0,g81_carry_i_2_n_0,g81_carry_i_3_n_0,1'b0}),
.O({NLW_g81_carry_O_UNCONNECTED[3:1],g81_carry_n_7}),
.S({g81_carry_i_4_n_0,g81_carry_i_5_n_0,g81_carry_i_6_n_0,g81_carry_i_7_n_0}));
CARRY4 g81_carry__0
(.CI(g81_carry_n_0),
.CO({g81_carry__0_n_0,g81_carry__0_n_1,g81_carry__0_n_2,g81_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__0_i_1_n_0,g81_carry__0_i_2_n_0,g81_carry__0_i_3_n_0,g81_carry__0_i_4_n_0}),
.O({g81_carry__0_n_4,g81_carry__0_n_5,g81_carry__0_n_6,NLW_g81_carry__0_O_UNCONNECTED[0]}),
.S({g81_carry__0_i_5_n_0,g81_carry__0_i_6_n_0,g81_carry__0_i_7_n_0,g81_carry__0_i_8_n_0}));
LUT6 #(
.INIT(64'hFEBAECA8BA32A820))
g81_carry__0_i_1
(.I0(g81_carry__0_i_9_n_0),
.I1(g84),
.I2(g83[5]),
.I3(g83__0_carry__0_n_6),
.I4(g83[7]),
.I5(g83__0_carry__0_n_4),
.O(g81_carry__0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_10
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81_carry__0_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_11
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81_carry__0_i_11_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_12
(.I0(g83__0_carry__0_n_5),
.I1(g83[6]),
.I2(g84),
.O(g81_carry__0_i_12_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_13
(.I0(g83__0_carry__0_n_7),
.I1(g83[4]),
.I2(g84),
.O(g81_carry__0_i_13_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_14
(.I0(g83__0_carry__0_n_6),
.I1(g83[5]),
.I2(g84),
.O(g81_carry__0_i_14_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h353AC5CA))
g81_carry__0_i_15
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81_carry__0_i_15_n_0));
LUT6 #(
.INIT(64'hFEBAECA8BA32A820))
g81_carry__0_i_2
(.I0(g81_carry__0_i_10_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g83[6]),
.I5(g83__0_carry__0_n_5),
.O(g81_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'hFEBAECA8BA32A820))
g81_carry__0_i_3
(.I0(g81_carry__0_i_11_n_0),
.I1(g84),
.I2(g83[3]),
.I3(g83__0_carry_n_4),
.I4(g83[5]),
.I5(g83__0_carry__0_n_6),
.O(g81_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'hC33CC33CA5A55A5A))
g81_carry__0_i_4
(.I0(g83[5]),
.I1(g83__0_carry__0_n_6),
.I2(g81_carry__0_i_11_n_0),
.I3(g83__0_carry_n_4),
.I4(g83[3]),
.I5(g84),
.O(g81_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81_carry__0_i_5
(.I0(g81_carry__0_i_1_n_0),
.I1(g81_carry__0_i_12_n_0),
.I2(g81_carry__0_i_13_n_0),
.I3(g83__0_carry__1_n_7),
.I4(g83[8]),
.I5(g84),
.O(g81_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81_carry__0_i_6
(.I0(g81_carry__0_i_2_n_0),
.I1(g81_carry__0_i_14_n_0),
.I2(g81_carry__0_i_9_n_0),
.I3(g83__0_carry__0_n_4),
.I4(g83[7]),
.I5(g84),
.O(g81_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h569AA965A965569A))
g81_carry__0_i_7
(.I0(g81_carry__0_i_3_n_0),
.I1(g84),
.I2(g83[4]),
.I3(g83__0_carry__0_n_7),
.I4(g81_carry__0_i_10_n_0),
.I5(g81_carry__0_i_12_n_0),
.O(g81_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h99666666A55A5A5A))
g81_carry__0_i_8
(.I0(g81_carry__0_i_15_n_0),
.I1(g83__0_carry__0_n_6),
.I2(g83[5]),
.I3(g81_carry__0_i_10_n_0),
.I4(g83__0_carry_n_7),
.I5(g84),
.O(g81_carry__0_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__0_i_9
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81_carry__0_i_9_n_0));
CARRY4 g81_carry__1
(.CI(g81_carry__0_n_0),
.CO({g81_carry__1_n_0,g81_carry__1_n_1,g81_carry__1_n_2,g81_carry__1_n_3}),
.CYINIT(1'b0),
.DI({g81_carry__1_i_1_n_0,g81_carry__1_i_2_n_0,g81_carry__1_i_3_n_0,g81_carry__1_i_4_n_0}),
.O({g81_carry__1_n_4,g81_carry__1_n_5,g81_carry__1_n_6,g81_carry__1_n_7}),
.S({g81_carry__1_i_5_n_0,g81_carry__1_i_6_n_0,g81_carry__1_i_7_n_0,g81_carry__1_i_8_n_0}));
LUT6 #(
.INIT(64'hCAC00A00CFCA0F0A))
g81_carry__1_i_1
(.I0(g83[7]),
.I1(g83__0_carry__0_n_4),
.I2(g84),
.I3(g83[9]),
.I4(g83__0_carry__1_n_2),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hCAC00A00CFCA0F0A))
g81_carry__1_i_2
(.I0(g83[6]),
.I1(g83__0_carry__0_n_5),
.I2(g84),
.I3(g83[8]),
.I4(g83__0_carry__1_n_7),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hFFE4EEA0F544E400))
g81_carry__1_i_3
(.I0(g84),
.I1(g83[5]),
.I2(g83__0_carry__0_n_6),
.I3(g81_carry__1_i_9_n_0),
.I4(g83[9]),
.I5(g83__0_carry__1_n_2),
.O(g81_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'hFFE4EEA0F544E400))
g81_carry__1_i_4
(.I0(g84),
.I1(g83[4]),
.I2(g83__0_carry__0_n_7),
.I3(g81_carry__0_i_12_n_0),
.I4(g83[8]),
.I5(g83__0_carry__1_n_7),
.O(g81_carry__1_i_4_n_0));
LUT4 #(
.INIT(16'h569A))
g81_carry__1_i_5
(.I0(g81_carry__1_i_1_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.O(g81_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81_carry__1_i_6
(.I0(g81_carry__1_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.I4(g81_carry__1_i_9_n_0),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA965569A9A5665A9))
g81_carry__1_i_7
(.I0(g81_carry__1_i_3_n_0),
.I1(g84),
.I2(g83[8]),
.I3(g83__0_carry__1_n_7),
.I4(g81_carry__0_i_12_n_0),
.I5(_carry__1_n_2),
.O(g81_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h6996699669699696))
g81_carry__1_i_8
(.I0(g81_carry__1_i_4_n_0),
.I1(g81_carry__1_i_9_n_0),
.I2(g81_carry__0_i_14_n_0),
.I3(g83__0_carry__1_n_2),
.I4(g83[9]),
.I5(g84),
.O(g81_carry__1_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
g81_carry__1_i_9
(.I0(g83__0_carry__0_n_4),
.I1(g83[7]),
.I2(g84),
.O(g81_carry__1_i_9_n_0));
CARRY4 g81_carry__2
(.CI(g81_carry__1_n_0),
.CO({NLW_g81_carry__2_CO_UNCONNECTED[3],g81_carry__2_n_1,NLW_g81_carry__2_CO_UNCONNECTED[1],g81_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,g81_carry__2_i_1_n_0,g81_carry__2_i_2_n_0}),
.O({NLW_g81_carry__2_O_UNCONNECTED[3:2],g81_carry__2_n_6,g81_carry__2_n_7}),
.S({1'b0,1'b1,1'b0,g81_carry__2_i_3_n_0}));
LUT2 #(
.INIT(4'h1))
g81_carry__2_i_1
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81_carry__2_i_1_n_0));
(* HLUTNM = "lutpair7" *)
LUT2 #(
.INIT(4'h1))
g81_carry__2_i_2
(.I0(g84),
.I1(_carry__1_n_2),
.O(g81_carry__2_i_2_n_0));
LUT4 #(
.INIT(16'h569A))
g81_carry__2_i_3
(.I0(g81_carry__2_i_2_n_0),
.I1(g84),
.I2(g83[9]),
.I3(g83__0_carry__1_n_2),
.O(g81_carry__2_i_3_n_0));
LUT4 #(
.INIT(16'h35CA))
g81_carry_i_1
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81_carry_i_1_n_0));
LUT3 #(
.INIT(8'hAC))
g81_carry_i_2
(.I0(g83__0_carry_n_4),
.I1(g83[3]),
.I2(g84),
.O(g81_carry_i_2_n_0));
LUT3 #(
.INIT(8'hAC))
g81_carry_i_3
(.I0(g83__0_carry_n_5),
.I1(g83[2]),
.I2(g84),
.O(g81_carry_i_3_n_0));
LUT6 #(
.INIT(64'h99A5995A66A5665A))
g81_carry_i_4
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_5),
.I2(g83[2]),
.I3(g84),
.I4(g83[4]),
.I5(g83__0_carry__0_n_7),
.O(g81_carry_i_4_n_0));
LUT5 #(
.INIT(32'h353AC5CA))
g81_carry_i_5
(.I0(g83[3]),
.I1(g83__0_carry_n_4),
.I2(g84),
.I3(g83[1]),
.I4(g83__0_carry_n_6),
.O(g81_carry_i_5_n_0));
LUT4 #(
.INIT(16'h35CA))
g81_carry_i_6
(.I0(g83[2]),
.I1(g83__0_carry_n_5),
.I2(g84),
.I3(g83__0_carry_n_7),
.O(g81_carry_i_6_n_0));
LUT3 #(
.INIT(8'hAC))
g81_carry_i_7
(.I0(g83__0_carry_n_6),
.I1(g83[1]),
.I2(g84),
.O(g81_carry_i_7_n_0));
CARRY4 g83__0_carry
(.CI(1'b0),
.CO({g83__0_carry_n_0,g83__0_carry_n_1,g83__0_carry_n_2,g83__0_carry_n_3}),
.CYINIT(1'b0),
.DI({g83__0_carry_i_1_n_0,g83__0_carry_i_2_n_0,g83__0_carry_i_3_n_0,1'b0}),
.O({g83__0_carry_n_4,g83__0_carry_n_5,g83__0_carry_n_6,g83__0_carry_n_7}),
.S({g83__0_carry_i_4_n_0,g83__0_carry_i_5_n_0,g83__0_carry_i_6_n_0,g83__0_carry_i_7_n_0}));
CARRY4 g83__0_carry__0
(.CI(g83__0_carry_n_0),
.CO({g83__0_carry__0_n_0,g83__0_carry__0_n_1,g83__0_carry__0_n_2,g83__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({g83__0_carry__0_i_1_n_0,g83__0_carry__0_i_2_n_0,g83__0_carry__0_i_3_n_0,g83__0_carry__0_i_4_n_0}),
.O({g83__0_carry__0_n_4,g83__0_carry__0_n_5,g83__0_carry__0_n_6,g83__0_carry__0_n_7}),
.S({g83__0_carry__0_i_5_n_0,g83__0_carry__0_i_6_n_0,g83__0_carry__0_i_7_n_0,g83__0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_1
(.I0(rgb888[14]),
.I1(rgb888[6]),
.I2(rgb888[22]),
.O(g83__0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_2
(.I0(rgb888[13]),
.I1(rgb888[5]),
.I2(rgb888[21]),
.O(g83__0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_3
(.I0(rgb888[12]),
.I1(rgb888[4]),
.I2(rgb888[20]),
.O(g83__0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry__0_i_4
(.I0(rgb888[11]),
.I1(rgb888[3]),
.I2(rgb888[19]),
.O(g83__0_carry__0_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_5
(.I0(g83__0_carry__0_i_1_n_0),
.I1(rgb888[7]),
.I2(rgb888[15]),
.I3(rgb888[23]),
.O(g83__0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_6
(.I0(rgb888[14]),
.I1(rgb888[6]),
.I2(rgb888[22]),
.I3(g83__0_carry__0_i_2_n_0),
.O(g83__0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_7
(.I0(rgb888[13]),
.I1(rgb888[5]),
.I2(rgb888[21]),
.I3(g83__0_carry__0_i_3_n_0),
.O(g83__0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry__0_i_8
(.I0(rgb888[12]),
.I1(rgb888[4]),
.I2(rgb888[20]),
.I3(g83__0_carry__0_i_4_n_0),
.O(g83__0_carry__0_i_8_n_0));
CARRY4 g83__0_carry__1
(.CI(g83__0_carry__0_n_0),
.CO({NLW_g83__0_carry__1_CO_UNCONNECTED[3:2],g83__0_carry__1_n_2,NLW_g83__0_carry__1_CO_UNCONNECTED[0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_g83__0_carry__1_O_UNCONNECTED[3:1],g83__0_carry__1_n_7}),
.S({1'b0,1'b0,1'b1,g83__0_carry__1_i_1_n_0}));
LUT3 #(
.INIT(8'hE8))
g83__0_carry__1_i_1
(.I0(rgb888[15]),
.I1(rgb888[7]),
.I2(rgb888[23]),
.O(g83__0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry_i_1
(.I0(rgb888[10]),
.I1(rgb888[2]),
.I2(rgb888[18]),
.O(g83__0_carry_i_1_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry_i_2
(.I0(rgb888[9]),
.I1(rgb888[1]),
.I2(rgb888[17]),
.O(g83__0_carry_i_2_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hE8))
g83__0_carry_i_3
(.I0(rgb888[8]),
.I1(rgb888[0]),
.I2(rgb888[16]),
.O(g83__0_carry_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry_i_4
(.I0(rgb888[11]),
.I1(rgb888[3]),
.I2(rgb888[19]),
.I3(g83__0_carry_i_1_n_0),
.O(g83__0_carry_i_4_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry_i_5
(.I0(rgb888[10]),
.I1(rgb888[2]),
.I2(rgb888[18]),
.I3(g83__0_carry_i_2_n_0),
.O(g83__0_carry_i_5_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
g83__0_carry_i_6
(.I0(rgb888[9]),
.I1(rgb888[1]),
.I2(rgb888[17]),
.I3(g83__0_carry_i_3_n_0),
.O(g83__0_carry_i_6_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h96))
g83__0_carry_i_7
(.I0(rgb888[8]),
.I1(rgb888[0]),
.I2(rgb888[16]),
.O(g83__0_carry_i_7_n_0));
CARRY4 g84_carry
(.CI(1'b0),
.CO({g84_carry_n_0,g84_carry_n_1,g84_carry_n_2,g84_carry_n_3}),
.CYINIT(1'b1),
.DI({g84_carry_i_1_n_0,g84_carry_i_2_n_0,g84_carry_i_3_n_0,g84_carry_i_4_n_0}),
.O(NLW_g84_carry_O_UNCONNECTED[3:0]),
.S({g84_carry_i_5_n_0,g84_carry_i_6_n_0,g84_carry_i_7_n_0,g84_carry_i_8_n_0}));
CARRY4 g84_carry__0
(.CI(g84_carry_n_0),
.CO({NLW_g84_carry__0_CO_UNCONNECTED[3:1],g84}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,g84_carry__0_i_1_n_0}),
.O(NLW_g84_carry__0_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,g84_carry__0_i_2_n_0}));
LUT2 #(
.INIT(4'hE))
g84_carry__0_i_1
(.I0(g83__0_carry__1_n_7),
.I1(g83__0_carry__1_n_2),
.O(g84_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry__0_i_2
(.I0(g83__0_carry__1_n_7),
.I1(g83__0_carry__1_n_2),
.O(g84_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_1
(.I0(g83__0_carry__0_n_5),
.I1(g83__0_carry__0_n_4),
.O(g84_carry_i_1_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_2
(.I0(g83__0_carry__0_n_7),
.I1(g83__0_carry__0_n_6),
.O(g84_carry_i_2_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_3
(.I0(g83__0_carry_n_5),
.I1(g83__0_carry_n_4),
.O(g84_carry_i_3_n_0));
LUT2 #(
.INIT(4'hE))
g84_carry_i_4
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_6),
.O(g84_carry_i_4_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_5
(.I0(g83__0_carry__0_n_5),
.I1(g83__0_carry__0_n_4),
.O(g84_carry_i_5_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_6
(.I0(g83__0_carry__0_n_7),
.I1(g83__0_carry__0_n_6),
.O(g84_carry_i_6_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_7
(.I0(g83__0_carry_n_5),
.I1(g83__0_carry_n_4),
.O(g84_carry_i_7_n_0));
LUT2 #(
.INIT(4'h1))
g84_carry_i_8
(.I0(g83__0_carry_n_7),
.I1(g83__0_carry_n_6),
.O(g84_carry_i_8_n_0));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[0]_i_1
(.I0(g81__206_carry__2_n_7),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_7),
.O(g810_in[0]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[1]_i_1
(.I0(g81__206_carry__2_n_6),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_6),
.O(g810_in[1]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[2]_i_1
(.I0(g81__206_carry__2_n_5),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_5),
.O(g810_in[2]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[3]_i_1
(.I0(g81__206_carry__2_n_4),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry_n_4),
.O(g810_in[3]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[4]_i_1
(.I0(g81__206_carry__3_n_7),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_7),
.O(g810_in[4]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[5]_i_1
(.I0(g81__206_carry__3_n_6),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_6),
.O(g810_in[5]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[6]_i_1
(.I0(g81__206_carry__3_n_5),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_5),
.O(g810_in[6]));
LUT6 #(
.INIT(64'hBABABABB8A8A8A88))
\g8[7]_i_1
(.I0(g81__206_carry__3_n_4),
.I1(g81__301_carry__6_n_1),
.I2(g81__261_carry__2_n_1),
.I3(g84),
.I4(_carry__1_n_2),
.I5(g81__347_carry__0_n_4),
.O(g810_in[7]));
FDRE \g8_reg[0]
(.C(clk),
.CE(1'b1),
.D(g810_in[0]),
.Q(g8[0]),
.R(1'b0));
FDRE \g8_reg[1]
(.C(clk),
.CE(1'b1),
.D(g810_in[1]),
.Q(g8[1]),
.R(1'b0));
FDRE \g8_reg[2]
(.C(clk),
.CE(1'b1),
.D(g810_in[2]),
.Q(g8[2]),
.R(1'b0));
FDRE \g8_reg[3]
(.C(clk),
.CE(1'b1),
.D(g810_in[3]),
.Q(g8[3]),
.R(1'b0));
FDRE \g8_reg[4]
(.C(clk),
.CE(1'b1),
.D(g810_in[4]),
.Q(g8[4]),
.R(1'b0));
FDRE \g8_reg[5]
(.C(clk),
.CE(1'b1),
.D(g810_in[5]),
.Q(g8[5]),
.R(1'b0));
FDRE \g8_reg[6]
(.C(clk),
.CE(1'b1),
.D(g810_in[6]),
.Q(g8[6]),
.R(1'b0));
FDRE \g8_reg[7]
(.C(clk),
.CE(1'b1),
.D(g810_in[7]),
.Q(g8[7]),
.R(1'b0));
endmodule |
module system_rgb888_to_g8_0_0
(clk,
rgb888,
g8);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [23:0]rgb888;
output [7:0]g8;
wire clk;
wire [7:0]g8;
wire [23:0]rgb888;
system_rgb888_to_g8_0_0_rgb888_to_g8 U0
(.clk(clk),
.g8(g8),
.rgb888(rgb888));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty, rd_data_count, wr_data_count, prog_full, prog_empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[9:0],wr_data_count[9:0],prog_full,prog_empty" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
endmodule |
module mem_intfc #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "1T",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane
// data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 4, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter ORDERING = "NORM",
parameter PHASE_DETECT = "OFF" , // to phy_top
parameter IBUF_LPWR_MODE = "OFF", // to phy_top
parameter IODELAY_HP_MODE = "ON", // to phy_top
parameter IODELAY_GRP = "IODELAY_MIG", //to phy_top
parameter OUTPUT_DRV = "HIGH" , // to phy_top
parameter REG_CTRL = "OFF" , // to phy_top
parameter RTT_NOM = "60" , // to phy_top
parameter RTT_WR = "120" , // to phy_top
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter WRLVL = "OFF" , // to phy_top
parameter DEBUG_PORT = "OFF" , // to phy_top
parameter CAL_WIDTH = "HALF" , // to phy_top
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter nDQS_COL0 = DQS_WIDTH,
parameter nDQS_COL1 = 0,
parameter nDQS_COL2 = 0,
parameter nDQS_COL3 = 0,
parameter DQS_LOC_COL0 = 144'h11100F0E0D0C0B0A09080706050403020100,
parameter DQS_LOC_COL1 = 0,
parameter DQS_LOC_COL2 = 0,
parameter DQS_LOC_COL3 = 0,
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1 // Support ODT output
)
(
input clk_ref,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input [BANK_WIDTH-1:0] bank, // To mc0 of mc.v
input clk ,
input [2:0] cmd, // To mc0 of mc.v
input [COL_WIDTH-1:0] col, // To mc0 of mc.v
input correct_en,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, // To mc0 of mc.v
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input hi_priority, // To mc0 of mc.v
input [RANK_WIDTH-1:0] rank, // To mc0 of mc.v
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
input [ROW_WIDTH-1:0] row, // To mc0 of mc.v
input rst, // To mc0 of mc.v, ...
input size, // To mc0 of mc.v
input [7:0] slot_0_present, // To mc0 of mc.v
input [7:0] slot_1_present, // To mc0 of mc.v
input use_addr, // To mc0 of mc.v
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept, // From mc0 of mc.v
output accept_ns, // From mc0 of mc.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From mc0 of mc.v
output [255:0] dbg_calib_top,
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
output [255:0] dbg_phy_rdlvl,
output [15:0] dbg_phy_wrcal,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [4*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [4:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [ROW_WIDTH-1:0] ddr_addr, // From phy_top0 of phy_top.v
output [BANK_WIDTH-1:0] ddr_ba, // From phy_top0 of phy_top.v
output ddr_cas_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck , // From phy_top0 of phy_top.v
output [CKE_WIDTH-1:0] ddr_cke, // From phy_top0 of phy_top.v
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, // From phy_top0 of phy_top.v
output [DM_WIDTH-1:0] ddr_dm, // From phy_top0 of phy_top.v
output [RANKS-1:0] ddr_odt, // From phy_top0 of phy_top.v
output ddr_ras_n, // From phy_top0 of phy_top.v
output ddr_reset_n, // From phy_top0 of phy_top.v
output ddr_parity,
output ddr_we_n, // From phy_top0 of phy_top.v
output init_calib_complete,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
output [2*nCK_PER_CLK-1:0] ecc_single,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
// From mc0 of mc.v
output rd_data_en, // From mc0 of mc.v
output rd_data_end, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, // From mc0 of mc.v
output [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr, // From mc0 of mc.v
output wr_data_en, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset, // From mc0 of mc.v
inout [DQ_WIDTH-1:0] ddr_dq, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs_n, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs // To/From phy_top0 of phy_top.v
);
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam SLOT_0_CONFIG_MC = (nSLOTS == 2)? 8'b0000_0101 : 8'b0000_1111;
localparam SLOT_1_CONFIG_MC = (nSLOTS == 2)? 8'b0000_1010 : 8'b0000_0000;
reg [7:0] slot_0_present_mc;
reg [7:0] slot_1_present_mc;
reg user_periodic_rd_req = 1'b0;
reg user_ref_req = 1'b0;
reg user_zq_req = 1'b0;
// MC/PHY interface
wire [nCK_PER_CLK-1:0] mc_ras_n;
wire [nCK_PER_CLK-1:0] mc_cas_n;
wire [nCK_PER_CLK-1:0] mc_we_n;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n;
wire mc_reset_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
wire mc_wrdata_en;
wire mc_cmd_wren;
wire mc_ctl_wren;
wire [2:0] mc_cmd;
wire [5:0] mc_data_offset;
wire [3:0] mc_aux_out0;
wire [3:0] mc_aux_out1;
wire [1:0] mc_rank_cnt;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data;
wire phy_rddata_valid;
wire [6*RANKS-1:0] calib_rd_data_offset;
// assigning CWL = CL -1 for DDR2. DDR2 customers will not know anything
// about CWL. There is also nCWL parameter. Need to clean it up.
localparam CWL_T = (DRAM_TYPE == "DDR3") ? CWL : CL-1;
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @ (slot_0_present[0] or slot_0_present[1]
or slot_0_present[2] or slot_0_present[3]) begin
slot_0_present_mc = slot_0_present;
slot_1_present_mc = slot_1_present;
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (slot_0_present[0] or slot_0_present[1]
or slot_1_present[0] or slot_1_present[1]) begin
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
//Two slot configuration, one slot present, single rank
4'b1000: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0000;
end
4'b0010: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_0010;
end
// Two slot configuration, one slot present, dual rank
4'b1100: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0000;
end
4'b0011: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_1010;
end
// Two slot configuration, one rank per slot
4'b1010: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - One slot with dual rank and the other with single rank
4'b1011: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_1010;
end
4'b1110: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - two ranks per slot
4'b1111: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_1010;
end
endcase
end
end
endgenerate
mc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nSLOTS (nSLOTS),
.CL (CL),
.nCS_PER_RANK (nCS_PER_RANK),
.CWL (CWL_T),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.STARVE_LIMIT (STARVE_LIMIT),
.SLOT_0_CONFIG (SLOT_0_CONFIG_MC),
.SLOT_1_CONFIG (SLOT_1_CONFIG_MC),
.tCK (tCK),
.tFAW (tFAW),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS))
mc0
(.app_periodic_rd_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.rd_data (rd_data),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rd_data_offset (calib_rd_data_offset),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.correct_en (correct_en),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.hi_priority (hi_priority),
.rank (rank[RANK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1 :0]),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.size (size),
.slot_0_present (slot_0_present_mc[7:0]),
.slot_1_present (slot_1_present_mc[7:0]),
.use_addr (use_addr));
// following calculations should be moved inside PHY
// odt bus should be added to PHY.
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
localparam nCL = CL;
localparam nCWL = CWL_T;
`ifdef MC_SVA
ddr2_improper_CL: assert property
(@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL > 6) || (CL < 3)))));
// Not needed after the CWL fix for DDR2
// ddr2_improper_CWL: assert property
// (@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL - CWL) != 1))));
`endif
phy_top #
(
.TCQ (TCQ),
.REFCLK_FREQ (REFCLK_FREQ),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.nCS_PER_RANK (nCS_PER_RANK),
.CS_WIDTH (CS_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DRAM_TYPE (DRAM_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.ROW_WIDTH (ROW_WIDTH),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CL (nCL),
.CWL (nCWL),
.tRFC (tRFC),
.tCK (tCK),
.OUTPUT_DRV (OUTPUT_DRV),
.RANKS (RANKS),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.WRLVL (WRLVL),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
// Prevent the following simulation-related parameters from
// being overridden for synthesis - for synthesis only the
// default values of these parameters should be used
// synthesis translate_off
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
// synthesis translate_on
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.DEBUG_PORT (DEBUG_PORT)
)
phy_top0
(
// Outputs
.calib_rd_data_offset (calib_rd_data_offset),
.ddr_ck (ddr_ck),
.ddr_ck_n (ddr_ck_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_cke (ddr_cke),
.ddr_odt (ddr_odt),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_dm (ddr_dm),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.init_calib_complete (init_calib_complete),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
.mem_refclk (mem_refclk),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
// Inouts
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
// Inputs
.clk_ref (clk_ref),
.freq_refclk (freq_refclk),
.clk (clk),
.rst (rst),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt)
);
endmodule |
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule |
module sfifo (
clk , // Clock input
rst , // Active high reset
wr_cs , // Write chip select
rd_cs , // Read chipe select
din , // Data input
rd_en , // Read enable
wr_en , // Write Enable
dout , // Data Output
empty , // FIFO empty
full , // FIFO full
data_count // DATA count
);
// FIFO constants
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// Port Declarations
input clk ;
input rst ;
input wr_cs ;
input rd_cs ;
input rd_en ;
input wr_en ;
input [DATA_WIDTH-1:0] din ;
output full ;
output empty ;
output [DATA_WIDTH-1:0] dout ;
output [ADDR_WIDTH-1:0] data_count;
//-----------Internal variables-------------------
reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH :0] status_cnt;
reg [DATA_WIDTH-1:0] dout ;
wire [DATA_WIDTH-1:0] data_ram ;
//-----------Variable assignments---------------
assign full = (status_cnt == (RAM_DEPTH-1));
assign empty = (status_cnt == 0);
assign data_count = wr_pointer - rd_pointer;
//-----------Code Start---------------------------
always @ (posedge clk or posedge rst)
begin : WRITE_POINTER
if (rst) begin
wr_pointer <= 0;
end else if (wr_cs && wr_en ) begin
wr_pointer <= wr_pointer + 1;
end
end
always @ (posedge clk or posedge rst)
begin : READ_POINTER
if (rst) begin
rd_pointer <= 0;
end else if (rd_cs && rd_en ) begin
rd_pointer <= rd_pointer + 1;
end
end
always @ (posedge clk or posedge rst)
begin : READ_DATA
if (rst) begin
dout <= 0;
end else if (rd_cs && rd_en ) begin
dout <= data_ram;
end
end
always @ (posedge clk or posedge rst)
begin : STATUS_COUNTER
if (rst) begin
status_cnt <= 0;
// Read but no write.
end else if ((rd_cs && rd_en) && !(wr_cs && wr_en)
&& (status_cnt != 0)) begin
status_cnt <= status_cnt - 1;
// Write but no read.
end else if ((wr_cs && wr_en) && !(rd_cs && rd_en)
&& (status_cnt != RAM_DEPTH)) begin
status_cnt <= status_cnt + 1;
end
end
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
.address_0 (wr_pointer) , // address_0 input
.data_0 (din) , // data_0 bi-directional
.cs_0 (wr_cs) , // chip select
.we_0 (wr_en) , // write enable
.oe_0 (1'b0) , // output enable
.address_1 (rd_pointer) , // address_q input
.data_1 (data_ram) , // data_1 bi-directional
.cs_1 (rd_cs) , // chip select
.we_1 (1'b0) , // Read enable
.oe_1 (rd_en) // output enable
);
endmodule |
module bsg_fsb_murn_gateway
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter `BSG_INV_PARAM(id_width_p)
// resets with core reset
// rather than by a command.
, parameter enabled_at_start_p=0
// once the node is enabled
// look at all packets;
// useful if we would like to
// test and ignore packet formats
, parameter snoop_p=0
)
(input clk_i
// from/to switch
, input reset_i
, input v_i
, input [width_p-1:0] data_i
, output ready_o // note this inspects v_i, so technically is v_i->ready_o
// but the underlying bsg_test_node is true v_i / ready_o
// from node
, output v_o
, input ready_i
, output node_en_r_o
, output node_reset_r_o
);
`declare_bsg_fsb_pkt_s(width_p, id_width_p)
// if we are in snoop mode and don't need a wakeup
// packet, we keep it simple and avoid having
// a dependency on the packet format.
if (snoop_p & enabled_at_start_p)
begin
assign v_o = v_i;
assign ready_o = ready_i;
assign node_reset_r_o = reset_i;
assign node_en_r_o = 1'b1;
wire stop_lint_unused_warning = clk_i | (|data_i);
end
else
begin
logic node_en_r , node_en_n;
logic node_reset_r, node_reset_n;
assign node_en_r_o = node_en_r;
assign node_reset_r_o = node_reset_r;
bsg_fsb_pkt_s data_RPT;
assign data_RPT = bsg_fsb_pkt_s ' (data_i);
wire id_match = data_RPT.destid == id_p;
wire for_this_node = v_i & (id_match | snoop_p) ;
// once this switch is enabled, then switch packets are ignored in snoop mode
wire for_switch = ~(snoop_p & node_en_r) & v_i & (id_match) & (data_RPT.cmd == 1'b1);
// filter out traffic for switch
assign v_o = node_en_r & for_this_node & ~for_switch;
// we will sink packets:
// - if the node is not enabled
// - if the message is valid and node is actually ready for the packet
// - or if the message is not for us
assign ready_o = v_i // guard against X propagation
& (~node_en_r // node is sleeping
| ready_i // node actually is ready
| for_switch // message is for a switch
| ~for_this_node // message is for another node
);
// on "real" reset initialize node_en to 1, otherwise 0.
always_ff @(posedge clk_i)
node_en_r <= reset_i ? (enabled_at_start_p != 0) : node_en_n;
// if we are master, the reset is fed straight through
if (enabled_at_start_p)
always_ff @(posedge clk_i)
node_reset_r <= reset_i;
else
begin
// we start with reset set to high on the node
// so that it clears its stuff out
always_ff @(posedge clk_i)
if (reset_i)
node_reset_r <= 1'b1;
else
node_reset_r <= node_reset_n;
end
always_comb
begin
node_en_n = node_en_r;
node_reset_n = node_reset_r;
if (for_switch)
unique case(data_RPT.opcode)
RNENABLE_CMD: node_en_n = 1'b1;
RNDISABLE_CMD: node_en_n = 1'b0;
RNRESET_ENABLE_CMD: node_reset_n = 1'b1;
RNRESET_DISABLE_CMD: node_reset_n = 1'b0;
default:
begin
end
endcase // unique case (data_RPT.opcode)
end // always_comb
end // else: !if(snoop_p & enabled_at_start_p)
endmodule |
module bsg_fsb_murn_gateway
import bsg_fsb_pkg::*;
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(id_p)
// resets with core reset
// rather than by a command.
, parameter enabled_at_start_p=0
// once the node is enabled
// look at all packets;
// useful if we would like to
// test and ignore packet formats
, parameter snoop_p=0
)
(input clk_i
// from/to switch
, input reset_i
, input v_i
, input [width_p-1:0] data_i
, output ready_o // note this inspects v_i, so technically is v_i->ready_o
// but the underlying bsg_test_node is true v_i / ready_o
// from node
, output v_o
, input ready_i
, output node_en_r_o
, output node_reset_r_o
);
// if we are in snoop mode and don't need a wakeup
// packet, we keep it simple and avoid having
// a dependency on the packet format.
if (snoop_p & enabled_at_start_p)
begin
assign v_o = v_i;
assign ready_o = ready_i;
assign node_reset_r_o = reset_i;
assign node_en_r_o = 1'b1;
wire stop_lint_unused_warning = clk_i | (|data_i);
end
else
begin
logic node_en_r , node_en_n;
logic node_reset_r, node_reset_n;
assign node_en_r_o = node_en_r;
assign node_reset_r_o = node_reset_r;
bsg_fsb_pkt_s data_RPT;
assign data_RPT = bsg_fsb_pkt_s ' (data_i);
wire id_match = data_RPT.destid == id_p;
wire for_this_node = v_i & (id_match | snoop_p) ;
// once this switch is enabled, then switch packets are ignored in snoop mode
wire for_switch = ~(snoop_p & node_en_r) & v_i & (id_match) & (data_RPT.cmd == 1'b1);
// filter out traffic for switch
assign v_o = node_en_r & for_this_node & ~for_switch;
// we will sink packets:
// - if the node is not enabled
// - if the message is valid and node is actually ready for the packet
// - or if the message is not for us
assign ready_o = v_i // guard against X propagation
& (~node_en_r // node is sleeping
| ready_i // node actually is ready
| for_switch // message is for a switch
| ~for_this_node // message is for another node
);
// on "real" reset initialize node_en to 1, otherwise 0.
always_ff @(posedge clk_i)
node_en_r <= reset_i ? (enabled_at_start_p != 0) : node_en_n;
// if we are master, the reset is fed straight through
if (enabled_at_start_p)
always_ff @(posedge clk_i)
node_reset_r <= reset_i;
else
begin
// we start with reset set to high on the node
// so that it clears its stuff out
always_ff @(posedge clk_i)
if (reset_i)
node_reset_r <= 1'b1;
else
node_reset_r <= node_reset_n;
end
always_comb
begin
node_en_n = node_en_r;
node_reset_n = node_reset_r;
if (for_switch)
unique case(data_RPT.opcode)
RNENABLE_CMD: node_en_n = 1'b1;
RNDISABLE_CMD: node_en_n = 1'b0;
RNRESET_ENABLE_CMD: node_reset_n = 1'b1;
RNRESET_DISABLE_CMD: node_reset_n = 1'b0;
default:
begin
end
endcase // unique case (data_RPT.opcode)
end // always_comb
end // else: !if(snoop_p & enabled_at_start_p)
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.