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module sysgen_delay_2640a39ee9 (
input [(1 - 1):0] d,
input [(1 - 1):0] en,
input [(1 - 1):0] rst,
output [(1 - 1):0] q,
input clk,
input ce,
input clr);
wire d_1_22;
wire en_1_25;
wire rst_1_29;
wire op_mem_0_8_24_next;
reg op_mem_0_8_24 = 1'b0;
wire op_mem_0_8_24_rst;
wire op_mem_0_8_24_en;
wire op_mem_1_8_24_next;
reg op_mem_1_8_24 = 1'b0;
wire op_mem_1_8_24_rst;
wire op_mem_1_8_24_en;
wire op_mem_2_8_24_next;
reg op_mem_2_8_24 = 1'b0;
wire op_mem_2_8_24_rst;
wire op_mem_2_8_24_en;
wire op_mem_3_8_24_next;
reg op_mem_3_8_24 = 1'b0;
wire op_mem_3_8_24_rst;
wire op_mem_3_8_24_en;
wire op_mem_4_8_24_next;
reg op_mem_4_8_24 = 1'b0;
wire op_mem_4_8_24_rst;
wire op_mem_4_8_24_en;
wire op_mem_5_8_24_next;
reg op_mem_5_8_24 = 1'b0;
wire op_mem_5_8_24_rst;
wire op_mem_5_8_24_en;
wire op_mem_6_8_24_next;
reg op_mem_6_8_24 = 1'b0;
wire op_mem_6_8_24_rst;
wire op_mem_6_8_24_en;
wire op_mem_7_8_24_next;
reg op_mem_7_8_24 = 1'b0;
wire op_mem_7_8_24_rst;
wire op_mem_7_8_24_en;
wire op_mem_8_8_24_next;
reg op_mem_8_8_24 = 1'b0;
wire op_mem_8_8_24_rst;
wire op_mem_8_8_24_en;
wire op_mem_9_8_24_next;
reg op_mem_9_8_24 = 1'b0;
wire op_mem_9_8_24_rst;
wire op_mem_9_8_24_en;
wire op_mem_10_8_24_next;
reg op_mem_10_8_24 = 1'b0;
wire op_mem_10_8_24_rst;
wire op_mem_10_8_24_en;
wire op_mem_11_8_24_next;
reg op_mem_11_8_24 = 1'b0;
wire op_mem_11_8_24_rst;
wire op_mem_11_8_24_en;
wire op_mem_12_8_24_next;
reg op_mem_12_8_24 = 1'b0;
wire op_mem_12_8_24_rst;
wire op_mem_12_8_24_en;
wire op_mem_13_8_24_next;
reg op_mem_13_8_24 = 1'b0;
wire op_mem_13_8_24_rst;
wire op_mem_13_8_24_en;
wire op_mem_14_8_24_next;
reg op_mem_14_8_24 = 1'b0;
wire op_mem_14_8_24_rst;
wire op_mem_14_8_24_en;
wire op_mem_15_8_24_next;
reg op_mem_15_8_24 = 1'b0;
wire op_mem_15_8_24_rst;
wire op_mem_15_8_24_en;
wire op_mem_16_8_24_next;
reg op_mem_16_8_24 = 1'b0;
wire op_mem_16_8_24_rst;
wire op_mem_16_8_24_en;
localparam [(5 - 1):0] const_value = 5'b10001;
reg op_mem_0_join_10_5;
reg op_mem_0_join_10_5_en;
reg op_mem_0_join_10_5_rst;
reg op_mem_2_join_10_5;
reg op_mem_2_join_10_5_en;
reg op_mem_2_join_10_5_rst;
reg op_mem_5_join_10_5;
reg op_mem_5_join_10_5_en;
reg op_mem_5_join_10_5_rst;
reg op_mem_13_join_10_5;
reg op_mem_13_join_10_5_en;
reg op_mem_13_join_10_5_rst;
reg op_mem_4_join_10_5;
reg op_mem_4_join_10_5_en;
reg op_mem_4_join_10_5_rst;
reg op_mem_7_join_10_5;
reg op_mem_7_join_10_5_en;
reg op_mem_7_join_10_5_rst;
reg op_mem_15_join_10_5;
reg op_mem_15_join_10_5_en;
reg op_mem_15_join_10_5_rst;
reg op_mem_6_join_10_5;
reg op_mem_6_join_10_5_en;
reg op_mem_6_join_10_5_rst;
reg op_mem_12_join_10_5;
reg op_mem_12_join_10_5_en;
reg op_mem_12_join_10_5_rst;
reg op_mem_3_join_10_5;
reg op_mem_3_join_10_5_en;
reg op_mem_3_join_10_5_rst;
reg op_mem_16_join_10_5;
reg op_mem_16_join_10_5_en;
reg op_mem_16_join_10_5_rst;
reg op_mem_10_join_10_5;
reg op_mem_10_join_10_5_en;
reg op_mem_10_join_10_5_rst;
reg op_mem_1_join_10_5;
reg op_mem_1_join_10_5_en;
reg op_mem_1_join_10_5_rst;
reg op_mem_8_join_10_5;
reg op_mem_8_join_10_5_en;
reg op_mem_8_join_10_5_rst;
reg op_mem_14_join_10_5;
reg op_mem_14_join_10_5_en;
reg op_mem_14_join_10_5_rst;
reg op_mem_9_join_10_5;
reg op_mem_9_join_10_5_en;
reg op_mem_9_join_10_5_rst;
reg op_mem_11_join_10_5;
reg op_mem_11_join_10_5_en;
reg op_mem_11_join_10_5_rst;
assign d_1_22 = d;
assign en_1_25 = en;
assign rst_1_29 = rst;
always @(posedge clk)
begin:proc_op_mem_0_8_24
if (((ce == 1'b1) && (op_mem_0_8_24_rst == 1'b1)))
begin
op_mem_0_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_0_8_24_en == 1'b1)))
begin
op_mem_0_8_24 <= op_mem_0_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_1_8_24
if (((ce == 1'b1) && (op_mem_1_8_24_rst == 1'b1)))
begin
op_mem_1_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_1_8_24_en == 1'b1)))
begin
op_mem_1_8_24 <= op_mem_1_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_2_8_24
if (((ce == 1'b1) && (op_mem_2_8_24_rst == 1'b1)))
begin
op_mem_2_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_2_8_24_en == 1'b1)))
begin
op_mem_2_8_24 <= op_mem_2_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_3_8_24
if (((ce == 1'b1) && (op_mem_3_8_24_rst == 1'b1)))
begin
op_mem_3_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_3_8_24_en == 1'b1)))
begin
op_mem_3_8_24 <= op_mem_3_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_4_8_24
if (((ce == 1'b1) && (op_mem_4_8_24_rst == 1'b1)))
begin
op_mem_4_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_4_8_24_en == 1'b1)))
begin
op_mem_4_8_24 <= op_mem_4_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_5_8_24
if (((ce == 1'b1) && (op_mem_5_8_24_rst == 1'b1)))
begin
op_mem_5_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_5_8_24_en == 1'b1)))
begin
op_mem_5_8_24 <= op_mem_5_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_6_8_24
if (((ce == 1'b1) && (op_mem_6_8_24_rst == 1'b1)))
begin
op_mem_6_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_6_8_24_en == 1'b1)))
begin
op_mem_6_8_24 <= op_mem_6_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_7_8_24
if (((ce == 1'b1) && (op_mem_7_8_24_rst == 1'b1)))
begin
op_mem_7_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_7_8_24_en == 1'b1)))
begin
op_mem_7_8_24 <= op_mem_7_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_8_8_24
if (((ce == 1'b1) && (op_mem_8_8_24_rst == 1'b1)))
begin
op_mem_8_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_8_8_24_en == 1'b1)))
begin
op_mem_8_8_24 <= op_mem_8_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_9_8_24
if (((ce == 1'b1) && (op_mem_9_8_24_rst == 1'b1)))
begin
op_mem_9_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_9_8_24_en == 1'b1)))
begin
op_mem_9_8_24 <= op_mem_9_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_10_8_24
if (((ce == 1'b1) && (op_mem_10_8_24_rst == 1'b1)))
begin
op_mem_10_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_10_8_24_en == 1'b1)))
begin
op_mem_10_8_24 <= op_mem_10_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_11_8_24
if (((ce == 1'b1) && (op_mem_11_8_24_rst == 1'b1)))
begin
op_mem_11_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_11_8_24_en == 1'b1)))
begin
op_mem_11_8_24 <= op_mem_11_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_12_8_24
if (((ce == 1'b1) && (op_mem_12_8_24_rst == 1'b1)))
begin
op_mem_12_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_12_8_24_en == 1'b1)))
begin
op_mem_12_8_24 <= op_mem_12_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_13_8_24
if (((ce == 1'b1) && (op_mem_13_8_24_rst == 1'b1)))
begin
op_mem_13_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_13_8_24_en == 1'b1)))
begin
op_mem_13_8_24 <= op_mem_13_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_14_8_24
if (((ce == 1'b1) && (op_mem_14_8_24_rst == 1'b1)))
begin
op_mem_14_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_14_8_24_en == 1'b1)))
begin
op_mem_14_8_24 <= op_mem_14_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_15_8_24
if (((ce == 1'b1) && (op_mem_15_8_24_rst == 1'b1)))
begin
op_mem_15_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_15_8_24_en == 1'b1)))
begin
op_mem_15_8_24 <= op_mem_15_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_16_8_24
if (((ce == 1'b1) && (op_mem_16_8_24_rst == 1'b1)))
begin
op_mem_16_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_16_8_24_en == 1'b1)))
begin
op_mem_16_8_24 <= op_mem_16_8_24_next;
end
end
always @(d_1_22 or en_1_25 or op_mem_0_8_24 or op_mem_10_8_24 or op_mem_11_8_24 or op_mem_12_8_24 or op_mem_13_8_24 or op_mem_14_8_24 or op_mem_15_8_24 or op_mem_1_8_24 or op_mem_2_8_24 or op_mem_3_8_24 or op_mem_4_8_24 or op_mem_5_8_24 or op_mem_6_8_24 or op_mem_7_8_24 or op_mem_8_8_24 or op_mem_9_8_24 or rst_1_29)
begin:proc_if_10_5
if (rst_1_29)
begin
op_mem_0_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_0_join_10_5_rst = 1'b0;
end
else
begin
op_mem_0_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_0_join_10_5_en = 1'b1;
end
else
begin
op_mem_0_join_10_5_en = 1'b0;
end
op_mem_0_join_10_5 = d_1_22;
if (rst_1_29)
begin
op_mem_2_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_2_join_10_5_rst = 1'b0;
end
else
begin
op_mem_2_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_2_join_10_5_en = 1'b1;
end
else
begin
op_mem_2_join_10_5_en = 1'b0;
end
op_mem_2_join_10_5 = op_mem_1_8_24;
if (rst_1_29)
begin
op_mem_5_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_5_join_10_5_rst = 1'b0;
end
else
begin
op_mem_5_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_5_join_10_5_en = 1'b1;
end
else
begin
op_mem_5_join_10_5_en = 1'b0;
end
op_mem_5_join_10_5 = op_mem_4_8_24;
if (rst_1_29)
begin
op_mem_13_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_13_join_10_5_rst = 1'b0;
end
else
begin
op_mem_13_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_13_join_10_5_en = 1'b1;
end
else
begin
op_mem_13_join_10_5_en = 1'b0;
end
op_mem_13_join_10_5 = op_mem_12_8_24;
if (rst_1_29)
begin
op_mem_4_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_4_join_10_5_rst = 1'b0;
end
else
begin
op_mem_4_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_4_join_10_5_en = 1'b1;
end
else
begin
op_mem_4_join_10_5_en = 1'b0;
end
op_mem_4_join_10_5 = op_mem_3_8_24;
if (rst_1_29)
begin
op_mem_7_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_7_join_10_5_rst = 1'b0;
end
else
begin
op_mem_7_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_7_join_10_5_en = 1'b1;
end
else
begin
op_mem_7_join_10_5_en = 1'b0;
end
op_mem_7_join_10_5 = op_mem_6_8_24;
if (rst_1_29)
begin
op_mem_15_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_15_join_10_5_rst = 1'b0;
end
else
begin
op_mem_15_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_15_join_10_5_en = 1'b1;
end
else
begin
op_mem_15_join_10_5_en = 1'b0;
end
op_mem_15_join_10_5 = op_mem_14_8_24;
if (rst_1_29)
begin
op_mem_6_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_6_join_10_5_rst = 1'b0;
end
else
begin
op_mem_6_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_6_join_10_5_en = 1'b1;
end
else
begin
op_mem_6_join_10_5_en = 1'b0;
end
op_mem_6_join_10_5 = op_mem_5_8_24;
if (rst_1_29)
begin
op_mem_12_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_12_join_10_5_rst = 1'b0;
end
else
begin
op_mem_12_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_12_join_10_5_en = 1'b1;
end
else
begin
op_mem_12_join_10_5_en = 1'b0;
end
op_mem_12_join_10_5 = op_mem_11_8_24;
if (rst_1_29)
begin
op_mem_3_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_3_join_10_5_rst = 1'b0;
end
else
begin
op_mem_3_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_3_join_10_5_en = 1'b1;
end
else
begin
op_mem_3_join_10_5_en = 1'b0;
end
op_mem_3_join_10_5 = op_mem_2_8_24;
if (rst_1_29)
begin
op_mem_16_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_16_join_10_5_rst = 1'b0;
end
else
begin
op_mem_16_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_16_join_10_5_en = 1'b1;
end
else
begin
op_mem_16_join_10_5_en = 1'b0;
end
op_mem_16_join_10_5 = op_mem_15_8_24;
if (rst_1_29)
begin
op_mem_10_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_10_join_10_5_rst = 1'b0;
end
else
begin
op_mem_10_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_10_join_10_5_en = 1'b1;
end
else
begin
op_mem_10_join_10_5_en = 1'b0;
end
op_mem_10_join_10_5 = op_mem_9_8_24;
if (rst_1_29)
begin
op_mem_1_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_1_join_10_5_rst = 1'b0;
end
else
begin
op_mem_1_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_1_join_10_5_en = 1'b1;
end
else
begin
op_mem_1_join_10_5_en = 1'b0;
end
op_mem_1_join_10_5 = op_mem_0_8_24;
if (rst_1_29)
begin
op_mem_8_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_8_join_10_5_rst = 1'b0;
end
else
begin
op_mem_8_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_8_join_10_5_en = 1'b1;
end
else
begin
op_mem_8_join_10_5_en = 1'b0;
end
op_mem_8_join_10_5 = op_mem_7_8_24;
if (rst_1_29)
begin
op_mem_14_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_14_join_10_5_rst = 1'b0;
end
else
begin
op_mem_14_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_14_join_10_5_en = 1'b1;
end
else
begin
op_mem_14_join_10_5_en = 1'b0;
end
op_mem_14_join_10_5 = op_mem_13_8_24;
if (rst_1_29)
begin
op_mem_9_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_9_join_10_5_rst = 1'b0;
end
else
begin
op_mem_9_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_9_join_10_5_en = 1'b1;
end
else
begin
op_mem_9_join_10_5_en = 1'b0;
end
op_mem_9_join_10_5 = op_mem_8_8_24;
if (rst_1_29)
begin
op_mem_11_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_11_join_10_5_rst = 1'b0;
end
else
begin
op_mem_11_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_11_join_10_5_en = 1'b1;
end
else
begin
op_mem_11_join_10_5_en = 1'b0;
end
op_mem_11_join_10_5 = op_mem_10_8_24;
end
assign op_mem_0_8_24_next = d_1_22;
assign op_mem_0_8_24_rst = op_mem_0_join_10_5_rst;
assign op_mem_0_8_24_en = op_mem_0_join_10_5_en;
assign op_mem_1_8_24_next = op_mem_0_8_24;
assign op_mem_1_8_24_rst = op_mem_1_join_10_5_rst;
assign op_mem_1_8_24_en = op_mem_1_join_10_5_en;
assign op_mem_2_8_24_next = op_mem_1_8_24;
assign op_mem_2_8_24_rst = op_mem_2_join_10_5_rst;
assign op_mem_2_8_24_en = op_mem_2_join_10_5_en;
assign op_mem_3_8_24_next = op_mem_2_8_24;
assign op_mem_3_8_24_rst = op_mem_3_join_10_5_rst;
assign op_mem_3_8_24_en = op_mem_3_join_10_5_en;
assign op_mem_4_8_24_next = op_mem_3_8_24;
assign op_mem_4_8_24_rst = op_mem_4_join_10_5_rst;
assign op_mem_4_8_24_en = op_mem_4_join_10_5_en;
assign op_mem_5_8_24_next = op_mem_4_8_24;
assign op_mem_5_8_24_rst = op_mem_5_join_10_5_rst;
assign op_mem_5_8_24_en = op_mem_5_join_10_5_en;
assign op_mem_6_8_24_next = op_mem_5_8_24;
assign op_mem_6_8_24_rst = op_mem_6_join_10_5_rst;
assign op_mem_6_8_24_en = op_mem_6_join_10_5_en;
assign op_mem_7_8_24_next = op_mem_6_8_24;
assign op_mem_7_8_24_rst = op_mem_7_join_10_5_rst;
assign op_mem_7_8_24_en = op_mem_7_join_10_5_en;
assign op_mem_8_8_24_next = op_mem_7_8_24;
assign op_mem_8_8_24_rst = op_mem_8_join_10_5_rst;
assign op_mem_8_8_24_en = op_mem_8_join_10_5_en;
assign op_mem_9_8_24_next = op_mem_8_8_24;
assign op_mem_9_8_24_rst = op_mem_9_join_10_5_rst;
assign op_mem_9_8_24_en = op_mem_9_join_10_5_en;
assign op_mem_10_8_24_next = op_mem_9_8_24;
assign op_mem_10_8_24_rst = op_mem_10_join_10_5_rst;
assign op_mem_10_8_24_en = op_mem_10_join_10_5_en;
assign op_mem_11_8_24_next = op_mem_10_8_24;
assign op_mem_11_8_24_rst = op_mem_11_join_10_5_rst;
assign op_mem_11_8_24_en = op_mem_11_join_10_5_en;
assign op_mem_12_8_24_next = op_mem_11_8_24;
assign op_mem_12_8_24_rst = op_mem_12_join_10_5_rst;
assign op_mem_12_8_24_en = op_mem_12_join_10_5_en;
assign op_mem_13_8_24_next = op_mem_12_8_24;
assign op_mem_13_8_24_rst = op_mem_13_join_10_5_rst;
assign op_mem_13_8_24_en = op_mem_13_join_10_5_en;
assign op_mem_14_8_24_next = op_mem_13_8_24;
assign op_mem_14_8_24_rst = op_mem_14_join_10_5_rst;
assign op_mem_14_8_24_en = op_mem_14_join_10_5_en;
assign op_mem_15_8_24_next = op_mem_14_8_24;
assign op_mem_15_8_24_rst = op_mem_15_join_10_5_rst;
assign op_mem_15_8_24_en = op_mem_15_join_10_5_en;
assign op_mem_16_8_24_next = op_mem_15_8_24;
assign op_mem_16_8_24_rst = op_mem_16_join_10_5_rst;
assign op_mem_16_8_24_en = op_mem_16_join_10_5_en;
assign q = op_mem_16_8_24;
endmodule |
module sysgen_delay_52cccd8896 (
input [(1 - 1):0] d,
input [(1 - 1):0] en,
input [(1 - 1):0] rst,
output [(1 - 1):0] q,
input clk,
input ce,
input clr);
wire d_1_22;
wire en_1_25;
wire rst_1_29;
wire op_mem_0_8_24_next;
reg op_mem_0_8_24 = 1'b0;
wire op_mem_0_8_24_rst;
wire op_mem_0_8_24_en;
localparam [(1 - 1):0] const_value = 1'b1;
reg op_mem_0_join_10_5;
reg op_mem_0_join_10_5_en;
reg op_mem_0_join_10_5_rst;
assign d_1_22 = d;
assign en_1_25 = en;
assign rst_1_29 = rst;
always @(posedge clk)
begin:proc_op_mem_0_8_24
if (((ce == 1'b1) && (op_mem_0_8_24_rst == 1'b1)))
begin
op_mem_0_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_0_8_24_en == 1'b1)))
begin
op_mem_0_8_24 <= op_mem_0_8_24_next;
end
end
always @(d_1_22 or en_1_25 or rst_1_29)
begin:proc_if_10_5
if (rst_1_29)
begin
op_mem_0_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_0_join_10_5_rst = 1'b0;
end
else
begin
op_mem_0_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_0_join_10_5_en = 1'b1;
end
else
begin
op_mem_0_join_10_5_en = 1'b0;
end
op_mem_0_join_10_5 = d_1_22;
end
assign op_mem_0_8_24_next = d_1_22;
assign op_mem_0_8_24_rst = op_mem_0_join_10_5_rst;
assign op_mem_0_8_24_en = op_mem_0_join_10_5_en;
assign q = op_mem_0_8_24;
endmodule |
module sysgen_reinterpret_4bd3487388 (
input [(34 - 1):0] input_port,
output [(34 - 1):0] output_port,
input clk,
input ce,
input clr);
wire signed [(34 - 1):0] input_port_1_40;
wire [(34 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule |
module sysgen_constant_1aff05159a (
output [(4 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 4'b1111;
endmodule |
module sysgen_relational_f303c211e7 (
input [(4 - 1):0] a,
input [(4 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(4 - 1):0] a_1_31;
wire [(4 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule |
module sysgen_relational_fc1426e2d9 (
input [(8 - 1):0] a,
input [(8 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(8 - 1):0] a_1_31;
wire [(8 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule |
module sysgen_relational_9133ff9c4b (
input [(2 - 1):0] a,
input [(2 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(2 - 1):0] a_1_31;
wire [(2 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule |
module sysgen_constant_07b701207a (
output [(8 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 8'b11001000;
endmodule |
module sysgen_constant_118900d9b9 (
output [(2 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 2'b11;
endmodule |
module channelizer_xlaxififogen(
s_aclk,
ce,
aresetn,
axis_underflow,
axis_overflow,
axis_data_count,
axis_prog_full_thresh,
axis_prog_empty_thresh,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
s_axis_tvalid,
s_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
m_axis_tvalid,
m_axis_tready
);
parameter core_name0 = "";
parameter has_aresetn = -1;
parameter tdata_width = -1;
parameter tdest_width = -1;
parameter tstrb_width = -1;
parameter tkeep_width = -1;
parameter tid_width = -1;
parameter tuser_width = -1;
parameter depth_bits = -1;
input ce;
input s_aclk;
input aresetn;
output axis_underflow;
output axis_overflow;
output [depth_bits-1:0] axis_data_count;
input [depth_bits-2:0] axis_prog_full_thresh;
input [depth_bits-2:0] axis_prog_empty_thresh;
input [tdata_width-1:0] s_axis_tdata;
input [tstrb_width-1:0] s_axis_tstrb;
input [tkeep_width-1:0] s_axis_tkeep;
input s_axis_tlast;
input [tid_width-1:0] s_axis_tid;
input [tdest_width-1:0] s_axis_tdest;
input [tuser_width-1:0] s_axis_tuser;
input s_axis_tvalid;
output s_axis_tready;
output [tdata_width-1:0] m_axis_tdata;
output [tstrb_width-1:0] m_axis_tstrb;
output [tkeep_width-1:0] m_axis_tkeep;
output m_axis_tlast;
output [tid_width-1:0] m_axis_tid;
output [tdest_width-1:0] m_axis_tdest;
output [tuser_width-1:0] m_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
wire srst;
reg reset_gen1 = 1'b0;
reg reset_gen_d1 = 1'b0;
reg reset_gen_d2 = 1'b0;
always @(posedge s_aclk)
begin
reset_gen1 <= 1'b1;
reset_gen_d1 <= reset_gen1;
reset_gen_d2 <= reset_gen_d1;
end
generate
if(has_aresetn == 0)
begin:if_block
assign srst = reset_gen_d2;
end
else
begin:else_block
assign srst = ~((~aresetn) & ce);
end
endgenerate
generate
if (core_name0 == "channelizer_fifo_generator_v12_0_0")
begin:comp0
channelizer_fifo_generator_v12_0_0 core_instance0 (
.s_aclk(s_aclk),
.s_aresetn(srst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid (s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid (m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready)
);
end
endgenerate
endmodule |
module channelizer_xlcounter_free (ce, clr, clk, op, up, load, din, en, rst);
parameter core_name0= "";
parameter op_width= 5;
parameter op_arith= `xlSigned;
input ce, clr, clk;
input up, load;
input [op_width-1:0] din;
input en, rst;
output [op_width-1:0] op;
parameter [(8*op_width)-1:0] oneStr = { op_width{"1"}};
wire core_sinit;
wire core_ce;
wire [op_width-1:0] op_net;
assign core_ce = ce & en;
assign core_sinit = (clr | rst) & ce;
assign op = op_net;
generate
if (core_name0 == "channelizer_c_counter_binary_v12_0_0")
begin:comp0
channelizer_c_counter_binary_v12_0_0 core_instance0 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
if (core_name0 == "channelizer_c_counter_binary_v12_0_1")
begin:comp1
channelizer_c_counter_binary_v12_0_1 core_instance1 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
if (core_name0 == "channelizer_c_counter_binary_v12_0_2")
begin:comp2
channelizer_c_counter_binary_v12_0_2 core_instance2 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
if (core_name0 == "channelizer_c_counter_binary_v12_0_3")
begin:comp3
channelizer_c_counter_binary_v12_0_3 core_instance3 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
endgenerate
endmodule |
module channelizer_xldpram (dina, addra, wea, a_ce, a_clk, rsta, ena, douta, dinb, addrb, web, b_ce, b_clk, rstb, enb, doutb);
parameter core_name0= "";
parameter c_width_a= 13;
parameter c_address_width_a= 4;
parameter c_width_b= 13;
parameter c_address_width_b= 4;
parameter latency= 1;
input [c_width_a-1:0] dina;
input [c_address_width_a-1:0] addra;
input wea, a_ce, a_clk, rsta, ena;
input [c_width_b-1:0] dinb;
input [c_address_width_b-1:0] addrb;
input web, b_ce, b_clk, rstb, enb;
output [c_width_a-1:0] douta;
output [c_width_b-1:0] doutb;
wire [c_address_width_a-1:0] core_addra;
wire [c_address_width_b-1:0] core_addrb;
wire [c_width_a-1:0] core_dina,core_douta,dly_douta;
wire [c_width_b-1:0] core_dinb,core_doutb,dly_doutb;
wire core_wea,core_web;
wire core_a_ce,core_b_ce;
wire sinita,sinitb;
assign core_addra = addra;
assign core_dina = dina;
assign douta = dly_douta;
assign core_wea = wea;
assign core_a_ce = a_ce & ena;
assign sinita = rsta & a_ce;
assign core_addrb = addrb;
assign core_dinb = dinb;
assign doutb = dly_doutb;
assign core_web = web;
assign core_b_ce = b_ce & enb;
assign sinitb = rstb & b_ce;
generate
if (core_name0 == "channelizer_blk_mem_gen_v8_2_0")
begin:comp0
channelizer_blk_mem_gen_v8_2_0 core_instance0 (
.addra(core_addra),
.clka(a_clk),
.addrb(core_addrb),
.clkb(b_clk),
.dina(core_dina),
.wea(core_wea),
.dinb(core_dinb),
.web(core_web),
.ena(core_a_ce),
.enb(core_b_ce),
.rsta(sinita),
.rstb(sinitb),
.douta(core_douta),
.doutb(core_doutb)
);
end
if (latency > 2)
begin:latency_test_instA
synth_reg # (c_width_a, latency-2)
regA(
.i(core_douta),
.ce(core_a_ce),
.clr(1'b0),
.clk(a_clk),
.o(dly_douta));
end
if (latency > 2)
begin:latency_test_instB
synth_reg # (c_width_b, latency-2)
regB(
.i(core_doutb),
.ce(core_b_ce),
.clr(1'b0),
.clk(b_clk),
.o(dly_doutb));
end
if (latency <= 2)
begin:latency1
assign dly_douta = core_douta;
assign dly_doutb = core_doutb;
end
endgenerate
endmodule |
module xlfast_fourier_transform_c87919ddd6bfbf81b10158bf539068dc (ce,clk,event_data_in_channel_halt,event_data_out_channel_halt,event_frame_started,event_status_channel_halt,event_tlast_missing,event_tlast_unexpected,m_axis_data_tdata_xn_im_0,m_axis_data_tdata_xn_re_0,m_axis_data_tlast,m_axis_data_tready,m_axis_data_tvalid,rst,s_axis_config_tdata_fwd_inv,s_axis_config_tready,s_axis_config_tvalid,s_axis_data_tdata_xn_im_0,s_axis_data_tdata_xn_re_0,s_axis_data_tlast,s_axis_data_tready,s_axis_data_tvalid);
input ce;
input clk;
output event_data_in_channel_halt;
output event_data_out_channel_halt;
output event_frame_started;
output event_status_channel_halt;
output event_tlast_missing;
output event_tlast_unexpected;
output[20:0] m_axis_data_tdata_xn_im_0;
output[20:0] m_axis_data_tdata_xn_re_0;
output m_axis_data_tlast;
input m_axis_data_tready;
output m_axis_data_tvalid;
input rst;
input[0:0] s_axis_config_tdata_fwd_inv;
output s_axis_config_tready;
input s_axis_config_tvalid;
input[15:0] s_axis_data_tdata_xn_im_0;
input[15:0] s_axis_data_tdata_xn_re_0;
input s_axis_data_tlast;
output s_axis_data_tready;
input s_axis_data_tvalid;
wire aresetn_net;
wire[47:0] m_axis_data_tdata_net;
wire[7:0] s_axis_config_tdata_net;
wire[31:0] s_axis_data_tdata_net;
assign aresetn_net = rst | (~ ce);
assign m_axis_data_tdata_xn_im_0 = m_axis_data_tdata_net[44 : 24];
assign m_axis_data_tdata_xn_re_0 = m_axis_data_tdata_net[20 : 0];
assign s_axis_config_tdata_net[7 : 1] = 7'b0;
assign s_axis_config_tdata_net[0 : 0] = s_axis_config_tdata_fwd_inv;
assign s_axis_data_tdata_net[31 : 16] = s_axis_data_tdata_xn_im_0;
assign s_axis_data_tdata_net[15 : 0] = s_axis_data_tdata_xn_re_0;
channelizer_xfft_v9_0_0 channelizer_xfft_v9_0_0_instance(
.aclk(clk),
.aclken(ce),
.aresetn(aresetn_net),
.event_data_in_channel_halt(event_data_in_channel_halt),
.event_data_out_channel_halt(event_data_out_channel_halt),
.event_frame_started(event_frame_started),
.event_status_channel_halt(event_status_channel_halt),
.event_tlast_missing(event_tlast_missing),
.event_tlast_unexpected(event_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata_net),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(s_axis_config_tdata_net),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_data_tdata(s_axis_data_tdata_net),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid)
);
endmodule |
module xlfir_compiler_19490f93cbd7e22fee0db5c2ec90c7a6 (ce,clk,event_s_config_tlast_missing,event_s_config_tlast_unexpected,event_s_data_tlast_missing,event_s_data_tlast_unexpected,m_axis_data_tdata_path0,m_axis_data_tdata_path1,m_axis_data_tlast,m_axis_data_tready,m_axis_data_tvalid,rst,s_axis_config_tdata_fsel,s_axis_config_tlast,s_axis_config_tready,s_axis_config_tvalid,s_axis_data_tdata_path0,s_axis_data_tdata_path1,s_axis_data_tlast,s_axis_data_tready,s_axis_data_tvalid,src_ce,src_clk);
input ce;
input clk;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
output event_s_data_tlast_missing;
output event_s_data_tlast_unexpected;
output[33:0] m_axis_data_tdata_path0;
output[33:0] m_axis_data_tdata_path1;
output m_axis_data_tlast;
input m_axis_data_tready;
output m_axis_data_tvalid;
input rst;
input[3:0] s_axis_config_tdata_fsel;
input s_axis_config_tlast;
output s_axis_config_tready;
input s_axis_config_tvalid;
input[17:0] s_axis_data_tdata_path0;
input[17:0] s_axis_data_tdata_path1;
input s_axis_data_tlast;
output s_axis_data_tready;
input s_axis_data_tvalid;
input src_ce;
input src_clk;
wire aresetn_net;
wire[79:0] m_axis_data_tdata_net;
wire[7:0] s_axis_config_tdata_net;
wire[47:0] s_axis_data_tdata_net;
assign aresetn_net = rst | (~ ce);
assign m_axis_data_tdata_path1 = m_axis_data_tdata_net[73 : 40];
assign m_axis_data_tdata_path0 = m_axis_data_tdata_net[33 : 0];
assign s_axis_config_tdata_net[7 : 4] = 4'b0;
assign s_axis_config_tdata_net[3 : 0] = s_axis_config_tdata_fsel;
assign s_axis_data_tdata_net[47 : 42] = 6'b0;
assign s_axis_data_tdata_net[41 : 24] = s_axis_data_tdata_path1;
assign s_axis_data_tdata_net[23 : 18] = 6'b0;
assign s_axis_data_tdata_net[17 : 0] = s_axis_data_tdata_path0;
channelizer_fir_compiler_v7_2_0 channelizer_fir_compiler_v7_2_0_instance(
.aclk(clk),
.aclken(ce),
.aresetn(aresetn_net),
.event_s_config_tlast_missing(event_s_config_tlast_missing),
.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected),
.event_s_data_tlast_missing(event_s_data_tlast_missing),
.event_s_data_tlast_unexpected(event_s_data_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata_net),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(s_axis_config_tdata_net),
.s_axis_config_tlast(s_axis_config_tlast),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_data_tdata(s_axis_data_tdata_net),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid)
);
endmodule |
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg KAPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__dlybuf4s18kapwr dut (.A(A), .VPWR(VPWR), .VGND(VGND), .KAPWR(KAPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module dbg_comm_vpi (
SYS_CLK,
P_TMS,
P_TCK,
P_TRST,
P_TDI,
P_TDO
);
//parameter Tp = 20;
input SYS_CLK;
output P_TMS;
output P_TCK;
output P_TRST;
output P_TDI;
input P_TDO;
reg [4:0] memory; // [0:0];
wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;
reg [3:0] in_word_r;
reg [5:0] clk_count;
// Handle commands from the upper level
initial
begin
in_word_r = 5'b0;
memory = 5'b0;
$jp_init(`JP_PORT);
#5500; // Wait until reset is complete
while(1)
begin
#1;
$jp_in(memory); // This will not change memory[][] if no command has been sent from jp
if(memory[4]) // was memory[0][4]
begin
in_word_r = memory[3:0];
memory = memory & 4'b1111;
clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
end
end
end
// Send the output bit to the upper layer
always @ (P_TDO)
begin
$jp_out(P_TDO);
end
assign P_TCK = in_word_r[0];
assign P_TRST = in_word_r[1];
assign P_TDI = in_word_r[2];
assign P_TMS = in_word_r[3];
// Send timeouts / wait periods to the upper layer
always @ (posedge SYS_CLK)
begin
if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
else if(clk_count == `TIMEOUT_COUNT) begin
$jp_wait_time();
clk_count[5:0] = clk_count[5:0] + 1;
end
// else it's already timed out, don't do anything
end
endmodule |
module limbus_tristate_conduit_pin_sharer_0 (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [18:0] sram_tcm_address_out, // .sram_tcm_address_out_out
output wire [1:0] sram_tcm_byteenable_n_out, // .sram_tcm_byteenable_n_out_out
output wire [0:0] sram_tcm_outputenable_n_out, // .sram_tcm_outputenable_n_out_out
output wire [0:0] sram_tcm_write_n_out, // .sram_tcm_write_n_out_out
output wire [15:0] sram_tcm_data_out, // .sram_tcm_data_out_out
input wire [15:0] sram_tcm_data_in, // .sram_tcm_data_out_in
output wire sram_tcm_data_outen, // .sram_tcm_data_out_outen
output wire [0:0] sram_tcm_chipselect_n_out, // .sram_tcm_chipselect_n_out_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [18:0] tcs0_address_out, // .address_out
input wire [1:0] tcs0_byteenable_n_out, // .byteenable_n_out
input wire [0:0] tcs0_outputenable_n_out, // .outputenable_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [15:0] tcs0_data_out, // .data_out
output wire [15:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [0:0] tcs0_chipselect_n_out // .chipselect_n_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_sram_tcm -> arbiter:sink0_valid
limbus_tristate_conduit_pin_sharer_0_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.sram_tcm_address_out (sram_tcm_address_out), // .sram_tcm_address_out_out
.sram_tcm_byteenable_n_out (sram_tcm_byteenable_n_out), // .sram_tcm_byteenable_n_out_out
.sram_tcm_outputenable_n_out (sram_tcm_outputenable_n_out), // .sram_tcm_outputenable_n_out_out
.sram_tcm_write_n_out (sram_tcm_write_n_out), // .sram_tcm_write_n_out_out
.sram_tcm_data_out (sram_tcm_data_out), // .sram_tcm_data_out_out
.sram_tcm_data_in (sram_tcm_data_in), // .sram_tcm_data_out_in
.sram_tcm_data_outen (sram_tcm_data_outen), // .sram_tcm_data_out_outen
.sram_tcm_chipselect_n_out (sram_tcm_chipselect_n_out), // .sram_tcm_chipselect_n_out_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_byteenable_n_out (tcs0_byteenable_n_out), // .byteenable_n_out
.tcs0_tcm_outputenable_n_out (tcs0_outputenable_n_out), // .outputenable_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_sram_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
limbus_tristate_conduit_pin_sharer_0_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule |
module quadpwm(rst_n, freq_clk, enable, mode, led);
input rst_n;
input freq_clk;
input enable;
input mode;
output pwm0;
output pwm1;
output pwm2;
output pwm3;
reg pwm0_reg;
reg pwm1_reg;
reg pwm2_reg;
reg pwm3_reg;
reg[31:0] engine_reg;
//debug led
reg led;
// generate 2500 Hz from 50 MHz
reg [31:0] count_reg;
reg pwm_clk;
always @(posedge freq_clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
pwm_clk <= 0;
end
else if (enable)
begin
if (count_reg < 999999) begin
count_reg <= count_reg + 1;
end else begin
count_reg <= 0;
pwm_clk <= ~pwm_clk;
end
end
end
reg[31:0] pwm_load_register;
/*process the pwm0 signal period*/
always @ (posedge pwm_clk or negedge rst_n)
begin
if (!rst_n)
begin
pwm_load_register <= 1'b0;
end
else if (out_div)
begin
case (pha_reg)
1'd1:
begin
pha_reg <= 1'd0;
end
1'd0:
begin
pha_reg <= 1'd1;
end
endcase
end
end
assign pwm0 = pwm0_reg;
endmodule |
module rom ( input [7:0] addr,output reg [15:0] dout );
always @ (addr)
case (addr)
8'b0000_0000: dout = 16'b0111_0000_0001_0111; ///addi r1,r0,#7;
8'b0000_0001: dout = 16'b1000_0001_0010_0010; //Subi r2,r1,#2
8'b0000_0010: dout = 16'b1010_0000_0010_0000; //store [r0],r2
8'b0000_0011: dout = 16'b1001_0000_0011_0000; //load r3 [r0]
8'b0000_0100: dout = 16'b0001_0001_0010_0100; //add r4,r1,r2
8'b0000_0101: dout = 16'b0010_0100_0010_0101; //Sub r5,r4,r2
8'b0000_0110: dout = 16'b1100_0000_0101_0001; //stori [1],$r5;
8'b0000_0111: dout = 16'b1011_0000_0110_0001; //loadi r6,[1];
8'b0000_1000: dout = 16'b0101_0100_0111_0011; //SHL r7, r4,#3
8'b0000_1001: dout = 16'b0110_0100_1000_0010; //SHR r8,r4,#2
8'b0000_1010: dout = 16'b0011_0100_0001_1001; //AND R9, R4, R1;
8'b0000_1011: dout = 16'b0100_0100_0010_1010; //OR R10, R4, R2;
8'b0000_1100: dout = 16'b1101_0110_0101_0111; //Bre Jump R10, R4, R2;
8'b0000_1101: dout = 16'b0000_0000_0000_0000; //Halt
default: dout = 16'h0000;
endcase
endmodule |
module usbHostSlaveAvalonWrap(
clk,
reset,
address,
writedata,
readdata,
write,
read,
waitrequest,
chipselect,
irq,
usbClk,
USBWireVPI,
USBWireVMI,
USBWireDataInTick,
USBWireVPO,
USBWireVMO,
USBWireDataOutTick,
USBWireOutEn_n,
USBFullSpeed
);
input clk;
input reset;
input [7:0] address;
input [7:0] writedata;
output [7:0] readdata;
input write;
input read;
output waitrequest;
input chipselect;
output irq;
input usbClk;
input USBWireVPI /* synthesis useioff=1 */;
input USBWireVMI /* synthesis useioff=1 */;
output USBWireVPO /* synthesis useioff=1 */;
output USBWireVMO /* synthesis useioff=1 */;
output USBWireDataOutTick /* synthesis useioff=1 */;
output USBWireDataInTick /* synthesis useioff=1 */;
output USBWireOutEn_n /* synthesis useioff=1 */;
output USBFullSpeed /* synthesis useioff=1 */;
wire clk;
wire reset;
wire [7:0] address;
wire [7:0] writedata;
wire [7:0] readdata;
wire write;
wire read;
wire waitrequest;
wire chipselect;
wire irq;
wire usbClk;
wire USBWireVPI;
wire USBWireVMI;
wire USBWireVPO;
wire USBWireVMO;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireOutEn_n;
wire USBFullSpeed;
//internal wiring
wire strobe_i;
wire ack_o;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
assign irq = hostSOFSentIntOut | hostConnEventIntOut |
hostResumeIntOut | hostTransDoneIntOut |
slaveSOFRxedIntOut | slaveResetEventIntOut |
slaveResumeIntOut | slaveTransDoneIntOut |
slaveNAKSentIntOut;
assign strobe_i = chipselect & ( read | write);
assign waitrequest = ~ack_o;
assign USBWireOutEn_n = ~USBWireCtrlOut;
assign USBWireDataIn = {USBWireVPI, USBWireVMI};
assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
//Parameters declaration:
defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
parameter HOST_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
parameter HOST_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
parameter EP0_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_ADDR_WIDTH = 6;
usbHostSlave usbHostSlaveInst (
.clk_i(clk),
.rst_i(reset),
.address_i(address),
.data_i(writedata),
.data_o(readdata),
.we_i(write),
.strobe_i(strobe_i),
.ack_o(ack_o),
.usbClk(usbClk),
.hostSOFSentIntOut(hostSOFSentIntOut),
.hostConnEventIntOut(hostConnEventIntOut),
.hostResumeIntOut(hostResumeIntOut),
.hostTransDoneIntOut(hostTransDoneIntOut),
.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
.slaveResetEventIntOut(slaveResetEventIntOut),
.slaveResumeIntOut(slaveResumeIntOut),
.slaveTransDoneIntOut(slaveTransDoneIntOut),
.slaveNAKSentIntOut(slaveNAKSentIntOut),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed));
endmodule |
module sky130_fd_sc_hd__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module test_setup();
// clock_generator_0_wb_system_to_wb_example_0_wb_system wires:
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
// Ad-hoc wires:
wire wb_example_0_start_to_wb_example_bench_0_start;
wire wb_example_0_done_to_wb_example_bench_0_done;
wire wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
wire wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// wb_example.bench_0 port wires:
wire wb_example_bench_0_clk_i;
wire wb_example_bench_0_done;
wire wb_example_bench_0_rst_i;
wire wb_example_bench_0_start;
// wb_example_0 port wires:
wire wb_example_0_clk_i;
wire wb_example_0_done;
wire wb_example_0_rst_i;
wire wb_example_0_start;
// clock_generator_0 assignments:
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_example_bench_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemrst = clock_generator_0_rst_o;
assign wb_example_bench_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
// wb_example.bench_0 assignments:
assign wb_example_bench_0_clk_i = wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
assign wb_example_bench_0_done = wb_example_0_done_to_wb_example_bench_0_done;
assign wb_example_bench_0_rst_i = wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
assign wb_example_0_start_to_wb_example_bench_0_start = wb_example_bench_0_start;
// wb_example_0 assignments:
assign wb_example_0_clk_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
assign wb_example_0_done_to_wb_example_bench_0_done = wb_example_0_done;
assign wb_example_0_rst_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
assign wb_example_0_start = wb_example_0_start_to_wb_example_bench_0_start;
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0(
// Interface: wb_system
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
// IP-XACT VLNV: tut.fi:other.subsystem.test:wb_example.bench:1.0
TestInitializer #(
.WAIT_TIME (1200))
wb_example_bench_0(
// These ports are not in any interface
.clk_i (wb_example_bench_0_clk_i),
.done (wb_example_bench_0_done),
.rst_i (wb_example_bench_0_rst_i),
.start (wb_example_bench_0_start));
// IP-XACT VLNV: tut.fi:other.subsystem:wb_example:1.0
wb_example_0 wb_example_0(
// Interface: wb_system
.clk_i (wb_example_0_clk_i),
.rst_i (wb_example_0_rst_i),
// These ports are not in any interface
.start (wb_example_0_start),
.done (wb_example_0_done));
endmodule |
module system_acl_iface_acl_kernel_interface_mm_interconnect_1 (
input wire clk_reset_clk_clk, // clk_reset_clk.clk
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cntrl_reset_reset_bridge_in_reset_reset, // kernel_cntrl_reset_reset_bridge_in_reset.reset
input wire sw_reset_clk_reset_reset_bridge_in_reset_reset, // sw_reset_clk_reset_reset_bridge_in_reset.reset
input wire [13:0] kernel_cntrl_m0_address, // kernel_cntrl_m0.address
output wire kernel_cntrl_m0_waitrequest, // .waitrequest
input wire [0:0] kernel_cntrl_m0_burstcount, // .burstcount
input wire [3:0] kernel_cntrl_m0_byteenable, // .byteenable
input wire kernel_cntrl_m0_read, // .read
output wire [31:0] kernel_cntrl_m0_readdata, // .readdata
output wire kernel_cntrl_m0_readdatavalid, // .readdatavalid
input wire kernel_cntrl_m0_write, // .write
input wire [31:0] kernel_cntrl_m0_writedata, // .writedata
input wire kernel_cntrl_m0_debugaccess, // .debugaccess
output wire address_span_extender_0_cntl_write, // address_span_extender_0_cntl.write
output wire address_span_extender_0_cntl_read, // .read
input wire [63:0] address_span_extender_0_cntl_readdata, // .readdata
output wire [63:0] address_span_extender_0_cntl_writedata, // .writedata
output wire [7:0] address_span_extender_0_cntl_byteenable, // .byteenable
output wire [9:0] address_span_extender_0_windowed_slave_address, // address_span_extender_0_windowed_slave.address
output wire address_span_extender_0_windowed_slave_write, // .write
output wire address_span_extender_0_windowed_slave_read, // .read
input wire [31:0] address_span_extender_0_windowed_slave_readdata, // .readdata
output wire [31:0] address_span_extender_0_windowed_slave_writedata, // .writedata
output wire [0:0] address_span_extender_0_windowed_slave_burstcount, // .burstcount
output wire [3:0] address_span_extender_0_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_0_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_0_windowed_slave_waitrequest, // .waitrequest
output wire irq_ena_0_s_write, // irq_ena_0_s.write
output wire irq_ena_0_s_read, // .read
input wire [31:0] irq_ena_0_s_readdata, // .readdata
output wire [31:0] irq_ena_0_s_writedata, // .writedata
output wire [3:0] irq_ena_0_s_byteenable, // .byteenable
input wire irq_ena_0_s_waitrequest, // .waitrequest
output wire mem_org_mode_s_write, // mem_org_mode_s.write
output wire mem_org_mode_s_read, // .read
input wire [31:0] mem_org_mode_s_readdata, // .readdata
output wire [31:0] mem_org_mode_s_writedata, // .writedata
input wire mem_org_mode_s_waitrequest, // .waitrequest
output wire sw_reset_s_write, // sw_reset_s.write
output wire sw_reset_s_read, // .read
input wire [63:0] sw_reset_s_readdata, // .readdata
output wire [63:0] sw_reset_s_writedata, // .writedata
output wire [7:0] sw_reset_s_byteenable, // .byteenable
input wire sw_reset_s_waitrequest, // .waitrequest
output wire [8:0] sys_description_rom_s1_address, // sys_description_rom_s1.address
output wire sys_description_rom_s1_write, // .write
input wire [63:0] sys_description_rom_s1_readdata, // .readdata
output wire [63:0] sys_description_rom_s1_writedata, // .writedata
output wire [7:0] sys_description_rom_s1_byteenable, // .byteenable
output wire sys_description_rom_s1_chipselect, // .chipselect
output wire sys_description_rom_s1_clken, // .clken
output wire sys_description_rom_s1_debugaccess, // .debugaccess
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest; // kernel_cntrl_m0_agent:av_waitrequest -> kernel_cntrl_m0_translator:uav_waitrequest
wire [2:0] kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount; // kernel_cntrl_m0_translator:uav_burstcount -> kernel_cntrl_m0_agent:av_burstcount
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_writedata; // kernel_cntrl_m0_translator:uav_writedata -> kernel_cntrl_m0_agent:av_writedata
wire [13:0] kernel_cntrl_m0_translator_avalon_universal_master_0_address; // kernel_cntrl_m0_translator:uav_address -> kernel_cntrl_m0_agent:av_address
wire kernel_cntrl_m0_translator_avalon_universal_master_0_lock; // kernel_cntrl_m0_translator:uav_lock -> kernel_cntrl_m0_agent:av_lock
wire kernel_cntrl_m0_translator_avalon_universal_master_0_write; // kernel_cntrl_m0_translator:uav_write -> kernel_cntrl_m0_agent:av_write
wire kernel_cntrl_m0_translator_avalon_universal_master_0_read; // kernel_cntrl_m0_translator:uav_read -> kernel_cntrl_m0_agent:av_read
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_readdata; // kernel_cntrl_m0_agent:av_readdata -> kernel_cntrl_m0_translator:uav_readdata
wire kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess; // kernel_cntrl_m0_translator:uav_debugaccess -> kernel_cntrl_m0_agent:av_debugaccess
wire [3:0] kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable; // kernel_cntrl_m0_translator:uav_byteenable -> kernel_cntrl_m0_agent:av_byteenable
wire kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid; // kernel_cntrl_m0_agent:av_readdatavalid -> kernel_cntrl_m0_translator:uav_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_waitrequest; // address_span_extender_0_windowed_slave_translator:uav_waitrequest -> address_span_extender_0_windowed_slave_agent:m0_waitrequest
wire [2:0] address_span_extender_0_windowed_slave_agent_m0_burstcount; // address_span_extender_0_windowed_slave_agent:m0_burstcount -> address_span_extender_0_windowed_slave_translator:uav_burstcount
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_writedata; // address_span_extender_0_windowed_slave_agent:m0_writedata -> address_span_extender_0_windowed_slave_translator:uav_writedata
wire [13:0] address_span_extender_0_windowed_slave_agent_m0_address; // address_span_extender_0_windowed_slave_agent:m0_address -> address_span_extender_0_windowed_slave_translator:uav_address
wire address_span_extender_0_windowed_slave_agent_m0_write; // address_span_extender_0_windowed_slave_agent:m0_write -> address_span_extender_0_windowed_slave_translator:uav_write
wire address_span_extender_0_windowed_slave_agent_m0_lock; // address_span_extender_0_windowed_slave_agent:m0_lock -> address_span_extender_0_windowed_slave_translator:uav_lock
wire address_span_extender_0_windowed_slave_agent_m0_read; // address_span_extender_0_windowed_slave_agent:m0_read -> address_span_extender_0_windowed_slave_translator:uav_read
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_readdata; // address_span_extender_0_windowed_slave_translator:uav_readdata -> address_span_extender_0_windowed_slave_agent:m0_readdata
wire address_span_extender_0_windowed_slave_agent_m0_readdatavalid; // address_span_extender_0_windowed_slave_translator:uav_readdatavalid -> address_span_extender_0_windowed_slave_agent:m0_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_debugaccess; // address_span_extender_0_windowed_slave_agent:m0_debugaccess -> address_span_extender_0_windowed_slave_translator:uav_debugaccess
wire [3:0] address_span_extender_0_windowed_slave_agent_m0_byteenable; // address_span_extender_0_windowed_slave_agent:m0_byteenable -> address_span_extender_0_windowed_slave_translator:uav_byteenable
wire address_span_extender_0_windowed_slave_agent_rf_source_endofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_endofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_windowed_slave_agent_rf_source_valid; // address_span_extender_0_windowed_slave_agent:rf_source_valid -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_valid
wire address_span_extender_0_windowed_slave_agent_rf_source_startofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_startofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rf_source_data; // address_span_extender_0_windowed_slave_agent:rf_source_data -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rf_source_ready; // address_span_extender_0_windowed_slave_agent_rsp_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rf_source_ready
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rf_sink_valid
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rf_sink_data
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rf_sink_ready -> address_span_extender_0_windowed_slave_agent_rsp_fifo:out_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_valid -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_data -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready; // address_span_extender_0_windowed_slave_agent_rdata_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rdata_fifo_src_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_ready -> address_span_extender_0_windowed_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> address_span_extender_0_windowed_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> address_span_extender_0_windowed_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> address_span_extender_0_windowed_slave_agent:cp_startofpacket
wire [88:0] cmd_mux_src_data; // cmd_mux:src_data -> address_span_extender_0_windowed_slave_agent:cp_data
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> address_span_extender_0_windowed_slave_agent:cp_channel
wire cmd_mux_src_ready; // address_span_extender_0_windowed_slave_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_0_cntl_agent_m0_waitrequest; // address_span_extender_0_cntl_translator:uav_waitrequest -> address_span_extender_0_cntl_agent:m0_waitrequest
wire [3:0] address_span_extender_0_cntl_agent_m0_burstcount; // address_span_extender_0_cntl_agent:m0_burstcount -> address_span_extender_0_cntl_translator:uav_burstcount
wire [63:0] address_span_extender_0_cntl_agent_m0_writedata; // address_span_extender_0_cntl_agent:m0_writedata -> address_span_extender_0_cntl_translator:uav_writedata
wire [13:0] address_span_extender_0_cntl_agent_m0_address; // address_span_extender_0_cntl_agent:m0_address -> address_span_extender_0_cntl_translator:uav_address
wire address_span_extender_0_cntl_agent_m0_write; // address_span_extender_0_cntl_agent:m0_write -> address_span_extender_0_cntl_translator:uav_write
wire address_span_extender_0_cntl_agent_m0_lock; // address_span_extender_0_cntl_agent:m0_lock -> address_span_extender_0_cntl_translator:uav_lock
wire address_span_extender_0_cntl_agent_m0_read; // address_span_extender_0_cntl_agent:m0_read -> address_span_extender_0_cntl_translator:uav_read
wire [63:0] address_span_extender_0_cntl_agent_m0_readdata; // address_span_extender_0_cntl_translator:uav_readdata -> address_span_extender_0_cntl_agent:m0_readdata
wire address_span_extender_0_cntl_agent_m0_readdatavalid; // address_span_extender_0_cntl_translator:uav_readdatavalid -> address_span_extender_0_cntl_agent:m0_readdatavalid
wire address_span_extender_0_cntl_agent_m0_debugaccess; // address_span_extender_0_cntl_agent:m0_debugaccess -> address_span_extender_0_cntl_translator:uav_debugaccess
wire [7:0] address_span_extender_0_cntl_agent_m0_byteenable; // address_span_extender_0_cntl_agent:m0_byteenable -> address_span_extender_0_cntl_translator:uav_byteenable
wire address_span_extender_0_cntl_agent_rf_source_endofpacket; // address_span_extender_0_cntl_agent:rf_source_endofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_cntl_agent_rf_source_valid; // address_span_extender_0_cntl_agent:rf_source_valid -> address_span_extender_0_cntl_agent_rsp_fifo:in_valid
wire address_span_extender_0_cntl_agent_rf_source_startofpacket; // address_span_extender_0_cntl_agent:rf_source_startofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rf_source_data; // address_span_extender_0_cntl_agent:rf_source_data -> address_span_extender_0_cntl_agent_rsp_fifo:in_data
wire address_span_extender_0_cntl_agent_rf_source_ready; // address_span_extender_0_cntl_agent_rsp_fifo:in_ready -> address_span_extender_0_cntl_agent:rf_source_ready
wire address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_cntl_agent:rf_sink_endofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_valid; // address_span_extender_0_cntl_agent_rsp_fifo:out_valid -> address_span_extender_0_cntl_agent:rf_sink_valid
wire address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_cntl_agent:rf_sink_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rsp_fifo_out_data; // address_span_extender_0_cntl_agent_rsp_fifo:out_data -> address_span_extender_0_cntl_agent:rf_sink_data
wire address_span_extender_0_cntl_agent_rsp_fifo_out_ready; // address_span_extender_0_cntl_agent:rf_sink_ready -> address_span_extender_0_cntl_agent_rsp_fifo:out_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_src_valid; // address_span_extender_0_cntl_agent:rdata_fifo_src_valid -> address_span_extender_0_cntl_agent_rdata_fifo:in_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_src_data; // address_span_extender_0_cntl_agent:rdata_fifo_src_data -> address_span_extender_0_cntl_agent_rdata_fifo:in_data
wire address_span_extender_0_cntl_agent_rdata_fifo_src_ready; // address_span_extender_0_cntl_agent_rdata_fifo:in_ready -> address_span_extender_0_cntl_agent:rdata_fifo_src_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_out_valid; // address_span_extender_0_cntl_agent_rdata_fifo:out_valid -> address_span_extender_0_cntl_agent:rdata_fifo_sink_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_out_data; // address_span_extender_0_cntl_agent_rdata_fifo:out_data -> address_span_extender_0_cntl_agent:rdata_fifo_sink_data
wire address_span_extender_0_cntl_agent_rdata_fifo_out_ready; // address_span_extender_0_cntl_agent:rdata_fifo_sink_ready -> address_span_extender_0_cntl_agent_rdata_fifo:out_ready
wire sys_description_rom_s1_agent_m0_waitrequest; // sys_description_rom_s1_translator:uav_waitrequest -> sys_description_rom_s1_agent:m0_waitrequest
wire [3:0] sys_description_rom_s1_agent_m0_burstcount; // sys_description_rom_s1_agent:m0_burstcount -> sys_description_rom_s1_translator:uav_burstcount
wire [63:0] sys_description_rom_s1_agent_m0_writedata; // sys_description_rom_s1_agent:m0_writedata -> sys_description_rom_s1_translator:uav_writedata
wire [13:0] sys_description_rom_s1_agent_m0_address; // sys_description_rom_s1_agent:m0_address -> sys_description_rom_s1_translator:uav_address
wire sys_description_rom_s1_agent_m0_write; // sys_description_rom_s1_agent:m0_write -> sys_description_rom_s1_translator:uav_write
wire sys_description_rom_s1_agent_m0_lock; // sys_description_rom_s1_agent:m0_lock -> sys_description_rom_s1_translator:uav_lock
wire sys_description_rom_s1_agent_m0_read; // sys_description_rom_s1_agent:m0_read -> sys_description_rom_s1_translator:uav_read
wire [63:0] sys_description_rom_s1_agent_m0_readdata; // sys_description_rom_s1_translator:uav_readdata -> sys_description_rom_s1_agent:m0_readdata
wire sys_description_rom_s1_agent_m0_readdatavalid; // sys_description_rom_s1_translator:uav_readdatavalid -> sys_description_rom_s1_agent:m0_readdatavalid
wire sys_description_rom_s1_agent_m0_debugaccess; // sys_description_rom_s1_agent:m0_debugaccess -> sys_description_rom_s1_translator:uav_debugaccess
wire [7:0] sys_description_rom_s1_agent_m0_byteenable; // sys_description_rom_s1_agent:m0_byteenable -> sys_description_rom_s1_translator:uav_byteenable
wire sys_description_rom_s1_agent_rf_source_endofpacket; // sys_description_rom_s1_agent:rf_source_endofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_endofpacket
wire sys_description_rom_s1_agent_rf_source_valid; // sys_description_rom_s1_agent:rf_source_valid -> sys_description_rom_s1_agent_rsp_fifo:in_valid
wire sys_description_rom_s1_agent_rf_source_startofpacket; // sys_description_rom_s1_agent:rf_source_startofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_startofpacket
wire [125:0] sys_description_rom_s1_agent_rf_source_data; // sys_description_rom_s1_agent:rf_source_data -> sys_description_rom_s1_agent_rsp_fifo:in_data
wire sys_description_rom_s1_agent_rf_source_ready; // sys_description_rom_s1_agent_rsp_fifo:in_ready -> sys_description_rom_s1_agent:rf_source_ready
wire sys_description_rom_s1_agent_rsp_fifo_out_endofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_endofpacket -> sys_description_rom_s1_agent:rf_sink_endofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_valid; // sys_description_rom_s1_agent_rsp_fifo:out_valid -> sys_description_rom_s1_agent:rf_sink_valid
wire sys_description_rom_s1_agent_rsp_fifo_out_startofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_startofpacket -> sys_description_rom_s1_agent:rf_sink_startofpacket
wire [125:0] sys_description_rom_s1_agent_rsp_fifo_out_data; // sys_description_rom_s1_agent_rsp_fifo:out_data -> sys_description_rom_s1_agent:rf_sink_data
wire sys_description_rom_s1_agent_rsp_fifo_out_ready; // sys_description_rom_s1_agent:rf_sink_ready -> sys_description_rom_s1_agent_rsp_fifo:out_ready
wire sys_description_rom_s1_agent_rdata_fifo_src_valid; // sys_description_rom_s1_agent:rdata_fifo_src_valid -> sys_description_rom_s1_agent:rdata_fifo_sink_valid
wire [65:0] sys_description_rom_s1_agent_rdata_fifo_src_data; // sys_description_rom_s1_agent:rdata_fifo_src_data -> sys_description_rom_s1_agent:rdata_fifo_sink_data
wire sys_description_rom_s1_agent_rdata_fifo_src_ready; // sys_description_rom_s1_agent:rdata_fifo_sink_ready -> sys_description_rom_s1_agent:rdata_fifo_src_ready
wire sw_reset_s_agent_m0_waitrequest; // sw_reset_s_translator:uav_waitrequest -> sw_reset_s_agent:m0_waitrequest
wire [3:0] sw_reset_s_agent_m0_burstcount; // sw_reset_s_agent:m0_burstcount -> sw_reset_s_translator:uav_burstcount
wire [63:0] sw_reset_s_agent_m0_writedata; // sw_reset_s_agent:m0_writedata -> sw_reset_s_translator:uav_writedata
wire [13:0] sw_reset_s_agent_m0_address; // sw_reset_s_agent:m0_address -> sw_reset_s_translator:uav_address
wire sw_reset_s_agent_m0_write; // sw_reset_s_agent:m0_write -> sw_reset_s_translator:uav_write
wire sw_reset_s_agent_m0_lock; // sw_reset_s_agent:m0_lock -> sw_reset_s_translator:uav_lock
wire sw_reset_s_agent_m0_read; // sw_reset_s_agent:m0_read -> sw_reset_s_translator:uav_read
wire [63:0] sw_reset_s_agent_m0_readdata; // sw_reset_s_translator:uav_readdata -> sw_reset_s_agent:m0_readdata
wire sw_reset_s_agent_m0_readdatavalid; // sw_reset_s_translator:uav_readdatavalid -> sw_reset_s_agent:m0_readdatavalid
wire sw_reset_s_agent_m0_debugaccess; // sw_reset_s_agent:m0_debugaccess -> sw_reset_s_translator:uav_debugaccess
wire [7:0] sw_reset_s_agent_m0_byteenable; // sw_reset_s_agent:m0_byteenable -> sw_reset_s_translator:uav_byteenable
wire sw_reset_s_agent_rf_source_endofpacket; // sw_reset_s_agent:rf_source_endofpacket -> sw_reset_s_agent_rsp_fifo:in_endofpacket
wire sw_reset_s_agent_rf_source_valid; // sw_reset_s_agent:rf_source_valid -> sw_reset_s_agent_rsp_fifo:in_valid
wire sw_reset_s_agent_rf_source_startofpacket; // sw_reset_s_agent:rf_source_startofpacket -> sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [125:0] sw_reset_s_agent_rf_source_data; // sw_reset_s_agent:rf_source_data -> sw_reset_s_agent_rsp_fifo:in_data
wire sw_reset_s_agent_rf_source_ready; // sw_reset_s_agent_rsp_fifo:in_ready -> sw_reset_s_agent:rf_source_ready
wire sw_reset_s_agent_rsp_fifo_out_endofpacket; // sw_reset_s_agent_rsp_fifo:out_endofpacket -> sw_reset_s_agent:rf_sink_endofpacket
wire sw_reset_s_agent_rsp_fifo_out_valid; // sw_reset_s_agent_rsp_fifo:out_valid -> sw_reset_s_agent:rf_sink_valid
wire sw_reset_s_agent_rsp_fifo_out_startofpacket; // sw_reset_s_agent_rsp_fifo:out_startofpacket -> sw_reset_s_agent:rf_sink_startofpacket
wire [125:0] sw_reset_s_agent_rsp_fifo_out_data; // sw_reset_s_agent_rsp_fifo:out_data -> sw_reset_s_agent:rf_sink_data
wire sw_reset_s_agent_rsp_fifo_out_ready; // sw_reset_s_agent:rf_sink_ready -> sw_reset_s_agent_rsp_fifo:out_ready
wire sw_reset_s_agent_rdata_fifo_src_valid; // sw_reset_s_agent:rdata_fifo_src_valid -> sw_reset_s_agent:rdata_fifo_sink_valid
wire [65:0] sw_reset_s_agent_rdata_fifo_src_data; // sw_reset_s_agent:rdata_fifo_src_data -> sw_reset_s_agent:rdata_fifo_sink_data
wire sw_reset_s_agent_rdata_fifo_src_ready; // sw_reset_s_agent:rdata_fifo_sink_ready -> sw_reset_s_agent:rdata_fifo_src_ready
wire mem_org_mode_s_agent_m0_waitrequest; // mem_org_mode_s_translator:uav_waitrequest -> mem_org_mode_s_agent:m0_waitrequest
wire [2:0] mem_org_mode_s_agent_m0_burstcount; // mem_org_mode_s_agent:m0_burstcount -> mem_org_mode_s_translator:uav_burstcount
wire [31:0] mem_org_mode_s_agent_m0_writedata; // mem_org_mode_s_agent:m0_writedata -> mem_org_mode_s_translator:uav_writedata
wire [13:0] mem_org_mode_s_agent_m0_address; // mem_org_mode_s_agent:m0_address -> mem_org_mode_s_translator:uav_address
wire mem_org_mode_s_agent_m0_write; // mem_org_mode_s_agent:m0_write -> mem_org_mode_s_translator:uav_write
wire mem_org_mode_s_agent_m0_lock; // mem_org_mode_s_agent:m0_lock -> mem_org_mode_s_translator:uav_lock
wire mem_org_mode_s_agent_m0_read; // mem_org_mode_s_agent:m0_read -> mem_org_mode_s_translator:uav_read
wire [31:0] mem_org_mode_s_agent_m0_readdata; // mem_org_mode_s_translator:uav_readdata -> mem_org_mode_s_agent:m0_readdata
wire mem_org_mode_s_agent_m0_readdatavalid; // mem_org_mode_s_translator:uav_readdatavalid -> mem_org_mode_s_agent:m0_readdatavalid
wire mem_org_mode_s_agent_m0_debugaccess; // mem_org_mode_s_agent:m0_debugaccess -> mem_org_mode_s_translator:uav_debugaccess
wire [3:0] mem_org_mode_s_agent_m0_byteenable; // mem_org_mode_s_agent:m0_byteenable -> mem_org_mode_s_translator:uav_byteenable
wire mem_org_mode_s_agent_rf_source_endofpacket; // mem_org_mode_s_agent:rf_source_endofpacket -> mem_org_mode_s_agent_rsp_fifo:in_endofpacket
wire mem_org_mode_s_agent_rf_source_valid; // mem_org_mode_s_agent:rf_source_valid -> mem_org_mode_s_agent_rsp_fifo:in_valid
wire mem_org_mode_s_agent_rf_source_startofpacket; // mem_org_mode_s_agent:rf_source_startofpacket -> mem_org_mode_s_agent_rsp_fifo:in_startofpacket
wire [89:0] mem_org_mode_s_agent_rf_source_data; // mem_org_mode_s_agent:rf_source_data -> mem_org_mode_s_agent_rsp_fifo:in_data
wire mem_org_mode_s_agent_rf_source_ready; // mem_org_mode_s_agent_rsp_fifo:in_ready -> mem_org_mode_s_agent:rf_source_ready
wire mem_org_mode_s_agent_rsp_fifo_out_endofpacket; // mem_org_mode_s_agent_rsp_fifo:out_endofpacket -> mem_org_mode_s_agent:rf_sink_endofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_valid; // mem_org_mode_s_agent_rsp_fifo:out_valid -> mem_org_mode_s_agent:rf_sink_valid
wire mem_org_mode_s_agent_rsp_fifo_out_startofpacket; // mem_org_mode_s_agent_rsp_fifo:out_startofpacket -> mem_org_mode_s_agent:rf_sink_startofpacket
wire [89:0] mem_org_mode_s_agent_rsp_fifo_out_data; // mem_org_mode_s_agent_rsp_fifo:out_data -> mem_org_mode_s_agent:rf_sink_data
wire mem_org_mode_s_agent_rsp_fifo_out_ready; // mem_org_mode_s_agent:rf_sink_ready -> mem_org_mode_s_agent_rsp_fifo:out_ready
wire mem_org_mode_s_agent_rdata_fifo_src_valid; // mem_org_mode_s_agent:rdata_fifo_src_valid -> mem_org_mode_s_agent:rdata_fifo_sink_valid
wire [33:0] mem_org_mode_s_agent_rdata_fifo_src_data; // mem_org_mode_s_agent:rdata_fifo_src_data -> mem_org_mode_s_agent:rdata_fifo_sink_data
wire mem_org_mode_s_agent_rdata_fifo_src_ready; // mem_org_mode_s_agent:rdata_fifo_sink_ready -> mem_org_mode_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> mem_org_mode_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> mem_org_mode_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> mem_org_mode_s_agent:cp_startofpacket
wire [88:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> mem_org_mode_s_agent:cp_data
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> mem_org_mode_s_agent:cp_channel
wire cmd_mux_004_src_ready; // mem_org_mode_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [13:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [89:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire irq_ena_0_s_agent_m0_waitrequest; // irq_ena_0_s_translator:uav_waitrequest -> irq_ena_0_s_agent:m0_waitrequest
wire [2:0] irq_ena_0_s_agent_m0_burstcount; // irq_ena_0_s_agent:m0_burstcount -> irq_ena_0_s_translator:uav_burstcount
wire [31:0] irq_ena_0_s_agent_m0_writedata; // irq_ena_0_s_agent:m0_writedata -> irq_ena_0_s_translator:uav_writedata
wire [13:0] irq_ena_0_s_agent_m0_address; // irq_ena_0_s_agent:m0_address -> irq_ena_0_s_translator:uav_address
wire irq_ena_0_s_agent_m0_write; // irq_ena_0_s_agent:m0_write -> irq_ena_0_s_translator:uav_write
wire irq_ena_0_s_agent_m0_lock; // irq_ena_0_s_agent:m0_lock -> irq_ena_0_s_translator:uav_lock
wire irq_ena_0_s_agent_m0_read; // irq_ena_0_s_agent:m0_read -> irq_ena_0_s_translator:uav_read
wire [31:0] irq_ena_0_s_agent_m0_readdata; // irq_ena_0_s_translator:uav_readdata -> irq_ena_0_s_agent:m0_readdata
wire irq_ena_0_s_agent_m0_readdatavalid; // irq_ena_0_s_translator:uav_readdatavalid -> irq_ena_0_s_agent:m0_readdatavalid
wire irq_ena_0_s_agent_m0_debugaccess; // irq_ena_0_s_agent:m0_debugaccess -> irq_ena_0_s_translator:uav_debugaccess
wire [3:0] irq_ena_0_s_agent_m0_byteenable; // irq_ena_0_s_agent:m0_byteenable -> irq_ena_0_s_translator:uav_byteenable
wire irq_ena_0_s_agent_rf_source_endofpacket; // irq_ena_0_s_agent:rf_source_endofpacket -> irq_ena_0_s_agent_rsp_fifo:in_endofpacket
wire irq_ena_0_s_agent_rf_source_valid; // irq_ena_0_s_agent:rf_source_valid -> irq_ena_0_s_agent_rsp_fifo:in_valid
wire irq_ena_0_s_agent_rf_source_startofpacket; // irq_ena_0_s_agent:rf_source_startofpacket -> irq_ena_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] irq_ena_0_s_agent_rf_source_data; // irq_ena_0_s_agent:rf_source_data -> irq_ena_0_s_agent_rsp_fifo:in_data
wire irq_ena_0_s_agent_rf_source_ready; // irq_ena_0_s_agent_rsp_fifo:in_ready -> irq_ena_0_s_agent:rf_source_ready
wire irq_ena_0_s_agent_rsp_fifo_out_endofpacket; // irq_ena_0_s_agent_rsp_fifo:out_endofpacket -> irq_ena_0_s_agent:rf_sink_endofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_valid; // irq_ena_0_s_agent_rsp_fifo:out_valid -> irq_ena_0_s_agent:rf_sink_valid
wire irq_ena_0_s_agent_rsp_fifo_out_startofpacket; // irq_ena_0_s_agent_rsp_fifo:out_startofpacket -> irq_ena_0_s_agent:rf_sink_startofpacket
wire [89:0] irq_ena_0_s_agent_rsp_fifo_out_data; // irq_ena_0_s_agent_rsp_fifo:out_data -> irq_ena_0_s_agent:rf_sink_data
wire irq_ena_0_s_agent_rsp_fifo_out_ready; // irq_ena_0_s_agent:rf_sink_ready -> irq_ena_0_s_agent_rsp_fifo:out_ready
wire irq_ena_0_s_agent_rdata_fifo_src_valid; // irq_ena_0_s_agent:rdata_fifo_src_valid -> irq_ena_0_s_agent:rdata_fifo_sink_valid
wire [33:0] irq_ena_0_s_agent_rdata_fifo_src_data; // irq_ena_0_s_agent:rdata_fifo_src_data -> irq_ena_0_s_agent:rdata_fifo_sink_data
wire irq_ena_0_s_agent_rdata_fifo_src_ready; // irq_ena_0_s_agent:rdata_fifo_sink_ready -> irq_ena_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> irq_ena_0_s_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> irq_ena_0_s_agent:cp_valid
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> irq_ena_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> irq_ena_0_s_agent:cp_data
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> irq_ena_0_s_agent:cp_channel
wire cmd_mux_006_src_ready; // irq_ena_0_s_agent:cp_ready -> cmd_mux_006:src_ready
wire kernel_cntrl_m0_agent_cp_endofpacket; // kernel_cntrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire kernel_cntrl_m0_agent_cp_valid; // kernel_cntrl_m0_agent:cp_valid -> router:sink_valid
wire kernel_cntrl_m0_agent_cp_startofpacket; // kernel_cntrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [88:0] kernel_cntrl_m0_agent_cp_data; // kernel_cntrl_m0_agent:cp_data -> router:sink_data
wire kernel_cntrl_m0_agent_cp_ready; // router:sink_ready -> kernel_cntrl_m0_agent:cp_ready
wire address_span_extender_0_windowed_slave_agent_rp_endofpacket; // address_span_extender_0_windowed_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rp_valid; // address_span_extender_0_windowed_slave_agent:rp_valid -> router_001:sink_valid
wire address_span_extender_0_windowed_slave_agent_rp_startofpacket; // address_span_extender_0_windowed_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [88:0] address_span_extender_0_windowed_slave_agent_rp_data; // address_span_extender_0_windowed_slave_agent:rp_data -> router_001:sink_data
wire address_span_extender_0_windowed_slave_agent_rp_ready; // router_001:sink_ready -> address_span_extender_0_windowed_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [88:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [6:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire address_span_extender_0_cntl_agent_rp_endofpacket; // address_span_extender_0_cntl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire address_span_extender_0_cntl_agent_rp_valid; // address_span_extender_0_cntl_agent:rp_valid -> router_002:sink_valid
wire address_span_extender_0_cntl_agent_rp_startofpacket; // address_span_extender_0_cntl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [124:0] address_span_extender_0_cntl_agent_rp_data; // address_span_extender_0_cntl_agent:rp_data -> router_002:sink_data
wire address_span_extender_0_cntl_agent_rp_ready; // router_002:sink_ready -> address_span_extender_0_cntl_agent:rp_ready
wire sys_description_rom_s1_agent_rp_endofpacket; // sys_description_rom_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sys_description_rom_s1_agent_rp_valid; // sys_description_rom_s1_agent:rp_valid -> router_003:sink_valid
wire sys_description_rom_s1_agent_rp_startofpacket; // sys_description_rom_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [124:0] sys_description_rom_s1_agent_rp_data; // sys_description_rom_s1_agent:rp_data -> router_003:sink_data
wire sys_description_rom_s1_agent_rp_ready; // router_003:sink_ready -> sys_description_rom_s1_agent:rp_ready
wire sw_reset_s_agent_rp_endofpacket; // sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sw_reset_s_agent_rp_valid; // sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire sw_reset_s_agent_rp_startofpacket; // sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [124:0] sw_reset_s_agent_rp_data; // sw_reset_s_agent:rp_data -> router_004:sink_data
wire sw_reset_s_agent_rp_ready; // router_004:sink_ready -> sw_reset_s_agent:rp_ready
wire mem_org_mode_s_agent_rp_endofpacket; // mem_org_mode_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire mem_org_mode_s_agent_rp_valid; // mem_org_mode_s_agent:rp_valid -> router_005:sink_valid
wire mem_org_mode_s_agent_rp_startofpacket; // mem_org_mode_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [88:0] mem_org_mode_s_agent_rp_data; // mem_org_mode_s_agent:rp_data -> router_005:sink_data
wire mem_org_mode_s_agent_rp_ready; // router_005:sink_ready -> mem_org_mode_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [88:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [88:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [88:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire irq_ena_0_s_agent_rp_endofpacket; // irq_ena_0_s_agent:rp_endofpacket -> router_007:sink_endofpacket
wire irq_ena_0_s_agent_rp_valid; // irq_ena_0_s_agent:rp_valid -> router_007:sink_valid
wire irq_ena_0_s_agent_rp_startofpacket; // irq_ena_0_s_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [88:0] irq_ena_0_s_agent_rp_data; // irq_ena_0_s_agent:rp_data -> router_007:sink_data
wire irq_ena_0_s_agent_rp_ready; // router_007:sink_ready -> irq_ena_0_s_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_006:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire [88:0] router_007_src_data; // router_007:src_data -> rsp_demux_006:sink_data
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_006:sink_channel
wire router_007_src_ready; // rsp_demux_006:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> kernel_cntrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> kernel_cntrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> kernel_cntrl_m0_limiter:cmd_sink_startofpacket
wire [88:0] router_src_data; // router:src_data -> kernel_cntrl_m0_limiter:cmd_sink_data
wire [6:0] router_src_channel; // router:src_channel -> kernel_cntrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // kernel_cntrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire kernel_cntrl_m0_limiter_cmd_src_endofpacket; // kernel_cntrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cntrl_m0_limiter_cmd_src_startofpacket; // kernel_cntrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_cmd_src_data; // kernel_cntrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [6:0] kernel_cntrl_m0_limiter_cmd_src_channel; // kernel_cntrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire kernel_cntrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> kernel_cntrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> kernel_cntrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> kernel_cntrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> kernel_cntrl_m0_limiter:rsp_sink_startofpacket
wire [88:0] rsp_mux_src_data; // rsp_mux:src_data -> kernel_cntrl_m0_limiter:rsp_sink_data
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> kernel_cntrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // kernel_cntrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire kernel_cntrl_m0_limiter_rsp_src_endofpacket; // kernel_cntrl_m0_limiter:rsp_src_endofpacket -> kernel_cntrl_m0_agent:rp_endofpacket
wire kernel_cntrl_m0_limiter_rsp_src_valid; // kernel_cntrl_m0_limiter:rsp_src_valid -> kernel_cntrl_m0_agent:rp_valid
wire kernel_cntrl_m0_limiter_rsp_src_startofpacket; // kernel_cntrl_m0_limiter:rsp_src_startofpacket -> kernel_cntrl_m0_agent:rp_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_rsp_src_data; // kernel_cntrl_m0_limiter:rsp_src_data -> kernel_cntrl_m0_agent:rp_data
wire [6:0] kernel_cntrl_m0_limiter_rsp_src_channel; // kernel_cntrl_m0_limiter:rsp_src_channel -> kernel_cntrl_m0_agent:rp_channel
wire kernel_cntrl_m0_limiter_rsp_src_ready; // kernel_cntrl_m0_agent:rp_ready -> kernel_cntrl_m0_limiter:rsp_src_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [88:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [88:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [88:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [88:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire [88:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [88:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [88:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [88:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [88:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire [88:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> address_span_extender_0_cntl_cmd_width_adapter:in_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> address_span_extender_0_cntl_cmd_width_adapter:in_data
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> address_span_extender_0_cntl_cmd_width_adapter:in_channel
wire cmd_mux_001_src_ready; // address_span_extender_0_cntl_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_endofpacket -> address_span_extender_0_cntl_agent:cp_endofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_valid; // address_span_extender_0_cntl_cmd_width_adapter:out_valid -> address_span_extender_0_cntl_agent:cp_valid
wire address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_startofpacket -> address_span_extender_0_cntl_agent:cp_startofpacket
wire [124:0] address_span_extender_0_cntl_cmd_width_adapter_src_data; // address_span_extender_0_cntl_cmd_width_adapter:out_data -> address_span_extender_0_cntl_agent:cp_data
wire address_span_extender_0_cntl_cmd_width_adapter_src_ready; // address_span_extender_0_cntl_agent:cp_ready -> address_span_extender_0_cntl_cmd_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_cmd_width_adapter_src_channel; // address_span_extender_0_cntl_cmd_width_adapter:out_channel -> address_span_extender_0_cntl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sys_description_rom_s1_cmd_width_adapter:in_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sys_description_rom_s1_cmd_width_adapter:in_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sys_description_rom_s1_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sys_description_rom_s1_cmd_width_adapter:in_data
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sys_description_rom_s1_cmd_width_adapter:in_channel
wire cmd_mux_002_src_ready; // sys_description_rom_s1_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire sys_description_rom_s1_cmd_width_adapter_src_endofpacket; // sys_description_rom_s1_cmd_width_adapter:out_endofpacket -> sys_description_rom_s1_agent:cp_endofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_valid; // sys_description_rom_s1_cmd_width_adapter:out_valid -> sys_description_rom_s1_agent:cp_valid
wire sys_description_rom_s1_cmd_width_adapter_src_startofpacket; // sys_description_rom_s1_cmd_width_adapter:out_startofpacket -> sys_description_rom_s1_agent:cp_startofpacket
wire [124:0] sys_description_rom_s1_cmd_width_adapter_src_data; // sys_description_rom_s1_cmd_width_adapter:out_data -> sys_description_rom_s1_agent:cp_data
wire sys_description_rom_s1_cmd_width_adapter_src_ready; // sys_description_rom_s1_agent:cp_ready -> sys_description_rom_s1_cmd_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_cmd_width_adapter_src_channel; // sys_description_rom_s1_cmd_width_adapter:out_channel -> sys_description_rom_s1_agent:cp_channel
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sw_reset_s_cmd_width_adapter:in_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sw_reset_s_cmd_width_adapter:in_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sw_reset_s_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sw_reset_s_cmd_width_adapter:in_data
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sw_reset_s_cmd_width_adapter:in_channel
wire cmd_mux_003_src_ready; // sw_reset_s_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire sw_reset_s_cmd_width_adapter_src_endofpacket; // sw_reset_s_cmd_width_adapter:out_endofpacket -> sw_reset_s_agent:cp_endofpacket
wire sw_reset_s_cmd_width_adapter_src_valid; // sw_reset_s_cmd_width_adapter:out_valid -> sw_reset_s_agent:cp_valid
wire sw_reset_s_cmd_width_adapter_src_startofpacket; // sw_reset_s_cmd_width_adapter:out_startofpacket -> sw_reset_s_agent:cp_startofpacket
wire [124:0] sw_reset_s_cmd_width_adapter_src_data; // sw_reset_s_cmd_width_adapter:out_data -> sw_reset_s_agent:cp_data
wire sw_reset_s_cmd_width_adapter_src_ready; // sw_reset_s_agent:cp_ready -> sw_reset_s_cmd_width_adapter:out_ready
wire [6:0] sw_reset_s_cmd_width_adapter_src_channel; // sw_reset_s_cmd_width_adapter:out_channel -> sw_reset_s_agent:cp_channel
wire router_002_src_endofpacket; // router_002:src_endofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_endofpacket
wire router_002_src_valid; // router_002:src_valid -> address_span_extender_0_cntl_rsp_width_adapter:in_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_startofpacket
wire [124:0] router_002_src_data; // router_002:src_data -> address_span_extender_0_cntl_rsp_width_adapter:in_data
wire [6:0] router_002_src_channel; // router_002:src_channel -> address_span_extender_0_cntl_rsp_width_adapter:in_channel
wire router_002_src_ready; // address_span_extender_0_cntl_rsp_width_adapter:in_ready -> router_002:src_ready
wire address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_valid; // address_span_extender_0_cntl_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire [88:0] address_span_extender_0_cntl_rsp_width_adapter_src_data; // address_span_extender_0_cntl_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire address_span_extender_0_cntl_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> address_span_extender_0_cntl_rsp_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_rsp_width_adapter_src_channel; // address_span_extender_0_cntl_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire router_003_src_endofpacket; // router_003:src_endofpacket -> sys_description_rom_s1_rsp_width_adapter:in_endofpacket
wire router_003_src_valid; // router_003:src_valid -> sys_description_rom_s1_rsp_width_adapter:in_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> sys_description_rom_s1_rsp_width_adapter:in_startofpacket
wire [124:0] router_003_src_data; // router_003:src_data -> sys_description_rom_s1_rsp_width_adapter:in_data
wire [6:0] router_003_src_channel; // router_003:src_channel -> sys_description_rom_s1_rsp_width_adapter:in_channel
wire router_003_src_ready; // sys_description_rom_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire sys_description_rom_s1_rsp_width_adapter_src_endofpacket; // sys_description_rom_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_valid; // sys_description_rom_s1_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire sys_description_rom_s1_rsp_width_adapter_src_startofpacket; // sys_description_rom_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire [88:0] sys_description_rom_s1_rsp_width_adapter_src_data; // sys_description_rom_s1_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire sys_description_rom_s1_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> sys_description_rom_s1_rsp_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_rsp_width_adapter_src_channel; // sys_description_rom_s1_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire router_004_src_endofpacket; // router_004:src_endofpacket -> sw_reset_s_rsp_width_adapter:in_endofpacket
wire router_004_src_valid; // router_004:src_valid -> sw_reset_s_rsp_width_adapter:in_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> sw_reset_s_rsp_width_adapter:in_startofpacket
wire [124:0] router_004_src_data; // router_004:src_data -> sw_reset_s_rsp_width_adapter:in_data
wire [6:0] router_004_src_channel; // router_004:src_channel -> sw_reset_s_rsp_width_adapter:in_channel
wire router_004_src_ready; // sw_reset_s_rsp_width_adapter:in_ready -> router_004:src_ready
wire sw_reset_s_rsp_width_adapter_src_endofpacket; // sw_reset_s_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire sw_reset_s_rsp_width_adapter_src_valid; // sw_reset_s_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire sw_reset_s_rsp_width_adapter_src_startofpacket; // sw_reset_s_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire [88:0] sw_reset_s_rsp_width_adapter_src_data; // sw_reset_s_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire sw_reset_s_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sw_reset_s_rsp_width_adapter:out_ready
wire [6:0] sw_reset_s_rsp_width_adapter_src_channel; // sw_reset_s_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire [88:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire [88:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire [6:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser_001:in_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [88:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser_001:in_data
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser_001:in_channel
wire cmd_demux_src1_ready; // crosser_001:in_ready -> cmd_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [88:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink0_data
wire [6:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_mux_001:sink0_ready -> crosser_001:out_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire [88:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire [88:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire [6:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire [88:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire [88:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire [6:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [6:0] kernel_cntrl_m0_limiter_cmd_valid_data; // kernel_cntrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) kernel_cntrl_m0_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (kernel_cntrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.av_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.av_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.av_read (kernel_cntrl_m0_read), // .read
.av_readdata (kernel_cntrl_m0_readdata), // .readdata
.av_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.av_write (kernel_cntrl_m0_write), // .write
.av_writedata (kernel_cntrl_m0_writedata), // .writedata
.av_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_windowed_slave_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_windowed_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.uav_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_0_windowed_slave_write), // .write
.av_read (address_span_extender_0_windowed_slave_read), // .read
.av_readdata (address_span_extender_0_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_0_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_0_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_cntl_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_cntl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_cntl_agent_m0_read), // .read
.uav_write (address_span_extender_0_cntl_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.av_write (address_span_extender_0_cntl_write), // avalon_anti_slave_0.write
.av_read (address_span_extender_0_cntl_read), // .read
.av_readdata (address_span_extender_0_cntl_readdata), // .readdata
.av_writedata (address_span_extender_0_cntl_writedata), // .writedata
.av_byteenable (address_span_extender_0_cntl_byteenable), // .byteenable
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_description_rom_s1_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_description_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_description_rom_s1_agent_m0_read), // .read
.uav_write (sys_description_rom_s1_agent_m0_write), // .write
.uav_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sys_description_rom_s1_address), // avalon_anti_slave_0.address
.av_write (sys_description_rom_s1_write), // .write
.av_readdata (sys_description_rom_s1_readdata), // .readdata
.av_writedata (sys_description_rom_s1_writedata), // .writedata
.av_byteenable (sys_description_rom_s1_byteenable), // .byteenable
.av_chipselect (sys_description_rom_s1_chipselect), // .chipselect
.av_clken (sys_description_rom_s1_clken), // .clken
.av_debugaccess (sys_description_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_reset_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (sw_reset_s_agent_m0_read), // .read
.uav_write (sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (sw_reset_s_read), // .read
.av_readdata (sw_reset_s_readdata), // .readdata
.av_writedata (sw_reset_s_writedata), // .writedata
.av_byteenable (sw_reset_s_byteenable), // .byteenable
.av_waitrequest (sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_org_mode_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_org_mode_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.uav_read (mem_org_mode_s_agent_m0_read), // .read
.uav_write (mem_org_mode_s_agent_m0_write), // .write
.uav_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.uav_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.uav_lock (mem_org_mode_s_agent_m0_lock), // .lock
.uav_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.av_write (mem_org_mode_s_write), // avalon_anti_slave_0.write
.av_read (mem_org_mode_s_read), // .read
.av_readdata (mem_org_mode_s_readdata), // .readdata
.av_writedata (mem_org_mode_s_writedata), // .writedata
.av_waitrequest (mem_org_mode_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) irq_ena_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (irq_ena_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.uav_read (irq_ena_0_s_agent_m0_read), // .read
.uav_write (irq_ena_0_s_agent_m0_write), // .write
.uav_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.uav_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.uav_lock (irq_ena_0_s_agent_m0_lock), // .lock
.uav_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.av_write (irq_ena_0_s_write), // avalon_anti_slave_0.write
.av_read (irq_ena_0_s_read), // .read
.av_readdata (irq_ena_0_s_readdata), // .readdata
.av_writedata (irq_ena_0_s_writedata), // .writedata
.av_byteenable (irq_ena_0_s_byteenable), // .byteenable
.av_waitrequest (irq_ena_0_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BEGIN_BURST (68),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_THREAD_ID_H (76),
.PKT_THREAD_ID_L (76),
.PKT_CACHE_H (83),
.PKT_CACHE_L (80),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cntrl_m0_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (kernel_cntrl_m0_agent_cp_valid), // cp.valid
.cp_data (kernel_cntrl_m0_agent_cp_data), // .data
.cp_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (kernel_cntrl_m0_agent_cp_ready), // .ready
.rp_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rp_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_windowed_slave_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_windowed_slave_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_cntl_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_cntl_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_cntl_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_cntl_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_cntl_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_cntl_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.cp_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.cp_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.cp_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_cntl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_cntl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sys_description_rom_s1_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_description_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.m0_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_description_rom_s1_agent_m0_read), // .read
.m0_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.m0_write (sys_description_rom_s1_agent_m0_write), // .write
.rp_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_description_rom_s1_agent_rp_ready), // .ready
.rp_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.rp_data (sys_description_rom_s1_agent_rp_data), // .data
.rp_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.cp_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_description_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_description_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_description_rom_s1_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_description_rom_s1_agent_rf_source_data), // in.data
.in_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.in_ready (sys_description_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_reset_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_reset_s_agent_rp_ready), // .ready
.rp_valid (sw_reset_s_agent_rp_valid), // .valid
.rp_data (sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (sw_reset_s_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.cp_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_reset_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_reset_s_agent_rf_source_data), // in.data
.in_valid (sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem_org_mode_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_org_mode_s_agent_m0_address), // m0.address
.m0_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_org_mode_s_agent_m0_lock), // .lock
.m0_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_org_mode_s_agent_m0_read), // .read
.m0_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.m0_write (mem_org_mode_s_agent_m0_write), // .write
.rp_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_org_mode_s_agent_rp_ready), // .ready
.rp_valid (mem_org_mode_s_agent_rp_valid), // .valid
.rp_data (mem_org_mode_s_agent_rp_data), // .data
.rp_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_org_mode_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_org_mode_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_org_mode_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_org_mode_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_org_mode_s_agent_rf_source_data), // in.data
.in_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.in_ready (mem_org_mode_s_agent_rf_source_ready), // .ready
.in_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_org_mode_s_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) irq_ena_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (irq_ena_0_s_agent_m0_address), // m0.address
.m0_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (irq_ena_0_s_agent_m0_lock), // .lock
.m0_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (irq_ena_0_s_agent_m0_read), // .read
.m0_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.m0_write (irq_ena_0_s_agent_m0_write), // .write
.rp_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (irq_ena_0_s_agent_rp_ready), // .ready
.rp_valid (irq_ena_0_s_agent_rp_valid), // .valid
.rp_data (irq_ena_0_s_agent_rp_data), // .data
.rp_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (irq_ena_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (irq_ena_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (irq_ena_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) irq_ena_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (irq_ena_0_s_agent_rf_source_data), // in.data
.in_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.in_ready (irq_ena_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (irq_ena_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router router (
.sink_ready (kernel_cntrl_m0_agent_cp_ready), // sink.ready
.sink_valid (kernel_cntrl_m0_agent_cp_valid), // .valid
.sink_data (kernel_cntrl_m0_agent_cp_data), // .data
.sink_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_001 (
.sink_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_002 (
.sink_ready (address_span_extender_0_cntl_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_cntl_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_003 (
.sink_ready (sys_description_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.sink_data (sys_description_rom_s1_agent_rp_data), // .data
.sink_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_004 (
.sink_ready (sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (sw_reset_s_agent_rp_valid), // .valid
.sink_data (sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_005 (
.sink_ready (mem_org_mode_s_agent_rp_ready), // sink.ready
.sink_valid (mem_org_mode_s_agent_rp_valid), // .valid
.sink_data (mem_org_mode_s_agent_rp_data), // .data
.sink_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_007 (
.sink_ready (irq_ena_0_s_agent_rp_ready), // sink.ready
.sink_valid (irq_ena_0_s_agent_rp_valid), // .valid
.sink_data (irq_ena_0_s_agent_rp_data), // .data
.sink_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) kernel_cntrl_m0_limiter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (kernel_cntrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (kernel_cntrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.sink_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sw_reset_s_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.sink_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.out_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.out_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule |
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module gng_top_tb;
reg clk, rst, test_clk;
wire [15:0] data_out;
integer lzd_file, urn_file, mult_in_file, mult1_file, sum1_file, mult2_file, sum2_file, output_file, scan_line;
reg [5:0] ref_lzd;
reg [63:0] ref_urn;
reg [14:0] ref_mult_in;
reg [34:0] ref_mult1;
reg [38:0] ref_sum1;
reg [35:0] ref_mult2;
reg [40:0] ref_sum2;
reg [15:0] ref_output;
reg [15:0] test_en_reg;
reg test_fail;
initial
begin
lzd_file = $fopen("lzd_ref_results.txt","r");
urn_file = $fopen("urn_ref_results.txt","r");
mult_in_file = $fopen("mult_input_ref_results.txt","r");
mult1_file = $fopen("mult1_output_ref_results.txt","r");
sum1_file = $fopen("sum1_output_ref_results.txt","r");
mult2_file = $fopen("mult2_output_ref_results.txt","r");
sum2_file = $fopen("sum2_output_ref_results.txt","r");
output_file = $fopen("output_ref_results.txt","r");
rst = 1'b1;
clk = 1'b0;
test_clk = 1'b0;
test_en_reg = 13'd0;
test_fail = 1'b0;
#20 rst = 1'b0;
end
always
#10 clk <= ~clk;
always begin
#1 test_clk <= ~test_clk;
#9 ;
end
gng_top i_gng_top (.clk(clk), .rst(rst), .awgn_out(data_out));
always @ (posedge test_clk) begin
test_en_reg <= {test_en_reg[14:0],1'b1};
end
always @(posedge test_clk) begin
if (test_en_reg[3]) begin
// Check Tausworthe generator output
scan_line = $fscanf(urn_file, "%b\n", ref_urn);
if (!$feof(urn_file)) begin
if (ref_urn !== i_gng_top.urn_data) begin
test_fail <= 1'b1;
$warning("***Mismatch in Uniform Random Number Generator data***");
end
end
end
if (test_en_reg[5]) begin
// Test Leading Zero Detector
scan_line = $fscanf(lzd_file, "%x\n", ref_lzd);
if (!$feof(lzd_file)) begin
if (ref_lzd !== (i_gng_top.i_gng_interpolator.lz_pos + 6'd1)) begin
// Add one to account for 0 vs 1 indexing
test_fail <= 1'b1;
$warning("***Mismatch in LZD data***");
end
end
// Test Mask To Zero
scan_line = $fscanf(mult_in_file, "%x\n", ref_mult_in);
if (!$feof(mult_in_file)) begin
if (ref_mult_in !== i_gng_top.i_gng_interpolator.mult_in) begin
test_fail <= 1'b1;
$warning("***Mismatch in Mask To Zero output data***");
end
end
end
if (test_en_reg[9]) begin
// Test first multiply
scan_line = $fscanf(mult1_file, "%x\n", ref_mult1);
if (!$feof(mult1_file)) begin
if (ref_mult1 !== i_gng_top.i_gng_interpolator.i_mult_add1.prod) begin
test_fail <= 1'b1;
$warning("***Mismatch in first multiply***");
end
end
end
if (test_en_reg[10]) begin
// Test first add
scan_line = $fscanf(sum1_file, "%x\n", ref_sum1);
if (!$feof(sum1_file)) begin
if (ref_sum1 !== i_gng_top.i_gng_interpolator.i_mult_add1.result) begin
test_fail <= 1'b1;
$warning("***Mismatch in first add***");
end
end
end
if (test_en_reg[12]) begin
// Test second multiply
scan_line = $fscanf(mult2_file, "%x\n", ref_mult2);
if (!$feof(mult2_file)) begin
if (ref_mult2 !== i_gng_top.i_gng_interpolator.i_mult_add2.prod) begin
test_fail <= 1'b1;
$warning("***Mismatch in second multiply***");
end
end
end
if (test_en_reg[13]) begin
// Test second add
scan_line = $fscanf(sum2_file, "%x\n", ref_sum2);
if (!$feof(sum2_file)) begin
if (ref_sum2 !== i_gng_top.i_gng_interpolator.i_mult_add2.result) begin
test_fail <= 1'b1;
$warning("***Mismatch in second add***");
end
end
end
if (test_en_reg[14]) begin
// Test second add
scan_line = $fscanf(output_file, "%d\n", ref_output);
if (!$feof(output_file)) begin
if (ref_output !== data_out) begin
test_fail <= 1'b1;
$warning("***Mismatch in output data***");
end
end
else begin
if (test_fail) begin
$display("TEST FAILED : Errors occured during simulation - check transcript");
$finish;
end
else begin
$display("Test Passed! All test-points are bit-accurate to the reference.");
$finish;
end
end
end
end
endmodule |
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule |
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim_default_after(25); // in prsim time units
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("timing after");
// $prsim_cmd("watchall");
// $prsim_cmd("fanin out1");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #30 $finish;
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule |
module sky130_fd_sc_lp__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module clkctrl2_tb ;
reg reset_b_r;
reg lsclk_r;
reg hsclk_r;
reg hienable_r;
wire clkout;
wire hsclk_selected_w;
initial
begin
$dumpvars();
reset_b_r = 0;
lsclk_r = 0;
hsclk_r = 0;
hienable_r = 0;
#500 reset_b_r = 1;
#2000;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2000 $finish();
end
always
#`LSCLK_HALF_CYCLE lsclk_r = !lsclk_r ;
always
#`HSCLK_HALF_CYCLE hsclk_r = !hsclk_r ;
`ifdef SYNC_SWITCH_D
clkctrl2 clkctrl2_u(
.hsclk_in(hsclk_r),
.lsclk_in(lsclk_r),
.rst_b(reset_b_r),
.hsclk_sel(hienable_r),
.hsclk_div_sel(`HSCLK_DIV),
.cpuclk_div_sel(`CPUCLK_DIV),
.hsclk_selected(hsclk_selected_w),
.clkout(clkout)
);
`else
clkctrl clkctrl_u(
.hsclk_in(hsclk_r),
.lsclk_in(lsclk_r),
.rst_b(reset_b_r),
.hsclk_sel(hienable_r),
.cpuclk_div_sel(`CPUCLK_DIV),
.hsclk_selected(hsclk_selected_w),
.clkout(clkout)
);
`endif
endmodule |
module sky130_fd_sc_ms__o41a_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__o41a_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule |
module sky130_fd_sc_hs__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sky130_fd_sc_hs__o21ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module sky130_fd_sc_ls__a221oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__a221oi_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule |
module ecfg (/*AUTOARG*/
// Outputs
mi_data_out, mi_data_sel, ecfg_sw_reset, ecfg_reset,
ecfg_tx_enable, ecfg_tx_mmu_mode, ecfg_tx_gpio_mode,
ecfg_tx_ctrl_mode, ecfg_tx_clkdiv, ecfg_rx_enable,
ecfg_rx_mmu_mode, ecfg_rx_gpio_mode, ecfg_rx_loopback_mode,
ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg, ecfg_coreid,
ecfg_gpio_dataout,
// Inputs
param_coreid, clk, hw_reset, mi_access, mi_write, mi_addr,
mi_data_in
);
//Register file parameters
/*
#####################################################################
COMPILE TIME PARAMETERS
######################################################################
*/
parameter EMAW = 12; //mmu table address width
parameter EDW = 32; //Epiphany native data width
parameter EAW = 32; //Epiphany native address width
parameter IDW = 12; //Elink ID (row,column coordinate)
parameter RFAW = 5; //Number of registers=2^RFAW
/*****************************/
/*STATIC CONFIG SIGNALS */
/*****************************/
input [IDW-1:0] param_coreid;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input clk;
input hw_reset;
input mi_access;
input mi_write;
input [19:0] mi_addr;
input [31:0] mi_data_in;
output [31:0] mi_data_out;
output mi_data_sel;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//RESET
output ecfg_sw_reset;
output ecfg_reset;
//tx
output ecfg_tx_enable; //enable signal for TX
output ecfg_tx_mmu_mode; //enables MMU on transnmit path
output ecfg_tx_gpio_mode; //forces TX output pins to constants
output [3:0] ecfg_tx_ctrl_mode; //value for emesh ctrlmode tag
output [3:0] ecfg_tx_clkdiv; //transmit clock divider
//rx
output ecfg_rx_enable; //enable signal for rx
output ecfg_rx_mmu_mode; //enables MMU on rx path
output ecfg_rx_gpio_mode; //forces rx wait pins to constants
output ecfg_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
//cclk
output ecfg_cclk_en; //cclk enable
output [3:0] ecfg_cclk_div; //cclk divider setting
output [3:0] ecfg_cclk_pllcfg; //pll configuration
//coreid
output [11:0] ecfg_coreid; //core-id of fpga elink
//gpio
output [11:0] ecfg_gpio_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0}
//registers
reg [11:0] ecfg_cfgtx_reg;
reg [4:0] ecfg_cfgrx_reg;
reg [7:0] ecfg_cfgclk_reg;
reg [11:0] ecfg_coreid_reg;
wire [31:0] ecfg_version_reg;
reg ecfg_reset_reg;
reg [11:0] ecfg_gpio_datain_reg;
reg [11:0] ecfg_gpio_dataout_reg;
reg [31:0] mi_data_out;
reg mi_data_sel;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_reset_match;
wire ecfg_cfgtx_match;
wire ecfg_cfgrx_match;
wire ecfg_cfgclk_match;
wire ecfg_coreid_match;
wire ecfg_version_match;
wire ecfg_datain_match;
wire ecfg_dataout_match;
wire ecfg_match;
wire ecfg_regmux;
wire [31:0] ecfg_reg_mux;
wire ecfg_cfgtx_write;
wire ecfg_cfgrx_write;
wire ecfg_cfgclk_write;
wire ecfg_coreid_write;
wire ecfg_version_write;
wire ecfg_datain_write;
wire ecfg_dataout_write;
wire ecfg_rx_monitor_mode;
wire ecfg_reset_write;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_access & mi_write;
assign ecfg_read = mi_access & ~mi_write;
//address match signals
assign ecfg_reset_match = mi_addr[19:0]==`E_REG_SYSRESET;
assign ecfg_cfgtx_match = mi_addr[19:0]==`E_REG_SYSCFGTX;
assign ecfg_cfgrx_match = mi_addr[19:0]==`E_REG_SYSCFGRX;
assign ecfg_cfgclk_match = mi_addr[19:0]==`E_REG_SYSCFGCLK;
assign ecfg_coreid_match = mi_addr[19:0]==`E_REG_SYSCOREID;
assign ecfg_version_match = mi_addr[19:0]==`E_REG_SYSVERSION;
assign ecfg_datain_match = mi_addr[19:0]==`E_REG_SYSDATAIN;
assign ecfg_dataout_match = mi_addr[19:0]==`E_REG_SYSDATAOUT;
assign ecfg_match = ecfg_reset_match |
ecfg_cfgtx_match |
ecfg_cfgrx_match |
ecfg_cfgclk_match |
ecfg_coreid_match |
ecfg_version_match |
ecfg_datain_match |
ecfg_dataout_match;
//Write enables
assign ecfg_reset_write = ecfg_reset_match & ecfg_write;
assign ecfg_cfgtx_write = ecfg_cfgtx_match & ecfg_write;
assign ecfg_cfgrx_write = ecfg_cfgrx_match & ecfg_write;
assign ecfg_cfgclk_write = ecfg_cfgclk_match & ecfg_write;
assign ecfg_coreid_write = ecfg_coreid_match & ecfg_write;
assign ecfg_version_write = ecfg_version_match & ecfg_write;
assign ecfg_datain_write = ecfg_datain_match & ecfg_write;
assign ecfg_dataout_write = ecfg_dataout_match & ecfg_write;
//###########################
//# ESYSCFGTX
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_cfgtx_reg[11:0] <= 12'b0;
else if (ecfg_cfgtx_write)
ecfg_cfgtx_reg[11:0] <= mi_data_in[11:0];
assign ecfg_tx_enable = ecfg_cfgtx_reg[0];
assign ecfg_tx_mmu_mode = ecfg_cfgtx_reg[1];
assign ecfg_tx_gpio_mode = ecfg_cfgtx_reg[3:2]==2'b01;
assign ecfg_tx_ctrl_mode[3:0] = ecfg_cfgtx_reg[7:4];
assign ecfg_tx_clkdiv[3:0] = ecfg_cfgtx_reg[11:8];
//###########################
//# ESYSCFGRX
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_cfgrx_reg[4:0] <= 5'b0;
else if (ecfg_cfgrx_write)
ecfg_cfgrx_reg[4:0] <= mi_data_in[4:0];
assign ecfg_rx_enable = ecfg_cfgrx_reg[0];
assign ecfg_rx_mmu_mode = ecfg_cfgrx_reg[1];
assign ecfg_rx_gpio_mode = ecfg_cfgrx_reg[3:2]==2'b01;
assign ecfg_rx_loopback_mode = ecfg_cfgrx_reg[3:2]==2'b10;
assign ecfg_rx_monitor_mode = ecfg_cfgrx_reg[4];
//###########################
//# ESYSCFGCLK
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_cfgclk_reg[7:0] <= 8'b0;
else if (ecfg_cfgclk_write)
ecfg_cfgclk_reg[7:0] <= mi_data_in[7:0];
assign ecfg_cclk_en = ~(ecfg_cfgclk_reg[3:0]==4'b0000);
assign ecfg_cclk_div[3:0] = ecfg_cfgclk_reg[3:0];
assign ecfg_cclk_pllcfg[3:0] = ecfg_cfgclk_reg[7:4];
//###########################
//# ESYSCOREID
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_coreid_reg[IDW-1:0] <= param_coreid[IDW-1:0];
else if (ecfg_coreid_write)
ecfg_coreid_reg[IDW-1:0] <= mi_data_in[IDW-1:0];
assign ecfg_coreid[IDW-1:0] = ecfg_coreid_reg[IDW-1:0];
//###########################
//# ESYSVERSION
//###########################
assign ecfg_version_reg[31:0] = `E_VERSION;
//###########################
//# ESYSDATAIN
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_gpio_datain_reg[11:0] <= 12'b0;
else if (ecfg_datain_write)
ecfg_gpio_datain_reg[11:0] <= mi_data_in[11:0];
//###########################
//# ESYSDATAOUT
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_gpio_dataout_reg[11:0] <= 12'b0;
else if (ecfg_dataout_write)
ecfg_gpio_dataout_reg[11:0] <= mi_data_in[11:0];
assign ecfg_gpio_dataout[11:0] = ecfg_gpio_dataout_reg[11:0];
//###########################
//# ESYSRESET
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_reset_reg <= 1'b0;
else if (ecfg_reset_write)
ecfg_reset_reg <= mi_data_in[0];
assign ecfg_sw_reset = ecfg_reset_reg;
assign ecfg_reset = ecfg_sw_reset | hw_reset;
//###############################
//# DATA READBACK MUX
//###############################
assign ecfg_reg_mux[31:0] = ({(32){ecfg_reset_match}} & {20'b0,ecfg_cfgtx_reg[11:0]}) |
({(32){ecfg_cfgtx_match}} & {20'b0,ecfg_cfgtx_reg[11:0]}) |
({(32){ecfg_cfgrx_match}} & {27'b0,ecfg_cfgrx_reg[4:0]}) |
({(32){ecfg_cfgclk_match}} & {24'b0,ecfg_cfgclk_reg[7:0]}) |
({(32){ecfg_coreid_match}} & {20'b0,ecfg_coreid_reg[11:0]}) |
({(32){ecfg_version_match}} & ecfg_version_reg[31:0]) |
({(32){ecfg_datain_match}} & {20'b0,ecfg_gpio_datain_reg[11:0]}) |
({(32){ecfg_dataout_match}} & {20'b0,ecfg_gpio_dataout_reg[11:0]}) ;
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
begin
mi_data_out[31:0] <= ecfg_reg_mux[31:0];
mi_data_sel <= ecfg_match;
end
endmodule |
module sky130_fd_sc_hs__tap_1 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__tap base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__tap base ();
endmodule |
module artemis_pcie_controller #(
parameter SERIAL_NUMBER = 64'h000000000000C594,
parameter DATA_INGRESS_FIFO_DEPTH = 10, //4096
parameter DATA_EGRESS_FIFO_DEPTH = 6 //256
)(
input clk,
input rst,
//The Following Signals are clocked at 62.5MHz
// PCI Express Fabric Interface
input gtp_clk_p,
input gtp_clk_n,
output pci_exp_txp,
output pci_exp_txn,
input pci_exp_rxp,
input pci_exp_rxn,
input i_pcie_reset,
// Transaction (TRN) Interface
output user_lnk_up,
(* KEEP = "TRUE" *) output clk_62p5,
// Conifguration: Interrupt
output [31:0] o_bar_addr0,
output [31:0] o_bar_addr1,
output [31:0] o_bar_addr2,
output [31:0] o_bar_addr3,
output [31:0] o_bar_addr4,
output [31:0] o_bar_addr5,
// Configuration: Power Management
input cfg_turnoff_ok,
output cfg_to_turnoff,
input cfg_pm_wake,
// System Interface
output o_pcie_reset,
output received_hot_reset,
output gtp_reset_done,
output gtp_pll_lock_detect,
output pll_lock_detect,
//GTP PHY Configurations
output rx_elec_idle,
input [1:0] rx_equalizer_ctrl,
input [3:0] tx_diff_ctrl,
input [2:0] tx_pre_emphasis,
output [4:0] cfg_ltssm_state,
output [5:0] tx_buf_av,
output tx_err_drop,
//Extra Info
output [6:0] o_bar_hit,
output o_receive_axi_ready,
output [2:0] cfg_pcie_link_state,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
// Configuration: Error
input cfg_err_ur,
input cfg_err_cor,
input cfg_err_ecrc,
input cfg_err_cpl_timeout,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_locked,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
//Debug
output [7:0] o_cfg_read_exec,
output [3:0] o_cfg_sm_state,
output [3:0] o_sm_state,
output [7:0] o_ingress_count,
output [3:0] o_ingress_state,
output [7:0] o_ingress_ri_count,
output [7:0] o_ingress_ci_count,
output [31:0] o_ingress_cmplt_count,
output [31:0] o_ingress_addr,
output dbg_reg_detected_correctable,
output dbg_reg_detected_fatal,
output dbg_reg_detected_non_fatal,
output dbg_reg_detected_unsupported,
output dbg_bad_dllp_status,
output dbg_bad_tlp_lcrc,
output dbg_bad_tlp_seq_num,
output dbg_bad_tlp_status,
output dbg_dl_protocol_status,
output dbg_fc_protocol_err_status,
output dbg_mlfrmd_length,
output dbg_mlfrmd_mps,
output dbg_mlfrmd_tcvc,
output dbg_mlfrmd_tlp_status,
output dbg_mlfrmd_unrec_type,
output dbg_poistlpstatus,
output dbg_rcvr_overflow_status,
output dbg_rply_rollover_status,
output dbg_rply_timeout_status,
output dbg_ur_no_bar_hit,
output dbg_ur_pois_cfg_wr,
output dbg_ur_status,
output dbg_ur_unsup_msg,
output [15:0] dbg_tag_ingress_fin,
output [15:0] dbg_tag_en,
output dbg_rerrfwd,
output dbg_ready_drop,
output o_dbg_reenable_stb,
output o_dbg_reenable_nzero_stb, //If the host responded a bit then this will be greater than zero
output o_sys_rst,
//User Interfaces
output o_per_fifo_sel,
output o_mem_fifo_sel,
output o_dma_fifo_sel,
input i_write_fin,
input i_read_fin,
output [31:0] o_data_size,
output [31:0] o_data_address,
output o_data_fifo_flg,
output o_data_read_flg,
output o_data_write_flg,
input i_usr_interrupt_stb,
input [31:0] i_usr_interrupt_value,
output [2:0] o_cplt_sts,
output o_unknown_tlp_stb,
output o_unexpected_end_stb,
//Ingress FIFO
input i_data_clk,
output o_ingress_fifo_rdy,
input i_ingress_fifo_act,
output [23:0] o_ingress_fifo_size,
input i_ingress_fifo_stb,
output [31:0] o_ingress_fifo_data,
output o_ingress_fifo_idle,
//Egress FIFO
output [1:0] o_egress_fifo_rdy,
input [1:0] i_egress_fifo_act,
output [23:0] o_egress_fifo_size,
input i_egress_fifo_stb,
input [31:0] i_egress_fifo_data
);
// local parameters
// registes/wires
// Control Signals
wire [1:0] c_in_wr_ready;
wire [1:0] c_in_wr_activate;
wire [23:0] c_in_wr_size;
wire c_in_wr_stb;
wire [31:0] c_in_wr_data;
wire c_out_rd_stb;
wire c_out_rd_ready;
wire c_out_rd_activate;
wire [23:0] c_out_rd_size;
wire [31:0] c_out_rd_data;
//Data
wire [1:0] d_in_wr_ready;
wire [1:0] d_in_wr_activate;
wire [23:0] d_in_wr_size;
wire d_in_wr_stb;
wire [31:0] d_in_wr_data;
wire d_out_rd_stb;
wire d_out_rd_ready;
wire d_out_rd_activate;
wire [23:0] d_out_rd_size;
wire [31:0] d_out_rd_data;
wire [31:0] m_axis_rx_tdata;
wire [3:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire s_axis_tx_tready;
wire [31:0] s_axis_tx_tdata;
wire [3:0] s_axis_tx_tkeep;
wire [3:0] s_axis_tx_tuser;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire cfg_trn_pending;
wire cfg_interrupt_stb;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_do;
wire [7:0] cfg_interrupt_di;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire [7:0] w_interrupt_msi_value;
wire w_interrupt_stb;
//XXX: Configuration Registers this should be read in by the controller
wire [31:0] w_write_a_addr;
wire [31:0] w_write_b_addr;
wire [31:0] w_read_a_addr;
wire [31:0] w_read_b_addr;
wire [31:0] w_status_addr;
wire [31:0] w_buffer_size;
wire [31:0] w_ping_value;
wire [31:0] w_dev_addr;
wire [1:0] w_update_buf;
wire w_update_buf_stb;
//XXX: Control SM Signals
wire [31:0] w_control_addr_base;
wire [31:0] w_cmd_data_count;
wire [31:0] w_cmd_data_address;
assign w_control_addr_base = o_bar_addr0;
//XXX: These signals are controlled by the buffer controller
//BUFFER Interface
wire w_buf_we;
wire [31:0] w_buf_addr;
wire [31:0] w_buf_dat;
wire s_axis_tx_discont;
wire s_axis_tx_stream;
wire s_axis_tx_err_fwd;
wire s_axis_tx_s6_not_used;
wire [31:0] cfg_do;
wire cfg_rd_wr_done;
wire [9:0] cfg_dwaddr;
wire cfg_rd_en;
wire cfg_enable;
wire tx_cfg_gnt;
wire rx_np_ok;
wire [6:0] w_bar_hit;
wire w_enable_config_read;
wire w_finished_config_read;
wire w_reg_write_stb;
//Command Strobe Signals
wire w_cmd_rst_stb;
wire w_cmd_wr_stb;
wire w_cmd_rd_stb;
wire w_cmd_ping_stb;
wire w_cmd_rd_cfg_stb;
wire w_cmd_unknown_stb;
//Command Flag Signals
wire w_cmd_flg_fifo_stb;
wire w_cmd_flg_sel_per_stb;
wire w_cmd_flg_sel_mem_stb;
wire w_cmd_flg_sel_dma_stb;
//Egress FIFO Signals
wire w_egress_enable;
wire w_egress_finished;
wire [7:0] w_egress_tlp_command;
wire [13:0] w_egress_tlp_flags;
wire [31:0] w_egress_tlp_address;
wire [15:0] w_egress_tlp_requester_id;
wire [7:0] w_egress_tag;
/****************************************************************************
* Egress FIFO Signals
****************************************************************************/
wire w_ctr_fifo_sel;
wire w_egress_fifo_rdy;
wire w_egress_fifo_act;
wire [23:0] w_egress_fifo_size;
wire [31:0] w_egress_fifo_data;
wire w_egress_fifo_stb;
wire w_e_ctr_fifo_rdy;
wire w_e_ctr_fifo_act;
wire [23:0] w_e_ctr_fifo_size;
wire [31:0] w_e_ctr_fifo_data;
wire w_e_ctr_fifo_stb;
wire w_e_per_fifo_rdy;
wire w_e_per_fifo_act;
wire [23:0] w_e_per_fifo_size;
wire [31:0] w_e_per_fifo_data;
wire w_e_per_fifo_stb;
wire w_e_mem_fifo_rdy;
wire w_e_mem_fifo_act;
wire [23:0] w_e_mem_fifo_size;
wire [31:0] w_e_mem_fifo_data;
wire w_e_mem_fifo_stb;
wire w_e_dma_fifo_rdy;
wire w_e_dma_fifo_act;
wire [23:0] w_e_dma_fifo_size;
wire [31:0] w_e_dma_fifo_data;
wire w_e_dma_fifo_stb;
wire [12:0] w_ibm_buf_offset;
wire w_bb_buf_we;
wire [10:0] w_bb_buf_addr;
wire [31:0] w_bb_buf_data;
wire [23:0] w_bb_data_count;
wire [1:0] w_i_data_fifo_rdy;
wire [1:0] w_o_data_fifo_act;
wire [23:0] w_o_data_fifo_size;
wire w_i_data_fifo_stb;
wire [31:0] w_i_data_fifo_data;
wire w_e_data_fifo_rdy;
wire w_e_data_fifo_act;
wire [23:0] w_e_data_fifo_size;
wire w_e_data_fifo_stb;
wire [31:0] w_e_data_fifo_data;
wire w_egress_inactive;
wire w_dat_fifo_sel;
wire [23:0] w_buf_max_size;
assign w_buf_max_size = 2**DATA_INGRESS_FIFO_DEPTH;
//Credit Manager
wire w_rcb_128B_sel;
wire [2:0] fc_sel;
wire [7:0] fc_nph;
wire [11:0] fc_npd;
wire [7:0] fc_ph;
wire [11:0] fc_pd;
wire [7:0] fc_cplh;
wire [11:0] fc_cpld;
wire w_pcie_ctr_fc_ready;
wire w_pcie_ctr_cmt_stb;
wire [9:0] w_pcie_ctr_dword_req_cnt;
wire w_pcie_ing_fc_rcv_stb;
wire [9:0] w_pcie_ing_fc_rcv_cnt;
//Buffer Manager
wire w_hst_buf_fin_stb;
wire [1:0] w_hst_buf_fin;
wire w_ctr_en;
wire w_ctr_mem_rd_req_stb;
wire w_ctr_dat_fin;
wire w_ctr_tag_rdy;
wire [7:0] w_ctr_tag;
wire [9:0] w_ctr_dword_size;
wire w_ctr_buf_sel;
wire w_ctr_idle;
wire [11:0] w_ctr_start_addr;
wire [7:0] w_ing_cplt_tag;
wire [6:0] w_ing_cplt_lwr_addr;
wire [1:0] w_bld_buf_en;
wire w_bld_buf_fin;
wire w_wr_fin;
wire w_rd_fin;
cross_clock_enable rd_fin_en (
.rst (o_pcie_reset ),
.in_en (i_read_fin ),
.out_clk (clk_62p5 ),
.out_en (w_rd_fin )
);
cross_clock_enable wr_fin_en (
.rst (o_pcie_reset ),
.in_en (i_write_fin ),
.out_clk (clk_62p5 ),
.out_en (w_wr_fin )
);
/****************************************************************************
* Interrupt State Machine Signals
****************************************************************************/
pcie_axi_bridge pcie_interface
//sim_pcie_axi_bridge pcie_interface
(
// PCI Express Fabric Interface
.pci_exp_txp (pci_exp_txp ),
.pci_exp_txn (pci_exp_txn ),
.pci_exp_rxp (pci_exp_rxp ),
.pci_exp_rxn (pci_exp_rxn ),
// Transaction (TRN) Interface
.user_lnk_up (user_lnk_up ),
// Tx
.s_axis_tx_tready (s_axis_tx_tready ),
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tkeep (s_axis_tx_tkeep ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
.tx_cfg_gnt (tx_cfg_gnt ),
// .user_enable_comm (user_enable_comm ),
// Rx
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tkeep (m_axis_rx_tkeep ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
.m_axis_rx_tuser (m_axis_rx_tuser ),
// output reg [21:0] m_axis_rx_tuser,
// input rx_np_ok,
.rx_np_ok (rx_np_ok ),
// Flow Control
.fc_sel (fc_sel ),
.fc_nph (fc_nph ),
.fc_npd (fc_npd ),
.fc_ph (fc_ph ),
.fc_pd (fc_pd ),
.fc_cplh (fc_cplh ),
.fc_cpld (fc_cpld ),
// Host Interface
.cfg_do (cfg_do ),
.cfg_rd_wr_done (cfg_rd_wr_done ),
.cfg_dwaddr (cfg_dwaddr ),
.cfg_rd_en (cfg_rd_en ),
// Configuration: Error
.cfg_err_ur (cfg_err_ur ),
.cfg_err_cor (cfg_err_cor ),
.cfg_err_ecrc (cfg_err_ecrc ),
.cfg_err_cpl_timeout (cfg_err_cpl_timeout ),
.cfg_err_cpl_abort (cfg_err_cpl_abort ),
.cfg_err_posted (cfg_err_posted ),
.cfg_err_locked (cfg_err_locked ),
.cfg_err_tlp_cpl_header (cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy (cfg_err_cpl_rdy ),
// Conifguration: Interrupt
.cfg_interrupt (cfg_interrupt ),
.cfg_interrupt_rdy (cfg_interrupt_rdy ),
.cfg_interrupt_assert (cfg_interrupt_assert ),
.cfg_interrupt_do (cfg_interrupt_do ),
.cfg_interrupt_di (cfg_interrupt_di ),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable ),
.cfg_interrupt_msienable (cfg_interrupt_msienable ),
// Configuration: Power Management
.cfg_turnoff_ok (cfg_turnoff_ok ),
.cfg_to_turnoff (cfg_to_turnoff ),
.cfg_pm_wake (cfg_pm_wake ),
//Core Controller
// Configuration: System/Status
.cfg_pcie_link_state (cfg_pcie_link_state ),
.cfg_trn_pending (cfg_trn_pending ), //XXX: Do I need to use cfg_trn_pending??
.cfg_dsn (SERIAL_NUMBER ),
.cfg_bus_number (cfg_bus_number ),
.cfg_device_number (cfg_device_number ),
.cfg_function_number (cfg_function_number ),
.cfg_status (cfg_status ),
.cfg_command (cfg_command ),
.cfg_dstatus (cfg_dstatus ),
.cfg_dcommand (cfg_dcommand ),
.cfg_lstatus (cfg_lstatus ),
.cfg_lcommand (cfg_lcommand ),
// System Interface
.sys_clk_p (gtp_clk_p ),
.sys_clk_n (gtp_clk_n ),
.sys_reset (i_pcie_reset ),
.user_clk_out (clk_62p5 ),
.user_reset_out (o_pcie_reset ),
.received_hot_reset (received_hot_reset ),
.pll_lock_detect (pll_lock_detect ),
.gtp_pll_lock_detect (gtp_pll_lock_detect ),
.gtp_reset_done (gtp_reset_done ),
.rx_elec_idle (rx_elec_idle ),
.rx_equalizer_ctrl (rx_equalizer_ctrl ),
.tx_diff_ctrl (tx_diff_ctrl ),
.tx_pre_emphasis (tx_pre_emphasis ),
.cfg_ltssm_state (cfg_ltssm_state ),
.tx_buf_av (tx_buf_av ),
.tx_err_drop (tx_err_drop ),
.o_bar_hit (w_bar_hit ),
.dbg_reg_detected_correctable (dbg_reg_detected_correctable ),
.dbg_reg_detected_fatal (dbg_reg_detected_fatal ),
.dbg_reg_detected_non_fatal (dbg_reg_detected_non_fatal ),
.dbg_reg_detected_unsupported (dbg_reg_detected_unsupported ),
.dbg_bad_dllp_status (dbg_bad_dllp_status ),
.dbg_bad_tlp_lcrc (dbg_bad_tlp_lcrc ),
.dbg_bad_tlp_seq_num (dbg_bad_tlp_seq_num ),
.dbg_bad_tlp_status (dbg_bad_tlp_status ),
.dbg_dl_protocol_status (dbg_dl_protocol_status ),
.dbg_fc_protocol_err_status (dbg_fc_protocol_err_status ),
.dbg_mlfrmd_length (dbg_mlfrmd_length ),
.dbg_mlfrmd_mps (dbg_mlfrmd_mps ),
.dbg_mlfrmd_tcvc (dbg_mlfrmd_tcvc ),
.dbg_mlfrmd_tlp_status (dbg_mlfrmd_tlp_status ),
.dbg_mlfrmd_unrec_type (dbg_mlfrmd_unrec_type ),
.dbg_poistlpstatus (dbg_poistlpstatus ),
.dbg_rcvr_overflow_status (dbg_rcvr_overflow_status ),
.dbg_rply_rollover_status (dbg_rply_rollover_status ),
.dbg_rply_timeout_status (dbg_rply_timeout_status ),
.dbg_ur_no_bar_hit (dbg_ur_no_bar_hit ),
.dbg_ur_pois_cfg_wr (dbg_ur_pois_cfg_wr ),
.dbg_ur_status (dbg_ur_status ),
.dbg_ur_unsup_msg (dbg_ur_unsup_msg )
);
/****************************************************************************
* Read the BAR Addresses from Config Space
****************************************************************************/
config_parser cfg (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
.i_en (w_enable_config_read ),
.o_finished (w_finished_config_read ),
.i_cfg_do (cfg_do ),
.i_cfg_rd_wr_done (cfg_rd_wr_done ),
.o_cfg_dwaddr (cfg_dwaddr ),
.o_cfg_rd_en (cfg_rd_en ),
.o_bar_addr0 (o_bar_addr0 ),
.o_bar_addr1 (o_bar_addr1 ),
.o_bar_addr2 (o_bar_addr2 ),
.o_bar_addr3 (o_bar_addr3 ),
.o_bar_addr4 (o_bar_addr4 ),
.o_bar_addr5 (o_bar_addr5 )
);
buffer_builder #(
.MEM_DEPTH (11 ), //8K Buffer
.DATA_WIDTH (32 )
) bb (
.mem_clk (clk_62p5 ),
.rst (o_pcie_reset ),
.i_ppfifo_wr_en (w_bld_buf_en ),
.o_ppfifo_wr_fin (w_bld_buf_fin ),
.i_bram_we (w_bb_buf_we ),
.i_bram_addr (w_bb_buf_addr ),
.i_bram_din (w_bb_buf_data ),
.ppfifo_clk (clk_62p5 ),
.i_data_count (w_bb_data_count ),
.i_write_ready (w_i_data_fifo_rdy ),
.o_write_activate (w_o_data_fifo_act ),
.i_write_size (w_o_data_fifo_size ),
.o_write_stb (w_i_data_fifo_stb ),
.o_write_data (w_i_data_fifo_data )
);
credit_manager cm (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//Credits
.o_fc_sel (fc_sel ),
.i_rcb_sel (w_rcb_128B_sel ),
.i_fc_cplh (fc_cplh ),
.i_fc_cpld (fc_cpld ),
//PCIE Control Interface
.o_ready (w_pcie_ctr_fc_ready ),
.i_cmt_stb (w_pcie_ctr_cmt_stb ),
.i_dword_req_count (w_pcie_ctr_dword_req_cnt ),
//Completion Receive Size
.i_rcv_stb (w_pcie_ing_fc_rcv_stb ),
.i_dword_rcv_count (w_pcie_ing_fc_rcv_cnt )
);
ingress_buffer_manager buf_man (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//Host Interface
.i_hst_buf_rdy_stb (w_update_buf_stb ),
.i_hst_buf_rdy (w_update_buf ),
.o_hst_buf_fin_stb (w_hst_buf_fin_stb ),
.o_hst_buf_fin (w_hst_buf_fin ),
//PCIE Control Interface
.i_ctr_en (w_ctr_en ),
.i_ctr_mem_rd_req_stb (w_ctr_mem_rd_req_stb ),
.i_ctr_dat_fin (w_ctr_dat_fin ),
.o_ctr_tag_rdy (w_ctr_tag_rdy ),
.o_ctr_tag (w_ctr_tag ),
.o_ctr_dword_size (w_ctr_dword_size ),
.o_ctr_start_addr (w_ctr_start_addr ),
.o_ctr_buf_sel (w_ctr_buf_sel ),
.o_ctr_idle (w_ctr_idle ),
//PCIE Ingress Interface
.i_ing_cplt_stb (w_pcie_ing_fc_rcv_stb ),
.i_ing_cplt_tag (w_ing_cplt_tag ),
.i_ing_cplt_pkt_cnt (w_pcie_ing_fc_rcv_cnt ),
.i_ing_cplt_lwr_addr (w_ing_cplt_lwr_addr ),
//Buffer Block Interface
.o_bld_mem_addr (w_ibm_buf_offset ),
.o_bld_buf_en (w_bld_buf_en ),
.i_bld_buf_fin (w_bld_buf_fin ),
.o_dbg_tag_ingress_fin (dbg_tag_ingress_fin ),
.o_dbg_tag_en (dbg_tag_en ),
.o_dbg_reenable_stb (o_dbg_reenable_stb ),
.o_dbg_reenable_nzero_stb (o_dbg_reenable_nzero_stb )
);
pcie_control controller (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//Configuration Values
.i_pcie_bus_num (cfg_bus_number ),
.i_pcie_dev_num (cfg_device_number ),
.i_pcie_fun_num (cfg_function_number ),
//Ingress Machine Interface
.i_write_a_addr (w_write_a_addr ),
.i_write_b_addr (w_write_b_addr ),
.i_read_a_addr (w_read_a_addr ),
.i_read_b_addr (w_read_b_addr ),
.i_status_addr (w_status_addr ),
.i_buffer_size (w_buffer_size ),
.i_ping_value (w_ping_value ),
.i_dev_addr (w_dev_addr ),
.i_update_buf (w_update_buf ),
.i_update_buf_stb (w_update_buf_stb ),
.i_reg_write_stb (w_reg_write_stb ),
//.i_device_select (w_device_select ),
.i_cmd_rst_stb (w_cmd_rst_stb ),
.i_cmd_wr_stb (w_cmd_wr_stb ),
.i_cmd_rd_stb (w_cmd_rd_stb ),
.i_cmd_ping_stb (w_cmd_ping_stb ),
.i_cmd_rd_cfg_stb (w_cmd_rd_cfg_stb ),
.i_cmd_unknown (w_cmd_unknown_stb ),
.i_cmd_flg_fifo (w_cmd_flg_fifo_stb ),
.i_cmd_flg_sel_periph (w_cmd_flg_sel_per_stb ),
.i_cmd_flg_sel_memory (w_cmd_flg_sel_mem_stb ),
.i_cmd_flg_sel_dma (w_cmd_flg_sel_dma_stb ),
.i_cmd_data_count (w_cmd_data_count ),
.i_cmd_data_address (w_cmd_data_address ),
.o_ctr_sel (w_ctr_fifo_sel ),
//User Interface
.o_per_sel (o_per_fifo_sel ),
.o_mem_sel (o_mem_fifo_sel ),
.o_dma_sel (o_dma_fifo_sel ),
//.i_write_fin (i_write_fin ),
.i_write_fin (w_wr_fin ),
// .i_read_fin (i_read_fin & w_egress_inactive ),
.i_read_fin (w_rd_fin & w_egress_inactive ),
.o_data_fifo_sel (w_dat_fifo_sel ),
.i_interrupt_stb (i_usr_interrupt_stb ),
.i_interrupt_value (i_usr_interrupt_value ),
.o_data_size (o_data_size ),
.o_data_address (o_data_address ),
.o_data_fifo_flg (o_data_fifo_flg ),
.o_data_read_flg (o_data_read_flg ),
.o_data_write_flg (o_data_write_flg ),
//Peripheral/Memory/DMA Egress FIFO Interface
.i_e_fifo_rdy (w_egress_fifo_rdy ),
.i_e_fifo_size (w_egress_fifo_size ),
//Egress Controller Interface
.o_egress_enable (w_egress_enable ),
.i_egress_finished (w_egress_finished ),
.o_egress_tlp_command (w_egress_tlp_command ),
.o_egress_tlp_flags (w_egress_tlp_flags ),
.o_egress_tlp_address (w_egress_tlp_address ),
.o_egress_tlp_requester_id (w_egress_tlp_requester_id ),
.o_egress_tag (w_egress_tag ),
.o_interrupt_msi_value (w_interrupt_msi_value ),
// .o_interrupt_stb (w_interrupt_stb ),
.o_interrupt_send_en (cfg_interrupt ),
.i_interrupt_send_rdy (cfg_interrupt_rdy ),
.o_egress_fifo_rdy (w_e_ctr_fifo_rdy ),
.i_egress_fifo_act (w_e_ctr_fifo_act ),
.o_egress_fifo_size (w_e_ctr_fifo_size ),
.i_egress_fifo_stb (w_e_ctr_fifo_stb ),
.o_egress_fifo_data (w_e_ctr_fifo_data ),
//Ingress Buffer Interface
.i_ibm_buf_fin_stb (w_hst_buf_fin_stb ),
.i_ibm_buf_fin (w_hst_buf_fin ),
.o_ibm_en (w_ctr_en ),
.o_ibm_req_stb (w_ctr_mem_rd_req_stb ),
.o_ibm_dat_fin (w_ctr_dat_fin ),
.i_ibm_tag_rdy (w_ctr_tag_rdy ),
.i_ibm_tag (w_ctr_tag ),
.i_ibm_dword_cnt (w_ctr_dword_size ),
.i_ibm_start_addr (w_ctr_start_addr ),
.i_ibm_buf_sel (w_ctr_buf_sel ),
.i_ibm_idle (w_ctr_idle ),
.i_buf_max_size (w_buf_max_size ),
.o_buf_data_count (w_bb_data_count ),
//System Interface
.o_sys_rst (o_sys_rst ),
.i_fc_ready (w_pcie_ctr_fc_ready ),
.o_fc_cmt_stb (w_pcie_ctr_cmt_stb ),
.o_dword_req_cnt (w_pcie_ctr_dword_req_cnt ),
//Configuration Reader Interface
.o_cfg_read_exec (o_cfg_read_exec ),
.o_cfg_sm_state (o_cfg_sm_state ),
.o_sm_state (o_sm_state )
);
//XXX: Need to think about resets
/****************************************************************************
* Single IN/OUT FIFO Solution (This Can Change in the future):
* Instead of dedicating unique FIFOs for each bus, I can just do one
* FIFO. This will reduce the size of the core at the cost of
* a certain amount of time it will take to fill up the FIFOs
****************************************************************************/
//INGRESS FIFO
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_INGRESS_FIFO_DEPTH ) // 1024 32-bit values (4096 Bytes)
) i_data_fifo (
.reset (o_pcie_reset || rst ),
//Write Side
.write_clock (clk_62p5 ),
.write_ready (w_i_data_fifo_rdy ),
.write_activate (w_o_data_fifo_act ),
.write_fifo_size (w_o_data_fifo_size ),
.write_strobe (w_i_data_fifo_stb ),
.write_data (w_i_data_fifo_data ),
//Read Side
.read_clock (i_data_clk ),
.read_ready (o_ingress_fifo_rdy ),
.read_activate (i_ingress_fifo_act ),
.read_count (o_ingress_fifo_size ),
.read_strobe (i_ingress_fifo_stb ),
.read_data (o_ingress_fifo_data ),
.inactive (o_ingress_fifo_idle )
);
//EGRESS FIFOs
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_EGRESS_FIFO_DEPTH ) // 64 32-bit values (256 Bytes)
) e_data_fifo (
.reset (o_pcie_reset || rst ),
//Write Side
.write_clock (i_data_clk ),
.write_ready (o_egress_fifo_rdy ),
.write_activate (i_egress_fifo_act ),
.write_fifo_size (o_egress_fifo_size ),
.write_strobe (i_egress_fifo_stb ),
.write_data (i_egress_fifo_data ),
//Read Side
.read_clock (clk_62p5 ),
.read_ready (w_e_data_fifo_rdy ),
.read_activate (w_e_data_fifo_act ),
.read_count (w_e_data_fifo_size ),
.read_strobe (w_e_data_fifo_stb ),
.read_data (w_e_data_fifo_data ),
.inactive (w_egress_inactive )
);
pcie_ingress ingress (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//AXI Stream Host 2 Device
.o_axi_ingress_ready (m_axis_rx_tready ),
.i_axi_ingress_data (m_axis_rx_tdata ),
.i_axi_ingress_keep (m_axis_rx_tkeep ),
.i_axi_ingress_last (m_axis_rx_tlast ),
.i_axi_ingress_valid (m_axis_rx_tvalid ),
//Configuration
.o_reg_write_stb (w_reg_write_stb ), //Strobes when new register data is detected
//Parsed out Register Values
.o_write_a_addr (w_write_a_addr ),
.o_write_b_addr (w_write_b_addr ),
.o_read_a_addr (w_read_a_addr ),
.o_read_b_addr (w_read_b_addr ),
.o_status_addr (w_status_addr ),
.o_buffer_size (w_buffer_size ),
.o_ping_value (w_ping_value ),
.o_dev_addr (w_dev_addr ),
.o_update_buf (w_update_buf ),
.o_update_buf_stb (w_update_buf_stb ),
//Command Interface
//.o_device_select (w_device_select ),
.o_cmd_rst_stb (w_cmd_rst_stb ), //Strobe when a reset command is detected
.o_cmd_wr_stb (w_cmd_wr_stb ), //Strobes when a write request is detected
.o_cmd_rd_stb (w_cmd_rd_stb ), //Strobes when a read request is detected
.o_cmd_ping_stb (w_cmd_ping_stb ), //Strobes when a ping request is detected
.o_cmd_rd_cfg_stb (w_cmd_rd_cfg_stb ), //Strobes when a read configuration id detected
.o_cmd_unknown_stb (w_cmd_unknown_stb ),
.o_cmd_flg_fifo_stb (w_cmd_flg_fifo_stb ), //Flag indicating that transfer shouldn't auto increment addr
.o_cmd_flg_sel_per_stb (w_cmd_flg_sel_per_stb ),
.o_cmd_flg_sel_mem_stb (w_cmd_flg_sel_mem_stb ),
.o_cmd_flg_sel_dma_stb (w_cmd_flg_sel_dma_stb ),
//Input Configuration Registers from either PCIE_A1 or controller
.i_bar_hit (o_bar_hit ),
//Local Address of where BAR0 is located (Used to do address translation)
.i_control_addr_base (w_control_addr_base ),
.o_enable_config_read (w_enable_config_read ),
.i_finished_config_read (w_finished_config_read ),
//When a command is detected the size of the transaction is reported here
.o_cmd_data_count (w_cmd_data_count ),
.o_cmd_data_address (w_cmd_data_address ),
//Flow Control
.o_cplt_pkt_stb (w_pcie_ing_fc_rcv_stb ),
.o_cplt_pkt_cnt (w_pcie_ing_fc_rcv_cnt ),
.o_cplt_sts (o_cplt_sts ),
.o_unknown_tlp_stb (o_unknown_tlp_stb ),
.o_unexpected_end_stb (o_unexpected_end_stb ),
.o_cplt_pkt_tag (w_ing_cplt_tag ),
.o_cplt_pkt_lwr_addr (w_ing_cplt_lwr_addr ),
//Buffer interface, the buffer controller will manage this
.i_buf_offset (w_ibm_buf_offset ),
.o_buf_we (w_bb_buf_we ),
.o_buf_addr (w_bb_buf_addr ),
.o_buf_data (w_bb_buf_data ),
.o_state (o_ingress_state ),
.o_ingress_count (o_ingress_count ),
.o_ingress_ri_count (o_ingress_ri_count ),
.o_ingress_ci_count (o_ingress_ci_count ),
.o_ingress_cmplt_count (o_ingress_cmplt_count ),
.o_ingress_addr (o_ingress_addr )
);
pcie_egress egress (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
.i_enable (w_egress_enable ),
.o_finished (w_egress_finished ),
.i_command (w_egress_tlp_command ),
.i_flags (w_egress_tlp_flags ),
.i_address (w_egress_tlp_address ),
.i_requester_id (w_egress_tlp_requester_id ),
.i_tag (w_egress_tag ),
.i_req_dword_cnt (w_pcie_ctr_dword_req_cnt ),
//AXI Interface
.i_axi_egress_ready (s_axis_tx_tready ),
.o_axi_egress_data (s_axis_tx_tdata ),
.o_axi_egress_keep (s_axis_tx_tkeep ),
.o_axi_egress_last (s_axis_tx_tlast ),
.o_axi_egress_valid (s_axis_tx_tvalid ),
//Data FIFO Interface
.i_fifo_rdy (w_egress_fifo_rdy ),
.o_fifo_act (w_egress_fifo_act ),
.i_fifo_size (w_egress_fifo_size ),
.i_fifo_data (w_egress_fifo_data ),
.o_fifo_stb (w_egress_fifo_stb ),
.dbg_ready_drop (dbg_ready_drop )
);
/****************************************************************************
* FIFO Multiplexer
****************************************************************************/
assign w_egress_fifo_rdy = (w_ctr_fifo_sel) ? w_e_ctr_fifo_rdy:
(w_dat_fifo_sel) ? w_e_data_fifo_rdy:
1'b0;
assign w_egress_fifo_size = (w_ctr_fifo_sel) ? w_e_ctr_fifo_size:
(w_dat_fifo_sel) ? w_e_data_fifo_size:
24'h0;
assign w_egress_fifo_data = (w_ctr_fifo_sel) ? w_e_ctr_fifo_data:
(w_dat_fifo_sel) ? w_e_data_fifo_data:
32'h00;
assign w_e_ctr_fifo_act = (w_ctr_fifo_sel) ? w_egress_fifo_act:
1'b0;
assign w_e_ctr_fifo_stb = (w_ctr_fifo_sel) ? w_egress_fifo_stb:
1'b0;
assign w_e_data_fifo_act = (w_dat_fifo_sel) ? w_egress_fifo_act:
1'b0;
assign w_e_data_fifo_stb = (w_dat_fifo_sel) ? w_egress_fifo_stb:
1'b0;
//assign w_dat_fifo_sel = (o_per_fifo_sel || o_mem_fifo_sel || o_dma_fifo_sel);
/****************************************************************************
* Temporary Debug Signals
****************************************************************************/
//This used to go to the wishbone slave device
//Need to create a flow controller
assign o_receive_axi_ready = 0;
/****************************************************************************
* AXI Signals from the user to the PCIE_A1 Core
****************************************************************************/
assign s_axis_tx_discont = 0;
assign s_axis_tx_stream = 0;
assign s_axis_tx_err_fwd = 0;
assign s_axis_tx_s6_not_used = 0;
assign s_axis_tx_tuser = {s_axis_tx_discont,
s_axis_tx_stream,
s_axis_tx_err_fwd,
s_axis_tx_s6_not_used};
//Use this BAR Hist because it is buffered with the AXI transaction
assign o_bar_hit = m_axis_rx_tuser[8:2];
assign dbg_rerrfwd = m_axis_rx_tuser[1];
/****************************************************************************
* The Following Signals Need to be integrated into the core
****************************************************************************/
//XXX: THIS SIGNAL MIGHT NEED TO BE SET HIGH WHEN AN UPSTREAM DATA REQUEST IS SENT
assign cfg_trn_pending = 1'b0;
//Allow PCIE_A1 Core to have priority over transactions
assign tx_cfg_gnt = 1'b1;
//Allow PCIE_A1 Core to send non-posted transactions to the user application (Flow Control from user app)
assign rx_np_ok = 1'b1;
/****************************************************************************
* Ingress Buffer Manager
****************************************************************************/
//XXX: THIS IS TEMPORARY BEFORE BUFFER MANAGER IS DONE
/****************************************************************************
* Add the configuration state machine controller to a command, the user
* should be able to send an initialization signal from the host, this will
* Trigger the configuration controller to read the internal address register
* of the bars... is this needed anymore? The host will only write small
* transactions to configure the state machine, there doesn't seem to be a
* reason for the configuration state machine any more
****************************************************************************/
//assign cfg_interrupt_di = i_interrupt_channel;
//assign cfg_interrupt_stb = i_interrupt_stb;
assign cfg_interrupt_di = w_interrupt_msi_value;
//assign cfg_interrupt_stb = w_interrupt_stb;
assign w_rcb_128B_sel = cfg_lcommand[3];
/****************************************************************************
* Interrupt State Machine
****************************************************************************/
//asynchronous logic
//synchronous logic
localparam IDLE = 0;
localparam SEND_INTERRUPT = 1;
reg int_state = IDLE;
/*
always @ (posedge clk_62p5) begin
if (o_pcie_reset) begin
cfg_interrupt <= 0;
int_state <= IDLE;
end
else begin
case (int_state)
IDLE: begin
cfg_interrupt <= 0;
if (cfg_interrupt_stb)
int_state <= SEND_INTERRUPT;
end
SEND_INTERRUPT: begin
cfg_interrupt <= 1;
if (cfg_interrupt_rdy) begin
int_state <= IDLE;
cfg_interrupt <= 0;
end
end
endcase
end
end
*/
endmodule |
module tb (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE
);
//SRAM
wire [19:0] SRAM_A;
wire [15:0] SRAM_IO;
wire SRAM_BHE_B;
wire SRAM_BLE_B;
wire SRAM_CE1_B;
wire SRAM_OE_B;
wire SRAM_WE_B;
wire [4:0] LED;
wire SDA;
wire SCL;
sram_test dut(.FCLK_IN(FCLK_IN),
.BUS_DATA(BUS_DATA), .ADD(ADD), .RD_B(RD_B), .WR_B(WR_B),
.FD(FD), .FREAD(FREAD), .FSTROBE(FSTROBE), .FMODE(FMODE),
.SRAM_A(SRAM_A), .SRAM_IO(SRAM_IO), .SRAM_BHE_B(SRAM_BHE_B), .SRAM_BLE_B(SRAM_BLE_B), .SRAM_CE1_B(SRAM_CE1_B), .SRAM_OE_B(SRAM_OE_B), .SRAM_WE_B(SRAM_WE_B),
.LED(LED), .SDA(SDA), .SCL(SCL) );
defparam dut.i_out_fifo.DEPTH = 21'h100;
/// SRAM
reg [15:0] sram [1048576-1:0];
always@(negedge SRAM_WE_B)
sram[SRAM_A] <= SRAM_IO;
assign SRAM_IO = !SRAM_OE_B ? sram[SRAM_A] : 16'hzzzz;
initial begin
$dumpfile("sram_test.vcd");
$dumpvars(0);
end
endmodule |
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: QSFP28
*/
input wire qsfp_tx_clk_1,
input wire qsfp_tx_rst_1,
output wire [63:0] qsfp_txd_1,
output wire [7:0] qsfp_txc_1,
input wire qsfp_rx_clk_1,
input wire qsfp_rx_rst_1,
input wire [63:0] qsfp_rxd_1,
input wire [7:0] qsfp_rxc_1,
input wire qsfp_tx_clk_2,
input wire qsfp_tx_rst_2,
output wire [63:0] qsfp_txd_2,
output wire [7:0] qsfp_txc_2,
input wire qsfp_rx_clk_2,
input wire qsfp_rx_rst_2,
input wire [63:0] qsfp_rxd_2,
input wire [7:0] qsfp_rxc_2,
input wire qsfp_tx_clk_3,
input wire qsfp_tx_rst_3,
output wire [63:0] qsfp_txd_3,
output wire [7:0] qsfp_txc_3,
input wire qsfp_rx_clk_3,
input wire qsfp_rx_rst_3,
input wire [63:0] qsfp_rxd_3,
input wire [7:0] qsfp_rxc_3,
input wire qsfp_tx_clk_4,
input wire qsfp_tx_rst_4,
output wire [63:0] qsfp_txd_4,
output wire [7:0] qsfp_txc_4,
input wire qsfp_rx_clk_4,
input wire qsfp_rx_rst_4,
input wire [63:0] qsfp_rxd_4,
input wire [7:0] qsfp_rxc_4,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_gmii_clk,
input wire phy_gmii_rst,
input wire phy_gmii_clk_en,
input wire [7:0] phy_gmii_rxd,
input wire phy_gmii_rx_dv,
input wire phy_gmii_rx_er,
output wire [7:0] phy_gmii_txd,
output wire phy_gmii_tx_en,
output wire phy_gmii_tx_er,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [63:0] mac_rx_axis_tdata;
wire [7:0] mac_rx_axis_tkeep;
wire mac_rx_axis_tvalid;
wire mac_rx_axis_tready;
wire mac_rx_axis_tlast;
wire mac_rx_axis_tuser;
wire [63:0] mac_tx_axis_tdata;
wire [7:0] mac_tx_axis_tkeep;
wire mac_tx_axis_tvalid;
wire mac_tx_axis_tready;
wire mac_tx_axis_tlast;
wire mac_tx_axis_tuser;
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign qsfp_txd_2 = 64'h0707070707070707;
assign qsfp_txc_2 = 8'hff;
assign qsfp_txd_3 = 64'h0707070707070707;
assign qsfp_txc_3 = 8'hff;
assign qsfp_txd_4 = 64'h0707070707070707;
assign qsfp_txc_4 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp_rx_clk_1),
.rx_rst(qsfp_rx_rst_1),
.tx_clk(qsfp_tx_clk_1),
.tx_rst(qsfp_tx_rst_1),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(mac_tx_axis_tdata),
.tx_axis_tkeep(mac_tx_axis_tkeep),
.tx_axis_tvalid(mac_tx_axis_tvalid),
.tx_axis_tready(mac_tx_axis_tready),
.tx_axis_tlast(mac_tx_axis_tlast),
.tx_axis_tuser(mac_tx_axis_tuser),
.rx_axis_tdata(mac_rx_axis_tdata),
.rx_axis_tkeep(mac_rx_axis_tkeep),
.rx_axis_tvalid(mac_rx_axis_tvalid),
.rx_axis_tready(mac_rx_axis_tready),
.rx_axis_tlast(mac_rx_axis_tlast),
.rx_axis_tuser(mac_rx_axis_tuser),
.xgmii_rxd(qsfp_rxd_1),
.xgmii_rxc(qsfp_rxc_1),
.xgmii_txd(qsfp_txd_1),
.xgmii_txc(qsfp_txc_1),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
// 1G interface for debugging
wire [7:0] gig_rx_axis_tdata;
wire gig_rx_axis_tvalid;
wire gig_rx_axis_tready;
wire gig_rx_axis_tlast;
wire gig_rx_axis_tuser;
wire [7:0] gig_tx_axis_tdata;
wire gig_tx_axis_tvalid;
wire gig_tx_axis_tready;
wire gig_tx_axis_tlast;
wire gig_tx_axis_tuser;
wire [63:0] gig_rx_axis_tdata_64;
wire [7:0] gig_rx_axis_tkeep_64;
wire gig_rx_axis_tvalid_64;
wire gig_rx_axis_tready_64;
wire gig_rx_axis_tlast_64;
wire gig_rx_axis_tuser_64;
wire [63:0] gig_tx_axis_tdata_64;
wire [7:0] gig_tx_axis_tkeep_64;
wire gig_tx_axis_tvalid_64;
wire gig_tx_axis_tready_64;
wire gig_tx_axis_tlast_64;
wire gig_tx_axis_tuser_64;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_1g_inst (
.rx_clk(phy_gmii_clk),
.rx_rst(phy_gmii_rst),
.tx_clk(phy_gmii_clk),
.tx_rst(phy_gmii_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(gig_tx_axis_tdata),
.tx_axis_tvalid(gig_tx_axis_tvalid),
.tx_axis_tready(gig_tx_axis_tready),
.tx_axis_tlast(gig_tx_axis_tlast),
.tx_axis_tuser(gig_tx_axis_tuser),
.rx_axis_tdata(gig_rx_axis_tdata),
.rx_axis_tvalid(gig_rx_axis_tvalid),
.rx_axis_tready(gig_rx_axis_tready),
.rx_axis_tlast(gig_rx_axis_tlast),
.rx_axis_tuser(gig_rx_axis_tuser),
.gmii_rxd(phy_gmii_rxd),
.gmii_rx_dv(phy_gmii_rx_dv),
.gmii_rx_er(phy_gmii_rx_er),
.gmii_txd(phy_gmii_txd),
.gmii_tx_en(phy_gmii_tx_en),
.gmii_tx_er(phy_gmii_tx_er),
.rx_clk_enable(phy_gmii_clk_en),
.tx_clk_enable(phy_gmii_clk_en),
.rx_mii_select(1'b0),
.tx_mii_select(1'b0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
axis_adapter #(
.S_DATA_WIDTH(8),
.M_DATA_WIDTH(64),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
gig_rx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(gig_rx_axis_tdata),
.s_axis_tkeep(1'b1),
.s_axis_tvalid(gig_rx_axis_tvalid),
.s_axis_tready(gig_rx_axis_tready),
.s_axis_tlast(gig_rx_axis_tlast),
.s_axis_tuser(gig_rx_axis_tuser),
// AXI output
.m_axis_tdata(gig_rx_axis_tdata_64),
.m_axis_tkeep(gig_rx_axis_tkeep_64),
.m_axis_tvalid(gig_rx_axis_tvalid_64),
.m_axis_tready(gig_rx_axis_tready_64),
.m_axis_tlast(gig_rx_axis_tlast_64),
.m_axis_tuser(gig_rx_axis_tuser_64)
);
axis_adapter #(
.S_DATA_WIDTH(64),
.M_DATA_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
gig_tx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(gig_tx_axis_tdata_64),
.s_axis_tkeep(gig_tx_axis_tkeep_64),
.s_axis_tvalid(gig_tx_axis_tvalid_64),
.s_axis_tready(gig_tx_axis_tready_64),
.s_axis_tlast(gig_tx_axis_tlast_64),
.s_axis_tuser(gig_tx_axis_tuser_64),
// AXI output
.m_axis_tdata(gig_tx_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(gig_tx_axis_tvalid),
.m_axis_tready(gig_tx_axis_tready),
.m_axis_tlast(gig_tx_axis_tlast),
.m_axis_tuser(gig_tx_axis_tuser)
);
// tap port mux logic
// sw[3] enable
// sw[2] select 0 rx, 1 tx
reg [1:0] mac_rx_tdest;
reg [1:0] tx_tdest;
reg [1:0] gig_rx_tdest;
always @* begin
if (sw[3]) begin
if (sw[2]) begin
// Tap on TX path
// MAC RX out -> stack RX in
// stack TX out -> gig TX in
// gig RX out -> MAC TX in
mac_rx_tdest = 2'd1;
tx_tdest = 2'd2;
gig_rx_tdest = 2'd0;
end else begin
// Tap on RX path
// MAC RX out -> gig TX in
// stack TX out -> MAC TX in
// gig RX out -> stack RX in
mac_rx_tdest = 2'd2;
tx_tdest = 2'd0;
gig_rx_tdest = 2'd1;
end
end else begin
// Tap disabled
// MAC RX out -> stack RX in
// stack TX out -> MAC TX in
// gig RX out -> blackhole
mac_rx_tdest = 2'd1;
tx_tdest = 2'd0;
gig_rx_tdest = 2'd3;
end
end
axis_switch #(
.S_COUNT(3),
.M_COUNT(3),
.DATA_WIDTH(64),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_WIDTH(2),
.USER_ENABLE(1),
.USER_WIDTH(1),
.M_BASE({2'd2, 2'd1, 2'd0}),
.M_TOP({2'd2, 2'd1, 2'd0}),
.M_CONNECT({3{3'b111}}),
.S_REG_TYPE(0),
.M_REG_TYPE(2),
.ARB_TYPE_ROUND_ROBIN(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
axis_switch_inst (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata({ gig_rx_axis_tdata_64, tx_axis_tdata, mac_rx_axis_tdata}),
.s_axis_tkeep({ gig_rx_axis_tkeep_64, tx_axis_tkeep, mac_rx_axis_tkeep}),
.s_axis_tvalid({gig_rx_axis_tvalid_64, tx_axis_tvalid, mac_rx_axis_tvalid}),
.s_axis_tready({gig_rx_axis_tready_64, tx_axis_tready, mac_rx_axis_tready}),
.s_axis_tlast({ gig_rx_axis_tlast_64, tx_axis_tlast, mac_rx_axis_tlast}),
.s_axis_tid(0),
.s_axis_tdest({ gig_rx_tdest, tx_tdest, mac_rx_tdest}),
.s_axis_tuser({ gig_rx_axis_tuser_64, tx_axis_tuser, mac_rx_axis_tuser}),
// AXI outputs
.m_axis_tdata({ gig_tx_axis_tdata_64, rx_axis_tdata, mac_tx_axis_tdata}),
.m_axis_tkeep({ gig_tx_axis_tkeep_64, rx_axis_tkeep, mac_tx_axis_tkeep}),
.m_axis_tvalid({gig_tx_axis_tvalid_64, rx_axis_tvalid, mac_tx_axis_tvalid}),
.m_axis_tready({gig_tx_axis_tready_64, rx_axis_tready, mac_tx_axis_tready}),
.m_axis_tlast({ gig_tx_axis_tlast_64, rx_axis_tlast, mac_tx_axis_tlast}),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser({ gig_tx_axis_tuser_64, rx_axis_tuser, mac_tx_axis_tuser})
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule |
module sclk_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 25,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule |
module dpth_alu_top (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
input wire rst_n,
//------------------------------
// Inputs
//------------------------------
input wire [15:0] rx,
input wire [15:0] m_data,
input wire ld_ir,
input wire ld_ra,
input wire ld_rz,
input wire ld_rn,
//------------------------------
// Outputs
//------------------------------
output reg [15:0] ir,
output wire [15:0] alu_out,
output reg rz,
output reg rn
);
//------------------------------
// Local registers
//------------------------------
reg [15:0] ra;
//------------------------------
// Local wires
//------------------------------
wire [15:0] ir_ext;
wire [15:0] alu_in_a;
reg [15:0] alu_in_b;
wire alu_z;
wire alu_n;
//------------------------------
// Local registers assignments
//------------------------------
always @(negedge rst_n, posedge clk)
begin: p_alu_ir_update
if (rst_n == 1'b0)
ir <= {16{1'b0}};
else if (ld_ir == 1'b1)
ir <= m_data;
end
always @(negedge rst_n, posedge clk)
begin: p_alu_ra_update
if (rst_n == 1'b0)
ra <= {16{1'b0}};
else if (ld_ra == 1'b1)
ra <= rx;
end
always @(negedge rst_n, posedge clk)
begin: p_alu_rz_update
if (rst_n == 1'b0)
rz <= 1'b0;
else if (ld_ir == 1'b1)
rz <= alu_z;
end
always @(negedge rst_n, posedge clk)
begin: p_alu_rn_update
if (rst_n == 1'b0)
rn <= 1'b0;
else if (ld_ir == 1'b1)
rn <= alu_n;
end
//------------------------------
// SELDAT mux
//------------------------------
always @(*)
begin : p_seldat_mux
if (ir[14] == 1'b0)
alu_in_b = m_data;
else if (ir[2] == 1'b0)
alu_in_b = ir_ext;
else
alu_in_b = rx;
end
//------------------------------
// Local wires
//------------------------------
assign ir_ext = {{12{ir[7]}}, ir[6:3]};
//------------------------------
// ALU
//------------------------------
dpth_alu alu (
// Input operands
.in_a ( alu_in_a ),
.in_b ( alu_in_b ),
// Output result
.out ( alu_out ),
// Input control
.op ( ir[1:0] ),
.enable( operate ),
// Output parameters
.z ( alu_z ),
.n ( alu_n )
);
endmodule |
module gmii_phy_if #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2"
)
(
input wire clk,
input wire rst,
/*
* GMII interface to MAC
*/
output wire mac_gmii_rx_clk,
output wire mac_gmii_rx_rst,
output wire [7:0] mac_gmii_rxd,
output wire mac_gmii_rx_dv,
output wire mac_gmii_rx_er,
output wire mac_gmii_tx_clk,
output wire mac_gmii_tx_rst,
input wire [7:0] mac_gmii_txd,
input wire mac_gmii_tx_en,
input wire mac_gmii_tx_er,
/*
* GMII interface to PHY
*/
input wire phy_gmii_rx_clk,
input wire [7:0] phy_gmii_rxd,
input wire phy_gmii_rx_dv,
input wire phy_gmii_rx_er,
input wire phy_mii_tx_clk,
output wire phy_gmii_tx_clk,
output wire [7:0] phy_gmii_txd,
output wire phy_gmii_tx_en,
output wire phy_gmii_tx_er,
/*
* Control
*/
input wire mii_select
);
ssio_sdr_in #
(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(10)
)
rx_ssio_sdr_inst (
.input_clk(phy_gmii_rx_clk),
.input_d({phy_gmii_rxd, phy_gmii_rx_dv, phy_gmii_rx_er}),
.output_clk(mac_gmii_rx_clk),
.output_q({mac_gmii_rxd, mac_gmii_rx_dv, mac_gmii_rx_er})
);
ssio_sdr_out #
(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(10)
)
tx_ssio_sdr_inst (
.clk(mac_gmii_tx_clk),
.input_d({mac_gmii_txd, mac_gmii_tx_en, mac_gmii_tx_er}),
.output_clk(phy_gmii_tx_clk),
.output_q({phy_gmii_txd, phy_gmii_tx_en, phy_gmii_tx_er})
);
generate
if (TARGET == "XILINX") begin
BUFGMUX
gmii_bufgmux_inst (
.I0(clk),
.I1(phy_mii_tx_clk),
.S(mii_select),
.O(mac_gmii_tx_clk)
);
end else begin
assign mac_gmii_tx_clk = mii_select ? phy_mii_tx_clk : clk;
end
endgenerate
// reset sync
reg [3:0] tx_rst_reg = 4'hf;
assign mac_gmii_tx_rst = tx_rst_reg[0];
always @(posedge mac_gmii_tx_clk or posedge rst) begin
if (rst) begin
tx_rst_reg <= 4'hf;
end else begin
tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
end
end
reg [3:0] rx_rst_reg = 4'hf;
assign mac_gmii_rx_rst = rx_rst_reg[0];
always @(posedge mac_gmii_rx_clk or posedge rst) begin
if (rst) begin
rx_rst_reg <= 4'hf;
end else begin
rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
end
end
endmodule |
module iss_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire enable,
// PC related inputs from fetch stage
input wire[31:0] next_pc_iss_pipe_reg_i,
input wire[31:0] instr_iss_pipe_reg_i,
input wire brn_pred_iss_pipe_reg_i,
input wire[31:0] curr_pc_iss_pipe_reg_i,
input wire[31:0] next_pred_pc_iss_pipe_reg_i,
// Register outputs
output wire[31:0] next_pc_iss_pipe_reg_o,
output wire[31:0] instr_iss_pipe_reg_o,
output wire brn_pred_iss_pipe_reg_o,
output wire[31:0] curr_pc_iss_pipe_reg_o,
output wire[31:0] next_pred_pc_iss_pipe_reg_o
);
reg [31:0] next_pc_iss_pipe_reg;
reg [31:0] instr_iss_pipe_reg;
reg brn_pred_iss_pipe_reg;
reg [31:0] curr_pc_iss_pipe_reg;
reg [31:0] next_pred_pc_iss_pipe_reg;
assign next_pc_iss_pipe_reg_o = next_pc_iss_pipe_reg;
assign instr_iss_pipe_reg_o = instr_iss_pipe_reg;
assign brn_pred_iss_pipe_reg_o = brn_pred_iss_pipe_reg;
assign curr_pc_iss_pipe_reg_o = curr_pc_iss_pipe_reg;
assign next_pred_pc_iss_pipe_reg_o = next_pred_pc_iss_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
next_pc_iss_pipe_reg <= 31'b0;
instr_iss_pipe_reg <= 31'b0;
brn_pred_iss_pipe_reg <= 31'b0;
curr_pc_iss_pipe_reg <= 31'b0;
next_pred_pc_iss_pipe_reg <= 31'b0;
end
else if (~enable)
begin
next_pc_iss_pipe_reg <= next_pc_iss_pipe_reg_i;
instr_iss_pipe_reg <= instr_iss_pipe_reg_i;
brn_pred_iss_pipe_reg <= brn_pred_iss_pipe_reg_i;
curr_pc_iss_pipe_reg <= curr_pc_iss_pipe_reg_i;
next_pred_pc_iss_pipe_reg <= next_pred_pc_iss_pipe_reg_i;
end
endmodule |
module sd_data_master (
input sd_clk,
input rst,
input start_tx_i,
input start_rx_i,
//Output to SD-Host Reg
output reg d_write_o,
output reg d_read_o,
//To fifo filler
output reg start_tx_fifo_o,
output reg start_rx_fifo_o,
input tx_fifo_empty_i,
input tx_fifo_full_i,
input rx_fifo_full_i,
//SD-DATA_Host
input xfr_complete_i,
input crc_ok_i,
//status output
output reg [`INT_DATA_SIZE-1:0] int_status_o,
input int_status_rst_i
);
reg tx_cycle;
parameter SIZE = 3;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 3'b000;
parameter START_TX_FIFO = 3'b001;
parameter START_RX_FIFO = 3'b010;
parameter DATA_TRANSFER = 3'b100;
reg trans_done;
always @(state or start_tx_i or start_rx_i or tx_fifo_full_i or xfr_complete_i or trans_done)
begin: FSM_COMBO
case(state)
IDLE: begin
if (start_tx_i == 1) begin
next_state <= START_TX_FIFO;
end
else if (start_rx_i == 1) begin
next_state <= START_RX_FIFO;
end
else begin
next_state <= IDLE;
end
end
START_TX_FIFO: begin
if (tx_fifo_full_i == 1 && xfr_complete_i == 0)
next_state <= DATA_TRANSFER;
else
next_state <= START_TX_FIFO;
end
START_RX_FIFO: begin
if (xfr_complete_i == 0)
next_state <= DATA_TRANSFER;
else
next_state <= START_RX_FIFO;
end
DATA_TRANSFER: begin
if (trans_done)
next_state <= IDLE;
else
next_state <= DATA_TRANSFER;
end
default: next_state <= IDLE;
endcase
end
//----------------Seq logic------------
always @(posedge sd_clk or posedge rst)
begin: FSM_SEQ
if (rst) begin
state <= IDLE;
end
else begin
state <= next_state;
end
end
//Output logic-----------------
always @(posedge sd_clk or posedge rst)
begin
if (rst) begin
start_tx_fifo_o <= 0;
start_rx_fifo_o <= 0;
d_write_o <= 0;
d_read_o <= 0;
trans_done <= 0;
tx_cycle <= 0;
int_status_o <= 0;
end
else begin
case(state)
IDLE: begin
start_tx_fifo_o <= 0;
start_rx_fifo_o <= 0;
d_write_o <= 0;
d_read_o <= 0;
trans_done <= 0;
tx_cycle <= 0;
end
START_RX_FIFO: begin
start_rx_fifo_o <= 1;
start_tx_fifo_o <= 0;
tx_cycle <= 0;
d_read_o <= 1;
end
START_TX_FIFO: begin
start_rx_fifo_o <= 0;
start_tx_fifo_o <= 1;
tx_cycle <= 1;
if (tx_fifo_full_i == 1)
d_write_o <= 1;
end
DATA_TRANSFER: begin
d_read_o <= 0;
d_write_o <= 0;
if (tx_cycle) begin
if (tx_fifo_empty_i) begin
if (!trans_done)
int_status_o[`INT_DATA_CFE] <= 1;
trans_done <= 1;
//stop sd_data_serial_host
d_write_o <= 1;
d_read_o <= 1;
end
end
else begin
if (rx_fifo_full_i) begin
if (!trans_done)
int_status_o[`INT_DATA_CFE] <= 1;
trans_done <= 1;
//stop sd_data_serial_host
d_write_o <= 1;
d_read_o <= 1;
end
end
if (xfr_complete_i) begin //Transfer complete
d_write_o <= 0;
d_read_o <= 0;
trans_done <= 1;
if (!crc_ok_i) begin //Wrong CRC and Data line free.
if (!trans_done)
int_status_o[`INT_DATA_CCRCE] <= 1;
end
else if (crc_ok_i) begin //Data Line free
if (!trans_done)
int_status_o[`INT_DATA_CC] <= 1;
end
end
end
endcase
if (int_status_rst_i)
int_status_o<=0;
end
end
endmodule |
module pdp1_iot(i_clk, i_rst,
pd_inst, pd_wait, pd_in, pd_out,
bs_stb, bs_adr, bs_pout, bs_pin, bs_dout, bs_din);
input i_clk;
input i_rst;
input [0:17] pd_inst;
output pd_wait;
input [0:17] pd_in;
output [0:17] pd_out;
output reg bs_stb;
output [0:10] bs_adr;
output bs_pout;
input bs_pin;
output [0:17] bs_dout;
input [0:17] bs_din;
wire [0:4] w_inst_op;
wire w_inst_w;
wire w_inst_p;
wire [0:4] w_inst_sop;
wire [0:5] w_inst_dev;
assign w_inst_op = pd_inst[0:4];
assign w_inst_w = pd_inst[5];
assign w_inst_p = pd_inst[6];
assign w_inst_sop = pd_inst[7:11];
assign w_inst_dev = pd_inst[12:17];
reg r_IOH;
reg r_IOP;
assign bs_adr = {w_inst_dev|w_inst_sop};
assign bs_pout = w_inst_p|w_inst_w;
assign pd_wait = r_IOH | ~r_IOP;
always @(posedge i_clk) begin
if(i_rst) begin
r_IOH <= 0;
r_IOP <= 0;
end
else begin
if(bs_pin)
r_IOP <= 1'b1;
if(w_inst_op == `PDP1_OP_IOT) begin
if(~(|{w_inst_dev, w_inst_sop})) begin // IOT 0000
if(r_IOP)
r_IOP <= 1'b0;
end
if(~r_IOH) begin
bs_stb <= 1'b1;
if(w_inst_w|w_inst_p)
r_IOP <= 1'b0;
if(w_inst_w)
r_IOH <= 1'b1;
end
else begin
if(bs_pin)
r_IOH <= 1'b0;
end
end // if (w_inst_op == `PDP1_OP_IOT)
end // else: !if(i_rst)
end // always @ (posedge i_clk)
endmodule |
module sky130_fd_sc_hd__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule |
module
assign daisy_p_o = 1'bz;
assign daisy_n_o = 1'bz;
endmodule |
module sensor_interface_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
// Register file signals
input wire clk,
input wire mm_en,
input wire mm_wr,
output reg [C_S_AXI_ADDR_WIDTH-1:0] mm_addr,
output reg [C_S_AXI_DATA_WIDTH-1:0] mm_wdata,
input wire [C_S_AXI_DATA_WIDTH-1:0] mm_rdata,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam OPT_MEM_ADDR_BITS = 1;
// Register file signals
reg [C_S_AXI_ADDR_WIDTH-1:0] reg_file [C_S_AXI_DATA_WIDTH-1:0];
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK or negedge S_AXI_ARESETN )
begin
if (S_AXI_ARESETN == 1'b1) begin
if (slv_reg_wren)
begin
/*
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
reg_file[axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]][(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
*/
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
mm_addr <= axi_araddr;
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= {mm_rdata[7:0], mm_rdata[15:8], mm_rdata[23:16], mm_rdata[31:24]}; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule |
module sky130_fd_sc_hs__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule |
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module system_util_ds_buf_0_0
(BUFG_I,
BUFG_O);
(* x_interface_info = "xilinx.com:signal:clock:1.0 BUFG_I CLK" *) input [0:0]BUFG_I;
(* x_interface_info = "xilinx.com:signal:clock:1.0 BUFG_O CLK" *) output [0:0]BUFG_O;
wire [0:0]BUFG_I;
wire [0:0]BUFG_O;
wire [0:0]NLW_U0_BUFGCE_O_UNCONNECTED;
wire [0:0]NLW_U0_BUFG_GT_O_UNCONNECTED;
wire [0:0]NLW_U0_BUFHCE_O_UNCONNECTED;
wire [0:0]NLW_U0_BUFH_O_UNCONNECTED;
wire [0:0]NLW_U0_IBUF_DS_ODIV2_UNCONNECTED;
wire [0:0]NLW_U0_IBUF_OUT_UNCONNECTED;
wire [0:0]NLW_U0_IOBUF_DS_N_UNCONNECTED;
wire [0:0]NLW_U0_IOBUF_DS_P_UNCONNECTED;
wire [0:0]NLW_U0_IOBUF_IO_O_UNCONNECTED;
wire [0:0]NLW_U0_OBUF_DS_N_UNCONNECTED;
wire [0:0]NLW_U0_OBUF_DS_P_UNCONNECTED;
(* C_BUF_TYPE = "BUFG" *)
(* C_SIZE = "1" *)
system_util_ds_buf_0_0_util_ds_buf U0
(.BUFGCE_CE(1'b0),
.BUFGCE_I(1'b0),
.BUFGCE_O(NLW_U0_BUFGCE_O_UNCONNECTED[0]),
.BUFG_GT_CE(1'b0),
.BUFG_GT_CEMASK(1'b0),
.BUFG_GT_CLR(1'b0),
.BUFG_GT_CLRMASK(1'b0),
.BUFG_GT_DIV({1'b0,1'b0,1'b0}),
.BUFG_GT_I(1'b0),
.BUFG_GT_O(NLW_U0_BUFG_GT_O_UNCONNECTED[0]),
.BUFG_I(BUFG_I),
.BUFG_O(BUFG_O),
.BUFHCE_CE(1'b0),
.BUFHCE_I(1'b0),
.BUFHCE_O(NLW_U0_BUFHCE_O_UNCONNECTED[0]),
.BUFH_I(1'b0),
.BUFH_O(NLW_U0_BUFH_O_UNCONNECTED[0]),
.IBUF_DS_N(1'b0),
.IBUF_DS_ODIV2(NLW_U0_IBUF_DS_ODIV2_UNCONNECTED[0]),
.IBUF_DS_P(1'b0),
.IBUF_OUT(NLW_U0_IBUF_OUT_UNCONNECTED[0]),
.IOBUF_DS_N(NLW_U0_IOBUF_DS_N_UNCONNECTED[0]),
.IOBUF_DS_P(NLW_U0_IOBUF_DS_P_UNCONNECTED[0]),
.IOBUF_IO_I(1'b0),
.IOBUF_IO_O(NLW_U0_IOBUF_IO_O_UNCONNECTED[0]),
.IOBUF_IO_T(1'b0),
.OBUF_DS_N(NLW_U0_OBUF_DS_N_UNCONNECTED[0]),
.OBUF_DS_P(NLW_U0_OBUF_DS_P_UNCONNECTED[0]),
.OBUF_IN(1'b0));
endmodule |
module system_util_ds_buf_0_0_util_ds_buf
(IBUF_DS_P,
IBUF_DS_N,
IBUF_OUT,
IBUF_DS_ODIV2,
OBUF_IN,
OBUF_DS_P,
OBUF_DS_N,
IOBUF_DS_P,
IOBUF_DS_N,
IOBUF_IO_T,
IOBUF_IO_I,
IOBUF_IO_O,
BUFG_I,
BUFG_O,
BUFGCE_I,
BUFGCE_CE,
BUFGCE_O,
BUFH_I,
BUFH_O,
BUFHCE_I,
BUFHCE_CE,
BUFHCE_O,
BUFG_GT_I,
BUFG_GT_CE,
BUFG_GT_CEMASK,
BUFG_GT_CLR,
BUFG_GT_CLRMASK,
BUFG_GT_DIV,
BUFG_GT_O);
input [0:0]IBUF_DS_P;
input [0:0]IBUF_DS_N;
output [0:0]IBUF_OUT;
output [0:0]IBUF_DS_ODIV2;
input [0:0]OBUF_IN;
output [0:0]OBUF_DS_P;
output [0:0]OBUF_DS_N;
inout [0:0]IOBUF_DS_P;
inout [0:0]IOBUF_DS_N;
input [0:0]IOBUF_IO_T;
input [0:0]IOBUF_IO_I;
output [0:0]IOBUF_IO_O;
input [0:0]BUFG_I;
output [0:0]BUFG_O;
input [0:0]BUFGCE_I;
input [0:0]BUFGCE_CE;
output [0:0]BUFGCE_O;
input [0:0]BUFH_I;
output [0:0]BUFH_O;
input [0:0]BUFHCE_I;
input [0:0]BUFHCE_CE;
output [0:0]BUFHCE_O;
input [0:0]BUFG_GT_I;
input [0:0]BUFG_GT_CE;
input [0:0]BUFG_GT_CEMASK;
input [0:0]BUFG_GT_CLR;
input [0:0]BUFG_GT_CLRMASK;
input [2:0]BUFG_GT_DIV;
output [0:0]BUFG_GT_O;
wire \<const0> ;
wire [0:0]BUFG_I;
wire [0:0]BUFG_O;
assign BUFGCE_O[0] = \<const0> ;
assign BUFG_GT_O[0] = \<const0> ;
assign BUFHCE_O[0] = \<const0> ;
assign BUFH_O[0] = \<const0> ;
assign IBUF_DS_ODIV2[0] = \<const0> ;
assign IBUF_OUT[0] = \<const0> ;
assign IOBUF_IO_O[0] = \<const0> ;
assign OBUF_DS_N[0] = \<const0> ;
assign OBUF_DS_P[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* box_type = "PRIMITIVE" *)
BUFG \USE_BUFG.GEN_BUFG[0].BUFG_U
(.I(BUFG_I),
.O(BUFG_O));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module wb_conbus_arb(
clk,
rst,
req,
gnt
);
input clk;
input rst;
input [ 1: 0] req; // Req input
output gnt; // Grant output
//input next; // Next Target
///////////////////////////////////////////////////////////////////////
//
// Parameters
//
parameter grant0 = 1'h0,
grant1 = 1'h1;
///////////////////////////////////////////////////////////////////////
//
// Local Registers and Wires
//
reg state = 0, next_state = 0;
///////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign gnt = state;
always@(posedge clk or posedge rst)
if(rst) state <= #1 grant0;
else state <= #1 next_state;
///////////////////////////////////////////////////////////////////////
//
// Next State Logic
// - implements round robin arbitration algorithm
// - switches grant if current req is dropped or next is asserted
// - parks at last grant
//
always@(state or req ) begin
next_state = state; // Default Keep State
case(state) // synopsys parallel_case full_case
grant0:
// if this req is dropped or next is asserted, check for other req's
if(!req[0] )
begin
if(req[1]) next_state = grant1;
/*
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
*/
end
grant1:
// if this req is dropped or next is asserted, check for other req's
if(!req[1] ) begin
/*
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
*/
if(req[0]) next_state = grant0;
end
/*
grant2:
// if this req is dropped or next is asserted, check for other req's
if(!req[2] ) begin
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
end
grant3:
// if this req is dropped or next is asserted, check for other req's
if(!req[3] ) begin
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
end
grant4:
// if this req is dropped or next is asserted, check for other req's
if(!req[4] ) begin
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
end
grant5:
// if this req is dropped or next is asserted, check for other req's
if(!req[5] ) begin
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
end
grant6:
// if this req is dropped or next is asserted, check for other req's
if(!req[6] ) begin
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
end
grant7:
// if this req is dropped or next is asserted, check for other req's
if(!req[7] ) begin
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
end*/
endcase
end
endmodule |
module sky130_fd_sc_hdll__probec_p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module sky130_fd_sc_ls__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module sata_command_layer (
input rst, //reset
input clk,
input data_in_clk,
input data_out_clk,
//User Interface
output sata_init,
output command_layer_ready,
output reg busy,
input send_sync_escape,
input [15:0] user_features,
//XXX: New Stb
input write_data_en,
input single_rdwr,
input read_data_en,
output dev_error,
input send_user_command_stb,
input soft_reset_en,
output reg pio_data_ready,
input [7:0] command,
input [15:0] sector_count,
input [47:0] sector_address,
input fifo_reset,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
//Transfer Layer Interface
input transport_layer_ready,
output reg sync_escape,
output t_send_command_stb,
output reg t_send_control_stb,
output t_send_data_stb,
input t_dma_activate_stb,
input t_d2h_reg_stb,
input t_pio_setup_stb,
input t_d2h_data_stb,
input t_dma_setup_stb,
input t_set_device_bits_stb,
input t_remote_abort,
input t_xmit_error,
input t_read_crc_error,
//PIO
input t_pio_response,
input t_pio_direction,
input [15:0] t_pio_transfer_count,
input [7:0] t_pio_e_status,
//Host to Device Register Values
output [7:0] h2d_command,
output reg [15:0] h2d_features,
output [7:0] h2d_control,
output [3:0] h2d_port_mult,
output [7:0] h2d_device,
output [47:0] h2d_lba,
output [15:0] h2d_sector_count,
//Device to Host Register Values
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
//command layer data interface
input t_if_strobe,
output [31:0] t_if_data,
output t_if_ready,
input t_if_activate,
output [23:0] t_if_size,
input t_of_strobe,
input [31:0] t_of_data,
output [1:0] t_of_ready,
input [1:0] t_of_activate,
output [23:0] t_of_size,
//Debug
output [3:0] cl_c_state,
output [3:0] cl_w_state,
output [3:0] cl_r_state
);
//Parameters
parameter IDLE = 4'h0;
parameter PIO_WAIT_FOR_DATA = 4'h1;
parameter PIO_WRITE_DATA = 4'h2;
parameter WAIT_FOR_DATA = 4'h1;
parameter WAIT_FOR_DMA_ACT = 4'h1;
parameter WAIT_FOR_WRITE_DATA = 4'h2;
parameter SEND_DATA = 4'h3;
parameter WAIT_FOR_STATUS = 4'h4;
//Registers/Wires
reg [3:0] cntrl_state;
reg srst;
reg [7:0] status;
wire idle;
reg cntrl_send_data_stb;
reg send_command_stb;
reg prev_send_command;
wire dev_busy;
wire dev_data_req;
reg [31:0] reset_count;
wire reset_timeout;
//Read State Machine
reg [3:0] read_state;
reg read_data_stb;
reg single_read_prev;
//Write State Machine
reg [3:0] write_state;
reg write_data_stb;
reg single_write_prev;
reg dma_send_data_stb;
reg dma_act_detected;
wire write_data_available;
reg first_write;
reg first_read;
reg enable_tl_data_ready;
//Ping Pong FIFOs
wire [1:0] if_write_ready;
wire [1:0] if_write_activate;
wire [23:0] if_write_size;
wire if_write_strobe;
wire if_starved;
wire [31:0] if_write_data;
wire if_read_strobe;
wire if_read_ready;
wire if_read_activate;
wire [23:0] if_read_size;
wire [31:0] if_read_data;
wire [31:0] of_write_data;
wire [1:0] of_write_ready;
wire [1:0] of_write_activate;
wire [23:0] of_read_size;
wire of_write_strobe;
wire out_fifo_starved;
wire of_read_ready;
wire [31:0] of_read_data;
wire of_read_activate;
wire [23:0] of_write_size;
wire of_read_strobe;
//XXX: There is a bug in the PPFIFO in that the FPGA code the FIFO cannot be filled up
//Submodules
//ping pong FIFO
//Input FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH + 1)
) fifo_in (
.reset (rst || fifo_reset ),
//write side
//XXX: This can be different clocks
.write_clock (data_in_clk ),
.write_data (if_write_data ),
.write_ready (if_write_ready ),
.write_activate (if_write_activate ),
.write_fifo_size (if_write_size ),
.write_strobe (if_write_strobe ),
.starved (if_starved ),
//read side
//XXX: This can be different clocks
.read_clock (clk ),
.read_strobe (if_read_strobe ),
.read_ready (if_read_ready ),
.read_activate (if_read_activate ),
.read_count (if_read_size ),
.read_data (if_read_data )
);
//Output FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH + 1)
) fifo_out (
.reset (rst ),
//write side
//XXX: This can be different clocks
.write_clock (clk ),
.write_data (of_write_data ),
.write_ready (of_write_ready ),
.write_activate (of_write_activate ),
.write_fifo_size (of_write_size ),
.write_strobe (of_write_strobe ),
.starved (out_fifo_starved ),
//read side
//XXX: This can be different clocks
.read_clock (data_out_clk ),
.read_strobe (of_read_strobe ),
.read_ready (of_read_ready ),
.read_activate (of_read_activate ),
.read_count (of_read_size ),
.read_data (of_read_data )
);
//Asynchronous Logic
//Attach output of Input FIFO to TL
assign t_if_ready = if_read_ready && enable_tl_data_ready;
assign t_if_size = if_read_size;
assign t_if_data = if_read_data;
assign if_read_activate = t_if_activate;
assign if_read_strobe = t_if_strobe;
//Attach input of output FIFO to TL
assign t_of_ready = of_write_ready;
//assign t_of_size = of_write_size;
assign t_of_size = 24'h00800;
assign of_write_data = t_of_data;
assign of_write_activate = t_of_activate;
assign of_write_strobe = t_of_strobe;
assign if_write_data = user_din;
assign if_write_strobe = user_din_stb;
assign user_din_ready = if_write_ready;
assign if_write_activate = user_din_activate;
//assign user_din_size = if_write_size;
assign user_din_size = 24'h00800;
//assign user_din_size = 24'h00400;
//assign user_din_size = 24'h00200;
assign user_dout = of_read_data;
assign user_dout_ready = of_read_ready;
assign of_read_activate = user_dout_activate;
assign user_dout_size = of_read_size;
assign of_read_strobe = user_dout_stb;
assign write_data_available = (if_read_ready || if_read_activate) || (if_write_ready != 2'b11);
//Strobes
assign t_send_command_stb = read_data_stb || write_data_stb || send_command_stb;
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
//IDLE
assign idle = (cntrl_state == IDLE) &&
(read_state == IDLE) &&
(write_state == IDLE) &&
transport_layer_ready;
assign command_layer_ready = idle;
assign sata_init = reset_timeout;
assign h2d_command = (write_data_en) ? `COMMAND_DMA_WRITE_EX :
(read_data_en) ? `COMMAND_DMA_READ_EX :
(send_user_command_stb) ? command :
h2d_command;
assign h2d_sector_count = sector_count;
assign h2d_lba = (write_data_en) ? (!single_rdwr && !first_write) ? d2h_lba + 1 : sector_address :
(read_data_en) ? (!single_rdwr && !first_read) ? d2h_lba + 1 : sector_address :
sector_address;
//XXX: The individual bits should be controlled directly
assign h2d_control = {5'h00, srst, 2'b00};
//XXX: This should be controlled from a higher level
assign h2d_port_mult = 4'h0;
//XXX: This should be controlled from a higher level
assign h2d_device = `D2H_REG_DEVICE;
assign dev_busy = status[`STATUS_BUSY_BIT];
assign dev_data_req = status[`STATUS_DRQ_BIT];
assign dev_error = status[`STATUS_ERR_BIT];
assign cl_c_state = cntrl_state;
assign cl_r_state = read_state;
assign cl_w_state = write_state;
assign reset_timeout = (reset_count >= `RESET_TIMEOUT);
//Synchronous Logic
//Control State Machine
always @ (posedge clk) begin
if (rst) begin
cntrl_state <= IDLE;
h2d_features <= `D2H_REG_FEATURES;
srst <= 0;
//Strobes
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
status <= 0;
prev_send_command <= 0;
send_command_stb <= 0;
reset_count <= 0;
busy <= 1;
end
else begin
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
send_command_stb <= 0;
//Reset Count
if (reset_count < `RESET_TIMEOUT) begin
reset_count <= reset_count + 1;
end
if (fifo_reset) begin
reset_count <= 0;
end
if (!reset_timeout) begin
cntrl_state <= IDLE;
end
//detected the first a user attempting to send a command
if (send_user_command_stb && !prev_send_command) begin
prev_send_command <= 1;
send_command_stb <= 1;
end
if (!send_user_command_stb) begin
prev_send_command <= 0;
end
if (t_d2h_reg_stb) begin
busy <= 0;
h2d_features <= `D2H_REG_FEATURES;
end
if (t_send_command_stb || t_send_control_stb || send_user_command_stb) begin
busy <= 1;
if (send_user_command_stb) begin
h2d_features <= user_features;
end
end
case (cntrl_state)
IDLE: begin
//Soft Reset will break out of any flow
if ((soft_reset_en) && !srst) begin
srst <= 1;
t_send_control_stb <= 1;
reset_count <= 0;
end
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//User Initiated commands
if (!soft_reset_en && srst && reset_timeout) begin
srst <= 0;
t_send_control_stb <= 1;
end
end
//Device Initiated Transfers
if(t_pio_setup_stb) begin
if (t_pio_direction) begin
//Read from device
cntrl_state <= PIO_WAIT_FOR_DATA;
end
else begin
//Write to device
cntrl_state <= PIO_WRITE_DATA;
end
end
if (t_set_device_bits_stb) begin
status <= d2h_status;
//status register was updated
end
if (t_d2h_reg_stb) begin
status <= d2h_status;
end
end
PIO_WAIT_FOR_DATA: begin
if (t_d2h_data_stb) begin
//the next peice of data is related to the PIO
pio_data_ready <= 1;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
PIO_WRITE_DATA: begin
if (if_read_activate) begin
cntrl_send_data_stb <= 0;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
default: begin
cntrl_state <= IDLE;
end
endcase
if (send_sync_escape) begin
cntrl_state <= IDLE;
busy <= 0;
end
end
end
//Read State Machine
always @ (posedge clk) begin
if (rst) begin
read_state <= IDLE;
sync_escape <= 0;
read_data_stb <= 0;
single_read_prev <= 0;
first_read <= 1;
end
else begin
read_data_stb <= 0;
sync_escape <= 0;
if (!read_data_en) begin
single_read_prev <= 0;
end
case (read_state)
IDLE: begin
if (idle) begin
sync_escape <= 0;
//The only way to transition to another state is if CL is IDLE
if (read_data_en) begin
if (single_rdwr) begin
if (!single_read_prev) begin
single_read_prev <= 1;
read_data_stb <= 1;
read_state <= WAIT_FOR_DATA;
end
end
else begin
//send a request to read data
read_data_stb <= 1;
read_state <= WAIT_FOR_DATA;
end
end
else begin
first_read <= 1;
end
end
end
WAIT_FOR_DATA: begin
//This state seems useless because it only sets a value but the state is used to indicate the system is idle or not
if (t_d2h_data_stb) begin
first_read <= 0;
end
/*
if (soft_reset_en) begin
//XXX: Issue a SYNC ESCAPE to cancel a large read request otherwise let it play out
//sync_escape <= 1;
end
*/
end
default: begin
read_state <= IDLE;
end
endcase
if (soft_reset_en || !reset_timeout || send_sync_escape) begin
if (read_state != IDLE) begin
sync_escape <= 1;
end
if (send_sync_escape) begin
sync_escape <= 1;
end
read_state <= IDLE;
end
//If this is received go back to IDLE
if (t_d2h_reg_stb) begin
read_state <= IDLE;
end
end
end
//Write State Machine
always @ (posedge clk) begin
if (rst) begin
write_state <= IDLE;
dma_send_data_stb <= 0;
write_data_stb <= 0;
single_write_prev <= 0;
first_write <= 1;
enable_tl_data_ready <= 0;
dma_act_detected <= 0;
end
else begin
dma_send_data_stb <= 0;
write_data_stb <= 0;
if (enable_tl_data_ready && if_read_activate) begin
//Closes the loop on the data write feedback
enable_tl_data_ready <= 0;
end
if (!write_data_en) begin
single_write_prev <= 0;
end
if (t_dma_activate_stb) begin
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
dma_act_detected <= 1;
end
case (write_state)
IDLE: begin
if (idle) begin
//The only way to transition to another state is if CL is IDLE
if (write_data_en) begin
if (single_rdwr) begin
if (!single_write_prev) begin
single_write_prev <= 1;
write_state <= WAIT_FOR_DMA_ACT;
write_data_stb <= 1;
end
end
else begin
//send a request to write data
write_state <= WAIT_FOR_DMA_ACT;
write_data_stb <= 1;
end
end
else begin
//reset the the first write when the user deassertes the write_data_en
first_write <= 1;
end
end
end
WAIT_FOR_DMA_ACT: begin
if (dma_act_detected) begin
dma_act_detected <= 0;
first_write <= 0;
enable_tl_data_ready <= 1;
write_state <= WAIT_FOR_WRITE_DATA;
end
end
WAIT_FOR_WRITE_DATA: begin
if (if_read_activate) begin
write_state <= SEND_DATA;
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
//Send the Data FIS
dma_send_data_stb <= 1;
write_state <= WAIT_FOR_DMA_ACT;
end
end
WAIT_FOR_STATUS: begin
if (t_d2h_reg_stb) begin
write_state <= IDLE;
end
end
default: begin
write_state <= IDLE;
end
endcase
if (soft_reset_en || !reset_timeout) begin
//Break out of the normal flow and return to IDLE
write_state <= IDLE;
end
if (t_d2h_reg_stb) begin
//Whenever I read a register transfer from the device I need to go back to IDLE
write_state <= IDLE;
end
if (send_sync_escape) begin
write_state <= IDLE;
end
end
end
endmodule |
module hw_dbg (
input clk,
input rst_lck,
output reg rst,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
// Wishbone master interface for the VDU
output reg [15:0] vdu_dat_o,
output reg [11:1] vdu_adr_o,
output vdu_we_o,
output vdu_stb_o,
output [ 1:0] vdu_sel_o,
output reg vdu_tga_o,
input vdu_ack_i,
// Wishbone master interface for the ZBT SRAM
input [15:0] zbt_dat_i,
output [19:1] zbt_adr_o,
output zbt_we_o,
output [ 1:0] zbt_sel_o,
output reg zbt_stb_o,
input zbt_ack_i
);
// Registers and nets
reg [ 5:0] st;
reg op;
reg [ 6:0] cur;
reg mr, ml, md, mu, dm;
reg br, bl, bd, bu, bc;
reg [15:0] cnt;
reg [ 4:0] i;
reg [19:0] adr;
reg [ 2:0] sp;
reg [15:0] col;
reg [ 3:0] nibb;
reg [ 7:0] low_adr;
wire [7:0] o;
wire cur_dump;
wire action;
wire [2:0] off;
wire [3:0] nib, inc_nib, dec_nib;
wire up_down;
wire left_right;
wire spg;
// Module instantiations
init_msg msg0 (
.i (i),
.o (o)
);
inc i0 (
.i (nib),
.o (inc_nib)
);
dec d0 (
.i (nib),
.o (dec_nib)
);
// Continuous assignments
assign vdu_we_o = op;
assign vdu_stb_o = op;
assign vdu_sel_o = 2'b11;
assign zbt_we_o = 1'b0;
assign zbt_sel_o = 2'b11;
assign cur_dump = (cur < 7'd25 && cur > 7'd19);
assign off = cur - 7'd20;
assign nib = off==3'd0 ? adr[19:16]
: (off==3'd1 ? adr[15:12]
: (off==3'd2 ? adr[11:8]
: (off==3'd3 ? adr[7:4] : adr[3:0])));
assign left_right = mr | ml;
assign up_down = mu | md;
assign action = left_right | up_down | dm;
assign spg = sp>3'b0;
assign zbt_adr_o = { adr[19:5] + low_adr[7:4], low_adr[3:0] };
// Behaviour
always @(posedge clk)
if (rst_lck)
begin
vdu_dat_o <= 16'd12;
vdu_adr_o <= 11'h4;
vdu_tga_o <= 1'b1;
st <= 6'd0;
op <= 1'b1;
i <= 4'h0;
zbt_stb_o <= 1'b0;
end
else
case (st)
6'd0: if (vdu_ack_i) begin
vdu_dat_o <= { 8'h06, o };
vdu_adr_o <= i + 5'h4;
vdu_tga_o <= 1'b0;
st <= (i==5'd21) ? 6'h2 : 6'h1;
op <= 1'b0;
i <= i + 5'h1;
end
6'd1: if (!vdu_ack_i) begin
st <= 6'h0;
op <= 1'b1;
i <= i;
end
6'd2: // main wait state
if (!vdu_ack_i && action) begin
vdu_dat_o <= mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1)
: ((ml && cur==7'd20) ? 7'd15 : cur - 7'b1);
vdu_adr_o <= 11'h0;
vdu_tga_o <= 1'b1;
st <= left_right ? 6'h3 : (dm ? 6'h5 : 6'h4);
op <= left_right;
col <= 16'd80;
sp <= 2'h3;
nibb <= 4'h0;
end
6'd3: if (vdu_ack_i) begin
vdu_dat_o <= 16'h0;
vdu_adr_o <= 11'h0;
vdu_tga_o <= 1'b1;
st <= 6'h2;
op <= 1'b0;
end
6'd4: // redraw the mem_dump counter
if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h03, itoa(nib) };
vdu_adr_o <= cur;
vdu_tga_o <= 1'b0;
st <= 6'h3;
op <= 1'b1;
end
6'd5: // memory dump
if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h05, spg ? 8'h20 : itoa(nibb) };
vdu_adr_o <= col;
vdu_tga_o <= 1'b0;
st <= 6'h6;
op <= 1'b1;
sp <= spg ? (sp - 3'b1) : 3'd4;
col <= col + 16'd1;
nibb <= spg ? nibb : (nibb + 4'h2);
end
6'd6: if (vdu_ack_i) begin
st <= (col==16'd160) ? 6'h7 : 6'h5;
op <= 1'b0;
end
6'd7: begin
low_adr <= 8'h0;
st <= 6'h8;
end
6'd8: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h5, itoa(zbt_adr_o[7:4]) };
vdu_adr_o <= col;
st <= 6'd9;
op <= 1'b1;
end
6'd9: if (vdu_ack_i) begin
st <= 6'd10;
op <= 1'b0;
col <= col + 16'd1;
end
6'd10: if (!zbt_ack_i) begin
st <= 6'd11;
zbt_stb_o <= 1'b1;
end
6'd11: if (zbt_ack_i) begin
st <= 6'd12;
zbt_stb_o <= 1'b0;
end
6'd12: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[15:12]) };
vdu_adr_o <= col;
st <= 6'd13;
op <= 1'b1;
end
6'd13: if (vdu_ack_i) begin
st <= 6'd14;
op <= 1'b0;
col <= col + 16'd1;
end
6'd14: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[11:8]) };
vdu_adr_o <= col;
st <= 6'd15;
op <= 1'b1;
end
6'd15: if (vdu_ack_i) begin
st <= 6'd16;
op <= 1'b0;
col <= col + 16'd1;
end
6'd16: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[7:4]) };
vdu_adr_o <= col;
st <= 6'd17;
op <= 1'b1;
end
6'd17: if (vdu_ack_i) begin
st <= 6'd18;
op <= 1'b0;
col <= col + 16'd1;
end
6'd18: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[3:0]) };
vdu_adr_o <= col;
st <= 6'd19;
op <= 1'b1;
end
6'd19: if (vdu_ack_i) begin
st <= (zbt_adr_o[4:1]==4'hf) ? 6'd22 : 6'd20;
op <= 1'b0;
col <= col + 16'd1;
low_adr <= low_adr + 8'h1;
end
6'd20: if (!vdu_ack_i) begin
vdu_dat_o <= 16'h0720;
vdu_adr_o <= col;
st <= 6'd21;
op <= 1'b1;
end
6'd21: if (vdu_ack_i) begin
st <= 6'd10;
op <= 1'b0;
col <= col + 16'd1;
end
6'd22: st <= (low_adr==8'h0) ? 6'd2 : 6'd8;
endcase
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : ((butc_ && cur==7'd12) ? 1'b0 : rst);
// cur
always @(posedge clk)
cur <= rst_lck ? 7'd12 : (mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1)
: (ml ? (cur==7'd20 ? 7'd15 : cur - 7'b1) : cur));
// adr
always @(posedge clk)
adr <= rst_lck ? 16'h0
: (mu ? (off==3'd0 ? { inc_nib, adr[15:0] }
: (off==3'd1 ? { adr[19:16], inc_nib, adr[11:0] }
: (off==3'd2 ? { adr[19:12], inc_nib, adr[7:0] }
: (off==3'd3 ? { adr[19:8], inc_nib, adr[3:0] }
: { adr[19:4], inc_nib }))))
: (md ? (off==3'd0 ? { dec_nib, adr[15:0] }
: (off==3'd1 ? { adr[19:16], dec_nib, adr[11:0] }
: (off==3'd2 ? { adr[19:12], dec_nib, adr[7:0] }
: (off==3'd3 ? { adr[19:8], dec_nib, adr[3:0] }
: { adr[19:4], dec_nib })))) : adr));
// mr - move right
always @(posedge clk)
mr <= rst_lck ? 1'b0 : (bute_ && !br
&& cnt==16'h0 && cur != 7'd24);
// br - button right
always @(posedge clk) br <= (cnt==16'h0 ? bute_ : br);
// ml - move right
always @(posedge clk)
ml <= rst_lck ? 1'b0 : (butw_ && !bl
&& cnt==16'h0 && cur != 7'd12);
// bl - button right
always @(posedge clk) bl <= (cnt==16'h0 ? butw_ : bl);
// md - move down
always @(posedge clk)
md <= rst_lck ? 1'b0 : (buts_ && !bd && cnt==16'h0 && cur_dump);
// bd - button down
always @(posedge clk) bd <= (cnt==16'h0 ? buts_ : bd);
// mu - move up
always @(posedge clk)
mu <= rst_lck ? 1'b0 : (butn_ && !bu && cnt==16'h0 && cur_dump);
// bu - button up
always @(posedge clk) bu <= (cnt==16'h0 ? butn_ : bu);
// dm - dump
always @(posedge clk)
dm <= rst_lck ? 1'b0 : (butc_ && !bc && cur==7'd13);
// bc - center button
always @(posedge clk) bc <= (cnt==16'h0 ? butc_ : bc);
// cnt - button counter
always @(posedge clk) cnt <= cnt + 1'b1;
function [7:0] itoa;
input [3:0] i;
begin
if (i < 8'd10) itoa = i + 8'h30;
else itoa = i + 8'h57;
end
endfunction
endmodule |
module init_msg (
input [4:0] i,
output reg [7:0] o
);
// Behaviour
always @(i)
case (i)
5'h00: o <= 8'h68; // h
5'h01: o <= 8'h77; // w
5'h02: o <= 8'h5f; // _
5'h03: o <= 8'h64; // d
5'h04: o <= 8'h62; // b
5'h05: o <= 8'h67; // g
5'h06: o <= 8'h20; //
5'h07: o <= 8'h5b; // [
5'h08: o <= 8'h43; // C
5'h09: o <= 8'h44; // D
5'h0a: o <= 8'h57; // W
5'h0b: o <= 8'h42; // B
5'h0c: o <= 8'h5d; // ]
5'h0d: o <= 8'h20; //
5'h0f: o <= 8'h78; // x
default: o <= 8'h30; // 0
endcase
endmodule |
module inc (
input [3:0] i,
output reg [3:0] o
);
// Behaviour
always @(i)
case (i)
4'h0: o <= 4'h1;
4'h1: o <= 4'h2;
4'h2: o <= 4'h3;
4'h3: o <= 4'h4;
4'h4: o <= 4'h5;
4'h5: o <= 4'h6;
4'h6: o <= 4'h7;
4'h7: o <= 4'h8;
4'h8: o <= 4'h9;
4'h9: o <= 4'ha;
4'ha: o <= 4'hb;
4'hb: o <= 4'hc;
4'hc: o <= 4'hd;
4'hd: o <= 4'he;
4'he: o <= 4'hf;
default: o <= 4'h0;
endcase
endmodule |
module dec (
input [3:0] i,
output reg [3:0] o
);
// Behaviour
always @(i)
case (i)
4'h0: o <= 4'hf;
4'h1: o <= 4'h0;
4'h2: o <= 4'h1;
4'h3: o <= 4'h2;
4'h4: o <= 4'h3;
4'h5: o <= 4'h4;
4'h6: o <= 4'h5;
4'h7: o <= 4'h6;
4'h8: o <= 4'h7;
4'h9: o <= 4'h8;
4'ha: o <= 4'h9;
4'hb: o <= 4'ha;
4'hc: o <= 4'hb;
4'hd: o <= 4'hc;
4'he: o <= 4'hd;
default: o <= 4'he;
endcase
endmodule |
module test_axis_frame_join_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 8'd0;
reg input_0_axis_tvalid = 1'b0;
reg input_0_axis_tlast = 1'b0;
reg input_0_axis_tuser = 1'b0;
reg [7:0] input_1_axis_tdata = 8'd0;
reg input_1_axis_tvalid = 1'b0;
reg input_1_axis_tlast = 1'b0;
reg input_1_axis_tuser = 1'b0;
reg [7:0] input_2_axis_tdata = 8'd0;
reg input_2_axis_tvalid = 1'b0;
reg input_2_axis_tlast = 1'b0;
reg input_2_axis_tuser = 1'b0;
reg [7:0] input_3_axis_tdata = 8'd0;
reg input_3_axis_tvalid = 1'b0;
reg input_3_axis_tlast = 1'b0;
reg input_3_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [15:0] tag = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
tag);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
// dump file
$dumpfile("test_axis_frame_join_4.lxt");
$dumpvars(0, test_axis_frame_join_4);
end
axis_frame_join_4 #(
.TAG_ENABLE(1)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// config
.tag(tag),
// status
.busy(busy)
);
endmodule |
module bw_io_cmos_edgelogic(
// Outputs
to_core, por, pad_up, bsr_up, pad_dn_l, bsr_dn_l,
// Inputs
data, oe, bsr_mode, por_l,
bsr_data_to_core, se, rcvr_data
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
input data;
input oe;
input bsr_mode;
input por_l;
input se;
input bsr_data_to_core;
input rcvr_data;
supply0 vss;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
output pad_up;
output pad_dn_l;
output bsr_up;
output bsr_dn_l;
output por;
output to_core;
// WIRES
wire pad_up;
wire pad_dn_l;
wire bsr_up;
wire bsr_dn_l;
wire por;
wire to_core;
//always
//begin
// bsr_up = pad_up;
// bsr_dn_l = pad_dn_l;
// por = ~por_l;
// pad_up = data && oe;
// pad_dn_l = ~(~data && oe);
// to_core = (bsr_mode && !se) ? bsr_data_to_core : rcvr_data;
//end
assign bsr_up = pad_up;
assign bsr_dn_l = pad_dn_l;
assign por = ~por_l;
assign pad_up = data && oe;
assign pad_dn_l = ~(~data && oe);
assign to_core = (bsr_mode && !se) ? bsr_data_to_core : rcvr_data;
endmodule |
module sky130_fd_sc_hs__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule |
module top(
input i_ce,
input i_clk,
input i_d1,
input i_d2,
input i_rst,
output [23:0] io
);
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1;
wire [0:0] LIOB33_X0Y21_IOB_X0Y22_O;
wire [0:0] LIOB33_X0Y23_IOB_X0Y23_O;
wire [0:0] LIOB33_X0Y23_IOB_X0Y24_O;
wire [0:0] LIOB33_X0Y25_IOB_X0Y25_O;
wire [0:0] LIOB33_X0Y25_IOB_X0Y26_O;
wire [0:0] LIOB33_X0Y27_IOB_X0Y27_O;
wire [0:0] LIOB33_X0Y27_IOB_X0Y28_O;
wire [0:0] LIOB33_X0Y29_IOB_X0Y29_O;
wire [0:0] LIOB33_X0Y29_IOB_X0Y30_O;
wire [0:0] LIOB33_X0Y31_IOB_X0Y31_O;
wire [0:0] LIOB33_X0Y31_IOB_X0Y32_O;
wire [0:0] LIOB33_X0Y33_IOB_X0Y33_O;
wire [0:0] LIOB33_X0Y33_IOB_X0Y34_O;
wire [0:0] LIOB33_X0Y35_IOB_X0Y35_O;
wire [0:0] LIOB33_X0Y35_IOB_X0Y36_O;
wire [0:0] LIOB33_X0Y37_IOB_X0Y37_O;
wire [0:0] LIOB33_X0Y37_IOB_X0Y38_O;
wire [0:0] LIOB33_X0Y39_IOB_X0Y39_O;
wire [0:0] LIOB33_X0Y39_IOB_X0Y40_O;
wire [0:0] LIOB33_X0Y41_IOB_X0Y41_O;
wire [0:0] LIOB33_X0Y41_IOB_X0Y42_O;
wire [0:0] LIOB33_X0Y43_IOB_X0Y43_O;
wire [0:0] LIOB33_X0Y45_IOB_X0Y45_O;
wire [0:0] LIOB33_X0Y45_IOB_X0Y46_O;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D2;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OCE;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_SR;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D2;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OCE;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_SR;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D2;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OCE;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_SR;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OCE;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_T1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_TQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OCE;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_T1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_TQ;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_CLK;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_D1;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_D2;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_OCE;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_OQ;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_SR;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_T1;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_TQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_CLK;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_D1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_D2;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_OCE;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_OQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_SR;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_T1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_TQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_CLK;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_D1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_D2;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_OCE;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_OQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_SR;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_T1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_TQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_CLK;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_D1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_D2;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_OCE;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_OQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_SR;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_T1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_TQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_CLK;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_D1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_D2;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_OCE;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_OQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_SR;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_T1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_TQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_CLK;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_D1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_D2;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_OCE;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_OQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_SR;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_T1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_TQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_CLK;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_D1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_D2;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_OCE;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_OQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_SR;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_T1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_TQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_CLK;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_D1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_D2;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_OCE;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_OQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_SR;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_T1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_TQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_CLK;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_D1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_D2;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_OCE;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_OQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_SR;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_T1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_TQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_CLK;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_D1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_D2;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_OCE;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_OQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_SR;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_T1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_TQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_CLK;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_D1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_D2;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_OCE;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_OQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_SR;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_T1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_TQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_CLK;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_D1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_D2;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_OCE;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_OQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_SR;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_T1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_TQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_CLK;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_D1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_D2;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_OCE;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_OQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_SR;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_T1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_TQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_CLK;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_D1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_D2;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_OCE;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_OQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_SR;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_T1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_TQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_CLK;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_D1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_D2;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_OCE;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_OQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_SR;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_T1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_TQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_CLK;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_D1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_D2;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_OCE;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_OQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_SR;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_T1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_TQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_CLK;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_D1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_D2;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_OCE;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_OQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_SR;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_T1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_TQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_CLK;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_D1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_D2;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_OCE;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_OQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_SR;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_T1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_TQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_CLK;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_D1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_D2;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_OCE;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_OQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_SR;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_T1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_TQ;
wire [0:0] RIOB33_X43Y25_IOB_X1Y26_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y43_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y44_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y45_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y46_I;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_D;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_O;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_D;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_O;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_D;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_O;
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(RIOB33_X43Y25_IOB_X1Y26_I),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y21_IOB_X0Y22_OBUF (
.I(LIOI3_X0Y21_OLOGIC_X0Y22_OQ),
.O(io[23])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y23_IOB_X0Y23_OBUF (
.I(LIOI3_X0Y23_OLOGIC_X0Y23_OQ),
.O(io[22])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y23_IOB_X0Y24_OBUF (
.I(LIOI3_X0Y23_OLOGIC_X0Y24_OQ),
.O(io[21])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y25_IOB_X0Y25_OBUF (
.I(LIOI3_X0Y25_OLOGIC_X0Y25_OQ),
.O(io[20])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y25_IOB_X0Y26_OBUF (
.I(LIOI3_X0Y25_OLOGIC_X0Y26_OQ),
.O(io[19])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y27_IOB_X0Y27_OBUF (
.I(LIOI3_X0Y27_OLOGIC_X0Y27_OQ),
.O(io[18])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y27_IOB_X0Y28_OBUF (
.I(LIOI3_X0Y27_OLOGIC_X0Y28_OQ),
.O(io[17])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y29_IOB_X0Y29_OBUF (
.I(LIOI3_X0Y29_OLOGIC_X0Y29_OQ),
.O(io[16])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y29_IOB_X0Y30_OBUF (
.I(LIOI3_X0Y29_OLOGIC_X0Y30_OQ),
.O(io[15])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y31_IOB_X0Y31_OBUF (
.I(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ),
.O(io[14])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y31_IOB_X0Y32_OBUF (
.I(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ),
.O(io[13])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y33_IOB_X0Y33_OBUF (
.I(LIOI3_X0Y33_OLOGIC_X0Y33_OQ),
.O(io[12])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y33_IOB_X0Y34_OBUF (
.I(LIOI3_X0Y33_OLOGIC_X0Y34_OQ),
.O(io[11])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y35_IOB_X0Y35_OBUF (
.I(LIOI3_X0Y35_OLOGIC_X0Y35_OQ),
.O(io[10])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y35_IOB_X0Y36_OBUF (
.I(LIOI3_X0Y35_OLOGIC_X0Y36_OQ),
.O(io[9])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y37_IOB_X0Y37_OBUF (
.I(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ),
.O(io[8])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y37_IOB_X0Y38_OBUF (
.I(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ),
.O(io[7])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y39_IOB_X0Y39_OBUF (
.I(LIOI3_X0Y39_OLOGIC_X0Y39_OQ),
.O(io[6])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y39_IOB_X0Y40_OBUF (
.I(LIOI3_X0Y39_OLOGIC_X0Y40_OQ),
.O(io[5])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y41_IOB_X0Y41_OBUF (
.I(LIOI3_X0Y41_OLOGIC_X0Y41_OQ),
.O(io[4])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y41_IOB_X0Y42_OBUF (
.I(LIOI3_X0Y41_OLOGIC_X0Y42_OQ),
.O(io[3])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y43_IOB_X0Y43_OBUF (
.I(LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ),
.O(io[2])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y45_IOB_X0Y45_OBUF (
.I(LIOI3_X0Y45_OLOGIC_X0Y45_OQ),
.O(io[1])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y45_IOB_X0Y46_OBUF (
.I(LIOI3_X0Y45_OLOGIC_X0Y46_OQ),
.O(io[0])
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y21_OLOGIC_X0Y22_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y21_OLOGIC_X0Y22_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y23_OLOGIC_X0Y24_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y23_OLOGIC_X0Y24_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y23_OLOGIC_X0Y23_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y23_OLOGIC_X0Y23_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y25_OLOGIC_X0Y26_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y25_OLOGIC_X0Y26_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y25_OLOGIC_X0Y25_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y25_OLOGIC_X0Y25_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y27_OLOGIC_X0Y28_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y27_OLOGIC_X0Y28_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y27_OLOGIC_X0Y27_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y27_OLOGIC_X0Y27_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y29_OLOGIC_X0Y30_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y29_OLOGIC_X0Y30_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y29_OLOGIC_X0Y29_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y29_OLOGIC_X0Y29_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y33_OLOGIC_X0Y34_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y33_OLOGIC_X0Y34_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y33_OLOGIC_X0Y33_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y33_OLOGIC_X0Y33_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y35_OLOGIC_X0Y36_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y35_OLOGIC_X0Y36_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y35_OLOGIC_X0Y35_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y35_OLOGIC_X0Y35_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y39_OLOGIC_X0Y40_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y39_OLOGIC_X0Y40_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y39_OLOGIC_X0Y39_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y39_OLOGIC_X0Y39_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y41_OLOGIC_X0Y42_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y41_OLOGIC_X0Y42_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y41_OLOGIC_X0Y41_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y41_OLOGIC_X0Y41_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y45_OLOGIC_X0Y46_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y45_OLOGIC_X0Y46_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y45_OLOGIC_X0Y45_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y45_OLOGIC_X0Y45_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y25_IOB_X1Y26_IBUF (
.I(i_clk),
.O(RIOB33_X43Y25_IOB_X1Y26_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y43_IOB_X1Y43_IBUF (
.I(i_d2),
.O(RIOB33_X43Y43_IOB_X1Y43_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y43_IOB_X1Y44_IBUF (
.I(i_d1),
.O(RIOB33_X43Y43_IOB_X1Y44_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y45_IBUF (
.I(i_ce),
.O(RIOB33_X43Y45_IOB_X1Y45_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y46_IBUF (
.I(i_rst),
.O(RIOB33_X43Y45_IOB_X1Y46_I)
);
assign LIOI3_X0Y21_OLOGIC_X0Y22_TQ = 1'b1;
assign LIOI3_X0Y23_OLOGIC_X0Y24_TQ = 1'b1;
assign LIOI3_X0Y23_OLOGIC_X0Y23_TQ = 1'b1;
assign LIOI3_X0Y25_OLOGIC_X0Y26_TQ = 1'b1;
assign LIOI3_X0Y25_OLOGIC_X0Y25_TQ = 1'b1;
assign LIOI3_X0Y27_OLOGIC_X0Y28_TQ = 1'b1;
assign LIOI3_X0Y27_OLOGIC_X0Y27_TQ = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y30_TQ = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y29_TQ = 1'b1;
assign LIOI3_X0Y33_OLOGIC_X0Y34_TQ = 1'b1;
assign LIOI3_X0Y33_OLOGIC_X0Y33_TQ = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y36_TQ = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y35_TQ = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y40_TQ = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y39_TQ = 1'b1;
assign LIOI3_X0Y41_OLOGIC_X0Y42_TQ = 1'b1;
assign LIOI3_X0Y41_OLOGIC_X0Y41_TQ = 1'b1;
assign LIOI3_X0Y45_OLOGIC_X0Y46_TQ = 1'b1;
assign LIOI3_X0Y45_OLOGIC_X0Y45_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_TQ = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_TQ = 1'b1;
assign RIOI3_X43Y25_ILOGIC_X1Y26_O = RIOB33_X43Y25_IOB_X1Y26_I;
assign RIOI3_X43Y45_ILOGIC_X1Y46_O = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_O = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_O = RIOB33_X43Y43_IOB_X1Y44_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_O = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y37_IOB_X0Y38_O = LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ;
assign LIOB33_X0Y37_IOB_X0Y37_O = LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_SR = 1'b0;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_SR = 1'b0;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_T1 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_T1 = 1'b1;
assign LIOI3_X0Y41_OLOGIC_X0Y42_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_T1 = 1'b1;
assign LIOB33_X0Y41_IOB_X0Y42_O = LIOI3_X0Y41_OLOGIC_X0Y42_OQ;
assign LIOB33_X0Y41_IOB_X0Y41_O = LIOI3_X0Y41_OLOGIC_X0Y41_OQ;
assign LIOI3_X0Y41_OLOGIC_X0Y41_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y41_OLOGIC_X0Y41_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y23_IOB_X0Y24_O = LIOI3_X0Y23_OLOGIC_X0Y24_OQ;
assign LIOB33_X0Y23_IOB_X0Y23_O = LIOI3_X0Y23_OLOGIC_X0Y23_OQ;
assign LIOI3_X0Y41_OLOGIC_X0Y41_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y41_OLOGIC_X0Y41_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y41_OLOGIC_X0Y41_T1 = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y36_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_T1 = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y35_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y35_OLOGIC_X0Y35_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y45_IOB_X0Y46_O = LIOI3_X0Y45_OLOGIC_X0Y46_OQ;
assign LIOB33_X0Y45_IOB_X0Y45_O = LIOI3_X0Y45_OLOGIC_X0Y45_OQ;
assign LIOI3_X0Y35_OLOGIC_X0Y35_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOB33_X0Y27_IOB_X0Y28_O = LIOI3_X0Y27_OLOGIC_X0Y28_OQ;
assign LIOB33_X0Y27_IOB_X0Y27_O = LIOI3_X0Y27_OLOGIC_X0Y27_OQ;
assign LIOI3_X0Y35_OLOGIC_X0Y35_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y35_OLOGIC_X0Y35_T1 = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y30_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_T1 = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y29_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_T1 = 1'b1;
assign LIOB33_X0Y31_IOB_X0Y32_O = LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ;
assign LIOB33_X0Y31_IOB_X0Y31_O = LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ;
assign LIOI3_X0Y25_OLOGIC_X0Y26_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_SR = 1'b0;
assign LIOI3_X0Y25_OLOGIC_X0Y26_T1 = 1'b1;
assign LIOI3_X0Y25_OLOGIC_X0Y25_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_D = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_D = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_T1 = 1'b1;
assign LIOI3_X0Y21_OLOGIC_X0Y22_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y21_OLOGIC_X0Y22_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y35_IOB_X0Y36_O = LIOI3_X0Y35_OLOGIC_X0Y36_OQ;
assign LIOB33_X0Y35_IOB_X0Y35_O = LIOI3_X0Y35_OLOGIC_X0Y35_OQ;
assign LIOI3_X0Y21_OLOGIC_X0Y22_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y21_OLOGIC_X0Y22_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y21_OLOGIC_X0Y22_T1 = 1'b1;
assign LIOI3_X0Y45_OLOGIC_X0Y46_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y45_OLOGIC_X0Y46_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y45_OLOGIC_X0Y46_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y45_OLOGIC_X0Y46_SR = 1'b0;
assign LIOI3_X0Y45_OLOGIC_X0Y46_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1 = 1'b1;
assign LIOB33_X0Y39_IOB_X0Y40_O = LIOI3_X0Y39_OLOGIC_X0Y40_OQ;
assign LIOB33_X0Y39_IOB_X0Y39_O = LIOI3_X0Y39_OLOGIC_X0Y39_OQ;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1 = 1'b1;
assign LIOB33_X0Y21_IOB_X0Y22_O = LIOI3_X0Y21_OLOGIC_X0Y22_OQ;
assign LIOI3_X0Y45_OLOGIC_X0Y45_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y45_OLOGIC_X0Y45_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y45_OLOGIC_X0Y45_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y45_OLOGIC_X0Y45_SR = 1'b0;
assign LIOI3_X0Y45_OLOGIC_X0Y45_T1 = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y40_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_T1 = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y39_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y39_OLOGIC_X0Y39_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y43_IOB_X0Y43_O = LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ;
assign LIOB33_X0Y25_IOB_X0Y26_O = LIOI3_X0Y25_OLOGIC_X0Y26_OQ;
assign LIOB33_X0Y25_IOB_X0Y25_O = LIOI3_X0Y25_OLOGIC_X0Y25_OQ;
assign LIOI3_X0Y39_OLOGIC_X0Y39_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y39_OLOGIC_X0Y39_SR = 1'b0;
assign LIOI3_X0Y39_OLOGIC_X0Y39_T1 = 1'b1;
assign LIOI3_X0Y33_OLOGIC_X0Y34_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_T1 = 1'b1;
assign RIOI3_X43Y45_ILOGIC_X1Y46_D = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_D = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_SR = 1'b0;
assign LIOI3_X0Y33_OLOGIC_X0Y33_T1 = 1'b1;
assign LIOB33_X0Y29_IOB_X0Y30_O = LIOI3_X0Y29_OLOGIC_X0Y30_OQ;
assign LIOB33_X0Y29_IOB_X0Y29_O = LIOI3_X0Y29_OLOGIC_X0Y29_OQ;
assign LIOI3_X0Y27_OLOGIC_X0Y28_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_T1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0 = RIOB33_X43Y25_IOB_X1Y26_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1 = 1'b1;
assign LIOI3_X0Y27_OLOGIC_X0Y27_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y27_OLOGIC_X0Y27_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOI3_X43Y25_ILOGIC_X1Y26_D = RIOB33_X43Y25_IOB_X1Y26_I;
assign LIOI3_X0Y27_OLOGIC_X0Y27_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y27_OLOGIC_X0Y27_SR = 1'b0;
assign LIOI3_X0Y27_OLOGIC_X0Y27_T1 = 1'b1;
assign LIOB33_X0Y33_IOB_X0Y34_O = LIOI3_X0Y33_OLOGIC_X0Y34_OQ;
assign LIOB33_X0Y33_IOB_X0Y33_O = LIOI3_X0Y33_OLOGIC_X0Y33_OQ;
assign LIOI3_X0Y23_OLOGIC_X0Y24_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_T1 = 1'b1;
assign LIOI3_X0Y23_OLOGIC_X0Y23_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_T1 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_OLOGIC_X0Y42_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_OLOGIC_X0Y41_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_OLOGIC_X0Y36_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_OLOGIC_X0Y35_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y29_OLOGIC_X0Y30_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y29_OLOGIC_X0Y29_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y25_OLOGIC_X0Y26_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y25_OLOGIC_X0Y25_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y21_OLOGIC_X0Y22_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_OLOGIC_X0Y46_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_OLOGIC_X0Y45_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y39_OLOGIC_X0Y40_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y39_OLOGIC_X0Y39_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y33_OLOGIC_X0Y34_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y33_OLOGIC_X0Y33_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y27_OLOGIC_X0Y28_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y27_OLOGIC_X0Y27_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y23_OLOGIC_X0Y24_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y23_OLOGIC_X0Y23_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
endmodule |
module testbench;
//--------------------------------------------------------------------
// Testbench signals
//--------------------------------------------------------------------
wire reset;
wire tx_client_clk;
wire [7:0] tx_ifg_delay;
wire rx_client_clk;
wire [15:0] pause_val;
wire pause_req;
// GMII wires
wire gmii_tx_clk;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_txd;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire gmii_rx_er;
wire [7:0] gmii_rxd;
// Not asserted: full duplex only testbench
wire mii_tx_clk;
wire gmii_crs;
wire gmii_col;
// MDIO wires
wire mdc;
wire mdc_in;
wire mdio_in;
wire mdio_out;
wire mdio_tri;
// Host wires
wire [1:0] host_opcode;
wire [9:0] host_addr;
wire [31:0] host_wr_data;
wire [31:0] host_rd_data;
wire host_miim_sel;
wire host_req;
wire host_miim_rdy;
// Clock wires
wire host_clk;
reg gtx_clk;
reg refclk;
//----------------------------------------------------------------
// Testbench Semaphores
//----------------------------------------------------------------
wire configuration_busy;
wire monitor_finished_1g;
wire monitor_finished_100m;
wire monitor_finished_10m;
//----------------------------------------------------------------
// Wire up device under test
//----------------------------------------------------------------
v6_emac_v1_3_example_design dut
(
// Client receiver interface
.EMACCLIENTRXDVLD (),
.EMACCLIENTRXFRAMEDROP (),
.EMACCLIENTRXSTATS (),
.EMACCLIENTRXSTATSVLD (),
.EMACCLIENTRXSTATSBYTEVLD (),
// Client transmitter interface
.CLIENTEMACTXIFGDELAY (tx_ifg_delay),
.EMACCLIENTTXSTATS (),
.EMACCLIENTTXSTATSVLD (),
.EMACCLIENTTXSTATSBYTEVLD (),
// MAC Control interface
.CLIENTEMACPAUSEREQ (pause_req),
.CLIENTEMACPAUSEVAL (pause_val),
// Clock signal
.GTX_CLK (gtx_clk),
// GMII interface
.GMII_TXD (gmii_txd),
.GMII_TX_EN (gmii_tx_en),
.GMII_TX_ER (gmii_tx_er),
.GMII_TX_CLK (gmii_tx_clk),
.GMII_RXD (gmii_rxd),
.GMII_RX_DV (gmii_rx_dv),
.GMII_RX_ER (gmii_rx_er),
.GMII_RX_CLK (gmii_rx_clk),
// MDIO interface
.MDC (mdc),
.MDIO_I (mdio_in),
.MDIO_O (mdio_out),
.MDIO_T (mdio_tri),
// Host interface
.HOSTCLK (host_clk),
.HOSTOPCODE (host_opcode),
.HOSTREQ (host_req),
.HOSTMIIMSEL (host_miim_sel),
.HOSTADDR (host_addr),
.HOSTWRDATA (host_wr_data),
.HOSTMIIMRDY (host_miim_rdy),
.HOSTRDDATA (host_rd_data),
.REFCLK (refclk),
// Asynchronous reset
.RESET (reset)
);
//--------------------------------------------------------------------------
// Flow control is unused in this demonstration
//--------------------------------------------------------------------------
assign pause_req = 1'b0;
assign pause_val = 16'b0;
// IFG stretching not used in demo.
assign tx_ifg_delay = 8'b0;
//--------------------------------------------------------------------------
// Simulate the MDIO_IN port floating high
//--------------------------------------------------------------------------
assign (strong0, weak1) mdio_in = 1'b1;
//--------------------------------------------------------------------------
// Clock drivers
//--------------------------------------------------------------------------
// Drive GTX_CLK at 125 MHz
initial
begin
gtx_clk <= 1'b0;
#10000;
forever
begin
gtx_clk <= 1'b0;
#4000;
gtx_clk <= 1'b1;
#4000;
end
end
// Drive refclk at 200MHz
initial
begin
refclk <= 1'b0;
#10000;
forever
begin
refclk <= 1'b1;
#2500;
refclk <= 1'b0;
#2500;
end
end
//--------------------------------------------------------------------
// Instantiate the PHY stimulus and monitor
//--------------------------------------------------------------------
phy_tb phy_test
(
//----------------------------------------------------------------
// GMII interface
//----------------------------------------------------------------
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.gmii_rx_clk (gmii_rx_clk),
.gmii_col (gmii_col),
.gmii_crs (gmii_crs),
.mii_tx_clk (mii_tx_clk),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
//--------------------------------------------------------------------
// Instantiate the host configuration stimulus
//--------------------------------------------------------------------
configuration_tb config_test
(
.reset (reset),
//----------------------------------------------------------------
// Host interface
//----------------------------------------------------------------
.host_clk (host_clk),
.host_opcode (host_opcode),
.host_req (host_req),
.host_miim_sel (host_miim_sel),
.host_addr (host_addr),
.host_wr_data (host_wr_data),
.host_miim_rdy (host_miim_rdy),
.host_rd_data (host_rd_data),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
endmodule |
module sky130_fd_sc_hdll__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule |
module DSP_MULTIPLIER #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter AMULTSEL = "A",
parameter BMULTSEL = "B",
parameter USE_MULT = "MULTIPLY"
)(
output AMULT26,
output BMULT17,
output [44:0] U,
output [44:0] V,
input [26:0] A2A1,
input [26:0] AD_DATA,
input [17:0] B2B1
);
// define constants
localparam MODULE_NAME = "DSP_MULTIPLIER";
// Parameter encodings and registers
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_MULTIPLIER_dr.v"
`else
reg [16:1] AMULTSEL_REG = AMULTSEL;
reg [16:1] BMULTSEL_REG = BMULTSEL;
reg [64:1] USE_MULT_REG = USE_MULT;
`endif
`ifdef XIL_XECLIB
wire AMULTSEL_BIN;
wire BMULTSEL_BIN;
wire [1:0] USE_MULT_BIN;
`else
reg AMULTSEL_BIN;
reg BMULTSEL_BIN;
reg [1:0] USE_MULT_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
`else
always @(trig_attr) begin
#1;
AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
end
`endif
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
`ifndef XIL_XECLIB
always @(trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-101] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-102] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE"))) begin
$display("Error: [Unisim %s-103] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
localparam M_WIDTH = 45;
reg [17:0] b_mult_mux;
reg [26:0] a_mult_mux;
reg [M_WIDTH-1:0] mult;
reg [M_WIDTH-2:0] ps_u_mask;
reg [M_WIDTH-2:0] ps_v_mask;
// initialize regs
`ifndef XIL_XECLIB
initial begin
ps_u_mask = 44'h55555555555;
ps_v_mask = 44'haaaaaaaaaaa;
end
`endif
always @(*) begin
if (AMULTSEL_BIN == AMULTSEL_A) a_mult_mux = A2A1;
else a_mult_mux = AD_DATA;
end
always @(*) begin
if (BMULTSEL_BIN == BMULTSEL_B) b_mult_mux = B2B1;
else b_mult_mux = AD_DATA;
end
assign AMULT26 = a_mult_mux[26];
assign BMULT17 = b_mult_mux[17];
// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1
assign U = {1'b1, mult[43:0] & ps_u_mask};
assign V = {~mult[44], mult[43:0] & ps_v_mask};
always @(*) begin
if (USE_MULT_BIN == USE_MULT_NONE) mult = 45'b0;
else mult = ({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux});
end
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(A2A1[0] => U[10]) = (0:0:0, 0:0:0);
(A2A1[0] => U[11]) = (0:0:0, 0:0:0);
(A2A1[0] => U[12]) = (0:0:0, 0:0:0);
(A2A1[0] => U[13]) = (0:0:0, 0:0:0);
(A2A1[0] => U[14]) = (0:0:0, 0:0:0);
(A2A1[0] => U[15]) = (0:0:0, 0:0:0);
(A2A1[0] => U[16]) = (0:0:0, 0:0:0);
(A2A1[0] => U[17]) = (0:0:0, 0:0:0);
(A2A1[0] => U[18]) = (0:0:0, 0:0:0);
(A2A1[0] => U[19]) = (0:0:0, 0:0:0);
(A2A1[0] => U[1]) = (0:0:0, 0:0:0);
(A2A1[0] => U[20]) = (0:0:0, 0:0:0);
(A2A1[0] => U[21]) = (0:0:0, 0:0:0);
(A2A1[0] => U[2]) = (0:0:0, 0:0:0);
(A2A1[0] => U[3]) = (0:0:0, 0:0:0);
(A2A1[0] => U[4]) = (0:0:0, 0:0:0);
(A2A1[0] => U[5]) = (0:0:0, 0:0:0);
(A2A1[0] => U[6]) = (0:0:0, 0:0:0);
(A2A1[0] => U[7]) = (0:0:0, 0:0:0);
(A2A1[0] => U[8]) = (0:0:0, 0:0:0);
(A2A1[0] => U[9]) = (0:0:0, 0:0:0);
(A2A1[0] => V[0]) = (0:0:0, 0:0:0);
(A2A1[0] => V[10]) = (0:0:0, 0:0:0);
(A2A1[0] => V[11]) = (0:0:0, 0:0:0);
(A2A1[0] => V[12]) = (0:0:0, 0:0:0);
(A2A1[0] => V[13]) = (0:0:0, 0:0:0);
(A2A1[0] => V[14]) = (0:0:0, 0:0:0);
(A2A1[0] => V[15]) = (0:0:0, 0:0:0);
(A2A1[0] => V[16]) = (0:0:0, 0:0:0);
(A2A1[0] => V[17]) = (0:0:0, 0:0:0);
(A2A1[0] => V[18]) = (0:0:0, 0:0:0);
(A2A1[0] => V[19]) = (0:0:0, 0:0:0);
(A2A1[0] => V[20]) = (0:0:0, 0:0:0);
(A2A1[0] => V[4]) = (0:0:0, 0:0:0);
(A2A1[0] => V[5]) = (0:0:0, 0:0:0);
(A2A1[0] => V[6]) = (0:0:0, 0:0:0);
(A2A1[0] => V[7]) = (0:0:0, 0:0:0);
(A2A1[0] => V[8]) = (0:0:0, 0:0:0);
(A2A1[0] => V[9]) = (0:0:0, 0:0:0);
(A2A1[10] => U[11]) = (0:0:0, 0:0:0);
(A2A1[10] => U[12]) = (0:0:0, 0:0:0);
(A2A1[10] => U[13]) = (0:0:0, 0:0:0);
(A2A1[10] => U[14]) = (0:0:0, 0:0:0);
(A2A1[10] => U[15]) = (0:0:0, 0:0:0);
(A2A1[10] => U[16]) = (0:0:0, 0:0:0);
(A2A1[10] => U[17]) = (0:0:0, 0:0:0);
(A2A1[10] => U[18]) = (0:0:0, 0:0:0);
(A2A1[10] => U[19]) = (0:0:0, 0:0:0);
(A2A1[10] => U[20]) = (0:0:0, 0:0:0);
(A2A1[10] => U[21]) = (0:0:0, 0:0:0);
(A2A1[10] => U[22]) = (0:0:0, 0:0:0);
(A2A1[10] => U[23]) = (0:0:0, 0:0:0);
(A2A1[10] => U[24]) = (0:0:0, 0:0:0);
(A2A1[10] => U[25]) = (0:0:0, 0:0:0);
(A2A1[10] => U[26]) = (0:0:0, 0:0:0);
(A2A1[10] => U[27]) = (0:0:0, 0:0:0);
(A2A1[10] => U[28]) = (0:0:0, 0:0:0);
(A2A1[10] => U[29]) = (0:0:0, 0:0:0);
(A2A1[10] => U[30]) = (0:0:0, 0:0:0);
(A2A1[10] => U[31]) = (0:0:0, 0:0:0);
(A2A1[10] => V[10]) = (0:0:0, 0:0:0);
(A2A1[10] => V[11]) = (0:0:0, 0:0:0);
(A2A1[10] => V[12]) = (0:0:0, 0:0:0);
(A2A1[10] => V[13]) = (0:0:0, 0:0:0);
(A2A1[10] => V[14]) = (0:0:0, 0:0:0);
(A2A1[10] => V[15]) = (0:0:0, 0:0:0);
(A2A1[10] => V[16]) = (0:0:0, 0:0:0);
(A2A1[10] => V[17]) = (0:0:0, 0:0:0);
(A2A1[10] => V[18]) = (0:0:0, 0:0:0);
(A2A1[10] => V[19]) = (0:0:0, 0:0:0);
(A2A1[10] => V[20]) = (0:0:0, 0:0:0);
(A2A1[10] => V[21]) = (0:0:0, 0:0:0);
(A2A1[10] => V[22]) = (0:0:0, 0:0:0);
(A2A1[10] => V[23]) = (0:0:0, 0:0:0);
(A2A1[10] => V[24]) = (0:0:0, 0:0:0);
(A2A1[10] => V[25]) = (0:0:0, 0:0:0);
(A2A1[10] => V[26]) = (0:0:0, 0:0:0);
(A2A1[10] => V[27]) = (0:0:0, 0:0:0);
(A2A1[10] => V[28]) = (0:0:0, 0:0:0);
(A2A1[10] => V[29]) = (0:0:0, 0:0:0);
(A2A1[10] => V[30]) = (0:0:0, 0:0:0);
(A2A1[11] => U[12]) = (0:0:0, 0:0:0);
(A2A1[11] => U[13]) = (0:0:0, 0:0:0);
(A2A1[11] => U[14]) = (0:0:0, 0:0:0);
(A2A1[11] => U[15]) = (0:0:0, 0:0:0);
(A2A1[11] => U[16]) = (0:0:0, 0:0:0);
(A2A1[11] => U[17]) = (0:0:0, 0:0:0);
(A2A1[11] => U[18]) = (0:0:0, 0:0:0);
(A2A1[11] => U[19]) = (0:0:0, 0:0:0);
(A2A1[11] => U[20]) = (0:0:0, 0:0:0);
(A2A1[11] => U[21]) = (0:0:0, 0:0:0);
(A2A1[11] => U[22]) = (0:0:0, 0:0:0);
(A2A1[11] => U[23]) = (0:0:0, 0:0:0);
(A2A1[11] => U[24]) = (0:0:0, 0:0:0);
(A2A1[11] => U[25]) = (0:0:0, 0:0:0);
(A2A1[11] => U[26]) = (0:0:0, 0:0:0);
(A2A1[11] => U[27]) = (0:0:0, 0:0:0);
(A2A1[11] => U[28]) = (0:0:0, 0:0:0);
(A2A1[11] => U[29]) = (0:0:0, 0:0:0);
(A2A1[11] => U[30]) = (0:0:0, 0:0:0);
(A2A1[11] => U[31]) = (0:0:0, 0:0:0);
(A2A1[11] => U[32]) = (0:0:0, 0:0:0);
(A2A1[11] => V[11]) = (0:0:0, 0:0:0);
(A2A1[11] => V[12]) = (0:0:0, 0:0:0);
(A2A1[11] => V[13]) = (0:0:0, 0:0:0);
(A2A1[11] => V[14]) = (0:0:0, 0:0:0);
(A2A1[11] => V[15]) = (0:0:0, 0:0:0);
(A2A1[11] => V[16]) = (0:0:0, 0:0:0);
(A2A1[11] => V[17]) = (0:0:0, 0:0:0);
(A2A1[11] => V[18]) = (0:0:0, 0:0:0);
(A2A1[11] => V[19]) = (0:0:0, 0:0:0);
(A2A1[11] => V[20]) = (0:0:0, 0:0:0);
(A2A1[11] => V[21]) = (0:0:0, 0:0:0);
(A2A1[11] => V[22]) = (0:0:0, 0:0:0);
(A2A1[11] => V[23]) = (0:0:0, 0:0:0);
(A2A1[11] => V[24]) = (0:0:0, 0:0:0);
(A2A1[11] => V[25]) = (0:0:0, 0:0:0);
(A2A1[11] => V[26]) = (0:0:0, 0:0:0);
(A2A1[11] => V[27]) = (0:0:0, 0:0:0);
(A2A1[11] => V[28]) = (0:0:0, 0:0:0);
(A2A1[11] => V[29]) = (0:0:0, 0:0:0);
(A2A1[11] => V[30]) = (0:0:0, 0:0:0);
(A2A1[11] => V[31]) = (0:0:0, 0:0:0);
(A2A1[12] => U[13]) = (0:0:0, 0:0:0);
(A2A1[12] => U[14]) = (0:0:0, 0:0:0);
(A2A1[12] => U[15]) = (0:0:0, 0:0:0);
(A2A1[12] => U[16]) = (0:0:0, 0:0:0);
(A2A1[12] => U[17]) = (0:0:0, 0:0:0);
(A2A1[12] => U[18]) = (0:0:0, 0:0:0);
(A2A1[12] => U[19]) = (0:0:0, 0:0:0);
(A2A1[12] => U[20]) = (0:0:0, 0:0:0);
(A2A1[12] => U[21]) = (0:0:0, 0:0:0);
(A2A1[12] => U[22]) = (0:0:0, 0:0:0);
(A2A1[12] => U[23]) = (0:0:0, 0:0:0);
(A2A1[12] => U[24]) = (0:0:0, 0:0:0);
(A2A1[12] => U[25]) = (0:0:0, 0:0:0);
(A2A1[12] => U[26]) = (0:0:0, 0:0:0);
(A2A1[12] => U[27]) = (0:0:0, 0:0:0);
(A2A1[12] => U[28]) = (0:0:0, 0:0:0);
(A2A1[12] => U[29]) = (0:0:0, 0:0:0);
(A2A1[12] => U[30]) = (0:0:0, 0:0:0);
(A2A1[12] => U[31]) = (0:0:0, 0:0:0);
(A2A1[12] => U[32]) = (0:0:0, 0:0:0);
(A2A1[12] => U[33]) = (0:0:0, 0:0:0);
(A2A1[12] => V[12]) = (0:0:0, 0:0:0);
(A2A1[12] => V[13]) = (0:0:0, 0:0:0);
(A2A1[12] => V[14]) = (0:0:0, 0:0:0);
(A2A1[12] => V[15]) = (0:0:0, 0:0:0);
(A2A1[12] => V[16]) = (0:0:0, 0:0:0);
(A2A1[12] => V[17]) = (0:0:0, 0:0:0);
(A2A1[12] => V[18]) = (0:0:0, 0:0:0);
(A2A1[12] => V[19]) = (0:0:0, 0:0:0);
(A2A1[12] => V[20]) = (0:0:0, 0:0:0);
(A2A1[12] => V[21]) = (0:0:0, 0:0:0);
(A2A1[12] => V[22]) = (0:0:0, 0:0:0);
(A2A1[12] => V[23]) = (0:0:0, 0:0:0);
(A2A1[12] => V[24]) = (0:0:0, 0:0:0);
(A2A1[12] => V[25]) = (0:0:0, 0:0:0);
(A2A1[12] => V[26]) = (0:0:0, 0:0:0);
(A2A1[12] => V[27]) = (0:0:0, 0:0:0);
(A2A1[12] => V[28]) = (0:0:0, 0:0:0);
(A2A1[12] => V[29]) = (0:0:0, 0:0:0);
(A2A1[12] => V[30]) = (0:0:0, 0:0:0);
(A2A1[12] => V[31]) = (0:0:0, 0:0:0);
(A2A1[12] => V[32]) = (0:0:0, 0:0:0);
(A2A1[13] => U[14]) = (0:0:0, 0:0:0);
(A2A1[13] => U[15]) = (0:0:0, 0:0:0);
(A2A1[13] => U[16]) = (0:0:0, 0:0:0);
(A2A1[13] => U[17]) = (0:0:0, 0:0:0);
(A2A1[13] => U[18]) = (0:0:0, 0:0:0);
(A2A1[13] => U[19]) = (0:0:0, 0:0:0);
(A2A1[13] => U[20]) = (0:0:0, 0:0:0);
(A2A1[13] => U[21]) = (0:0:0, 0:0:0);
(A2A1[13] => U[22]) = (0:0:0, 0:0:0);
(A2A1[13] => U[23]) = (0:0:0, 0:0:0);
(A2A1[13] => U[24]) = (0:0:0, 0:0:0);
(A2A1[13] => U[25]) = (0:0:0, 0:0:0);
(A2A1[13] => U[26]) = (0:0:0, 0:0:0);
(A2A1[13] => U[27]) = (0:0:0, 0:0:0);
(A2A1[13] => U[28]) = (0:0:0, 0:0:0);
(A2A1[13] => U[29]) = (0:0:0, 0:0:0);
(A2A1[13] => U[30]) = (0:0:0, 0:0:0);
(A2A1[13] => U[31]) = (0:0:0, 0:0:0);
(A2A1[13] => U[32]) = (0:0:0, 0:0:0);
(A2A1[13] => U[33]) = (0:0:0, 0:0:0);
(A2A1[13] => U[34]) = (0:0:0, 0:0:0);
(A2A1[13] => V[13]) = (0:0:0, 0:0:0);
(A2A1[13] => V[14]) = (0:0:0, 0:0:0);
(A2A1[13] => V[15]) = (0:0:0, 0:0:0);
(A2A1[13] => V[16]) = (0:0:0, 0:0:0);
(A2A1[13] => V[17]) = (0:0:0, 0:0:0);
(A2A1[13] => V[18]) = (0:0:0, 0:0:0);
(A2A1[13] => V[19]) = (0:0:0, 0:0:0);
(A2A1[13] => V[20]) = (0:0:0, 0:0:0);
(A2A1[13] => V[21]) = (0:0:0, 0:0:0);
(A2A1[13] => V[22]) = (0:0:0, 0:0:0);
(A2A1[13] => V[23]) = (0:0:0, 0:0:0);
(A2A1[13] => V[24]) = (0:0:0, 0:0:0);
(A2A1[13] => V[25]) = (0:0:0, 0:0:0);
(A2A1[13] => V[26]) = (0:0:0, 0:0:0);
(A2A1[13] => V[27]) = (0:0:0, 0:0:0);
(A2A1[13] => V[28]) = (0:0:0, 0:0:0);
(A2A1[13] => V[29]) = (0:0:0, 0:0:0);
(A2A1[13] => V[30]) = (0:0:0, 0:0:0);
(A2A1[13] => V[31]) = (0:0:0, 0:0:0);
(A2A1[13] => V[32]) = (0:0:0, 0:0:0);
(A2A1[13] => V[33]) = (0:0:0, 0:0:0);
(A2A1[14] => U[15]) = (0:0:0, 0:0:0);
(A2A1[14] => U[16]) = (0:0:0, 0:0:0);
(A2A1[14] => U[17]) = (0:0:0, 0:0:0);
(A2A1[14] => U[18]) = (0:0:0, 0:0:0);
(A2A1[14] => U[19]) = (0:0:0, 0:0:0);
(A2A1[14] => U[20]) = (0:0:0, 0:0:0);
(A2A1[14] => U[21]) = (0:0:0, 0:0:0);
(A2A1[14] => U[22]) = (0:0:0, 0:0:0);
(A2A1[14] => U[23]) = (0:0:0, 0:0:0);
(A2A1[14] => U[24]) = (0:0:0, 0:0:0);
(A2A1[14] => U[25]) = (0:0:0, 0:0:0);
(A2A1[14] => U[26]) = (0:0:0, 0:0:0);
(A2A1[14] => U[27]) = (0:0:0, 0:0:0);
(A2A1[14] => U[28]) = (0:0:0, 0:0:0);
(A2A1[14] => U[29]) = (0:0:0, 0:0:0);
(A2A1[14] => U[30]) = (0:0:0, 0:0:0);
(A2A1[14] => U[31]) = (0:0:0, 0:0:0);
(A2A1[14] => U[32]) = (0:0:0, 0:0:0);
(A2A1[14] => U[33]) = (0:0:0, 0:0:0);
(A2A1[14] => U[34]) = (0:0:0, 0:0:0);
(A2A1[14] => V[14]) = (0:0:0, 0:0:0);
(A2A1[14] => V[15]) = (0:0:0, 0:0:0);
(A2A1[14] => V[16]) = (0:0:0, 0:0:0);
(A2A1[14] => V[17]) = (0:0:0, 0:0:0);
(A2A1[14] => V[18]) = (0:0:0, 0:0:0);
(A2A1[14] => V[19]) = (0:0:0, 0:0:0);
(A2A1[14] => V[20]) = (0:0:0, 0:0:0);
(A2A1[14] => V[21]) = (0:0:0, 0:0:0);
(A2A1[14] => V[22]) = (0:0:0, 0:0:0);
(A2A1[14] => V[23]) = (0:0:0, 0:0:0);
(A2A1[14] => V[24]) = (0:0:0, 0:0:0);
(A2A1[14] => V[25]) = (0:0:0, 0:0:0);
(A2A1[14] => V[26]) = (0:0:0, 0:0:0);
(A2A1[14] => V[27]) = (0:0:0, 0:0:0);
(A2A1[14] => V[28]) = (0:0:0, 0:0:0);
(A2A1[14] => V[29]) = (0:0:0, 0:0:0);
(A2A1[14] => V[30]) = (0:0:0, 0:0:0);
(A2A1[14] => V[31]) = (0:0:0, 0:0:0);
(A2A1[14] => V[32]) = (0:0:0, 0:0:0);
(A2A1[14] => V[33]) = (0:0:0, 0:0:0);
(A2A1[15] => U[16]) = (0:0:0, 0:0:0);
(A2A1[15] => U[17]) = (0:0:0, 0:0:0);
(A2A1[15] => U[18]) = (0:0:0, 0:0:0);
(A2A1[15] => U[19]) = (0:0:0, 0:0:0);
(A2A1[15] => U[20]) = (0:0:0, 0:0:0);
(A2A1[15] => U[21]) = (0:0:0, 0:0:0);
(A2A1[15] => U[22]) = (0:0:0, 0:0:0);
(A2A1[15] => U[23]) = (0:0:0, 0:0:0);
(A2A1[15] => U[24]) = (0:0:0, 0:0:0);
(A2A1[15] => U[25]) = (0:0:0, 0:0:0);
(A2A1[15] => U[26]) = (0:0:0, 0:0:0);
(A2A1[15] => U[27]) = (0:0:0, 0:0:0);
(A2A1[15] => U[28]) = (0:0:0, 0:0:0);
(A2A1[15] => U[29]) = (0:0:0, 0:0:0);
(A2A1[15] => U[30]) = (0:0:0, 0:0:0);
(A2A1[15] => U[31]) = (0:0:0, 0:0:0);
(A2A1[15] => U[32]) = (0:0:0, 0:0:0);
(A2A1[15] => U[33]) = (0:0:0, 0:0:0);
(A2A1[15] => U[34]) = (0:0:0, 0:0:0);
(A2A1[15] => U[35]) = (0:0:0, 0:0:0);
(A2A1[15] => U[36]) = (0:0:0, 0:0:0);
(A2A1[15] => V[15]) = (0:0:0, 0:0:0);
(A2A1[15] => V[16]) = (0:0:0, 0:0:0);
(A2A1[15] => V[17]) = (0:0:0, 0:0:0);
(A2A1[15] => V[18]) = (0:0:0, 0:0:0);
(A2A1[15] => V[19]) = (0:0:0, 0:0:0);
(A2A1[15] => V[20]) = (0:0:0, 0:0:0);
(A2A1[15] => V[21]) = (0:0:0, 0:0:0);
(A2A1[15] => V[22]) = (0:0:0, 0:0:0);
(A2A1[15] => V[23]) = (0:0:0, 0:0:0);
(A2A1[15] => V[24]) = (0:0:0, 0:0:0);
(A2A1[15] => V[25]) = (0:0:0, 0:0:0);
(A2A1[15] => V[26]) = (0:0:0, 0:0:0);
(A2A1[15] => V[27]) = (0:0:0, 0:0:0);
(A2A1[15] => V[28]) = (0:0:0, 0:0:0);
(A2A1[15] => V[29]) = (0:0:0, 0:0:0);
(A2A1[15] => V[30]) = (0:0:0, 0:0:0);
(A2A1[15] => V[31]) = (0:0:0, 0:0:0);
(A2A1[15] => V[32]) = (0:0:0, 0:0:0);
(A2A1[15] => V[33]) = (0:0:0, 0:0:0);
(A2A1[15] => V[34]) = (0:0:0, 0:0:0);
(A2A1[15] => V[35]) = (0:0:0, 0:0:0);
(A2A1[16] => U[17]) = (0:0:0, 0:0:0);
(A2A1[16] => U[18]) = (0:0:0, 0:0:0);
(A2A1[16] => U[19]) = (0:0:0, 0:0:0);
(A2A1[16] => U[20]) = (0:0:0, 0:0:0);
(A2A1[16] => U[21]) = (0:0:0, 0:0:0);
(A2A1[16] => U[22]) = (0:0:0, 0:0:0);
(A2A1[16] => U[23]) = (0:0:0, 0:0:0);
(A2A1[16] => U[24]) = (0:0:0, 0:0:0);
(A2A1[16] => U[25]) = (0:0:0, 0:0:0);
(A2A1[16] => U[26]) = (0:0:0, 0:0:0);
(A2A1[16] => U[27]) = (0:0:0, 0:0:0);
(A2A1[16] => U[28]) = (0:0:0, 0:0:0);
(A2A1[16] => U[29]) = (0:0:0, 0:0:0);
(A2A1[16] => U[30]) = (0:0:0, 0:0:0);
(A2A1[16] => U[31]) = (0:0:0, 0:0:0);
(A2A1[16] => U[32]) = (0:0:0, 0:0:0);
(A2A1[16] => U[33]) = (0:0:0, 0:0:0);
(A2A1[16] => U[34]) = (0:0:0, 0:0:0);
(A2A1[16] => U[35]) = (0:0:0, 0:0:0);
(A2A1[16] => U[36]) = (0:0:0, 0:0:0);
(A2A1[16] => V[16]) = (0:0:0, 0:0:0);
(A2A1[16] => V[17]) = (0:0:0, 0:0:0);
(A2A1[16] => V[18]) = (0:0:0, 0:0:0);
(A2A1[16] => V[19]) = (0:0:0, 0:0:0);
(A2A1[16] => V[20]) = (0:0:0, 0:0:0);
(A2A1[16] => V[21]) = (0:0:0, 0:0:0);
(A2A1[16] => V[22]) = (0:0:0, 0:0:0);
(A2A1[16] => V[23]) = (0:0:0, 0:0:0);
(A2A1[16] => V[24]) = (0:0:0, 0:0:0);
(A2A1[16] => V[25]) = (0:0:0, 0:0:0);
(A2A1[16] => V[26]) = (0:0:0, 0:0:0);
(A2A1[16] => V[27]) = (0:0:0, 0:0:0);
(A2A1[16] => V[28]) = (0:0:0, 0:0:0);
(A2A1[16] => V[29]) = (0:0:0, 0:0:0);
(A2A1[16] => V[30]) = (0:0:0, 0:0:0);
(A2A1[16] => V[31]) = (0:0:0, 0:0:0);
(A2A1[16] => V[32]) = (0:0:0, 0:0:0);
(A2A1[16] => V[33]) = (0:0:0, 0:0:0);
(A2A1[16] => V[34]) = (0:0:0, 0:0:0);
(A2A1[16] => V[35]) = (0:0:0, 0:0:0);
(A2A1[17] => U[18]) = (0:0:0, 0:0:0);
(A2A1[17] => U[19]) = (0:0:0, 0:0:0);
(A2A1[17] => U[20]) = (0:0:0, 0:0:0);
(A2A1[17] => U[21]) = (0:0:0, 0:0:0);
(A2A1[17] => U[22]) = (0:0:0, 0:0:0);
(A2A1[17] => U[23]) = (0:0:0, 0:0:0);
(A2A1[17] => U[24]) = (0:0:0, 0:0:0);
(A2A1[17] => U[25]) = (0:0:0, 0:0:0);
(A2A1[17] => U[26]) = (0:0:0, 0:0:0);
(A2A1[17] => U[27]) = (0:0:0, 0:0:0);
(A2A1[17] => U[28]) = (0:0:0, 0:0:0);
(A2A1[17] => U[29]) = (0:0:0, 0:0:0);
(A2A1[17] => U[30]) = (0:0:0, 0:0:0);
(A2A1[17] => U[31]) = (0:0:0, 0:0:0);
(A2A1[17] => U[32]) = (0:0:0, 0:0:0);
(A2A1[17] => U[33]) = (0:0:0, 0:0:0);
(A2A1[17] => U[34]) = (0:0:0, 0:0:0);
(A2A1[17] => U[35]) = (0:0:0, 0:0:0);
(A2A1[17] => U[36]) = (0:0:0, 0:0:0);
(A2A1[17] => U[37]) = (0:0:0, 0:0:0);
(A2A1[17] => V[17]) = (0:0:0, 0:0:0);
(A2A1[17] => V[18]) = (0:0:0, 0:0:0);
(A2A1[17] => V[19]) = (0:0:0, 0:0:0);
(A2A1[17] => V[20]) = (0:0:0, 0:0:0);
(A2A1[17] => V[21]) = (0:0:0, 0:0:0);
(A2A1[17] => V[22]) = (0:0:0, 0:0:0);
(A2A1[17] => V[23]) = (0:0:0, 0:0:0);
(A2A1[17] => V[24]) = (0:0:0, 0:0:0);
(A2A1[17] => V[25]) = (0:0:0, 0:0:0);
(A2A1[17] => V[26]) = (0:0:0, 0:0:0);
(A2A1[17] => V[27]) = (0:0:0, 0:0:0);
(A2A1[17] => V[28]) = (0:0:0, 0:0:0);
(A2A1[17] => V[29]) = (0:0:0, 0:0:0);
(A2A1[17] => V[30]) = (0:0:0, 0:0:0);
(A2A1[17] => V[31]) = (0:0:0, 0:0:0);
(A2A1[17] => V[32]) = (0:0:0, 0:0:0);
(A2A1[17] => V[33]) = (0:0:0, 0:0:0);
(A2A1[17] => V[34]) = (0:0:0, 0:0:0);
(A2A1[17] => V[35]) = (0:0:0, 0:0:0);
(A2A1[17] => V[36]) = (0:0:0, 0:0:0);
(A2A1[18] => U[19]) = (0:0:0, 0:0:0);
(A2A1[18] => U[20]) = (0:0:0, 0:0:0);
(A2A1[18] => U[21]) = (0:0:0, 0:0:0);
(A2A1[18] => U[22]) = (0:0:0, 0:0:0);
(A2A1[18] => U[23]) = (0:0:0, 0:0:0);
(A2A1[18] => U[24]) = (0:0:0, 0:0:0);
(A2A1[18] => U[25]) = (0:0:0, 0:0:0);
(A2A1[18] => U[26]) = (0:0:0, 0:0:0);
(A2A1[18] => U[27]) = (0:0:0, 0:0:0);
(A2A1[18] => U[28]) = (0:0:0, 0:0:0);
(A2A1[18] => U[29]) = (0:0:0, 0:0:0);
(A2A1[18] => U[30]) = (0:0:0, 0:0:0);
(A2A1[18] => U[31]) = (0:0:0, 0:0:0);
(A2A1[18] => U[32]) = (0:0:0, 0:0:0);
(A2A1[18] => U[33]) = (0:0:0, 0:0:0);
(A2A1[18] => U[34]) = (0:0:0, 0:0:0);
(A2A1[18] => U[35]) = (0:0:0, 0:0:0);
(A2A1[18] => U[36]) = (0:0:0, 0:0:0);
(A2A1[18] => U[37]) = (0:0:0, 0:0:0);
(A2A1[18] => U[38]) = (0:0:0, 0:0:0);
(A2A1[18] => V[18]) = (0:0:0, 0:0:0);
(A2A1[18] => V[19]) = (0:0:0, 0:0:0);
(A2A1[18] => V[20]) = (0:0:0, 0:0:0);
(A2A1[18] => V[21]) = (0:0:0, 0:0:0);
(A2A1[18] => V[22]) = (0:0:0, 0:0:0);
(A2A1[18] => V[23]) = (0:0:0, 0:0:0);
(A2A1[18] => V[24]) = (0:0:0, 0:0:0);
(A2A1[18] => V[25]) = (0:0:0, 0:0:0);
(A2A1[18] => V[26]) = (0:0:0, 0:0:0);
(A2A1[18] => V[27]) = (0:0:0, 0:0:0);
(A2A1[18] => V[28]) = (0:0:0, 0:0:0);
(A2A1[18] => V[29]) = (0:0:0, 0:0:0);
(A2A1[18] => V[30]) = (0:0:0, 0:0:0);
(A2A1[18] => V[31]) = (0:0:0, 0:0:0);
(A2A1[18] => V[32]) = (0:0:0, 0:0:0);
(A2A1[18] => V[33]) = (0:0:0, 0:0:0);
(A2A1[18] => V[34]) = (0:0:0, 0:0:0);
(A2A1[18] => V[35]) = (0:0:0, 0:0:0);
(A2A1[18] => V[36]) = (0:0:0, 0:0:0);
(A2A1[18] => V[37]) = (0:0:0, 0:0:0);
(A2A1[19] => U[20]) = (0:0:0, 0:0:0);
(A2A1[19] => U[21]) = (0:0:0, 0:0:0);
(A2A1[19] => U[22]) = (0:0:0, 0:0:0);
(A2A1[19] => U[23]) = (0:0:0, 0:0:0);
(A2A1[19] => U[24]) = (0:0:0, 0:0:0);
(A2A1[19] => U[25]) = (0:0:0, 0:0:0);
(A2A1[19] => U[26]) = (0:0:0, 0:0:0);
(A2A1[19] => U[27]) = (0:0:0, 0:0:0);
(A2A1[19] => U[28]) = (0:0:0, 0:0:0);
(A2A1[19] => U[29]) = (0:0:0, 0:0:0);
(A2A1[19] => U[30]) = (0:0:0, 0:0:0);
(A2A1[19] => U[31]) = (0:0:0, 0:0:0);
(A2A1[19] => U[32]) = (0:0:0, 0:0:0);
(A2A1[19] => U[33]) = (0:0:0, 0:0:0);
(A2A1[19] => U[34]) = (0:0:0, 0:0:0);
(A2A1[19] => U[35]) = (0:0:0, 0:0:0);
(A2A1[19] => U[36]) = (0:0:0, 0:0:0);
(A2A1[19] => U[37]) = (0:0:0, 0:0:0);
(A2A1[19] => U[38]) = (0:0:0, 0:0:0);
(A2A1[19] => U[39]) = (0:0:0, 0:0:0);
(A2A1[19] => V[19]) = (0:0:0, 0:0:0);
(A2A1[19] => V[20]) = (0:0:0, 0:0:0);
(A2A1[19] => V[21]) = (0:0:0, 0:0:0);
(A2A1[19] => V[22]) = (0:0:0, 0:0:0);
(A2A1[19] => V[23]) = (0:0:0, 0:0:0);
(A2A1[19] => V[24]) = (0:0:0, 0:0:0);
(A2A1[19] => V[25]) = (0:0:0, 0:0:0);
(A2A1[19] => V[26]) = (0:0:0, 0:0:0);
(A2A1[19] => V[27]) = (0:0:0, 0:0:0);
(A2A1[19] => V[28]) = (0:0:0, 0:0:0);
(A2A1[19] => V[29]) = (0:0:0, 0:0:0);
(A2A1[19] => V[30]) = (0:0:0, 0:0:0);
(A2A1[19] => V[31]) = (0:0:0, 0:0:0);
(A2A1[19] => V[32]) = (0:0:0, 0:0:0);
(A2A1[19] => V[33]) = (0:0:0, 0:0:0);
(A2A1[19] => V[34]) = (0:0:0, 0:0:0);
(A2A1[19] => V[35]) = (0:0:0, 0:0:0);
(A2A1[19] => V[36]) = (0:0:0, 0:0:0);
(A2A1[19] => V[37]) = (0:0:0, 0:0:0);
(A2A1[19] => V[38]) = (0:0:0, 0:0:0);
(A2A1[1] => U[10]) = (0:0:0, 0:0:0);
(A2A1[1] => U[11]) = (0:0:0, 0:0:0);
(A2A1[1] => U[12]) = (0:0:0, 0:0:0);
(A2A1[1] => U[13]) = (0:0:0, 0:0:0);
(A2A1[1] => U[14]) = (0:0:0, 0:0:0);
(A2A1[1] => U[15]) = (0:0:0, 0:0:0);
(A2A1[1] => U[16]) = (0:0:0, 0:0:0);
(A2A1[1] => U[17]) = (0:0:0, 0:0:0);
(A2A1[1] => U[18]) = (0:0:0, 0:0:0);
(A2A1[1] => U[19]) = (0:0:0, 0:0:0);
(A2A1[1] => U[1]) = (0:0:0, 0:0:0);
(A2A1[1] => U[20]) = (0:0:0, 0:0:0);
(A2A1[1] => U[21]) = (0:0:0, 0:0:0);
(A2A1[1] => U[22]) = (0:0:0, 0:0:0);
(A2A1[1] => U[2]) = (0:0:0, 0:0:0);
(A2A1[1] => U[3]) = (0:0:0, 0:0:0);
(A2A1[1] => U[4]) = (0:0:0, 0:0:0);
(A2A1[1] => U[5]) = (0:0:0, 0:0:0);
(A2A1[1] => U[6]) = (0:0:0, 0:0:0);
(A2A1[1] => U[7]) = (0:0:0, 0:0:0);
(A2A1[1] => U[8]) = (0:0:0, 0:0:0);
(A2A1[1] => U[9]) = (0:0:0, 0:0:0);
(A2A1[1] => V[10]) = (0:0:0, 0:0:0);
(A2A1[1] => V[11]) = (0:0:0, 0:0:0);
(A2A1[1] => V[12]) = (0:0:0, 0:0:0);
(A2A1[1] => V[13]) = (0:0:0, 0:0:0);
(A2A1[1] => V[14]) = (0:0:0, 0:0:0);
(A2A1[1] => V[15]) = (0:0:0, 0:0:0);
(A2A1[1] => V[16]) = (0:0:0, 0:0:0);
(A2A1[1] => V[17]) = (0:0:0, 0:0:0);
(A2A1[1] => V[18]) = (0:0:0, 0:0:0);
(A2A1[1] => V[19]) = (0:0:0, 0:0:0);
(A2A1[1] => V[20]) = (0:0:0, 0:0:0);
(A2A1[1] => V[21]) = (0:0:0, 0:0:0);
(A2A1[1] => V[4]) = (0:0:0, 0:0:0);
(A2A1[1] => V[5]) = (0:0:0, 0:0:0);
(A2A1[1] => V[6]) = (0:0:0, 0:0:0);
(A2A1[1] => V[7]) = (0:0:0, 0:0:0);
(A2A1[1] => V[8]) = (0:0:0, 0:0:0);
(A2A1[1] => V[9]) = (0:0:0, 0:0:0);
(A2A1[20] => U[21]) = (0:0:0, 0:0:0);
(A2A1[20] => U[22]) = (0:0:0, 0:0:0);
(A2A1[20] => U[23]) = (0:0:0, 0:0:0);
(A2A1[20] => U[24]) = (0:0:0, 0:0:0);
(A2A1[20] => U[25]) = (0:0:0, 0:0:0);
(A2A1[20] => U[26]) = (0:0:0, 0:0:0);
(A2A1[20] => U[27]) = (0:0:0, 0:0:0);
(A2A1[20] => U[28]) = (0:0:0, 0:0:0);
(A2A1[20] => U[29]) = (0:0:0, 0:0:0);
(A2A1[20] => U[30]) = (0:0:0, 0:0:0);
(A2A1[20] => U[31]) = (0:0:0, 0:0:0);
(A2A1[20] => U[32]) = (0:0:0, 0:0:0);
(A2A1[20] => U[33]) = (0:0:0, 0:0:0);
(A2A1[20] => U[34]) = (0:0:0, 0:0:0);
(A2A1[20] => U[35]) = (0:0:0, 0:0:0);
(A2A1[20] => U[36]) = (0:0:0, 0:0:0);
(A2A1[20] => U[37]) = (0:0:0, 0:0:0);
(A2A1[20] => U[38]) = (0:0:0, 0:0:0);
(A2A1[20] => U[39]) = (0:0:0, 0:0:0);
(A2A1[20] => V[20]) = (0:0:0, 0:0:0);
(A2A1[20] => V[21]) = (0:0:0, 0:0:0);
(A2A1[20] => V[22]) = (0:0:0, 0:0:0);
(A2A1[20] => V[23]) = (0:0:0, 0:0:0);
(A2A1[20] => V[24]) = (0:0:0, 0:0:0);
(A2A1[20] => V[25]) = (0:0:0, 0:0:0);
(A2A1[20] => V[26]) = (0:0:0, 0:0:0);
(A2A1[20] => V[27]) = (0:0:0, 0:0:0);
(A2A1[20] => V[28]) = (0:0:0, 0:0:0);
(A2A1[20] => V[29]) = (0:0:0, 0:0:0);
(A2A1[20] => V[30]) = (0:0:0, 0:0:0);
(A2A1[20] => V[31]) = (0:0:0, 0:0:0);
(A2A1[20] => V[32]) = (0:0:0, 0:0:0);
(A2A1[20] => V[33]) = (0:0:0, 0:0:0);
(A2A1[20] => V[34]) = (0:0:0, 0:0:0);
(A2A1[20] => V[35]) = (0:0:0, 0:0:0);
(A2A1[20] => V[36]) = (0:0:0, 0:0:0);
(A2A1[20] => V[37]) = (0:0:0, 0:0:0);
(A2A1[20] => V[38]) = (0:0:0, 0:0:0);
(A2A1[21] => U[22]) = (0:0:0, 0:0:0);
(A2A1[21] => U[23]) = (0:0:0, 0:0:0);
(A2A1[21] => U[24]) = (0:0:0, 0:0:0);
(A2A1[21] => U[25]) = (0:0:0, 0:0:0);
(A2A1[21] => U[26]) = (0:0:0, 0:0:0);
(A2A1[21] => U[27]) = (0:0:0, 0:0:0);
(A2A1[21] => U[28]) = (0:0:0, 0:0:0);
(A2A1[21] => U[29]) = (0:0:0, 0:0:0);
(A2A1[21] => U[30]) = (0:0:0, 0:0:0);
(A2A1[21] => U[31]) = (0:0:0, 0:0:0);
(A2A1[21] => U[32]) = (0:0:0, 0:0:0);
(A2A1[21] => U[33]) = (0:0:0, 0:0:0);
(A2A1[21] => U[34]) = (0:0:0, 0:0:0);
(A2A1[21] => U[35]) = (0:0:0, 0:0:0);
(A2A1[21] => U[36]) = (0:0:0, 0:0:0);
(A2A1[21] => U[37]) = (0:0:0, 0:0:0);
(A2A1[21] => U[38]) = (0:0:0, 0:0:0);
(A2A1[21] => U[39]) = (0:0:0, 0:0:0);
(A2A1[21] => U[40]) = (0:0:0, 0:0:0);
(A2A1[21] => V[21]) = (0:0:0, 0:0:0);
(A2A1[21] => V[22]) = (0:0:0, 0:0:0);
(A2A1[21] => V[23]) = (0:0:0, 0:0:0);
(A2A1[21] => V[24]) = (0:0:0, 0:0:0);
(A2A1[21] => V[25]) = (0:0:0, 0:0:0);
(A2A1[21] => V[26]) = (0:0:0, 0:0:0);
(A2A1[21] => V[27]) = (0:0:0, 0:0:0);
(A2A1[21] => V[28]) = (0:0:0, 0:0:0);
(A2A1[21] => V[29]) = (0:0:0, 0:0:0);
(A2A1[21] => V[30]) = (0:0:0, 0:0:0);
(A2A1[21] => V[31]) = (0:0:0, 0:0:0);
(A2A1[21] => V[32]) = (0:0:0, 0:0:0);
(A2A1[21] => V[33]) = (0:0:0, 0:0:0);
(A2A1[21] => V[34]) = (0:0:0, 0:0:0);
(A2A1[21] => V[35]) = (0:0:0, 0:0:0);
(A2A1[21] => V[36]) = (0:0:0, 0:0:0);
(A2A1[21] => V[37]) = (0:0:0, 0:0:0);
(A2A1[21] => V[38]) = (0:0:0, 0:0:0);
(A2A1[21] => V[39]) = (0:0:0, 0:0:0);
(A2A1[22] => U[23]) = (0:0:0, 0:0:0);
(A2A1[22] => U[24]) = (0:0:0, 0:0:0);
(A2A1[22] => U[25]) = (0:0:0, 0:0:0);
(A2A1[22] => U[26]) = (0:0:0, 0:0:0);
(A2A1[22] => U[27]) = (0:0:0, 0:0:0);
(A2A1[22] => U[28]) = (0:0:0, 0:0:0);
(A2A1[22] => U[29]) = (0:0:0, 0:0:0);
(A2A1[22] => U[30]) = (0:0:0, 0:0:0);
(A2A1[22] => U[31]) = (0:0:0, 0:0:0);
(A2A1[22] => U[32]) = (0:0:0, 0:0:0);
(A2A1[22] => U[33]) = (0:0:0, 0:0:0);
(A2A1[22] => U[34]) = (0:0:0, 0:0:0);
(A2A1[22] => U[35]) = (0:0:0, 0:0:0);
(A2A1[22] => U[36]) = (0:0:0, 0:0:0);
(A2A1[22] => U[37]) = (0:0:0, 0:0:0);
(A2A1[22] => U[38]) = (0:0:0, 0:0:0);
(A2A1[22] => U[39]) = (0:0:0, 0:0:0);
(A2A1[22] => U[40]) = (0:0:0, 0:0:0);
(A2A1[22] => U[41]) = (0:0:0, 0:0:0);
(A2A1[22] => V[22]) = (0:0:0, 0:0:0);
(A2A1[22] => V[23]) = (0:0:0, 0:0:0);
(A2A1[22] => V[24]) = (0:0:0, 0:0:0);
(A2A1[22] => V[25]) = (0:0:0, 0:0:0);
(A2A1[22] => V[26]) = (0:0:0, 0:0:0);
(A2A1[22] => V[27]) = (0:0:0, 0:0:0);
(A2A1[22] => V[28]) = (0:0:0, 0:0:0);
(A2A1[22] => V[29]) = (0:0:0, 0:0:0);
(A2A1[22] => V[30]) = (0:0:0, 0:0:0);
(A2A1[22] => V[31]) = (0:0:0, 0:0:0);
(A2A1[22] => V[32]) = (0:0:0, 0:0:0);
(A2A1[22] => V[33]) = (0:0:0, 0:0:0);
(A2A1[22] => V[34]) = (0:0:0, 0:0:0);
(A2A1[22] => V[35]) = (0:0:0, 0:0:0);
(A2A1[22] => V[36]) = (0:0:0, 0:0:0);
(A2A1[22] => V[37]) = (0:0:0, 0:0:0);
(A2A1[22] => V[38]) = (0:0:0, 0:0:0);
(A2A1[22] => V[39]) = (0:0:0, 0:0:0);
(A2A1[22] => V[40]) = (0:0:0, 0:0:0);
(A2A1[23] => U[24]) = (0:0:0, 0:0:0);
(A2A1[23] => U[25]) = (0:0:0, 0:0:0);
(A2A1[23] => U[26]) = (0:0:0, 0:0:0);
(A2A1[23] => U[27]) = (0:0:0, 0:0:0);
(A2A1[23] => U[28]) = (0:0:0, 0:0:0);
(A2A1[23] => U[29]) = (0:0:0, 0:0:0);
(A2A1[23] => U[30]) = (0:0:0, 0:0:0);
(A2A1[23] => U[31]) = (0:0:0, 0:0:0);
(A2A1[23] => U[32]) = (0:0:0, 0:0:0);
(A2A1[23] => U[33]) = (0:0:0, 0:0:0);
(A2A1[23] => U[34]) = (0:0:0, 0:0:0);
(A2A1[23] => U[35]) = (0:0:0, 0:0:0);
(A2A1[23] => U[36]) = (0:0:0, 0:0:0);
(A2A1[23] => U[37]) = (0:0:0, 0:0:0);
(A2A1[23] => U[38]) = (0:0:0, 0:0:0);
(A2A1[23] => U[39]) = (0:0:0, 0:0:0);
(A2A1[23] => U[40]) = (0:0:0, 0:0:0);
(A2A1[23] => U[41]) = (0:0:0, 0:0:0);
(A2A1[23] => U[42]) = (0:0:0, 0:0:0);
(A2A1[23] => V[23]) = (0:0:0, 0:0:0);
(A2A1[23] => V[24]) = (0:0:0, 0:0:0);
(A2A1[23] => V[25]) = (0:0:0, 0:0:0);
(A2A1[23] => V[26]) = (0:0:0, 0:0:0);
(A2A1[23] => V[27]) = (0:0:0, 0:0:0);
(A2A1[23] => V[28]) = (0:0:0, 0:0:0);
(A2A1[23] => V[29]) = (0:0:0, 0:0:0);
(A2A1[23] => V[30]) = (0:0:0, 0:0:0);
(A2A1[23] => V[31]) = (0:0:0, 0:0:0);
(A2A1[23] => V[32]) = (0:0:0, 0:0:0);
(A2A1[23] => V[33]) = (0:0:0, 0:0:0);
(A2A1[23] => V[34]) = (0:0:0, 0:0:0);
(A2A1[23] => V[35]) = (0:0:0, 0:0:0);
(A2A1[23] => V[36]) = (0:0:0, 0:0:0);
(A2A1[23] => V[37]) = (0:0:0, 0:0:0);
(A2A1[23] => V[38]) = (0:0:0, 0:0:0);
(A2A1[23] => V[39]) = (0:0:0, 0:0:0);
(A2A1[23] => V[40]) = (0:0:0, 0:0:0);
(A2A1[23] => V[41]) = (0:0:0, 0:0:0);
(A2A1[24] => U[25]) = (0:0:0, 0:0:0);
(A2A1[24] => U[26]) = (0:0:0, 0:0:0);
(A2A1[24] => U[27]) = (0:0:0, 0:0:0);
(A2A1[24] => U[28]) = (0:0:0, 0:0:0);
(A2A1[24] => U[29]) = (0:0:0, 0:0:0);
(A2A1[24] => U[30]) = (0:0:0, 0:0:0);
(A2A1[24] => U[31]) = (0:0:0, 0:0:0);
(A2A1[24] => U[32]) = (0:0:0, 0:0:0);
(A2A1[24] => U[33]) = (0:0:0, 0:0:0);
(A2A1[24] => U[34]) = (0:0:0, 0:0:0);
(A2A1[24] => U[35]) = (0:0:0, 0:0:0);
(A2A1[24] => U[36]) = (0:0:0, 0:0:0);
(A2A1[24] => U[37]) = (0:0:0, 0:0:0);
(A2A1[24] => U[38]) = (0:0:0, 0:0:0);
(A2A1[24] => U[39]) = (0:0:0, 0:0:0);
(A2A1[24] => U[40]) = (0:0:0, 0:0:0);
(A2A1[24] => U[41]) = (0:0:0, 0:0:0);
(A2A1[24] => U[42]) = (0:0:0, 0:0:0);
(A2A1[24] => V[24]) = (0:0:0, 0:0:0);
(A2A1[24] => V[25]) = (0:0:0, 0:0:0);
(A2A1[24] => V[26]) = (0:0:0, 0:0:0);
(A2A1[24] => V[27]) = (0:0:0, 0:0:0);
(A2A1[24] => V[28]) = (0:0:0, 0:0:0);
(A2A1[24] => V[29]) = (0:0:0, 0:0:0);
(A2A1[24] => V[30]) = (0:0:0, 0:0:0);
(A2A1[24] => V[31]) = (0:0:0, 0:0:0);
(A2A1[24] => V[32]) = (0:0:0, 0:0:0);
(A2A1[24] => V[33]) = (0:0:0, 0:0:0);
(A2A1[24] => V[34]) = (0:0:0, 0:0:0);
(A2A1[24] => V[35]) = (0:0:0, 0:0:0);
(A2A1[24] => V[36]) = (0:0:0, 0:0:0);
(A2A1[24] => V[37]) = (0:0:0, 0:0:0);
(A2A1[24] => V[38]) = (0:0:0, 0:0:0);
(A2A1[24] => V[39]) = (0:0:0, 0:0:0);
(A2A1[24] => V[40]) = (0:0:0, 0:0:0);
(A2A1[24] => V[41]) = (0:0:0, 0:0:0);
(A2A1[25] => U[26]) = (0:0:0, 0:0:0);
(A2A1[25] => U[27]) = (0:0:0, 0:0:0);
(A2A1[25] => U[28]) = (0:0:0, 0:0:0);
(A2A1[25] => U[29]) = (0:0:0, 0:0:0);
(A2A1[25] => U[30]) = (0:0:0, 0:0:0);
(A2A1[25] => U[31]) = (0:0:0, 0:0:0);
(A2A1[25] => U[32]) = (0:0:0, 0:0:0);
(A2A1[25] => U[33]) = (0:0:0, 0:0:0);
(A2A1[25] => U[34]) = (0:0:0, 0:0:0);
(A2A1[25] => U[35]) = (0:0:0, 0:0:0);
(A2A1[25] => U[36]) = (0:0:0, 0:0:0);
(A2A1[25] => U[37]) = (0:0:0, 0:0:0);
(A2A1[25] => U[38]) = (0:0:0, 0:0:0);
(A2A1[25] => U[39]) = (0:0:0, 0:0:0);
(A2A1[25] => U[40]) = (0:0:0, 0:0:0);
(A2A1[25] => U[41]) = (0:0:0, 0:0:0);
(A2A1[25] => U[42]) = (0:0:0, 0:0:0);
(A2A1[25] => U[43]) = (0:0:0, 0:0:0);
(A2A1[25] => V[25]) = (0:0:0, 0:0:0);
(A2A1[25] => V[26]) = (0:0:0, 0:0:0);
(A2A1[25] => V[27]) = (0:0:0, 0:0:0);
(A2A1[25] => V[28]) = (0:0:0, 0:0:0);
(A2A1[25] => V[29]) = (0:0:0, 0:0:0);
(A2A1[25] => V[30]) = (0:0:0, 0:0:0);
(A2A1[25] => V[31]) = (0:0:0, 0:0:0);
(A2A1[25] => V[32]) = (0:0:0, 0:0:0);
(A2A1[25] => V[33]) = (0:0:0, 0:0:0);
(A2A1[25] => V[34]) = (0:0:0, 0:0:0);
(A2A1[25] => V[35]) = (0:0:0, 0:0:0);
(A2A1[25] => V[36]) = (0:0:0, 0:0:0);
(A2A1[25] => V[37]) = (0:0:0, 0:0:0);
(A2A1[25] => V[38]) = (0:0:0, 0:0:0);
(A2A1[25] => V[39]) = (0:0:0, 0:0:0);
(A2A1[25] => V[40]) = (0:0:0, 0:0:0);
(A2A1[25] => V[41]) = (0:0:0, 0:0:0);
(A2A1[25] => V[42]) = (0:0:0, 0:0:0);
(A2A1[26] => AMULT26) = (0:0:0, 0:0:0);
(A2A1[26] => U[27]) = (0:0:0, 0:0:0);
(A2A1[26] => U[28]) = (0:0:0, 0:0:0);
(A2A1[26] => U[29]) = (0:0:0, 0:0:0);
(A2A1[26] => U[30]) = (0:0:0, 0:0:0);
(A2A1[26] => U[31]) = (0:0:0, 0:0:0);
(A2A1[26] => U[32]) = (0:0:0, 0:0:0);
(A2A1[26] => U[33]) = (0:0:0, 0:0:0);
(A2A1[26] => U[34]) = (0:0:0, 0:0:0);
(A2A1[26] => U[35]) = (0:0:0, 0:0:0);
(A2A1[26] => U[36]) = (0:0:0, 0:0:0);
(A2A1[26] => U[37]) = (0:0:0, 0:0:0);
(A2A1[26] => U[38]) = (0:0:0, 0:0:0);
(A2A1[26] => U[39]) = (0:0:0, 0:0:0);
(A2A1[26] => U[40]) = (0:0:0, 0:0:0);
(A2A1[26] => U[41]) = (0:0:0, 0:0:0);
(A2A1[26] => U[42]) = (0:0:0, 0:0:0);
(A2A1[26] => U[43]) = (0:0:0, 0:0:0);
(A2A1[26] => V[26]) = (0:0:0, 0:0:0);
(A2A1[26] => V[27]) = (0:0:0, 0:0:0);
(A2A1[26] => V[28]) = (0:0:0, 0:0:0);
(A2A1[26] => V[29]) = (0:0:0, 0:0:0);
(A2A1[26] => V[30]) = (0:0:0, 0:0:0);
(A2A1[26] => V[31]) = (0:0:0, 0:0:0);
(A2A1[26] => V[32]) = (0:0:0, 0:0:0);
(A2A1[26] => V[33]) = (0:0:0, 0:0:0);
(A2A1[26] => V[34]) = (0:0:0, 0:0:0);
(A2A1[26] => V[35]) = (0:0:0, 0:0:0);
(A2A1[26] => V[36]) = (0:0:0, 0:0:0);
(A2A1[26] => V[37]) = (0:0:0, 0:0:0);
(A2A1[26] => V[38]) = (0:0:0, 0:0:0);
(A2A1[26] => V[39]) = (0:0:0, 0:0:0);
(A2A1[26] => V[40]) = (0:0:0, 0:0:0);
(A2A1[26] => V[41]) = (0:0:0, 0:0:0);
(A2A1[26] => V[42]) = (0:0:0, 0:0:0);
(A2A1[26] => V[43]) = (0:0:0, 0:0:0);
(A2A1[2] => U[10]) = (0:0:0, 0:0:0);
(A2A1[2] => U[11]) = (0:0:0, 0:0:0);
(A2A1[2] => U[12]) = (0:0:0, 0:0:0);
(A2A1[2] => U[13]) = (0:0:0, 0:0:0);
(A2A1[2] => U[14]) = (0:0:0, 0:0:0);
(A2A1[2] => U[15]) = (0:0:0, 0:0:0);
(A2A1[2] => U[16]) = (0:0:0, 0:0:0);
(A2A1[2] => U[17]) = (0:0:0, 0:0:0);
(A2A1[2] => U[18]) = (0:0:0, 0:0:0);
(A2A1[2] => U[19]) = (0:0:0, 0:0:0);
(A2A1[2] => U[20]) = (0:0:0, 0:0:0);
(A2A1[2] => U[21]) = (0:0:0, 0:0:0);
(A2A1[2] => U[22]) = (0:0:0, 0:0:0);
(A2A1[2] => U[23]) = (0:0:0, 0:0:0);
(A2A1[2] => U[2]) = (0:0:0, 0:0:0);
(A2A1[2] => U[3]) = (0:0:0, 0:0:0);
(A2A1[2] => U[4]) = (0:0:0, 0:0:0);
(A2A1[2] => U[5]) = (0:0:0, 0:0:0);
(A2A1[2] => U[6]) = (0:0:0, 0:0:0);
(A2A1[2] => U[7]) = (0:0:0, 0:0:0);
(A2A1[2] => U[8]) = (0:0:0, 0:0:0);
(A2A1[2] => U[9]) = (0:0:0, 0:0:0);
(A2A1[2] => V[10]) = (0:0:0, 0:0:0);
(A2A1[2] => V[11]) = (0:0:0, 0:0:0);
(A2A1[2] => V[12]) = (0:0:0, 0:0:0);
(A2A1[2] => V[13]) = (0:0:0, 0:0:0);
(A2A1[2] => V[14]) = (0:0:0, 0:0:0);
(A2A1[2] => V[15]) = (0:0:0, 0:0:0);
(A2A1[2] => V[16]) = (0:0:0, 0:0:0);
(A2A1[2] => V[17]) = (0:0:0, 0:0:0);
(A2A1[2] => V[18]) = (0:0:0, 0:0:0);
(A2A1[2] => V[19]) = (0:0:0, 0:0:0);
(A2A1[2] => V[20]) = (0:0:0, 0:0:0);
(A2A1[2] => V[21]) = (0:0:0, 0:0:0);
(A2A1[2] => V[22]) = (0:0:0, 0:0:0);
(A2A1[2] => V[4]) = (0:0:0, 0:0:0);
(A2A1[2] => V[5]) = (0:0:0, 0:0:0);
(A2A1[2] => V[6]) = (0:0:0, 0:0:0);
(A2A1[2] => V[7]) = (0:0:0, 0:0:0);
(A2A1[2] => V[8]) = (0:0:0, 0:0:0);
(A2A1[2] => V[9]) = (0:0:0, 0:0:0);
(A2A1[3] => U[10]) = (0:0:0, 0:0:0);
(A2A1[3] => U[11]) = (0:0:0, 0:0:0);
(A2A1[3] => U[12]) = (0:0:0, 0:0:0);
(A2A1[3] => U[13]) = (0:0:0, 0:0:0);
(A2A1[3] => U[14]) = (0:0:0, 0:0:0);
(A2A1[3] => U[15]) = (0:0:0, 0:0:0);
(A2A1[3] => U[16]) = (0:0:0, 0:0:0);
(A2A1[3] => U[17]) = (0:0:0, 0:0:0);
(A2A1[3] => U[18]) = (0:0:0, 0:0:0);
(A2A1[3] => U[19]) = (0:0:0, 0:0:0);
(A2A1[3] => U[20]) = (0:0:0, 0:0:0);
(A2A1[3] => U[21]) = (0:0:0, 0:0:0);
(A2A1[3] => U[22]) = (0:0:0, 0:0:0);
(A2A1[3] => U[23]) = (0:0:0, 0:0:0);
(A2A1[3] => U[24]) = (0:0:0, 0:0:0);
(A2A1[3] => U[3]) = (0:0:0, 0:0:0);
(A2A1[3] => U[4]) = (0:0:0, 0:0:0);
(A2A1[3] => U[5]) = (0:0:0, 0:0:0);
(A2A1[3] => U[6]) = (0:0:0, 0:0:0);
(A2A1[3] => U[7]) = (0:0:0, 0:0:0);
(A2A1[3] => U[8]) = (0:0:0, 0:0:0);
(A2A1[3] => U[9]) = (0:0:0, 0:0:0);
(A2A1[3] => V[10]) = (0:0:0, 0:0:0);
(A2A1[3] => V[11]) = (0:0:0, 0:0:0);
(A2A1[3] => V[12]) = (0:0:0, 0:0:0);
(A2A1[3] => V[13]) = (0:0:0, 0:0:0);
(A2A1[3] => V[14]) = (0:0:0, 0:0:0);
(A2A1[3] => V[15]) = (0:0:0, 0:0:0);
(A2A1[3] => V[16]) = (0:0:0, 0:0:0);
(A2A1[3] => V[17]) = (0:0:0, 0:0:0);
(A2A1[3] => V[18]) = (0:0:0, 0:0:0);
(A2A1[3] => V[19]) = (0:0:0, 0:0:0);
(A2A1[3] => V[20]) = (0:0:0, 0:0:0);
(A2A1[3] => V[21]) = (0:0:0, 0:0:0);
(A2A1[3] => V[22]) = (0:0:0, 0:0:0);
(A2A1[3] => V[23]) = (0:0:0, 0:0:0);
(A2A1[3] => V[4]) = (0:0:0, 0:0:0);
(A2A1[3] => V[5]) = (0:0:0, 0:0:0);
(A2A1[3] => V[6]) = (0:0:0, 0:0:0);
(A2A1[3] => V[7]) = (0:0:0, 0:0:0);
(A2A1[3] => V[8]) = (0:0:0, 0:0:0);
(A2A1[3] => V[9]) = (0:0:0, 0:0:0);
(A2A1[4] => U[10]) = (0:0:0, 0:0:0);
(A2A1[4] => U[11]) = (0:0:0, 0:0:0);
(A2A1[4] => U[12]) = (0:0:0, 0:0:0);
(A2A1[4] => U[13]) = (0:0:0, 0:0:0);
(A2A1[4] => U[14]) = (0:0:0, 0:0:0);
(A2A1[4] => U[15]) = (0:0:0, 0:0:0);
(A2A1[4] => U[16]) = (0:0:0, 0:0:0);
(A2A1[4] => U[17]) = (0:0:0, 0:0:0);
(A2A1[4] => U[18]) = (0:0:0, 0:0:0);
(A2A1[4] => U[19]) = (0:0:0, 0:0:0);
(A2A1[4] => U[20]) = (0:0:0, 0:0:0);
(A2A1[4] => U[21]) = (0:0:0, 0:0:0);
(A2A1[4] => U[22]) = (0:0:0, 0:0:0);
(A2A1[4] => U[23]) = (0:0:0, 0:0:0);
(A2A1[4] => U[24]) = (0:0:0, 0:0:0);
(A2A1[4] => U[25]) = (0:0:0, 0:0:0);
(A2A1[4] => U[5]) = (0:0:0, 0:0:0);
(A2A1[4] => U[6]) = (0:0:0, 0:0:0);
(A2A1[4] => U[7]) = (0:0:0, 0:0:0);
(A2A1[4] => U[8]) = (0:0:0, 0:0:0);
(A2A1[4] => U[9]) = (0:0:0, 0:0:0);
(A2A1[4] => V[10]) = (0:0:0, 0:0:0);
(A2A1[4] => V[11]) = (0:0:0, 0:0:0);
(A2A1[4] => V[12]) = (0:0:0, 0:0:0);
(A2A1[4] => V[13]) = (0:0:0, 0:0:0);
(A2A1[4] => V[14]) = (0:0:0, 0:0:0);
(A2A1[4] => V[15]) = (0:0:0, 0:0:0);
(A2A1[4] => V[16]) = (0:0:0, 0:0:0);
(A2A1[4] => V[17]) = (0:0:0, 0:0:0);
(A2A1[4] => V[18]) = (0:0:0, 0:0:0);
(A2A1[4] => V[19]) = (0:0:0, 0:0:0);
(A2A1[4] => V[20]) = (0:0:0, 0:0:0);
(A2A1[4] => V[21]) = (0:0:0, 0:0:0);
(A2A1[4] => V[22]) = (0:0:0, 0:0:0);
(A2A1[4] => V[23]) = (0:0:0, 0:0:0);
(A2A1[4] => V[24]) = (0:0:0, 0:0:0);
(A2A1[4] => V[4]) = (0:0:0, 0:0:0);
(A2A1[4] => V[5]) = (0:0:0, 0:0:0);
(A2A1[4] => V[6]) = (0:0:0, 0:0:0);
(A2A1[4] => V[7]) = (0:0:0, 0:0:0);
(A2A1[4] => V[8]) = (0:0:0, 0:0:0);
(A2A1[4] => V[9]) = (0:0:0, 0:0:0);
(A2A1[5] => U[10]) = (0:0:0, 0:0:0);
(A2A1[5] => U[11]) = (0:0:0, 0:0:0);
(A2A1[5] => U[12]) = (0:0:0, 0:0:0);
(A2A1[5] => U[13]) = (0:0:0, 0:0:0);
(A2A1[5] => U[14]) = (0:0:0, 0:0:0);
(A2A1[5] => U[15]) = (0:0:0, 0:0:0);
(A2A1[5] => U[16]) = (0:0:0, 0:0:0);
(A2A1[5] => U[17]) = (0:0:0, 0:0:0);
(A2A1[5] => U[18]) = (0:0:0, 0:0:0);
(A2A1[5] => U[19]) = (0:0:0, 0:0:0);
(A2A1[5] => U[20]) = (0:0:0, 0:0:0);
(A2A1[5] => U[21]) = (0:0:0, 0:0:0);
(A2A1[5] => U[22]) = (0:0:0, 0:0:0);
(A2A1[5] => U[23]) = (0:0:0, 0:0:0);
(A2A1[5] => U[24]) = (0:0:0, 0:0:0);
(A2A1[5] => U[25]) = (0:0:0, 0:0:0);
(A2A1[5] => U[26]) = (0:0:0, 0:0:0);
(A2A1[5] => U[6]) = (0:0:0, 0:0:0);
(A2A1[5] => U[7]) = (0:0:0, 0:0:0);
(A2A1[5] => U[8]) = (0:0:0, 0:0:0);
(A2A1[5] => U[9]) = (0:0:0, 0:0:0);
(A2A1[5] => V[10]) = (0:0:0, 0:0:0);
(A2A1[5] => V[11]) = (0:0:0, 0:0:0);
(A2A1[5] => V[12]) = (0:0:0, 0:0:0);
(A2A1[5] => V[13]) = (0:0:0, 0:0:0);
(A2A1[5] => V[14]) = (0:0:0, 0:0:0);
(A2A1[5] => V[15]) = (0:0:0, 0:0:0);
(A2A1[5] => V[16]) = (0:0:0, 0:0:0);
(A2A1[5] => V[17]) = (0:0:0, 0:0:0);
(A2A1[5] => V[18]) = (0:0:0, 0:0:0);
(A2A1[5] => V[19]) = (0:0:0, 0:0:0);
(A2A1[5] => V[20]) = (0:0:0, 0:0:0);
(A2A1[5] => V[21]) = (0:0:0, 0:0:0);
(A2A1[5] => V[22]) = (0:0:0, 0:0:0);
(A2A1[5] => V[23]) = (0:0:0, 0:0:0);
(A2A1[5] => V[24]) = (0:0:0, 0:0:0);
(A2A1[5] => V[25]) = (0:0:0, 0:0:0);
(A2A1[5] => V[5]) = (0:0:0, 0:0:0);
(A2A1[5] => V[6]) = (0:0:0, 0:0:0);
(A2A1[5] => V[7]) = (0:0:0, 0:0:0);
(A2A1[5] => V[8]) = (0:0:0, 0:0:0);
(A2A1[5] => V[9]) = (0:0:0, 0:0:0);
(A2A1[6] => U[10]) = (0:0:0, 0:0:0);
(A2A1[6] => U[11]) = (0:0:0, 0:0:0);
(A2A1[6] => U[12]) = (0:0:0, 0:0:0);
(A2A1[6] => U[13]) = (0:0:0, 0:0:0);
(A2A1[6] => U[14]) = (0:0:0, 0:0:0);
(A2A1[6] => U[15]) = (0:0:0, 0:0:0);
(A2A1[6] => U[16]) = (0:0:0, 0:0:0);
(A2A1[6] => U[17]) = (0:0:0, 0:0:0);
(A2A1[6] => U[18]) = (0:0:0, 0:0:0);
(A2A1[6] => U[19]) = (0:0:0, 0:0:0);
(A2A1[6] => U[20]) = (0:0:0, 0:0:0);
(A2A1[6] => U[21]) = (0:0:0, 0:0:0);
(A2A1[6] => U[22]) = (0:0:0, 0:0:0);
(A2A1[6] => U[23]) = (0:0:0, 0:0:0);
(A2A1[6] => U[24]) = (0:0:0, 0:0:0);
(A2A1[6] => U[25]) = (0:0:0, 0:0:0);
(A2A1[6] => U[26]) = (0:0:0, 0:0:0);
(A2A1[6] => U[27]) = (0:0:0, 0:0:0);
(A2A1[6] => U[7]) = (0:0:0, 0:0:0);
(A2A1[6] => U[8]) = (0:0:0, 0:0:0);
(A2A1[6] => U[9]) = (0:0:0, 0:0:0);
(A2A1[6] => V[10]) = (0:0:0, 0:0:0);
(A2A1[6] => V[11]) = (0:0:0, 0:0:0);
(A2A1[6] => V[12]) = (0:0:0, 0:0:0);
(A2A1[6] => V[13]) = (0:0:0, 0:0:0);
(A2A1[6] => V[14]) = (0:0:0, 0:0:0);
(A2A1[6] => V[15]) = (0:0:0, 0:0:0);
(A2A1[6] => V[16]) = (0:0:0, 0:0:0);
(A2A1[6] => V[17]) = (0:0:0, 0:0:0);
(A2A1[6] => V[18]) = (0:0:0, 0:0:0);
(A2A1[6] => V[19]) = (0:0:0, 0:0:0);
(A2A1[6] => V[20]) = (0:0:0, 0:0:0);
(A2A1[6] => V[21]) = (0:0:0, 0:0:0);
(A2A1[6] => V[22]) = (0:0:0, 0:0:0);
(A2A1[6] => V[23]) = (0:0:0, 0:0:0);
(A2A1[6] => V[24]) = (0:0:0, 0:0:0);
(A2A1[6] => V[25]) = (0:0:0, 0:0:0);
(A2A1[6] => V[26]) = (0:0:0, 0:0:0);
(A2A1[6] => V[6]) = (0:0:0, 0:0:0);
(A2A1[6] => V[7]) = (0:0:0, 0:0:0);
(A2A1[6] => V[8]) = (0:0:0, 0:0:0);
(A2A1[6] => V[9]) = (0:0:0, 0:0:0);
(A2A1[7] => U[10]) = (0:0:0, 0:0:0);
(A2A1[7] => U[11]) = (0:0:0, 0:0:0);
(A2A1[7] => U[12]) = (0:0:0, 0:0:0);
(A2A1[7] => U[13]) = (0:0:0, 0:0:0);
(A2A1[7] => U[14]) = (0:0:0, 0:0:0);
(A2A1[7] => U[15]) = (0:0:0, 0:0:0);
(A2A1[7] => U[16]) = (0:0:0, 0:0:0);
(A2A1[7] => U[17]) = (0:0:0, 0:0:0);
(A2A1[7] => U[18]) = (0:0:0, 0:0:0);
(A2A1[7] => U[19]) = (0:0:0, 0:0:0);
(A2A1[7] => U[20]) = (0:0:0, 0:0:0);
(A2A1[7] => U[21]) = (0:0:0, 0:0:0);
(A2A1[7] => U[22]) = (0:0:0, 0:0:0);
(A2A1[7] => U[23]) = (0:0:0, 0:0:0);
(A2A1[7] => U[24]) = (0:0:0, 0:0:0);
(A2A1[7] => U[25]) = (0:0:0, 0:0:0);
(A2A1[7] => U[26]) = (0:0:0, 0:0:0);
(A2A1[7] => U[27]) = (0:0:0, 0:0:0);
(A2A1[7] => U[28]) = (0:0:0, 0:0:0);
(A2A1[7] => U[8]) = (0:0:0, 0:0:0);
(A2A1[7] => U[9]) = (0:0:0, 0:0:0);
(A2A1[7] => V[10]) = (0:0:0, 0:0:0);
(A2A1[7] => V[11]) = (0:0:0, 0:0:0);
(A2A1[7] => V[12]) = (0:0:0, 0:0:0);
(A2A1[7] => V[13]) = (0:0:0, 0:0:0);
(A2A1[7] => V[14]) = (0:0:0, 0:0:0);
(A2A1[7] => V[15]) = (0:0:0, 0:0:0);
(A2A1[7] => V[16]) = (0:0:0, 0:0:0);
(A2A1[7] => V[17]) = (0:0:0, 0:0:0);
(A2A1[7] => V[18]) = (0:0:0, 0:0:0);
(A2A1[7] => V[19]) = (0:0:0, 0:0:0);
(A2A1[7] => V[20]) = (0:0:0, 0:0:0);
(A2A1[7] => V[21]) = (0:0:0, 0:0:0);
(A2A1[7] => V[22]) = (0:0:0, 0:0:0);
(A2A1[7] => V[23]) = (0:0:0, 0:0:0);
(A2A1[7] => V[24]) = (0:0:0, 0:0:0);
(A2A1[7] => V[25]) = (0:0:0, 0:0:0);
(A2A1[7] => V[26]) = (0:0:0, 0:0:0);
(A2A1[7] => V[27]) = (0:0:0, 0:0:0);
(A2A1[7] => V[7]) = (0:0:0, 0:0:0);
(A2A1[7] => V[8]) = (0:0:0, 0:0:0);
(A2A1[7] => V[9]) = (0:0:0, 0:0:0);
(A2A1[8] => U[10]) = (0:0:0, 0:0:0);
(A2A1[8] => U[11]) = (0:0:0, 0:0:0);
(A2A1[8] => U[12]) = (0:0:0, 0:0:0);
(A2A1[8] => U[13]) = (0:0:0, 0:0:0);
(A2A1[8] => U[14]) = (0:0:0, 0:0:0);
(A2A1[8] => U[15]) = (0:0:0, 0:0:0);
(A2A1[8] => U[16]) = (0:0:0, 0:0:0);
(A2A1[8] => U[17]) = (0:0:0, 0:0:0);
(A2A1[8] => U[18]) = (0:0:0, 0:0:0);
(A2A1[8] => U[19]) = (0:0:0, 0:0:0);
(A2A1[8] => U[20]) = (0:0:0, 0:0:0);
(A2A1[8] => U[21]) = (0:0:0, 0:0:0);
(A2A1[8] => U[22]) = (0:0:0, 0:0:0);
(A2A1[8] => U[23]) = (0:0:0, 0:0:0);
(A2A1[8] => U[24]) = (0:0:0, 0:0:0);
(A2A1[8] => U[25]) = (0:0:0, 0:0:0);
(A2A1[8] => U[26]) = (0:0:0, 0:0:0);
(A2A1[8] => U[27]) = (0:0:0, 0:0:0);
(A2A1[8] => U[28]) = (0:0:0, 0:0:0);
(A2A1[8] => U[29]) = (0:0:0, 0:0:0);
(A2A1[8] => U[9]) = (0:0:0, 0:0:0);
(A2A1[8] => V[10]) = (0:0:0, 0:0:0);
(A2A1[8] => V[11]) = (0:0:0, 0:0:0);
(A2A1[8] => V[12]) = (0:0:0, 0:0:0);
(A2A1[8] => V[13]) = (0:0:0, 0:0:0);
(A2A1[8] => V[14]) = (0:0:0, 0:0:0);
(A2A1[8] => V[15]) = (0:0:0, 0:0:0);
(A2A1[8] => V[16]) = (0:0:0, 0:0:0);
(A2A1[8] => V[17]) = (0:0:0, 0:0:0);
(A2A1[8] => V[18]) = (0:0:0, 0:0:0);
(A2A1[8] => V[19]) = (0:0:0, 0:0:0);
(A2A1[8] => V[20]) = (0:0:0, 0:0:0);
(A2A1[8] => V[21]) = (0:0:0, 0:0:0);
(A2A1[8] => V[22]) = (0:0:0, 0:0:0);
(A2A1[8] => V[23]) = (0:0:0, 0:0:0);
(A2A1[8] => V[24]) = (0:0:0, 0:0:0);
(A2A1[8] => V[25]) = (0:0:0, 0:0:0);
(A2A1[8] => V[26]) = (0:0:0, 0:0:0);
(A2A1[8] => V[27]) = (0:0:0, 0:0:0);
(A2A1[8] => V[28]) = (0:0:0, 0:0:0);
(A2A1[8] => V[8]) = (0:0:0, 0:0:0);
(A2A1[8] => V[9]) = (0:0:0, 0:0:0);
(A2A1[9] => U[10]) = (0:0:0, 0:0:0);
(A2A1[9] => U[11]) = (0:0:0, 0:0:0);
(A2A1[9] => U[12]) = (0:0:0, 0:0:0);
(A2A1[9] => U[13]) = (0:0:0, 0:0:0);
(A2A1[9] => U[14]) = (0:0:0, 0:0:0);
(A2A1[9] => U[15]) = (0:0:0, 0:0:0);
(A2A1[9] => U[16]) = (0:0:0, 0:0:0);
(A2A1[9] => U[17]) = (0:0:0, 0:0:0);
(A2A1[9] => U[18]) = (0:0:0, 0:0:0);
(A2A1[9] => U[19]) = (0:0:0, 0:0:0);
(A2A1[9] => U[20]) = (0:0:0, 0:0:0);
(A2A1[9] => U[21]) = (0:0:0, 0:0:0);
(A2A1[9] => U[22]) = (0:0:0, 0:0:0);
(A2A1[9] => U[23]) = (0:0:0, 0:0:0);
(A2A1[9] => U[24]) = (0:0:0, 0:0:0);
(A2A1[9] => U[25]) = (0:0:0, 0:0:0);
(A2A1[9] => U[26]) = (0:0:0, 0:0:0);
(A2A1[9] => U[27]) = (0:0:0, 0:0:0);
(A2A1[9] => U[28]) = (0:0:0, 0:0:0);
(A2A1[9] => U[29]) = (0:0:0, 0:0:0);
(A2A1[9] => U[30]) = (0:0:0, 0:0:0);
(A2A1[9] => V[10]) = (0:0:0, 0:0:0);
(A2A1[9] => V[11]) = (0:0:0, 0:0:0);
(A2A1[9] => V[12]) = (0:0:0, 0:0:0);
(A2A1[9] => V[13]) = (0:0:0, 0:0:0);
(A2A1[9] => V[14]) = (0:0:0, 0:0:0);
(A2A1[9] => V[15]) = (0:0:0, 0:0:0);
(A2A1[9] => V[16]) = (0:0:0, 0:0:0);
(A2A1[9] => V[17]) = (0:0:0, 0:0:0);
(A2A1[9] => V[18]) = (0:0:0, 0:0:0);
(A2A1[9] => V[19]) = (0:0:0, 0:0:0);
(A2A1[9] => V[20]) = (0:0:0, 0:0:0);
(A2A1[9] => V[21]) = (0:0:0, 0:0:0);
(A2A1[9] => V[22]) = (0:0:0, 0:0:0);
(A2A1[9] => V[23]) = (0:0:0, 0:0:0);
(A2A1[9] => V[24]) = (0:0:0, 0:0:0);
(A2A1[9] => V[25]) = (0:0:0, 0:0:0);
(A2A1[9] => V[26]) = (0:0:0, 0:0:0);
(A2A1[9] => V[27]) = (0:0:0, 0:0:0);
(A2A1[9] => V[28]) = (0:0:0, 0:0:0);
(A2A1[9] => V[29]) = (0:0:0, 0:0:0);
(A2A1[9] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[1]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[0]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[17] => BMULT17) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[0]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[1]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[0]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => AMULT26) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[9]) = (0:0:0, 0:0:0);
(B2B1[0] => U[10]) = (0:0:0, 0:0:0);
(B2B1[0] => U[11]) = (0:0:0, 0:0:0);
(B2B1[0] => U[12]) = (0:0:0, 0:0:0);
(B2B1[0] => U[13]) = (0:0:0, 0:0:0);
(B2B1[0] => U[14]) = (0:0:0, 0:0:0);
(B2B1[0] => U[15]) = (0:0:0, 0:0:0);
(B2B1[0] => U[16]) = (0:0:0, 0:0:0);
(B2B1[0] => U[17]) = (0:0:0, 0:0:0);
(B2B1[0] => U[18]) = (0:0:0, 0:0:0);
(B2B1[0] => U[19]) = (0:0:0, 0:0:0);
(B2B1[0] => U[1]) = (0:0:0, 0:0:0);
(B2B1[0] => U[20]) = (0:0:0, 0:0:0);
(B2B1[0] => U[21]) = (0:0:0, 0:0:0);
(B2B1[0] => U[22]) = (0:0:0, 0:0:0);
(B2B1[0] => U[23]) = (0:0:0, 0:0:0);
(B2B1[0] => U[24]) = (0:0:0, 0:0:0);
(B2B1[0] => U[25]) = (0:0:0, 0:0:0);
(B2B1[0] => U[26]) = (0:0:0, 0:0:0);
(B2B1[0] => U[27]) = (0:0:0, 0:0:0);
(B2B1[0] => U[28]) = (0:0:0, 0:0:0);
(B2B1[0] => U[29]) = (0:0:0, 0:0:0);
(B2B1[0] => U[2]) = (0:0:0, 0:0:0);
(B2B1[0] => U[30]) = (0:0:0, 0:0:0);
(B2B1[0] => U[31]) = (0:0:0, 0:0:0);
(B2B1[0] => U[3]) = (0:0:0, 0:0:0);
(B2B1[0] => U[4]) = (0:0:0, 0:0:0);
(B2B1[0] => U[5]) = (0:0:0, 0:0:0);
(B2B1[0] => U[6]) = (0:0:0, 0:0:0);
(B2B1[0] => U[7]) = (0:0:0, 0:0:0);
(B2B1[0] => U[8]) = (0:0:0, 0:0:0);
(B2B1[0] => U[9]) = (0:0:0, 0:0:0);
(B2B1[0] => V[0]) = (0:0:0, 0:0:0);
(B2B1[0] => V[10]) = (0:0:0, 0:0:0);
(B2B1[0] => V[11]) = (0:0:0, 0:0:0);
(B2B1[0] => V[12]) = (0:0:0, 0:0:0);
(B2B1[0] => V[13]) = (0:0:0, 0:0:0);
(B2B1[0] => V[14]) = (0:0:0, 0:0:0);
(B2B1[0] => V[15]) = (0:0:0, 0:0:0);
(B2B1[0] => V[16]) = (0:0:0, 0:0:0);
(B2B1[0] => V[17]) = (0:0:0, 0:0:0);
(B2B1[0] => V[18]) = (0:0:0, 0:0:0);
(B2B1[0] => V[19]) = (0:0:0, 0:0:0);
(B2B1[0] => V[20]) = (0:0:0, 0:0:0);
(B2B1[0] => V[21]) = (0:0:0, 0:0:0);
(B2B1[0] => V[22]) = (0:0:0, 0:0:0);
(B2B1[0] => V[23]) = (0:0:0, 0:0:0);
(B2B1[0] => V[24]) = (0:0:0, 0:0:0);
(B2B1[0] => V[25]) = (0:0:0, 0:0:0);
(B2B1[0] => V[26]) = (0:0:0, 0:0:0);
(B2B1[0] => V[27]) = (0:0:0, 0:0:0);
(B2B1[0] => V[28]) = (0:0:0, 0:0:0);
(B2B1[0] => V[29]) = (0:0:0, 0:0:0);
(B2B1[0] => V[30]) = (0:0:0, 0:0:0);
(B2B1[0] => V[4]) = (0:0:0, 0:0:0);
(B2B1[0] => V[5]) = (0:0:0, 0:0:0);
(B2B1[0] => V[6]) = (0:0:0, 0:0:0);
(B2B1[0] => V[7]) = (0:0:0, 0:0:0);
(B2B1[0] => V[8]) = (0:0:0, 0:0:0);
(B2B1[0] => V[9]) = (0:0:0, 0:0:0);
(B2B1[10] => U[11]) = (0:0:0, 0:0:0);
(B2B1[10] => U[12]) = (0:0:0, 0:0:0);
(B2B1[10] => U[13]) = (0:0:0, 0:0:0);
(B2B1[10] => U[14]) = (0:0:0, 0:0:0);
(B2B1[10] => U[15]) = (0:0:0, 0:0:0);
(B2B1[10] => U[16]) = (0:0:0, 0:0:0);
(B2B1[10] => U[17]) = (0:0:0, 0:0:0);
(B2B1[10] => U[18]) = (0:0:0, 0:0:0);
(B2B1[10] => U[19]) = (0:0:0, 0:0:0);
(B2B1[10] => U[20]) = (0:0:0, 0:0:0);
(B2B1[10] => U[21]) = (0:0:0, 0:0:0);
(B2B1[10] => U[22]) = (0:0:0, 0:0:0);
(B2B1[10] => U[23]) = (0:0:0, 0:0:0);
(B2B1[10] => U[24]) = (0:0:0, 0:0:0);
(B2B1[10] => U[25]) = (0:0:0, 0:0:0);
(B2B1[10] => U[26]) = (0:0:0, 0:0:0);
(B2B1[10] => U[27]) = (0:0:0, 0:0:0);
(B2B1[10] => U[28]) = (0:0:0, 0:0:0);
(B2B1[10] => U[29]) = (0:0:0, 0:0:0);
(B2B1[10] => U[30]) = (0:0:0, 0:0:0);
(B2B1[10] => U[31]) = (0:0:0, 0:0:0);
(B2B1[10] => U[32]) = (0:0:0, 0:0:0);
(B2B1[10] => U[33]) = (0:0:0, 0:0:0);
(B2B1[10] => U[34]) = (0:0:0, 0:0:0);
(B2B1[10] => U[35]) = (0:0:0, 0:0:0);
(B2B1[10] => U[36]) = (0:0:0, 0:0:0);
(B2B1[10] => U[37]) = (0:0:0, 0:0:0);
(B2B1[10] => U[38]) = (0:0:0, 0:0:0);
(B2B1[10] => U[39]) = (0:0:0, 0:0:0);
(B2B1[10] => U[40]) = (0:0:0, 0:0:0);
(B2B1[10] => V[10]) = (0:0:0, 0:0:0);
(B2B1[10] => V[11]) = (0:0:0, 0:0:0);
(B2B1[10] => V[12]) = (0:0:0, 0:0:0);
(B2B1[10] => V[13]) = (0:0:0, 0:0:0);
(B2B1[10] => V[14]) = (0:0:0, 0:0:0);
(B2B1[10] => V[15]) = (0:0:0, 0:0:0);
(B2B1[10] => V[16]) = (0:0:0, 0:0:0);
(B2B1[10] => V[17]) = (0:0:0, 0:0:0);
(B2B1[10] => V[18]) = (0:0:0, 0:0:0);
(B2B1[10] => V[19]) = (0:0:0, 0:0:0);
(B2B1[10] => V[20]) = (0:0:0, 0:0:0);
(B2B1[10] => V[21]) = (0:0:0, 0:0:0);
(B2B1[10] => V[22]) = (0:0:0, 0:0:0);
(B2B1[10] => V[23]) = (0:0:0, 0:0:0);
(B2B1[10] => V[24]) = (0:0:0, 0:0:0);
(B2B1[10] => V[25]) = (0:0:0, 0:0:0);
(B2B1[10] => V[26]) = (0:0:0, 0:0:0);
(B2B1[10] => V[27]) = (0:0:0, 0:0:0);
(B2B1[10] => V[28]) = (0:0:0, 0:0:0);
(B2B1[10] => V[29]) = (0:0:0, 0:0:0);
(B2B1[10] => V[30]) = (0:0:0, 0:0:0);
(B2B1[10] => V[31]) = (0:0:0, 0:0:0);
(B2B1[10] => V[32]) = (0:0:0, 0:0:0);
(B2B1[10] => V[33]) = (0:0:0, 0:0:0);
(B2B1[10] => V[34]) = (0:0:0, 0:0:0);
(B2B1[10] => V[35]) = (0:0:0, 0:0:0);
(B2B1[10] => V[36]) = (0:0:0, 0:0:0);
(B2B1[10] => V[37]) = (0:0:0, 0:0:0);
(B2B1[10] => V[38]) = (0:0:0, 0:0:0);
(B2B1[10] => V[39]) = (0:0:0, 0:0:0);
(B2B1[11] => U[11]) = (0:0:0, 0:0:0);
(B2B1[11] => U[12]) = (0:0:0, 0:0:0);
(B2B1[11] => U[13]) = (0:0:0, 0:0:0);
(B2B1[11] => U[14]) = (0:0:0, 0:0:0);
(B2B1[11] => U[15]) = (0:0:0, 0:0:0);
(B2B1[11] => U[16]) = (0:0:0, 0:0:0);
(B2B1[11] => U[17]) = (0:0:0, 0:0:0);
(B2B1[11] => U[18]) = (0:0:0, 0:0:0);
(B2B1[11] => U[19]) = (0:0:0, 0:0:0);
(B2B1[11] => U[20]) = (0:0:0, 0:0:0);
(B2B1[11] => U[21]) = (0:0:0, 0:0:0);
(B2B1[11] => U[22]) = (0:0:0, 0:0:0);
(B2B1[11] => U[23]) = (0:0:0, 0:0:0);
(B2B1[11] => U[24]) = (0:0:0, 0:0:0);
(B2B1[11] => U[25]) = (0:0:0, 0:0:0);
(B2B1[11] => U[26]) = (0:0:0, 0:0:0);
(B2B1[11] => U[27]) = (0:0:0, 0:0:0);
(B2B1[11] => U[28]) = (0:0:0, 0:0:0);
(B2B1[11] => U[29]) = (0:0:0, 0:0:0);
(B2B1[11] => U[30]) = (0:0:0, 0:0:0);
(B2B1[11] => U[31]) = (0:0:0, 0:0:0);
(B2B1[11] => U[32]) = (0:0:0, 0:0:0);
(B2B1[11] => U[33]) = (0:0:0, 0:0:0);
(B2B1[11] => U[34]) = (0:0:0, 0:0:0);
(B2B1[11] => U[35]) = (0:0:0, 0:0:0);
(B2B1[11] => U[36]) = (0:0:0, 0:0:0);
(B2B1[11] => U[37]) = (0:0:0, 0:0:0);
(B2B1[11] => U[38]) = (0:0:0, 0:0:0);
(B2B1[11] => U[39]) = (0:0:0, 0:0:0);
(B2B1[11] => U[40]) = (0:0:0, 0:0:0);
(B2B1[11] => U[41]) = (0:0:0, 0:0:0);
(B2B1[11] => V[10]) = (0:0:0, 0:0:0);
(B2B1[11] => V[11]) = (0:0:0, 0:0:0);
(B2B1[11] => V[12]) = (0:0:0, 0:0:0);
(B2B1[11] => V[13]) = (0:0:0, 0:0:0);
(B2B1[11] => V[14]) = (0:0:0, 0:0:0);
(B2B1[11] => V[15]) = (0:0:0, 0:0:0);
(B2B1[11] => V[16]) = (0:0:0, 0:0:0);
(B2B1[11] => V[17]) = (0:0:0, 0:0:0);
(B2B1[11] => V[18]) = (0:0:0, 0:0:0);
(B2B1[11] => V[19]) = (0:0:0, 0:0:0);
(B2B1[11] => V[20]) = (0:0:0, 0:0:0);
(B2B1[11] => V[21]) = (0:0:0, 0:0:0);
(B2B1[11] => V[22]) = (0:0:0, 0:0:0);
(B2B1[11] => V[23]) = (0:0:0, 0:0:0);
(B2B1[11] => V[24]) = (0:0:0, 0:0:0);
(B2B1[11] => V[25]) = (0:0:0, 0:0:0);
(B2B1[11] => V[26]) = (0:0:0, 0:0:0);
(B2B1[11] => V[27]) = (0:0:0, 0:0:0);
(B2B1[11] => V[28]) = (0:0:0, 0:0:0);
(B2B1[11] => V[29]) = (0:0:0, 0:0:0);
(B2B1[11] => V[30]) = (0:0:0, 0:0:0);
(B2B1[11] => V[31]) = (0:0:0, 0:0:0);
(B2B1[11] => V[32]) = (0:0:0, 0:0:0);
(B2B1[11] => V[33]) = (0:0:0, 0:0:0);
(B2B1[11] => V[34]) = (0:0:0, 0:0:0);
(B2B1[11] => V[35]) = (0:0:0, 0:0:0);
(B2B1[11] => V[36]) = (0:0:0, 0:0:0);
(B2B1[11] => V[37]) = (0:0:0, 0:0:0);
(B2B1[11] => V[38]) = (0:0:0, 0:0:0);
(B2B1[11] => V[39]) = (0:0:0, 0:0:0);
(B2B1[11] => V[40]) = (0:0:0, 0:0:0);
(B2B1[12] => U[13]) = (0:0:0, 0:0:0);
(B2B1[12] => U[14]) = (0:0:0, 0:0:0);
(B2B1[12] => U[15]) = (0:0:0, 0:0:0);
(B2B1[12] => U[16]) = (0:0:0, 0:0:0);
(B2B1[12] => U[17]) = (0:0:0, 0:0:0);
(B2B1[12] => U[18]) = (0:0:0, 0:0:0);
(B2B1[12] => U[19]) = (0:0:0, 0:0:0);
(B2B1[12] => U[20]) = (0:0:0, 0:0:0);
(B2B1[12] => U[21]) = (0:0:0, 0:0:0);
(B2B1[12] => U[22]) = (0:0:0, 0:0:0);
(B2B1[12] => U[23]) = (0:0:0, 0:0:0);
(B2B1[12] => U[24]) = (0:0:0, 0:0:0);
(B2B1[12] => U[25]) = (0:0:0, 0:0:0);
(B2B1[12] => U[26]) = (0:0:0, 0:0:0);
(B2B1[12] => U[27]) = (0:0:0, 0:0:0);
(B2B1[12] => U[28]) = (0:0:0, 0:0:0);
(B2B1[12] => U[29]) = (0:0:0, 0:0:0);
(B2B1[12] => U[30]) = (0:0:0, 0:0:0);
(B2B1[12] => U[31]) = (0:0:0, 0:0:0);
(B2B1[12] => U[32]) = (0:0:0, 0:0:0);
(B2B1[12] => U[33]) = (0:0:0, 0:0:0);
(B2B1[12] => U[34]) = (0:0:0, 0:0:0);
(B2B1[12] => U[35]) = (0:0:0, 0:0:0);
(B2B1[12] => U[36]) = (0:0:0, 0:0:0);
(B2B1[12] => U[37]) = (0:0:0, 0:0:0);
(B2B1[12] => U[38]) = (0:0:0, 0:0:0);
(B2B1[12] => U[39]) = (0:0:0, 0:0:0);
(B2B1[12] => U[40]) = (0:0:0, 0:0:0);
(B2B1[12] => U[41]) = (0:0:0, 0:0:0);
(B2B1[12] => V[12]) = (0:0:0, 0:0:0);
(B2B1[12] => V[13]) = (0:0:0, 0:0:0);
(B2B1[12] => V[14]) = (0:0:0, 0:0:0);
(B2B1[12] => V[15]) = (0:0:0, 0:0:0);
(B2B1[12] => V[16]) = (0:0:0, 0:0:0);
(B2B1[12] => V[17]) = (0:0:0, 0:0:0);
(B2B1[12] => V[18]) = (0:0:0, 0:0:0);
(B2B1[12] => V[19]) = (0:0:0, 0:0:0);
(B2B1[12] => V[20]) = (0:0:0, 0:0:0);
(B2B1[12] => V[21]) = (0:0:0, 0:0:0);
(B2B1[12] => V[22]) = (0:0:0, 0:0:0);
(B2B1[12] => V[23]) = (0:0:0, 0:0:0);
(B2B1[12] => V[24]) = (0:0:0, 0:0:0);
(B2B1[12] => V[25]) = (0:0:0, 0:0:0);
(B2B1[12] => V[26]) = (0:0:0, 0:0:0);
(B2B1[12] => V[27]) = (0:0:0, 0:0:0);
(B2B1[12] => V[28]) = (0:0:0, 0:0:0);
(B2B1[12] => V[29]) = (0:0:0, 0:0:0);
(B2B1[12] => V[30]) = (0:0:0, 0:0:0);
(B2B1[12] => V[31]) = (0:0:0, 0:0:0);
(B2B1[12] => V[32]) = (0:0:0, 0:0:0);
(B2B1[12] => V[33]) = (0:0:0, 0:0:0);
(B2B1[12] => V[34]) = (0:0:0, 0:0:0);
(B2B1[12] => V[35]) = (0:0:0, 0:0:0);
(B2B1[12] => V[36]) = (0:0:0, 0:0:0);
(B2B1[12] => V[37]) = (0:0:0, 0:0:0);
(B2B1[12] => V[38]) = (0:0:0, 0:0:0);
(B2B1[12] => V[39]) = (0:0:0, 0:0:0);
(B2B1[12] => V[40]) = (0:0:0, 0:0:0);
(B2B1[13] => U[13]) = (0:0:0, 0:0:0);
(B2B1[13] => U[14]) = (0:0:0, 0:0:0);
(B2B1[13] => U[15]) = (0:0:0, 0:0:0);
(B2B1[13] => U[16]) = (0:0:0, 0:0:0);
(B2B1[13] => U[17]) = (0:0:0, 0:0:0);
(B2B1[13] => U[18]) = (0:0:0, 0:0:0);
(B2B1[13] => U[19]) = (0:0:0, 0:0:0);
(B2B1[13] => U[20]) = (0:0:0, 0:0:0);
(B2B1[13] => U[21]) = (0:0:0, 0:0:0);
(B2B1[13] => U[22]) = (0:0:0, 0:0:0);
(B2B1[13] => U[23]) = (0:0:0, 0:0:0);
(B2B1[13] => U[24]) = (0:0:0, 0:0:0);
(B2B1[13] => U[25]) = (0:0:0, 0:0:0);
(B2B1[13] => U[26]) = (0:0:0, 0:0:0);
(B2B1[13] => U[27]) = (0:0:0, 0:0:0);
(B2B1[13] => U[28]) = (0:0:0, 0:0:0);
(B2B1[13] => U[29]) = (0:0:0, 0:0:0);
(B2B1[13] => U[30]) = (0:0:0, 0:0:0);
(B2B1[13] => U[31]) = (0:0:0, 0:0:0);
(B2B1[13] => U[32]) = (0:0:0, 0:0:0);
(B2B1[13] => U[33]) = (0:0:0, 0:0:0);
(B2B1[13] => U[34]) = (0:0:0, 0:0:0);
(B2B1[13] => U[35]) = (0:0:0, 0:0:0);
(B2B1[13] => U[36]) = (0:0:0, 0:0:0);
(B2B1[13] => U[37]) = (0:0:0, 0:0:0);
(B2B1[13] => U[38]) = (0:0:0, 0:0:0);
(B2B1[13] => U[39]) = (0:0:0, 0:0:0);
(B2B1[13] => U[40]) = (0:0:0, 0:0:0);
(B2B1[13] => U[41]) = (0:0:0, 0:0:0);
(B2B1[13] => U[42]) = (0:0:0, 0:0:0);
(B2B1[13] => V[12]) = (0:0:0, 0:0:0);
(B2B1[13] => V[13]) = (0:0:0, 0:0:0);
(B2B1[13] => V[14]) = (0:0:0, 0:0:0);
(B2B1[13] => V[15]) = (0:0:0, 0:0:0);
(B2B1[13] => V[16]) = (0:0:0, 0:0:0);
(B2B1[13] => V[17]) = (0:0:0, 0:0:0);
(B2B1[13] => V[18]) = (0:0:0, 0:0:0);
(B2B1[13] => V[19]) = (0:0:0, 0:0:0);
(B2B1[13] => V[20]) = (0:0:0, 0:0:0);
(B2B1[13] => V[21]) = (0:0:0, 0:0:0);
(B2B1[13] => V[22]) = (0:0:0, 0:0:0);
(B2B1[13] => V[23]) = (0:0:0, 0:0:0);
(B2B1[13] => V[24]) = (0:0:0, 0:0:0);
(B2B1[13] => V[25]) = (0:0:0, 0:0:0);
(B2B1[13] => V[26]) = (0:0:0, 0:0:0);
(B2B1[13] => V[27]) = (0:0:0, 0:0:0);
(B2B1[13] => V[28]) = (0:0:0, 0:0:0);
(B2B1[13] => V[29]) = (0:0:0, 0:0:0);
(B2B1[13] => V[30]) = (0:0:0, 0:0:0);
(B2B1[13] => V[31]) = (0:0:0, 0:0:0);
(B2B1[13] => V[32]) = (0:0:0, 0:0:0);
(B2B1[13] => V[33]) = (0:0:0, 0:0:0);
(B2B1[13] => V[34]) = (0:0:0, 0:0:0);
(B2B1[13] => V[35]) = (0:0:0, 0:0:0);
(B2B1[13] => V[36]) = (0:0:0, 0:0:0);
(B2B1[13] => V[37]) = (0:0:0, 0:0:0);
(B2B1[13] => V[38]) = (0:0:0, 0:0:0);
(B2B1[13] => V[39]) = (0:0:0, 0:0:0);
(B2B1[13] => V[40]) = (0:0:0, 0:0:0);
(B2B1[13] => V[41]) = (0:0:0, 0:0:0);
(B2B1[14] => U[15]) = (0:0:0, 0:0:0);
(B2B1[14] => U[16]) = (0:0:0, 0:0:0);
(B2B1[14] => U[17]) = (0:0:0, 0:0:0);
(B2B1[14] => U[18]) = (0:0:0, 0:0:0);
(B2B1[14] => U[19]) = (0:0:0, 0:0:0);
(B2B1[14] => U[20]) = (0:0:0, 0:0:0);
(B2B1[14] => U[21]) = (0:0:0, 0:0:0);
(B2B1[14] => U[22]) = (0:0:0, 0:0:0);
(B2B1[14] => U[23]) = (0:0:0, 0:0:0);
(B2B1[14] => U[24]) = (0:0:0, 0:0:0);
(B2B1[14] => U[25]) = (0:0:0, 0:0:0);
(B2B1[14] => U[26]) = (0:0:0, 0:0:0);
(B2B1[14] => U[27]) = (0:0:0, 0:0:0);
(B2B1[14] => U[28]) = (0:0:0, 0:0:0);
(B2B1[14] => U[29]) = (0:0:0, 0:0:0);
(B2B1[14] => U[30]) = (0:0:0, 0:0:0);
(B2B1[14] => U[31]) = (0:0:0, 0:0:0);
(B2B1[14] => U[32]) = (0:0:0, 0:0:0);
(B2B1[14] => U[33]) = (0:0:0, 0:0:0);
(B2B1[14] => U[34]) = (0:0:0, 0:0:0);
(B2B1[14] => U[35]) = (0:0:0, 0:0:0);
(B2B1[14] => U[36]) = (0:0:0, 0:0:0);
(B2B1[14] => U[37]) = (0:0:0, 0:0:0);
(B2B1[14] => U[38]) = (0:0:0, 0:0:0);
(B2B1[14] => U[39]) = (0:0:0, 0:0:0);
(B2B1[14] => U[40]) = (0:0:0, 0:0:0);
(B2B1[14] => U[41]) = (0:0:0, 0:0:0);
(B2B1[14] => U[42]) = (0:0:0, 0:0:0);
(B2B1[14] => V[14]) = (0:0:0, 0:0:0);
(B2B1[14] => V[15]) = (0:0:0, 0:0:0);
(B2B1[14] => V[16]) = (0:0:0, 0:0:0);
(B2B1[14] => V[17]) = (0:0:0, 0:0:0);
(B2B1[14] => V[18]) = (0:0:0, 0:0:0);
(B2B1[14] => V[19]) = (0:0:0, 0:0:0);
(B2B1[14] => V[20]) = (0:0:0, 0:0:0);
(B2B1[14] => V[21]) = (0:0:0, 0:0:0);
(B2B1[14] => V[22]) = (0:0:0, 0:0:0);
(B2B1[14] => V[23]) = (0:0:0, 0:0:0);
(B2B1[14] => V[24]) = (0:0:0, 0:0:0);
(B2B1[14] => V[25]) = (0:0:0, 0:0:0);
(B2B1[14] => V[26]) = (0:0:0, 0:0:0);
(B2B1[14] => V[27]) = (0:0:0, 0:0:0);
(B2B1[14] => V[28]) = (0:0:0, 0:0:0);
(B2B1[14] => V[29]) = (0:0:0, 0:0:0);
(B2B1[14] => V[30]) = (0:0:0, 0:0:0);
(B2B1[14] => V[31]) = (0:0:0, 0:0:0);
(B2B1[14] => V[32]) = (0:0:0, 0:0:0);
(B2B1[14] => V[33]) = (0:0:0, 0:0:0);
(B2B1[14] => V[34]) = (0:0:0, 0:0:0);
(B2B1[14] => V[35]) = (0:0:0, 0:0:0);
(B2B1[14] => V[36]) = (0:0:0, 0:0:0);
(B2B1[14] => V[37]) = (0:0:0, 0:0:0);
(B2B1[14] => V[38]) = (0:0:0, 0:0:0);
(B2B1[14] => V[39]) = (0:0:0, 0:0:0);
(B2B1[14] => V[40]) = (0:0:0, 0:0:0);
(B2B1[14] => V[41]) = (0:0:0, 0:0:0);
(B2B1[15] => U[15]) = (0:0:0, 0:0:0);
(B2B1[15] => U[16]) = (0:0:0, 0:0:0);
(B2B1[15] => U[17]) = (0:0:0, 0:0:0);
(B2B1[15] => U[18]) = (0:0:0, 0:0:0);
(B2B1[15] => U[19]) = (0:0:0, 0:0:0);
(B2B1[15] => U[20]) = (0:0:0, 0:0:0);
(B2B1[15] => U[21]) = (0:0:0, 0:0:0);
(B2B1[15] => U[22]) = (0:0:0, 0:0:0);
(B2B1[15] => U[23]) = (0:0:0, 0:0:0);
(B2B1[15] => U[24]) = (0:0:0, 0:0:0);
(B2B1[15] => U[25]) = (0:0:0, 0:0:0);
(B2B1[15] => U[26]) = (0:0:0, 0:0:0);
(B2B1[15] => U[27]) = (0:0:0, 0:0:0);
(B2B1[15] => U[28]) = (0:0:0, 0:0:0);
(B2B1[15] => U[29]) = (0:0:0, 0:0:0);
(B2B1[15] => U[30]) = (0:0:0, 0:0:0);
(B2B1[15] => U[31]) = (0:0:0, 0:0:0);
(B2B1[15] => U[32]) = (0:0:0, 0:0:0);
(B2B1[15] => U[33]) = (0:0:0, 0:0:0);
(B2B1[15] => U[34]) = (0:0:0, 0:0:0);
(B2B1[15] => U[35]) = (0:0:0, 0:0:0);
(B2B1[15] => U[36]) = (0:0:0, 0:0:0);
(B2B1[15] => U[37]) = (0:0:0, 0:0:0);
(B2B1[15] => U[38]) = (0:0:0, 0:0:0);
(B2B1[15] => U[39]) = (0:0:0, 0:0:0);
(B2B1[15] => U[40]) = (0:0:0, 0:0:0);
(B2B1[15] => U[41]) = (0:0:0, 0:0:0);
(B2B1[15] => U[42]) = (0:0:0, 0:0:0);
(B2B1[15] => U[43]) = (0:0:0, 0:0:0);
(B2B1[15] => V[14]) = (0:0:0, 0:0:0);
(B2B1[15] => V[15]) = (0:0:0, 0:0:0);
(B2B1[15] => V[16]) = (0:0:0, 0:0:0);
(B2B1[15] => V[17]) = (0:0:0, 0:0:0);
(B2B1[15] => V[18]) = (0:0:0, 0:0:0);
(B2B1[15] => V[19]) = (0:0:0, 0:0:0);
(B2B1[15] => V[20]) = (0:0:0, 0:0:0);
(B2B1[15] => V[21]) = (0:0:0, 0:0:0);
(B2B1[15] => V[22]) = (0:0:0, 0:0:0);
(B2B1[15] => V[23]) = (0:0:0, 0:0:0);
(B2B1[15] => V[24]) = (0:0:0, 0:0:0);
(B2B1[15] => V[25]) = (0:0:0, 0:0:0);
(B2B1[15] => V[26]) = (0:0:0, 0:0:0);
(B2B1[15] => V[27]) = (0:0:0, 0:0:0);
(B2B1[15] => V[28]) = (0:0:0, 0:0:0);
(B2B1[15] => V[29]) = (0:0:0, 0:0:0);
(B2B1[15] => V[30]) = (0:0:0, 0:0:0);
(B2B1[15] => V[31]) = (0:0:0, 0:0:0);
(B2B1[15] => V[32]) = (0:0:0, 0:0:0);
(B2B1[15] => V[33]) = (0:0:0, 0:0:0);
(B2B1[15] => V[34]) = (0:0:0, 0:0:0);
(B2B1[15] => V[35]) = (0:0:0, 0:0:0);
(B2B1[15] => V[36]) = (0:0:0, 0:0:0);
(B2B1[15] => V[37]) = (0:0:0, 0:0:0);
(B2B1[15] => V[38]) = (0:0:0, 0:0:0);
(B2B1[15] => V[39]) = (0:0:0, 0:0:0);
(B2B1[15] => V[40]) = (0:0:0, 0:0:0);
(B2B1[15] => V[41]) = (0:0:0, 0:0:0);
(B2B1[15] => V[42]) = (0:0:0, 0:0:0);
(B2B1[15] => V[43]) = (0:0:0, 0:0:0);
(B2B1[16] => U[17]) = (0:0:0, 0:0:0);
(B2B1[16] => U[18]) = (0:0:0, 0:0:0);
(B2B1[16] => U[19]) = (0:0:0, 0:0:0);
(B2B1[16] => U[20]) = (0:0:0, 0:0:0);
(B2B1[16] => U[21]) = (0:0:0, 0:0:0);
(B2B1[16] => U[22]) = (0:0:0, 0:0:0);
(B2B1[16] => U[23]) = (0:0:0, 0:0:0);
(B2B1[16] => U[24]) = (0:0:0, 0:0:0);
(B2B1[16] => U[25]) = (0:0:0, 0:0:0);
(B2B1[16] => U[26]) = (0:0:0, 0:0:0);
(B2B1[16] => U[27]) = (0:0:0, 0:0:0);
(B2B1[16] => U[28]) = (0:0:0, 0:0:0);
(B2B1[16] => U[29]) = (0:0:0, 0:0:0);
(B2B1[16] => U[30]) = (0:0:0, 0:0:0);
(B2B1[16] => U[31]) = (0:0:0, 0:0:0);
(B2B1[16] => U[32]) = (0:0:0, 0:0:0);
(B2B1[16] => U[33]) = (0:0:0, 0:0:0);
(B2B1[16] => U[34]) = (0:0:0, 0:0:0);
(B2B1[16] => U[35]) = (0:0:0, 0:0:0);
(B2B1[16] => U[36]) = (0:0:0, 0:0:0);
(B2B1[16] => U[37]) = (0:0:0, 0:0:0);
(B2B1[16] => U[38]) = (0:0:0, 0:0:0);
(B2B1[16] => U[39]) = (0:0:0, 0:0:0);
(B2B1[16] => U[40]) = (0:0:0, 0:0:0);
(B2B1[16] => U[41]) = (0:0:0, 0:0:0);
(B2B1[16] => U[42]) = (0:0:0, 0:0:0);
(B2B1[16] => U[43]) = (0:0:0, 0:0:0);
(B2B1[16] => V[16]) = (0:0:0, 0:0:0);
(B2B1[16] => V[17]) = (0:0:0, 0:0:0);
(B2B1[16] => V[18]) = (0:0:0, 0:0:0);
(B2B1[16] => V[19]) = (0:0:0, 0:0:0);
(B2B1[16] => V[20]) = (0:0:0, 0:0:0);
(B2B1[16] => V[21]) = (0:0:0, 0:0:0);
(B2B1[16] => V[22]) = (0:0:0, 0:0:0);
(B2B1[16] => V[23]) = (0:0:0, 0:0:0);
(B2B1[16] => V[24]) = (0:0:0, 0:0:0);
(B2B1[16] => V[25]) = (0:0:0, 0:0:0);
(B2B1[16] => V[26]) = (0:0:0, 0:0:0);
(B2B1[16] => V[27]) = (0:0:0, 0:0:0);
(B2B1[16] => V[28]) = (0:0:0, 0:0:0);
(B2B1[16] => V[29]) = (0:0:0, 0:0:0);
(B2B1[16] => V[30]) = (0:0:0, 0:0:0);
(B2B1[16] => V[31]) = (0:0:0, 0:0:0);
(B2B1[16] => V[32]) = (0:0:0, 0:0:0);
(B2B1[16] => V[33]) = (0:0:0, 0:0:0);
(B2B1[16] => V[34]) = (0:0:0, 0:0:0);
(B2B1[16] => V[35]) = (0:0:0, 0:0:0);
(B2B1[16] => V[36]) = (0:0:0, 0:0:0);
(B2B1[16] => V[37]) = (0:0:0, 0:0:0);
(B2B1[16] => V[38]) = (0:0:0, 0:0:0);
(B2B1[16] => V[39]) = (0:0:0, 0:0:0);
(B2B1[16] => V[40]) = (0:0:0, 0:0:0);
(B2B1[16] => V[41]) = (0:0:0, 0:0:0);
(B2B1[16] => V[42]) = (0:0:0, 0:0:0);
(B2B1[16] => V[43]) = (0:0:0, 0:0:0);
(B2B1[17] => BMULT17) = (0:0:0, 0:0:0);
(B2B1[17] => U[17]) = (0:0:0, 0:0:0);
(B2B1[17] => U[18]) = (0:0:0, 0:0:0);
(B2B1[17] => U[19]) = (0:0:0, 0:0:0);
(B2B1[17] => U[20]) = (0:0:0, 0:0:0);
(B2B1[17] => U[21]) = (0:0:0, 0:0:0);
(B2B1[17] => U[22]) = (0:0:0, 0:0:0);
(B2B1[17] => U[23]) = (0:0:0, 0:0:0);
(B2B1[17] => U[24]) = (0:0:0, 0:0:0);
(B2B1[17] => U[25]) = (0:0:0, 0:0:0);
(B2B1[17] => U[26]) = (0:0:0, 0:0:0);
(B2B1[17] => U[27]) = (0:0:0, 0:0:0);
(B2B1[17] => U[28]) = (0:0:0, 0:0:0);
(B2B1[17] => U[29]) = (0:0:0, 0:0:0);
(B2B1[17] => U[30]) = (0:0:0, 0:0:0);
(B2B1[17] => U[31]) = (0:0:0, 0:0:0);
(B2B1[17] => U[32]) = (0:0:0, 0:0:0);
(B2B1[17] => U[33]) = (0:0:0, 0:0:0);
(B2B1[17] => U[34]) = (0:0:0, 0:0:0);
(B2B1[17] => U[35]) = (0:0:0, 0:0:0);
(B2B1[17] => U[36]) = (0:0:0, 0:0:0);
(B2B1[17] => U[37]) = (0:0:0, 0:0:0);
(B2B1[17] => U[38]) = (0:0:0, 0:0:0);
(B2B1[17] => U[39]) = (0:0:0, 0:0:0);
(B2B1[17] => U[40]) = (0:0:0, 0:0:0);
(B2B1[17] => U[41]) = (0:0:0, 0:0:0);
(B2B1[17] => U[42]) = (0:0:0, 0:0:0);
(B2B1[17] => U[43]) = (0:0:0, 0:0:0);
(B2B1[17] => V[16]) = (0:0:0, 0:0:0);
(B2B1[17] => V[17]) = (0:0:0, 0:0:0);
(B2B1[17] => V[18]) = (0:0:0, 0:0:0);
(B2B1[17] => V[19]) = (0:0:0, 0:0:0);
(B2B1[17] => V[20]) = (0:0:0, 0:0:0);
(B2B1[17] => V[21]) = (0:0:0, 0:0:0);
(B2B1[17] => V[22]) = (0:0:0, 0:0:0);
(B2B1[17] => V[23]) = (0:0:0, 0:0:0);
(B2B1[17] => V[24]) = (0:0:0, 0:0:0);
(B2B1[17] => V[25]) = (0:0:0, 0:0:0);
(B2B1[17] => V[26]) = (0:0:0, 0:0:0);
(B2B1[17] => V[27]) = (0:0:0, 0:0:0);
(B2B1[17] => V[28]) = (0:0:0, 0:0:0);
(B2B1[17] => V[29]) = (0:0:0, 0:0:0);
(B2B1[17] => V[30]) = (0:0:0, 0:0:0);
(B2B1[17] => V[31]) = (0:0:0, 0:0:0);
(B2B1[17] => V[32]) = (0:0:0, 0:0:0);
(B2B1[17] => V[33]) = (0:0:0, 0:0:0);
(B2B1[17] => V[34]) = (0:0:0, 0:0:0);
(B2B1[17] => V[35]) = (0:0:0, 0:0:0);
(B2B1[17] => V[36]) = (0:0:0, 0:0:0);
(B2B1[17] => V[37]) = (0:0:0, 0:0:0);
(B2B1[17] => V[38]) = (0:0:0, 0:0:0);
(B2B1[17] => V[39]) = (0:0:0, 0:0:0);
(B2B1[17] => V[40]) = (0:0:0, 0:0:0);
(B2B1[17] => V[41]) = (0:0:0, 0:0:0);
(B2B1[17] => V[42]) = (0:0:0, 0:0:0);
(B2B1[17] => V[43]) = (0:0:0, 0:0:0);
(B2B1[1] => U[0]) = (0:0:0, 0:0:0);
(B2B1[1] => U[10]) = (0:0:0, 0:0:0);
(B2B1[1] => U[11]) = (0:0:0, 0:0:0);
(B2B1[1] => U[12]) = (0:0:0, 0:0:0);
(B2B1[1] => U[13]) = (0:0:0, 0:0:0);
(B2B1[1] => U[14]) = (0:0:0, 0:0:0);
(B2B1[1] => U[15]) = (0:0:0, 0:0:0);
(B2B1[1] => U[16]) = (0:0:0, 0:0:0);
(B2B1[1] => U[17]) = (0:0:0, 0:0:0);
(B2B1[1] => U[18]) = (0:0:0, 0:0:0);
(B2B1[1] => U[19]) = (0:0:0, 0:0:0);
(B2B1[1] => U[1]) = (0:0:0, 0:0:0);
(B2B1[1] => U[20]) = (0:0:0, 0:0:0);
(B2B1[1] => U[21]) = (0:0:0, 0:0:0);
(B2B1[1] => U[22]) = (0:0:0, 0:0:0);
(B2B1[1] => U[23]) = (0:0:0, 0:0:0);
(B2B1[1] => U[24]) = (0:0:0, 0:0:0);
(B2B1[1] => U[25]) = (0:0:0, 0:0:0);
(B2B1[1] => U[26]) = (0:0:0, 0:0:0);
(B2B1[1] => U[27]) = (0:0:0, 0:0:0);
(B2B1[1] => U[28]) = (0:0:0, 0:0:0);
(B2B1[1] => U[29]) = (0:0:0, 0:0:0);
(B2B1[1] => U[2]) = (0:0:0, 0:0:0);
(B2B1[1] => U[30]) = (0:0:0, 0:0:0);
(B2B1[1] => U[31]) = (0:0:0, 0:0:0);
(B2B1[1] => U[32]) = (0:0:0, 0:0:0);
(B2B1[1] => U[33]) = (0:0:0, 0:0:0);
(B2B1[1] => U[3]) = (0:0:0, 0:0:0);
(B2B1[1] => U[4]) = (0:0:0, 0:0:0);
(B2B1[1] => U[5]) = (0:0:0, 0:0:0);
(B2B1[1] => U[6]) = (0:0:0, 0:0:0);
(B2B1[1] => U[7]) = (0:0:0, 0:0:0);
(B2B1[1] => U[8]) = (0:0:0, 0:0:0);
(B2B1[1] => U[9]) = (0:0:0, 0:0:0);
(B2B1[1] => V[0]) = (0:0:0, 0:0:0);
(B2B1[1] => V[10]) = (0:0:0, 0:0:0);
(B2B1[1] => V[11]) = (0:0:0, 0:0:0);
(B2B1[1] => V[12]) = (0:0:0, 0:0:0);
(B2B1[1] => V[13]) = (0:0:0, 0:0:0);
(B2B1[1] => V[14]) = (0:0:0, 0:0:0);
(B2B1[1] => V[15]) = (0:0:0, 0:0:0);
(B2B1[1] => V[16]) = (0:0:0, 0:0:0);
(B2B1[1] => V[17]) = (0:0:0, 0:0:0);
(B2B1[1] => V[18]) = (0:0:0, 0:0:0);
(B2B1[1] => V[19]) = (0:0:0, 0:0:0);
(B2B1[1] => V[20]) = (0:0:0, 0:0:0);
(B2B1[1] => V[21]) = (0:0:0, 0:0:0);
(B2B1[1] => V[22]) = (0:0:0, 0:0:0);
(B2B1[1] => V[23]) = (0:0:0, 0:0:0);
(B2B1[1] => V[24]) = (0:0:0, 0:0:0);
(B2B1[1] => V[25]) = (0:0:0, 0:0:0);
(B2B1[1] => V[26]) = (0:0:0, 0:0:0);
(B2B1[1] => V[27]) = (0:0:0, 0:0:0);
(B2B1[1] => V[28]) = (0:0:0, 0:0:0);
(B2B1[1] => V[29]) = (0:0:0, 0:0:0);
(B2B1[1] => V[30]) = (0:0:0, 0:0:0);
(B2B1[1] => V[31]) = (0:0:0, 0:0:0);
(B2B1[1] => V[32]) = (0:0:0, 0:0:0);
(B2B1[1] => V[4]) = (0:0:0, 0:0:0);
(B2B1[1] => V[5]) = (0:0:0, 0:0:0);
(B2B1[1] => V[6]) = (0:0:0, 0:0:0);
(B2B1[1] => V[7]) = (0:0:0, 0:0:0);
(B2B1[1] => V[8]) = (0:0:0, 0:0:0);
(B2B1[1] => V[9]) = (0:0:0, 0:0:0);
(B2B1[2] => U[10]) = (0:0:0, 0:0:0);
(B2B1[2] => U[11]) = (0:0:0, 0:0:0);
(B2B1[2] => U[12]) = (0:0:0, 0:0:0);
(B2B1[2] => U[13]) = (0:0:0, 0:0:0);
(B2B1[2] => U[14]) = (0:0:0, 0:0:0);
(B2B1[2] => U[15]) = (0:0:0, 0:0:0);
(B2B1[2] => U[16]) = (0:0:0, 0:0:0);
(B2B1[2] => U[17]) = (0:0:0, 0:0:0);
(B2B1[2] => U[18]) = (0:0:0, 0:0:0);
(B2B1[2] => U[19]) = (0:0:0, 0:0:0);
(B2B1[2] => U[20]) = (0:0:0, 0:0:0);
(B2B1[2] => U[21]) = (0:0:0, 0:0:0);
(B2B1[2] => U[22]) = (0:0:0, 0:0:0);
(B2B1[2] => U[23]) = (0:0:0, 0:0:0);
(B2B1[2] => U[24]) = (0:0:0, 0:0:0);
(B2B1[2] => U[25]) = (0:0:0, 0:0:0);
(B2B1[2] => U[26]) = (0:0:0, 0:0:0);
(B2B1[2] => U[27]) = (0:0:0, 0:0:0);
(B2B1[2] => U[28]) = (0:0:0, 0:0:0);
(B2B1[2] => U[29]) = (0:0:0, 0:0:0);
(B2B1[2] => U[2]) = (0:0:0, 0:0:0);
(B2B1[2] => U[30]) = (0:0:0, 0:0:0);
(B2B1[2] => U[31]) = (0:0:0, 0:0:0);
(B2B1[2] => U[32]) = (0:0:0, 0:0:0);
(B2B1[2] => U[33]) = (0:0:0, 0:0:0);
(B2B1[2] => U[3]) = (0:0:0, 0:0:0);
(B2B1[2] => U[4]) = (0:0:0, 0:0:0);
(B2B1[2] => U[5]) = (0:0:0, 0:0:0);
(B2B1[2] => U[6]) = (0:0:0, 0:0:0);
(B2B1[2] => U[7]) = (0:0:0, 0:0:0);
(B2B1[2] => U[8]) = (0:0:0, 0:0:0);
(B2B1[2] => U[9]) = (0:0:0, 0:0:0);
(B2B1[2] => V[10]) = (0:0:0, 0:0:0);
(B2B1[2] => V[11]) = (0:0:0, 0:0:0);
(B2B1[2] => V[12]) = (0:0:0, 0:0:0);
(B2B1[2] => V[13]) = (0:0:0, 0:0:0);
(B2B1[2] => V[14]) = (0:0:0, 0:0:0);
(B2B1[2] => V[15]) = (0:0:0, 0:0:0);
(B2B1[2] => V[16]) = (0:0:0, 0:0:0);
(B2B1[2] => V[17]) = (0:0:0, 0:0:0);
(B2B1[2] => V[18]) = (0:0:0, 0:0:0);
(B2B1[2] => V[19]) = (0:0:0, 0:0:0);
(B2B1[2] => V[20]) = (0:0:0, 0:0:0);
(B2B1[2] => V[21]) = (0:0:0, 0:0:0);
(B2B1[2] => V[22]) = (0:0:0, 0:0:0);
(B2B1[2] => V[23]) = (0:0:0, 0:0:0);
(B2B1[2] => V[24]) = (0:0:0, 0:0:0);
(B2B1[2] => V[25]) = (0:0:0, 0:0:0);
(B2B1[2] => V[26]) = (0:0:0, 0:0:0);
(B2B1[2] => V[27]) = (0:0:0, 0:0:0);
(B2B1[2] => V[28]) = (0:0:0, 0:0:0);
(B2B1[2] => V[29]) = (0:0:0, 0:0:0);
(B2B1[2] => V[30]) = (0:0:0, 0:0:0);
(B2B1[2] => V[31]) = (0:0:0, 0:0:0);
(B2B1[2] => V[32]) = (0:0:0, 0:0:0);
(B2B1[2] => V[4]) = (0:0:0, 0:0:0);
(B2B1[2] => V[5]) = (0:0:0, 0:0:0);
(B2B1[2] => V[6]) = (0:0:0, 0:0:0);
(B2B1[2] => V[7]) = (0:0:0, 0:0:0);
(B2B1[2] => V[8]) = (0:0:0, 0:0:0);
(B2B1[2] => V[9]) = (0:0:0, 0:0:0);
(B2B1[3] => U[10]) = (0:0:0, 0:0:0);
(B2B1[3] => U[11]) = (0:0:0, 0:0:0);
(B2B1[3] => U[12]) = (0:0:0, 0:0:0);
(B2B1[3] => U[13]) = (0:0:0, 0:0:0);
(B2B1[3] => U[14]) = (0:0:0, 0:0:0);
(B2B1[3] => U[15]) = (0:0:0, 0:0:0);
(B2B1[3] => U[16]) = (0:0:0, 0:0:0);
(B2B1[3] => U[17]) = (0:0:0, 0:0:0);
(B2B1[3] => U[18]) = (0:0:0, 0:0:0);
(B2B1[3] => U[19]) = (0:0:0, 0:0:0);
(B2B1[3] => U[20]) = (0:0:0, 0:0:0);
(B2B1[3] => U[21]) = (0:0:0, 0:0:0);
(B2B1[3] => U[22]) = (0:0:0, 0:0:0);
(B2B1[3] => U[23]) = (0:0:0, 0:0:0);
(B2B1[3] => U[24]) = (0:0:0, 0:0:0);
(B2B1[3] => U[25]) = (0:0:0, 0:0:0);
(B2B1[3] => U[26]) = (0:0:0, 0:0:0);
(B2B1[3] => U[27]) = (0:0:0, 0:0:0);
(B2B1[3] => U[28]) = (0:0:0, 0:0:0);
(B2B1[3] => U[29]) = (0:0:0, 0:0:0);
(B2B1[3] => U[2]) = (0:0:0, 0:0:0);
(B2B1[3] => U[30]) = (0:0:0, 0:0:0);
(B2B1[3] => U[31]) = (0:0:0, 0:0:0);
(B2B1[3] => U[32]) = (0:0:0, 0:0:0);
(B2B1[3] => U[33]) = (0:0:0, 0:0:0);
(B2B1[3] => U[34]) = (0:0:0, 0:0:0);
(B2B1[3] => U[35]) = (0:0:0, 0:0:0);
(B2B1[3] => U[3]) = (0:0:0, 0:0:0);
(B2B1[3] => U[4]) = (0:0:0, 0:0:0);
(B2B1[3] => U[5]) = (0:0:0, 0:0:0);
(B2B1[3] => U[6]) = (0:0:0, 0:0:0);
(B2B1[3] => U[7]) = (0:0:0, 0:0:0);
(B2B1[3] => U[8]) = (0:0:0, 0:0:0);
(B2B1[3] => U[9]) = (0:0:0, 0:0:0);
(B2B1[3] => V[10]) = (0:0:0, 0:0:0);
(B2B1[3] => V[11]) = (0:0:0, 0:0:0);
(B2B1[3] => V[12]) = (0:0:0, 0:0:0);
(B2B1[3] => V[13]) = (0:0:0, 0:0:0);
(B2B1[3] => V[14]) = (0:0:0, 0:0:0);
(B2B1[3] => V[15]) = (0:0:0, 0:0:0);
(B2B1[3] => V[16]) = (0:0:0, 0:0:0);
(B2B1[3] => V[17]) = (0:0:0, 0:0:0);
(B2B1[3] => V[18]) = (0:0:0, 0:0:0);
(B2B1[3] => V[19]) = (0:0:0, 0:0:0);
(B2B1[3] => V[20]) = (0:0:0, 0:0:0);
(B2B1[3] => V[21]) = (0:0:0, 0:0:0);
(B2B1[3] => V[22]) = (0:0:0, 0:0:0);
(B2B1[3] => V[23]) = (0:0:0, 0:0:0);
(B2B1[3] => V[24]) = (0:0:0, 0:0:0);
(B2B1[3] => V[25]) = (0:0:0, 0:0:0);
(B2B1[3] => V[26]) = (0:0:0, 0:0:0);
(B2B1[3] => V[27]) = (0:0:0, 0:0:0);
(B2B1[3] => V[28]) = (0:0:0, 0:0:0);
(B2B1[3] => V[29]) = (0:0:0, 0:0:0);
(B2B1[3] => V[30]) = (0:0:0, 0:0:0);
(B2B1[3] => V[31]) = (0:0:0, 0:0:0);
(B2B1[3] => V[32]) = (0:0:0, 0:0:0);
(B2B1[3] => V[33]) = (0:0:0, 0:0:0);
(B2B1[3] => V[34]) = (0:0:0, 0:0:0);
(B2B1[3] => V[4]) = (0:0:0, 0:0:0);
(B2B1[3] => V[5]) = (0:0:0, 0:0:0);
(B2B1[3] => V[6]) = (0:0:0, 0:0:0);
(B2B1[3] => V[7]) = (0:0:0, 0:0:0);
(B2B1[3] => V[8]) = (0:0:0, 0:0:0);
(B2B1[3] => V[9]) = (0:0:0, 0:0:0);
(B2B1[4] => U[10]) = (0:0:0, 0:0:0);
(B2B1[4] => U[11]) = (0:0:0, 0:0:0);
(B2B1[4] => U[12]) = (0:0:0, 0:0:0);
(B2B1[4] => U[13]) = (0:0:0, 0:0:0);
(B2B1[4] => U[14]) = (0:0:0, 0:0:0);
(B2B1[4] => U[15]) = (0:0:0, 0:0:0);
(B2B1[4] => U[16]) = (0:0:0, 0:0:0);
(B2B1[4] => U[17]) = (0:0:0, 0:0:0);
(B2B1[4] => U[18]) = (0:0:0, 0:0:0);
(B2B1[4] => U[19]) = (0:0:0, 0:0:0);
(B2B1[4] => U[20]) = (0:0:0, 0:0:0);
(B2B1[4] => U[21]) = (0:0:0, 0:0:0);
(B2B1[4] => U[22]) = (0:0:0, 0:0:0);
(B2B1[4] => U[23]) = (0:0:0, 0:0:0);
(B2B1[4] => U[24]) = (0:0:0, 0:0:0);
(B2B1[4] => U[25]) = (0:0:0, 0:0:0);
(B2B1[4] => U[26]) = (0:0:0, 0:0:0);
(B2B1[4] => U[27]) = (0:0:0, 0:0:0);
(B2B1[4] => U[28]) = (0:0:0, 0:0:0);
(B2B1[4] => U[29]) = (0:0:0, 0:0:0);
(B2B1[4] => U[30]) = (0:0:0, 0:0:0);
(B2B1[4] => U[31]) = (0:0:0, 0:0:0);
(B2B1[4] => U[32]) = (0:0:0, 0:0:0);
(B2B1[4] => U[33]) = (0:0:0, 0:0:0);
(B2B1[4] => U[34]) = (0:0:0, 0:0:0);
(B2B1[4] => U[35]) = (0:0:0, 0:0:0);
(B2B1[4] => U[5]) = (0:0:0, 0:0:0);
(B2B1[4] => U[6]) = (0:0:0, 0:0:0);
(B2B1[4] => U[7]) = (0:0:0, 0:0:0);
(B2B1[4] => U[8]) = (0:0:0, 0:0:0);
(B2B1[4] => U[9]) = (0:0:0, 0:0:0);
(B2B1[4] => V[10]) = (0:0:0, 0:0:0);
(B2B1[4] => V[11]) = (0:0:0, 0:0:0);
(B2B1[4] => V[12]) = (0:0:0, 0:0:0);
(B2B1[4] => V[13]) = (0:0:0, 0:0:0);
(B2B1[4] => V[14]) = (0:0:0, 0:0:0);
(B2B1[4] => V[15]) = (0:0:0, 0:0:0);
(B2B1[4] => V[16]) = (0:0:0, 0:0:0);
(B2B1[4] => V[17]) = (0:0:0, 0:0:0);
(B2B1[4] => V[18]) = (0:0:0, 0:0:0);
(B2B1[4] => V[19]) = (0:0:0, 0:0:0);
(B2B1[4] => V[20]) = (0:0:0, 0:0:0);
(B2B1[4] => V[21]) = (0:0:0, 0:0:0);
(B2B1[4] => V[22]) = (0:0:0, 0:0:0);
(B2B1[4] => V[23]) = (0:0:0, 0:0:0);
(B2B1[4] => V[24]) = (0:0:0, 0:0:0);
(B2B1[4] => V[25]) = (0:0:0, 0:0:0);
(B2B1[4] => V[26]) = (0:0:0, 0:0:0);
(B2B1[4] => V[27]) = (0:0:0, 0:0:0);
(B2B1[4] => V[28]) = (0:0:0, 0:0:0);
(B2B1[4] => V[29]) = (0:0:0, 0:0:0);
(B2B1[4] => V[30]) = (0:0:0, 0:0:0);
(B2B1[4] => V[31]) = (0:0:0, 0:0:0);
(B2B1[4] => V[32]) = (0:0:0, 0:0:0);
(B2B1[4] => V[33]) = (0:0:0, 0:0:0);
(B2B1[4] => V[34]) = (0:0:0, 0:0:0);
(B2B1[4] => V[4]) = (0:0:0, 0:0:0);
(B2B1[4] => V[5]) = (0:0:0, 0:0:0);
(B2B1[4] => V[6]) = (0:0:0, 0:0:0);
(B2B1[4] => V[7]) = (0:0:0, 0:0:0);
(B2B1[4] => V[8]) = (0:0:0, 0:0:0);
(B2B1[4] => V[9]) = (0:0:0, 0:0:0);
(B2B1[5] => U[10]) = (0:0:0, 0:0:0);
(B2B1[5] => U[11]) = (0:0:0, 0:0:0);
(B2B1[5] => U[12]) = (0:0:0, 0:0:0);
(B2B1[5] => U[13]) = (0:0:0, 0:0:0);
(B2B1[5] => U[14]) = (0:0:0, 0:0:0);
(B2B1[5] => U[15]) = (0:0:0, 0:0:0);
(B2B1[5] => U[16]) = (0:0:0, 0:0:0);
(B2B1[5] => U[17]) = (0:0:0, 0:0:0);
(B2B1[5] => U[18]) = (0:0:0, 0:0:0);
(B2B1[5] => U[19]) = (0:0:0, 0:0:0);
(B2B1[5] => U[20]) = (0:0:0, 0:0:0);
(B2B1[5] => U[21]) = (0:0:0, 0:0:0);
(B2B1[5] => U[22]) = (0:0:0, 0:0:0);
(B2B1[5] => U[23]) = (0:0:0, 0:0:0);
(B2B1[5] => U[24]) = (0:0:0, 0:0:0);
(B2B1[5] => U[25]) = (0:0:0, 0:0:0);
(B2B1[5] => U[26]) = (0:0:0, 0:0:0);
(B2B1[5] => U[27]) = (0:0:0, 0:0:0);
(B2B1[5] => U[28]) = (0:0:0, 0:0:0);
(B2B1[5] => U[29]) = (0:0:0, 0:0:0);
(B2B1[5] => U[30]) = (0:0:0, 0:0:0);
(B2B1[5] => U[31]) = (0:0:0, 0:0:0);
(B2B1[5] => U[32]) = (0:0:0, 0:0:0);
(B2B1[5] => U[33]) = (0:0:0, 0:0:0);
(B2B1[5] => U[34]) = (0:0:0, 0:0:0);
(B2B1[5] => U[35]) = (0:0:0, 0:0:0);
(B2B1[5] => U[36]) = (0:0:0, 0:0:0);
(B2B1[5] => U[5]) = (0:0:0, 0:0:0);
(B2B1[5] => U[6]) = (0:0:0, 0:0:0);
(B2B1[5] => U[7]) = (0:0:0, 0:0:0);
(B2B1[5] => U[8]) = (0:0:0, 0:0:0);
(B2B1[5] => U[9]) = (0:0:0, 0:0:0);
(B2B1[5] => V[10]) = (0:0:0, 0:0:0);
(B2B1[5] => V[11]) = (0:0:0, 0:0:0);
(B2B1[5] => V[12]) = (0:0:0, 0:0:0);
(B2B1[5] => V[13]) = (0:0:0, 0:0:0);
(B2B1[5] => V[14]) = (0:0:0, 0:0:0);
(B2B1[5] => V[15]) = (0:0:0, 0:0:0);
(B2B1[5] => V[16]) = (0:0:0, 0:0:0);
(B2B1[5] => V[17]) = (0:0:0, 0:0:0);
(B2B1[5] => V[18]) = (0:0:0, 0:0:0);
(B2B1[5] => V[19]) = (0:0:0, 0:0:0);
(B2B1[5] => V[20]) = (0:0:0, 0:0:0);
(B2B1[5] => V[21]) = (0:0:0, 0:0:0);
(B2B1[5] => V[22]) = (0:0:0, 0:0:0);
(B2B1[5] => V[23]) = (0:0:0, 0:0:0);
(B2B1[5] => V[24]) = (0:0:0, 0:0:0);
(B2B1[5] => V[25]) = (0:0:0, 0:0:0);
(B2B1[5] => V[26]) = (0:0:0, 0:0:0);
(B2B1[5] => V[27]) = (0:0:0, 0:0:0);
(B2B1[5] => V[28]) = (0:0:0, 0:0:0);
(B2B1[5] => V[29]) = (0:0:0, 0:0:0);
(B2B1[5] => V[30]) = (0:0:0, 0:0:0);
(B2B1[5] => V[31]) = (0:0:0, 0:0:0);
(B2B1[5] => V[32]) = (0:0:0, 0:0:0);
(B2B1[5] => V[33]) = (0:0:0, 0:0:0);
(B2B1[5] => V[34]) = (0:0:0, 0:0:0);
(B2B1[5] => V[35]) = (0:0:0, 0:0:0);
(B2B1[5] => V[4]) = (0:0:0, 0:0:0);
(B2B1[5] => V[5]) = (0:0:0, 0:0:0);
(B2B1[5] => V[6]) = (0:0:0, 0:0:0);
(B2B1[5] => V[7]) = (0:0:0, 0:0:0);
(B2B1[5] => V[8]) = (0:0:0, 0:0:0);
(B2B1[5] => V[9]) = (0:0:0, 0:0:0);
(B2B1[6] => U[10]) = (0:0:0, 0:0:0);
(B2B1[6] => U[11]) = (0:0:0, 0:0:0);
(B2B1[6] => U[12]) = (0:0:0, 0:0:0);
(B2B1[6] => U[13]) = (0:0:0, 0:0:0);
(B2B1[6] => U[14]) = (0:0:0, 0:0:0);
(B2B1[6] => U[15]) = (0:0:0, 0:0:0);
(B2B1[6] => U[16]) = (0:0:0, 0:0:0);
(B2B1[6] => U[17]) = (0:0:0, 0:0:0);
(B2B1[6] => U[18]) = (0:0:0, 0:0:0);
(B2B1[6] => U[19]) = (0:0:0, 0:0:0);
(B2B1[6] => U[20]) = (0:0:0, 0:0:0);
(B2B1[6] => U[21]) = (0:0:0, 0:0:0);
(B2B1[6] => U[22]) = (0:0:0, 0:0:0);
(B2B1[6] => U[23]) = (0:0:0, 0:0:0);
(B2B1[6] => U[24]) = (0:0:0, 0:0:0);
(B2B1[6] => U[25]) = (0:0:0, 0:0:0);
(B2B1[6] => U[26]) = (0:0:0, 0:0:0);
(B2B1[6] => U[27]) = (0:0:0, 0:0:0);
(B2B1[6] => U[28]) = (0:0:0, 0:0:0);
(B2B1[6] => U[29]) = (0:0:0, 0:0:0);
(B2B1[6] => U[30]) = (0:0:0, 0:0:0);
(B2B1[6] => U[31]) = (0:0:0, 0:0:0);
(B2B1[6] => U[32]) = (0:0:0, 0:0:0);
(B2B1[6] => U[33]) = (0:0:0, 0:0:0);
(B2B1[6] => U[34]) = (0:0:0, 0:0:0);
(B2B1[6] => U[35]) = (0:0:0, 0:0:0);
(B2B1[6] => U[36]) = (0:0:0, 0:0:0);
(B2B1[6] => U[7]) = (0:0:0, 0:0:0);
(B2B1[6] => U[8]) = (0:0:0, 0:0:0);
(B2B1[6] => U[9]) = (0:0:0, 0:0:0);
(B2B1[6] => V[10]) = (0:0:0, 0:0:0);
(B2B1[6] => V[11]) = (0:0:0, 0:0:0);
(B2B1[6] => V[12]) = (0:0:0, 0:0:0);
(B2B1[6] => V[13]) = (0:0:0, 0:0:0);
(B2B1[6] => V[14]) = (0:0:0, 0:0:0);
(B2B1[6] => V[15]) = (0:0:0, 0:0:0);
(B2B1[6] => V[16]) = (0:0:0, 0:0:0);
(B2B1[6] => V[17]) = (0:0:0, 0:0:0);
(B2B1[6] => V[18]) = (0:0:0, 0:0:0);
(B2B1[6] => V[19]) = (0:0:0, 0:0:0);
(B2B1[6] => V[20]) = (0:0:0, 0:0:0);
(B2B1[6] => V[21]) = (0:0:0, 0:0:0);
(B2B1[6] => V[22]) = (0:0:0, 0:0:0);
(B2B1[6] => V[23]) = (0:0:0, 0:0:0);
(B2B1[6] => V[24]) = (0:0:0, 0:0:0);
(B2B1[6] => V[25]) = (0:0:0, 0:0:0);
(B2B1[6] => V[26]) = (0:0:0, 0:0:0);
(B2B1[6] => V[27]) = (0:0:0, 0:0:0);
(B2B1[6] => V[28]) = (0:0:0, 0:0:0);
(B2B1[6] => V[29]) = (0:0:0, 0:0:0);
(B2B1[6] => V[30]) = (0:0:0, 0:0:0);
(B2B1[6] => V[31]) = (0:0:0, 0:0:0);
(B2B1[6] => V[32]) = (0:0:0, 0:0:0);
(B2B1[6] => V[33]) = (0:0:0, 0:0:0);
(B2B1[6] => V[34]) = (0:0:0, 0:0:0);
(B2B1[6] => V[35]) = (0:0:0, 0:0:0);
(B2B1[6] => V[6]) = (0:0:0, 0:0:0);
(B2B1[6] => V[7]) = (0:0:0, 0:0:0);
(B2B1[6] => V[8]) = (0:0:0, 0:0:0);
(B2B1[6] => V[9]) = (0:0:0, 0:0:0);
(B2B1[7] => U[10]) = (0:0:0, 0:0:0);
(B2B1[7] => U[11]) = (0:0:0, 0:0:0);
(B2B1[7] => U[12]) = (0:0:0, 0:0:0);
(B2B1[7] => U[13]) = (0:0:0, 0:0:0);
(B2B1[7] => U[14]) = (0:0:0, 0:0:0);
(B2B1[7] => U[15]) = (0:0:0, 0:0:0);
(B2B1[7] => U[16]) = (0:0:0, 0:0:0);
(B2B1[7] => U[17]) = (0:0:0, 0:0:0);
(B2B1[7] => U[18]) = (0:0:0, 0:0:0);
(B2B1[7] => U[19]) = (0:0:0, 0:0:0);
(B2B1[7] => U[20]) = (0:0:0, 0:0:0);
(B2B1[7] => U[21]) = (0:0:0, 0:0:0);
(B2B1[7] => U[22]) = (0:0:0, 0:0:0);
(B2B1[7] => U[23]) = (0:0:0, 0:0:0);
(B2B1[7] => U[24]) = (0:0:0, 0:0:0);
(B2B1[7] => U[25]) = (0:0:0, 0:0:0);
(B2B1[7] => U[26]) = (0:0:0, 0:0:0);
(B2B1[7] => U[27]) = (0:0:0, 0:0:0);
(B2B1[7] => U[28]) = (0:0:0, 0:0:0);
(B2B1[7] => U[29]) = (0:0:0, 0:0:0);
(B2B1[7] => U[30]) = (0:0:0, 0:0:0);
(B2B1[7] => U[31]) = (0:0:0, 0:0:0);
(B2B1[7] => U[32]) = (0:0:0, 0:0:0);
(B2B1[7] => U[33]) = (0:0:0, 0:0:0);
(B2B1[7] => U[34]) = (0:0:0, 0:0:0);
(B2B1[7] => U[35]) = (0:0:0, 0:0:0);
(B2B1[7] => U[36]) = (0:0:0, 0:0:0);
(B2B1[7] => U[37]) = (0:0:0, 0:0:0);
(B2B1[7] => U[38]) = (0:0:0, 0:0:0);
(B2B1[7] => U[7]) = (0:0:0, 0:0:0);
(B2B1[7] => U[8]) = (0:0:0, 0:0:0);
(B2B1[7] => U[9]) = (0:0:0, 0:0:0);
(B2B1[7] => V[10]) = (0:0:0, 0:0:0);
(B2B1[7] => V[11]) = (0:0:0, 0:0:0);
(B2B1[7] => V[12]) = (0:0:0, 0:0:0);
(B2B1[7] => V[13]) = (0:0:0, 0:0:0);
(B2B1[7] => V[14]) = (0:0:0, 0:0:0);
(B2B1[7] => V[15]) = (0:0:0, 0:0:0);
(B2B1[7] => V[16]) = (0:0:0, 0:0:0);
(B2B1[7] => V[17]) = (0:0:0, 0:0:0);
(B2B1[7] => V[18]) = (0:0:0, 0:0:0);
(B2B1[7] => V[19]) = (0:0:0, 0:0:0);
(B2B1[7] => V[20]) = (0:0:0, 0:0:0);
(B2B1[7] => V[21]) = (0:0:0, 0:0:0);
(B2B1[7] => V[22]) = (0:0:0, 0:0:0);
(B2B1[7] => V[23]) = (0:0:0, 0:0:0);
(B2B1[7] => V[24]) = (0:0:0, 0:0:0);
(B2B1[7] => V[25]) = (0:0:0, 0:0:0);
(B2B1[7] => V[26]) = (0:0:0, 0:0:0);
(B2B1[7] => V[27]) = (0:0:0, 0:0:0);
(B2B1[7] => V[28]) = (0:0:0, 0:0:0);
(B2B1[7] => V[29]) = (0:0:0, 0:0:0);
(B2B1[7] => V[30]) = (0:0:0, 0:0:0);
(B2B1[7] => V[31]) = (0:0:0, 0:0:0);
(B2B1[7] => V[32]) = (0:0:0, 0:0:0);
(B2B1[7] => V[33]) = (0:0:0, 0:0:0);
(B2B1[7] => V[34]) = (0:0:0, 0:0:0);
(B2B1[7] => V[35]) = (0:0:0, 0:0:0);
(B2B1[7] => V[36]) = (0:0:0, 0:0:0);
(B2B1[7] => V[37]) = (0:0:0, 0:0:0);
(B2B1[7] => V[6]) = (0:0:0, 0:0:0);
(B2B1[7] => V[7]) = (0:0:0, 0:0:0);
(B2B1[7] => V[8]) = (0:0:0, 0:0:0);
(B2B1[7] => V[9]) = (0:0:0, 0:0:0);
(B2B1[8] => U[10]) = (0:0:0, 0:0:0);
(B2B1[8] => U[11]) = (0:0:0, 0:0:0);
(B2B1[8] => U[12]) = (0:0:0, 0:0:0);
(B2B1[8] => U[13]) = (0:0:0, 0:0:0);
(B2B1[8] => U[14]) = (0:0:0, 0:0:0);
(B2B1[8] => U[15]) = (0:0:0, 0:0:0);
(B2B1[8] => U[16]) = (0:0:0, 0:0:0);
(B2B1[8] => U[17]) = (0:0:0, 0:0:0);
(B2B1[8] => U[18]) = (0:0:0, 0:0:0);
(B2B1[8] => U[19]) = (0:0:0, 0:0:0);
(B2B1[8] => U[20]) = (0:0:0, 0:0:0);
(B2B1[8] => U[21]) = (0:0:0, 0:0:0);
(B2B1[8] => U[22]) = (0:0:0, 0:0:0);
(B2B1[8] => U[23]) = (0:0:0, 0:0:0);
(B2B1[8] => U[24]) = (0:0:0, 0:0:0);
(B2B1[8] => U[25]) = (0:0:0, 0:0:0);
(B2B1[8] => U[26]) = (0:0:0, 0:0:0);
(B2B1[8] => U[27]) = (0:0:0, 0:0:0);
(B2B1[8] => U[28]) = (0:0:0, 0:0:0);
(B2B1[8] => U[29]) = (0:0:0, 0:0:0);
(B2B1[8] => U[30]) = (0:0:0, 0:0:0);
(B2B1[8] => U[31]) = (0:0:0, 0:0:0);
(B2B1[8] => U[32]) = (0:0:0, 0:0:0);
(B2B1[8] => U[33]) = (0:0:0, 0:0:0);
(B2B1[8] => U[34]) = (0:0:0, 0:0:0);
(B2B1[8] => U[35]) = (0:0:0, 0:0:0);
(B2B1[8] => U[36]) = (0:0:0, 0:0:0);
(B2B1[8] => U[37]) = (0:0:0, 0:0:0);
(B2B1[8] => U[38]) = (0:0:0, 0:0:0);
(B2B1[8] => U[9]) = (0:0:0, 0:0:0);
(B2B1[8] => V[10]) = (0:0:0, 0:0:0);
(B2B1[8] => V[11]) = (0:0:0, 0:0:0);
(B2B1[8] => V[12]) = (0:0:0, 0:0:0);
(B2B1[8] => V[13]) = (0:0:0, 0:0:0);
(B2B1[8] => V[14]) = (0:0:0, 0:0:0);
(B2B1[8] => V[15]) = (0:0:0, 0:0:0);
(B2B1[8] => V[16]) = (0:0:0, 0:0:0);
(B2B1[8] => V[17]) = (0:0:0, 0:0:0);
(B2B1[8] => V[18]) = (0:0:0, 0:0:0);
(B2B1[8] => V[19]) = (0:0:0, 0:0:0);
(B2B1[8] => V[20]) = (0:0:0, 0:0:0);
(B2B1[8] => V[21]) = (0:0:0, 0:0:0);
(B2B1[8] => V[22]) = (0:0:0, 0:0:0);
(B2B1[8] => V[23]) = (0:0:0, 0:0:0);
(B2B1[8] => V[24]) = (0:0:0, 0:0:0);
(B2B1[8] => V[25]) = (0:0:0, 0:0:0);
(B2B1[8] => V[26]) = (0:0:0, 0:0:0);
(B2B1[8] => V[27]) = (0:0:0, 0:0:0);
(B2B1[8] => V[28]) = (0:0:0, 0:0:0);
(B2B1[8] => V[29]) = (0:0:0, 0:0:0);
(B2B1[8] => V[30]) = (0:0:0, 0:0:0);
(B2B1[8] => V[31]) = (0:0:0, 0:0:0);
(B2B1[8] => V[32]) = (0:0:0, 0:0:0);
(B2B1[8] => V[33]) = (0:0:0, 0:0:0);
(B2B1[8] => V[34]) = (0:0:0, 0:0:0);
(B2B1[8] => V[35]) = (0:0:0, 0:0:0);
(B2B1[8] => V[36]) = (0:0:0, 0:0:0);
(B2B1[8] => V[37]) = (0:0:0, 0:0:0);
(B2B1[8] => V[8]) = (0:0:0, 0:0:0);
(B2B1[8] => V[9]) = (0:0:0, 0:0:0);
(B2B1[9] => U[10]) = (0:0:0, 0:0:0);
(B2B1[9] => U[11]) = (0:0:0, 0:0:0);
(B2B1[9] => U[12]) = (0:0:0, 0:0:0);
(B2B1[9] => U[13]) = (0:0:0, 0:0:0);
(B2B1[9] => U[14]) = (0:0:0, 0:0:0);
(B2B1[9] => U[15]) = (0:0:0, 0:0:0);
(B2B1[9] => U[16]) = (0:0:0, 0:0:0);
(B2B1[9] => U[17]) = (0:0:0, 0:0:0);
(B2B1[9] => U[18]) = (0:0:0, 0:0:0);
(B2B1[9] => U[19]) = (0:0:0, 0:0:0);
(B2B1[9] => U[20]) = (0:0:0, 0:0:0);
(B2B1[9] => U[21]) = (0:0:0, 0:0:0);
(B2B1[9] => U[22]) = (0:0:0, 0:0:0);
(B2B1[9] => U[23]) = (0:0:0, 0:0:0);
(B2B1[9] => U[24]) = (0:0:0, 0:0:0);
(B2B1[9] => U[25]) = (0:0:0, 0:0:0);
(B2B1[9] => U[26]) = (0:0:0, 0:0:0);
(B2B1[9] => U[27]) = (0:0:0, 0:0:0);
(B2B1[9] => U[28]) = (0:0:0, 0:0:0);
(B2B1[9] => U[29]) = (0:0:0, 0:0:0);
(B2B1[9] => U[30]) = (0:0:0, 0:0:0);
(B2B1[9] => U[31]) = (0:0:0, 0:0:0);
(B2B1[9] => U[32]) = (0:0:0, 0:0:0);
(B2B1[9] => U[33]) = (0:0:0, 0:0:0);
(B2B1[9] => U[34]) = (0:0:0, 0:0:0);
(B2B1[9] => U[35]) = (0:0:0, 0:0:0);
(B2B1[9] => U[36]) = (0:0:0, 0:0:0);
(B2B1[9] => U[37]) = (0:0:0, 0:0:0);
(B2B1[9] => U[38]) = (0:0:0, 0:0:0);
(B2B1[9] => U[39]) = (0:0:0, 0:0:0);
(B2B1[9] => U[40]) = (0:0:0, 0:0:0);
(B2B1[9] => U[9]) = (0:0:0, 0:0:0);
(B2B1[9] => V[10]) = (0:0:0, 0:0:0);
(B2B1[9] => V[11]) = (0:0:0, 0:0:0);
(B2B1[9] => V[12]) = (0:0:0, 0:0:0);
(B2B1[9] => V[13]) = (0:0:0, 0:0:0);
(B2B1[9] => V[14]) = (0:0:0, 0:0:0);
(B2B1[9] => V[15]) = (0:0:0, 0:0:0);
(B2B1[9] => V[16]) = (0:0:0, 0:0:0);
(B2B1[9] => V[17]) = (0:0:0, 0:0:0);
(B2B1[9] => V[18]) = (0:0:0, 0:0:0);
(B2B1[9] => V[19]) = (0:0:0, 0:0:0);
(B2B1[9] => V[20]) = (0:0:0, 0:0:0);
(B2B1[9] => V[21]) = (0:0:0, 0:0:0);
(B2B1[9] => V[22]) = (0:0:0, 0:0:0);
(B2B1[9] => V[23]) = (0:0:0, 0:0:0);
(B2B1[9] => V[24]) = (0:0:0, 0:0:0);
(B2B1[9] => V[25]) = (0:0:0, 0:0:0);
(B2B1[9] => V[26]) = (0:0:0, 0:0:0);
(B2B1[9] => V[27]) = (0:0:0, 0:0:0);
(B2B1[9] => V[28]) = (0:0:0, 0:0:0);
(B2B1[9] => V[29]) = (0:0:0, 0:0:0);
(B2B1[9] => V[30]) = (0:0:0, 0:0:0);
(B2B1[9] => V[31]) = (0:0:0, 0:0:0);
(B2B1[9] => V[32]) = (0:0:0, 0:0:0);
(B2B1[9] => V[33]) = (0:0:0, 0:0:0);
(B2B1[9] => V[34]) = (0:0:0, 0:0:0);
(B2B1[9] => V[35]) = (0:0:0, 0:0:0);
(B2B1[9] => V[36]) = (0:0:0, 0:0:0);
(B2B1[9] => V[37]) = (0:0:0, 0:0:0);
(B2B1[9] => V[38]) = (0:0:0, 0:0:0);
(B2B1[9] => V[39]) = (0:0:0, 0:0:0);
(B2B1[9] => V[8]) = (0:0:0, 0:0:0);
(B2B1[9] => V[9]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule |
module sky130_fd_sc_ls__a311oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__a311oi_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule |
module fsa_stream_v2 #(
parameter integer C_OUT_DW = 24, /// C_CHANNEL_WIDTH * 3
parameter integer C_OUT_DV = 1,
parameter integer C_IMG_HW = 12,
parameter integer C_IMG_WW = 12,
parameter integer BR_AW = 12, /// same as C_IMG_WW
parameter integer C_CHANNEL_WIDTH = 8,
parameter integer C_S_CHANNEL = 1
)(
input clk,
input resetn,
input wire [C_IMG_HW-1:0] height ,
input wire [C_IMG_WW-1:0] width ,
input wire fsync ,
input wire en_overlay,
output wire rd_sof ,
output wire rd_en ,
output wire [BR_AW-1:0] rd_addr ,
input wire rd_black,
input wire rd_val_outer,
input wire [C_IMG_HW-1:0] rd_top_outer,
input wire [C_IMG_HW-1:0] rd_bot_outer,
input wire rd_val_inner,
input wire [C_IMG_HW-1:0] rd_top_inner,
input wire [C_IMG_HW-1:0] rd_bot_inner,
input wire lft_valid ,
input wire [C_IMG_WW-1:0] lft_edge ,
input wire rt_valid ,
input wire [C_IMG_WW-1:0] rt_edge ,
input wire lft_header_outer_valid,
input wire [C_IMG_WW-1:0] lft_header_outer_x ,
input wire lft_corner_valid,
input wire [C_IMG_WW-1:0] lft_corner_top_x,
input wire [C_IMG_HW-1:0] lft_corner_top_y,
input wire [C_IMG_WW-1:0] lft_corner_bot_x,
input wire [C_IMG_HW-1:0] lft_corner_bot_y,
input wire rt_header_outer_valid,
input wire [C_IMG_WW-1:0] rt_header_outer_x ,
input wire rt_corner_valid,
input wire [C_IMG_WW-1:0] rt_corner_top_x,
input wire [C_IMG_HW-1:0] rt_corner_top_y,
input wire [C_IMG_WW-1:0] rt_corner_bot_x,
input wire [C_IMG_HW-1:0] rt_corner_bot_y,
input wire s_axis_tvalid,
input wire [C_CHANNEL_WIDTH*C_S_CHANNEL-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
input wire [C_IMG_WW-1:0] s_axis_source_x,
input wire [C_IMG_HW-1:0] s_axis_source_y,
output wire m_axis_tvalid,
output wire [C_CHANNEL_WIDTH*3-1:0] m_axis_tdata,
output wire m_axis_tuser,
output wire m_axis_tlast,
input wire m_axis_tready
);
localparam integer C_STAGE_WIDTH = 2 + C_CHANNEL_WIDTH*C_S_CHANNEL;
localparam integer FIFO_DW = 2 + C_OUT_DW;
localparam integer FD_SOF = 0;
localparam integer FD_LAST = 1;
localparam integer FD_DATA = 2;
assign rd_sof = fsync;
assign rd_en = s_axis_tvalid && s_axis_tready;
assign rd_addr = s_axis_source_x;
reg rd_en_d1;
reg [C_IMG_HW-1:0] py_d1;
reg [C_IMG_WW-1:0] px_d1;
reg [C_STAGE_WIDTH-1:0] data_d1;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d1 <= 0;
py_d1 <= 0;
px_d1 <= 0;
data_d1 <= 0;
end
else begin
rd_en_d1 <= rd_en;
px_d1 <= s_axis_source_x;
py_d1 <= s_axis_source_y;
data_d1 <= {s_axis_tdata, s_axis_tlast, s_axis_tuser};
end
end
reg rd_en_d2;
reg [C_IMG_HW-1:0] py_d2;
reg [C_IMG_WW-1:0] px_d2;
reg [C_STAGE_WIDTH-1:0] data_d2;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d2 <= 0;
py_d2 <= 0;
px_d2 <= 0;
data_d2 <= 0;
end
else begin
rd_en_d2 <= rd_en_d1;
px_d2 <= px_d1;
py_d2 <= py_d1;
data_d2 <= data_d1;
end
end
reg rd_en_d3;
reg [C_IMG_HW-1:0] py_d3;
reg [C_IMG_WW-1:0] px_d3;
reg [C_STAGE_WIDTH-1:0] data_d3;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d3 <= 0;
py_d3 <= 0;
px_d3 <= 0;
data_d3 <= 0;
end
else begin
rd_en_d3 <= rd_en_d2;
py_d3 <= py_d2;
px_d3 <= px_d2;
data_d3 <= data_d2;
end
end
/// rd_data is valid
reg rd_en_d4;
reg [C_IMG_HW-1:0] py_d4;
reg [C_STAGE_WIDTH-1:0] data_d4;
/// corner
reg lc_t;
reg lc_b;
reg rc_t;
reg rc_b;
/// body
reg lb;
reg lb_t;
reg lb_b;
reg rb;
reg rb_t;
reg rb_b;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d4 <= 0;
py_d4 <= 0;
data_d4 <= 0;
lc_t <= 0;
lc_b <= 0;
rc_t <= 0;
rc_b <= 0;
lb <= 0;
lb_t <= 0;
lb_b <= 0;
rb <= 0;
rb_t <= 0;
rb_b <= 0;
end
else begin
rd_en_d4 <= rd_en_d3;
py_d4 <= py_d3;
data_d4 <= data_d3;
// @note if we use single result for multiple blockram, the image noise will result in vibrate
// header, then the defect will extent to image top at header column.
// if we blockram and result is one2one, then we can drop 'rd_val_outer', the lef_edge/rt_edge
// will work as expected.
lc_t <= (lft_corner_valid && rd_val_outer) && ((lft_corner_top_y <= py_d3 && py_d3 < rd_top_outer)
&& (lft_corner_top_x < px_d3 && px_d3 <= lft_edge));
lc_b <= (lft_corner_valid && rd_val_outer) && ((lft_corner_bot_y >= py_d3 && py_d3 > rd_bot_outer)
&& (lft_corner_bot_x < px_d3 && px_d3 <= lft_edge));
rc_t <= (rt_corner_valid && rd_val_outer) && ((rt_corner_top_y <= py_d3 && py_d3 < rd_top_outer)
&& (rt_edge <= px_d3 && px_d3 < rt_corner_top_x));
rc_b <= (rt_corner_valid && rd_val_outer) && ((rt_corner_bot_y >= py_d3 && py_d3 > rd_bot_outer)
&& (rt_edge <= px_d3 && px_d3 < rt_corner_bot_x));
lb <= lft_header_outer_valid && (px_d3 <= lft_header_outer_x);
rb <= rt_header_outer_valid && (px_d3 >= rt_header_outer_x);
lb_t <= lft_corner_valid && ((px_d3 <= lft_corner_top_x) && (py_d3 < rd_top_outer));
lb_b <= lft_corner_valid && ((px_d3 <= lft_corner_bot_x) && (py_d3 > rd_bot_outer));
rb_t <= rt_corner_valid && ((px_d3 >= rt_corner_top_x) && (py_d3 < rd_top_outer));
rb_b <= rt_corner_valid && ((px_d3 >= rt_corner_bot_x) && (py_d3 > rd_bot_outer));
end
end
/// @NOTE: delay 5, the almost_full for blockram must be 6
/// if you add delay, don't forget to change blockram config.
reg rd_en_d5;
reg [FIFO_DW-1 : 0] out_data_d5;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d5 <= 0;
out_data_d5 <= 0;
end
else begin
rd_en_d5 <= rd_en_d4;
out_data_d5[FD_SOF] <= data_d4[FD_SOF];
out_data_d5[FD_LAST] <= data_d4[FD_LAST];
if (en_overlay && ((lft_valid && (lc_t | lc_b))
|| (rt_valid && (rc_t | rc_b)))) begin
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= C_OUT_DV;
end
else begin
if (C_S_CHANNEL == 1) begin
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= {
data_d4[C_STAGE_WIDTH-1:FD_DATA],
data_d4[C_STAGE_WIDTH-1:FD_DATA],
data_d4[C_STAGE_WIDTH-1:FD_DATA]};
end
else if (C_S_CHANNEL == 3) begin
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= data_d4[C_STAGE_WIDTH-1:FD_DATA];
end
else begin
/// @ERROR
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= 0;
end
end
end
end
//////////////////////////////////////////////////// FIFO ////////////////////////////////////////
wire fw_en;
wire [FIFO_DW-1:0] fw_data;
wire fw_af;
wire fr_en;
wire[FIFO_DW-1:0] fr_data;
wire fr_empty;
simple_fifo # (
.DEPTH_WIDTH(3),
.DATA_WIDTH(FIFO_DW),
.ALMOST_FULL_TH(6),
.ALMOST_EMPTY_TH(1)
) fifo_inst (
.clk(clk),
.rst(~resetn),
.wr_data(fw_data),
.wr_en (fw_en ),
.rd_data(fr_data),
.rd_en (fr_en ),
.full(),
.empty(fr_empty),
.almost_full(fw_af),
.almost_empty()
);
assign fw_en = rd_en_d5;
assign fw_data = out_data_d5;
assign fr_en = (~m_axis_tvalid || m_axis_tready) && ~fr_empty;
assign s_axis_tready = ~fw_af;
reg axis_tvalid;
assign m_axis_tvalid = axis_tvalid;
always @(posedge clk) begin
if (resetn == 0)
axis_tvalid <= 0;
else if (fr_en)
axis_tvalid <= 1;
else if (m_axis_tready)
axis_tvalid <= 0;
end
assign m_axis_tdata = fr_data[FIFO_DW-1:FD_DATA];
assign m_axis_tuser = fr_data[FD_SOF];
assign m_axis_tlast = fr_data[FD_LAST];
endmodule |
module top();
// Inputs are registered
reg UDP_IN;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 UDP_IN = 1'b1;
#80 VGND = 1'b1;
#100 UDP_IN = 1'b0;
#120 VGND = 1'b0;
#140 VGND = 1'b1;
#160 UDP_IN = 1'b1;
#180 VGND = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_ms__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule |
module PIO_EP #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
input clk,
input rst_n,
// AXIS TX
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [STRB_WIDTH-1:0] s_axis_tx_tstrb,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
//AXIS RX
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [STRB_WIDTH-1:0] m_axis_rx_tstrb,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output req_compl_o,
output compl_done_o,
input [15:0] cfg_completer_id,
input cfg_bus_mstr_enable
);
// Local wires
wire [10:0] rd_addr;
wire [3:0] rd_be;
wire [31:0] rd_data;
wire [10:0] wr_addr;
wire [7:0] wr_be;
wire [31:0] wr_data;
wire wr_en;
wire wr_busy;
wire req_compl;
wire req_compl_wd;
wire compl_done;
wire [2:0] req_tc;
wire req_td;
wire req_ep;
wire [1:0] req_attr;
wire [9:0] req_len;
wire [15:0] req_rid;
wire [7:0] req_tag;
wire [7:0] req_be;
wire [12:0] req_addr;
//
// ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
//
PIO_EP_MEM_ACCESS EP_MEM (
.clk(clk), // I
.rst_n(rst_n), // I
// Read Port
.rd_addr_i(rd_addr), // I [10:0]
.rd_be_i(rd_be), // I [3:0]
.rd_data_o(rd_data), // O [31:0]
// Write Port
.wr_addr_i(wr_addr), // I [10:0]
.wr_be_i(wr_be), // I [7:0]
.wr_data_i(wr_data), // I [31:0]
.wr_en_i(wr_en), // I
.wr_busy_o(wr_busy) // O
);
//
// Local-Link Receive Controller
//
PIO_64_RX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) EP_RX (
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS RX
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tstrb( m_axis_rx_tstrb ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
// Handshake with Tx engine
.req_compl_o(req_compl), // O
.req_compl_wd_o(req_compl_wd), // O
.compl_done_i(compl_done), // I
.req_tc_o(req_tc), // O [2:0]
.req_td_o(req_td), // O
.req_ep_o(req_ep), // O
.req_attr_o(req_attr), // O [1:0]
.req_len_o(req_len), // O [9:0]
.req_rid_o(req_rid), // O [15:0]
.req_tag_o(req_tag), // O [7:0]
.req_be_o(req_be), // O [7:0]
.req_addr_o(req_addr), // O [12:0]
// Memory Write Port
.wr_addr_o(wr_addr), // O [10:0]
.wr_be_o(wr_be), // O [7:0]
.wr_data_o(wr_data), // O [31:0]
.wr_en_o(wr_en), // O
.wr_busy_i(wr_busy) // I
);
//
// Local-Link Transmit Controller
//
PIO_64_TX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
)EP_TX(
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS Tx
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tstrb( s_axis_tx_tstrb ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
// Handshake with Rx engine
.req_compl_i(req_compl), // I
.req_compl_wd_i(req_compl_wd), // I
.compl_done_o(compl_done), // 0
.req_tc_i(req_tc), // I [2:0]
.req_td_i(req_td), // I
.req_ep_i(req_ep), // I
.req_attr_i(req_attr), // I [1:0]
.req_len_i(req_len), // I [9:0]
.req_rid_i(req_rid), // I [15:0]
.req_tag_i(req_tag), // I [7:0]
.req_be_i(req_be), // I [7:0]
.req_addr_i(req_addr), // I [12:0]
// Read Port
.rd_addr_o(rd_addr), // O [10:0]
.rd_be_o(rd_be), // O [3:0]
.rd_data_i(rd_data), // I [31:0]
.completer_id_i(cfg_completer_id), // I [15:0]
.cfg_bus_mstr_enable_i(cfg_bus_mstr_enable) // I
);
assign req_compl_o = req_compl;
assign compl_done_o = compl_done;
endmodule |
module ADT7410 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7410.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7410.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7410.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7410.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_ReceiveSend_n", src = "../../verilog/adt7410.v:11" *)
output I2C_ReceiveSend_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_ReadCount", src = "../../verilog/adt7410.v:13" *)
output[7:0] I2C_ReadCount_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_StartProcess", src = "../../verilog/adt7410.v:15" *)
output I2C_StartProcess_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Busy", src = "../../verilog/adt7410.v:17" *)
input I2C_Busy_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOReadNext", src = "../../verilog/adt7410.v:19" *)
output I2C_FIFOReadNext_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOWrite", src = "../../verilog/adt7410.v:21" *)
output I2C_FIFOWrite_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataIn", src = "../../verilog/adt7410.v:23" *)
output[7:0] I2C_Data_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataOut", src = "../../verilog/adt7410.v:25" *)
input[7:0] I2C_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Error", src = "../../verilog/adt7410.v:27" *)
input I2C_Error_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7410.v:29" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7410.v:31" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7410.v:33" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPreset_i", src = "../../verilog/adt7410.v:35" *)
input[15:0] WaitCounterPreset_i
);
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.Overflow_s ;
wire \$techmap\I2CFSM_1.$procmux$1156_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1168_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1169_CMP ;
wire [7:0] \$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.Overflow_s ;
(* src = "../../verilog/i2cfsm.v:10" *)
wire [7:0] \I2CFSM_1.Byte0_o ;
(* src = "../../verilog/i2cfsm.v:11" *)
wire [7:0] \I2CFSM_1.Byte1_o ;
(* src = "../../verilog/i2cfsm.v:8" *)
wire \I2CFSM_1.Done_o ;
(* src = "../../verilog/i2cfsm.v:9" *)
wire \I2CFSM_1.Error_o ;
(* src = "../../verilog/i2cfsm.v:77" *)
wire \I2CFSM_1.I2C_FSM_TimerEnable ;
(* src = "../../verilog/i2cfsm.v:75" *)
wire \I2CFSM_1.I2C_FSM_TimerOvfl ;
(* src = "../../verilog/i2cfsm.v:76" *)
wire \I2CFSM_1.I2C_FSM_TimerPreset ;
(* src = "../../verilog/i2cfsm.v:79" *)
wire \I2CFSM_1.I2C_FSM_Wr0 ;
(* src = "../../verilog/i2cfsm.v:78" *)
wire \I2CFSM_1.I2C_FSM_Wr1 ;
(* src = "../../verilog/i2cfsm.v:7" *)
wire \I2CFSM_1.Start_i ;
(* src = "../../verilog/sensorfsm.v:41" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:35" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.SensorValue ;
wire TRFSM1_1_Out14_s;
wire TRFSM1_1_CfgMode_s;
wire TRFSM1_1_CfgClk_s;
wire TRFSM1_1_CfgShift_s;
wire TRFSM1_1_CfgDataIn_s;
wire TRFSM1_1_CfgDataOut_s;
wire TRFSM0_1_Out5_s;
wire TRFSM0_1_Out6_s;
wire TRFSM0_1_Out7_s;
wire TRFSM0_1_Out8_s;
wire TRFSM0_1_Out9_s;
wire TRFSM0_1_CfgMode_s;
wire TRFSM0_1_CfgClk_s;
wire TRFSM0_1_CfgShift_s;
wire TRFSM0_1_CfgDataIn_s;
wire TRFSM0_1_CfgDataOut_s;
Byte2Word \$extract$\Byte2Word$2915 (
.H_i(\I2CFSM_1.Byte1_o ),
.L_i(\I2CFSM_1.Byte0_o ),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2910 (
.A_i(8'b00000000),
.B_i(8'b00000010),
.S_i(I2C_ReceiveSend_n_o),
.Y_o(I2C_ReadCount_o)
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2911 (
.A_i(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ),
.B_i(8'b00000011),
.S_i(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Y_o(I2C_Data_o)
);
ByteMuxQuad \$techmap\I2CFSM_1.$extract$\ByteMuxQuad$2909 (
.A_i(8'b00000000),
.B_i(8'b10010001),
.C_i(8'b10010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.SC_i(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.SD_i(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Y_o(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y )
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2906 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr0 ),
.Q_o(\I2CFSM_1.Byte0_o ),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2907 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr1 ),
.Q_o(\I2CFSM_1.Byte1_o ),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.D_s ),
.Direction_i(1'b1),
.Enable_i(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Overflow_o(\$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.Overflow_s ),
.PresetVal_i(WaitCounterPreset_i),
.Preset_i(\I2CFSM_1.I2C_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\I2CFSM_1.I2C_FSM_TimerOvfl )
);
TRFSM1 TRFSM1_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(I2C_Busy_i),
.In1_i(I2C_Error_i),
.In2_i(\I2CFSM_1.I2C_FSM_TimerOvfl ),
.In3_i(\I2CFSM_1.Start_i ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.Out1_o(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Out2_o(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Out3_o(\I2CFSM_1.Done_o ),
.Out4_o(\I2CFSM_1.I2C_FSM_Wr0 ),
.Out5_o(I2C_ReceiveSend_n_o),
.Out6_o(I2C_StartProcess_o),
.Out7_o(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.Out8_o(\I2CFSM_1.Error_o ),
.Out9_o(\I2CFSM_1.I2C_FSM_Wr1 ),
.Out10_o(I2C_FIFOReadNext_o),
.Out11_o(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Out12_o(\I2CFSM_1.I2C_FSM_TimerPreset ),
.Out13_o(I2C_FIFOWrite_o),
.Out14_o(TRFSM1_1_Out14_s),
.CfgMode_i(TRFSM1_1_CfgMode_s),
.CfgClk_i(TRFSM1_1_CfgClk_s),
.CfgShift_i(TRFSM1_1_CfgShift_s),
.CfgDataIn_i(TRFSM1_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM1_1_CfgDataOut_s)
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2904 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.D_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2905 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
TRFSM0 TRFSM0_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(\I2CFSM_1.Done_o ),
.In2_i(\I2CFSM_1.Error_o ),
.In3_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In4_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.In5_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ),
.Out0_o(\I2CFSM_1.Start_i ),
.Out1_o(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Out2_o(CpuIntr_o),
.Out3_o(\SensorFSM_1.SensorFSM_TimerEnable ),
.Out4_o(\SensorFSM_1.SensorFSM_TimerPreset ),
.Out5_o(TRFSM0_1_Out5_s),
.Out6_o(TRFSM0_1_Out6_s),
.Out7_o(TRFSM0_1_Out7_s),
.Out8_o(TRFSM0_1_Out8_s),
.Out9_o(TRFSM0_1_Out9_s),
.CfgMode_i(TRFSM0_1_CfgMode_s),
.CfgClk_i(TRFSM0_1_CfgClk_s),
.CfgShift_i(TRFSM0_1_CfgShift_s),
.CfgDataIn_i(TRFSM0_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM0_1_CfgDataOut_s)
);
assign TRFSM1_1_CfgMode_s = 1'b0;
assign TRFSM1_1_CfgClk_s = 1'b0;
assign TRFSM1_1_CfgShift_s = 1'b0;
assign TRFSM1_1_CfgDataIn_s = 1'b0;
assign TRFSM0_1_CfgMode_s = 1'b0;
assign TRFSM0_1_CfgClk_s = 1'b0;
assign TRFSM0_1_CfgShift_s = 1'b0;
assign TRFSM0_1_CfgDataIn_s = 1'b0;
endmodule |
module sky130_fd_sc_hd__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule |
module sky130_fd_sc_hs__o311a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__o311a_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule |
module B_AudioClkGen_v0_83 (
clkout,
clk,
sync_sof
);
output clkout;
input clk;
input sync_sof;
//`#start body` -- edit after this line, do not edit this line
wire transfer;
wire sync_ready;
wire sync_done;
wire value;
wire delta;
wire trigger_shaper;
wire clk_async;
//SOFConunter to sync to USB
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE)) CtlClkSync
(
/* input */ .clock_in(clk),
/* input */ .enable(1'b1),
/* output */ .clock_out(clk_async)
);
SOFCounter sync(
.done(sync_done),
.ready(sync_ready),
.value(value),
.clk(clk_async),
.sof(sync_sof),
.start(transfer)
);
Shaper1stOrder shaper(
.delta(delta),
.transfer(transfer),
.clk(clk_async),
.done(sync_done),
.ready(sync_ready),
.start(trigger_shaper),
.value(value)
);
DivNorNPlus1 div(
.clkout(clkout),
.start(trigger_shaper),
.clk(clk_async),
.delta(delta)
);
//`#end` -- edit above this line, do not edit this line
endmodule |
module SOFCounter (
done,
ready,
value,
clk,
sof,
start
);
output done;
output ready;
output value;
input clk;
input sof;
input start;
wire [1:0] so;
reg ready;
reg [3:0] state;
wire [2:0] addr = state[2:0];
reg [2:0] counterAddr;
reg lastSof;
wire sofPulse = ~lastSof & sof;
wire counterZ0;
wire counterZ1;
assign value = so[1];
always @(posedge clk)
begin
lastSof <= sof;
end
localparam SOFCOUNTER_STATE_COUNT = 4'd0;
localparam SOFCOUNTER_STATE_SUB = 4'd1;
localparam SOFCOUNTER_STATE_LOADACC = 4'd2;
localparam SOFCOUNTER_STATE_MULTIPLY = 4'd3;
localparam SOFCOUNTER_STATE_ADD = 4'd4;
localparam SOFCOUNTER_STATE_CLEAR = 4'd5;
localparam SOFCOUNTER_STATE_SHIFT = 4'd6;
localparam SOFCOUNTER_STATE_DISABLED = 4'd7;
localparam SOFCOUNTER_STATE_WAIT = 4'd8; // Lower 3 bits same as COUNT
localparam COUNTER_ADDR_NOP = 3'd0;
localparam COUNTER_ADDR_MULTLOAD = 3'd1;
localparam COUNTER_ADDR_MULTCOUNT = 3'd2;
localparam COUNTER_ADDR_SHIFTLOAD = 3'd3;
localparam COUNTER_ADDR_SHIFTCOUNT = 3'd4;
assign done = (state == SOFCOUNTER_STATE_SHIFT) & counterZ1;
always @(posedge clk)
begin
case (state)
SOFCOUNTER_STATE_DISABLED:
begin
if (sofPulse) state <= SOFCOUNTER_STATE_COUNT;
ready <= 1'b0;
end
SOFCOUNTER_STATE_COUNT:
if (sofPulse) state <= SOFCOUNTER_STATE_SUB;
SOFCOUNTER_STATE_SUB:
state <= SOFCOUNTER_STATE_LOADACC;
SOFCOUNTER_STATE_LOADACC:
state <= SOFCOUNTER_STATE_MULTIPLY;
SOFCOUNTER_STATE_MULTIPLY:
if (counterZ0) state <= SOFCOUNTER_STATE_ADD;
SOFCOUNTER_STATE_ADD:
begin
state <= SOFCOUNTER_STATE_CLEAR;
ready <= 1'b1;
end
SOFCOUNTER_STATE_CLEAR:
if (start) state <= SOFCOUNTER_STATE_SHIFT;
else state <= SOFCOUNTER_STATE_WAIT;
SOFCOUNTER_STATE_WAIT:
if (start) state <= SOFCOUNTER_STATE_SHIFT;
SOFCOUNTER_STATE_SHIFT:
begin
if (counterZ1)
begin
state <= SOFCOUNTER_STATE_COUNT;
end
ready <= 1'b0;
end
default:
state <= SOFCOUNTER_STATE_DISABLED;
endcase
end
always @(state)
begin
case (state)
SOFCOUNTER_STATE_LOADACC:
counterAddr = COUNTER_ADDR_MULTLOAD;
SOFCOUNTER_STATE_MULTIPLY:
counterAddr = COUNTER_ADDR_MULTCOUNT;
SOFCOUNTER_STATE_CLEAR:
counterAddr = COUNTER_ADDR_SHIFTLOAD;
SOFCOUNTER_STATE_SHIFT:
counterAddr = COUNTER_ADDR_SHIFTCOUNT;
default:
counterAddr = COUNTER_ADDR_NOP;
endcase
end
// 16-Bit Datapath
cy_psoc3_dp16 #(.cy_dpconfig_a(
{
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Count */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:LoadAcc */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Multiply */
`CS_ALU_OP__ADD, `CS_SRCA_A1, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Add */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment:Clear */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment:Shift */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment:Disabled */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_b(
{
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Count */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:LoadAcc */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Multiply */
`CS_ALU_OP__ADD, `CS_SRCA_A1, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Add */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment:Clear */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment:Shift */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment:Disabled */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_CHNED,
`SC_CMP0_CHNED, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) SofCounter(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(addr),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output [01:00] */ .ce0(),
/* output [01:00] */ .cl0(),
/* output [01:00] */ .z0(),
/* output [01:00] */ .ff0(),
/* output [01:00] */ .ce1(),
/* output [01:00] */ .cl1(),
/* output [01:00] */ .z1(),
/* output [01:00] */ .ff1(),
/* output [01:00] */ .ov_msb(),
/* output [01:00] */ .co_msb(),
/* output [01:00] */ .cmsb(),
/* output [01:00] */ .so(so),
/* output [01:00] */ .f0_bus_stat(),
/* output [01:00] */ .f0_blk_stat(),
/* output [01:00] */ .f1_bus_stat(),
/* output [01:00] */ .f1_blk_stat()
);
// 8-Bit Datapath
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:NOP */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:MULTLOAD */
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:MULTCOUNT */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC___D1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:SHIFTLOAD */
`CS_ALU_OP__DEC, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:SHIFTCOUNT */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) Counter(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(counterAddr),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(counterZ0),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(counterZ1),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
endmodule |
module Shaper1stOrder (
delta,
transfer,
clk,
done,
ready,
start,
value
);
output delta;
output transfer;
input clk;
input done;
input ready;
input start;
input value;
reg transfer;
reg [2:0] state;
reg delta;
wire [1:0] cl0;
localparam SHAPER1STORDER_STATE_WAIT = 3'd0;
localparam SHAPER1STORDER_STATE_ACCUM = 3'd1;
localparam SHAPER1STORDER_STATE_SUB = 3'd2;
localparam SHAPER1STORDER_STATE_CHECK = 3'd3;
localparam SHAPER1STORDER_STATE_SHIFT = 3'd4;
always @(posedge clk)
begin
transfer <= 1'b0;
case (state)
SHAPER1STORDER_STATE_WAIT:
if (start) state <= SHAPER1STORDER_STATE_ACCUM;
SHAPER1STORDER_STATE_ACCUM:
if (cl0[1])
begin
state <= SHAPER1STORDER_STATE_CHECK;
delta <= 1'b0;
end
else
begin
state <= SHAPER1STORDER_STATE_SUB;
delta <= 1'b1;
end
SHAPER1STORDER_STATE_SUB:
state <= SHAPER1STORDER_STATE_CHECK;
SHAPER1STORDER_STATE_CHECK:
if (ready)
begin
state <= SHAPER1STORDER_STATE_SHIFT;
transfer <= 1'b1;
end
else
begin
state <= SHAPER1STORDER_STATE_WAIT;
end
SHAPER1STORDER_STATE_SHIFT:
if (done)
begin
state <= SHAPER1STORDER_STATE_WAIT;
end
default:
state <= SHAPER1STORDER_STATE_WAIT;
endcase
end
// 16-Bit Datapath
cy_psoc3_dp16 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Wait */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Accum */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Check */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Shift */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_ROUTE,
`SC_SI_A_ROUTE, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_b(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Wait */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Accum */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Check */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Shift */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
`SC_FB_NOCHN, `SC_CMP1_CHNED,
`SC_CMP0_CHNED, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) Div(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(value),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output [01:00] */ .ce0(),
/* output [01:00] */ .cl0(cl0),
/* output [01:00] */ .z0(),
/* output [01:00] */ .ff0(),
/* output [01:00] */ .ce1(),
/* output [01:00] */ .cl1(),
/* output [01:00] */ .z1(),
/* output [01:00] */ .ff1(),
/* output [01:00] */ .ov_msb(),
/* output [01:00] */ .co_msb(),
/* output [01:00] */ .cmsb(),
/* output [01:00] */ .so(),
/* output [01:00] */ .f0_bus_stat(),
/* output [01:00] */ .f0_blk_stat(),
/* output [01:00] */ .f1_bus_stat(),
/* output [01:00] */ .f1_blk_stat()
);
endmodule |
module DivNorNPlus1 (
clkout,
start,
clk,
delta
);
output clkout;
output start;
input clk;
input delta;
wire ce0;
wire ce1;
reg deltaReg;
reg [1:0] state;
reg clkout;
localparam DIVNORNPLUS1_STATE_CLEAR = 2'd0;
localparam DIVNORNPLUS1_STATE_EXTEND = 2'd1;
localparam DIVNORNPLUS1_STATE_INC0 = 2'd2;
localparam DIVNORNPLUS1_STATE_INC1 = 2'd3;
assign start = ce1;
// assign clkout = (state != DIVNORNPLUS1_STATE_INC1);
always @(posedge clk)
begin
clkout <= ~(state != DIVNORNPLUS1_STATE_INC1);
end
always @(posedge clk)
begin
case (state)
DIVNORNPLUS1_STATE_CLEAR:
if (deltaReg) state <= DIVNORNPLUS1_STATE_EXTEND;
else state <= DIVNORNPLUS1_STATE_INC0;
DIVNORNPLUS1_STATE_EXTEND:
state <= DIVNORNPLUS1_STATE_INC0;
DIVNORNPLUS1_STATE_INC0:
if (ce0) state <= DIVNORNPLUS1_STATE_INC1;
DIVNORNPLUS1_STATE_INC1:
if (ce1)
begin
state <= DIVNORNPLUS1_STATE_CLEAR;
deltaReg <= delta;
end
default:
state <= DIVNORNPLUS1_STATE_CLEAR;
endcase
end
// 8-Bit Datapath
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Clear */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Extend */
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:Inc0 */
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Inc1 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A0_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) Div(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr({1'b0, state}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(ce0),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(ce1),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
endmodule |
module sky130_fd_sc_hs__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
endmodule |
module system_util_vector_logic_0_0(Op1, Op2, Res)
/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
endmodule |
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule |
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we[0]),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule |
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule |
module roi(input clk, input [255:0] din, output [255:0] dout);
clb_NCY0_MX # (.LOC("SLICE_X20Y100"), .BEL("A6LUT"), .N(0))
am (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y101"), .BEL("A6LUT"), .N(0))
a5 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y102"), .BEL("B6LUT"), .N(1))
bm (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y103"), .BEL("B6LUT"), .N(1))
b5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y104"), .BEL("C6LUT"), .N(2))
cm (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[32 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y105"), .BEL("C6LUT"), .N(2))
c5 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[40 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y106"), .BEL("D6LUT"), .N(3))
dm (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[48 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y107"), .BEL("D6LUT"), .N(3))
d5 (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[56 +: 8]));
endmodule |
module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
always @(*) begin
s = din[7:4];
s[N] = o6;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
endmodule |
module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
reg [3:0] di;
always @(*) begin
s = din[7:4];
s[N] = o6;
di = {din[3:0]};
di[N] = o5;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
endmodule |
module sky130_fd_sc_hd__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule |
module test_wb_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i);
$to_myhdl(wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o);
// dump file
$dumpfile("test_wb_reg.lxt");
$dumpvars(0, test_wb_reg);
end
wb_reg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule |
module staff(
input [7:0]scan_code1,
output [15:0]sound1,
output sound_off1
);
//////SoundOff Key///////
assign sound_off1=(scan_code1==8'hf0)?0:1;
/////////Channel-1 Trigger////////
wire L_5_tr=(scan_code1==8'h1c)?1:0;//-5
wire L_6_tr=(scan_code1==8'h1b)?1:0;//-6
wire L_7_tr=(scan_code1==8'h23)?1:0;//-7
wire M_1_tr=(scan_code1==8'h2b)?1:0;//1
wire M_2_tr=(scan_code1==8'h34)?1:0;//2
wire M_3_tr=(scan_code1==8'h33)?1:0;//3
wire M_4_tr=(scan_code1==8'h3b)?1:0;//4
wire M_5_tr=(scan_code1==8'h42)?1:0;//5
wire M_6_tr=(scan_code1==8'h4b)?1:0;//6
wire M_7_tr=(scan_code1==8'h4c)?1:0;//7
wire H_1_tr=(scan_code1==8'h52)?1:0;//+1
wire H_2_tr=0;//+2
wire H_3_tr=0;//+3
wire H_4_tr=0;//+4
wire H_5_tr=0;//+5
wire Hu4_tr=0;//((!get_gate) && (scan_code==8'h15))?1:0;//+#4
wire Hu2_tr=0;//((!get_gate) && (scan_code==8'h1d))?1:0;//+#2
wire Hu1_tr=(scan_code1==8'h5b)?1:0;//+#1
wire Mu6_tr=(scan_code1==8'h4d)?1:0;//#6
wire Mu5_tr=(scan_code1==8'h44)?1:0;//#5
wire Mu4_tr=(scan_code1==8'h43)?1:0;//#4
wire Mu2_tr=(scan_code1==8'h35)?1:0;//#2
wire Mu1_tr=(scan_code1==8'h2c)?1:0;//#1
wire Lu6_tr=(scan_code1==8'h24)?1:0;//-#6
wire Lu5_tr=(scan_code1==8'h1d)?1:0;//-#5
wire Lu4_tr=(scan_code1==8'h15)?1:0;//-#4
assign sound1=( //channel-1 frequency
(Lu4_tr)?400 :(
(L_5_tr)?423 :(
(Lu5_tr)?448 :(
(L_6_tr)?475 :(
(Lu6_tr)?503 :(
(L_7_tr)?533 :(
(M_1_tr)?565 :(
(Mu1_tr)?599 :(
(M_2_tr)?634 :(
(Mu2_tr)?672 :(
(M_3_tr)?712 :(
(M_4_tr)?755 :(
(Mu4_tr)?800 :(
(M_5_tr)?847 :(
(Mu5_tr)?897 :(
(M_6_tr)?951 :(
(Mu6_tr)?1007 :(
(M_7_tr)?1067 :(
(H_1_tr)?1131 :(
(Hu1_tr)?1198 :1
)))))))))))))))))))
);
endmodule |
module RAMB16_RIGEL(
WEA,
ENA,
SSRA,
CLKA,
ADDRA,
DIPA,
DIA,
DOA,
DIB,
DOB,
WEB,
ENB,
SSRB,
CLKB,
ADDRB,
DIPB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
parameter BITS=1;
input WEA;
input ENA;
input SSRA;
input CLKA;
input [13-$clog2(BITS):0] ADDRA;
input [((BITS<8?8:BITS)/8)-1:0] DIPA;
input [BITS-1:0] DIA;
output [BITS-1:0] DOA;
input [BITS-1:0] DIB;
output [BITS-1:0] DOB;
input WEB;
input ENB;
input SSRB;
input CLKB;
input [13-$clog2(BITS):0] ADDRB;
input [((BITS<8?8:BITS)/8)-1:0] DIPB;
reg [BITS-1:0] ram [(2048*8)/BITS-1:0];
reg [BITS-1:0] bufferA;
reg [BITS-1:0] bufferB;
reg [16383:0] initpacked = {INIT_3F,INIT_3E,INIT_3D,INIT_3C,INIT_3B,INIT_3A,INIT_39,INIT_38,INIT_37,INIT_36,INIT_35,INIT_34,INIT_33,INIT_32,INIT_31,INIT_30,INIT_2F,INIT_2E,INIT_2D,INIT_2C,INIT_2B,INIT_2A,INIT_29,INIT_28,INIT_27,INIT_26,INIT_25,INIT_24,INIT_23,INIT_22,INIT_21,INIT_20,INIT_1F,INIT_1E,INIT_1D,INIT_1C,INIT_1B,INIT_1A,INIT_19,INIT_18,INIT_17,INIT_16,INIT_15,INIT_14,INIT_13,INIT_12,INIT_11,INIT_10,INIT_0F,INIT_0E,INIT_0D,INIT_0C,INIT_0B,INIT_0A,INIT_09,INIT_08,INIT_07,INIT_06,INIT_05,INIT_04,INIT_03,INIT_02,INIT_01,INIT_00};
reg [31:0] i=0;
reg [31:0] j=0;
initial begin
for(i=0; i<(2048*8)/BITS-1; i=i+1) begin
for(j=0; j<BITS; j=j+1) begin
ram[i][j] = initpacked[i*BITS+j];
end
end
end
assign DOA = bufferA;
assign DOB = bufferB;
// assign DOPA = 4'b0;
// assign DOPB = 4'b0;
always @(posedge CLKA or posedge CLKB) begin
if( CLKA && CLKB && ENA && ENB && WEA && WEB ) begin
if(ADDRA==ADDRB) begin
$display("ERROR: write to some address on both ports");
end else begin
// different address: OK
bufferA <= ram[ADDRA];
bufferB <= ram[ADDRB];
ram[ADDRA] <= DIA;
ram[ADDRB] <= DIB;
end
end else begin
// not writing on both ports: can treat A/B differently
if (CLKA && ENA) begin
if (WEA) begin
ram[ADDRA] <= DIA;
bufferA <= ram[ADDRA];
end else begin
bufferA <= ram[ADDRA];
end
end
if (CLKB && ENB) begin
if (WEB) begin
ram[ADDRB] <= DIB;
bufferB <= ram[ADDRB];
end else begin
bufferB <= ram[ADDRB];
end
end
end
end
endmodule |
module riscv_alu
(
// Inputs
input [ 3:0] alu_op_i
,input [ 31:0] alu_a_i
,input [ 31:0] alu_b_i
// Outputs
,output [ 31:0] alu_p_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0] result_r;
reg [31:16] shift_right_fill_r;
reg [31:0] shift_right_1_r;
reg [31:0] shift_right_2_r;
reg [31:0] shift_right_4_r;
reg [31:0] shift_right_8_r;
reg [31:0] shift_left_1_r;
reg [31:0] shift_left_2_r;
reg [31:0] shift_left_4_r;
reg [31:0] shift_left_8_r;
wire [31:0] sub_res_w = alu_a_i - alu_b_i;
//-----------------------------------------------------------------
// ALU
//-----------------------------------------------------------------
always @ (alu_op_i or alu_a_i or alu_b_i or sub_res_w)
begin
shift_right_fill_r = 16'b0;
shift_right_1_r = 32'b0;
shift_right_2_r = 32'b0;
shift_right_4_r = 32'b0;
shift_right_8_r = 32'b0;
shift_left_1_r = 32'b0;
shift_left_2_r = 32'b0;
shift_left_4_r = 32'b0;
shift_left_8_r = 32'b0;
case (alu_op_i)
//----------------------------------------------
// Shift Left
//----------------------------------------------
`ALU_SHIFTL :
begin
if (alu_b_i[0] == 1'b1)
shift_left_1_r = {alu_a_i[30:0],1'b0};
else
shift_left_1_r = alu_a_i;
if (alu_b_i[1] == 1'b1)
shift_left_2_r = {shift_left_1_r[29:0],2'b00};
else
shift_left_2_r = shift_left_1_r;
if (alu_b_i[2] == 1'b1)
shift_left_4_r = {shift_left_2_r[27:0],4'b0000};
else
shift_left_4_r = shift_left_2_r;
if (alu_b_i[3] == 1'b1)
shift_left_8_r = {shift_left_4_r[23:0],8'b00000000};
else
shift_left_8_r = shift_left_4_r;
if (alu_b_i[4] == 1'b1)
result_r = {shift_left_8_r[15:0],16'b0000000000000000};
else
result_r = shift_left_8_r;
end
//----------------------------------------------
// Shift Right
//----------------------------------------------
`ALU_SHIFTR, `ALU_SHIFTR_ARITH:
begin
// Arithmetic shift? Fill with 1's if MSB set
if (alu_a_i[31] == 1'b1 && alu_op_i == `ALU_SHIFTR_ARITH)
shift_right_fill_r = 16'b1111111111111111;
else
shift_right_fill_r = 16'b0000000000000000;
if (alu_b_i[0] == 1'b1)
shift_right_1_r = {shift_right_fill_r[31], alu_a_i[31:1]};
else
shift_right_1_r = alu_a_i;
if (alu_b_i[1] == 1'b1)
shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]};
else
shift_right_2_r = shift_right_1_r;
if (alu_b_i[2] == 1'b1)
shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]};
else
shift_right_4_r = shift_right_2_r;
if (alu_b_i[3] == 1'b1)
shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]};
else
shift_right_8_r = shift_right_4_r;
if (alu_b_i[4] == 1'b1)
result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]};
else
result_r = shift_right_8_r;
end
//----------------------------------------------
// Arithmetic
//----------------------------------------------
`ALU_ADD :
begin
result_r = (alu_a_i + alu_b_i);
end
`ALU_SUB :
begin
result_r = sub_res_w;
end
//----------------------------------------------
// Logical
//----------------------------------------------
`ALU_AND :
begin
result_r = (alu_a_i & alu_b_i);
end
`ALU_OR :
begin
result_r = (alu_a_i | alu_b_i);
end
`ALU_XOR :
begin
result_r = (alu_a_i ^ alu_b_i);
end
//----------------------------------------------
// Comparision
//----------------------------------------------
`ALU_LESS_THAN :
begin
result_r = (alu_a_i < alu_b_i) ? 32'h1 : 32'h0;
end
`ALU_LESS_THAN_SIGNED :
begin
if (alu_a_i[31] != alu_b_i[31])
result_r = alu_a_i[31] ? 32'h1 : 32'h0;
else
result_r = sub_res_w[31] ? 32'h1 : 32'h0;
end
default :
begin
result_r = alu_a_i;
end
endcase
end
assign alu_p_o = result_r;
endmodule |
module seqPortAlloc(
numFlit_in,
availPortVector_in,
ppv,
allocatedPortVector,
availPortVector_out,
numFlit_out
);
input [`PC_INDEX_WIDTH-1:0] numFlit_in;
input [`NUM_PORT-2:0] availPortVector_in, ppv;
output [`NUM_PORT-2:0] allocatedPortVector, availPortVector_out;
output [`PC_INDEX_WIDTH-1:0] numFlit_out;
wire [`PC_INDEX_WIDTH-1:0] numFlit [`NUM_PORT-1:0];
wire [`NUM_PORT-2:0] allocatedPortVector_st1, availPortVector_out_st1;
wire [`NUM_PORT-2:0] allocatedPortVector_st2, availPortVector_out_st2;
assign numFlit[0] = numFlit_in;
genvar i;
generate
// Stage 1: allocate the productive port
for (i=0; i<`NUM_PORT-1; i=i+1) begin : productiveAlloc
assign allocatedPortVector_st1[i] = ppv[i] && availPortVector_in[i] && (numFlit[i] <= `NUM_PORT-1);
assign numFlit[i+1] = numFlit[i] + allocatedPortVector_st1[i];
assign availPortVector_out_st1[i] = availPortVector_in[i] && ~allocatedPortVector_st1[i];
end
endgenerate
// Stage 2: deflection: find the first available port in the order of N, E, S, W
assign allocatedPortVector_st2[0] = availPortVector_out_st1[0];
assign allocatedPortVector_st2[1] = availPortVector_out_st1[1] && ~availPortVector_out_st1[0];
assign allocatedPortVector_st2[2] = availPortVector_out_st1[2] && ~availPortVector_out_st1[1] && ~availPortVector_out_st1[0];
assign allocatedPortVector_st2[3] = availPortVector_out_st1[3] && ~availPortVector_out_st1[2] && ~availPortVector_out_st1[1] && ~availPortVector_out_st1[0];
assign availPortVector_out_st2 [0] = 1'b0;
assign availPortVector_out_st2 [1] = availPortVector_out_st1[0] && availPortVector_out_st1[1];
assign availPortVector_out_st2 [2] = |availPortVector_out_st1[1:0] && availPortVector_out_st1[2];
assign availPortVector_out_st2 [3] = |availPortVector_out_st1[2:0] && availPortVector_out_st1[3];
wire get_port_st1;
assign get_port_st1 = |allocatedPortVector_st1;
assign allocatedPortVector = (~|ppv || get_port_st1) ? allocatedPortVector_st1 : allocatedPortVector_st2;
assign availPortVector_out = (~|ppv || get_port_st1) ? availPortVector_out_st1 : availPortVector_out_st2;
assign numFlit_out = (~|ppv || get_port_st1) ? numFlit[`NUM_PORT-1] : numFlit[`NUM_PORT-1] + 1'b1;
endmodule |
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