module_content
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module sky130_fd_sc_ls__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_hd__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule |
module system_stub
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
processing_system7_0_M_AXI_GP1_ARESETN_pin,
processing_system7_0_S_AXI_HP1_ARESETN_pin,
processing_system7_0_FCLK_CLK3_pin,
processing_system7_0_FCLK_CLK0_pin,
processing_system7_0_M_AXI_GP1_ARVALID_pin,
processing_system7_0_M_AXI_GP1_AWVALID_pin,
processing_system7_0_M_AXI_GP1_BREADY_pin,
processing_system7_0_M_AXI_GP1_RREADY_pin,
processing_system7_0_M_AXI_GP1_WLAST_pin,
processing_system7_0_M_AXI_GP1_WVALID_pin,
processing_system7_0_M_AXI_GP1_ARID_pin,
processing_system7_0_M_AXI_GP1_AWID_pin,
processing_system7_0_M_AXI_GP1_WID_pin,
processing_system7_0_M_AXI_GP1_ARBURST_pin,
processing_system7_0_M_AXI_GP1_ARLOCK_pin,
processing_system7_0_M_AXI_GP1_ARSIZE_pin,
processing_system7_0_M_AXI_GP1_AWBURST_pin,
processing_system7_0_M_AXI_GP1_AWLOCK_pin,
processing_system7_0_M_AXI_GP1_AWSIZE_pin,
processing_system7_0_M_AXI_GP1_ARPROT_pin,
processing_system7_0_M_AXI_GP1_AWPROT_pin,
processing_system7_0_M_AXI_GP1_ARADDR_pin,
processing_system7_0_M_AXI_GP1_AWADDR_pin,
processing_system7_0_M_AXI_GP1_WDATA_pin,
processing_system7_0_M_AXI_GP1_ARCACHE_pin,
processing_system7_0_M_AXI_GP1_ARLEN_pin,
processing_system7_0_M_AXI_GP1_ARQOS_pin,
processing_system7_0_M_AXI_GP1_AWCACHE_pin,
processing_system7_0_M_AXI_GP1_AWLEN_pin,
processing_system7_0_M_AXI_GP1_AWQOS_pin,
processing_system7_0_M_AXI_GP1_WSTRB_pin,
processing_system7_0_M_AXI_GP1_ACLK_pin,
processing_system7_0_M_AXI_GP1_ARREADY_pin,
processing_system7_0_M_AXI_GP1_AWREADY_pin,
processing_system7_0_M_AXI_GP1_BVALID_pin,
processing_system7_0_M_AXI_GP1_RLAST_pin,
processing_system7_0_M_AXI_GP1_RVALID_pin,
processing_system7_0_M_AXI_GP1_WREADY_pin,
processing_system7_0_M_AXI_GP1_BID_pin,
processing_system7_0_M_AXI_GP1_RID_pin,
processing_system7_0_M_AXI_GP1_BRESP_pin,
processing_system7_0_M_AXI_GP1_RRESP_pin,
processing_system7_0_M_AXI_GP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ARREADY_pin,
processing_system7_0_S_AXI_HP1_AWREADY_pin,
processing_system7_0_S_AXI_HP1_BVALID_pin,
processing_system7_0_S_AXI_HP1_RLAST_pin,
processing_system7_0_S_AXI_HP1_RVALID_pin,
processing_system7_0_S_AXI_HP1_WREADY_pin,
processing_system7_0_S_AXI_HP1_BRESP_pin,
processing_system7_0_S_AXI_HP1_RRESP_pin,
processing_system7_0_S_AXI_HP1_BID_pin,
processing_system7_0_S_AXI_HP1_RID_pin,
processing_system7_0_S_AXI_HP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ACLK_pin,
processing_system7_0_S_AXI_HP1_ARVALID_pin,
processing_system7_0_S_AXI_HP1_AWVALID_pin,
processing_system7_0_S_AXI_HP1_BREADY_pin,
processing_system7_0_S_AXI_HP1_RREADY_pin,
processing_system7_0_S_AXI_HP1_WLAST_pin,
processing_system7_0_S_AXI_HP1_WVALID_pin,
processing_system7_0_S_AXI_HP1_ARBURST_pin,
processing_system7_0_S_AXI_HP1_ARLOCK_pin,
processing_system7_0_S_AXI_HP1_ARSIZE_pin,
processing_system7_0_S_AXI_HP1_AWBURST_pin,
processing_system7_0_S_AXI_HP1_AWLOCK_pin,
processing_system7_0_S_AXI_HP1_AWSIZE_pin,
processing_system7_0_S_AXI_HP1_ARPROT_pin,
processing_system7_0_S_AXI_HP1_AWPROT_pin,
processing_system7_0_S_AXI_HP1_ARADDR_pin,
processing_system7_0_S_AXI_HP1_AWADDR_pin,
processing_system7_0_S_AXI_HP1_ARCACHE_pin,
processing_system7_0_S_AXI_HP1_ARLEN_pin,
processing_system7_0_S_AXI_HP1_ARQOS_pin,
processing_system7_0_S_AXI_HP1_AWCACHE_pin,
processing_system7_0_S_AXI_HP1_AWLEN_pin,
processing_system7_0_S_AXI_HP1_AWQOS_pin,
processing_system7_0_S_AXI_HP1_ARID_pin,
processing_system7_0_S_AXI_HP1_AWID_pin,
processing_system7_0_S_AXI_HP1_WID_pin,
processing_system7_0_S_AXI_HP1_WDATA_pin,
processing_system7_0_S_AXI_HP1_WSTRB_pin,
processing_system7_0_I2C0_SDA_I_pin,
processing_system7_0_I2C0_SDA_O_pin,
processing_system7_0_I2C0_SDA_T_pin,
processing_system7_0_I2C0_SCL_I_pin,
processing_system7_0_I2C0_SCL_O_pin,
processing_system7_0_I2C0_SCL_T_pin,
processing_system7_0_GPIO_I_pin,
processing_system7_0_GPIO_O_pin,
processing_system7_0_GPIO_T_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB_pin;
input processing_system7_0_PS_CLK_pin;
input processing_system7_0_PS_PORB_pin;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB_pin;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output processing_system7_0_M_AXI_GP1_ARESETN_pin;
output processing_system7_0_S_AXI_HP1_ARESETN_pin;
output processing_system7_0_FCLK_CLK3_pin;
output processing_system7_0_FCLK_CLK0_pin;
output processing_system7_0_M_AXI_GP1_ARVALID_pin;
output processing_system7_0_M_AXI_GP1_AWVALID_pin;
output processing_system7_0_M_AXI_GP1_BREADY_pin;
output processing_system7_0_M_AXI_GP1_RREADY_pin;
output processing_system7_0_M_AXI_GP1_WLAST_pin;
output processing_system7_0_M_AXI_GP1_WVALID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_ARID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_AWID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_WID_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARSIZE_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWSIZE_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARPROT_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWPROT_pin;
output [31:0] processing_system7_0_M_AXI_GP1_ARADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_AWADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_WDATA_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_WSTRB_pin;
input processing_system7_0_M_AXI_GP1_ACLK_pin;
input processing_system7_0_M_AXI_GP1_ARREADY_pin;
input processing_system7_0_M_AXI_GP1_AWREADY_pin;
input processing_system7_0_M_AXI_GP1_BVALID_pin;
input processing_system7_0_M_AXI_GP1_RLAST_pin;
input processing_system7_0_M_AXI_GP1_RVALID_pin;
input processing_system7_0_M_AXI_GP1_WREADY_pin;
input [11:0] processing_system7_0_M_AXI_GP1_BID_pin;
input [11:0] processing_system7_0_M_AXI_GP1_RID_pin;
input [1:0] processing_system7_0_M_AXI_GP1_BRESP_pin;
input [1:0] processing_system7_0_M_AXI_GP1_RRESP_pin;
input [31:0] processing_system7_0_M_AXI_GP1_RDATA_pin;
output processing_system7_0_S_AXI_HP1_ARREADY_pin;
output processing_system7_0_S_AXI_HP1_AWREADY_pin;
output processing_system7_0_S_AXI_HP1_BVALID_pin;
output processing_system7_0_S_AXI_HP1_RLAST_pin;
output processing_system7_0_S_AXI_HP1_RVALID_pin;
output processing_system7_0_S_AXI_HP1_WREADY_pin;
output [1:0] processing_system7_0_S_AXI_HP1_BRESP_pin;
output [1:0] processing_system7_0_S_AXI_HP1_RRESP_pin;
output [5:0] processing_system7_0_S_AXI_HP1_BID_pin;
output [5:0] processing_system7_0_S_AXI_HP1_RID_pin;
output [63:0] processing_system7_0_S_AXI_HP1_RDATA_pin;
input processing_system7_0_S_AXI_HP1_ACLK_pin;
input processing_system7_0_S_AXI_HP1_ARVALID_pin;
input processing_system7_0_S_AXI_HP1_AWVALID_pin;
input processing_system7_0_S_AXI_HP1_BREADY_pin;
input processing_system7_0_S_AXI_HP1_RREADY_pin;
input processing_system7_0_S_AXI_HP1_WLAST_pin;
input processing_system7_0_S_AXI_HP1_WVALID_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARSIZE_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWSIZE_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARPROT_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWPROT_pin;
input [31:0] processing_system7_0_S_AXI_HP1_ARADDR_pin;
input [31:0] processing_system7_0_S_AXI_HP1_AWADDR_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARQOS_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWQOS_pin;
input [5:0] processing_system7_0_S_AXI_HP1_ARID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_AWID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_WID_pin;
input [63:0] processing_system7_0_S_AXI_HP1_WDATA_pin;
input [7:0] processing_system7_0_S_AXI_HP1_WSTRB_pin;
input processing_system7_0_I2C0_SDA_I_pin;
output processing_system7_0_I2C0_SDA_O_pin;
output processing_system7_0_I2C0_SDA_T_pin;
input processing_system7_0_I2C0_SCL_I_pin;
output processing_system7_0_I2C0_SCL_O_pin;
output processing_system7_0_I2C0_SCL_T_pin;
input [47:0] processing_system7_0_GPIO_I_pin;
output [47:0] processing_system7_0_GPIO_O_pin;
output [47:0] processing_system7_0_GPIO_T_pin;
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB_pin ( processing_system7_0_PS_SRSTB_pin ),
.processing_system7_0_PS_CLK_pin ( processing_system7_0_PS_CLK_pin ),
.processing_system7_0_PS_PORB_pin ( processing_system7_0_PS_PORB_pin ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
.processing_system7_0_M_AXI_GP1_ARESETN_pin ( processing_system7_0_M_AXI_GP1_ARESETN_pin ),
.processing_system7_0_S_AXI_HP1_ARESETN_pin ( processing_system7_0_S_AXI_HP1_ARESETN_pin ),
.processing_system7_0_FCLK_CLK3_pin ( processing_system7_0_FCLK_CLK3_pin ),
.processing_system7_0_FCLK_CLK0_pin ( processing_system7_0_FCLK_CLK0_pin ),
.processing_system7_0_M_AXI_GP1_ARVALID_pin ( processing_system7_0_M_AXI_GP1_ARVALID_pin ),
.processing_system7_0_M_AXI_GP1_AWVALID_pin ( processing_system7_0_M_AXI_GP1_AWVALID_pin ),
.processing_system7_0_M_AXI_GP1_BREADY_pin ( processing_system7_0_M_AXI_GP1_BREADY_pin ),
.processing_system7_0_M_AXI_GP1_RREADY_pin ( processing_system7_0_M_AXI_GP1_RREADY_pin ),
.processing_system7_0_M_AXI_GP1_WLAST_pin ( processing_system7_0_M_AXI_GP1_WLAST_pin ),
.processing_system7_0_M_AXI_GP1_WVALID_pin ( processing_system7_0_M_AXI_GP1_WVALID_pin ),
.processing_system7_0_M_AXI_GP1_ARID_pin ( processing_system7_0_M_AXI_GP1_ARID_pin ),
.processing_system7_0_M_AXI_GP1_AWID_pin ( processing_system7_0_M_AXI_GP1_AWID_pin ),
.processing_system7_0_M_AXI_GP1_WID_pin ( processing_system7_0_M_AXI_GP1_WID_pin ),
.processing_system7_0_M_AXI_GP1_ARBURST_pin ( processing_system7_0_M_AXI_GP1_ARBURST_pin ),
.processing_system7_0_M_AXI_GP1_ARLOCK_pin ( processing_system7_0_M_AXI_GP1_ARLOCK_pin ),
.processing_system7_0_M_AXI_GP1_ARSIZE_pin ( processing_system7_0_M_AXI_GP1_ARSIZE_pin ),
.processing_system7_0_M_AXI_GP1_AWBURST_pin ( processing_system7_0_M_AXI_GP1_AWBURST_pin ),
.processing_system7_0_M_AXI_GP1_AWLOCK_pin ( processing_system7_0_M_AXI_GP1_AWLOCK_pin ),
.processing_system7_0_M_AXI_GP1_AWSIZE_pin ( processing_system7_0_M_AXI_GP1_AWSIZE_pin ),
.processing_system7_0_M_AXI_GP1_ARPROT_pin ( processing_system7_0_M_AXI_GP1_ARPROT_pin ),
.processing_system7_0_M_AXI_GP1_AWPROT_pin ( processing_system7_0_M_AXI_GP1_AWPROT_pin ),
.processing_system7_0_M_AXI_GP1_ARADDR_pin ( processing_system7_0_M_AXI_GP1_ARADDR_pin ),
.processing_system7_0_M_AXI_GP1_AWADDR_pin ( processing_system7_0_M_AXI_GP1_AWADDR_pin ),
.processing_system7_0_M_AXI_GP1_WDATA_pin ( processing_system7_0_M_AXI_GP1_WDATA_pin ),
.processing_system7_0_M_AXI_GP1_ARCACHE_pin ( processing_system7_0_M_AXI_GP1_ARCACHE_pin ),
.processing_system7_0_M_AXI_GP1_ARLEN_pin ( processing_system7_0_M_AXI_GP1_ARLEN_pin ),
.processing_system7_0_M_AXI_GP1_ARQOS_pin ( processing_system7_0_M_AXI_GP1_ARQOS_pin ),
.processing_system7_0_M_AXI_GP1_AWCACHE_pin ( processing_system7_0_M_AXI_GP1_AWCACHE_pin ),
.processing_system7_0_M_AXI_GP1_AWLEN_pin ( processing_system7_0_M_AXI_GP1_AWLEN_pin ),
.processing_system7_0_M_AXI_GP1_AWQOS_pin ( processing_system7_0_M_AXI_GP1_AWQOS_pin ),
.processing_system7_0_M_AXI_GP1_WSTRB_pin ( processing_system7_0_M_AXI_GP1_WSTRB_pin ),
.processing_system7_0_M_AXI_GP1_ACLK_pin ( processing_system7_0_M_AXI_GP1_ACLK_pin ),
.processing_system7_0_M_AXI_GP1_ARREADY_pin ( processing_system7_0_M_AXI_GP1_ARREADY_pin ),
.processing_system7_0_M_AXI_GP1_AWREADY_pin ( processing_system7_0_M_AXI_GP1_AWREADY_pin ),
.processing_system7_0_M_AXI_GP1_BVALID_pin ( processing_system7_0_M_AXI_GP1_BVALID_pin ),
.processing_system7_0_M_AXI_GP1_RLAST_pin ( processing_system7_0_M_AXI_GP1_RLAST_pin ),
.processing_system7_0_M_AXI_GP1_RVALID_pin ( processing_system7_0_M_AXI_GP1_RVALID_pin ),
.processing_system7_0_M_AXI_GP1_WREADY_pin ( processing_system7_0_M_AXI_GP1_WREADY_pin ),
.processing_system7_0_M_AXI_GP1_BID_pin ( processing_system7_0_M_AXI_GP1_BID_pin ),
.processing_system7_0_M_AXI_GP1_RID_pin ( processing_system7_0_M_AXI_GP1_RID_pin ),
.processing_system7_0_M_AXI_GP1_BRESP_pin ( processing_system7_0_M_AXI_GP1_BRESP_pin ),
.processing_system7_0_M_AXI_GP1_RRESP_pin ( processing_system7_0_M_AXI_GP1_RRESP_pin ),
.processing_system7_0_M_AXI_GP1_RDATA_pin ( processing_system7_0_M_AXI_GP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ARREADY_pin ( processing_system7_0_S_AXI_HP1_ARREADY_pin ),
.processing_system7_0_S_AXI_HP1_AWREADY_pin ( processing_system7_0_S_AXI_HP1_AWREADY_pin ),
.processing_system7_0_S_AXI_HP1_BVALID_pin ( processing_system7_0_S_AXI_HP1_BVALID_pin ),
.processing_system7_0_S_AXI_HP1_RLAST_pin ( processing_system7_0_S_AXI_HP1_RLAST_pin ),
.processing_system7_0_S_AXI_HP1_RVALID_pin ( processing_system7_0_S_AXI_HP1_RVALID_pin ),
.processing_system7_0_S_AXI_HP1_WREADY_pin ( processing_system7_0_S_AXI_HP1_WREADY_pin ),
.processing_system7_0_S_AXI_HP1_BRESP_pin ( processing_system7_0_S_AXI_HP1_BRESP_pin ),
.processing_system7_0_S_AXI_HP1_RRESP_pin ( processing_system7_0_S_AXI_HP1_RRESP_pin ),
.processing_system7_0_S_AXI_HP1_BID_pin ( processing_system7_0_S_AXI_HP1_BID_pin ),
.processing_system7_0_S_AXI_HP1_RID_pin ( processing_system7_0_S_AXI_HP1_RID_pin ),
.processing_system7_0_S_AXI_HP1_RDATA_pin ( processing_system7_0_S_AXI_HP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ACLK_pin ( processing_system7_0_S_AXI_HP1_ACLK_pin ),
.processing_system7_0_S_AXI_HP1_ARVALID_pin ( processing_system7_0_S_AXI_HP1_ARVALID_pin ),
.processing_system7_0_S_AXI_HP1_AWVALID_pin ( processing_system7_0_S_AXI_HP1_AWVALID_pin ),
.processing_system7_0_S_AXI_HP1_BREADY_pin ( processing_system7_0_S_AXI_HP1_BREADY_pin ),
.processing_system7_0_S_AXI_HP1_RREADY_pin ( processing_system7_0_S_AXI_HP1_RREADY_pin ),
.processing_system7_0_S_AXI_HP1_WLAST_pin ( processing_system7_0_S_AXI_HP1_WLAST_pin ),
.processing_system7_0_S_AXI_HP1_WVALID_pin ( processing_system7_0_S_AXI_HP1_WVALID_pin ),
.processing_system7_0_S_AXI_HP1_ARBURST_pin ( processing_system7_0_S_AXI_HP1_ARBURST_pin ),
.processing_system7_0_S_AXI_HP1_ARLOCK_pin ( processing_system7_0_S_AXI_HP1_ARLOCK_pin ),
.processing_system7_0_S_AXI_HP1_ARSIZE_pin ( processing_system7_0_S_AXI_HP1_ARSIZE_pin ),
.processing_system7_0_S_AXI_HP1_AWBURST_pin ( processing_system7_0_S_AXI_HP1_AWBURST_pin ),
.processing_system7_0_S_AXI_HP1_AWLOCK_pin ( processing_system7_0_S_AXI_HP1_AWLOCK_pin ),
.processing_system7_0_S_AXI_HP1_AWSIZE_pin ( processing_system7_0_S_AXI_HP1_AWSIZE_pin ),
.processing_system7_0_S_AXI_HP1_ARPROT_pin ( processing_system7_0_S_AXI_HP1_ARPROT_pin ),
.processing_system7_0_S_AXI_HP1_AWPROT_pin ( processing_system7_0_S_AXI_HP1_AWPROT_pin ),
.processing_system7_0_S_AXI_HP1_ARADDR_pin ( processing_system7_0_S_AXI_HP1_ARADDR_pin ),
.processing_system7_0_S_AXI_HP1_AWADDR_pin ( processing_system7_0_S_AXI_HP1_AWADDR_pin ),
.processing_system7_0_S_AXI_HP1_ARCACHE_pin ( processing_system7_0_S_AXI_HP1_ARCACHE_pin ),
.processing_system7_0_S_AXI_HP1_ARLEN_pin ( processing_system7_0_S_AXI_HP1_ARLEN_pin ),
.processing_system7_0_S_AXI_HP1_ARQOS_pin ( processing_system7_0_S_AXI_HP1_ARQOS_pin ),
.processing_system7_0_S_AXI_HP1_AWCACHE_pin ( processing_system7_0_S_AXI_HP1_AWCACHE_pin ),
.processing_system7_0_S_AXI_HP1_AWLEN_pin ( processing_system7_0_S_AXI_HP1_AWLEN_pin ),
.processing_system7_0_S_AXI_HP1_AWQOS_pin ( processing_system7_0_S_AXI_HP1_AWQOS_pin ),
.processing_system7_0_S_AXI_HP1_ARID_pin ( processing_system7_0_S_AXI_HP1_ARID_pin ),
.processing_system7_0_S_AXI_HP1_AWID_pin ( processing_system7_0_S_AXI_HP1_AWID_pin ),
.processing_system7_0_S_AXI_HP1_WID_pin ( processing_system7_0_S_AXI_HP1_WID_pin ),
.processing_system7_0_S_AXI_HP1_WDATA_pin ( processing_system7_0_S_AXI_HP1_WDATA_pin ),
.processing_system7_0_S_AXI_HP1_WSTRB_pin ( processing_system7_0_S_AXI_HP1_WSTRB_pin ),
.processing_system7_0_I2C0_SDA_I_pin ( processing_system7_0_I2C0_SDA_I_pin ),
.processing_system7_0_I2C0_SDA_O_pin ( processing_system7_0_I2C0_SDA_O_pin ),
.processing_system7_0_I2C0_SDA_T_pin ( processing_system7_0_I2C0_SDA_T_pin ),
.processing_system7_0_I2C0_SCL_I_pin ( processing_system7_0_I2C0_SCL_I_pin ),
.processing_system7_0_I2C0_SCL_O_pin ( processing_system7_0_I2C0_SCL_O_pin ),
.processing_system7_0_I2C0_SCL_T_pin ( processing_system7_0_I2C0_SCL_T_pin ),
.processing_system7_0_GPIO_I_pin ( processing_system7_0_GPIO_I_pin ),
.processing_system7_0_GPIO_O_pin ( processing_system7_0_GPIO_O_pin ),
.processing_system7_0_GPIO_T_pin ( processing_system7_0_GPIO_T_pin )
);
endmodule |
module sky130_fd_sc_hdll__o211ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__o211ai_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule |
module karray(
input wire [5:0] idx, output reg [31:0] k
);
always @(*) begin
case (idx)
6'b000000: k = 32'h428a2f98;
6'b000001: k = 32'h71374491;
6'b000010: k = 32'hb5c0fbcf;
6'b000011: k = 32'he9b5dba5;
6'b000100: k = 32'h3956c25b;
6'b000101: k = 32'h59f111f1;
6'b000110: k = 32'h923f82a4;
6'b000111: k = 32'hab1c5ed5;
6'b001000: k = 32'hd807aa98;
6'b001001: k = 32'h12835b01;
6'b001010: k = 32'h243185be;
6'b001011: k = 32'h550c7dc3;
6'b001100: k = 32'h72be5d74;
6'b001101: k = 32'h80deb1fe;
6'b001110: k = 32'h9bdc06a7;
6'b001111: k = 32'hc19bf174;
6'b010000: k = 32'he49b69c1;
6'b010001: k = 32'hefbe4786;
6'b010010: k = 32'h0fc19dc6;
6'b010011: k = 32'h240ca1cc;
6'b010100: k = 32'h2de92c6f;
6'b010101: k = 32'h4a7484aa;
6'b010110: k = 32'h5cb0a9dc;
6'b010111: k = 32'h76f988da;
6'b011000: k = 32'h983e5152;
6'b011001: k = 32'ha831c66d;
6'b011010: k = 32'hb00327c8;
6'b011011: k = 32'hbf597fc7;
6'b011100: k = 32'hc6e00bf3;
6'b011101: k = 32'hd5a79147;
6'b011110: k = 32'h06ca6351;
6'b011111: k = 32'h14292967;
6'b100000: k = 32'h27b70a85;
6'b100001: k = 32'h2e1b2138;
6'b100010: k = 32'h4d2c6dfc;
6'b100011: k = 32'h53380d13;
6'b100100: k = 32'h650a7354;
6'b100101: k = 32'h766a0abb;
6'b100110: k = 32'h81c2c92e;
6'b100111: k = 32'h92722c85;
6'b101000: k = 32'ha2bfe8a1;
6'b101001: k = 32'ha81a664b;
6'b101010: k = 32'hc24b8b70;
6'b101011: k = 32'hc76c51a3;
6'b101100: k = 32'hd192e819;
6'b101101: k = 32'hd6990624;
6'b101110: k = 32'hf40e3585;
6'b101111: k = 32'h106aa070;
6'b110000: k = 32'h19a4c116;
6'b110001: k = 32'h1e376c08;
6'b110010: k = 32'h2748774c;
6'b110011: k = 32'h34b0bcb5;
6'b110100: k = 32'h391c0cb3;
6'b110101: k = 32'h4ed8aa4a;
6'b110110: k = 32'h5b9cca4f;
6'b110111: k = 32'h682e6ff3;
6'b111000: k = 32'h748f82ee;
6'b111001: k = 32'h78a5636f;
6'b111010: k = 32'h84c87814;
6'b111011: k = 32'h8cc70208;
6'b111100: k = 32'h90befffa;
6'b111101: k = 32'ha4506ceb;
6'b111110: k = 32'hbef9a3f7;
6'b111111: k = 32'hc67178f2;
endcase
end
endmodule |
module sha256_chunk(
input wire clk, input wire [511:0] data, input wire [255:0] V_in, output wire [255:0] hash
);
/*
design choices:
select parts of data via shifter or by muxing
use hash output as temp storage
*/
function [31:0] rotate (input [31:0] data, input [4:0] shift);
// from http://stackoverflow.com/questions/6316653/defining-a-rightrotate-function-with-non-fixed-rotation-length/6317189#6317189
reg [63:0] tmp;
begin
tmp = {data, data} >> shift;
rotate = tmp[31:0];
end
endfunction
function [31:0] flipbytes (input [31:0] data);
flipbytes = {data[7:0], data[15:8], data[23:16], data[31:24]};
endfunction
// State:
reg [255:0] V;
reg [31:0] R[7:0]; // R[0] through R[7] represent a through h
reg [31:0] w[15:0];
// round computation
// nw and nR are the computation of w and R for the next round.
reg [31:0] nw, nR[7:0], s0, s1, S1, ch, temp1, S0, maj, temp2;
wire [31:0] k;
karray karray(.idx(roundnum), .k(k));
// On round i, we calculate nw=w[i+16].
assign hash[31:0] = V[31:0] + nR[0];
assign hash[63:32] = V[63:32] + nR[1];
assign hash[95:64] = V[95:64] + nR[2];
assign hash[127:96] = V[127:96] + nR[3];
assign hash[159:128] = V[159:128] + nR[4];
assign hash[191:160] = V[191:160] + nR[5];
assign hash[223:192] = V[223:192] + nR[6];
assign hash[255:224] = V[255:224] + nR[7];
reg [5:0] roundnum = 0;
always @(*) begin
s0 = rotate(w[1], 7) ^ rotate(w[1], 18) ^ (w[1] >> 3);
s1 = rotate(w[14], 17) ^ rotate(w[14], 19) ^ (w[14] >> 10);
nw = w[0] + s0 + w[9] + s1;
S1 = rotate(R[4], 6) ^ rotate(R[4], 11) ^ rotate(R[4], 25);
ch = (R[4] & R[5]) ^ ((~R[4]) & R[6]);
temp1 = R[7] + S1 + ch + k + w[0];
S0 = rotate(R[0], 2) ^ rotate(R[0], 13) ^ rotate(R[0], 22);
maj = (R[0] & R[1]) ^ (R[0] & R[2]) ^ (R[1] & R[2]);
temp2 = S0 + maj;
nR[7] = R[6];
nR[6] = R[5];
nR[5] = R[4];
nR[4] = R[3] + temp1;
nR[3] = R[2];
nR[2] = R[1];
nR[1] = R[0];
nR[0] = temp1 + temp2;
end
always @(posedge clk) begin
if (roundnum == 6'b111111) begin
V <= V_in;
R[0] <= V_in[31:0];
R[1] <= V_in[63:32];
R[2] <= V_in[95:64];
R[3] <= V_in[127:96];
R[4] <= V_in[159:128];
R[5] <= V_in[191:160];
R[6] <= V_in[223:192];
R[7] <= V_in[255:224];
w[0] <= flipbytes(data[31:0]);
w[1] <= flipbytes(data[63:32]);
w[2] <= flipbytes(data[95:64]);
w[3] <= flipbytes(data[127:96]);
w[4] <= flipbytes(data[159:128]);
w[5] <= flipbytes(data[191:160]);
w[6] <= flipbytes(data[223:192]);
w[7] <= flipbytes(data[255:224]);
w[8] <= flipbytes(data[287:256]);
w[9] <= flipbytes(data[319:288]);
w[10] <= flipbytes(data[351:320]);
w[11] <= flipbytes(data[383:352]);
w[12] <= flipbytes(data[415:384]);
w[13] <= flipbytes(data[447:416]);
w[14] <= flipbytes(data[479:448]);
w[15] <= flipbytes(data[511:480]);
end else begin
R[0] <= nR[0];
R[1] <= nR[1];
R[2] <= nR[2];
R[3] <= nR[3];
R[4] <= nR[4];
R[5] <= nR[5];
R[6] <= nR[6];
R[7] <= nR[7];
w[0] <= w[1];
w[1] <= w[2];
w[2] <= w[3];
w[3] <= w[4];
w[4] <= w[5];
w[5] <= w[6];
w[6] <= w[7];
w[7] <= w[8];
w[8] <= w[9];
w[9] <= w[10];
w[10] <= w[11];
w[11] <= w[12];
w[12] <= w[13];
w[13] <= w[14];
w[14] <= w[15];
w[15] <= nw;
end
roundnum <= roundnum + 1'b1;
end
endmodule |
module sky130_fd_sc_lp__a2111oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__a2111oi_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule |
module ROM_programa (address, instruction, enable, rdl, clk);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "S6";
parameter integer C_RAM_SIZE_KWORDS = 1;
//
input clk;
input [11:0] address;
input enable;
output [17:0] instruction;
output rdl;
//
//
wire [15:0] address_a;
wire pipe_a11;
wire [35:0] data_in_a;
wire [35:0] data_out_a;
wire [35:0] data_out_a_l;
wire [35:0] data_out_a_h;
wire [35:0] data_out_a_ll;
wire [35:0] data_out_a_lh;
wire [35:0] data_out_a_hl;
wire [35:0] data_out_a_hh;
wire [15:0] address_b;
wire [35:0] data_in_b;
wire [35:0] data_in_b_l;
wire [35:0] data_in_b_ll;
wire [35:0] data_in_b_hl;
wire [35:0] data_out_b;
wire [35:0] data_out_b_l;
wire [35:0] data_out_b_ll;
wire [35:0] data_out_b_hl;
wire [35:0] data_in_b_h;
wire [35:0] data_in_b_lh;
wire [35:0] data_in_b_hh;
wire [35:0] data_out_b_h;
wire [35:0] data_out_b_lh;
wire [35:0] data_out_b_hh;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
wire [3:0] we_b_l;
wire [3:0] we_b_h;
//
wire [11:0] jtag_addr;
wire jtag_we;
wire jtag_clk;
wire [17:0] jtag_din;
wire [17:0] jtag_dout;
wire [17:0] jtag_dout_1;
wire [0:0] jtag_en;
//
wire [0:0] picoblaze_reset;
wire [0:0] rdl_bus;
//
parameter integer BRAM_ADDRESS_WIDTH = addr_width_calc(C_RAM_SIZE_KWORDS);
//
//
function integer addr_width_calc;
input integer size_in_k;
if (size_in_k == 1) begin addr_width_calc = 10; end
else if (size_in_k == 2) begin addr_width_calc = 11; end
else if (size_in_k == 4) begin addr_width_calc = 12; end
else begin
if (C_RAM_SIZE_KWORDS != 1 && C_RAM_SIZE_KWORDS != 2 && C_RAM_SIZE_KWORDS != 4) begin
//#0;
$display("Invalid BlockRAM size. Please set to 1, 2 or 4 K words..\n");
$finish;
end
end
endfunction
//
//
generate
if (C_RAM_SIZE_KWORDS == 1) begin : ram_1k_generate
//
if (C_FAMILY == "S6") begin: s6
//
assign address_a[13:0] = {address[9:0], 4'b0000};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {34'b0000000000000000000000000000000000, address[11:10]};
assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b = {2'b00, data_out_b[33:32], 16'b0000000000000000, data_out_b[15:0]};
assign address_b[13:0] = 14'b00000000000000;
assign we_b[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b = {2'b00, jtag_din[17:16], 16'b0000000000000000, jtag_din[15:0]};
assign address_b[13:0] = {jtag_addr[9:0], 4'b0000};
assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB16BWER #(.DATA_WIDTH_A (18),
.DOA_REG (0),
.EN_RSTRAM_A ("FALSE"),
.INIT_A (9'b000000000),
.RST_PRIORITY_A ("CE"),
.SRVAL_A (9'b000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.DATA_WIDTH_B (18),
.DOB_REG (0),
.EN_RSTRAM_B ("FALSE"),
.INIT_B (9'b000000000),
.RST_PRIORITY_B ("CE"),
.SRVAL_B (9'b000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.RSTTYPE ("SYNC"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.SIM_DEVICE ("SPARTAN6"),
.INIT_00 (256'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
.INIT_01 (256'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
.INIT_02 (256'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
.INIT_03 (256'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
.INIT_04 (256'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
.INIT_05 (256'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
.INIT_06 (256'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
.INIT_07 (256'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
.INIT_08 (256'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
.INIT_09 (256'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
.INIT_0A (256'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
.INIT_0B (256'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
.INIT_0C (256'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
.INIT_0D (256'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
.INIT_0E (256'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
.INITP_01 (256'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom( .ADDRA (address_a[13:0]),
.ENA (enable),
.CLKA (clk),
.DOA (data_out_a[31:0]),
.DOPA (data_out_a[35:32]),
.DIA (data_in_a[31:0]),
.DIPA (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEA (1'b0),
.RSTA (1'b0),
.ADDRB (address_b[13:0]),
.ENB (enable_b),
.CLKB (clk_b),
.DOB (data_out_b[31:0]),
.DOPB (data_out_b[35:32]),
.DIB (data_in_b[31:0]),
.DIPB (data_in_b[35:32]),
.WEB (we_b[3:0]),
.REGCEB (1'b0),
.RSTB (1'b0));
end // s6;
//
//
if (C_FAMILY == "V6") begin: v6
//
assign address_a[13:0] = {address[9:0], 4'b1111};
assign instruction = data_out_a[17:0];
assign data_in_a[17:0] = {16'b0000000000000000, address[11:10]};
assign jtag_dout = data_out_b[17:0];
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b[17:0] = data_out_b[17:0];
assign address_b[13:0] = 14'b11111111111111;
assign we_b[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b[17:0] = jtag_din[17:0];
assign address_b[13:0] = {jtag_addr[9:0], 4'b1111};
assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB18E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (18'b000000000000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (18'b000000000000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (18'b000000000000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (18'b000000000000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.SIM_DEVICE ("VIRTEX6"),
.INIT_00 (256'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
.INIT_01 (256'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
.INIT_02 (256'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
.INIT_03 (256'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
.INIT_04 (256'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
.INIT_05 (256'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
.INIT_06 (256'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
.INIT_07 (256'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
.INIT_08 (256'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
.INIT_09 (256'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
.INIT_0A (256'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
.INIT_0B (256'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
.INIT_0C (256'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
.INIT_0D (256'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
.INIT_0E (256'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
.INITP_01 (256'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom( .ADDRARDADDR (address_a[13:0]),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[15:0]),
.DOPADOP (data_out_a[17:16]),
.DIADI (data_in_a[15:0]),
.DIPADIP (data_in_a[17:16]),
.WEA (2'b00),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b[13:0]),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[15:0]),
.DOPBDOP (data_out_b[17:16]),
.DIBDI (data_in_b[15:0]),
.DIPBDIP (data_in_b[17:16]),
.WEBWE (we_b[3:0]),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0));
end // v6;
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a[13:0] = {address[9:0], 4'b1111};
assign instruction = data_out_a[17:0];
assign data_in_a[17:0] = {16'b0000000000000000, address[11:10]};
assign jtag_dout = data_out_b[17:0];
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b[17:0] = data_out_b[17:0];
assign address_b[13:0] = 14'b11111111111111;
assign we_b[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b[17:0] = jtag_din[17:0];
assign address_b[13:0] = {jtag_addr[9:0], 4'b1111};
assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB18E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (18'b000000000000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (18'b000000000000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (18'b000000000000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (18'b000000000000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
.INIT_01 (256'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
.INIT_02 (256'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
.INIT_03 (256'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
.INIT_04 (256'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
.INIT_05 (256'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
.INIT_06 (256'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
.INIT_07 (256'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
.INIT_08 (256'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
.INIT_09 (256'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
.INIT_0A (256'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
.INIT_0B (256'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
.INIT_0C (256'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
.INIT_0D (256'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
.INIT_0E (256'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
.INITP_01 (256'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom( .ADDRARDADDR (address_a[13:0]),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[15:0]),
.DOPADOP (data_out_a[17:16]),
.DIADI (data_in_a[15:0]),
.DIPADIP (data_in_a[17:16]),
.WEA (2'b00),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b[13:0]),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[15:0]),
.DOPBDOP (data_out_b[17:16]),
.DIBDI (data_in_b[15:0]),
.DIPBDIP (data_in_b[17:16]),
.WEBWE (we_b[3:0]),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0));
end // akv7;
//
end // ram_1k_generate;
endgenerate
//
generate
if (C_RAM_SIZE_KWORDS == 2) begin : ram_2k_generate
//
if (C_FAMILY == "S6") begin: s6
//
assign address_a[13:0] = {address[10:0], 3'b000};
assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
assign data_in_a = {35'b00000000000000000000000000000000000, address[11]};
assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b_l = {3'b000, data_out_b_l[32], 24'b000000000000000000000000, data_out_b_l[7:0]};
assign data_in_b_h = {3'b000, data_out_b_h[32], 24'b000000000000000000000000, data_out_b_h[7:0]};
assign address_b[13:0] = 14'b00000000000000;
assign we_b[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b_h = {3'b000, jtag_din[17], 24'b000000000000000000000000, jtag_din[16:9]};
assign data_in_b_l = {3'b000, jtag_din[8], 24'b000000000000000000000000, jtag_din[7:0]};
assign address_b[13:0] = {jtag_addr[10:0], 3'b000};
assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB16BWER #(.DATA_WIDTH_A (9),
.DOA_REG (0),
.EN_RSTRAM_A ("FALSE"),
.INIT_A (9'b000000000),
.RST_PRIORITY_A ("CE"),
.SRVAL_A (9'b000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.DATA_WIDTH_B (9),
.DOB_REG (0),
.EN_RSTRAM_B ("FALSE"),
.INIT_B (9'b000000000),
.RST_PRIORITY_B ("CE"),
.SRVAL_B (9'b000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.RSTTYPE ("SYNC"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.SIM_DEVICE ("SPARTAN6"),
.INIT_00 (256'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
.INIT_01 (256'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
.INIT_02 (256'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
.INIT_03 (256'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
.INIT_04 (256'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
.INIT_05 (256'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
.INIT_06 (256'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
.INIT_07 (256'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_l( .ADDRA (address_a[13:0]),
.ENA (enable),
.CLKA (clk),
.DOA (data_out_a_l[31:0]),
.DOPA (data_out_a_l[35:32]),
.DIA (data_in_a[31:0]),
.DIPA (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEA (1'b0),
.RSTA (1'b0),
.ADDRB (address_b[13:0]),
.ENB (enable_b),
.CLKB (clk_b),
.DOB (data_out_b_l[31:0]),
.DOPB (data_out_b_l[35:32]),
.DIB (data_in_b_l[31:0]),
.DIPB (data_in_b_l[35:32]),
.WEB (we_b[3:0]),
.REGCEB (1'b0),
.RSTB (1'b0));
//
RAMB16BWER #(.DATA_WIDTH_A (9),
.DOA_REG (0),
.EN_RSTRAM_A ("FALSE"),
.INIT_A (9'b000000000),
.RST_PRIORITY_A ("CE"),
.SRVAL_A (9'b000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.DATA_WIDTH_B (9),
.DOB_REG (0),
.EN_RSTRAM_B ("FALSE"),
.INIT_B (9'b000000000),
.RST_PRIORITY_B ("CE"),
.SRVAL_B (9'b000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.RSTTYPE ("SYNC"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.SIM_DEVICE ("SPARTAN6"),
.INIT_00 (256'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
.INIT_01 (256'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
.INIT_02 (256'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
.INIT_03 (256'h68000880E068000800080D286800086800086800086800086800086800080008),
.INIT_04 (256'h08004808100008080008000800080008080448044803480D2880E068000880E0),
.INIT_05 (256'h0008080008000808000800080008081000080048080048080048080048080048),
.INIT_06 (256'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
.INIT_07 (256'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_h( .ADDRA (address_a[13:0]),
.ENA (enable),
.CLKA (clk),
.DOA (data_out_a_h[31:0]),
.DOPA (data_out_a_h[35:32]),
.DIA (data_in_a[31:0]),
.DIPA (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEA (1'b0),
.RSTA (1'b0),
.ADDRB (address_b[13:0]),
.ENB (enable_b),
.CLKB (clk_b),
.DOB (data_out_b_h[31:0]),
.DOPB (data_out_b_h[35:32]),
.DIB (data_in_b_h[31:0]),
.DIPB (data_in_b_h[35:32]),
.WEB (we_b[3:0]),
.REGCEB (1'b0),
.RSTB (1'b0));
end // s6;
//
//
if (C_FAMILY == "V6") begin: v6
//
assign address_a = {1'b1, address[10:0], 4'b1111};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {35'b00000000000000000000000000000000000, address[11]};
assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b = {2'b00, data_out_b[33:32], 16'b0000000000000000, data_out_b[15:0]};
assign address_b = 16'b1111111111111111;
assign we_b = 8'b00000000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b = {2'b00, jtag_din[17:16], 16'b0000000000000000, jtag_din[15:0]};
assign address_b = {1'b1, jtag_addr[10:0], 4'b1111};
assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB36E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("VIRTEX6"),
.INIT_00 (256'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
.INIT_01 (256'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
.INIT_02 (256'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
.INIT_03 (256'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
.INIT_04 (256'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
.INIT_05 (256'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
.INIT_06 (256'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
.INIT_07 (256'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
.INIT_08 (256'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
.INIT_09 (256'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
.INIT_0A (256'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
.INIT_0B (256'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
.INIT_0C (256'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
.INIT_0D (256'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
.INIT_0E (256'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
.INITP_01 (256'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[31:0]),
.DOPADOP (data_out_a[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[31:0]),
.DOPBDOP (data_out_b[35:32]),
.DIBDI (data_in_b[31:0]),
.DIPBDIP (data_in_b[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
end // v6;
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a = {1'b1, address[10:0], 4'b1111};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {35'b00000000000000000000000000000000000, address[11]};
assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b = {2'b00, data_out_b[33:32], 16'b0000000000000000, data_out_b[15:0]};
assign address_b = 16'b1111111111111111;
assign we_b = 8'b00000000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b = {2'b00, jtag_din[17:16], 16'b0000000000000000, jtag_din[15:0]};
assign address_b = {1'b1, jtag_addr[10:0], 4'b1111};
assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB36E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
.INIT_01 (256'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
.INIT_02 (256'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
.INIT_03 (256'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
.INIT_04 (256'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
.INIT_05 (256'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
.INIT_06 (256'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
.INIT_07 (256'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
.INIT_08 (256'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
.INIT_09 (256'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
.INIT_0A (256'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
.INIT_0B (256'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
.INIT_0C (256'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
.INIT_0D (256'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
.INIT_0E (256'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_40 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41 (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48 (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4D (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_54 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58 (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_60 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
.INITP_01 (256'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[31:0]),
.DOPADOP (data_out_a[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[31:0]),
.DOPBDOP (data_out_b[35:32]),
.DIBDI (data_in_b[31:0]),
.DIPBDIP (data_in_b[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
end // akv7;
//
end // ram_2k_generate;
endgenerate
//
generate
if (C_RAM_SIZE_KWORDS == 4) begin : ram_4k_generate
if (C_FAMILY == "S6") begin: s6
//
assign address_a[13:0] = {address[10:0], 3'b000};
assign data_in_a = 36'b000000000000000000000000000000000000;
//
FD s6_a11_flop ( .D (address[11]),
.Q (pipe_a11),
.C (clk));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux0_lut( .I0 (data_out_a_ll[0]),
.I1 (data_out_a_hl[0]),
.I2 (data_out_a_ll[1]),
.I3 (data_out_a_hl[1]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[0]),
.O6 (instruction[1]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux2_lut( .I0 (data_out_a_ll[2]),
.I1 (data_out_a_hl[2]),
.I2 (data_out_a_ll[3]),
.I3 (data_out_a_hl[3]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[2]),
.O6 (instruction[3]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux4_lut( .I0 (data_out_a_ll[4]),
.I1 (data_out_a_hl[4]),
.I2 (data_out_a_ll[5]),
.I3 (data_out_a_hl[5]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[4]),
.O6 (instruction[5]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux6_lut( .I0 (data_out_a_ll[6]),
.I1 (data_out_a_hl[6]),
.I2 (data_out_a_ll[7]),
.I3 (data_out_a_hl[7]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[6]),
.O6 (instruction[7]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux8_lut( .I0 (data_out_a_ll[32]),
.I1 (data_out_a_hl[32]),
.I2 (data_out_a_lh[0]),
.I3 (data_out_a_hh[0]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[8]),
.O6 (instruction[9]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux10_lut( .I0 (data_out_a_lh[1]),
.I1 (data_out_a_hh[1]),
.I2 (data_out_a_lh[2]),
.I3 (data_out_a_hh[2]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[10]),
.O6 (instruction[11]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux12_lut( .I0 (data_out_a_lh[3]),
.I1 (data_out_a_hh[3]),
.I2 (data_out_a_lh[4]),
.I3 (data_out_a_hh[4]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[12]),
.O6 (instruction[13]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux14_lut( .I0 (data_out_a_lh[5]),
.I1 (data_out_a_hh[5]),
.I2 (data_out_a_lh[6]),
.I3 (data_out_a_hh[6]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[14]),
.O6 (instruction[15]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_mux16_lut( .I0 (data_out_a_lh[7]),
.I1 (data_out_a_hh[7]),
.I2 (data_out_a_lh[32]),
.I3 (data_out_a_hh[32]),
.I4 (pipe_a11),
.I5 (1'b1),
.O5 (instruction[16]),
.O6 (instruction[17]));
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b_ll = {3'b000, data_out_b_ll[32], 24'b000000000000000000000000, data_out_b_ll[7:0]};
assign data_in_b_lh = {3'b000, data_out_b_lh[32], 24'b000000000000000000000000, data_out_b_lh[7:0]};
assign data_in_b_hl = {3'b000, data_out_b_hl[32], 24'b000000000000000000000000, data_out_b_hl[7:0]};
assign data_in_b_hh = {3'b000, data_out_b_hh[32], 24'b000000000000000000000000, data_out_b_hh[7:0]};
assign address_b[13:0] = 14'b00000000000000;
assign we_b_l[3:0] = 4'b0000;
assign we_b_h[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b_lh = {3'b000, jtag_din[17], 24'b000000000000000000000000, jtag_din[16:9]};
assign data_in_b_ll = {3'b000, jtag_din[8], 24'b000000000000000000000000, jtag_din[7:0]};
assign data_in_b_hh = {3'b000, jtag_din[17], 24'b000000000000000000000000, jtag_din[16:9]};
assign data_in_b_hl = {3'b000, jtag_din[8], 24'b000000000000000000000000, jtag_din[7:0]};
assign address_b[13:0] = {jtag_addr[10:0], 3'b000};
//
LUT6_2 # ( .INIT (64'h8000000020000000))
s6_4k_jtag_we_lut( .I0 (jtag_we),
.I1 (jtag_addr[11]),
.I2 (1'b1),
.I3 (1'b1),
.I4 (1'b1),
.I5 (1'b1),
.O5 (jtag_we_l),
.O6 (jtag_we_h));
//
assign we_b_l[3:0] = {jtag_we_l, jtag_we_l, jtag_we_l, jtag_we_l};
assign we_b_h[3:0] = {jtag_we_h, jtag_we_h, jtag_we_h, jtag_we_h};
//
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux0_lut( .I0 (data_out_b_ll[0]),
.I1 (data_out_b_hl[0]),
.I2 (data_out_b_ll[1]),
.I3 (data_out_b_hl[1]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[0]),
.O6 (jtag_dout[1]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux2_lut( .I0 (data_out_b_ll[2]),
.I1 (data_out_b_hl[2]),
.I2 (data_out_b_ll[3]),
.I3 (data_out_b_hl[3]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[2]),
.O6 (jtag_dout[3]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux4_lut( .I0 (data_out_b_ll[4]),
.I1 (data_out_b_hl[4]),
.I2 (data_out_b_ll[5]),
.I3 (data_out_b_hl[5]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[4]),
.O6 (jtag_dout[5]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux6_lut( .I0 (data_out_b_ll[6]),
.I1 (data_out_b_hl[6]),
.I2 (data_out_b_ll[7]),
.I3 (data_out_b_hl[7]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[6]),
.O6 (jtag_dout[7]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux8_lut( .I0 (data_out_b_ll[32]),
.I1 (data_out_b_hl[32]),
.I2 (data_out_b_lh[0]),
.I3 (data_out_b_hh[0]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[8]),
.O6 (jtag_dout[9]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux10_lut( .I0 (data_out_b_lh[1]),
.I1 (data_out_b_hh[1]),
.I2 (data_out_b_lh[2]),
.I3 (data_out_b_hh[2]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[10]),
.O6 (jtag_dout[11]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux12_lut( .I0 (data_out_b_lh[3]),
.I1 (data_out_b_hh[3]),
.I2 (data_out_b_lh[4]),
.I3 (data_out_b_hh[4]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[12]),
.O6 (jtag_dout[13]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux14_lut( .I0 (data_out_b_lh[5]),
.I1 (data_out_b_hh[5]),
.I2 (data_out_b_lh[6]),
.I3 (data_out_b_hh[6]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[14]),
.O6 (jtag_dout[15]));
//
LUT6_2 # ( .INIT (64'hFF00F0F0CCCCAAAA))
s6_4k_jtag_mux16_lut( .I0 (data_out_b_lh[7]),
.I1 (data_out_b_hh[7]),
.I2 (data_out_b_lh[32]),
.I3 (data_out_b_hh[32]),
.I4 (jtag_addr[11]),
.I5 (1'b1),
.O5 (jtag_dout[16]),
.O6 (jtag_dout[17]));
//
end // loader;
//
RAMB16BWER #(.DATA_WIDTH_A (9),
.DOA_REG (0),
.EN_RSTRAM_A ("FALSE"),
.INIT_A (9'b000000000),
.RST_PRIORITY_A ("CE"),
.SRVAL_A (9'b000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.DATA_WIDTH_B (9),
.DOB_REG (0),
.EN_RSTRAM_B ("FALSE"),
.INIT_B (9'b000000000),
.RST_PRIORITY_B ("CE"),
.SRVAL_B (9'b000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.RSTTYPE ("SYNC"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.SIM_DEVICE ("SPARTAN6"),
.INIT_00 (256'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
.INIT_01 (256'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
.INIT_02 (256'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
.INIT_03 (256'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
.INIT_04 (256'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
.INIT_05 (256'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
.INIT_06 (256'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
.INIT_07 (256'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_ll( .ADDRA (address_a[13:0]),
.ENA (enable),
.CLKA (clk),
.DOA (data_out_a_ll[31:0]),
.DOPA (data_out_a_ll[35:32]),
.DIA (data_in_a[31:0]),
.DIPA (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEA (1'b0),
.RSTA (1'b0),
.ADDRB (address_b[13:0]),
.ENB (enable_b),
.CLKB (clk_b),
.DOB (data_out_b_ll[31:0]),
.DOPB (data_out_b_ll[35:32]),
.DIB (data_in_b_ll[31:0]),
.DIPB (data_in_b_ll[35:32]),
.WEB (we_b_l[3:0]),
.REGCEB (1'b0),
.RSTB (1'b0));
//
RAMB16BWER #(.DATA_WIDTH_A (9),
.DOA_REG (0),
.EN_RSTRAM_A ("FALSE"),
.INIT_A (9'b000000000),
.RST_PRIORITY_A ("CE"),
.SRVAL_A (9'b000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.DATA_WIDTH_B (9),
.DOB_REG (0),
.EN_RSTRAM_B ("FALSE"),
.INIT_B (9'b000000000),
.RST_PRIORITY_B ("CE"),
.SRVAL_B (9'b000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.RSTTYPE ("SYNC"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.SIM_DEVICE ("SPARTAN6"),
.INIT_00 (256'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
.INIT_01 (256'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
.INIT_02 (256'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
.INIT_03 (256'h68000880E068000800080D286800086800086800086800086800086800080008),
.INIT_04 (256'h08004808100008080008000800080008080448044803480D2880E068000880E0),
.INIT_05 (256'h0008080008000808000800080008081000080048080048080048080048080048),
.INIT_06 (256'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
.INIT_07 (256'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_lh( .ADDRA (address_a[13:0]),
.ENA (enable),
.CLKA (clk),
.DOA (data_out_a_lh[31:0]),
.DOPA (data_out_a_lh[35:32]),
.DIA (data_in_a[31:0]),
.DIPA (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEA (1'b0),
.RSTA (1'b0),
.ADDRB (address_b[13:0]),
.ENB (enable_b),
.CLKB (clk_b),
.DOB (data_out_b_lh[31:0]),
.DOPB (data_out_b_lh[35:32]),
.DIB (data_in_b_lh[31:0]),
.DIPB (data_in_b_lh[35:32]),
.WEB (we_b_l[3:0]),
.REGCEB (1'b0),
.RSTB (1'b0));
//
RAMB16BWER #(.DATA_WIDTH_A (9),
.DOA_REG (0),
.EN_RSTRAM_A ("FALSE"),
.INIT_A (9'b000000000),
.RST_PRIORITY_A ("CE"),
.SRVAL_A (9'b000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.DATA_WIDTH_B (9),
.DOB_REG (0),
.EN_RSTRAM_B ("FALSE"),
.INIT_B (9'b000000000),
.RST_PRIORITY_B ("CE"),
.SRVAL_B (9'b000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.RSTTYPE ("SYNC"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.SIM_DEVICE ("SPARTAN6"),
.INIT_00 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_hl( .ADDRA (address_a[13:0]),
.ENA (enable),
.CLKA (clk),
.DOA (data_out_a_hl[31:0]),
.DOPA (data_out_a_hl[35:32]),
.DIA (data_in_a[31:0]),
.DIPA (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEA (1'b0),
.RSTA (1'b0),
.ADDRB (address_b[13:0]),
.ENB (enable_b),
.CLKB (clk_b),
.DOB (data_out_b_hl[31:0]),
.DOPB (data_out_b_hl[35:32]),
.DIB (data_in_b_hl[31:0]),
.DIPB (data_in_b_hl[35:32]),
.WEB (we_b_h[3:0]),
.REGCEB (1'b0),
.RSTB (1'b0));
//
RAMB16BWER #(.DATA_WIDTH_A (9),
.DOA_REG (0),
.EN_RSTRAM_A ("FALSE"),
.INIT_A (9'b000000000),
.RST_PRIORITY_A ("CE"),
.SRVAL_A (9'b000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.DATA_WIDTH_B (9),
.DOB_REG (0),
.EN_RSTRAM_B ("FALSE"),
.INIT_B (9'b000000000),
.RST_PRIORITY_B ("CE"),
.SRVAL_B (9'b000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.RSTTYPE ("SYNC"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.SIM_DEVICE ("SPARTAN6"),
.INIT_00 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_hh( .ADDRA (address_a[13:0]),
.ENA (enable),
.CLKA (clk),
.DOA (data_out_a_hh[31:0]),
.DOPA (data_out_a_hh[35:32]),
.DIA (data_in_a[31:0]),
.DIPA (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEA (1'b0),
.RSTA (1'b0),
.ADDRB (address_b[13:0]),
.ENB (enable_b),
.CLKB (clk_b),
.DOB (data_out_b_hh[31:0]),
.DOPB (data_out_b_hh[35:32]),
.DIB (data_in_b_hh[31:0]),
.DIPB (data_in_b_hh[35:32]),
.WEB (we_b_h[3:0]),
.REGCEB (1'b0),
.RSTB (1'b0));
//
end // s6;
//
//
if (C_FAMILY == "V6") begin: v6
//
assign address_a = {1'b1, address[11:0], 3'b111};
assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
assign data_in_a = 36'b00000000000000000000000000000000000;
assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b_l = {3'b000, data_out_b_l[32], 24'b000000000000000000000000, data_out_b_l[7:0]};
assign data_in_b_h = {3'b000, data_out_b_h[32], 24'b000000000000000000000000, data_out_b_h[7:0]};
assign address_b = 16'b1111111111111111;
assign we_b = 8'b00000000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b_h = {3'b000, jtag_din[17], 24'b000000000000000000000000, jtag_din[16:9]};
assign data_in_b_l = {3'b000, jtag_din[8], 24'b000000000000000000000000, jtag_din[7:0]};
assign address_b = {1'b1, jtag_addr[11:0], 3'b111};
assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB36E1 #(.READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("VIRTEX6"),
.INIT_00 (256'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
.INIT_01 (256'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
.INIT_02 (256'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
.INIT_03 (256'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
.INIT_04 (256'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
.INIT_05 (256'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
.INIT_06 (256'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
.INIT_07 (256'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41 (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49 (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_l( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_l[31:0]),
.DOPADOP (data_out_a_l[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_l[31:0]),
.DOPBDOP (data_out_b_l[35:32]),
.DIBDI (data_in_b_l[31:0]),
.DIPBDIP (data_in_b_l[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
RAMB36E1 #(.READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("VIRTEX6"),
.INIT_00 (256'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
.INIT_01 (256'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
.INIT_02 (256'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
.INIT_03 (256'h68000880E068000800080D286800086800086800086800086800086800080008),
.INIT_04 (256'h08004808100008080008000800080008080448044803480D2880E068000880E0),
.INIT_05 (256'h0008080008000808000800080008081000080048080048080048080048080048),
.INIT_06 (256'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
.INIT_07 (256'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_h( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_h[31:0]),
.DOPADOP (data_out_a_h[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_h[31:0]),
.DOPBDOP (data_out_b_h[35:32]),
.DIBDI (data_in_b_h[31:0]),
.DIPBDIP (data_in_b_h[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
end // v6;
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a = {1'b1, address[11:0], 3'b111};
assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
assign data_in_a = 36'b00000000000000000000000000000000000;
assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b_l = {3'b000, data_out_b_l[32], 24'b000000000000000000000000, data_out_b_l[7:0]};
assign data_in_b_h = {3'b000, data_out_b_h[32], 24'b000000000000000000000000, data_out_b_h[7:0]};
assign address_b = 16'b1111111111111111;
assign we_b = 8'b00000000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b_h = {3'b000, jtag_din[17], 24'b000000000000000000000000, jtag_din[16:9]};
assign data_in_b_l = {3'b000, jtag_din[8], 24'b000000000000000000000000, jtag_din[7:0]};
assign address_b = {1'b1, jtag_addr[11:0], 3'b111};
assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB36E1 #(.READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
.INIT_01 (256'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
.INIT_02 (256'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
.INIT_03 (256'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
.INIT_04 (256'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
.INIT_05 (256'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
.INIT_06 (256'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
.INIT_07 (256'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_l( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_l[31:0]),
.DOPADOP (data_out_a_l[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_l[31:0]),
.DOPBDOP (data_out_b_l[35:32]),
.DIBDI (data_in_b_l[31:0]),
.DIPBDIP (data_in_b_l[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
RAMB36E1 #(.READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
.INIT_01 (256'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
.INIT_02 (256'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
.INIT_03 (256'h68000880E068000800080D286800086800086800086800086800086800080008),
.INIT_04 (256'h08004808100008080008000800080008080448044803480D2880E068000880E0),
.INIT_05 (256'h0008080008000808000800080008081000080048080048080048080048080048),
.INIT_06 (256'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
.INIT_07 (256'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
.INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_00 (256'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
.INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F (256'h0000000000000000000000000000000000000000000000000000000000000000))
kcpsm6_rom_h( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_h[31:0]),
.DOPADOP (data_out_a_h[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_h[31:0]),
.DOPBDOP (data_out_b_h[35:32]),
.DIBDI (data_in_b_h[31:0]),
.DIPBDIP (data_in_b_h[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
end // akv7;
//
end // ram_4k_generate;
endgenerate
//
// JTAG Loader
//
generate
if (C_JTAG_LOADER_ENABLE == 1) begin: instantiate_loader
jtag_loader_6 #( .C_FAMILY (C_FAMILY),
.C_NUM_PICOBLAZE (1),
.C_JTAG_LOADER_ENABLE (C_JTAG_LOADER_ENABLE),
.C_BRAM_MAX_ADDR_WIDTH (BRAM_ADDRESS_WIDTH),
.C_ADDR_WIDTH_0 (BRAM_ADDRESS_WIDTH))
jtag_loader_6_inst(.picoblaze_reset (rdl_bus),
.jtag_en (jtag_en),
.jtag_din (jtag_din),
.jtag_addr (jtag_addr[BRAM_ADDRESS_WIDTH-1 : 0]),
.jtag_clk (jtag_clk),
.jtag_we (jtag_we),
.jtag_dout_0 (jtag_dout),
.jtag_dout_1 (jtag_dout), // ports 1-7 are not used
.jtag_dout_2 (jtag_dout), // in a 1 device debug
.jtag_dout_3 (jtag_dout), // session. However, Synplify
.jtag_dout_4 (jtag_dout), // etc require all ports are
.jtag_dout_5 (jtag_dout), // connected
.jtag_dout_6 (jtag_dout),
.jtag_dout_7 (jtag_dout));
end //instantiate_loader
endgenerate
//
//
endmodule |
module jtag_loader_6 (picoblaze_reset, jtag_en, jtag_din, jtag_addr, jtag_clk, jtag_we, jtag_dout_0, jtag_dout_1, jtag_dout_2, jtag_dout_3, jtag_dout_4, jtag_dout_5, jtag_dout_6, jtag_dout_7);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "V6";
parameter integer C_NUM_PICOBLAZE = 1;
parameter integer C_BRAM_MAX_ADDR_WIDTH = 10;
parameter integer C_PICOBLAZE_INSTRUCTION_DATA_WIDTH = 18;
parameter integer C_JTAG_CHAIN = 2;
parameter [4:0] C_ADDR_WIDTH_0 = 10;
parameter [4:0] C_ADDR_WIDTH_1 = 10;
parameter [4:0] C_ADDR_WIDTH_2 = 10;
parameter [4:0] C_ADDR_WIDTH_3 = 10;
parameter [4:0] C_ADDR_WIDTH_4 = 10;
parameter [4:0] C_ADDR_WIDTH_5 = 10;
parameter [4:0] C_ADDR_WIDTH_6 = 10;
parameter [4:0] C_ADDR_WIDTH_7 = 10;
//
output [C_NUM_PICOBLAZE-1:0] picoblaze_reset;
output [C_NUM_PICOBLAZE-1:0] jtag_en;
output [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din;
output [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr;
output jtag_clk ;
output jtag_we;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7;
//
//
wire [2:0] num_picoblaze;
wire [4:0] picoblaze_instruction_data_width;
//
wire drck;
wire shift_clk;
wire shift_din;
wire shift_dout;
wire shift;
wire capture;
//
reg control_reg_ce;
reg [C_NUM_PICOBLAZE-1:0] bram_ce;
wire [C_NUM_PICOBLAZE-1:0] bus_zero;
wire [C_NUM_PICOBLAZE-1:0] jtag_en_int;
wire [7:0] jtag_en_expanded;
reg [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr_int;
reg [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_din;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_dout;
reg [7:0] control_dout_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] bram_dout_int;
reg jtag_we_int;
wire jtag_clk_int;
wire bram_ce_valid;
reg din_load;
//
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7_masked;
reg [C_NUM_PICOBLAZE-1:0] picoblaze_reset_int;
//
initial picoblaze_reset_int = 0;
//
genvar i;
//
generate
for (i = 0; i <= C_NUM_PICOBLAZE-1; i = i+1)
begin : npzero_loop
assign bus_zero[i] = 1'b0;
end
endgenerate
//
generate
//
if (C_JTAG_LOADER_ENABLE == 1)
begin : jtag_loader_gen
//
// Insert BSCAN primitive for target device architecture.
//
if (C_FAMILY == "S6")
begin : BSCAN_SPARTAN6_gen
BSCAN_SPARTAN6 # (.JTAG_CHAIN (C_JTAG_CHAIN))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "V6")
begin : BSCAN_VIRTEX6_gen
BSCAN_VIRTEX6 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "7S")
begin : BSCAN_7SERIES_gen
BSCANE2 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
// Insert clock buffer to ensure reliable shift operations.
//
BUFG upload_clock (.I (drck), .O (shift_clk));
//
//
// Shift Register
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
control_reg_ce <= shift_din;
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[0] <= control_reg_ce;
end
end
//
for (i = 0; i <= C_NUM_PICOBLAZE-2; i = i+1)
begin : loop0
if (C_NUM_PICOBLAZE > 1) begin
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[i+1] <= bram_ce[i];
end
end
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_we_int <= bram_ce[C_NUM_PICOBLAZE-1];
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[0] <= jtag_we_int;
end
end
//
for (i = 0; i <= C_BRAM_MAX_ADDR_WIDTH-2; i = i+1)
begin : loop1
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[i+1] <= jtag_addr_int[i];
end
end
end
//
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[0] <= bram_dout_int[0];
end
else if (shift == 1'b1) begin
jtag_din_int[0] <= jtag_addr_int[C_BRAM_MAX_ADDR_WIDTH-1];
end
end
//
for (i = 0; i <= C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2; i = i+1)
begin : loop2
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[i+1] <= bram_dout_int[i+1];
end
if (shift == 1'b1) begin
jtag_din_int[i+1] <= jtag_din_int[i];
end
end
end
//
assign shift_dout = jtag_din_int[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1];
//
//
always @ (bram_ce or din_load or capture or bus_zero or control_reg_ce) begin
if ( bram_ce == bus_zero ) begin
din_load <= capture & control_reg_ce;
end else begin
din_load <= capture;
end
end
//
//
// Control Registers
//
assign num_picoblaze = C_NUM_PICOBLAZE-3'h1;
assign picoblaze_instruction_data_width = C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-5'h01;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b0 && control_reg_ce == 1'b1) begin
case (jtag_addr_int[3:0])
0 : // 0 = version - returns (7:4) illustrating number of PB
// and [3:0] picoblaze instruction data width
control_dout_int <= {num_picoblaze, picoblaze_instruction_data_width};
1 : // 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) begin
control_dout_int <= {picoblaze_reset_int[0], 2'b00, C_ADDR_WIDTH_0-5'h01};
end else begin
control_dout_int <= 8'h00;
end
2 : // 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) begin
control_dout_int <= {picoblaze_reset_int[1], 2'b00, C_ADDR_WIDTH_1-5'h01};
end else begin
control_dout_int <= 8'h00;
end
3 : // 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) begin
control_dout_int <= {picoblaze_reset_int[2], 2'b00, C_ADDR_WIDTH_2-5'h01};
end else begin
control_dout_int <= 8'h00;
end
4 : // 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) begin
control_dout_int <= {picoblaze_reset_int[3], 2'b00, C_ADDR_WIDTH_3-5'h01};
end else begin
control_dout_int <= 8'h00;
end
5: // 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) begin
control_dout_int <= {picoblaze_reset_int[4], 2'b00, C_ADDR_WIDTH_4-5'h01};
end else begin
control_dout_int <= 8'h00;
end
6 : // 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) begin
control_dout_int <= {picoblaze_reset_int[5], 2'b00, C_ADDR_WIDTH_5-5'h01};
end else begin
control_dout_int <= 8'h00;
end
7 : // 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) begin
control_dout_int <= {picoblaze_reset_int[6], 2'b00, C_ADDR_WIDTH_6-5'h01};
end else begin
control_dout_int <= 8'h00;
end
8 : // 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) begin
control_dout_int <= {picoblaze_reset_int[7], 2'b00, C_ADDR_WIDTH_7-5'h01};
end else begin
control_dout_int <= 8'h00;
end
15 : control_dout_int <= C_BRAM_MAX_ADDR_WIDTH -1;
default : control_dout_int <= 8'h00;
//
endcase
end else begin
control_dout_int <= 8'h00;
end
end
//
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8] = control_dout_int;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b1 && control_reg_ce == 1'b1) begin
picoblaze_reset_int[C_NUM_PICOBLAZE-1:0] <= control_din[C_NUM_PICOBLAZE-1:0];
end
end
//
//
// Assignments
//
if (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8) begin
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9:0] = 10'h000;
end
//
// Qualify the blockram CS signal with bscan select output
assign jtag_en_int = (bram_ce_valid) ? bram_ce : bus_zero;
//
assign jtag_en_expanded[C_NUM_PICOBLAZE-1:0] = jtag_en_int;
//
for (i = 7; i >= C_NUM_PICOBLAZE; i = i-1)
begin : loop4
if (C_NUM_PICOBLAZE < 8) begin : jtag_en_expanded_gen
assign jtag_en_expanded[i] = 1'b0;
end
end
//
assign bram_dout_int = control_dout | jtag_dout_0_masked | jtag_dout_1_masked | jtag_dout_2_masked | jtag_dout_3_masked | jtag_dout_4_masked | jtag_dout_5_masked | jtag_dout_6_masked | jtag_dout_7_masked;
//
assign control_din = jtag_din_int;
//
assign jtag_dout_0_masked = (jtag_en_expanded[0]) ? jtag_dout_0 : 18'h00000;
assign jtag_dout_1_masked = (jtag_en_expanded[1]) ? jtag_dout_1 : 18'h00000;
assign jtag_dout_2_masked = (jtag_en_expanded[2]) ? jtag_dout_2 : 18'h00000;
assign jtag_dout_3_masked = (jtag_en_expanded[3]) ? jtag_dout_3 : 18'h00000;
assign jtag_dout_4_masked = (jtag_en_expanded[4]) ? jtag_dout_4 : 18'h00000;
assign jtag_dout_5_masked = (jtag_en_expanded[5]) ? jtag_dout_5 : 18'h00000;
assign jtag_dout_6_masked = (jtag_en_expanded[6]) ? jtag_dout_6 : 18'h00000;
assign jtag_dout_7_masked = (jtag_en_expanded[7]) ? jtag_dout_7 : 18'h00000;
//
assign jtag_en = jtag_en_int;
assign jtag_din = jtag_din_int;
assign jtag_addr = jtag_addr_int;
assign jtag_clk = jtag_clk_int;
assign jtag_we = jtag_we_int;
assign picoblaze_reset = picoblaze_reset_int;
//
end
endgenerate
//
endmodule |
module PLL1 (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [0:0] sub_wire2 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c0 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 5,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 4,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 5,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 8,
altpll_component.clk2_phase_shift = "6250",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule |
module HSDAC #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter SIM_DEVICE = "ULTRASCALE_PLUS",
parameter integer XPA_CFG0 = 0,
parameter integer XPA_CFG1 = 0,
parameter integer XPA_NUM_DACS = 0,
parameter integer XPA_NUM_DUCS = 0,
parameter XPA_PLL_USED = "No",
parameter integer XPA_SAMPLE_RATE_MSPS = 0
)(
output CLK_DAC,
output [15:0] DOUT,
output DRDY,
output PLL_DMON_OUT,
output PLL_REFCLK_OUT,
output [15:0] STATUS_COMMON,
output [15:0] STATUS_DAC0,
output [15:0] STATUS_DAC1,
output [15:0] STATUS_DAC2,
output [15:0] STATUS_DAC3,
output SYSREF_OUT_NORTH,
output SYSREF_OUT_SOUTH,
output VOUT0_N,
output VOUT0_P,
output VOUT1_N,
output VOUT1_P,
output VOUT2_N,
output VOUT2_P,
output VOUT3_N,
output VOUT3_P,
input CLK_FIFO_LM,
input [15:0] CONTROL_COMMON,
input [15:0] CONTROL_DAC0,
input [15:0] CONTROL_DAC1,
input [15:0] CONTROL_DAC2,
input [15:0] CONTROL_DAC3,
input DAC_CLK_N,
input DAC_CLK_P,
input [11:0] DADDR,
input [255:0] DATA_DAC0,
input [255:0] DATA_DAC1,
input [255:0] DATA_DAC2,
input [255:0] DATA_DAC3,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input FABRIC_CLK,
input PLL_MONCLK,
input PLL_REFCLK_IN,
input SYSREF_IN_NORTH,
input SYSREF_IN_SOUTH,
input SYSREF_N,
input SYSREF_P
);
// define constants
localparam MODULE_NAME = "HSDAC";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "HSDAC_dr.v"
`else
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam [15:0] XPA_CFG0_REG = XPA_CFG0;
localparam [15:0] XPA_CFG1_REG = XPA_CFG1;
localparam [2:0] XPA_NUM_DACS_REG = XPA_NUM_DACS;
localparam [2:0] XPA_NUM_DUCS_REG = XPA_NUM_DUCS;
localparam [24:1] XPA_PLL_USED_REG = XPA_PLL_USED;
localparam [13:0] XPA_SAMPLE_RATE_MSPS_REG = XPA_SAMPLE_RATE_MSPS;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire CLK_DAC_SPARE_out;
wire CLK_DAC_out;
wire DRDY_out;
wire PLL_DMON_OUT_out;
wire PLL_REFCLK_OUT_out;
wire SYSREF_OUT_NORTH_out;
wire SYSREF_OUT_SOUTH_out;
wire VOUT0_N_out;
wire VOUT0_P_out;
wire VOUT1_N_out;
wire VOUT1_P_out;
wire VOUT2_N_out;
wire VOUT2_P_out;
wire VOUT3_N_out;
wire VOUT3_P_out;
wire [15:0] DOUT_out;
wire [15:0] STATUS_COMMON_out;
wire [15:0] STATUS_DAC0_out;
wire [15:0] STATUS_DAC1_out;
wire [15:0] STATUS_DAC2_out;
wire [15:0] STATUS_DAC3_out;
wire [15:0] TEST_STATUS_out;
wire [1:0] PLL_SCAN_OUT_B_FD_out;
wire [299:0] TEST_SO_out;
wire CLK_FIFO_LM_in;
wire DAC_CLK_N_in;
wire DAC_CLK_P_in;
wire DCLK_in;
wire DEN_in;
wire DWE_in;
wire FABRIC_CLK_in;
wire PLL_MONCLK_in;
wire PLL_REFCLK_IN_in;
wire PLL_SCAN_EN_B_FD_in;
wire PLL_SCAN_MODE_B_FD_in;
wire PLL_SCAN_RST_EN_FD_in;
wire SYSREF_IN_NORTH_in;
wire SYSREF_IN_SOUTH_in;
wire SYSREF_N_in;
wire SYSREF_P_in;
wire TEST_SCAN_MODE_B_in;
wire TEST_SCAN_RESET_in;
wire TEST_SE_B_in;
wire [11:0] DADDR_in;
wire [15:0] CONTROL_COMMON_in;
wire [15:0] CONTROL_DAC0_in;
wire [15:0] CONTROL_DAC1_in;
wire [15:0] CONTROL_DAC2_in;
wire [15:0] CONTROL_DAC3_in;
wire [15:0] DI_in;
wire [15:0] TEST_SCAN_CTRL_in;
wire [1:0] PLL_SCAN_CLK_FD_in;
wire [1:0] PLL_SCAN_IN_FD_in;
wire [255:0] DATA_DAC0_in;
wire [255:0] DATA_DAC1_in;
wire [255:0] DATA_DAC2_in;
wire [255:0] DATA_DAC3_in;
wire [299:0] TEST_SI_in;
wire [4:0] TEST_SCAN_CLK_in;
`ifdef XIL_TIMING
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire FABRIC_CLK_delay;
wire [11:0] DADDR_delay;
wire [15:0] CONTROL_COMMON_delay;
wire [15:0] DI_delay;
`endif
real VOUT0_N_real;
real VOUT0_P_real;
real VOUT1_N_real;
real VOUT1_P_real;
real VOUT2_N_real;
real VOUT2_P_real;
real VOUT3_N_real;
real VOUT3_P_real;
assign CLK_DAC = CLK_DAC_out;
assign DOUT = DOUT_out;
assign DRDY = DRDY_out;
assign PLL_DMON_OUT = PLL_DMON_OUT_out;
assign PLL_REFCLK_OUT = PLL_REFCLK_OUT_out;
assign STATUS_COMMON = STATUS_COMMON_out;
assign STATUS_DAC0 = STATUS_DAC0_out;
assign STATUS_DAC1 = STATUS_DAC1_out;
assign STATUS_DAC2 = STATUS_DAC2_out;
assign STATUS_DAC3 = STATUS_DAC3_out;
assign SYSREF_OUT_NORTH = SYSREF_OUT_NORTH_out;
assign SYSREF_OUT_SOUTH = SYSREF_OUT_SOUTH_out;
assign VOUT0_N = VOUT0_N_out;
assign VOUT0_P = VOUT0_P_out;
assign VOUT1_N = VOUT1_N_out;
assign VOUT1_P = VOUT1_P_out;
assign VOUT2_N = VOUT2_N_out;
assign VOUT2_P = VOUT2_P_out;
assign VOUT3_N = VOUT3_N_out;
assign VOUT3_P = VOUT3_P_out;
`ifdef XIL_TIMING
assign CONTROL_COMMON_in = CONTROL_COMMON_delay;
assign DADDR_in = DADDR_delay;
assign DCLK_in = DCLK_delay;
assign DEN_in = DEN_delay;
assign DI_in = DI_delay;
assign DWE_in = DWE_delay;
assign FABRIC_CLK_in = FABRIC_CLK_delay;
`else
assign CONTROL_COMMON_in = CONTROL_COMMON;
assign DADDR_in = DADDR;
assign DCLK_in = DCLK;
assign DEN_in = DEN;
assign DI_in = DI;
assign DWE_in = DWE;
assign FABRIC_CLK_in = FABRIC_CLK;
`endif
assign CLK_FIFO_LM_in = CLK_FIFO_LM;
assign CONTROL_DAC0_in = CONTROL_DAC0;
assign CONTROL_DAC1_in = CONTROL_DAC1;
assign CONTROL_DAC2_in = CONTROL_DAC2;
assign CONTROL_DAC3_in = CONTROL_DAC3;
assign DAC_CLK_N_in = DAC_CLK_N;
assign DAC_CLK_P_in = DAC_CLK_P;
assign DATA_DAC0_in = DATA_DAC0;
assign DATA_DAC1_in = DATA_DAC1;
assign DATA_DAC2_in = DATA_DAC2;
assign DATA_DAC3_in = DATA_DAC3;
assign PLL_MONCLK_in = PLL_MONCLK;
assign PLL_REFCLK_IN_in = PLL_REFCLK_IN;
assign SYSREF_IN_NORTH_in = SYSREF_IN_NORTH;
assign SYSREF_IN_SOUTH_in = SYSREF_IN_SOUTH;
assign SYSREF_N_in = SYSREF_N;
assign SYSREF_P_in = SYSREF_P;
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_CFG0_REG < 0) || (XPA_CFG0_REG > 65535))) begin
$display("Error: [Unisim %s-102] XPA_CFG0 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_CFG1_REG < 0) || (XPA_CFG1_REG > 65535))) begin
$display("Error: [Unisim %s-103] XPA_CFG1 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_NUM_DACS_REG < 0) || (XPA_NUM_DACS_REG > 4))) begin
$display("Error: [Unisim %s-104] XPA_NUM_DACS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DACS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_NUM_DUCS_REG < 0) || (XPA_NUM_DUCS_REG > 4))) begin
$display("Error: [Unisim %s-105] XPA_NUM_DUCS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DUCS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_PLL_USED_REG != "No") &&
(XPA_PLL_USED_REG != "Yes"))) begin
$display("Error: [Unisim %s-106] XPA_PLL_USED attribute is set to %s. Legal values for this attribute are No or Yes. Instance: %m", MODULE_NAME, XPA_PLL_USED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_SAMPLE_RATE_MSPS_REG < 0) || (XPA_SAMPLE_RATE_MSPS_REG > 10000))) begin
$display("Error: [Unisim %s-107] XPA_SAMPLE_RATE_MSPS attribute is set to %d. Legal values for this attribute are 0 to 10000. Instance: %m", MODULE_NAME, XPA_SAMPLE_RATE_MSPS_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
assign PLL_SCAN_CLK_FD_in = 2'b11; // tie off
assign TEST_SCAN_CLK_in = 5'b11111; // tie off
assign PLL_SCAN_EN_B_FD_in = 1'b1; // tie off
assign PLL_SCAN_IN_FD_in = 2'b11; // tie off
assign PLL_SCAN_MODE_B_FD_in = 1'b1; // tie off
assign PLL_SCAN_RST_EN_FD_in = 1'b1; // tie off
assign TEST_SCAN_CTRL_in = 16'b1111111111111111; // tie off
assign TEST_SCAN_MODE_B_in = 1'b1; // tie off
assign TEST_SCAN_RESET_in = 1'b1; // tie off
assign TEST_SE_B_in = 1'b1; // tie off
assign TEST_SI_in = 300'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
SIP_HSDAC SIP_HSDAC_INST (
.SIM_DEVICE (SIM_DEVICE_REG),
.CLK_DAC (CLK_DAC_out),
.CLK_DAC_SPARE (CLK_DAC_SPARE_out),
.DOUT (DOUT_out),
.DRDY (DRDY_out),
.PLL_DMON_OUT (PLL_DMON_OUT_out),
.PLL_REFCLK_OUT (PLL_REFCLK_OUT_out),
.PLL_SCAN_OUT_B_FD (PLL_SCAN_OUT_B_FD_out),
.STATUS_COMMON (STATUS_COMMON_out),
.STATUS_DAC0 (STATUS_DAC0_out),
.STATUS_DAC1 (STATUS_DAC1_out),
.STATUS_DAC2 (STATUS_DAC2_out),
.STATUS_DAC3 (STATUS_DAC3_out),
.SYSREF_OUT_NORTH (SYSREF_OUT_NORTH_out),
.SYSREF_OUT_SOUTH (SYSREF_OUT_SOUTH_out),
.TEST_SO (TEST_SO_out),
.TEST_STATUS (TEST_STATUS_out),
.VOUT0_N (VOUT0_N_real),
.VOUT0_P (VOUT0_P_real),
.VOUT1_N (VOUT1_N_real),
.VOUT1_P (VOUT1_P_real),
.VOUT2_N (VOUT2_N_real),
.VOUT2_P (VOUT2_P_real),
.VOUT3_N (VOUT3_N_real),
.VOUT3_P (VOUT3_P_real),
.CLK_FIFO_LM (CLK_FIFO_LM_in),
.CONTROL_COMMON (CONTROL_COMMON_in),
.CONTROL_DAC0 (CONTROL_DAC0_in),
.CONTROL_DAC1 (CONTROL_DAC1_in),
.CONTROL_DAC2 (CONTROL_DAC2_in),
.CONTROL_DAC3 (CONTROL_DAC3_in),
.DAC_CLK_N (DAC_CLK_N_in),
.DAC_CLK_P (DAC_CLK_P_in),
.DADDR (DADDR_in),
.DATA_DAC0 (DATA_DAC0_in),
.DATA_DAC1 (DATA_DAC1_in),
.DATA_DAC2 (DATA_DAC2_in),
.DATA_DAC3 (DATA_DAC3_in),
.DCLK (DCLK_in),
.DEN (DEN_in),
.DI (DI_in),
.DWE (DWE_in),
.FABRIC_CLK (FABRIC_CLK_in),
.PLL_MONCLK (PLL_MONCLK_in),
.PLL_REFCLK_IN (PLL_REFCLK_IN_in),
.PLL_SCAN_CLK_FD (PLL_SCAN_CLK_FD_in),
.PLL_SCAN_EN_B_FD (PLL_SCAN_EN_B_FD_in),
.PLL_SCAN_IN_FD (PLL_SCAN_IN_FD_in),
.PLL_SCAN_MODE_B_FD (PLL_SCAN_MODE_B_FD_in),
.PLL_SCAN_RST_EN_FD (PLL_SCAN_RST_EN_FD_in),
.SYSREF_IN_NORTH (SYSREF_IN_NORTH_in),
.SYSREF_IN_SOUTH (SYSREF_IN_SOUTH_in),
.SYSREF_N (SYSREF_N_in),
.SYSREF_P (SYSREF_P_in),
.TEST_SCAN_CLK (TEST_SCAN_CLK_in),
.TEST_SCAN_CTRL (TEST_SCAN_CTRL_in),
.TEST_SCAN_MODE_B (TEST_SCAN_MODE_B_in),
.TEST_SCAN_RESET (TEST_SCAN_RESET_in),
.TEST_SE_B (TEST_SE_B_in),
.TEST_SI (TEST_SI_in),
.GSR (glblGSR)
);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(DCLK => DOUT[0]) = (100:100:100, 100:100:100);
(DCLK => DOUT[10]) = (100:100:100, 100:100:100);
(DCLK => DOUT[11]) = (100:100:100, 100:100:100);
(DCLK => DOUT[12]) = (100:100:100, 100:100:100);
(DCLK => DOUT[13]) = (100:100:100, 100:100:100);
(DCLK => DOUT[14]) = (100:100:100, 100:100:100);
(DCLK => DOUT[15]) = (100:100:100, 100:100:100);
(DCLK => DOUT[1]) = (100:100:100, 100:100:100);
(DCLK => DOUT[2]) = (100:100:100, 100:100:100);
(DCLK => DOUT[3]) = (100:100:100, 100:100:100);
(DCLK => DOUT[4]) = (100:100:100, 100:100:100);
(DCLK => DOUT[5]) = (100:100:100, 100:100:100);
(DCLK => DOUT[6]) = (100:100:100, 100:100:100);
(DCLK => DOUT[7]) = (100:100:100, 100:100:100);
(DCLK => DOUT[8]) = (100:100:100, 100:100:100);
(DCLK => DOUT[9]) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(DCLK => STATUS_COMMON[6]) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK_DAC, 0:0:0, notifier);
$period (negedge CLK_FIFO_LM, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (negedge FABRIC_CLK, 0:0:0, notifier);
$period (negedge PLL_DMON_OUT, 0:0:0, notifier);
$period (negedge PLL_MONCLK, 0:0:0, notifier);
$period (negedge PLL_REFCLK_IN, 0:0:0, notifier);
$period (negedge PLL_REFCLK_OUT, 0:0:0, notifier);
$period (posedge CLK_DAC, 0:0:0, notifier);
$period (posedge CLK_FIFO_LM, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$period (posedge FABRIC_CLK, 0:0:0, notifier);
$period (posedge PLL_DMON_OUT, 0:0:0, notifier);
$period (posedge PLL_MONCLK, 0:0:0, notifier);
$period (posedge PLL_REFCLK_IN, 0:0:0, notifier);
$period (posedge PLL_REFCLK_OUT, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, negedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]);
$setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, negedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]);
$setuphold (posedge DCLK, negedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, posedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]);
$setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, posedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]);
$setuphold (posedge DCLK, posedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay);
$setuphold (posedge FABRIC_CLK, negedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]);
$setuphold (posedge FABRIC_CLK, posedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]);
$width (negedge CLK_FIFO_LM, 0:0:0, 0, notifier);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (negedge FABRIC_CLK, 0:0:0, 0, notifier);
$width (negedge PLL_MONCLK, 0:0:0, 0, notifier);
$width (negedge PLL_REFCLK_IN, 0:0:0, 0, notifier);
$width (posedge CLK_FIFO_LM, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
$width (posedge FABRIC_CLK, 0:0:0, 0, notifier);
$width (posedge PLL_MONCLK, 0:0:0, 0, notifier);
$width (posedge PLL_REFCLK_IN, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule |
module system_zed_vga_0_0
(rgb565,
vga_r,
vga_g,
vga_b);
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
wire [15:0]rgb565;
assign vga_b[3:0] = rgb565[4:1];
assign vga_g[3:0] = rgb565[10:7];
assign vga_r[3:0] = rgb565[15:12];
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module multiplexor32a1 #(parameter Width = 3)
(coeff00,coeff01,coeff02,coeff03,coeff04,coeff05,coeff06,coeff07,coeff08,coeff09,
coeff10,coeff11,coeff12,coeff13,coeff14,coeff15,coeff16,coeff17,coeff18,coeff19,
coeff20,coeff21,coeff22,coeff23,coeff24,coeff25,coeff26,coeff27,coeff28,coeff29,
coeff30,coeff31,SEL,outMUX);
input [4:0] SEL;
input signed [Width-1:0] coeff00,coeff01,coeff02,coeff03,coeff04,coeff05,coeff06,coeff07,coeff08,coeff09,
coeff10,coeff11,coeff12,coeff13,coeff14,coeff15,coeff16,coeff17,coeff18,coeff19,
coeff20,coeff21,coeff22,coeff23,coeff24,coeff25,coeff26,coeff27,coeff28,coeff29,
coeff30,coeff31;
output reg signed [Width-1:0] outMUX;
always @*begin
case (SEL)
5'd00: outMUX <= coeff00;
5'd01: outMUX <= coeff01;
5'd02: outMUX <= coeff02;
5'd03: outMUX <= coeff03;
5'd04: outMUX <= coeff04;
5'd05: outMUX <= coeff05;
5'd06: outMUX <= coeff06;
5'd07: outMUX <= coeff07;
5'd08: outMUX <= coeff08;
5'd09: outMUX <= coeff09;
5'd10: outMUX <= coeff10;
5'd11: outMUX <= coeff11;
5'd12: outMUX <= coeff12;
5'd13: outMUX <= coeff13;
5'd14: outMUX <= coeff14;
5'd15: outMUX <= coeff15;
5'd16: outMUX <= coeff16;
5'd17: outMUX <= coeff17;
5'd18: outMUX <= coeff18;
5'd19: outMUX <= coeff19;
5'd20: outMUX <= coeff20;
5'd21: outMUX <= coeff21;
5'd22: outMUX <= coeff22;
5'd23: outMUX <= coeff23;
5'd24: outMUX <= coeff24;
5'd25: outMUX <= coeff25;
5'd26: outMUX <= coeff26;
5'd27: outMUX <= coeff27;
5'd28: outMUX <= coeff28;
5'd29: outMUX <= coeff29;
5'd30: outMUX <= coeff30;
5'd31: outMUX <= coeff31;
endcase
end
endmodule |
module soc_interface
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
/*
* AXI output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
/*
* MCB interface port 0
*/
output wire port0_cmd_clk,
output wire port0_cmd_en,
output wire [2:0] port0_cmd_instr,
output wire [5:0] port0_cmd_bl,
output wire [31:0] port0_cmd_byte_addr,
input wire port0_cmd_empty,
input wire port0_cmd_full,
output wire port0_wr_clk,
output wire port0_wr_en,
output wire [3:0] port0_wr_mask,
output wire [31:0] port0_wr_data,
input wire port0_wr_empty,
input wire port0_wr_full,
input wire port0_wr_underrun,
input wire [6:0] port0_wr_count,
input wire port0_wr_error,
output wire port0_rd_clk,
output wire port0_rd_en,
input wire [31:0] port0_rd_data,
input wire port0_rd_empty,
input wire port0_rd_full,
input wire port0_rd_overflow,
input wire [6:0] port0_rd_count,
input wire port0_rd_error,
/*
* MCB interface port 1
*/
output wire port1_cmd_clk,
output wire port1_cmd_en,
output wire [2:0] port1_cmd_instr,
output wire [5:0] port1_cmd_bl,
output wire [31:0] port1_cmd_byte_addr,
input wire port1_cmd_empty,
input wire port1_cmd_full,
output wire port1_wr_clk,
output wire port1_wr_en,
output wire [3:0] port1_wr_mask,
output wire [31:0] port1_wr_data,
input wire port1_wr_empty,
input wire port1_wr_full,
input wire port1_wr_underrun,
input wire [6:0] port1_wr_count,
input wire port1_wr_error,
output wire port1_rd_clk,
output wire port1_rd_en,
input wire [31:0] port1_rd_data,
input wire port1_rd_empty,
input wire port1_rd_full,
input wire port1_rd_overflow,
input wire [6:0] port1_rd_count,
input wire port1_rd_error,
/*
* Status
*/
output wire busy
);
// state register
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_ADDR = 3'd1,
STATE_MCB_READ = 3'd2,
STATE_MCB_WRITE = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
reg inc_addr_reg = 0, inc_addr_next;
reg rd_empty;
reg [31:0] rd_data;
reg cmd_en;
reg wr_en;
reg rd_en;
reg [7:0] cmd_reg = 0, cmd_next;
reg [31:0] addr_reg = 0, addr_next;
reg [31:0] data_reg = 0, data_next;
reg data_valid_reg = 0, data_valid_next;
reg [3:0] bank_reg = 0, bank_next;
reg [1:0] byte_cnt_reg = 0, byte_cnt_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
reg [7:0] output_axis_tdata_reg = 0, output_axis_tdata_next;
reg output_axis_tvalid_reg = 0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 0, output_axis_tlast_next;
reg port0_cmd_en_reg = 0, port0_cmd_en_next;
reg port1_cmd_en_reg = 0, port1_cmd_en_next;
reg [2:0] port_cmd_instr_reg = 0, port_cmd_instr_next;
reg [5:0] port_cmd_bl_reg = 0, port_cmd_bl_next;
reg [31:0] port_cmd_byte_addr_reg = 0, port_cmd_byte_addr_next;
reg port0_wr_en_reg = 0, port0_wr_en_next;
reg port1_wr_en_reg = 0, port1_wr_en_next;
reg [3:0] port_wr_mask_reg = 0, port_wr_mask_next;
reg [31:0] port_wr_data_reg = 0, port_wr_data_next;
reg port0_rd_en_reg = 0, port0_rd_en_next;
reg port1_rd_en_reg = 0, port1_rd_en_next;
reg busy_reg = 0;
assign input_axis_tready = input_axis_tready_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign port0_cmd_clk = clk;
assign port0_cmd_en = port0_cmd_en_reg;
assign port0_cmd_instr = port_cmd_instr_reg;
assign port0_cmd_bl = port_cmd_bl_reg;
assign port0_cmd_byte_addr = port_cmd_byte_addr_reg;
assign port0_wr_clk = clk;
assign port0_wr_en = port0_wr_en_reg;
assign port0_wr_mask = port_wr_mask_reg;
assign port0_wr_data = port_wr_data_reg;
assign port0_rd_clk = clk;
assign port0_rd_en = port0_rd_en_reg;
assign port1_cmd_clk = clk;
assign port1_cmd_en = port1_cmd_en_reg;
assign port1_cmd_instr = port_cmd_instr_reg;
assign port1_cmd_bl = port_cmd_bl_reg;
assign port1_cmd_byte_addr = port_cmd_byte_addr_reg;
assign port1_wr_clk = clk;
assign port1_wr_en = port1_wr_en_reg;
assign port1_wr_mask = port_wr_mask_reg;
assign port1_wr_data = port_wr_data_reg;
assign port1_rd_clk = clk;
assign port1_rd_en = port1_rd_en_reg;
assign busy = busy_reg;
// registers for timing
reg port0_rd_empty_reg = 0;
reg [31:0] port0_rd_data_reg = 0;
reg port1_rd_empty_reg = 0;
reg [31:0] port1_rd_data_reg = 0;
always @(posedge clk) begin
port0_rd_empty_reg <= port0_rd_empty;
port0_rd_data_reg <= port0_rd_data;
port1_rd_empty_reg <= port1_rd_empty;
port1_rd_data_reg <= port1_rd_data;
end
// read data mux
always @(posedge clk) begin
case (bank_reg)
4'd0: begin
rd_empty <= port0_rd_empty_reg;
rd_data <= port0_rd_data_reg;
end
4'd1: begin
rd_empty <= port1_rd_empty_reg;
rd_data <= port1_rd_data_reg;
end
default: begin
rd_empty <= 0;
rd_data <= 0;
end
endcase
end
always @* begin
state_next = 0;
inc_addr_next = 0;
cmd_en = 0;
wr_en = 0;
rd_en = 0;
cmd_next = cmd_reg;
if (inc_addr_reg) begin
port_cmd_byte_addr_next = {port_cmd_byte_addr_reg[31:2], 2'b00} + 4;
end else begin
port_cmd_byte_addr_next = port_cmd_byte_addr_reg;
end
data_next = data_reg;
data_valid_next = data_valid_reg;
bank_next = bank_reg;
byte_cnt_next = byte_cnt_reg;
input_axis_tready_next = 0;
output_axis_tdata_next = output_axis_tdata_reg;
output_axis_tvalid_next = output_axis_tvalid_reg & ~output_axis_tready;
output_axis_tlast_next = output_axis_tlast_reg;
port0_cmd_en_next = 0;
port1_cmd_en_next = 0;
port_cmd_instr_next = port_cmd_instr_reg;
port_cmd_bl_next = port_cmd_bl_reg;
port0_wr_en_next = 0;
port1_wr_en_next = 0;
port_wr_mask_next = port_wr_mask_reg;
port_wr_data_next = port_wr_data_reg;
port0_rd_en_next = 0;
port1_rd_en_next = 0;
case (state_reg)
STATE_IDLE: begin
input_axis_tready_next = 1;
rd_en = 1;
data_valid_next = 0;
if (input_axis_tready & input_axis_tvalid) begin
// get command
cmd_next = input_axis_tdata;
if (input_axis_tlast) begin
// early end of frame
state_next = STATE_IDLE;
end else if (cmd_next[7:4] == 4'hA || cmd_next[7:4] == 4'hB) begin
// read or write command
bank_next = cmd_next[3:0];
byte_cnt_next = 0;
state_next = STATE_READ_ADDR;
if (bank_next == 0 || bank_next == 1) begin
state_next = STATE_READ_ADDR;
end else begin
// invalid bank
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_ADDR: begin
input_axis_tready_next = 1;
if (input_axis_tready & input_axis_tvalid) begin
// read address byte (MSB first)
byte_cnt_next = byte_cnt_reg + 1;
case (byte_cnt_reg)
2'd0: port_cmd_byte_addr_next[31:24] = input_axis_tdata;
2'd1: port_cmd_byte_addr_next[23:16] = input_axis_tdata;
2'd2: port_cmd_byte_addr_next[15: 8] = input_axis_tdata;
2'd3: begin
port_cmd_byte_addr_next[ 7: 0] = {input_axis_tdata[7:2], 2'b00};
byte_cnt_next = input_axis_tdata[1:0];
end
endcase
if (input_axis_tlast) begin
// early end of frame
state_next = STATE_IDLE;
end else if (byte_cnt_reg == 3) begin
// last address byte, process command
if (cmd_reg[7:4] == 4'hA) begin
// read command
// initiate read, length 1
port_cmd_instr_next = 3'b001;
port_cmd_bl_next = 5'd0;
cmd_en = 1;
inc_addr_next = 1;
state_next = STATE_MCB_READ;
end else if (cmd_reg[7:4] == 4'hB) begin
// write command
case (byte_cnt_next[1:0])
2'd0: port_wr_mask_next = 4'b0000;
2'd1: port_wr_mask_next = 4'b0001;
2'd2: port_wr_mask_next = 4'b0011;
2'd3: port_wr_mask_next = 4'b0111;
endcase
data_next = 0;
state_next = STATE_MCB_WRITE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_READ_ADDR;
end
end else begin
state_next = STATE_READ_ADDR;
end
end
STATE_MCB_READ: begin
input_axis_tready_next = 1;
if (!output_axis_tvalid & data_valid_reg) begin
// send start flag
output_axis_tdata_next = 1;
output_axis_tvalid_next = 1;
output_axis_tlast_next = 0;
end else if (output_axis_tready & data_valid_reg) begin
// send read data
byte_cnt_next = byte_cnt_reg + 1;
output_axis_tvalid_next = 1;
case (byte_cnt_reg)
2'd0: output_axis_tdata_next = data_reg[ 7: 0];
2'd1: output_axis_tdata_next = data_reg[15: 8];
2'd2: output_axis_tdata_next = data_reg[23:16];
2'd3: output_axis_tdata_next = data_reg[31:24];
endcase
// invalidate data reg on byte count rollover
if (byte_cnt_reg == 3) begin
data_valid_next = 0;
byte_cnt_next = 0;
end
end
state_next = STATE_MCB_READ;
if (input_axis_tvalid & input_axis_tlast) begin
// send zero with last set on frame end
output_axis_tvalid_next = 1;
output_axis_tlast_next = 1;
output_axis_tdata_next = 0;
state_next = STATE_IDLE;
end
if (!data_valid_next & !rd_empty) begin
// read data word into register
data_next = rd_data;
data_valid_next = 1;
// initiate a new read
port_cmd_instr_next = 3'b001;
port_cmd_bl_next = 5'd0;
cmd_en = 1;
rd_en = 1;
inc_addr_next = 1;
end
end
STATE_MCB_WRITE: begin
input_axis_tready_next = 1;
if (input_axis_tready & input_axis_tvalid) begin
// got data byte
byte_cnt_next = byte_cnt_reg + 1;
case (byte_cnt_reg)
2'd0: port_wr_data_next[ 7: 0] = input_axis_tdata;
2'd1: port_wr_data_next[15: 8] = input_axis_tdata;
2'd2: port_wr_data_next[23:16] = input_axis_tdata;
2'd3: port_wr_data_next[31:24] = input_axis_tdata;
endcase
if (input_axis_tlast || byte_cnt_reg == 3) begin
// end of frame or end of word
// calculate mask
case (byte_cnt_reg[1:0])
2'd0: port_wr_mask_next = port_wr_mask_next | 4'b1110;
2'd1: port_wr_mask_next = port_wr_mask_next | 4'b1100;
2'd2: port_wr_mask_next = port_wr_mask_next | 4'b1000;
2'd3: port_wr_mask_next = port_wr_mask_next | 4'b0000;
endcase
// write, burst length 1
port_cmd_instr_next = 3'b000;
port_cmd_bl_next = 5'd0;
cmd_en = 1;
wr_en = 1;
// increment address
inc_addr_next = 1;
if (input_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_MCB_WRITE;
end
end else begin
state_next = STATE_MCB_WRITE;
end
end else begin
state_next = STATE_MCB_WRITE;
end
end
STATE_WAIT_LAST: begin
input_axis_tready_next = 1;
if (input_axis_tready & input_axis_tvalid & input_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
// command demux
case (bank_reg)
4'd0: begin
port0_cmd_en_next = cmd_en;
port0_wr_en_next = wr_en;
port0_rd_en_next = rd_en;
end
4'd1: begin
port1_cmd_en_next = cmd_en;
port1_wr_en_next = wr_en;
port1_rd_en_next = rd_en;
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
inc_addr_reg <= 0;
cmd_reg <= 0;
addr_reg <= 0;
data_reg <= 0;
data_valid_reg <= 0;
bank_reg <= 0;
byte_cnt_reg <= 0;
input_axis_tready_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
port0_cmd_en_reg <= 0;
port1_cmd_en_reg <= 0;
port_cmd_instr_reg <= 0;
port_cmd_bl_reg <= 0;
port_cmd_byte_addr_reg <= 0;
port0_wr_en_reg <= 0;
port1_wr_en_reg <= 0;
port_wr_mask_reg <= 0;
port_wr_data_reg <= 0;
port0_rd_en_reg <= 0;
port1_rd_en_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
inc_addr_reg <= inc_addr_next;
cmd_reg <= cmd_next;
addr_reg <= addr_next;
data_reg <= data_next;
data_valid_reg <= data_valid_next;
bank_reg <= bank_next;
byte_cnt_reg <= byte_cnt_next;
input_axis_tready_reg <= input_axis_tready_next;
output_axis_tdata_reg <= output_axis_tdata_next;
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tlast_reg <= output_axis_tlast_next;
port0_cmd_en_reg <= port0_cmd_en_next;
port1_cmd_en_reg <= port1_cmd_en_next;
port_cmd_instr_reg <= port_cmd_instr_next;
port_cmd_bl_reg <= port_cmd_bl_next;
port_cmd_byte_addr_reg <= port_cmd_byte_addr_next;
port0_wr_en_reg <= port0_wr_en_next;
port1_wr_en_reg <= port1_wr_en_next;
port_wr_mask_reg <= port_wr_mask_next;
port_wr_data_reg <= port_wr_data_next;
port0_rd_en_reg <= port0_rd_en_next;
port1_rd_en_reg <= port1_rd_en_next;
busy_reg <= state_next != STATE_IDLE;
end
end
endmodule |
module fifo_async_103x32(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[102:0],wr_en,rd_en,dout[102:0],full,empty,prog_full" */;
input rst;
input wr_clk;
input rd_clk;
input [102:0]din;
input wr_en;
input rd_en;
output [102:0]dout;
output full;
output empty;
output prog_full;
endmodule |
module eg_cnt(
input clk,
input clk_en,
input rst,
input [14:0] eg_cnt,
input [2:0] state_IV,
input [5:0] rate_IV,
output reg [2:0] state_V,
output reg [5:0] rate_V,
output [2:0] cnt_V,
output reg sum_up
);
localparam ATTACK=3'd0, DECAY1=3'd1, DECAY2=3'd2, RELEASE=3'd7, HOLD=3'd3;
wire [2:0] cnt_out;
assign cnt_V = cnt_out;
reg lsb;
reg [2:0] cnt_in;
reg [3:0] mux_sel;
always @(*) begin
mux_sel = (state_IV == ATTACK && rate_IV[5:2]!=4'hf) ? (rate_IV[5:2]+4'd1): rate_IV[5:2];
case( mux_sel )
4'h0: lsb = eg_cnt[12];
4'h1: lsb = eg_cnt[11];
4'h2: lsb = eg_cnt[10];
4'h3: lsb = eg_cnt[ 9];
4'h4: lsb = eg_cnt[ 8];
4'h5: lsb = eg_cnt[ 7];
4'h6: lsb = eg_cnt[ 6];
4'h7: lsb = eg_cnt[ 5];
4'h8: lsb = eg_cnt[ 4];
4'h9: lsb = eg_cnt[ 3];
4'ha: lsb = eg_cnt[ 2];
4'hb: lsb = eg_cnt[ 1];
default: lsb = eg_cnt[ 0];
endcase
cnt_in =lsb!=cnt_out ? (cnt_out+3'd1) : cnt_out;
end
always @(posedge clk) if( clk_en ) begin
if( rst ) begin
state_V <= RELEASE;
rate_V <= 6'h1F; // should it be 6'h3F? TODO
//cnt_V<= 3'd0;
end
else begin
state_V <= state_IV;
rate_V <= rate_IV;
end
end
jt12_sh/*_rst*/ #( .width(3), .stages(24) ) u_cntsh(
.clk ( clk ),
.clk_en ( clk_en ),
// .rst ( rst ),
.din ( cnt_in ),
.drop ( cnt_out )
);
always @(posedge clk)
if( clk_en )
sum_up <= lsb!=cnt_out;
endmodule |
module system_debounce_0_0
(clk,
signal_in,
signal_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input signal_in;
output signal_out;
wire clk;
wire signal_in;
wire signal_out;
system_debounce_0_0_debounce U0
(.clk(clk),
.signal_in(signal_in),
.signal_out(signal_out));
endmodule |
module system_debounce_0_0_debounce
(signal_out,
clk,
signal_in);
output signal_out;
input clk;
input signal_in;
wire \c[0]_i_3_n_0 ;
wire \c[0]_i_4_n_0 ;
wire \c[0]_i_5_n_0 ;
wire \c[0]_i_6_n_0 ;
wire \c[12]_i_2_n_0 ;
wire \c[12]_i_3_n_0 ;
wire \c[12]_i_4_n_0 ;
wire \c[12]_i_5_n_0 ;
wire \c[16]_i_2_n_0 ;
wire \c[16]_i_3_n_0 ;
wire \c[16]_i_4_n_0 ;
wire \c[16]_i_5_n_0 ;
wire \c[20]_i_2_n_0 ;
wire \c[20]_i_3_n_0 ;
wire \c[20]_i_4_n_0 ;
wire \c[20]_i_5_n_0 ;
wire \c[4]_i_2_n_0 ;
wire \c[4]_i_3_n_0 ;
wire \c[4]_i_4_n_0 ;
wire \c[4]_i_5_n_0 ;
wire \c[8]_i_2_n_0 ;
wire \c[8]_i_3_n_0 ;
wire \c[8]_i_4_n_0 ;
wire \c[8]_i_5_n_0 ;
wire [23:0]c_reg;
wire \c_reg[0]_i_2_n_0 ;
wire \c_reg[0]_i_2_n_1 ;
wire \c_reg[0]_i_2_n_2 ;
wire \c_reg[0]_i_2_n_3 ;
wire \c_reg[0]_i_2_n_4 ;
wire \c_reg[0]_i_2_n_5 ;
wire \c_reg[0]_i_2_n_6 ;
wire \c_reg[0]_i_2_n_7 ;
wire \c_reg[12]_i_1_n_0 ;
wire \c_reg[12]_i_1_n_1 ;
wire \c_reg[12]_i_1_n_2 ;
wire \c_reg[12]_i_1_n_3 ;
wire \c_reg[12]_i_1_n_4 ;
wire \c_reg[12]_i_1_n_5 ;
wire \c_reg[12]_i_1_n_6 ;
wire \c_reg[12]_i_1_n_7 ;
wire \c_reg[16]_i_1_n_0 ;
wire \c_reg[16]_i_1_n_1 ;
wire \c_reg[16]_i_1_n_2 ;
wire \c_reg[16]_i_1_n_3 ;
wire \c_reg[16]_i_1_n_4 ;
wire \c_reg[16]_i_1_n_5 ;
wire \c_reg[16]_i_1_n_6 ;
wire \c_reg[16]_i_1_n_7 ;
wire \c_reg[20]_i_1_n_1 ;
wire \c_reg[20]_i_1_n_2 ;
wire \c_reg[20]_i_1_n_3 ;
wire \c_reg[20]_i_1_n_4 ;
wire \c_reg[20]_i_1_n_5 ;
wire \c_reg[20]_i_1_n_6 ;
wire \c_reg[20]_i_1_n_7 ;
wire \c_reg[4]_i_1_n_0 ;
wire \c_reg[4]_i_1_n_1 ;
wire \c_reg[4]_i_1_n_2 ;
wire \c_reg[4]_i_1_n_3 ;
wire \c_reg[4]_i_1_n_4 ;
wire \c_reg[4]_i_1_n_5 ;
wire \c_reg[4]_i_1_n_6 ;
wire \c_reg[4]_i_1_n_7 ;
wire \c_reg[8]_i_1_n_0 ;
wire \c_reg[8]_i_1_n_1 ;
wire \c_reg[8]_i_1_n_2 ;
wire \c_reg[8]_i_1_n_3 ;
wire \c_reg[8]_i_1_n_4 ;
wire \c_reg[8]_i_1_n_5 ;
wire \c_reg[8]_i_1_n_6 ;
wire \c_reg[8]_i_1_n_7 ;
wire clear;
wire clk;
wire signal_in;
wire signal_out;
wire signal_out_i_1_n_0;
wire signal_out_i_2_n_0;
wire signal_out_i_3_n_0;
wire signal_out_i_4_n_0;
wire signal_out_i_5_n_0;
wire [3:3]\NLW_c_reg[20]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\c[0]_i_1
(.I0(signal_in),
.O(clear));
LUT1 #(
.INIT(2'h2))
\c[0]_i_3
(.I0(c_reg[3]),
.O(\c[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[0]_i_4
(.I0(c_reg[2]),
.O(\c[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[0]_i_5
(.I0(c_reg[1]),
.O(\c[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\c[0]_i_6
(.I0(c_reg[0]),
.O(\c[0]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_2
(.I0(c_reg[15]),
.O(\c[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_3
(.I0(c_reg[14]),
.O(\c[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_4
(.I0(c_reg[13]),
.O(\c[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_5
(.I0(c_reg[12]),
.O(\c[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_2
(.I0(c_reg[19]),
.O(\c[16]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_3
(.I0(c_reg[18]),
.O(\c[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_4
(.I0(c_reg[17]),
.O(\c[16]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_5
(.I0(c_reg[16]),
.O(\c[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_2
(.I0(c_reg[23]),
.O(\c[20]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_3
(.I0(c_reg[22]),
.O(\c[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_4
(.I0(c_reg[21]),
.O(\c[20]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_5
(.I0(c_reg[20]),
.O(\c[20]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_2
(.I0(c_reg[7]),
.O(\c[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_3
(.I0(c_reg[6]),
.O(\c[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_4
(.I0(c_reg[5]),
.O(\c[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_5
(.I0(c_reg[4]),
.O(\c[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_2
(.I0(c_reg[11]),
.O(\c[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_3
(.I0(c_reg[10]),
.O(\c[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_4
(.I0(c_reg[9]),
.O(\c[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_5
(.I0(c_reg[8]),
.O(\c[8]_i_5_n_0 ));
FDRE \c_reg[0]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_7 ),
.Q(c_reg[0]),
.R(clear));
CARRY4 \c_reg[0]_i_2
(.CI(1'b0),
.CO({\c_reg[0]_i_2_n_0 ,\c_reg[0]_i_2_n_1 ,\c_reg[0]_i_2_n_2 ,\c_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\c_reg[0]_i_2_n_4 ,\c_reg[0]_i_2_n_5 ,\c_reg[0]_i_2_n_6 ,\c_reg[0]_i_2_n_7 }),
.S({\c[0]_i_3_n_0 ,\c[0]_i_4_n_0 ,\c[0]_i_5_n_0 ,\c[0]_i_6_n_0 }));
FDRE \c_reg[10]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_5 ),
.Q(c_reg[10]),
.R(clear));
FDRE \c_reg[11]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_4 ),
.Q(c_reg[11]),
.R(clear));
FDRE \c_reg[12]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_7 ),
.Q(c_reg[12]),
.R(clear));
CARRY4 \c_reg[12]_i_1
(.CI(\c_reg[8]_i_1_n_0 ),
.CO({\c_reg[12]_i_1_n_0 ,\c_reg[12]_i_1_n_1 ,\c_reg[12]_i_1_n_2 ,\c_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[12]_i_1_n_4 ,\c_reg[12]_i_1_n_5 ,\c_reg[12]_i_1_n_6 ,\c_reg[12]_i_1_n_7 }),
.S({\c[12]_i_2_n_0 ,\c[12]_i_3_n_0 ,\c[12]_i_4_n_0 ,\c[12]_i_5_n_0 }));
FDRE \c_reg[13]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_6 ),
.Q(c_reg[13]),
.R(clear));
FDRE \c_reg[14]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_5 ),
.Q(c_reg[14]),
.R(clear));
FDRE \c_reg[15]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_4 ),
.Q(c_reg[15]),
.R(clear));
FDRE \c_reg[16]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_7 ),
.Q(c_reg[16]),
.R(clear));
CARRY4 \c_reg[16]_i_1
(.CI(\c_reg[12]_i_1_n_0 ),
.CO({\c_reg[16]_i_1_n_0 ,\c_reg[16]_i_1_n_1 ,\c_reg[16]_i_1_n_2 ,\c_reg[16]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[16]_i_1_n_4 ,\c_reg[16]_i_1_n_5 ,\c_reg[16]_i_1_n_6 ,\c_reg[16]_i_1_n_7 }),
.S({\c[16]_i_2_n_0 ,\c[16]_i_3_n_0 ,\c[16]_i_4_n_0 ,\c[16]_i_5_n_0 }));
FDRE \c_reg[17]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_6 ),
.Q(c_reg[17]),
.R(clear));
FDRE \c_reg[18]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_5 ),
.Q(c_reg[18]),
.R(clear));
FDRE \c_reg[19]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_4 ),
.Q(c_reg[19]),
.R(clear));
FDRE \c_reg[1]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_6 ),
.Q(c_reg[1]),
.R(clear));
FDRE \c_reg[20]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_7 ),
.Q(c_reg[20]),
.R(clear));
CARRY4 \c_reg[20]_i_1
(.CI(\c_reg[16]_i_1_n_0 ),
.CO({\NLW_c_reg[20]_i_1_CO_UNCONNECTED [3],\c_reg[20]_i_1_n_1 ,\c_reg[20]_i_1_n_2 ,\c_reg[20]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[20]_i_1_n_4 ,\c_reg[20]_i_1_n_5 ,\c_reg[20]_i_1_n_6 ,\c_reg[20]_i_1_n_7 }),
.S({\c[20]_i_2_n_0 ,\c[20]_i_3_n_0 ,\c[20]_i_4_n_0 ,\c[20]_i_5_n_0 }));
FDRE \c_reg[21]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_6 ),
.Q(c_reg[21]),
.R(clear));
FDRE \c_reg[22]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_5 ),
.Q(c_reg[22]),
.R(clear));
FDRE \c_reg[23]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_4 ),
.Q(c_reg[23]),
.R(clear));
FDRE \c_reg[2]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_5 ),
.Q(c_reg[2]),
.R(clear));
FDRE \c_reg[3]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_4 ),
.Q(c_reg[3]),
.R(clear));
FDRE \c_reg[4]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_7 ),
.Q(c_reg[4]),
.R(clear));
CARRY4 \c_reg[4]_i_1
(.CI(\c_reg[0]_i_2_n_0 ),
.CO({\c_reg[4]_i_1_n_0 ,\c_reg[4]_i_1_n_1 ,\c_reg[4]_i_1_n_2 ,\c_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[4]_i_1_n_4 ,\c_reg[4]_i_1_n_5 ,\c_reg[4]_i_1_n_6 ,\c_reg[4]_i_1_n_7 }),
.S({\c[4]_i_2_n_0 ,\c[4]_i_3_n_0 ,\c[4]_i_4_n_0 ,\c[4]_i_5_n_0 }));
FDRE \c_reg[5]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_6 ),
.Q(c_reg[5]),
.R(clear));
FDRE \c_reg[6]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_5 ),
.Q(c_reg[6]),
.R(clear));
FDRE \c_reg[7]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_4 ),
.Q(c_reg[7]),
.R(clear));
FDRE \c_reg[8]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_7 ),
.Q(c_reg[8]),
.R(clear));
CARRY4 \c_reg[8]_i_1
(.CI(\c_reg[4]_i_1_n_0 ),
.CO({\c_reg[8]_i_1_n_0 ,\c_reg[8]_i_1_n_1 ,\c_reg[8]_i_1_n_2 ,\c_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[8]_i_1_n_4 ,\c_reg[8]_i_1_n_5 ,\c_reg[8]_i_1_n_6 ,\c_reg[8]_i_1_n_7 }),
.S({\c[8]_i_2_n_0 ,\c[8]_i_3_n_0 ,\c[8]_i_4_n_0 ,\c[8]_i_5_n_0 }));
FDRE \c_reg[9]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_6 ),
.Q(c_reg[9]),
.R(clear));
LUT5 #(
.INIT(32'h80000000))
signal_out_i_1
(.I0(signal_out_i_2_n_0),
.I1(signal_out_i_3_n_0),
.I2(signal_out_i_4_n_0),
.I3(c_reg[0]),
.I4(signal_out_i_5_n_0),
.O(signal_out_i_1_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_2
(.I0(c_reg[3]),
.I1(c_reg[4]),
.I2(c_reg[1]),
.I3(c_reg[2]),
.I4(c_reg[6]),
.I5(c_reg[5]),
.O(signal_out_i_2_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_3
(.I0(c_reg[21]),
.I1(c_reg[22]),
.I2(c_reg[19]),
.I3(c_reg[20]),
.I4(signal_in),
.I5(c_reg[23]),
.O(signal_out_i_3_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_4
(.I0(c_reg[15]),
.I1(c_reg[16]),
.I2(c_reg[13]),
.I3(c_reg[14]),
.I4(c_reg[18]),
.I5(c_reg[17]),
.O(signal_out_i_4_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_5
(.I0(c_reg[9]),
.I1(c_reg[10]),
.I2(c_reg[7]),
.I3(c_reg[8]),
.I4(c_reg[12]),
.I5(c_reg[11]),
.O(signal_out_i_5_n_0));
FDRE signal_out_reg
(.C(clk),
.CE(1'b1),
.D(signal_out_i_1_n_0),
.Q(signal_out),
.R(1'b0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
// initialize every entry
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule |
module ZedboardOLED_v1_0 #
(
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
)
(
// Interface with the SSD1306 starts here
output wire SDIN,
output wire SCLK,
output wire DC,
output wire RES,
output wire VBAT,
output wire VDD,
// Interface with the SSD1306 ends here
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
ZedboardOLED_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) ZedboardOLED_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.SDIN(SDIN),
.SCLK(SCLK),
.DC(DC),
.RES(RES),
.VBAT(VBAT),
.VDD(VDD),
.S_AXI_RREADY(s00_axi_rready)
);
endmodule |
module sky130_fd_sc_hs__o32a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 or0_out ;
wire B1 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule |
module bsg_nonsynth_mem_1rw_sync_assoc
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
)
(
input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_p-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
wire unused = reset_i;
// associative array
//
`ifdef VERILATOR
// Verilator 4.024 supports associative array, but not wildcard indexed.
logic [width_p-1:0] mem [longint];
`else
logic [width_p-1:0] mem [*];
`endif
// write logic
//
always_ff @ (posedge clk_i) begin
if (~reset_i & v_i & w_i) begin
mem[addr_i] <= data_i;
end
end
// read logic
//
always_ff @ (posedge clk_i) begin
if (~reset_i & v_i & ~w_i) begin
data_o <= mem[addr_i];
end
end
endmodule |
module bsg_trace_rom #(parameter `BSG_INV_PARAM(width_p), parameter `BSG_INV_PARAM(addr_width_p))
(input [addr_width_p-1:0] addr_i
,output logic [width_p-1:0] data_o
);
always_comb case(addr_i)
// ### test params #########
// #
// # payload = 17
// # len_width = 2
// # y = 2
// # x = 2
// #
// # padding = 17
// # flit = 6
// #
// ###########################
// # send packet
0: data_o = width_p ' (27'b0001_11100000110000101_10_00_11); // 0x0F06163
// # recv flits
1: data_o = width_p ' (27'b0010_000000000000000_01100011); // 0x1000063
2: data_o = width_p ' (27'b0010_000000000000000_01100001); // 0x1000061
3: data_o = width_p ' (27'b0010_000000000000000_01110000); // 0x1000070
// # send packet
4: data_o = width_p ' (27'b0001_00001100110011111_01_11_01); // 0x08667DD
// # recv flits
5: data_o = width_p ' (27'b0010_000000000000000_11011101); // 0x10000DD
6: data_o = width_p ' (27'b0010_000000000000000_01100111); // 0x1000067
// # send packet
7: data_o = width_p ' (27'b0001_00001100110011111_00_11_01); // 0x08667CD
// # recv flits
8: data_o = width_p ' (27'b0010_000000000000000_11001101); // 0x10000CD
// # done
9: data_o = width_p ' (27'b0011_00000000000000000_000000); // 0x1800000
default: data_o = 'X;
endcase
endmodule |
module RAMB16_S9_S9(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [10:0] ADDRA,
input [7:0] DIA,
input DIPA,
// output [3:0] DOPA,
output [7:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [10:0] ADDRB,
input [7:0] DIB,
input DIPB,
// output [3:0] DOPB,
output [7:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(8),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(DIPA),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(DIPB),.DOB(DOB));
endmodule |
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module bd_350b_slot_2_w_0 (
In0,
In1,
In2,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
input wire [0 : 0] In2;
output wire [2 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(3),
.NUM_PORTS(3)
) inst (
.In0(In0),
.In1(In1),
.In2(In2),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule |
module sky130_fd_sc_lp__and2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module sky130_fd_sc_ms__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module bram_tdp #(
parameter DATA = 32,
parameter ADDR = 10
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule |
module
input [15:0] DQX_In;
input flash_data_fifo_empty;
output reg rd_flash_datafifo_en;
output reg clear_flash_datafifo;
(*IOB="FALSE"*)output reg during_read_data;
output reg [7:0] DQX_Out;
// output reg DQS_Out;
output reg DQS_Start;
//Ports with Chips
input [7:0] RB_L;
output reg [7:0] CE_L;
output CLE_H;
output ALE_H;
output reg WP_L;
//ͬ²½Òì²½¸´ÓÃÐźÅ
output WE_Lorclk;//output WE_L(Asynchronous),clk(synchronous)
output RE_LorWR_L;//output RE_L£¨Asynchronous),W/R#(synchronous)
//******Asynchornous interface reset all targets parameter definition
//reset the 4 targets
parameter POWER_UP = 4'h0;
parameter TARGET_SELECTION = 4'h1;
parameter PREPARE_RESET_TARGET = 4'h2;
parameter RESET_TARGET_COMMAND_1 = 4'h3;
parameter RESET_WAIT_FOR_0 = 4'h4;
parameter RESET_WAIT_FOR_1 = 4'h5;
//end of reset the 4 targets
parameter RESET_CHIP_END = 4'h6;
//Active synchronous interface
parameter ACTIVESYN_CMD = 4'h7;
parameter ACTIVESYN_ADDR = 4'h8;
parameter ACTIVESYN_WAITTADL = 4'h9;
parameter ACTIVESYN_DATAMODE = 4'ha;
parameter ACTIVESYN_DATA00 = 4'hb;
parameter ACTIVESYN_WAITRB0 = 4'hc;
parameter ACTIVESYN_WAITRB1 = 4'hd;
parameter ACTIVESYN_END = 4'he;
//define toggle states
parameter TOGGLE_WAIT = 'h0;
parameter TOGGLECLR = 'h1;
parameter TOGGLE_CE_EN = 'h2;
parameter TOGGLE1 = 'h3;
parameter TOGGLEADD = 'h4;
parameter TOGGLE2 = 'h5;
parameter TOGGLE_DONE = 'h6;
//**********************************Synchronous interfaces operation***//
parameter SYN_WAIT4SYNACTIVE = 'h00;
parameter SYN_STANDBY = 'h01;
parameter SYN_BUSIDLE = 'h02;
//read states
parameter READ_PAGE_COMMAND_1 = 'h03;//·¢ËͶÁÒ³²Ù×÷µÄµÚÒ»¸öÃüÁî00h£¬Ò»¸öÖÜÆÚ
parameter READ_PAGE_ADDRESS_00 = 'h04;//·¢ËÍÄ¿±êÒ³µØÖ·µÄÒ³ÄÚµØÖ·0000h£¬Á½¸öÖÜÆÚ
parameter READ_PAGE_ADDRESS_3CYCLE = 'h05;//·¢ËÍÄ¿±êÒ³µØÖ·µÄҳƫÒƺͿéÆ«ÒÆ£¬3¸öÖÜÆÚ
parameter READ_PAGE_COMMAND_2 = 'h06;//·¢ËͶÁÒ³²Ù×÷µÄµÚ¶þ¸öÃüÁî30h£¬Ò»¸öÖÜÆÚ
parameter READ_PAGE_WAIT_FOR_0 = 'h07;//µÈ´ýflashµÄrbÐźÅÀµÍ
//write states
parameter WRITE_PAGE_COMMAND_1 = 'h08;//
parameter WRITE_PAGE_ADDRESS_00 = 'h09;//
parameter WRITE_PAGE_ADDRESS_3CYCELE = 'h0a;//
parameter WRITE_PAGE_DELAY70NS = 'h0b;
parameter WRITE_PAGE_DATA = 'h0c;//
parameter WRITE_PAGE_COMMAND_2 = 'h0d;//
parameter WRITE_PAGE_WAIT_FOR_0 = 'h0e;//
//erase states
parameter ERASE_BLOCK_COMMAND_1 = 'h0f;//
parameter ERASE_BLOCK_ADDRESS_3CYCLES = 'h10;//
parameter ERASE_BLOCK_COMMAND_2 = 'h11;//
parameter ERASE_BLOCK_WAIT_FOR_0 = 'h12;//
parameter READ_PAGE_WAIT = 'h13;
parameter READ_PAGE_DATA_OUT = 'h14;
parameter READ_DELAY_TRHW120 = 'h15;
parameter READ_PAGE_END = 'h16;//¶ÁÒ³²Ù×÷Íê±Ï
// Command and Address issure machine state definition
parameter CA_PREPARE = 'd0;
parameter CA_WAIT = 'd1;
parameter CA_ISSURE = 'd2;
parameter CA_COMPLETE = 'd3;
parameter CA_END = 'd14;
//DDR dataout
parameter DDR_DATAOUT_EN = 'd4;
parameter DDR_DATAOUT_PREPARE ='d5;
parameter DDR_MODE = 'd6;
parameter DDR_DATAOUT_ALECLE_HOLD = 'd7;
parameter DDR_DATAOUT_END = 'd8;
//DDR datain
parameter DDR_DATAIN_EN = 'd9;
parameter DATAIN_PREPARE = 'd10;
parameter DATAIN_MODE = 'd11;
parameter DDR_DATAIN_LAST2 = 'd12;
parameter DDR_DATAIN_END = 'd13;
//define command
parameter RESET_COMMAND_1 = 'hff;
parameter SET_FEATURES = 'hef;
parameter READ_MODE = 'h00;
parameter READ_PAGE = 'h30;
parameter PROGRAM_MODE = 'h80;
parameter PROGRAM_PAGE = 'h10;
parameter ERASE_BLOCK_CMD1 ='h60;
parameter ERASE_BLOCK_CMDQUEUE = 'hd1;
parameter ERASE_BLOCK_CMDEND = 'hd0;
// Command and Address issure machine state regs declarison
reg [3:0]Syn_CA_currentstate,Syn_CA_nextstate;
reg [3:0]CA_Control_Signal0,CA_Control_Signal1,CA_Control_Signal2;
reg CA_Start;
reg CA_Done;
// DDR Dataout from chips
reg Dataout_Start;
reg Dataout_Done;
//DDR Datain
//reg DQS_Start;
reg Datain_Start;//start a writing operation
reg Datain_Done;
//reg Datain_ready;//implication for the FIFO outsides to allow datainput .
reg FIFO_Dataout_Valid;// synchoronization of FIFO dout and DQX_reg.
reg [7:0] Command;
reg Asyn_CE_L;
reg Syn_CE_L;
reg Asyn_CLE_H;
reg Syn_CLE_H;
reg Asyn_ALE_H;
reg Syn_ALE_H;
reg Asyn_RB_L0;
reg Asyn_RB_L1;
reg Syn_RB_L;
reg [7:0]Asyn_DQX_reg;
reg [7:0]Syn_DQX_reg;
reg [3:0] Asyn_current_state;
reg [3:0] Asyn_next_state;
reg [2:0] current_toggle_state;
reg [2:0] next_toggle_state;
reg [7:0] page_offset_addr_reg [3:0];
reg [4:0] flash_control_signals1;
reg [4:0] flash_control_signals2;
reg toggle_enable;
reg toggledone;
/**delay counter**/
reg [7:0] delay_counter;
reg delay_counter_rst;
reg delay_counter_en;
/****internal_counter0****/
reg [3:0] internal_counter0;//¼ÆÊýÆ÷
reg [1:0] internal_counter0_upto;//¼ÆÊýÉèÖÃ
reg internal_counter0_rst ;//¼ÆÊýÇåÁã
reg internal_counter0_en;
/****internal_counter2****/
reg [1:0] internal_counter2;//¼ÆÊýÆ÷
reg [1:0] internal_counter2_upto;//¼ÆÊýÉèÖÃ
reg internal_counter2_rst ;//¼ÆÊýÇåÁã
reg internal_counter2_en;
//Timer0
reg [7:0]Timer0;
reg Timer0En;
reg Timer0Start;
//Timer1
reg [12:0]Timer1;
reg Timer1En;
reg Timer1Start;
//Timer2
reg [7:0]Timer2;
reg Timer2En;
reg Timer2Start;
reg WE_L;
reg RE_L;
reg WR_L;
reg SyncActive;
//**********Data output from NAND flash Chips*****************/
assign data_from_flash=DQX_In;
assign data_from_flash_en=rd_flash_datafifo_en;
/************select output signals according to the output interface mode.***********************/
//reg WE_Lorclk_bufin;
reg RE_LorWR_L_temp;
reg CLE_H_temp;
reg ALE_H_temp;
reg DQS_Start_temp;
reg WE_Lorclk_delay;
always @(*)
begin
if(!rst)
begin
RE_LorWR_L_temp=RE_L;
CLE_H_temp =Asyn_CLE_H;
ALE_H_temp =Asyn_ALE_H;
WE_Lorclk_delay =WE_L;
end
else if(1'b0==SyncActive)
begin
RE_LorWR_L_temp=RE_L;
CLE_H_temp =Asyn_CLE_H;
ALE_H_temp =Asyn_ALE_H;
WE_Lorclk_delay =WE_L;
end
else
begin
RE_LorWR_L_temp=WR_L;
CLE_H_temp =Syn_CLE_H;
ALE_H_temp =Syn_ALE_H;
WE_Lorclk_delay =clk_83M_reverse;
end
end
reg RE_LorWR_L_delay;
reg CLE_H_delay;
reg ALE_H_delay;
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
RE_LorWR_L_delay<=1'b0;
CLE_H_delay<=1'b0;
ALE_H_delay<=1'b0;
end
else
begin
RE_LorWR_L_delay<=RE_LorWR_L_temp;
CLE_H_delay<=CLE_H_temp;
ALE_H_delay<=ALE_H_temp;
end
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
DQS_Start<=1'b0;
end
else
begin
DQS_Start<= DQS_Start_temp;
end
end
//delay 31 taps for RE_LorWR_L.
(* IODELAY_GROUP = "iodelay_delayDQS" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
IODELAYE1 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE")
.DELAY_SRC("O"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("FIXED"), // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
.IDELAY_VALUE(), // Input delay tap setting (0-32)
.ODELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE"
.ODELAY_VALUE(31), // Output delay tap setting (0-32)
.REFCLK_FREQUENCY(200), // IDELAYCTRL clock input frequency in MHz
.SIGNAL_PATTERN("DATA") // "DATA" or "CLOCK" input signal
)
IODELAYE1_inst_RE_LorWR_L (
.CNTVALUEOUT(), // 5-bit output - Counter value for monitoring purpose
.DATAOUT(RE_LorWR_L), // 1-bit output - Delayed data output
.C(), // 1-bit input - Clock input
.CE(1'b0), // 1-bit input - Active high enable increment/decrement function
.CINVCTRL(), // 1-bit input - Dynamically inverts the Clock (C) polarity
.CLKIN(), // 1-bit input - Clock Access into the IODELAY
.CNTVALUEIN(), // 5-bit input - Counter value for loadable counter application
.DATAIN(), // 1-bit input - Internal delay data
.IDATAIN(), // 1-bit input - Delay data input
.INC(), // 1-bit input - Increment / Decrement tap delay
.ODATAIN(RE_LorWR_L_delay), // 1-bit input - Data input for the output datapath from the device
.RST(), // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
// ODELAY_VALUE tap. If no value is specified, the default is 0.
.T() // 1-bit input - 3-state input control. Tie high for input-only or internal delay or
// tie low for output only.
);
//delay 31 taps for CLE_H.
(* IODELAY_GROUP = "iodelay_delayDQS" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
IODELAYE1 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE")
.DELAY_SRC("O"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("FIXED"), // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
.IDELAY_VALUE(), // Input delay tap setting (0-32)
.ODELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE"
.ODELAY_VALUE(31), // Output delay tap setting (0-32)
.REFCLK_FREQUENCY(200), // IDELAYCTRL clock input frequency in MHz
.SIGNAL_PATTERN("DATA") // "DATA" or "CLOCK" input signal
)
IODELAYE1_inst_CLE_H(
.CNTVALUEOUT(), // 5-bit output - Counter value for monitoring purpose
.DATAOUT(CLE_H), // 1-bit output - Delayed data output
.C(), // 1-bit input - Clock input
.CE(1'b0), // 1-bit input - Active high enable increment/decrement function
.CINVCTRL(), // 1-bit input - Dynamically inverts the Clock (C) polarity
.CLKIN(), // 1-bit input - Clock Access into the IODELAY
.CNTVALUEIN(), // 5-bit input - Counter value for loadable counter application
.DATAIN(), // 1-bit input - Internal delay data
.IDATAIN(), // 1-bit input - Delay data input
.INC(), // 1-bit input - Increment / Decrement tap delay
.ODATAIN(CLE_H_delay), // 1-bit input - Data input for the output datapath from the device
.RST(), // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
// ODELAY_VALUE tap. If no value is specified, the default is 0.
.T() // 1-bit input - 3-state input control. Tie high for input-only or internal delay or
// tie low for output only.
);
//delay 31 taps for ALE_H.
(* IODELAY_GROUP = "iodelay_delayDQS" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
IODELAYE1 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE")
.DELAY_SRC("O"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("FIXED"), // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
.IDELAY_VALUE(), // Input delay tap setting (0-32)
.ODELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE"
.ODELAY_VALUE(31), // Output delay tap setting (0-32)
.REFCLK_FREQUENCY(200), // IDELAYCTRL clock input frequency in MHz
.SIGNAL_PATTERN("DATA") // "DATA" or "CLOCK" input signal
)
IODELAYE1_inst_ALE_H (
.CNTVALUEOUT(), // 5-bit output - Counter value for monitoring purpose
.DATAOUT(ALE_H), // 1-bit output - Delayed data output
.C(), // 1-bit input - Clock input
.CE(1'b0), // 1-bit input - Active high enable increment/decrement function
.CINVCTRL(), // 1-bit input - Dynamically inverts the Clock (C) polarity
.CLKIN(), // 1-bit input - Clock Access into the IODELAY
.CNTVALUEIN(), // 5-bit input - Counter value for loadable counter application
.DATAIN(), // 1-bit input - Internal delay data
.IDATAIN(), // 1-bit input - Delay data input
.INC(), // 1-bit input - Increment / Decrement tap delay
.ODATAIN(ALE_H_delay), // 1-bit input - Data input for the output datapath from the device
.RST(), // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
// ODELAY_VALUE tap. If no value is specified, the default is 0.
.T() // 1-bit input - 3-state input control. Tie high for input-only or internal delay or
// tie low for output only.
);
//delay 31 taps for WE_Lorclk.
(* IODELAY_GROUP = "iodelay_delayDQS" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
IODELAYE1 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE")
.DELAY_SRC("O"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("FIXED"), // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
.IDELAY_VALUE(), // Input delay tap setting (0-32)
.ODELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE"
.ODELAY_VALUE(23), // Output delay tap setting (0-32)
.REFCLK_FREQUENCY(200), // IDELAYCTRL clock input frequency in MHz
.SIGNAL_PATTERN("DATA") // "DATA" or "CLOCK" input signal
)
IODELAYE1_inst_WE_Lorclk (
.CNTVALUEOUT(), // 5-bit output - Counter value for monitoring purpose
.DATAOUT(WE_Lorclk), // 1-bit output - Delayed data output
.C(), // 1-bit input - Clock input
.CE(1'b0), // 1-bit input - Active high enable increment/decrement function
.CINVCTRL(), // 1-bit input - Dynamically inverts the Clock (C) polarity
.CLKIN(), // 1-bit input - Clock Access into the IODELAY
.CNTVALUEIN(), // 5-bit input - Counter value for loadable counter application
.DATAIN(), // 1-bit input - Internal delay data
.IDATAIN(), // 1-bit input - Delay data input
.INC(), // 1-bit input - Increment / Decrement tap delay
.ODATAIN(WE_Lorclk_delay), // 1-bit input - Data input for the output datapath from the device
.RST(), // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
// ODELAY_VALUE tap. If no value is specified, the default is 0.
.T() // 1-bit input - 3-state input control. Tie high for input-only or internal delay or
// tie low for output only.
);
/*
always@(*)
begin
if(DQS_Start)
DQS_Out=clk_83M_reverse;
else
DQS_Out=1'b0;
end
*/
/****************************FIFO controll signal output***************************
*****************************data_to_flash_en and data_from_flash_en**************/
//implication for the FIFO outsides for trigger data output, as to FIFO
//DQX bus output the FIFO,outside the controller, data to the chip.
//(*IOB="FORCE"*)reg [7:0] DQX_Out;
reg [7:0] DQX_Out_reg ;
always @(*)
begin
if(!rst)
begin
DQX_Out_reg=Asyn_DQX_reg;
//data_to_flash_en=1'b0;
end
else if(1'b0==SyncActive)
begin
DQX_Out_reg=Asyn_DQX_reg;
end
else
begin
if(FIFO_Dataout_Valid)
begin
DQX_Out_reg=data_from_host;
end
else
begin
DQX_Out_reg=Command;
end
end
end
always @(posedge clk_data_transfer or negedge rst)
begin
if(!rst)
begin
DQX_Out<=8'b0;
end
else
begin
DQX_Out<=DQX_Out_reg;
end
end
//*************************select the operation target from 0 to 7****************************//
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
Asyn_RB_L0<=1'b0;
Asyn_RB_L1<=1'b0;
end
else
begin
Asyn_RB_L0<=|RB_L;
Asyn_RB_L1<=&RB_L;
end
end
reg [7:0] CE_L_temp;
reg Syn_RB_L_temp;
always@(*)
begin
if(!rst)
begin
CE_L_temp=8'hff;//target is non-active after power on
Syn_RB_L_temp =1'b0;
end
else if (1'b0==SyncActive)
begin
Syn_RB_L_temp =1'b0;
CE_L_temp[0]=Asyn_CE_L;
CE_L_temp[1]=Asyn_CE_L;
CE_L_temp[2]=Asyn_CE_L;
CE_L_temp[3]=Asyn_CE_L;
CE_L_temp[4]=Asyn_CE_L;
CE_L_temp[5]=Asyn_CE_L;
CE_L_temp[6]=Asyn_CE_L;
CE_L_temp[7]=Asyn_CE_L;
end
else
begin
case(Target_Addr)
3'h0:begin
Syn_RB_L_temp =RB_L[0];
CE_L_temp[0]=Syn_CE_L;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=1'b1;
end
3'h1:begin
Syn_RB_L_temp =RB_L[1];
CE_L_temp[0]=1'b1;
CE_L_temp[1]=Syn_CE_L;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=1'b1;
end
3'h2:begin
Syn_RB_L_temp =RB_L[2];
CE_L_temp[0]=1'b1;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=Syn_CE_L;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=1'b1;
end
3'h3:begin
Syn_RB_L_temp =RB_L[3];
CE_L_temp[0]=1'b1;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=Syn_CE_L;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=1'b1;
end
3'h4:begin
Syn_RB_L_temp =RB_L[4];
CE_L_temp[0]=1'b1;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=Syn_CE_L;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=1'b1;
end
3'h5:begin
Syn_RB_L_temp =RB_L[5];
CE_L_temp[0]=1'b1;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=Syn_CE_L;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=1'b1;
end
3'h6:begin
Syn_RB_L_temp =RB_L[6];
CE_L_temp[0]=1'b1;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=Syn_CE_L;
CE_L_temp[7]=1'b1;
end
3'h7:begin
Syn_RB_L_temp =RB_L[7];
CE_L_temp[0]=1'b1;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=Syn_CE_L;
end
default:begin
Syn_RB_L_temp =1'b0;
CE_L_temp[0]=1'b1;
CE_L_temp[1]=1'b1;
CE_L_temp[2]=1'b1;
CE_L_temp[3]=1'b1;
CE_L_temp[4]=1'b1;
CE_L_temp[5]=1'b1;
CE_L_temp[6]=1'b1;
CE_L_temp[7]=1'b1;
end
endcase
end
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
CE_L<=8'hff;
Syn_RB_L<=1'b0;
end
else
begin
CE_L<=CE_L_temp;
Syn_RB_L<=Syn_RB_L_temp;
end
end
//****************************************************************************************//
//***********************Asychronous interface reset main Asyn_current_state machine***************************************//
always@(posedge clk_83M or negedge rst)
begin
if(!rst) begin
Asyn_current_state <= POWER_UP;//
current_toggle_state <= TOGGLE_WAIT;
end
else begin
Asyn_current_state <= Asyn_next_state;
current_toggle_state <= next_toggle_state;
end
end
always@(*)
begin
// Asyn_next_state = POWER_UP;
case(Asyn_current_state)
//Chip power up and wait for command to reset chip.
POWER_UP : begin
Asyn_next_state=TARGET_SELECTION;
end
/**chip reset**/
TARGET_SELECTION:begin
if(Timer0=='d10)
Asyn_next_state=PREPARE_RESET_TARGET;
else
Asyn_next_state=TARGET_SELECTION;
end
PREPARE_RESET_TARGET:begin//'h17
if(Asyn_RB_L1)
Asyn_next_state = RESET_TARGET_COMMAND_1;
else
begin
Asyn_next_state = PREPARE_RESET_TARGET;
end
end
RESET_TARGET_COMMAND_1:begin//'h18
if(toggledone)
Asyn_next_state = RESET_WAIT_FOR_0;
else
Asyn_next_state = RESET_TARGET_COMMAND_1;
end
RESET_WAIT_FOR_0: begin//'h19
if(Asyn_RB_L0)
Asyn_next_state = RESET_WAIT_FOR_0;
else
Asyn_next_state = RESET_WAIT_FOR_1;
end
RESET_WAIT_FOR_1: begin//'h1a
if(Asyn_RB_L1)
Asyn_next_state = RESET_CHIP_END;
else
Asyn_next_state = RESET_WAIT_FOR_1;
end
RESET_CHIP_END:begin
Asyn_next_state =ACTIVESYN_CMD;
end
//********Active Synchronous Interface***************//
ACTIVESYN_CMD:begin
if(toggledone)
Asyn_next_state =ACTIVESYN_ADDR;
else
Asyn_next_state =ACTIVESYN_CMD;
end
ACTIVESYN_ADDR:begin
if(toggledone)
Asyn_next_state =ACTIVESYN_WAITTADL;
else
Asyn_next_state =ACTIVESYN_ADDR;
end
ACTIVESYN_WAITTADL:begin
if(Timer0>='d42)
begin
Asyn_next_state =ACTIVESYN_DATAMODE;
end
else
Asyn_next_state =ACTIVESYN_WAITTADL;
end
ACTIVESYN_DATAMODE:begin//data 14h,selection of DDR and timing mode4
if(toggledone)
Asyn_next_state = ACTIVESYN_DATA00;
else
Asyn_next_state = ACTIVESYN_DATAMODE;
end
ACTIVESYN_DATA00:begin//data 00h,00h,00h
if(toggledone)
Asyn_next_state = ACTIVESYN_WAITRB0;
else
Asyn_next_state = ACTIVESYN_DATA00;
end
ACTIVESYN_WAITRB0:begin
if(Asyn_RB_L0)
begin
Asyn_next_state =ACTIVESYN_WAITRB0;
end
else
Asyn_next_state = ACTIVESYN_WAITRB1;
end
ACTIVESYN_WAITRB1:begin
if(Asyn_RB_L1)
Asyn_next_state = ACTIVESYN_END;
else
Asyn_next_state =ACTIVESYN_WAITRB1;
end
ACTIVESYN_END:begin
Asyn_next_state =ACTIVESYN_END;
end
default:begin
Asyn_next_state=POWER_UP;
end
endcase
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst) begin
SyncActive<=1'b0;
Timer0Start<=1'b0;
Timer0En<=1'b0;
toggle_enable <= 'b0;
Asyn_DQX_reg<=8'b0;
flash_control_signals1<=5'b11001;
flash_control_signals2<=5'b11001;
//active sync interface mode
internal_counter0_upto<='b0;
end
else begin
case(Asyn_next_state)
//Chip power up and wait for command to reset chip.
POWER_UP : begin
Timer0En<=1'b0;
Timer0Start<=1'b0;
SyncActive<=1'b0;
internal_counter0_upto <= 'h0;
end
TARGET_SELECTION:begin
SyncActive<=1'b0;
Timer0En<=1'b1;
Timer0Start<=1'b1;
end
/**chip reset**/
PREPARE_RESET_TARGET:begin//'h17
Timer0En<=1'b0;
Timer0Start<=1'b0;
SyncActive<=1'b0;
end
RESET_TARGET_COMMAND_1:begin//'h18
Asyn_DQX_reg<= RESET_COMMAND_1;
toggle_enable <= 'b1;
flash_control_signals1 <= 5'b10010;
flash_control_signals2 <= 5'b11010;
end
RESET_WAIT_FOR_0: begin//'h19
toggle_enable <= 'b0;
end
RESET_WAIT_FOR_1: begin//'h1a
end
RESET_CHIP_END:begin
end
//********Active Synchronous Interface***************//
ACTIVESYN_CMD:begin
internal_counter0_upto <= 'h0;
Asyn_DQX_reg<=SET_FEATURES;
toggle_enable <= 'b1;
flash_control_signals1 <= 'b10010;
flash_control_signals2 <= 'b11010;
end
ACTIVESYN_ADDR:begin
Asyn_DQX_reg<='h01;
toggle_enable <= 'b1;
internal_counter0_upto <= 'h0;
flash_control_signals1 <= 'b10100;
flash_control_signals2 <= 'b11100;
end
ACTIVESYN_WAITTADL:begin
toggle_enable <= 'b0;
Timer0En<=1'b1;
Timer0Start<=1'b1;
end
ACTIVESYN_DATAMODE:begin//data 14h,selection of DDR and timing mode4
Timer0Start<=1'b0;
Timer0En<=1'b0;
toggle_enable <= 'b1;
Asyn_DQX_reg<='h14;
flash_control_signals1 <= 'b10000;
flash_control_signals2 <= 'b11000;
end
ACTIVESYN_DATA00:begin//data 00h,00h,00h
internal_counter0_upto <= 'h3;
toggle_enable <= 'b1;
Asyn_DQX_reg<='h00;
flash_control_signals1 <= 'b10000;
flash_control_signals2 <= 'b11000;
end
ACTIVESYN_WAITRB0:begin
toggle_enable <= 'b0;
internal_counter0_upto <= 'h0;
end
ACTIVESYN_WAITRB1:begin
end
ACTIVESYN_END:begin
SyncActive<=1'b1;//switch to synchoronous mode WE_Lorclk <=WE_L;RE_LorWR_L<=RE_L;
end
default:begin
end
endcase
end
end
always@(*)
begin
case(current_toggle_state)
TOGGLE_WAIT: begin
if(toggle_enable == 'b1)
next_toggle_state = TOGGLECLR;
else
next_toggle_state = TOGGLE_WAIT;
end
TOGGLECLR:begin
next_toggle_state = TOGGLE_CE_EN;
end
TOGGLE_CE_EN : begin
if(delay_counter >= 'd7) begin//??WE_N??? ??16?clk.??>=70ns(tCS)
next_toggle_state = TOGGLE1;
end
else begin
next_toggle_state = TOGGLE_CE_EN;
end
end
TOGGLE1: begin
if(delay_counter >= 'd14) begin//??WE_N??? ??16?clk.??>=70ns(tCS)
next_toggle_state = TOGGLEADD;
end
else begin
next_toggle_state = TOGGLE1;
end
end
TOGGLEADD:begin
next_toggle_state =TOGGLE2;
end
TOGGLE2: begin
if (delay_counter == 'd19)
if(internal_counter0 >= internal_counter0_upto)
next_toggle_state = TOGGLE_DONE;
else
begin
next_toggle_state = TOGGLECLR;
end
else
next_toggle_state = TOGGLE2;
end
TOGGLE_DONE: begin
next_toggle_state = TOGGLE_WAIT;
end
default: begin
next_toggle_state = TOGGLE_WAIT;
end
endcase
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst) begin
delay_counter_rst <= 'b0;
delay_counter_en <= 'b0;
internal_counter0_rst <= 'b0;
internal_counter0_en <= 'b0;
Asyn_CE_L <= 1'b1;
Asyn_CLE_H <= 1'b0;
Asyn_ALE_H <= 1'b0;
WE_L <= 1'b1;
RE_L <= 1'b1;
toggledone <= 'b0;
end
else begin
case(next_toggle_state)
TOGGLE_WAIT: begin
delay_counter_rst <= 'b0;
delay_counter_en <= 'b0;
internal_counter0_rst <= 'b0;
internal_counter0_en <= 'b0;
{RE_L,WE_L,Asyn_ALE_H,Asyn_CLE_H,Asyn_CE_L}<=5'b11000;
toggledone <= 'b0;
end
TOGGLECLR:begin
delay_counter_rst <= 'b0;
end
TOGGLE_CE_EN : begin
delay_counter_rst <= 'b1;
delay_counter_en <= 'b1;
internal_counter0_rst <= 'b1;
{RE_L,WE_L,Asyn_ALE_H,Asyn_CLE_H,Asyn_CE_L}<=5'b11000;
end
TOGGLE1: begin
delay_counter_rst <= 'b1;
delay_counter_en <= 'b1;
internal_counter0_rst <= 'b1;
{RE_L,WE_L,Asyn_ALE_H,Asyn_CLE_H,Asyn_CE_L}<=flash_control_signals1;
end
TOGGLEADD:begin
internal_counter0_en <= 'b1;
end
TOGGLE2: begin
delay_counter_en <= 'b1;
internal_counter0_en <= 'b0;
{RE_L,WE_L,Asyn_ALE_H,Asyn_CLE_H,Asyn_CE_L}<=flash_control_signals2;
end
TOGGLE_DONE: begin
toggledone <= 'b1;
{RE_L,WE_L,Asyn_ALE_H,Asyn_CLE_H,Asyn_CE_L}<=5'b11000;
end
default: begin
end
endcase
end
end
/**delay counter**/
always@(posedge clk_83M or negedge rst)
begin
if(!rst) begin
delay_counter <= 'h0;
end
else begin
if(!delay_counter_rst)
delay_counter <= 'h0;
else if(delay_counter == 'hff)
delay_counter <= 'h0;
else if(delay_counter_en)
delay_counter <= delay_counter + 1'b1;
else
delay_counter <= delay_counter;
end
end
//internal_counter0 is for account of the No. of commands or addresses needed to send in asynchronous interface.
/****internal_counter0****/
always@(posedge clk_83M or negedge rst)
begin
if(!rst) begin
internal_counter0 <= 'h0;
end
else begin
if(!internal_counter0_rst)
internal_counter0 <= 'h0;
else if(internal_counter0_en)
internal_counter0 <= internal_counter0 + 1'b1;
else
internal_counter0 <= internal_counter0;
end
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
Timer0<='h00;
end
else if(1'b1==Timer0En)
begin
if(1'b1==Timer0Start)
Timer0<=Timer0+1'b1;
else
Timer0<=Timer0;
end
else
Timer0<='h00;
end
//***************************Synchronous Interface operation part*******************************************//
reg [4:0] Syn_current_state;
reg [4:0] Syn_next_state;
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
Syn_current_state<=SYN_WAIT4SYNACTIVE;
Syn_CA_currentstate<=CA_PREPARE;
page_offset_addr_reg[0] <= 'h00;
page_offset_addr_reg[1] <= 'h00;
page_offset_addr_reg[2] <= 'h00;
page_offset_addr_reg[3] <= 'h00;
WP_L=1'b1;
end
else
begin
page_offset_addr_reg[0] <= page_offset_addr[7:0];
page_offset_addr_reg[1] <= page_offset_addr[15:8];
page_offset_addr_reg[2] <= {3'b000,page_offset_addr[ADDR_WIDTH-4:16]};//modified by qww
page_offset_addr_reg[3] <= 'h00;
Syn_current_state<=Syn_next_state;
Syn_CA_currentstate<=Syn_CA_nextstate;
end
end
always@(*)
begin
case(Syn_current_state)
SYN_WAIT4SYNACTIVE:begin
if(SyncActive)
begin
Syn_next_state=SYN_STANDBY;
end
else
begin
Syn_next_state=SYN_WAIT4SYNACTIVE;
end
end
SYN_STANDBY:begin
if(Operation_en)
begin
Syn_next_state=SYN_BUSIDLE;
end
else
begin
Syn_next_state=SYN_STANDBY;
end
end
SYN_BUSIDLE: begin
case(Operation_Type)
3'h1:begin
Syn_next_state = READ_PAGE_COMMAND_1;
end
3'h2:begin
Syn_next_state = WRITE_PAGE_COMMAND_1;
end
3'h4:begin
Syn_next_state = ERASE_BLOCK_COMMAND_1;
end
3'h5:begin
Syn_next_state = READ_PAGE_WAIT;
end
default:begin
Syn_next_state =SYN_STANDBY;
end
endcase
end
// read page from flash operation
READ_PAGE_COMMAND_1:begin
if(CA_Done)
Syn_next_state=READ_PAGE_ADDRESS_00;
else
Syn_next_state=READ_PAGE_COMMAND_1;
end
READ_PAGE_ADDRESS_00:begin
if(CA_Done)
Syn_next_state=READ_PAGE_ADDRESS_3CYCLE;
else
Syn_next_state=READ_PAGE_ADDRESS_00;
end
READ_PAGE_ADDRESS_3CYCLE:begin
if(CA_Done)
Syn_next_state=READ_PAGE_COMMAND_2;
else
Syn_next_state=READ_PAGE_ADDRESS_3CYCLE;
end
READ_PAGE_COMMAND_2:begin
if(CA_Done)
Syn_next_state=READ_PAGE_WAIT_FOR_0;
else
Syn_next_state=READ_PAGE_COMMAND_2;
end
READ_PAGE_WAIT_FOR_0: begin
if(!Syn_RB_L)
begin
Syn_next_state= SYN_STANDBY;
end
else begin
Syn_next_state = READ_PAGE_WAIT_FOR_0;
end
end
/*
READ_PAGE_WAIT_FOR_1: begin
if(Syn_RB_L)
begin
Syn_next_state= READ_PAGE_WAIT;
end
else
Syn_next_state= READ_PAGE_WAIT_FOR_1;
end
*/
READ_PAGE_WAIT: begin
if('d3==Timer2)
begin
if(RD_data_FIFO_full)//Data-reading from flash will not start until host inform is coming.
Syn_next_state=SYN_STANDBY;
else
Syn_next_state=READ_PAGE_DATA_OUT;
end
else
begin
Syn_next_state=READ_PAGE_WAIT;
end
end
READ_PAGE_DATA_OUT:begin
if(Dataout_Done)
Syn_next_state=READ_DELAY_TRHW120;
else
Syn_next_state=READ_PAGE_DATA_OUT;
end
READ_DELAY_TRHW120:begin
if('d10==Timer2)//Timer2: Tclk ns a count
Syn_next_state=READ_PAGE_END;
else
Syn_next_state=READ_DELAY_TRHW120;
end
READ_PAGE_END: begin
Syn_next_state=SYN_STANDBY;
end
//programming page operation procedure
WRITE_PAGE_COMMAND_1:begin
if(CA_Done)
Syn_next_state=WRITE_PAGE_ADDRESS_00;
else
Syn_next_state=WRITE_PAGE_COMMAND_1;
end
WRITE_PAGE_ADDRESS_00:begin
if(CA_Done)
Syn_next_state=WRITE_PAGE_ADDRESS_3CYCELE;
else
Syn_next_state=WRITE_PAGE_ADDRESS_00;
end
WRITE_PAGE_ADDRESS_3CYCELE:begin
if(CA_Done)
Syn_next_state=WRITE_PAGE_DELAY70NS;
else
Syn_next_state=WRITE_PAGE_ADDRESS_3CYCELE;
end
WRITE_PAGE_DELAY70NS:begin
if('d5==Timer2)//Timer2: Tclk a count
begin
Syn_next_state=WRITE_PAGE_DATA;
end
else
Syn_next_state=WRITE_PAGE_DELAY70NS;
end
WRITE_PAGE_DATA:begin
if(Datain_Done)
Syn_next_state=WRITE_PAGE_COMMAND_2;
else
Syn_next_state=WRITE_PAGE_DATA;
end
WRITE_PAGE_COMMAND_2:begin
if(CA_Done)
Syn_next_state=WRITE_PAGE_WAIT_FOR_0;
else
Syn_next_state=WRITE_PAGE_COMMAND_2;
end
WRITE_PAGE_WAIT_FOR_0:begin
if(!Syn_RB_L)
Syn_next_state = SYN_STANDBY;
else
Syn_next_state = WRITE_PAGE_WAIT_FOR_0;
end
/*
WRITE_PAGE_WAIT_FOR_1:begin
if(Syn_RB_L)
Syn_next_state = SYN_STANDBY;
else
Syn_next_state = WRITE_PAGE_WAIT_FOR_1;
end
*/
// erase block operation procedure
ERASE_BLOCK_COMMAND_1:begin
if(CA_Done)
Syn_next_state=ERASE_BLOCK_ADDRESS_3CYCLES;
else
Syn_next_state=ERASE_BLOCK_COMMAND_1;
end
ERASE_BLOCK_ADDRESS_3CYCLES:begin//writing three address cycles containing the row address
if(CA_Done)
Syn_next_state=ERASE_BLOCK_COMMAND_2;
else
Syn_next_state=ERASE_BLOCK_ADDRESS_3CYCLES;
end
ERASE_BLOCK_COMMAND_2:begin//the ERASE BLOCK(60h-D0h) operation.
if(CA_Done)
Syn_next_state=ERASE_BLOCK_WAIT_FOR_0;
else
Syn_next_state=ERASE_BLOCK_COMMAND_2;
end
ERASE_BLOCK_WAIT_FOR_0:begin
if(!Syn_RB_L)
Syn_next_state = SYN_STANDBY;
else
Syn_next_state = ERASE_BLOCK_WAIT_FOR_0;
end
/*
ERASE_BLOCK_WAIT_FOR_1:begin
if(Syn_RB_L)
Syn_next_state = ERASE_BLOCK_END;
else
Syn_next_state = ERASE_BLOCK_WAIT_FOR_1;
end
ERASE_BLOCK_END:begin
Syn_next_state = SYN_STANDBY;
end
*/
default: Syn_next_state = SYN_STANDBY;
endcase
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
Command<='b0;
during_read_data <= 'b0;
controller_rb_l <= 'b0;
CA_Control_Signal0<=4'b0;
CA_Control_Signal1<=4'b0;
CA_Control_Signal2<=4'b0;
internal_counter2_upto<='b0;
CA_Start<=1'b0;
Dataout_Start<=1'b0;
Datain_Start <=1'b0;
Timer2En<=1'b0;
Timer2Start<=1'b0;
read_data_stall<=1'b0;
end
else begin
case(Syn_next_state)
SYN_WAIT4SYNACTIVE:begin
Command<='b0;
during_read_data <= 'b0;
controller_rb_l <= 'b0;
CA_Control_Signal0<=4'b1001;
internal_counter2_upto<='b0;
CA_Start<=1'b0;
Dataout_Start<=1'b0;
Datain_Start <=1'b0;
Timer2En<=1'b0;
Timer2Start<=1'b0;
read_data_stall<=1'b0;
end
SYN_STANDBY:begin
controller_rb_l <= 'b1;//until now the controller can be operated
CA_Start<=1'b0;
Dataout_Start<=1'b0;
Datain_Start <=1'b0;
CA_Control_Signal0<=4'b1001;
Timer2En<=1'b0;
Timer2Start<=1'b0;
end
SYN_BUSIDLE: begin
controller_rb_l <= 'b0;
CA_Start<=1'b0;
Dataout_Start<=1'b0;
Datain_Start <=1'b0;
CA_Control_Signal0<=4'b0001;
Timer2En<=1'b0;
Timer2Start<=1'b0;
end
// read page from flash operation
READ_PAGE_COMMAND_1:begin
controller_rb_l<=1'b0;
internal_counter2_upto<='d0;//send one command.
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0101;
CA_Control_Signal2<=4'b0001;
Command<=READ_MODE;//00h: read operation first command
end
READ_PAGE_ADDRESS_00:begin
internal_counter2_upto<='d1;//send 2 commands(0,1).
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0011;
CA_Control_Signal2<=4'b0001;
Command<=00;//00h: read from colum 0 in a page.
end
READ_PAGE_ADDRESS_3CYCLE:begin
internal_counter2_upto<='d2;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0011;
CA_Control_Signal2<=4'b0001;
Command<=page_offset_addr_reg[internal_counter2[1:0]];
end
READ_PAGE_COMMAND_2:begin
internal_counter2_upto<='d0;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0101;
CA_Control_Signal2<=4'b0001;
Command<=READ_PAGE; //'h30
end
READ_PAGE_WAIT_FOR_0: begin
CA_Start<=1'b0;
CA_Control_Signal0<=4'b1001;// transition to STANDBY mode.
end
/*
READ_PAGE_WAIT_FOR_1: begin
end
*/
READ_PAGE_WAIT: begin
controller_rb_l<=1'b0;
read_data_stall<=1'b1;
Timer2En<=1'b1;
Timer2Start<=1'b1;
end
READ_PAGE_DATA_OUT:begin
Timer2En<=1'b0;
Timer2Start<=1'b0;
read_data_stall<=1'b0;
controller_rb_l<=1'b0;
during_read_data<=1'b1;
CA_Control_Signal0<=4'b0001;// transition to IDLE mode.
CA_Control_Signal1<=4'b0000;
CA_Control_Signal2<=4'b0110;
Dataout_Start<=1'b1;
end
READ_DELAY_TRHW120:begin
Dataout_Start<=1'b0;
Timer2En<=1'b1;
Timer2Start<=1'b1;
end
READ_PAGE_END: begin
Timer2En<=1'b0;
Timer2Start<=1'b0;
during_read_data<=1'b0;
end
//programming page operation procedure
WRITE_PAGE_COMMAND_1:begin
controller_rb_l <= 'b0;
during_read_data<=1'b0;
internal_counter2_upto<='d0;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0101;
CA_Control_Signal2<=4'b0001;
Command<=PROGRAM_MODE;//80h: program operation first command
end
WRITE_PAGE_ADDRESS_00:begin
internal_counter2_upto<='d1;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0011;
CA_Control_Signal2<=4'b0001;
Command<=00;//00h: read from colum 0 in a page.
end
WRITE_PAGE_ADDRESS_3CYCELE:begin
internal_counter2_upto<='d2;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0011;
CA_Control_Signal2<=4'b0001;
Command<=page_offset_addr_reg[internal_counter2[1:0]];
end
WRITE_PAGE_DELAY70NS:begin
CA_Start<=1'b0;
Timer2En<=1'b1;
Timer2Start<=1'b1;
end
WRITE_PAGE_DATA:begin
Timer2En<=1'b0;
Timer2Start<=1'b0;
Datain_Start<=1'b1;
CA_Control_Signal1<=4'b0001;
CA_Control_Signal2<=4'b0111;
end
WRITE_PAGE_COMMAND_2:begin
Datain_Start<=1'b0;
internal_counter2_upto<='d0;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0101;
CA_Control_Signal2<=4'b0001;
Command<=PROGRAM_PAGE;//10h Program second command
end
WRITE_PAGE_WAIT_FOR_0:begin
Timer2En<=1'b1;
Timer2Start<=1'b1;
CA_Start<=1'b0;
end
/*
WRITE_PAGE_WAIT_FOR_1:begin
CA_Control_Signal0<=4'b1001;// transition to STANDBY mode.
Release<=1'b1;
end
*/
// erase block operation procedure
ERASE_BLOCK_COMMAND_1:begin
controller_rb_l <= 'b0;
internal_counter2_upto<='d0;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0101;
CA_Control_Signal2<=4'b0001;
Command<=ERASE_BLOCK_CMD1;//60h:the first Erase OPerations command,before three addresses
end
ERASE_BLOCK_ADDRESS_3CYCLES:begin//writing three address cycles containing the row address
internal_counter2_upto<='d2;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0011;
CA_Control_Signal2<=4'b0001;
Command<=page_offset_addr_reg[internal_counter2[1:0]];
end
ERASE_BLOCK_COMMAND_2:begin//the ERASE BLOCK(60h-D0h) operation.
internal_counter2_upto<='d0;
CA_Start<=1'b1;
CA_Control_Signal1<=4'b0101;
CA_Control_Signal2<=4'b0001;
Command<=ERASE_BLOCK_CMDEND;//the concluded command of ERASE BLOCK(60h-D0h) operation
end
ERASE_BLOCK_WAIT_FOR_0:begin
CA_Start<=1'b0;
end
/*
ERASE_BLOCK_WAIT_FOR_1:begin
CA_Control_Signal0<=4'b1001;// transition to STANDBY mode.
Release<=1'b1;
end
ERASE_BLOCK_END:begin
Release<=1'b0;
end
*/
default: begin
end
endcase
end
end
//**********************Synchoronus Command or Address Issure procedure************//
always@(*)
begin
case(Syn_CA_currentstate )
CA_PREPARE:begin
if(CA_Start)
Syn_CA_nextstate=CA_WAIT;
else if (Dataout_Start)
Syn_CA_nextstate=DDR_DATAOUT_PREPARE;
else if (Datain_Start)
Syn_CA_nextstate=DDR_DATAIN_EN;
else
Syn_CA_nextstate=CA_PREPARE;
end
CA_WAIT :begin
if(Timer1>='h2)
begin
Syn_CA_nextstate=CA_ISSURE;
end
else
Syn_CA_nextstate=CA_WAIT;
end
CA_ISSURE:begin
Syn_CA_nextstate=CA_COMPLETE;
end
CA_COMPLETE:begin
if(internal_counter2>=internal_counter2_upto)// ÏÈÅжϺó¼Ó1
Syn_CA_nextstate=CA_END;
else
Syn_CA_nextstate=CA_WAIT;
end
CA_END: begin
Syn_CA_nextstate=CA_PREPARE;
end
// DDR Data out
DDR_DATAOUT_PREPARE:begin
if(Timer1=='d3)
Syn_CA_nextstate=DDR_MODE;
else
Syn_CA_nextstate=DDR_DATAOUT_PREPARE;
end
DDR_MODE:begin
if(Timer1=='d2056)
Syn_CA_nextstate=DDR_DATAOUT_END;
else
Syn_CA_nextstate=DDR_MODE;
end
DDR_DATAOUT_END:begin
if(Timer1=='d2060)
Syn_CA_nextstate=CA_PREPARE;
else
Syn_CA_nextstate=DDR_DATAOUT_END;
end
//DDR data in part
DDR_DATAIN_EN:begin
if(Timer1=='d3)
Syn_CA_nextstate=DATAIN_PREPARE;
else
Syn_CA_nextstate=DDR_DATAIN_EN;
end
DATAIN_PREPARE:begin // a clk period
Syn_CA_nextstate=DATAIN_MODE;
end
DATAIN_MODE:begin
if(Timer1=='d2051)
Syn_CA_nextstate=DDR_DATAIN_LAST2;
else
Syn_CA_nextstate=DATAIN_MODE;
end
DDR_DATAIN_LAST2:begin
if(Timer1=='d2052)
Syn_CA_nextstate=DDR_DATAIN_END;
else
Syn_CA_nextstate=DDR_DATAIN_LAST2;
end
DDR_DATAIN_END:begin
Syn_CA_nextstate=CA_PREPARE;
end
default:Syn_CA_nextstate=CA_PREPARE;
endcase
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
FIFO_Dataout_Valid<=1'b0;
Timer1En<=1'b0;
Timer1Start<=1'b0;
internal_counter2_rst<=1'b0;
internal_counter2_en<=1'b0;
CA_Done<=1'b0;
Dataout_Done<=1'b0;
data_to_flash_en<='b0;
Datain_Done <=1'b0;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=4'b0;
clear_flash_datafifo<=1'b0;
DQS_Start_temp<='b0;
end
else
begin
case(Syn_CA_nextstate )
CA_PREPARE:begin
//DQS_Start_temp<='b0;
data_to_flash_en<='b0;
Datain_Done <=1'b0;
CA_Done<=1'b0;
Dataout_Done<=1'b0;
FIFO_Dataout_Valid<=1'b0;
Timer1En<=1'b0;
Timer1Start<=1'b0;
internal_counter2_rst<=1'b0;
internal_counter2_en<=1'b0;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal0;
clear_flash_datafifo<=1'b0;
end
CA_WAIT :begin
internal_counter2_rst<=1'b1;
Timer1En<=1'b1;
Timer1Start<=1'b1;
internal_counter2_en<=1'b0;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal0;
end
CA_ISSURE:begin
Timer1En<=1'b0;
Timer1Start<=1'b0;
internal_counter2_en<=1'b0;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal1;
end
CA_COMPLETE:begin
internal_counter2_en<=1'b1;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal2;
end
CA_END: begin
internal_counter2_rst<=1'b0;
internal_counter2_en<=1'b0;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal0;
CA_Done<=1'b1;
end
// DDR Data out
DDR_DATAOUT_PREPARE:begin
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal1;
Timer1En<=1'b1;
Timer1Start<=1'b1;
clear_flash_datafifo<=1'b1;
end
DDR_MODE:begin
clear_flash_datafifo<=1'b0;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal2;
end
DDR_DATAOUT_END:begin
Dataout_Done<=1'b1;
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal0;
end
//DDR data in part
DDR_DATAIN_EN:begin
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal1;
Timer1En<=1'b1;
Timer1Start<=1'b1;
end
DATAIN_PREPARE:begin
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal2;
FIFO_Dataout_Valid<=1'b1;
data_to_flash_en<=1'b0;
end
DATAIN_MODE:begin
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal2;
DQS_Start_temp<=1'b1;
data_to_flash_en<=1'b1;
end
DDR_DATAIN_LAST2:begin
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal1;
end
DDR_DATAIN_END:begin
{Syn_CE_L,Syn_CLE_H,Syn_ALE_H,WR_L}<=CA_Control_Signal1;
DQS_Start_temp<=1'b0;
// FIFO_Dataout_Valid<=1'b0;
data_to_flash_en<=1'b0;
Timer1En<=1'b0;
Timer1Start<=1'b0;
Datain_Done<=1'b1;
end
default:begin
end
endcase
end
end
//internal_counter2 is for account of the No. of commands or addresses needed to send in synchronous interface.
/****internal_counter2****/
always@(posedge clk_83M or negedge rst)
begin
if(!rst) begin
internal_counter2 <= 2'b0;
end
else begin
if(!internal_counter2_rst)
internal_counter2 <= 'h0;
else if(internal_counter2_en)
internal_counter2 <= internal_counter2 + 1'b1;
else
internal_counter2 <= internal_counter2;
end
end
//Time1 for Synchoronus Command or Address Issure procedure
//T=5ns
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
Timer1<='h00;
end
else if(1'b1==Timer1En)
begin
if(1'b1==Timer1Start)
Timer1<=Timer1+1'b1;
else
Timer1<=Timer1;
end
else
Timer1<='h00;
end
//Time2 for Synchoronus main machine state
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
Timer2<='h00;
end
else if(1'b1==Timer2En)
begin
if(1'b1==Timer2Start)
Timer2<=Timer2+1'b1;
else
Timer2<=Timer2;
end
else
Timer2<='h00;
end
/*
reg curr_en_state;
reg next_en_state;
parameter RD_FLASH_EN_0 =1'b0;
parameter RD_FLASH_EN_1 =1'b1;
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
curr_en_state<=RD_FLASH_EN_0;
end
else
curr_en_state<=next_en_state;
end
always@(*)
begin
case(curr_en_state)
RD_FLASH_EN_0:begin
if( flash_data_fifo_empty==1'b0 )
next_en_state=RD_FLASH_EN_1;
else
next_en_state=RD_FLASH_EN_0;
end
RD_FLASH_EN_1:begin
next_en_state=RD_FLASH_EN_0;
end
endcase
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
rd_flash_datafifo_en<=1'b0;
end
else
begin
case(next_en_state)
RD_FLASH_EN_0:begin
rd_flash_datafifo_en<=1'b0;
end
RD_FLASH_EN_1:begin
rd_flash_datafifo_en<=1'b1;
end
endcase
end
end
*/
reg [11:0] ddr_datain_counter;
always@( posedge clk_83M or negedge rst)
begin
if(!rst)
ddr_datain_counter<=12'b0;
else
begin
if(clear_flash_datafifo)
ddr_datain_counter<=12'b0;
else if(rd_flash_datafifo_en)
ddr_datain_counter<=ddr_datain_counter+1'b1;
else
ddr_datain_counter<=ddr_datain_counter;
end
end
always@(posedge clk_83M or negedge rst)
begin
if(!rst)
begin
rd_flash_datafifo_en<=1'b0;
end
else
begin
if(ddr_datain_counter>='h7ff)
rd_flash_datafifo_en<=1'b0;
else if( flash_data_fifo_empty==1'b0 )
rd_flash_datafifo_en<=1'b1;
else
rd_flash_datafifo_en<=1'b0;
end
end
/*
// FIFO Write operation:Data output from FIFO, to flash chips.
always@( posedge clk_data_transfer or negedge rst)
begin
if(!rst)
data_to_flash_en<=1'b0;
else
data_to_flash_en<=Datain_ready;
end
//assign data_to_flash_en=Datain_ready;
*/
endmodule |
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module diploma_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module sky130_fd_sc_hd__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module scsdpram
#(
parameter C_WIDTH = 32,
parameter C_DEPTH = 1024
)
(
input CLK,
input RD1_EN,
input [clog2s(C_DEPTH)-1:0] RD1_ADDR,
output [C_WIDTH-1:0] RD1_DATA,
input WR1_EN,
input [clog2s(C_DEPTH)-1:0] WR1_ADDR,
input [C_WIDTH-1:0] WR1_DATA
);
reg [C_WIDTH-1:0] rMemory [C_DEPTH-1:0];
reg [C_WIDTH-1:0] rDataOut;
assign RD1_DATA = rDataOut;
always @(posedge CLK) begin
if (WR1_EN) begin
rMemory[WR1_ADDR] <= #1 WR1_DATA;
end
if(RD1_EN) begin
rDataOut <= #1 rMemory[RD1_ADDR];
end
end
endmodule |
module dbg_crc8_d1 (Data, EnableCrc, Reset, SyncResetCrc, CrcOut, Clk);
parameter Tp = 1;
input Data;
input EnableCrc;
input Reset;
input SyncResetCrc;
input Clk;
output [7:0] CrcOut;
reg [7:0] CrcOut;
// polynomial: (0 1 2 8)
// data width: 1
function [7:0] nextCRC8_D1;
input Data;
input [7:0] Crc;
reg [0:0] D;
reg [7:0] C;
reg [7:0] NewCRC;
begin
D[0] = Data;
C = Crc;
NewCRC[0] = D[0] ^ C[7];
NewCRC[1] = D[0] ^ C[0] ^ C[7];
NewCRC[2] = D[0] ^ C[1] ^ C[7];
NewCRC[3] = C[2];
NewCRC[4] = C[3];
NewCRC[5] = C[4];
NewCRC[6] = C[5];
NewCRC[7] = C[6];
nextCRC8_D1 = NewCRC;
end
endfunction
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
CrcOut[7:0] <= #Tp 0;
else
if(SyncResetCrc)
CrcOut[7:0] <= #Tp 0;
else
if(EnableCrc)
CrcOut[7:0] <= #Tp nextCRC8_D1(Data, CrcOut);
end
endmodule |
module ram_16x1k_sp (
clka,
ena,
wea,
addra,
dina,
douta
);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
//============
// RAM
//============
ram_sp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_sp_inst (
// OUTPUTs
.ram_dout ( douta), // RAM data output
// INPUTs
.ram_addr ( addra), // RAM address
.ram_cen (~ena), // RAM chip enable (low active)
.ram_clk ( clka), // RAM clock
.ram_din ( dina), // RAM data input
.ram_wen (~wea) // RAM write enable (low active)
);
endmodule |
module simple_test ();
reg [3:0] a_in;
reg [3:0] b_in;
reg [3:0] s_in;
reg M_in,Ci_inverse_in;
wire [3:0] Y_out;
wire P_out,Q_out,Co_inverse_out,AequalsB_out;
ALU alu(a_in,b_in,s_in,M_in,Ci_inverse_in,P_out,Q_out,Co_inverse_out,Y_out,AequalsB_out);
integer i,j,k,l,m;
initial begin
a_in = 4'b0110;
b_in = 4'b1011;
s_in = 4'b0000;
M_in = 1'b0;
Ci_inverse_in = 1'b0;
end
initial begin
for (i=0;i<2;i=i+1)
begin
for(j=0;j<2;j=j+1)
begin
for(k=0;k<16;k=k+1)
begin
#100 a_in = 4'b0110;
b_in = 4'b1011;
s_in = k;
M_in = j;
Ci_inverse_in = i;
#10 $display($time,,"a_in=%b,b_in=%b,s_in=%b,M_in=%b,Ci_inverse_in=%b Y_out=%b,P_out=%b,Q_out=%b,Co_inverse_out=%b,AequalsB_out=%b",a_in,b_in,s_in,M_in,Ci_inverse_in,Y_out,P_out,Q_out,Co_inverse_out,AequalsB_out);
end
end
end
end
endmodule |
module module1(clk_, rst_, bar0, bar1, foo0, foo1);
input clk_;
input rst_;
input [1:0] bar0;
input [1:0] bar1;
output [1:0] foo0;
output [1:0] foo1;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1+1-0+1;
parameter poser_width_out = 0+1-0+1+1-0+1;
parameter poser_grid_width = 2;
parameter poser_grid_depth = 2;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 2'b11,2'b11 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar0,bar1 };
wire [poser_width_out-1:0] poser_outputs;
assign { foo0,foo1 } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule |
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module cpu
#(
parameter OPTION_RESET_ADDR = 32'hbfc00000,
parameter OPTION_TRAP_ADDR = 32'hbfc00180
)
(
input CLK,
input RESET_I,
output [31:0] CADDR_O,
output [1:0] CTRANS_O,
input [31:0] CRDATA_I,
input CREADY_I,
input [1:0] CRESP_I,
output [31:0] DADDR_O,
output [1:0] DTRANS_O,
output [2:0] DSIZE_O,
input [31:0] DRDATA_I,
output [31:0] DWDATA_O,
output DWRITE_O,
input DREADY_I,
input [1:0] DRESP_I,
input [4:0] HWIRQ_I,
input STALL_I
);
//==== Local parameters ====================================================
// Hardwired values of several CSR. Not really user-configurable.
localparam FEATURE_PRID = 32'h00000000;
localparam FEATURE_CONFIG0 = 32'h00000000;
localparam FEATURE_CONFIG1 = 32'h00000000;
// Translated indices of implemented, writeable CSRs.
// Smaller than spec index to save a few DFFs in the pipeline regs.
// (Read-only regs don't need their indices propagated to writeback stage.)
localparam
CSRB_MCOMPARE = 4'b0000, CSRB_MSTATUS = 4'b0001,
CSRB_MCAUSE = 4'b0010, CSRB_MEPC = 4'b0011,
CSRB_MCONFIG0 = 4'b0100, CSRB_MERROREPC = 4'b0101;
// Instruction formats. Used to decode position of instruction fields.
localparam
TYP_J = 4'b0000, TYP_B = 4'b0001, TYP_I = 4'b0010, TYP_M = 4'b0011,
TYP_S = 4'b0100, TYP_R = 4'b0101, TYP_P = 4'b0110, TYP_T = 4'b0111,
TYP_E = 4'b1000, TYP_IH =4'b1001, TYP_IU =4'b1010, TYP_BAD = 4'b1111;
// Selection mux control for ALU operand 0.
localparam
P0_0 = 3'b000, P0_RS1 = 3'b001, P0_PC = 3'b010,
P0_PCS = 3'b011, P0_IMM = 3'b100, P0_X = 3'b000;
// Selection mux control for ALU operand 1.
localparam
P1_0 = 2'b00, P1_RS2 = 2'b01, P1_CSR = 2'b10,
P1_IMM = 2'b11, P1_X = 2'b00;
// ALU operation selection.
localparam
OP_NOP = 5'b00000, OP_SLL = 5'b00100, OP_SRL = 5'b00110,
OP_SRA = 5'b00111, OP_ADD = 5'b10000, OP_SUB = 5'b10001,
OP_SLT = 5'b10101, OP_SLTU = 5'b10111, OP_OR = 5'b01000,
OP_AND = 5'b01001, OP_XOR = 5'b01010, OP_NOR = 5'b01011;
// Writeback selection ({R}egister bank, {C}SR or {N}one).
localparam
WB_R = 2'b10, WB_N = 2'b00, WB_C = 2'b01;
//==== Register macros -- all DFFs inferred using these ====================
// Pipeline reg. Input st is load enable for stalls.
`define PREG(st, name, resval, enable, loadval) \
always @(posedge CLK) \
if (RESET_I) /* enable ignored. */ \
name <= resval; \
else if(~st) \
name <= loadval;
// Same as PREG but gets RESET when the stage is bubbled -- even if stalled.
`define PREGC(st, name, resval, enable, loadval) \
always @(posedge CLK) \
if (RESET_I || ~enable) \
name <= resval; \
else if(~st) \
name <= loadval;
// COP0 reg. Load ports for MTC0 writebacks AND traps.
`define CSREGT(st, name, resval, trapen, trapval, loadval) \
always @(posedge CLK) \
if (RESET_I) \
s42r_csr_``name <= resval; \
else begin \
if (s4_en & ~st & trapen) \
s42r_csr_``name <= trapval; \
else if (s4_en & s34r_wb_csr_en & (s34r_csr_xindex==CSRB_``name)) \
s42r_csr_``name <= loadval; \
end
// COP0 reg. Load port for MTC0 only.
`define CSREG(st, name) \
always @(posedge CLK) \
if (RESET_I) \
s42r_csr_``name <= 32'h0; \
else if (s4_en & ~st & s34r_wb_csr_en & (s34r_csr_xindex==CSRB_``name)) \
s42r_csr_``name <= s34r_alu_res;
//==== Per-machine state registers =========================================
// COP0 registers. Note they are 'packed' (@note6).
reg [16:0] s42r_csr_MCAUSE;
reg [12:0] s42r_csr_MSTATUS;
reg [31:0] s42r_csr_MEPC;
reg [31:0] s42r_csr_MIP; // FIXME merge into CAUSE
reg [31:0] s42r_csr_MERROREPC;
reg [31:0] s42r_csr_MCOMPARE;
// Register bank.
reg [31:0] s42r_rbank [0:31];
// These macros unpack COP0 regs into useful names.
// Also define packed-to-32 and 32-to-packed macros.
`define STATUS_BEV s42r_csr_MSTATUS[12]
`define STATUS_IM s42r_csr_MSTATUS[11:4]
`define STATUS_UM s42r_csr_MSTATUS[3]
`define STATUS_ERL s42r_csr_MSTATUS[2]
`define STATUS_EXL s42r_csr_MSTATUS[1]
`define STATUS_IE s42r_csr_MSTATUS[0]
`define STATUS_PACK(w) {w[22],w[15:8],w[4],w[2],w[1],w[0]}
`define STATUS_UNPACK(p) {9'h0,p[12],6'h0,p[11:4],3'h0,p[3:0]}
`define CAUSE_BD s42r_csr_MCAUSE[16]
`define CAUSE_CE s42r_csr_MCAUSE[15:14]
`define CAUSE_IV s42r_csr_MCAUSE[13]
`define CAUSE_IPHW s42r_csr_MCAUSE[12:7]
`define CAUSE_IPSW s42r_csr_MCAUSE[6:5]
`define CAUSE_EXCODE s42r_csr_MCAUSE[4:0]
`define CAUSE_PACK(w) {w[31],w[29:28],w[23],w[15:8],w[6:2]}
`define CAUSE_UNPACK(p) {p[16],1'b0,p[15:14],4'b0,p[13],7'b0,p[12:5],1'b0,p[4:0],2'b0}
//==== Forward declaration of control signals ==============================
reg co_s0_bubble; // Insert bubble in FAddr stage.
reg co_s1_bubble; // Insert bubble in FData stage.
reg co_s2_bubble; // Insert bubble in Decode stage.
reg s0_st, s1_st, s2_st, s3_st, s4_st; // Per-stage stall controls.
//==== Pipeline stage 0 -- Fetch-Address ===================================
// Address phase of fetch cycle.
reg s0_en; // FAddr stage enable.
reg s01r_pending; // Cycle in progress in code bus.
reg s0_pending; //
reg [31:0] s0_pc_fetch; // Fetch address (PC of next instruction).
reg s01r_en; // FData stage enable carried from FAaddr.
reg [31:0] s01r_pc; // PC of instr in FData stage.
reg [31:0] s01r_pc_seq;
// Fetch address mux: sequential or non sequential.
always @(*) begin
s0_en = ~RESET_I & ~co_s0_bubble; // See @note11.
s0_pc_fetch = s2_go_seq? s01r_pc_seq : s2_pc_nonseq;
// A new cycle is started whenever this stage is enabled and it is
// terminated whenever CREADY comes high.
s0_pending = s0_en | (s01r_pending & ~CREADY_I);
end
// Drive code bus straight from stage control signals.
assign CADDR_O = s0_pc_fetch;
assign CTRANS_O = s0_en? 2'b10 : 2'b00;
// Remember if there's a bus cycle in progress.
`PREG (s0_st, s01r_pending, 0, 1, s0_pending)
// FA-FD pipeline registers.
`PREG (s0_st, s01r_en, 1'b1, 1'b1, s0_en)
`PREG (s0_st, s01r_pc, OPTION_RESET_ADDR-4, s0_en, s0_pc_fetch)
`PREG (s0_st, s01r_pc_seq, OPTION_RESET_ADDR, s0_en, s0_pc_fetch + 4)
//==== Pipeline stage 1 -- Fetch-Data ======================================
// Data phase of fetch cycle.
reg s1_en; // FD stage enable.
reg s1_mem_truncated; // Code cycle truncated by (non-code) stall.
reg s12r_mem_truncated; //
reg s12r_en; // Decode stage enable carried from FData.
reg [31:0] s12r_ir; // Instruction register (valid in stage DE).
reg [31:0] s12r_irs; // FIXME explain.
reg [31:0] s12r_pc; // PC of instruction in DE stage.
reg [31:0] s12r_pc_seq; // PC of instr following fdr_pc_de one.
reg [31:0] s1_ir; // Mux at input of IR reg.
always @(*) begin
s1_en = s01r_en & ~co_s1_bubble;
// If we have a word coming in on code bus but this stage is stalled,
// store it in s12r_irs and remember we've truncated a cycle.
s1_mem_truncated = s1_st & CREADY_I;
s1_ir = s12r_mem_truncated? s12r_irs : CRDATA_I; // @note1
end
// Load IR from code bus (if cycle complete) OR saved IR after a stall.
`PREGC(s1_st, s12r_ir, 32'h0, s1_en & CREADY_I, s1_ir) // @note9
// When stage 1 is stalled, save IR to be used after end of stall.
`PREG (1'b0, s12r_irs, 32'h0, s1_mem_truncated, CRDATA_I)
// Remember if we have saved a code word from a truncated code cycle.
`PREG (1'b0, s12r_mem_truncated, 1'b0, 1'b1, s1_mem_truncated)
// FD-DE pipeline registers.
`PREG (s1_st, s12r_en, 1'b1, 1'b1, s1_en)
`PREG (s1_st, s12r_pc, OPTION_RESET_ADDR, s1_en, s01r_pc)
`PREG (s1_st, s12r_pc_seq, OPTION_RESET_ADDR+4, s1_en, s01r_pc_seq)
//==== Pipeline stage Decode ===============================================
// Last stage of Fetch pipeline, first of Execute pipeline.
// PC flow logic / IR decoding / RBank read.
reg [31:0] s23r_arg0; // ALU arg0.
reg [31:0] s23r_arg1; // ALU arg1.
reg s23r_wb_en; // Writeback enable (main reg bank).
reg s23r_wb_csr_en; // Writeback enable (CSR reg bank).
reg [3:0] s23r_csr_xindex; // Index (translated) of target CSR if any.
reg [4:0] s23r_rd_index; // Index of target register if any.
reg [4:0] s23r_alu_op; // ALU operation.
reg [31:0] s23r_mem_addr; // MEM address.
reg [1:0] s23r_mem_trans; // MEM transaction type.
reg [1:0] s23r_mem_size; // MEM transaction size.
reg s23r_store_en; // Active for store MEM cycle.
reg s23r_load_en; // Active for load MEM cycle.
reg [31:0] s23r_mem_wdata; // MEM write data.
reg s23r_load_exz; // 1 if MEM subword load zero-extends to word.
reg s23r_trap; // TRAP event CSR control passed on to EX.
reg s23r_eret; // ERET event CSR control passed on to EX.
reg [4:0] s23r_excode; // Trap cause code passed on to EX.
reg [31:0] s23r_epc; // Next EPC to be passed on to next stages.
reg s2_en; // DE stage enable.
reg s23r_en; // Execute stage enable carried over from Dec.
reg [31:0] s2_pc_nonseq; // Next PC if any possible jump is taken.
reg [1:0] s2_opcode; // IR opcode field (2 bits used out of 6).
reg [4:0] s2_rs1_index; // Index for RS1 from IR.
reg [4:0] s2_rs2_index; // Index for RS2 from IR.
reg [4:0] s2_rd_index; // Index for RD from IR.
reg [7:0] s2_csr_index; // Index for CSR from IR (Reg index + sel).
reg [3:0] s2_csr_xindex; // Index for CSR translated.
reg [27:0] s2_m; // Concatenation of other signals for clarity.
reg [3:0] s2_type; // Format of instruction in IR.
reg s2_link; // Save PC to r31.
reg [2:0] s2_p0_sel; // ALU argument 0 selection.
reg [1:0] s2_p1_sel; // ALU argument 1 selection.
reg s2_wb_en; // Writeback enable for reg bank.
reg s2_wb_csr_en; // Writeback enable for CSR.
reg [1:0] s2_alu_sel; // Select ALU operation (hardwired/IR).
reg [4:0] s2_alu_op; // ALU operation fully decoded.
reg [4:0] s2_alu_op_f3; // ALU operation as encoded in func3 (IMM).
reg [4:0] s2_alu_op_csr; // ALU operation for CSR instructions.
reg s2_alu_en; // ALU operation is actually used.
reg s2_invalid; // IR is invalid;
reg [1:0] s2_flow_sel; // {00,01,10,11} = {seq/trap, JALR, JAL, Bxx}.
reg s2_cop0_access; // COP0 access instruction in IR.
reg s2_user_mode; // 1 -> user mode, 0 -> kernel mode.
reg [1:0] s2_break_syscall; // Trap caused by BREAK or SYSCALL instruction.
reg s2_trap_cop_unusable; // Trap caused by COP access in user mode.
reg s2_trap; // Take trap for any cause.
reg s2_eret; // ERET instruction.
reg s2_skip_seq_instr; // Skip instruction at stage 1 (traps/erets/etc.)
reg [4:0] s2_excode; // Trap cause code.
reg [31:0] s2_pc_branch; // Branch target;
reg [31:0] s2_pc_jump; // Jump (JAL) target;
reg [31:0] s2_pc_jalr; // Jump (JALR) target;
reg [31:0] s2_pc_trap_eret; // Trap/ERET PC target.
reg [31:0] s2_j_immediate; // Immediate value from J-type IR.
reg [31:0] s2_b_immediate; // Immediate value from B-type IR.
reg [31:0] s2_s_immediate; // Immediate value from S-type IR.
reg [31:0] s2_i_immediate; // Immediate value from I-type IR.
reg [31:0] s2_ih_immediate; // Immediate value from IH-type IR.
reg [31:0] s2_iu_immediate; // Immediate value from IU-type IR.
reg [31:0] s2_e_immediate; // Immediate value from E-type IR.
reg [31:0] s2_t_immediate; // Immediate value from T-type IR.
reg [31:0] s2_immediate; // Immediate value used in Execute stage.
reg [31:0] s2_cop_imm; // Immediate value for trap-related instructions.
reg [31:0] s2_csr; // CSR value read from CSR bank.
reg [31:0] s2_rs1_bank; // Register RS1 value read from bank.
reg [31:0] s2_rs2_bank; // Register RS2 value read from bank.
reg [31:0] s2_rs1; // Register RS1 value after FFWD mux.
reg [31:0] s2_rs2; // Register RS2 value after FFWD mux.
reg s2_rs12_equal; // RS1 == RS2.
reg s2_bxx_cond_val; // Set if Bxx condition is true.
reg [2:0] s2_bxx_cond_sel; // Selection of branch condition.
reg [31:0] s2_arg0; // ALU arg0 selection mux.
reg [31:0] s2_arg1; // ALU arg1 selection mux.
reg s2_3reg; // 1 in 3-reg formats, 0 in others.
reg [31:0] s2_mem_addr; // MEM address for load/store ops.
reg [31:0] s2_mem_addr_imm; // Immediate value used to compute mem address.
reg [1:0] s2_mem_trans; // MEM transaction type.
reg [1:0] s2_mem_size; // MEM transaction size.
reg s2_load_exz; // 1 if MEM subword load zero-extends to word.
reg s2_load_en; // MEM load.
reg s2_store_en; // MEM store.
reg [31:0] s2_mem_wdata; // MEM write data.
reg s2_ie; // Final irq enable.
reg [7:0] s2_masked_irq; // IRQ lines after masking.
reg s2_irq_final; // At least one pending IRQ enabled.
reg s2_hw_trap; // Any HW trap caught in stages 0..2.
reg s2_go_seq; // Sequential/Non-sequential PC selection.
// Pipeline bubble logic.
always @(*) begin
// The load hazard stalls & trap stalls inserts a bubble in stage 2 by
// clearing s2_en (in addition to stalling stages 0 to 2.)
s2_en = s12r_en & ~co_s2_bubble;
end
// Macros for several families of instruction binary pattern.
// Used as keys in the decoding table below.
// 'TA2' stands for "Table A-2" of the MIPS arch manual, vol. 2.
`define TA2(op) {op, 26'b?????_?????_????????????????}
`define TA2rt0(op) {op, 26'b?????_00000_????????????????}
`define TA2rs0(op) {op, 26'b00000_?????_????????????????}
`define TA3(fn) {26'b000000_?????_???????????????, fn}
`define TA3rs0(fn) {26'b000000_00000_???????????????, fn}
`define TA4(fn) {11'b000001_?????, fn, 16'b????????????????}
`define TA9(mt) {6'b010000, mt, 21'b?????_?????_00000000_???}
`define TA10(fn) {26'b010000_1_0000000000000000000, fn}
// Grouped control signals output by decoding table.
// Each macro is used for a bunch of alike instructions.
`define IN_B(sel) {3'b000, sel, 4'h0, 2'd3, TYP_B, P0_X, P1_X, WB_N, OP_NOP}
`define IN_BAL(sel) {3'b000, sel, 4'h0, 2'd3, TYP_B, P0_PCS, P1_0, WB_R, OP_ADD}
`define IN_IH(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_IH, P0_RS1, P1_IMM, WB_R, op}
`define IN_IU(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_IU, P0_RS1, P1_IMM, WB_R, op}
`define IN_Ilx {3'b000, 3'b0, 4'h8, 2'b0, TYP_I, P0_RS1, P1_IMM, WB_R, OP_NOP}
`define IN_Isx {3'b000, 3'b0, 4'h4, 2'b0, TYP_I, P0_RS1, P1_IMM, WB_N, OP_NOP}
`define IN_I(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_I, P0_RS1, P1_IMM, WB_R, op}
`define IN_J(link) {3'b000, 3'b0, 4'h0, 2'd2, TYP_J, P0_PCS, P1_0, link, OP_ADD}
`define IN_IS(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_S, P0_IMM, P1_RS2, WB_R, op}
`define IN_R(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_R, P0_RS1, P1_RS2, WB_R, op}
`define IN_JR {3'b000, 3'b0, 4'h0, 2'b1, TYP_I, P0_PCS, P1_0, WB_N, OP_ADD}
`define IN_CP0(r,w) {3'b001, 3'b0, 4'h0, 2'd0, TYP_I, P0_0, r, w, OP_OR}
`define SPEC(q,r) {q, 3'b0, 3'h0,r, 2'd0, TYP_I, P0_0, P1_X, WB_N, OP_NOP}
`define IN_BAD {3'b000, 3'b0, 4'h0, 2'b0, TYP_BAD, P0_X, P1_X, WB_N, OP_NOP}
// Decoding table.
// TODO A few bits of decoding still done outside this table (see @note7).
always @(*) begin
// FIXME Many instructions missing.
casez (s12r_ir)
`TA2 (6'b000100): s2_m = `IN_B(3'b000); // BEQ
`TA2 (6'b000101): s2_m = `IN_B(3'b001); // BNE
`TA2 (6'b000110): s2_m = `IN_B(3'b010); // BLEZ
`TA2 (6'b000111): s2_m = `IN_B(3'b011); // BGTZ
`TA4 (5'b00000): s2_m = `IN_B(3'b100); // BLTZ
`TA4 (5'b00001): s2_m = `IN_B(3'b101); // BGEZ
`TA4 (5'b10000): s2_m = `IN_BAL(3'b100); // BLTZAL
`TA4 (5'b10001): s2_m = `IN_BAL(3'b101); // BGEZAL
`TA2rs0 (6'b001111): s2_m = `IN_IH(OP_OR); // LUI
`TA2 (6'b001001): s2_m = `IN_I(OP_ADD); // ADDIU
`TA2 (6'b001000): s2_m = `IN_I(OP_ADD); // ADDI
`TA2 (6'b000011): s2_m = `IN_J(WB_R); // JAL
`TA2 (6'b000010): s2_m = `IN_J(WB_N); // J
`TA2 (6'b100000): s2_m = `IN_Ilx; // LB
`TA2 (6'b100100): s2_m = `IN_Ilx; // LBU
`TA2 (6'b100011): s2_m = `IN_Ilx; // LW
`TA2 (6'b100001): s2_m = `IN_Ilx; // LH
`TA2 (6'b100101): s2_m = `IN_Ilx; // LHU
`TA2 (6'b101000): s2_m = `IN_Isx; // SB
`TA2 (6'b101011): s2_m = `IN_Isx; // SW
`TA2 (6'b101001): s2_m = `IN_Isx; // SH
`TA3 (6'b001000): s2_m = `IN_JR; // JR
`TA3 (6'b100000): s2_m = `IN_R(OP_ADD); // ADD
`TA3 (6'b100001): s2_m = `IN_R(OP_ADD); // ADDU @note2
`TA3 (6'b100010): s2_m = `IN_R(OP_SUB); // SUB
`TA3 (6'b100011): s2_m = `IN_R(OP_SUB); // SUBU
`TA3 (6'b101010): s2_m = `IN_R(OP_SLT); // SLT
`TA3 (6'b101011): s2_m = `IN_R(OP_SLTU); // SLTU
`TA2 (6'b001010): s2_m = `IN_I(OP_SLT); // SLTI
`TA2 (6'b001011): s2_m = `IN_IU(OP_SLTU); // SLTIU
`TA3 (6'b100100): s2_m = `IN_R(OP_AND); // AND
`TA3 (6'b100101): s2_m = `IN_R(OP_OR); // OR
`TA3 (6'b100110): s2_m = `IN_R(OP_XOR); // XOR
`TA3 (6'b100111): s2_m = `IN_R(OP_NOR); // NOR
`TA2 (6'b001100): s2_m = `IN_IU(OP_AND); // ANDI
`TA2 (6'b001101): s2_m = `IN_IU(OP_OR); // ORI
`TA2 (6'b001110): s2_m = `IN_IU(OP_XOR); // XORI
`TA3rs0 (6'b000000): s2_m = `IN_IS(OP_SLL); // SLL
`TA3 (6'b000100): s2_m = `IN_R(OP_SLL); // SLLV
`TA3rs0 (6'b000010): s2_m = `IN_IS(OP_SRL); // SRL
`TA3 (6'b000110): s2_m = `IN_R(OP_SRL); // SRLV
`TA3rs0 (6'b000011): s2_m = `IN_IS(OP_SRA); // SRA
`TA3 (6'b000111): s2_m = `IN_R(OP_SRA); // SRAV
`TA9 (5'b00100): s2_m = `IN_CP0(P1_RS2,WB_C);// MTC0
`TA9 (5'b00000): s2_m = `IN_CP0(P1_CSR,WB_R);// MFC0
`TA10 (6'b011000): s2_m = `SPEC(3'b0,1'b1); // ERET
`TA3 (6'b001100): s2_m = `SPEC(3'b010,1'b0); // SYSCALL
`TA3 (6'b001101): s2_m = `SPEC(3'b100,1'b0); // BREAK
default: s2_m = `IN_BAD; // All others
endcase
// Unpack the control signals output by the table.
s2_break_syscall = s2_m[27:26];
s2_cop0_access = s2_m[25];
s2_bxx_cond_sel = s2_m[24:22];
{s2_load_en, s2_store_en} = s2_m[21:20];
{s2_eret, s2_flow_sel, s2_type} = s2_m[19:12];
{s2_p0_sel, s2_p1_sel} = s2_m[11:7];
{s2_wb_en, s2_wb_csr_en, s2_alu_op} = s2_m[6:0];
s2_alu_en = ~(s2_alu_op == OP_NOP);
s2_3reg = (s2_type==TYP_R) | (s2_type == TYP_P) | (s2_type == TYP_S);
s2_link = (s2_p0_sel==P0_PCS) & s2_wb_en;
end
// Extract some common instruction fields including immediate field.
always @(*) begin
s2_opcode = s12r_ir[27:26];
s2_rs1_index = s12r_ir[25:21];
s2_rs2_index = s12r_ir[20:16];
s2_rd_index = s2_link? 5'b11111 : s2_3reg? s12r_ir[15:11] : s12r_ir[20:16];
s2_csr_index = {s12r_ir[15:11], s12r_ir[2:0]};
// Decode immediate field.
s2_j_immediate = {s01r_pc[31:28], s12r_ir[25:0], 2'b00};
s2_b_immediate = {{14{s12r_ir[15]}}, s12r_ir[15:0], 2'b00};
s2_i_immediate = {{16{s12r_ir[15]}}, s12r_ir[15:0]};
s2_iu_immediate = {16'h0, s12r_ir[15:0]};
s2_ih_immediate = {s12r_ir[15:0], 16'h0};
s2_s_immediate = {27'h0, s12r_ir[10:6]};
s2_e_immediate = {12'h0, s12r_ir[25:6]};
s2_t_immediate = {22'h0, s12r_ir[15:6]};
case (s2_type)
TYP_M,
TYP_I: s2_immediate = s2_i_immediate;
TYP_S: s2_immediate = s2_s_immediate;
TYP_IH: s2_immediate = s2_ih_immediate;
TYP_IU: s2_immediate = s2_iu_immediate;
default: s2_immediate = s2_i_immediate;
endcase
case (s2_type)
TYP_E: s2_cop_imm = s2_e_immediate;
default: s2_cop_imm = s2_t_immediate;
endcase
end
// Register bank read ports.
always @(*) begin
s2_rs1_bank = (s2_rs1_index == 5'd0)? 32'd0 : s42r_rbank[s2_rs1_index];
s2_rs2_bank = (s2_rs2_index == 5'd0)? 32'd0 : s42r_rbank[s2_rs2_index];
end
// Feedforward mux.
always @(*) begin
s2_rs1 = co_dhaz_rs1_s3? s3_alu_res : co_dhaz_rs1_s4? s4_wb_data : s2_rs1_bank;
s2_rs2 = co_dhaz_rs2_s3? s3_alu_res : co_dhaz_rs2_s4? s4_wb_data : s2_rs2_bank;
end
// CSR bank multiplexors.
always @(*) begin
// Translation of CSR address to CSR implementation index for writeback.
// (We only need to translate indices of implemented writeable regs.)
case (s2_csr_index)
8'b01011_000: s2_csr_xindex = CSRB_MCOMPARE;
8'b01100_000: s2_csr_xindex = CSRB_MSTATUS;
8'b01101_000: s2_csr_xindex = CSRB_MCAUSE;
8'b01110_000: s2_csr_xindex = CSRB_MEPC;
8'b10000_000: s2_csr_xindex = CSRB_MCONFIG0;
8'b11110_000: s2_csr_xindex = CSRB_MERROREPC;
default: s2_csr_xindex = 4'b1111; // CSR WB does nothing.
endcase
// CSR read multiplexor.
case (s2_csr_index)
8'b01011_000: s2_csr = s42r_csr_MCOMPARE;
8'b01100_000: s2_csr = `STATUS_UNPACK(s42r_csr_MSTATUS);
8'b01101_000: s2_csr = `CAUSE_UNPACK(s42r_csr_MCAUSE);
8'b01110_000: s2_csr = s42r_csr_MEPC;
8'b01111_000: s2_csr = FEATURE_PRID;
8'b10000_000: s2_csr = FEATURE_CONFIG0;
8'b10000_001: s2_csr = FEATURE_CONFIG1;
8'b11110_000: s2_csr = s42r_csr_MERROREPC;
default: s2_csr = 32'h00000000; // Value for unimplemented CSRs.
endcase
end
// Branch condition logic.
always @(*) begin
s2_rs12_equal = (s2_rs1 == s2_rs2);
case (s2_bxx_cond_sel)
3'b000: s2_bxx_cond_val = s2_rs12_equal; // BEQ
3'b001: s2_bxx_cond_val = ~s2_rs12_equal; // BNE
3'b010: s2_bxx_cond_val = s2_rs1[31] | ~(|s2_rs1); // BLEZ
3'b011: s2_bxx_cond_val = ~s2_rs1[31] & (|s2_rs1); // BGTZ
3'b100: s2_bxx_cond_val = s2_rs1[31]; // BLTZ
3'b101: s2_bxx_cond_val = ~s2_rs1[31] | ~(|s2_rs1); // BGEZ
default:s2_bxx_cond_val = s2_rs12_equal; // Don't care case.
endcase
end
// Branch/sequential PC selection logic.
always @(*) begin
// Mux: either sequential or TRAP or ERET -- All SW driven.
s2_pc_trap_eret = (s2_trap|s2_hw_trap)? OPTION_TRAP_ADDR : s42r_csr_MEPC;
s2_pc_branch = s12r_pc_seq + s2_b_immediate;
s2_pc_jump = s2_j_immediate;
s2_pc_jalr = s2_rs1;
// Final PC change mux. Includes branch cond evaluation and HW-driven TRAPs.
s2_go_seq = 1'b0;
casez ({(s2_trap|s2_hw_trap|s2_eret),s2_bxx_cond_val,s2_flow_sel})
4'b1???: s2_pc_nonseq = s2_pc_trap_eret;
4'b0?01: s2_pc_nonseq = s2_pc_jalr;
4'b0?10: s2_pc_nonseq = s2_pc_jump;
4'b0111: s2_pc_nonseq = s2_pc_branch;
default: begin
s2_pc_nonseq = s2_pc_trap_eret;
s2_go_seq = 1'b1; // meaning no jump at all.
end
endcase
end
// ALU input & function code selection.
always @(*) begin
case (s2_p0_sel)
P0_0: s2_arg0 = 32'h0;
P0_RS1: s2_arg0 = s2_rs1;
P0_PCS: s2_arg0 = s01r_pc_seq; // JAL (-> instr after delay slot)
P0_PC: s2_arg0 = s12r_pc; // AUIPC
P0_IMM: s2_arg0 = s2_immediate; // Shift instructions
default: s2_arg0 = 32'h0;
endcase
case (s2_p1_sel)
P1_0: s2_arg1 = 32'h0;
P1_IMM: s2_arg1 = s2_immediate;
P1_RS2: s2_arg1 = s2_rs2;
P1_CSR: s2_arg1 = s2_csr;
default: s2_arg1 = 32'h0;
endcase
end
// Interrupt. (@note5)
always @(*) begin
s2_ie = `STATUS_IE & ~(`STATUS_ERL | `STATUS_EXL);
// TODO timer interrupt request missing.
s2_masked_irq = {1'b0, HWIRQ_I, `CAUSE_IPSW} & `STATUS_IM;
s2_irq_final = |(s2_masked_irq) & s2_ie;
s2_hw_trap = s2_irq_final; // Our only HW trap so far in stages 0..2.
end
// Trap logic.
always @(*) begin
s2_user_mode = {`STATUS_UM,`STATUS_ERL,`STATUS_EXL}==3'b100;
s2_trap_cop_unusable = s2_cop0_access & s2_user_mode;
// Encode trap cause as per table 9.31 in arch manual vol 3.
casez ({s2_irq_final,s2_trap_cop_unusable,s2_break_syscall})
4'b1???: s2_excode = 5'b00000; // Int -- Interrupt.
4'b01??: s2_excode = 5'b01011; // CpU -- Coprocessor unusable.
4'b0010: s2_excode = 5'b01001; // Bp -- Breakpoint.
4'b0001: s2_excode = 5'b01000; // Sys -- Syscall.
default: s2_excode = 5'b00000; // Don't care.
endcase
// Final trap OR.
s2_trap = (|s2_break_syscall) | s2_trap_cop_unusable | s2_irq_final;
// All the cases where we'll want to abort the 'next' instruction.
s2_skip_seq_instr = s2_trap | s2_hw_trap | s2_eret;
end
// MEM control logic.
always @(*) begin
s2_mem_addr_imm = s2_i_immediate;
s2_mem_addr = s2_rs1 + s2_mem_addr_imm;
s2_mem_trans = (s2_load_en | s2_store_en)? 2'b10 : 2'b00; // NONSEQ.
s2_load_exz = s12r_ir[28]; // @note7.
case (s2_opcode[1:0]) // @note7.
2'b00: s2_mem_size = 2'b00;
2'b01: s2_mem_size = 2'b01;
2'b10: s2_mem_size = 2'b10;
default: s2_mem_size = 2'b10;
endcase
case (s2_mem_size)
2'b00: s2_mem_wdata = {4{s2_rs2[ 7: 0]}};
2'b01: s2_mem_wdata = {2{s2_rs2[15: 0]}};
default: s2_mem_wdata = s2_rs2;
endcase
end
// DE-EX pipeline registers.
`PREG (s2_st, s23r_en, 1'b0, 1'b1, s2_en)
`PREG (s2_st, s23r_arg0, 32'h0, s2_en, s2_arg0)
`PREG (s2_st, s23r_arg1, 32'h0, s2_en, s2_arg1)
`PREGC(s2_st, s23r_wb_en, 1'b0, s2_en, s2_wb_en & ~s2_trap)
`PREG (s2_st, s23r_rd_index, 5'd0, s2_en & s2_wb_en, s2_rd_index)
`PREG (s2_st, s23r_alu_op, 5'd0, s2_en & s2_alu_en, s2_alu_op)
`PREG (s2_st, s23r_mem_addr, 32'h0, s2_en, s2_mem_addr)
`PREGC(s2_st, s23r_store_en, 1'b0, s2_en, s2_store_en /* & ~s2_trap*/)
`PREGC(s2_st, s23r_load_en, 1'b0, s2_en, s2_load_en & ~s2_trap)
`PREG (s2_st, s23r_mem_wdata, 32'h0, s2_en, s2_mem_wdata)
`PREG (s2_st, s23r_mem_size, 2'b0, s2_en, s2_mem_size)
`PREGC(s2_st, s23r_mem_trans, 2'b0, s2_en, s2_mem_trans)
`PREG (s2_st, s23r_load_exz, 1'b0, s2_en, s2_load_exz)
`PREG (s2_st, s23r_csr_xindex, 4'd0, s2_en & s2_wb_csr_en, s2_csr_xindex)
`PREGC(s2_st, s23r_wb_csr_en, 1'b0, s2_en, s2_wb_csr_en & ~s2_trap)
`PREGC(s2_st, s23r_trap, 1'd0, s2_en, s2_trap)
`PREGC(s2_st, s23r_eret, 1'd0, s2_en, s2_eret)
`PREG (s2_st, s23r_epc, 32'h0, s2_en & s2_trap, s12r_pc)
`PREG (s2_st, s23r_excode, 5'd0, s2_en & s2_trap, s2_excode)
//==== Pipeline stage Execute ==============================================
// Combinational ALU logic / address phase of MEM cycle.
reg s3_en; // EX stage enable.
reg s34r_en; // WB stage enable carried from EX stage.
reg [31:0] s3_alu_res; // Final ALU result.
reg [31:0] s34r_alu_res; // ALU result in WB stage.
reg s34r_wb_en; // Writeback enable for reg bank.
reg [4:0] s34r_rd_index; // Writeback register index.
reg s34r_load_en; // MEM load.
reg [31:0] s34r_mem_wdata; // MEM store data.
reg [1:0] s34r_mem_size; // 2 LSBs of MEM op size for LOAD data mux.
reg [1:0] s34r_mem_addr; // 2 LSBs of MEM address for LOAD data mux.
reg s34r_load_exz; // 1 if MEM subword load zero-extends to word.
reg s34r_wb_csr_en; // WB enable for CSR bank.
reg [3:0] s34r_csr_xindex; // CSR WB target (translated index).
reg s34r_trap; // TRAP event CSR control passed on to WB.
reg s34r_eret; // ERET event CSR control passed on to WB.
reg [4:0] s34r_excode; // Trap cause code passed on to WB.
reg [31:0] s34r_epc; // Next EPC to be passed on to next stages.
reg [32:0] s3_arg0_ext; // ALU arg0 extended for arith ops.
reg [32:0] s3_arg1_ext; // ALU arg1 extended for arith ops.
reg [32:0] s3_alu_addsub; // Add/sub intermediate result.
reg [31:0] s3_alu_arith; // Arith (+/-/SLT*) intermediate result.
reg [31:0] s3_alu_logic; // Logic intermediate result.
reg [31:0] s3_alu_shift; // Shift intermediate result.
reg [31:0] s3_alu_noarith; // Mux for shift/logic interm-results.
reg s3_mem_pending; // Data bus cycle pending.
reg s34r_mem_pending; // Data bus cycle pending.
// DATA AHB outputs driven directly by S2/3 pipeline registers.
assign DADDR_O = s23r_mem_addr;
assign DTRANS_O = s23r_mem_trans;
assign DSIZE_O = s23r_mem_size;
assign DWRITE_O = s23r_store_en;
// Stage bubble logic.
always @(*) begin
s3_en = s23r_en;
s3_mem_pending = (s23r_load_en | s23r_store_en) | (s34r_mem_pending & ~DREADY_I);
end
// Remember if there's a bus cycle in progress.
`PREG (1'b0, s34r_mem_pending, 0, 1, s3_mem_pending)
// ALU.
always @(*) begin
s3_arg0_ext[31:0] = s23r_arg0;
s3_arg0_ext[32] = s23r_alu_op[1]? 1'b0 : s23r_arg0[31];
s3_arg1_ext[31:0] = s23r_arg1;
s3_arg1_ext[32] = s23r_alu_op[1]? 1'b0 : s23r_arg1[31];
s3_alu_addsub = s23r_alu_op[0]?
s3_arg0_ext - s3_arg1_ext :
s3_arg0_ext + s3_arg1_ext;
case (s23r_alu_op[2:1])
2'b10,
2'b11: s3_alu_arith = {31'h0, s3_alu_addsub[32]};
default: s3_alu_arith = s3_alu_addsub[31:0];
endcase
case (s23r_alu_op[1:0])
2'b00: s3_alu_shift = s23r_arg1 << s23r_arg0[4:0];
2'b10: s3_alu_shift = s23r_arg1 >> s23r_arg0[4:0];
default: s3_alu_shift = $signed(s23r_arg1) >>> s23r_arg0[4:0];
endcase
case (s23r_alu_op[1:0])
2'b00: s3_alu_logic = s23r_arg0 | s23r_arg1;
2'b01: s3_alu_logic = s23r_arg0 & s23r_arg1;
2'b10: s3_alu_logic = s23r_arg0 ^ s23r_arg1;
default: s3_alu_logic = ~(s23r_arg0 | s23r_arg1);
endcase
s3_alu_noarith = s23r_alu_op[3]? s3_alu_logic : s3_alu_shift;
s3_alu_res = s23r_alu_op[4]? s3_alu_arith : s3_alu_noarith;
end
// EX-WB pipeline registers.
`PREG (1'b0, s34r_en, 1'b0, 1'b1, s3_en)
`PREG (s3_st, s34r_alu_res, 32'h0, s3_en, s3_alu_res)
`PREGC(s3_st, s34r_wb_en, 1'b0, s3_en, s23r_wb_en)
`PREG (s3_st, s34r_rd_index, 5'd0, s3_en, s23r_rd_index)
`PREGC(s3_st, s34r_load_en, 1'b0, s3_en, s23r_load_en)
`PREG (s3_st, s34r_mem_size, 2'b00, s3_en, s23r_mem_size)
`PREG (s3_st, s34r_mem_addr, 2'b00, s3_en, s23r_mem_addr[1:0])
`PREG (s3_st, s34r_load_exz, 1'b0, s3_en, s23r_load_exz)
`PREG (s3_st, s34r_csr_xindex, 4'd0, s3_en & s23r_wb_csr_en, s23r_csr_xindex)
`PREG (s3_st, s34r_wb_csr_en, 1'b0, s3_en, s23r_wb_csr_en)
`PREG (s3_st, s34r_mem_wdata, 32'h0, s3_en & s23r_store_en, s23r_mem_wdata)
`PREGC(s3_st, s34r_trap, 1'd0, s3_en, s23r_trap)
`PREGC(s3_st, s34r_eret, 1'd0, s3_en, s23r_eret)
`PREG (s3_st, s34r_epc, 32'h0, s3_en & s23r_trap, s23r_epc)
`PREG (s3_st, s34r_excode, 5'd0, s3_en & s23r_trap, s23r_excode)
//==== Pipeline stage Writeback ============================================
// Writeback selection logic / data phase of MEM cycle.
reg s4_en; // EX stage enable.
reg [31:0] s4_load_data; // Data from MEM load.
reg [31:0] s4_wb_data; // Writeback data (ALU or MEM).
reg [4:0] s4_excode; // Cause code to load in MCAUSE CSR.
reg [16:0] s4_cause_trap; // Value to load on packed CAUSE reg on traps.
reg [12:0] s4_status_trap; // Value to load on MSTATUS CSR on trap.
reg [31:0] s4r_drdata;
reg s4_mem_truncated;
reg s42r_mem_truncated;
assign DWDATA_O = s34r_mem_wdata;
always @(*) begin
s4_mem_truncated = s4_st & DREADY_I;
//s4r_drdata = s42r_mem_truncated? s12r_irs : DRDATA_I;
end
`PREG (1'b0, s4r_drdata, 32'h0, s4_mem_truncated & ~s42r_mem_truncated, DRDATA_I)
`PREG (1'b0, s42r_mem_truncated, 1'b0, 1'b1, s4_mem_truncated)
// Mux for load data byte lanes.
always @(*) begin
case ({s34r_mem_size, s34r_mem_addr})
4'b0011: s4_load_data = s4r_drdata[7:0];
4'b0010: s4_load_data = s4r_drdata[15:8];
4'b0001: s4_load_data = s4r_drdata[23:16];
4'b0000: s4_load_data = s4r_drdata[31:24];
4'b0110: s4_load_data = s4r_drdata[15:0];
4'b0100: s4_load_data = s4r_drdata[31:16];
default: s4_load_data = s4r_drdata;
endcase
if (~s34r_load_exz) begin
case (s34r_mem_size)
2'b00: s4_load_data[31:8] = {24{s4_load_data[7]}};
2'b01: s4_load_data[31:16] = {16{s4_load_data[15]}};
endcase
end
end
always @(*) begin
s4_en = s34r_en;
// FIXME ready/split ignored
s4_wb_data = s34r_load_en? s4_load_data : s34r_alu_res;
// TODO traps caught in WB stage missing.
s4_excode = s34r_excode;
end
// Register bank write port.
always @(posedge CLK) begin
if (s4_en & ~s4_st & s34r_wb_en) begin
s42r_rbank[s34r_rd_index] <= s4_wb_data;
end
end
// CSR input logic. These values are only used if the CSR is not loaded
// using MTC0, see macros CSREGT and CSREG.
always @(*) begin
// STATUS logic: flags modified by TRAP/ERET.
s4_status_trap = s42r_csr_MSTATUS;
casez ({s34r_trap, s34r_eret})
2'b1?: begin // TRAP | (TRAP & ERET)
s4_status_trap[1] = 1'b1; // EXL = 0
end
2'b01: begin // ERET
if (`STATUS_ERL) begin
s4_status_trap[2] = 1'b0; // ERL = 0
end
else begin
s4_status_trap[1] = 1'b0; // EXL = 0
end
end
default:; // No change to STATUS flags.
endcase
// FIXME Cause BC, CE, IV fields h-wired to zero.
// FIXME loading interrupts from stage 2!
s4_cause_trap = {1'b0,2'b00,1'b0, s2_masked_irq, s4_excode};
end
// CSR 'writeback ports'.
`CSREGT(s4_st, MCAUSE, 17'h0, s34r_trap, s4_cause_trap, `CAUSE_PACK(s34r_alu_res))
`CSREGT(s4_st, MEPC, 32'h0, s34r_trap, s34r_epc, s34r_alu_res)
`CSREGT(s4_st, MERROREPC, 32'h0, s34r_trap, s34r_epc, s34r_alu_res)
`CSREGT(s4_st, MSTATUS, 13'h1004, s34r_trap|s34r_eret, s4_status_trap, `STATUS_PACK(s34r_alu_res))
`CSREG (s4_st, MCOMPARE)
//==== Control logic =======================================================
reg co_dhaz_rs1_s3; // S3 wb matches rs1 read.
reg co_dhaz_rs2_s3; // S3 wb matches rs2 read.
reg co_dhaz_rs1_s4; // S4 wb matches rs1 read.
reg co_dhaz_rs2_s4; // S4 wb matches rs2 read.
reg co_dhaz_rs1_ld; // S3vload matches rs1 read.
reg co_dhaz_rs2_ld; // S3vload matches rs2 read.
reg co_s2_stall_load; // Decode stage stall, by load hazard.
reg co_s2_stall_trap; // Decode stage stall, SW trap.
reg co_s012_stall_eret; // Stages 0..2 stall, ERET.
reg co_sx_code_wait; // Code fetch stall.
reg co_sx_data_wait; // Data cycle stall.
// TODO this block will be tidied up when the logic is done.
always @(*) begin
// Data hazard: instr. on stage 3 will write on reg used in stage 2.
co_dhaz_rs1_s3 = (s3_en & s23r_wb_en & (s23r_rd_index==s2_rs1_index));
co_dhaz_rs2_s3 = (s3_en & s23r_wb_en & (s23r_rd_index==s2_rs2_index));
// Data hazard: instr on stage 4 will write on reg used in stage 2.
co_dhaz_rs1_s4 = (s4_en & s34r_wb_en & (s34r_rd_index==s2_rs1_index));
co_dhaz_rs2_s4 = (s4_en & s34r_wb_en & (s34r_rd_index==s2_rs2_index));
// Load data hazard: instr. on stage 3 will load data used in stage 2.
co_dhaz_rs1_ld = (s3_en & s23r_load_en & (s23r_rd_index==s2_rs1_index));
co_dhaz_rs2_ld = (s3_en & s23r_load_en & (s23r_rd_index==s2_rs2_index));
// Stall S0..2 while load data hazard is resolved.
co_s2_stall_load = (co_dhaz_rs1_ld | co_dhaz_rs2_ld);
// Stall S0..2 until trap bubble propagates from to S4. @note3.
co_s2_stall_trap = s23r_trap & s4_en;
// Stall S0..2 & bubble S3..4 until eret bubble propagates to S4. @note4.
co_s012_stall_eret = s23r_eret & s4_en;
// Stall S0..2 & bubble S3..4 while code bus is waited.
co_sx_code_wait = s01r_pending & ~CREADY_I;
co_sx_data_wait = s34r_mem_pending & ~DREADY_I;
// See @note11 on bubbles vs. stalls.
// S2 will bubble on load, trap and eret stalls, and on fetch waits.
co_s2_bubble = co_s2_stall_load | co_s2_stall_trap | co_s012_stall_eret | co_sx_code_wait;
// S1 will bubble on eret and trap stalls AND when the next seq instruction
// needs to be skipped for other reasons. @note8.
co_s1_bubble = co_s2_stall_trap | co_s012_stall_eret | s2_skip_seq_instr;
// S0 bubbles (won't initiate new code fetches) on data waits only.
co_s0_bubble = co_sx_data_wait; // @@@ IN-PROGRESS
// Stall logic. A bunch of OR gates whose truth table is declared
// procedurally, please note the order of the assignments. See @note10.
s4_st = 1'b0 | co_sx_data_wait;
s3_st = s4_st;
s2_st = s3_st | co_s012_stall_eret | co_s2_stall_load | co_s2_stall_trap | co_sx_code_wait;
s1_st = s2_st;
s0_st = s1_st;
end
endmodule |
module id_ex_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`ALU_OPERATOR_BUS] id_operator,
input wire[`ALU_CATEGORY_BUS] id_category,
input wire[`REGS_DATA_BUS] id_operand1,
input wire[`REGS_DATA_BUS] id_operand2,
input wire[`REGS_ADDR_BUS] id_write_addr,
input wire id_write_enable,
input wire[`REGS_DATA_BUS] id_return_target,
input wire id_is_curr_in_delayslot,
input wire input_is_next_in_delayslot,
input wire[`REGS_DATA_BUS] id_instruction,
output reg[`ALU_OPERATOR_BUS] ex_operator,
output reg[`ALU_CATEGORY_BUS] ex_category,
output reg[`REGS_DATA_BUS] ex_operand1,
output reg[`REGS_DATA_BUS] ex_operand2,
output reg[`REGS_ADDR_BUS] ex_write_addr,
output reg ex_write_enable,
output reg[`REGS_DATA_BUS] ex_return_target,
output reg ex_is_curr_in_delayslot,
output reg is_curr_in_delayslot,
output reg[`REGS_DATA_BUS] ex_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
ex_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but I used 0
ex_category <= 0; // FIXME: EXE_RES_NOP should be used here, but I used 0
ex_operand1 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_write_enable <= `DISABLE;
ex_return_target <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_is_curr_in_delayslot <= `FALSE;
is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
end else if (stall[2] == `ENABLE && stall[3] == `DISABLE) begin
ex_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but I used 0
ex_category <= 0; // FIXME: EXE_RES_NOP should be used here, but I used 0
ex_operand1 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_write_enable <= `DISABLE;
ex_return_target <= 0;
ex_is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
end else if (stall[2] == `DISABLE) begin
ex_operator <= id_operator;
ex_category <= id_category;
ex_operand1 <= id_operand1;
ex_operand2 <= id_operand2;
ex_write_addr <= id_write_addr;
ex_write_enable <= id_write_enable;
ex_return_target <= id_return_target;
ex_is_curr_in_delayslot <= id_is_curr_in_delayslot;
is_curr_in_delayslot <= input_is_next_in_delayslot;
ex_instruction <= id_instruction;
end
end
endmodule |
module Controlador_Menu_Editor(
clk,
reset,
boton_arriba_in,
boton_abajo_in,
boton_izq_in,
boton_der_in,
boton_elige_in,
//boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige,
text_red,
text_green,
text_blue,
char_scale,
es_mayuscula,
text_red_temp,
text_green_temp,
text_blue_temp,
char_scale_temp,
es_mayuscula_temp,
nuevo,
guardar,
cerrar,
where_fila,
where_columna
);
input clk, reset;
input boton_arriba_in, boton_abajo_in, boton_izq_in, boton_der_in, boton_elige_in;
wire boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige;
Navegador_PushButtons nav_pb(
.clk_100Mhz (clk),
.boton_arriba_in (boton_arriba_in),
.boton_abajo_in (boton_abajo_in),
.boton_izq_in (boton_izq_in),
.boton_der_in (boton_der_in),
.boton_elige_in (boton_elige_in),
.boton_arriba_out (boton_arriba),
.boton_abajo_out (boton_abajo),
.boton_izq_out (boton_izq),
.boton_der_out (boton_der),
.boton_elige_out (boton_elige)
);
output reg [2:0] where_fila;
output reg [2:0] where_columna;
output reg [9:0] char_scale;
output wire [9:0] char_scale_temp;
output reg text_red, text_green, text_blue, es_mayuscula;
output wire text_red_temp, text_green_temp, text_blue_temp, es_mayuscula_temp;
output reg nuevo, guardar, cerrar;
assign text_red_temp = (where_fila == 5 && where_columna == 1)? 0 :
(where_fila == 5 && where_columna == 2)? 0 :
(where_fila == 5 && where_columna == 3)? 0 :
(where_fila == 5 && where_columna == 4)? 1 :
(where_fila == 5 && where_columna == 5)? 1 :
(where_fila == 5 && where_columna == 6)? 1 : 0;
assign text_green_temp = (where_fila == 5 && where_columna == 1)? 0 :
(where_fila == 5 && where_columna == 2)? 1 :
(where_fila == 5 && where_columna == 3)? 1 :
(where_fila == 5 && where_columna == 4)? 0 :
(where_fila == 5 && where_columna == 5)? 0 :
(where_fila == 5 && where_columna == 6)? 1 : 0;
assign text_blue_temp = (where_fila == 5 && where_columna == 1)? 1 :
(where_fila == 5 && where_columna == 2)? 0 :
(where_fila == 5 && where_columna == 3)? 1 :
(where_fila == 5 && where_columna == 4)? 0 :
(where_fila == 5 && where_columna == 5)? 1 :
(where_fila == 5 && where_columna == 6)? 0 : 1;
assign es_mayuscula_temp = (where_fila == 4 && where_columna == 2)? 0 : 1;
assign char_scale_temp = (where_fila == 6 && where_columna == 1)? 10'd1 :
(where_fila == 6 && where_columna == 2)? 10'd2 :
(where_fila == 6 && where_columna == 3)? 10'd3 :
10'd2;
initial begin
where_fila <= 1;
where_columna <= 1;
char_scale <= 10'd2;
text_red <= 1'b0;
text_green <= 1'b0;
text_blue <= 1'b1;
es_mayuscula <= 1'b1;
nuevo <= 1'b0;
guardar <= 1'b0;
cerrar <= 1'b0;
end
wire temp_clk;
assign temp_clk = (boton_abajo || boton_izq || boton_arriba || boton_der || boton_elige);
reg [2:0] estado, sigEstado;
parameter inicio = 0;
parameter aumenta_fila = 1;
parameter disminuye_fila = 2;
parameter aumenta_columna = 3;
parameter disminuye_columna = 4;
parameter elige = 5;
always @(posedge clk or posedge reset) begin
if (reset)
estado <= inicio;
else
estado <= sigEstado;
end
always @(posedge temp_clk) begin
case (estado)
inicio:
begin
if (boton_arriba)
sigEstado = disminuye_columna;
else if (boton_abajo)
sigEstado = aumenta_columna;
else if (boton_izq)
sigEstado = disminuye_fila;
else if (boton_der)
sigEstado = aumenta_fila;
else if (boton_elige)
sigEstado = elige;
else
sigEstado = inicio;
end
aumenta_fila:
begin
nuevo = 0;
where_columna = 1;
where_fila = (where_fila < 6)? where_fila + 1 : where_fila;
sigEstado = inicio;
end
disminuye_fila:
begin
where_columna = 1;
where_fila = (where_fila > 1)? where_fila - 1 : where_fila;
sigEstado = inicio;
end
aumenta_columna:
begin
case (where_fila)
4:
where_columna = (where_columna < 2)? where_columna + 1: where_columna;
5:
where_columna = (where_columna < 6)? where_columna + 1: where_columna;
6:
where_columna = (where_columna < 3)? where_columna + 1: where_columna;
endcase
sigEstado = inicio;
end
disminuye_columna:
begin
where_columna = (where_columna > 1)? where_columna - 1 : where_columna;
sigEstado = inicio;
end
elige:
begin
case (where_fila)
1:
nuevo = 1;
2:
guardar = 1;
3:
cerrar = 1;
4:
begin
case (where_columna)
1:
es_mayuscula = 1;
2:
es_mayuscula = 0;
endcase
end
5:
begin
case (where_columna)
1:
begin
text_red = 0;
text_green = 0;
text_blue = 1;
end
2:
begin
text_red = 0;
text_green = 1;
text_blue = 0;
end
3:
begin
text_red = 0;
text_green = 1;
text_blue = 1;
end
4:
begin
text_red = 1;
text_green = 0;
text_blue = 0;
end
5:
begin
text_red = 1;
text_green = 0;
text_blue = 1;
end
6:
begin
text_red = 1;
text_green = 1;
text_blue = 0;
end
endcase
end
6:
begin
case (where_columna)
1:
char_scale = 10'd1;
2:
char_scale = 10'd2;
3:
char_scale = 10'd3;
endcase
end
endcase
sigEstado = inicio;
end
default: sigEstado = inicio;
endcase
end
endmodule |
module MULT (
dataa,
result);
input [12:0] dataa;
output [25:0] result;
wire [25:0] sub_wire0;
wire [25:0] result = sub_wire0[25:0];
altsquare altsquare_component (
.data (dataa),
.result (sub_wire0),
.aclr (1'b0),
.clock (1'b1),
.ena (1'b1));
defparam
altsquare_component.data_width = 13,
altsquare_component.lpm_type = "ALTSQUARE",
altsquare_component.pipeline = 0,
altsquare_component.representation = "SIGNED",
altsquare_component.result_width = 26;
endmodule |
module latch_id_ex(
input clock ,
input reset ,
input [ 5:0] stall ,
input [31:0] id_instruction ,
output reg [31:0] ex_instruction ,
input [ 7:0] id_operator ,
output reg [ 7:0] ex_operator ,
input [ 2:0] id_category ,
output reg [ 2:0] ex_category ,
input [31:0] id_operand_a ,
output reg [31:0] ex_operand_a ,
input [31:0] id_operand_b ,
output reg [31:0] ex_operand_b ,
input id_register_write_enable ,
output reg ex_register_write_enable ,
input [ 4:0] id_register_write_address,
output reg [ 4:0] ex_register_write_address,
input [31:0] id_register_write_data ,
output reg [31:0] ex_register_write_data
);
always @ (posedge clock) begin
if (reset == `RESET_ENABLE || (stall[2] == `STALL_ENABLE && stall[3] == `STALL_DISABLE)) begin
ex_instruction <= 32'b0 ;
ex_operator <= `OPERATOR_NOP ;
ex_category <= `CATEGORY_NONE;
ex_operand_a <= 32'b0 ;
ex_operand_b <= 32'b0 ;
ex_register_write_enable <= `WRITE_DISABLE;
ex_register_write_address <= 32'b0 ;
ex_register_write_data <= 32'b0 ;
end
else if (stall[2] == `STALL_DISABLE) begin
ex_instruction <= id_instruction ;
ex_operator <= id_operator ;
ex_category <= id_category ;
ex_operand_a <= id_operand_a ;
ex_operand_b <= id_operand_b ;
ex_register_write_enable <= id_register_write_enable ;
ex_register_write_address <= id_register_write_address;
ex_register_write_data <= id_register_write_data ;
end
end
endmodule |
module (provides software interface to UART)
uart_ctrl uart_ctrl (
.clk(clk),
.reset_(reset_),
.tx(tx),
.rx(rx),
.addr(addr),
.cs(uart_cs),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.rd_data(uart_rd_data),
.rdy(uart_rdy)
);
// Xilinx MicroBlaze CPU core
microblaze_mcs_v1_4 mcs_0 (
.Clk(clk), // input Clk
.Reset(~reset_), // input Reset
.IO_Addr_Strobe(), // output IO_Addr_Strobe
.IO_Read_Strobe(mcs_rd_enable), // output IO_Read_Strobe
.IO_Write_Strobe(mcs_wr_enable), // output IO_Write_Strobe
.IO_Address(mcs_addr), // output [31 : 0] IO_Address
.IO_Byte_Enable(mcs_byte_enable), // output [3 : 0] IO_Byte_Enable
.IO_Write_Data(mcs_wr_data), // output [31 : 0] IO_Write_Data
.IO_Read_Data(mcs_rd_data), // input [31 : 0] IO_Read_Data
.IO_Ready(mcs_ready) // input IO_Ready
);
endmodule |
module sky130_fd_sc_hd__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A)
);
endmodule |
module qrs_refinement1(q_begin_ref,s_end_ref,q_begin_l3_temp,s_end_l3_temp,q_begin_l3,s_end_l3,s_end_l3_flag,
count1,count2,clk,nReset,swindow1_full,qwindow1_full,
q_begin_l3_flag);
output [15:0] q_begin_ref,s_end_ref,q_begin_l3_temp
,s_end_l3_temp;
reg signed [15:0] q_begin_ref,s_end_ref,q_begin_l3_temp,
s_end_l3_temp;
input [15:0] q_begin_l3,s_end_l3;
input swindow1_full,qwindow1_full,s_end_l3_flag,q_begin_l3_flag;
input [3:0] count1;
input [8:0] count2;
input clk, nReset;
wire clk, nReset;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
q_begin_ref <= #20 0;
s_end_ref <= #20 0;
q_begin_l3_temp <= #20 0;
s_end_l3_temp <= #20 0;
end
else
begin
if (count1 == 2 && count2 == 1)
begin
if (qwindow1_full != 0)
begin
if (q_begin_l3_flag != 0)
q_begin_l3_temp <= #20 (q_begin_l3-(8*`rat));
else
q_begin_l3_temp <= #20 q_begin_l3_temp;
end
else
begin
q_begin_l3_temp <= #20 q_begin_l3_temp;
end
q_begin_ref <= #20 q_begin_l3_temp << `shift3;
if (swindow1_full != 0)
begin
if (s_end_l3_flag != 0)
s_end_l3_temp <= #20 (s_end_l3+(15*`rat));
else
s_end_l3_temp <= #20 s_end_l3_temp;
end
else
begin
s_end_l3_temp <= #20 s_end_l3_temp;
end
s_end_ref <= #20 s_end_l3_temp << `shift3;
end
else
begin
q_begin_ref <= #20 q_begin_ref;
s_end_ref <= #20 s_end_ref;
q_begin_l3_temp <= #20 q_begin_l3_temp;
s_end_l3_temp <= #20 s_end_l3_temp;
end
end
endmodule |
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n912, n913, n914, n915, n916, n917, n918, n919,
DP_OP_15J35_125_2314_n8, DP_OP_15J35_125_2314_n7,
DP_OP_15J35_125_2314_n6, DP_OP_15J35_125_2314_n5,
DP_OP_15J35_125_2314_n4, intadd_38_B_12_, intadd_38_B_11_,
intadd_38_B_10_, intadd_38_B_9_, intadd_38_B_8_, intadd_38_B_7_,
intadd_38_B_6_, intadd_38_B_5_, intadd_38_B_4_, intadd_38_B_3_,
intadd_38_B_2_, intadd_38_B_1_, intadd_38_B_0_, intadd_38_CI,
intadd_38_SUM_12_, intadd_38_SUM_11_, intadd_38_SUM_10_,
intadd_38_SUM_9_, intadd_38_SUM_8_, intadd_38_SUM_7_,
intadd_38_SUM_6_, intadd_38_SUM_5_, intadd_38_SUM_4_,
intadd_38_SUM_3_, intadd_38_SUM_2_, intadd_38_SUM_1_,
intadd_38_SUM_0_, intadd_38_n13, intadd_38_n12, intadd_38_n11,
intadd_38_n10, intadd_38_n9, intadd_38_n8, intadd_38_n7, intadd_38_n6,
intadd_38_n5, intadd_38_n4, intadd_38_n3, intadd_38_n2, intadd_38_n1,
intadd_39_A_1_, intadd_39_B_2_, intadd_39_B_1_, intadd_39_B_0_,
intadd_39_CI, intadd_39_SUM_2_, intadd_39_SUM_1_, intadd_39_SUM_0_,
intadd_39_n3, intadd_39_n2, intadd_39_n1, intadd_40_B_2_,
intadd_40_B_1_, intadd_40_B_0_, intadd_40_CI, intadd_40_SUM_2_,
intadd_40_SUM_1_, intadd_40_SUM_0_, intadd_40_n3, intadd_40_n2,
intadd_40_n1, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:1] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1631), .QN(
n933) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n1632), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n1634), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1633),
.Q(ready) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n1635),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n1638),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n1635),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n1634),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n809), .CK(clk), .RN(n943), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n808), .CK(clk), .RN(n1645), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n807), .CK(clk), .RN(n1658), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n806), .CK(clk), .RN(n1645), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n805), .CK(clk), .RN(n1658), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n804), .CK(clk), .RN(n1645), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n803), .CK(clk), .RN(n1658), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n802), .CK(clk), .RN(n1645), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n1639), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n800), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n799), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n798), .CK(clk), .RN(n1638), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n797), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n796), .CK(clk), .RN(n1639), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n795), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n794), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n793), .CK(clk), .RN(n1643), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n792), .CK(clk), .RN(n1634), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n791), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n790), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n789), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n788), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n787), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1634), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n785), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n784), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n783), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n782), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n781), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n780), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n774), .CK(clk), .RN(n1641), .QN(n934)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n773), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n772), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n771), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n770), .CK(clk), .RN(n1641), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n1641), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n768), .CK(clk), .RN(n1642), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n763), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n761), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n760), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n759), .CK(clk), .RN(n1642), .Q(
DMP_SFG[2]), .QN(n1608) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n758), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n757), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n756), .CK(clk), .RN(n1646), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n755), .CK(clk), .RN(n1657), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n754), .CK(clk), .RN(n1658), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n752), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n751), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n749), .CK(clk), .RN(n1648), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n748), .CK(clk), .RN(n1648), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1659), .QN(n927)
);
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1654), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n745), .CK(clk), .RN(n1643), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n743), .CK(clk), .RN(n1643), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n742), .CK(clk), .RN(n943), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n740), .CK(clk), .RN(n1646), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n739), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n737), .CK(clk), .RN(n1645), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n736), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n735), .CK(clk), .RN(n1654), .Q(
DMP_SFG[10]), .QN(n1557) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n734), .CK(clk), .RN(n1643), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n733), .CK(clk), .RN(n943), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n732), .CK(clk), .RN(n1644), .Q(
DMP_SFG[11]), .QN(n1567) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n731), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n730), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n729), .CK(clk), .RN(n1644), .Q(
DMP_SFG[12]), .QN(n1566) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n728), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n727), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n726), .CK(clk), .RN(n1644), .Q(
DMP_SFG[13]), .QN(n1573) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n725), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n724), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n723), .CK(clk), .RN(n1644), .Q(
DMP_SFG[14]), .QN(n1572) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n722), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n721), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n720), .CK(clk), .RN(n1658), .Q(
DMP_SFG[15]), .QN(n1580) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n719), .CK(clk), .RN(n1645), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n718), .CK(clk), .RN(n1658), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n717), .CK(clk), .RN(n1645), .Q(
DMP_SFG[16]), .QN(n1603) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n716), .CK(clk), .RN(n1658), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n715), .CK(clk), .RN(n1645), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n714), .CK(clk), .RN(n1658), .Q(
DMP_SFG[17]), .QN(n1602) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n713), .CK(clk), .RN(n1645), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n712), .CK(clk), .RN(n1658), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n711), .CK(clk), .RN(n1645), .Q(
DMP_SFG[18]), .QN(n1611) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n710), .CK(clk), .RN(n1658), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n709), .CK(clk), .RN(n1645), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n708), .CK(clk), .RN(n1659), .Q(
DMP_SFG[19]), .QN(n1610) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n707), .CK(clk), .RN(n1646), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n706), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n705), .CK(clk), .RN(n1646), .Q(
DMP_SFG[20]), .QN(n1624) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n704), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n703), .CK(clk), .RN(n1654), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n702), .CK(clk), .RN(n1643), .Q(
DMP_SFG[21]), .QN(n1623) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n701), .CK(clk), .RN(n943), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n700), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n699), .CK(clk), .RN(n1646), .Q(
DMP_SFG[22]), .QN(n1627) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n698), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n697), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n696), .CK(clk), .RN(n1654), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n1643), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n693), .CK(clk), .RN(n943), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n692), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n691), .CK(clk), .RN(n1646), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n690), .CK(clk), .RN(n1659), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n688), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n687), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n686), .CK(clk), .RN(n1659), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n1641), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n683), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n682), .CK(clk), .RN(n1654), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n681), .CK(clk), .RN(n1657), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n680), .CK(clk), .RN(n1653), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n678), .CK(clk), .RN(n1647), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n677), .CK(clk), .RN(n1651), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n676), .CK(clk), .RN(n1652), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n675), .CK(clk), .RN(n1632), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n673), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n672), .CK(clk), .RN(n1640), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n671), .CK(clk), .RN(n1647), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n670), .CK(clk), .RN(n1651), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n668), .CK(clk), .RN(n1652), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n667), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n666), .CK(clk), .RN(n1648), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n665), .CK(clk), .RN(n1648), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n663), .CK(clk), .RN(n1648), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n662), .CK(clk), .RN(n1648), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n661), .CK(clk), .RN(n1648), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n660), .CK(clk), .RN(n1648), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n658), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n657), .CK(clk), .RN(n1648), .QN(
n936) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n656), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n654), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n652), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n650), .CK(clk), .RN(n979), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n649), .CK(clk), .RN(n1655), .QN(
n941) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n648), .CK(clk), .RN(n1649), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n647), .CK(clk), .RN(n1653), .QN(
n942) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n1656), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n644), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n642), .CK(clk), .RN(n1656), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n640), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n639), .CK(clk), .RN(n1656), .QN(
n937) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n638), .CK(clk), .RN(n1655), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n636), .CK(clk), .RN(n979), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n635), .CK(clk), .RN(n1653),
.QN(n935) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n634), .CK(clk), .RN(n1649), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n632), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n631), .CK(clk), .RN(n1656),
.QN(n938) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n630), .CK(clk), .RN(n1655), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n628), .CK(clk), .RN(n1652), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n627), .CK(clk), .RN(n1640),
.QN(n939) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n626), .CK(clk), .RN(n1634), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n624), .CK(clk), .RN(n1632), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n622), .CK(clk), .RN(n1647), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n620), .CK(clk), .RN(n1651), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n1652),
.QN(n940) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1634), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n616), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n614), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1652), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1645), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1642), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n1644), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n979), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1653), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n601), .CK(clk), .RN(n1649), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n600), .CK(clk), .RN(n1650), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n599), .CK(clk), .RN(n1656), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n598), .CK(clk), .RN(n1655), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n596), .CK(clk), .RN(n979), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n595), .CK(clk), .RN(n1653), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n594), .CK(clk), .RN(n1649), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n593), .CK(clk), .RN(n1650), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n592), .CK(clk), .RN(n1656), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n591), .CK(clk), .RN(n1658), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n574), .CK(clk), .RN(n1654), .Q(
LZD_output_NRM2_EW[4]), .QN(n1574) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n573), .CK(clk), .RN(n1647), .Q(
DmP_mant_SFG_SWR[1]), .QN(n966) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n571), .CK(clk), .RN(n1642), .Q(
LZD_output_NRM2_EW[2]), .QN(n1569) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n566), .CK(clk), .RN(n1646), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n564), .CK(clk), .RN(n1651), .QN(
n931) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n560), .CK(clk), .RN(n1659), .Q(
LZD_output_NRM2_EW[3]), .QN(n1575) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n559), .CK(clk), .RN(n1646), .Q(
LZD_output_NRM2_EW[1]), .QN(n1568) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n552), .CK(clk), .RN(n1652), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n551), .CK(clk), .RN(n1657), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n549), .CK(clk), .RN(n1656), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n548), .CK(clk), .RN(n1655), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n547), .CK(clk), .RN(n979), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n546), .CK(clk), .RN(n1653), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n544), .CK(clk), .RN(n1649), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n543), .CK(clk), .RN(n1650), .Q(
final_result_ieee[14]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n542), .CK(clk), .RN(n1656), .Q(
DmP_mant_SFG_SWR[5]), .QN(n971) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n541), .CK(clk), .RN(n1653), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n540), .CK(clk), .RN(n1655), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n539), .CK(clk), .RN(n979), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n538), .CK(clk), .RN(n1649), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n536), .CK(clk), .RN(n1655), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n535), .CK(clk), .RN(n979), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n533), .CK(clk), .RN(n1653), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n532), .CK(clk), .RN(n1649), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n531), .CK(clk), .RN(n1650), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n530), .CK(clk), .RN(n1656), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n529), .CK(clk), .RN(n979), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n528), .CK(clk), .RN(n1655), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n527), .CK(clk), .RN(n1653), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n526), .CK(clk), .RN(n1649), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n525), .CK(clk), .RN(n1657), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n519), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[17]), .QN(n975) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n516), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[20]), .QN(n974) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n515), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[21]), .QN(n973) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n512), .CK(clk), .RN(n1645), .Q(
DmP_mant_SFG_SWR[24]), .QN(n972) );
CMPR32X2TS intadd_38_U14 ( .A(n1557), .B(intadd_38_B_0_), .C(intadd_38_CI),
.CO(intadd_38_n13), .S(intadd_38_SUM_0_) );
CMPR32X2TS intadd_38_U13 ( .A(n1567), .B(intadd_38_B_1_), .C(intadd_38_n13),
.CO(intadd_38_n12), .S(intadd_38_SUM_1_) );
CMPR32X2TS intadd_38_U12 ( .A(n1566), .B(intadd_38_B_2_), .C(intadd_38_n12),
.CO(intadd_38_n11), .S(intadd_38_SUM_2_) );
CMPR32X2TS intadd_38_U11 ( .A(n1573), .B(intadd_38_B_3_), .C(intadd_38_n11),
.CO(intadd_38_n10), .S(intadd_38_SUM_3_) );
CMPR32X2TS intadd_38_U10 ( .A(n1572), .B(intadd_38_B_4_), .C(intadd_38_n10),
.CO(intadd_38_n9), .S(intadd_38_SUM_4_) );
CMPR32X2TS intadd_38_U9 ( .A(n1580), .B(intadd_38_B_5_), .C(intadd_38_n9),
.CO(intadd_38_n8), .S(intadd_38_SUM_5_) );
CMPR32X2TS intadd_38_U8 ( .A(n1603), .B(intadd_38_B_6_), .C(intadd_38_n8),
.CO(intadd_38_n7), .S(intadd_38_SUM_6_) );
CMPR32X2TS intadd_38_U7 ( .A(n1602), .B(intadd_38_B_7_), .C(intadd_38_n7),
.CO(intadd_38_n6), .S(intadd_38_SUM_7_) );
CMPR32X2TS intadd_38_U6 ( .A(n1611), .B(intadd_38_B_8_), .C(intadd_38_n6),
.CO(intadd_38_n5), .S(intadd_38_SUM_8_) );
CMPR32X2TS intadd_38_U5 ( .A(n1610), .B(intadd_38_B_9_), .C(intadd_38_n5),
.CO(intadd_38_n4), .S(intadd_38_SUM_9_) );
CMPR32X2TS intadd_38_U4 ( .A(n1624), .B(intadd_38_B_10_), .C(intadd_38_n4),
.CO(intadd_38_n3), .S(intadd_38_SUM_10_) );
CMPR32X2TS intadd_38_U3 ( .A(n1623), .B(intadd_38_B_11_), .C(intadd_38_n3),
.CO(intadd_38_n2), .S(intadd_38_SUM_11_) );
CMPR32X2TS intadd_38_U2 ( .A(n1627), .B(intadd_38_B_12_), .C(intadd_38_n2),
.CO(intadd_38_n1), .S(intadd_38_SUM_12_) );
CMPR32X2TS intadd_39_U4 ( .A(n1608), .B(intadd_39_B_0_), .C(intadd_39_CI),
.CO(intadd_39_n3), .S(intadd_39_SUM_0_) );
CMPR32X2TS intadd_39_U3 ( .A(intadd_39_A_1_), .B(n964), .C(intadd_39_n3),
.CO(intadd_39_n2), .S(intadd_39_SUM_1_) );
CMPR32X2TS intadd_39_U2 ( .A(n1622), .B(intadd_39_B_2_), .C(intadd_39_n2),
.CO(intadd_39_n1), .S(intadd_39_SUM_2_) );
CMPR32X2TS intadd_40_U4 ( .A(n956), .B(intadd_40_B_0_), .C(intadd_40_CI),
.CO(intadd_40_n3), .S(intadd_40_SUM_0_) );
CMPR32X2TS intadd_40_U3 ( .A(DMP_SFG[7]), .B(intadd_40_B_1_), .C(
intadd_40_n3), .CO(intadd_40_n2), .S(intadd_40_SUM_1_) );
CMPR32X2TS intadd_40_U2 ( .A(DMP_SFG[8]), .B(intadd_40_B_2_), .C(
intadd_40_n2), .CO(intadd_40_n1), .S(intadd_40_SUM_2_) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n915), .CK(clk), .RN(n1632), .QN(
n1628) );
DFFSX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n967), .CK(clk), .SN(n1631), .Q(
n1660), .QN(Shift_reg_FLAGS_7[0]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1634), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1533) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n561), .CK(clk), .RN(n1640), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1604) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n597), .CK(clk), .RN(n1650), .Q(
OP_FLAG_SFG), .QN(n1661) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n555), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1558) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n568), .CK(clk), .RN(n1652), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1561) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n588), .CK(clk), .RN(n1659), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1548) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1633), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1549) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n586), .CK(clk), .RN(n1654), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1606) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n853), .CK(clk), .RN(n1638),
.Q(intDY_EWSW[23]), .QN(n1597) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n854), .CK(clk), .RN(n1635),
.Q(intDY_EWSW[22]), .QN(n1538) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n855), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[21]), .QN(n1586) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n856), .CK(clk), .RN(n1643),
.Q(intDY_EWSW[20]), .QN(n1594) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n862), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[14]), .QN(n1592) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n863), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[13]), .QN(n1585) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1645),
.Q(intDY_EWSW[12]), .QN(n1591) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n858), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[18]), .QN(n1599) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n859), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[17]), .QN(n1583) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n868), .CK(clk), .RN(n1638), .Q(
intDY_EWSW[8]), .QN(n1588) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n873), .CK(clk), .RN(n1635), .Q(
intDY_EWSW[3]), .QN(n1582) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n875), .CK(clk), .RN(n1637), .Q(
intDY_EWSW[1]), .QN(n1587) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[28]), .QN(n1598) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[26]), .QN(n1545) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[25]), .QN(n1544) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[24]), .QN(n1618) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[16]), .QN(n1559) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n1633), .Q(
intDX_EWSW[7]), .QN(n1530) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n1631), .Q(
intDX_EWSW[6]), .QN(n1560) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n1637), .Q(
intDX_EWSW[5]), .QN(n1555) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n1640), .Q(
intDX_EWSW[4]), .QN(n1529) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n1633), .Q(
shift_value_SHT2_EWR[4]), .QN(n1531) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n844), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[25]), .QN(n1535) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n831), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[12]), .QN(n1617) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n659), .CK(clk), .RN(n979), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1609) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n664), .CK(clk), .RN(n1650), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1601) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n669), .CK(clk), .RN(n1653), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1579) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n694), .CK(clk), .RN(n1659), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1556) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n562), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1553) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n753), .CK(clk), .RN(n1646), .Q(
DMP_SFG[4]), .QN(n1622) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n741), .CK(clk), .RN(n1643), .Q(
DMP_SFG[8]), .QN(n1551) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n557), .CK(clk), .RN(n1651), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1528) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n1646), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1550) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n554), .CK(clk), .RN(n1652), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1552) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n567), .CK(clk), .RN(n1650), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1554) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n585), .CK(clk), .RN(n1650), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1570) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n918), .CK(clk), .RN(
n1633), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1578) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n775), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[26]), .QN(n1620) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n776), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[25]), .QN(n1605) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n777), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[24]), .QN(n1543) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n609), .CK(clk), .RN(n1652), .Q(
DmP_EXP_EWSW[26]), .QN(n1616) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n610), .CK(clk), .RN(n1646), .Q(
DmP_EXP_EWSW[25]), .QN(n1621) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n611), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[24]), .QN(n1542) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n846), .CK(clk), .RN(n1634),
.Q(intDY_EWSW[30]), .QN(n1532) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n581), .CK(clk), .RN(n1659), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1562) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n857), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[19]), .QN(n1540) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n849), .CK(clk), .RN(n1631),
.Q(intDY_EWSW[27]), .QN(n1595) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n852), .CK(clk), .RN(n1658),
.Q(intDY_EWSW[24]), .QN(n1526) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n860), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[16]), .QN(n1593) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n867), .CK(clk), .RN(n1643), .Q(
intDY_EWSW[9]), .QN(n1584) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n870), .CK(clk), .RN(n1636), .Q(
intDY_EWSW[6]), .QN(n1576) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n872), .CK(clk), .RN(n1639), .Q(
intDY_EWSW[4]), .QN(n1590) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n871), .CK(clk), .RN(n1645), .Q(
intDY_EWSW[5]), .QN(n1534) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n876), .CK(clk), .RN(n1632), .Q(
intDY_EWSW[0]), .QN(n1536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n874), .CK(clk), .RN(n1634), .Q(
intDY_EWSW[2]), .QN(n1589) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[30]), .QN(n1539) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n1637),
.Q(intDX_EWSW[29]), .QN(n1596) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n869), .CK(clk), .RN(n1638), .Q(
intDY_EWSW[7]), .QN(n1577) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n580), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1525) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n847), .CK(clk), .RN(n1640),
.Q(intDY_EWSW[29]), .QN(n1564) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n578), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1524) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n577), .CK(clk), .RN(n1651), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1547) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n1632), .Q(
shift_value_SHT2_EWR[3]), .QN(n1571) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n818), .CK(clk), .RN(n1633), .Q(
shift_value_SHT2_EWR[2]), .QN(n1563) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n829), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[10]), .QN(n1607) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n826), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[7]), .QN(n1615) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n839), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[20]), .QN(n1625) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n825), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[6]), .QN(n1614) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n841), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[22]), .QN(n1612) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n833), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[14]), .QN(n1541) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n840), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[21]), .QN(n1600) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[23]), .QN(n1613) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n828), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[9]), .QN(n1619) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n1632), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n843), .CK(clk), .RN(n1634), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n582), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n1634), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n1637), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n1634),
.Q(intDX_EWSW[27]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n556), .CK(clk), .RN(n1651), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n832), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n587), .CK(clk), .RN(n943), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n569), .CK(clk), .RN(n979), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n589), .CK(clk), .RN(n1654), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n583), .CK(clk), .RN(n1653), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1637), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n1634),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n572), .CK(clk), .RN(n1633), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n834), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[15]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n919), .CK(clk), .RN(
n1640), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n838), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n827), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n837), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n835), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n584), .CK(clk), .RN(n1649), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n738), .CK(clk), .RN(n979), .Q(
DMP_SFG[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n824), .CK(clk), .RN(n1658), .Q(
Data_array_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n579), .CK(clk), .RN(n943), .Q(
Raw_mant_NRM_SWR[23]), .QN(n926) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n762), .CK(clk), .RN(n1642), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n744), .CK(clk), .RN(n943), .Q(
DMP_SFG[7]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n613), .CK(clk), .RN(n1647), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n623), .CK(clk), .RN(n1634), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n625), .CK(clk), .RN(n979), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n643), .CK(clk), .RN(n1655), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n651), .CK(clk), .RN(n979), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n621), .CK(clk), .RN(n1647), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n633), .CK(clk), .RN(n979), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n637), .CK(clk), .RN(n1655), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n641), .CK(clk), .RN(n1653), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n866), .CK(clk), .RN(n1635),
.Q(intDY_EWSW[10]), .QN(n930) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n617), .CK(clk), .RN(n1651), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n629), .CK(clk), .RN(n1653), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n615), .CK(clk), .RN(n1651), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n645), .CK(clk), .RN(n1649), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n653), .CK(clk), .RN(n1648), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n655), .CK(clk), .RN(n1648), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n750), .CK(clk), .RN(n1650), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n765), .CK(clk), .RN(n1642), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n534), .CK(clk), .RN(n1649), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n537), .CK(clk), .RN(n1656), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n545), .CK(clk), .RN(n1656), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n553), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n558), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n563), .CK(clk), .RN(n1632), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n576), .CK(clk), .RN(n1652), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n513), .CK(clk), .RN(n1658), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n514), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n517), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n518), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n520), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n521), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n522), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n523), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n524), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n1641),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n861), .CK(clk), .RN(n1635),
.Q(intDY_EWSW[15]), .QN(n1537) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n850), .CK(clk), .RN(n1638),
.Q(intDY_EWSW[26]), .QN(n1581) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n851), .CK(clk), .RN(n1658),
.Q(intDY_EWSW[25]), .QN(n1630) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n674), .CK(clk), .RN(n1646), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n679), .CK(clk), .RN(n1654), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n684), .CK(clk), .RN(n1643), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n943), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n822), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[3]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n865), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[11]), .QN(n1565) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n845), .CK(clk), .RN(n1634),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n1634),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n1637),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n1632), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n1632), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n848), .CK(clk), .RN(n1637),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n830), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n570), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[8]), .QN(n968) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n565), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[0]), .QN(n969) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n612), .CK(clk), .RN(n1647), .Q(
DmP_EXP_EWSW[23]), .QN(n977) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n819), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n608), .CK(clk), .RN(n1651), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n550), .CK(clk), .RN(n1653), .Q(
DmP_mant_SFG_SWR[4]), .QN(n970) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n511), .CK(clk), .RN(n1658), .Q(
DmP_mant_SFG_SWR[25]), .QN(n976) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n916), .CK(clk), .RN(n1631), .Q(
n1527), .QN(n1626) );
ADDFX1TS DP_OP_15J35_125_2314_U8 ( .A(n1568), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J35_125_2314_n8), .CO(DP_OP_15J35_125_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J35_125_2314_U7 ( .A(n1569), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J35_125_2314_n7), .CO(DP_OP_15J35_125_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J35_125_2314_U6 ( .A(n1575), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J35_125_2314_n6), .CO(DP_OP_15J35_125_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J35_125_2314_U5 ( .A(n1574), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J35_125_2314_n5), .CO(DP_OP_15J35_125_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n1637), .Q(
Shift_reg_FLAGS_7[1]), .QN(n920) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n1640), .Q(
Shift_reg_FLAGS_7_6), .QN(n925) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n913), .CK(clk), .RN(n1632), .Q(
n1546), .QN(n1629) );
AOI222X4TS U927 ( .A0(Data_array_SWR[21]), .A1(n997), .B0(Data_array_SWR[17]), .B1(n998), .C0(Data_array_SWR[25]), .C1(n1001), .Y(n1462) );
NOR2X6TS U928 ( .A(n1082), .B(n1177), .Y(n1088) );
NOR2XLTS U929 ( .A(n1228), .B(n1345), .Y(n1213) );
AOI31XLTS U930 ( .A0(n1202), .A1(Raw_mant_NRM_SWR[8]), .A2(n1561), .B0(n1307), .Y(n1203) );
INVX3TS U931 ( .A(n1360), .Y(n923) );
CLKBUFX3TS U932 ( .A(n1324), .Y(n1325) );
CLKINVX6TS U933 ( .A(n1324), .Y(n921) );
NAND4X1TS U934 ( .A(n926), .B(n1525), .C(n1547), .D(n1524), .Y(n1301) );
CLKINVX6TS U935 ( .A(rst), .Y(n979) );
INVX3TS U936 ( .A(n1278), .Y(n1350) );
AOI222X1TS U937 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1331), .B0(n959), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1343), .C1(DmP_mant_SHT1_SW[17]), .Y(n1246) );
AOI222X1TS U938 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1343), .C1(DmP_mant_SHT1_SW[22]), .Y(n1249) );
INVX3TS U939 ( .A(n1335), .Y(n1331) );
INVX3TS U940 ( .A(n1335), .Y(n1353) );
CLKINVX6TS U941 ( .A(n1352), .Y(n1207) );
AND2X2TS U942 ( .A(n1208), .B(n1360), .Y(n1209) );
NOR2X1TS U943 ( .A(n1283), .B(n1315), .Y(n996) );
AO21X1TS U944 ( .A0(n1195), .A1(Raw_mant_NRM_SWR[18]), .B0(n1299), .Y(n1196)
);
AND2X4TS U945 ( .A(Shift_reg_FLAGS_7_6), .B(n1082), .Y(n1128) );
INVX4TS U946 ( .A(n1325), .Y(n922) );
NOR2X4TS U947 ( .A(n1456), .B(shift_value_SHT2_EWR[4]), .Y(n928) );
INVX4TS U948 ( .A(n1448), .Y(n997) );
AND2X4TS U949 ( .A(beg_OP), .B(n1322), .Y(n1324) );
BUFX6TS U950 ( .A(n1629), .Y(n1441) );
NOR2BX4TS U951 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1236) );
NAND2X4TS U952 ( .A(n946), .B(n1660), .Y(n980) );
NOR2X6TS U953 ( .A(shift_value_SHT2_EWR[4]), .B(n924), .Y(n998) );
INVX3TS U954 ( .A(n1427), .Y(n1001) );
BUFX6TS U955 ( .A(n1653), .Y(n1643) );
BUFX4TS U956 ( .A(n1661), .Y(n963) );
NAND2BXLTS U957 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1031) );
NAND2BXLTS U958 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1065) );
NAND2BXLTS U959 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1019) );
NAND2BXLTS U960 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1044) );
NAND2BXLTS U961 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1040) );
NAND2BXLTS U962 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1059) );
CLKAND2X2TS U963 ( .A(n1293), .B(n1294), .Y(n1292) );
INVX2TS U964 ( .A(n944), .Y(n1456) );
OAI211XLTS U965 ( .A0(n1022), .A1(n1077), .B0(n1021), .C0(n1020), .Y(n1027)
);
NAND3XLTS U966 ( .A(n1581), .B(n1019), .C(intDX_EWSW[26]), .Y(n1021) );
NAND3BXLTS U967 ( .AN(n1063), .B(n1061), .C(n1060), .Y(n1080) );
AO22XLTS U968 ( .A0(DMP_SFG[7]), .A1(intadd_40_B_1_), .B0(intadd_40_CI),
.B1(n956), .Y(n1285) );
AOI31XLTS U969 ( .A0(n1550), .A1(Raw_mant_NRM_SWR[11]), .A2(n1199), .B0(
n1196), .Y(n1016) );
AOI222X4TS U970 ( .A0(Data_array_SWR[21]), .A1(n945), .B0(Data_array_SWR[17]), .B1(n944), .C0(Data_array_SWR[25]), .C1(n1412), .Y(n1419) );
OAI21XLTS U971 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1008), .Y(n1009) );
NAND2BXLTS U972 ( .AN(n1205), .B(Raw_mant_NRM_SWR[5]), .Y(n1304) );
AOI222X1TS U973 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1353), .B0(n960), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1343), .C1(DmP_mant_SHT1_SW[3]), .Y(n1275)
);
AOI222X1TS U974 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1343), .C1(DmP_mant_SHT1_SW[18]), .Y(n1259) );
AOI222X1TS U975 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1331), .B0(n960), .B1(n949),
.C0(n1343), .C1(DmP_mant_SHT1_SW[16]), .Y(n1243) );
AOI222X1TS U976 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1331), .B0(n960), .B1(n950), .C0(n1343), .C1(DmP_mant_SHT1_SW[14]), .Y(n1231) );
AOI222X1TS U977 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1331), .B0(n960), .B1(n952), .C0(n1343), .C1(DmP_mant_SHT1_SW[10]), .Y(n1264) );
AOI222X1TS U978 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1331), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1343), .C0(n960), .C1(n948), .Y(n1256) );
OAI21XLTS U979 ( .A0(n1561), .A1(n1335), .B0(n1244), .Y(n1245) );
AO22XLTS U980 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1331), .B0(n962), .B1(n1333),
.Y(n1332) );
OAI21XLTS U981 ( .A0(n1604), .A1(n1335), .B0(n1334), .Y(n1336) );
OAI21XLTS U982 ( .A0(n1528), .A1(n1345), .B0(n1237), .Y(n1238) );
AOI222X1TS U983 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1343), .C1(DmP_mant_SHT1_SW[8]), .Y(n1267)
);
AOI222X1TS U984 ( .A0(n1282), .A1(DMP_SFG[1]), .B0(n1282), .B1(n1434), .C0(
DMP_SFG[1]), .C1(n1434), .Y(intadd_39_B_0_) );
OAI21XLTS U985 ( .A0(n1554), .A1(n1345), .B0(n1340), .Y(n1341) );
OAI21XLTS U986 ( .A0(n1550), .A1(n1345), .B0(n1344), .Y(n1346) );
AOI222X1TS U987 ( .A0(n1493), .A1(n1520), .B0(Data_array_SWR[8]), .B1(n1492),
.C0(n1491), .C1(n1490), .Y(n1508) );
AOI222X1TS U988 ( .A0(n1493), .A1(n1496), .B0(n1521), .B1(Data_array_SWR[8]),
.C0(n1491), .C1(n1472), .Y(n1489) );
OAI21XLTS U989 ( .A0(n1302), .A1(n1301), .B0(n1300), .Y(n1308) );
NAND2BXLTS U990 ( .AN(n1311), .B(n986), .Y(n989) );
AOI2BB2XLTS U991 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1350), .A0N(n1260), .A1N(
n1207), .Y(n1261) );
OAI211XLTS U992 ( .A0(n1243), .A1(n958), .B0(n1242), .C0(n1241), .Y(n836) );
AOI2BB2XLTS U993 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1350), .A0N(n1259), .A1N(
n1207), .Y(n1241) );
AO22XLTS U994 ( .A0(n1323), .A1(Data_X[19]), .B0(n922), .B1(intDX_EWSW[19]),
.Y(n891) );
AO22XLTS U995 ( .A0(n1324), .A1(Data_Y[28]), .B0(n1328), .B1(intDY_EWSW[28]),
.Y(n848) );
AO22XLTS U996 ( .A0(n1327), .A1(Data_X[10]), .B0(n922), .B1(intDX_EWSW[10]),
.Y(n900) );
AO22XLTS U997 ( .A0(n1329), .A1(Data_Y[31]), .B0(n922), .B1(intDY_EWSW[31]),
.Y(n845) );
AO22XLTS U998 ( .A0(n961), .A1(n1403), .B0(n1507), .B1(DmP_mant_SFG_SWR[11]),
.Y(n576) );
AO22XLTS U999 ( .A0(n961), .A1(n1488), .B0(n1430), .B1(DmP_mant_SFG_SWR[2]),
.Y(n563) );
AO22XLTS U1000 ( .A0(n961), .A1(DMP_SHT2_EWSW[0]), .B0(n1430), .B1(
DMP_SFG[0]), .Y(n765) );
AO22XLTS U1001 ( .A0(n961), .A1(DMP_SHT2_EWSW[5]), .B0(n1517), .B1(
DMP_SFG[5]), .Y(n750) );
AO22XLTS U1002 ( .A0(n1527), .A1(DmP_EXP_EWSW[1]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[1]), .Y(n655) );
AO22XLTS U1003 ( .A0(n1527), .A1(DmP_EXP_EWSW[2]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[2]), .Y(n653) );
AO22XLTS U1004 ( .A0(n1527), .A1(DmP_EXP_EWSW[6]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[6]), .Y(n645) );
AO22XLTS U1005 ( .A0(n1396), .A1(DmP_EXP_EWSW[14]), .B0(n1386), .B1(
DmP_mant_SHT1_SW[14]), .Y(n629) );
AO22XLTS U1006 ( .A0(n1396), .A1(DmP_EXP_EWSW[20]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[20]), .Y(n617) );
AO22XLTS U1007 ( .A0(n1527), .A1(DmP_EXP_EWSW[8]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[8]), .Y(n641) );
AO22XLTS U1008 ( .A0(n1396), .A1(DmP_EXP_EWSW[10]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[10]), .Y(n637) );
AO22XLTS U1009 ( .A0(n1396), .A1(DmP_EXP_EWSW[12]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[12]), .Y(n633) );
AO22XLTS U1010 ( .A0(n1396), .A1(DmP_EXP_EWSW[18]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[18]), .Y(n621) );
AO22XLTS U1011 ( .A0(n1527), .A1(DmP_EXP_EWSW[3]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[3]), .Y(n651) );
AO22XLTS U1012 ( .A0(n1527), .A1(DmP_EXP_EWSW[7]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[7]), .Y(n643) );
AO22XLTS U1013 ( .A0(n1396), .A1(DmP_EXP_EWSW[22]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[22]), .Y(n613) );
AO22XLTS U1014 ( .A0(n1323), .A1(Data_X[31]), .B0(n1326), .B1(intDX_EWSW[31]), .Y(n879) );
AO22XLTS U1015 ( .A0(n961), .A1(DMP_SHT2_EWSW[7]), .B0(n1517), .B1(
DMP_SFG[7]), .Y(n744) );
AO22XLTS U1016 ( .A0(n1516), .A1(DMP_SHT2_EWSW[1]), .B0(n1430), .B1(
DMP_SFG[1]), .Y(n762) );
OAI211XLTS U1017 ( .A0(n1271), .A1(n958), .B0(n1270), .C0(n1269), .Y(n824)
);
OAI211XLTS U1018 ( .A0(n1275), .A1(n958), .B0(n1274), .C0(n1273), .Y(n823)
);
AO22XLTS U1019 ( .A0(n1523), .A1(DMP_SHT2_EWSW[9]), .B0(n1517), .B1(
DMP_SFG[9]), .Y(n738) );
OAI21XLTS U1020 ( .A0(n1342), .A1(n958), .B0(n1248), .Y(n835) );
OAI21XLTS U1021 ( .A0(n1338), .A1(n1207), .B0(n1240), .Y(n837) );
OAI21XLTS U1022 ( .A0(n1348), .A1(n1207), .B0(n1281), .Y(n827) );
OAI211XLTS U1023 ( .A0(n1259), .A1(n958), .B0(n1258), .C0(n1257), .Y(n838)
);
AOI2BB2XLTS U1024 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1350), .A0N(n1256), .A1N(
n1207), .Y(n1257) );
OAI211XLTS U1025 ( .A0(n1231), .A1(n958), .B0(n1230), .C0(n1229), .Y(n834)
);
AOI2BB2XLTS U1026 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1350), .A0N(n1243), .A1N(
n1207), .Y(n1229) );
AO22XLTS U1027 ( .A0(n1325), .A1(Data_X[18]), .B0(n1328), .B1(intDX_EWSW[18]), .Y(n892) );
AO22XLTS U1028 ( .A0(n1329), .A1(Data_X[0]), .B0(n1328), .B1(intDX_EWSW[0]),
.Y(n910) );
AO22XLTS U1029 ( .A0(n1546), .A1(intadd_40_SUM_0_), .B0(n1629), .B1(
Raw_mant_NRM_SWR[8]), .Y(n569) );
AOI2BB2XLTS U1030 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1350), .A0N(n1231),
.A1N(n1207), .Y(n1232) );
OAI211XLTS U1031 ( .A0(n1267), .A1(n958), .B0(n1266), .C0(n1265), .Y(n828)
);
AOI2BB2XLTS U1032 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1350), .A0N(n1264),
.A1N(n1207), .Y(n1265) );
OAI21XLTS U1033 ( .A0(n1330), .A1(n1207), .B0(n1251), .Y(n842) );
OAI211XLTS U1034 ( .A0(n1256), .A1(n958), .B0(n1235), .C0(n1234), .Y(n840)
);
AOI2BB2XLTS U1035 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1350), .A0N(n1249), .A1N(
n1207), .Y(n1234) );
OAI211XLTS U1036 ( .A0(n1279), .A1(n1207), .B0(n1227), .C0(n1226), .Y(n825)
);
OAI211XLTS U1037 ( .A0(n1267), .A1(n1207), .B0(n1223), .C0(n1222), .Y(n826)
);
OAI21XLTS U1038 ( .A0(n1360), .A1(n1531), .B0(n1191), .Y(n815) );
AO22XLTS U1039 ( .A0(n1396), .A1(DmP_EXP_EWSW[15]), .B0(n1386), .B1(n949),
.Y(n627) );
AO22XLTS U1040 ( .A0(n1396), .A1(DmP_EXP_EWSW[13]), .B0(n1388), .B1(n950),
.Y(n631) );
AO22XLTS U1041 ( .A0(n1396), .A1(DmP_EXP_EWSW[11]), .B0(n1388), .B1(n951),
.Y(n635) );
AO22XLTS U1042 ( .A0(n1396), .A1(DmP_EXP_EWSW[9]), .B0(n1388), .B1(n952),
.Y(n639) );
AO22XLTS U1043 ( .A0(n1527), .A1(DmP_EXP_EWSW[5]), .B0(n1388), .B1(n953),
.Y(n647) );
AO22XLTS U1044 ( .A0(n1527), .A1(DmP_EXP_EWSW[4]), .B0(n1388), .B1(n947),
.Y(n649) );
AO22XLTS U1045 ( .A0(n1527), .A1(DmP_EXP_EWSW[0]), .B0(n1397), .B1(n954),
.Y(n657) );
AO22XLTS U1046 ( .A0(n961), .A1(DMP_SHT2_EWSW[6]), .B0(n1517), .B1(n956),
.Y(n747) );
AO22XLTS U1047 ( .A0(n1320), .A1(n1546), .B0(n1321), .B1(n946), .Y(n913) );
AO22XLTS U1048 ( .A0(n1321), .A1(busy), .B0(n1320), .B1(n946), .Y(n914) );
OR2X1TS U1049 ( .A(shift_value_SHT2_EWR[3]), .B(n1563), .Y(n924) );
OR2X1TS U1050 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n929) );
BUFX3TS U1051 ( .A(n923), .Y(n1358) );
OR2X1TS U1052 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n932) );
AOI211XLTS U1053 ( .A0(intDY_EWSW[16]), .A1(n1559), .B0(n1068), .C0(n1098),
.Y(n1060) );
OAI211XLTS U1054 ( .A0(n1255), .A1(n958), .B0(n1254), .C0(n1253), .Y(n820)
);
AOI31XLTS U1055 ( .A0(n1195), .A1(Raw_mant_NRM_SWR[16]), .A2(n1570), .B0(
n1194), .Y(n1204) );
NOR2BX2TS U1056 ( .AN(n1302), .B(n1301), .Y(n1195) );
BUFX4TS U1057 ( .A(n979), .Y(n1650) );
BUFX4TS U1058 ( .A(n979), .Y(n1653) );
BUFX4TS U1059 ( .A(n1651), .Y(n1644) );
BUFX4TS U1060 ( .A(n1645), .Y(n1648) );
BUFX4TS U1061 ( .A(n1652), .Y(n1642) );
BUFX4TS U1062 ( .A(n1631), .Y(n1641) );
BUFX4TS U1063 ( .A(n1631), .Y(n1658) );
BUFX4TS U1064 ( .A(n1637), .Y(n1645) );
BUFX3TS U1065 ( .A(n1626), .Y(n1387) );
BUFX4TS U1066 ( .A(n1647), .Y(n1657) );
BUFX4TS U1067 ( .A(n1638), .Y(n1640) );
BUFX3TS U1068 ( .A(n1653), .Y(n943) );
BUFX4TS U1069 ( .A(n1655), .Y(n1646) );
BUFX4TS U1070 ( .A(n1650), .Y(n1659) );
BUFX4TS U1071 ( .A(n1635), .Y(n1633) );
BUFX4TS U1072 ( .A(n1639), .Y(n1634) );
BUFX4TS U1073 ( .A(n1633), .Y(n1632) );
BUFX4TS U1074 ( .A(n1636), .Y(n1631) );
XNOR2X2TS U1075 ( .A(DMP_exp_NRM2_EW[7]), .B(n992), .Y(n1313) );
XNOR2X2TS U1076 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J35_125_2314_n4), .Y(
n1310) );
INVX2TS U1077 ( .A(n929), .Y(n944) );
INVX2TS U1078 ( .A(n924), .Y(n945) );
BUFX4TS U1079 ( .A(n1083), .Y(n1381) );
AOI222X1TS U1080 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1331), .B0(n960), .B1(
n951), .C0(n1343), .C1(DmP_mant_SHT1_SW[12]), .Y(n1260) );
INVX2TS U1081 ( .A(n933), .Y(n946) );
INVX2TS U1082 ( .A(n941), .Y(n947) );
INVX2TS U1083 ( .A(n940), .Y(n948) );
INVX2TS U1084 ( .A(n939), .Y(n949) );
INVX2TS U1085 ( .A(n938), .Y(n950) );
INVX2TS U1086 ( .A(n935), .Y(n951) );
INVX2TS U1087 ( .A(n937), .Y(n952) );
INVX2TS U1088 ( .A(n942), .Y(n953) );
INVX2TS U1089 ( .A(n936), .Y(n954) );
INVX2TS U1090 ( .A(n934), .Y(n955) );
INVX2TS U1091 ( .A(n927), .Y(n956) );
CLKINVX3TS U1092 ( .A(n1495), .Y(n1521) );
CLKINVX3TS U1093 ( .A(n1467), .Y(n1492) );
CLKINVX6TS U1094 ( .A(n1520), .Y(n1496) );
BUFX6TS U1095 ( .A(left_right_SHT2), .Y(n1520) );
BUFX4TS U1096 ( .A(n996), .Y(n1498) );
BUFX4TS U1097 ( .A(n1177), .Y(n1319) );
INVX2TS U1098 ( .A(n1209), .Y(n957) );
INVX4TS U1099 ( .A(n1209), .Y(n958) );
INVX2TS U1100 ( .A(n932), .Y(n959) );
INVX4TS U1101 ( .A(n932), .Y(n960) );
INVX4TS U1102 ( .A(n1517), .Y(n961) );
INVX2TS U1103 ( .A(n931), .Y(n962) );
OAI211XLTS U1104 ( .A0(n1264), .A1(n957), .B0(n1262), .C0(n1261), .Y(n830)
);
AOI32X1TS U1105 ( .A0(n1599), .A1(n1065), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1540), .Y(n1066) );
AOI221X1TS U1106 ( .A0(n1599), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1540), .C0(n1098), .Y(n1103) );
AOI221X1TS U1107 ( .A0(n1595), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1598), .C0(n1091), .Y(n1095) );
AOI221X1TS U1108 ( .A0(n930), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1179), .C0(n1106), .Y(n1111) );
AOI221X1TS U1109 ( .A0(n1589), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1582), .C0(n1114), .Y(n1119) );
AOI221X1TS U1110 ( .A0(n1587), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1583), .C0(n1097), .Y(n1104) );
AOI221X1TS U1111 ( .A0(n1538), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1597), .C0(n1100), .Y(n1101) );
AOI221X1TS U1112 ( .A0(n1592), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1184), .C0(n1108), .Y(n1109) );
OAI211X2TS U1113 ( .A0(intDX_EWSW[20]), .A1(n1594), .B0(n1073), .C0(n1059),
.Y(n1068) );
AOI221X1TS U1114 ( .A0(n1594), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1586), .C0(n1099), .Y(n1102) );
OAI211X2TS U1115 ( .A0(intDX_EWSW[12]), .A1(n1591), .B0(n1054), .C0(n1040),
.Y(n1056) );
AOI221X1TS U1116 ( .A0(n1591), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1585), .C0(n1107), .Y(n1110) );
INVX1TS U1117 ( .A(DMP_SFG[3]), .Y(intadd_39_A_1_) );
OAI211XLTS U1118 ( .A0(n1271), .A1(n1207), .B0(n1215), .C0(n1214), .Y(n822)
);
OAI211XLTS U1119 ( .A0(n1275), .A1(n1207), .B0(n1219), .C0(n1218), .Y(n821)
);
OAI31XLTS U1120 ( .A0(n1383), .A1(n1127), .A2(n1392), .B0(n1126), .Y(n768)
);
NOR2X2TS U1121 ( .A(n977), .B(DMP_EXP_EWSW[23]), .Y(n1367) );
NOR2X2TS U1122 ( .A(shift_value_SHT2_EWR[2]), .B(n1571), .Y(n1412) );
BUFX4TS U1123 ( .A(n1643), .Y(n1636) );
XNOR2X2TS U1124 ( .A(DMP_exp_NRM2_EW[6]), .B(n987), .Y(n1311) );
XNOR2X2TS U1125 ( .A(DMP_exp_NRM2_EW[0]), .B(n1289), .Y(n1309) );
OAI22X2TS U1126 ( .A0(n1600), .A1(n1456), .B0(n1535), .B1(n924), .Y(n1468)
);
AO22XLTS U1127 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n963), .B0(n1425), .B1(n971),
.Y(intadd_39_B_1_) );
INVX2TS U1128 ( .A(intadd_39_B_1_), .Y(n964) );
AOI222X4TS U1129 ( .A0(intadd_39_A_1_), .A1(n964), .B0(intadd_39_A_1_), .B1(
n1404), .C0(n964), .C1(n1404), .Y(n1405) );
AOI2BB2X2TS U1130 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1425), .A0N(n1425),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1409) );
AOI2BB2X2TS U1131 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1425), .A0N(n1425), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1434) );
AOI2BB2X2TS U1132 ( .B0(DmP_mant_SFG_SWR[9]), .B1(n1425), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[9]), .Y(intadd_40_B_1_) );
AOI222X1TS U1133 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1353), .B0(n960), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1343), .C1(DmP_mant_SHT1_SW[7]), .Y(n1279)
);
NOR4BBX2TS U1134 ( .AN(n1193), .BN(n1016), .C(n1188), .D(n1015), .Y(n1228)
);
AOI31XLTS U1135 ( .A0(n1399), .A1(Shift_amount_SHT1_EWR[4]), .A2(n920), .B0(
n1291), .Y(n1191) );
CLKINVX6TS U1136 ( .A(n1385), .Y(n1399) );
INVX4TS U1137 ( .A(n1324), .Y(n1326) );
CLKINVX6TS U1138 ( .A(n1128), .Y(n1389) );
NAND2X4TS U1139 ( .A(n920), .B(n1385), .Y(n1360) );
BUFX4TS U1140 ( .A(n1628), .Y(n1385) );
AOI222X1TS U1141 ( .A0(n1475), .A1(n1496), .B0(n1521), .B1(Data_array_SWR[5]), .C0(n1474), .C1(n1472), .Y(n1473) );
AOI222X1TS U1142 ( .A0(n1475), .A1(n1520), .B0(Data_array_SWR[5]), .B1(n1492), .C0(n1474), .C1(n1490), .Y(n1512) );
AOI222X1TS U1143 ( .A0(n1458), .A1(n1496), .B0(n1521), .B1(Data_array_SWR[4]), .C0(n1468), .C1(n1472), .Y(n1457) );
AOI222X1TS U1144 ( .A0(n1458), .A1(n1520), .B0(Data_array_SWR[4]), .B1(n1492), .C0(n1468), .C1(n1490), .Y(n1513) );
INVX3TS U1145 ( .A(n1441), .Y(n1446) );
AOI222X4TS U1146 ( .A0(n1409), .A1(DMP_SFG[9]), .B0(n1409), .B1(n1288), .C0(
DMP_SFG[9]), .C1(n1288), .Y(intadd_38_B_0_) );
AOI222X4TS U1147 ( .A0(Data_array_SWR[20]), .A1(n997), .B0(
Data_array_SWR[24]), .B1(n1001), .C0(Data_array_SWR[16]), .C1(n998),
.Y(n1461) );
AOI222X4TS U1148 ( .A0(Data_array_SWR[20]), .A1(n945), .B0(
Data_array_SWR[24]), .B1(n1412), .C0(Data_array_SWR[16]), .C1(n944),
.Y(n1465) );
AOI22X2TS U1149 ( .A0(Data_array_SWR[22]), .A1(n945), .B0(Data_array_SWR[18]), .B1(n944), .Y(n1483) );
AOI222X4TS U1150 ( .A0(Data_array_SWR[22]), .A1(n1001), .B0(
Data_array_SWR[14]), .B1(n998), .C0(Data_array_SWR[18]), .C1(n997),
.Y(n1481) );
AOI222X4TS U1151 ( .A0(Data_array_SWR[23]), .A1(n1001), .B0(
Data_array_SWR[19]), .B1(n997), .C0(Data_array_SWR[15]), .C1(n998),
.Y(n1477) );
AOI22X2TS U1152 ( .A0(Data_array_SWR[23]), .A1(n945), .B0(Data_array_SWR[19]), .B1(n944), .Y(n1453) );
NOR2X2TS U1153 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1578), .Y(n1318) );
OAI21X2TS U1154 ( .A0(intDX_EWSW[18]), .A1(n1599), .B0(n1065), .Y(n1098) );
AOI32X1TS U1155 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1012), .A2(n1011), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1012), .Y(n1013) );
NOR3X1TS U1156 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1302) );
NOR2X2TS U1157 ( .A(Raw_mant_NRM_SWR[13]), .B(n1006), .Y(n1199) );
CLKINVX3TS U1158 ( .A(Shift_reg_FLAGS_7[0]), .Y(n965) );
AOI221X1TS U1159 ( .A0(n1588), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1576), .C0(n1116), .Y(n1117) );
AOI222X1TS U1160 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1343), .C1(n947), .Y(n1271) );
AO22XLTS U1161 ( .A0(n1321), .A1(n920), .B0(n965), .B1(n1320), .Y(n967) );
NOR2XLTS U1162 ( .A(n1565), .B(intDX_EWSW[11]), .Y(n1042) );
OAI21XLTS U1163 ( .A0(intDX_EWSW[15]), .A1(n1537), .B0(intDX_EWSW[14]), .Y(
n1050) );
NOR2XLTS U1164 ( .A(n1063), .B(intDY_EWSW[16]), .Y(n1064) );
OAI21XLTS U1165 ( .A0(intDX_EWSW[21]), .A1(n1586), .B0(intDX_EWSW[20]), .Y(
n1062) );
OAI21XLTS U1166 ( .A0(DmP_EXP_EWSW[25]), .A1(n1605), .B0(n1371), .Y(n1368)
);
OAI21XLTS U1167 ( .A0(n1548), .A1(n1345), .B0(n1276), .Y(n1277) );
OAI21XLTS U1168 ( .A0(n1584), .A1(n1163), .B0(n1155), .Y(n640) );
OAI21XLTS U1169 ( .A0(n1589), .A1(n1389), .B0(n1156), .Y(n654) );
OAI21XLTS U1170 ( .A0(n1539), .A1(n1389), .B0(n1145), .Y(n771) );
OAI21XLTS U1171 ( .A0(n1585), .A1(n1183), .B0(n1180), .Y(n788) );
OAI211XLTS U1172 ( .A0(n1260), .A1(n957), .B0(n1233), .C0(n1232), .Y(n832)
);
NOR2XLTS U1173 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n978) );
AOI32X4TS U1174 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n978), .B1(n1578), .Y(n1321)
);
INVX2TS U1175 ( .A(n1321), .Y(n1320) );
INVX4TS U1176 ( .A(n1385), .Y(busy) );
BUFX3TS U1177 ( .A(n1643), .Y(n1651) );
BUFX3TS U1178 ( .A(n979), .Y(n1655) );
BUFX3TS U1179 ( .A(n943), .Y(n1647) );
BUFX3TS U1180 ( .A(n979), .Y(n1649) );
BUFX3TS U1181 ( .A(n943), .Y(n1635) );
BUFX3TS U1182 ( .A(n1654), .Y(n1652) );
BUFX3TS U1183 ( .A(n1654), .Y(n1639) );
BUFX3TS U1184 ( .A(n979), .Y(n1656) );
BUFX3TS U1185 ( .A(n943), .Y(n1638) );
BUFX3TS U1186 ( .A(n1650), .Y(n1654) );
BUFX3TS U1187 ( .A(n1636), .Y(n1637) );
AO22XLTS U1188 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n920),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n601) );
AO22XLTS U1189 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n920),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n592) );
BUFX3TS U1190 ( .A(n980), .Y(n1517) );
BUFX3TS U1191 ( .A(n1517), .Y(n1430) );
INVX4TS U1192 ( .A(n980), .Y(n1510) );
AO22XLTS U1193 ( .A0(n1430), .A1(DMP_SFG[20]), .B0(n1510), .B1(
DMP_SHT2_EWSW[20]), .Y(n705) );
AO22XLTS U1194 ( .A0(n1430), .A1(DMP_SFG[21]), .B0(n1510), .B1(
DMP_SHT2_EWSW[21]), .Y(n702) );
AO22XLTS U1195 ( .A0(n1430), .A1(DMP_SFG[18]), .B0(n1510), .B1(
DMP_SHT2_EWSW[18]), .Y(n711) );
AO22XLTS U1196 ( .A0(n1430), .A1(DMP_SFG[17]), .B0(n1510), .B1(
DMP_SHT2_EWSW[17]), .Y(n714) );
AO22XLTS U1197 ( .A0(n1430), .A1(DMP_SFG[16]), .B0(n1510), .B1(
DMP_SHT2_EWSW[16]), .Y(n717) );
AO22XLTS U1198 ( .A0(n1430), .A1(DMP_SFG[8]), .B0(n1510), .B1(
DMP_SHT2_EWSW[8]), .Y(n741) );
AO22XLTS U1199 ( .A0(n1441), .A1(Raw_mant_NRM_SWR[9]), .B0(n1546), .B1(
intadd_40_SUM_1_), .Y(n568) );
AO22XLTS U1200 ( .A0(n1441), .A1(Raw_mant_NRM_SWR[10]), .B0(n1546), .B1(
intadd_40_SUM_2_), .Y(n567) );
INVX2TS U1201 ( .A(DP_OP_15J35_125_2314_n4), .Y(n981) );
NAND2X1TS U1202 ( .A(n1579), .B(n981), .Y(n987) );
INVX1TS U1203 ( .A(LZD_output_NRM2_EW[0]), .Y(n1289) );
NOR2XLTS U1204 ( .A(n1309), .B(exp_rslt_NRM2_EW1[1]), .Y(n984) );
INVX2TS U1205 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n983) );
INVX2TS U1206 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n982) );
NAND4BXLTS U1207 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n984), .C(n983), .D(n982),
.Y(n985) );
NOR2XLTS U1208 ( .A(n985), .B(n1310), .Y(n986) );
INVX2TS U1209 ( .A(n987), .Y(n988) );
NAND2X1TS U1210 ( .A(n1601), .B(n988), .Y(n992) );
OR2X1TS U1211 ( .A(n989), .B(n1313), .Y(n1393) );
INVX2TS U1212 ( .A(n1393), .Y(n1283) );
AND4X1TS U1213 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1309), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n990) );
AND4X1TS U1214 ( .A(n1311), .B(n1310), .C(exp_rslt_NRM2_EW1[4]), .D(n990),
.Y(n991) );
CLKAND2X2TS U1215 ( .A(n1313), .B(n991), .Y(n995) );
INVX2TS U1216 ( .A(n992), .Y(n993) );
CLKAND2X2TS U1217 ( .A(n1609), .B(n993), .Y(n994) );
OAI2BB1X1TS U1218 ( .A0N(n995), .A1N(n994), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1315) );
NAND2X2TS U1219 ( .A(n1496), .B(n928), .Y(n1495) );
NOR2X2TS U1220 ( .A(n1531), .B(n1456), .Y(n1450) );
NAND3X1TS U1221 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1531), .Y(n1427) );
NAND2X1TS U1222 ( .A(n1531), .B(n1412), .Y(n1448) );
AOI22X1TS U1223 ( .A0(Data_array_SWR[17]), .A1(n997), .B0(Data_array_SWR[13]), .B1(n998), .Y(n999) );
OAI21XLTS U1224 ( .A0(n1600), .A1(n1427), .B0(n999), .Y(n1000) );
AOI21X1TS U1225 ( .A0(Data_array_SWR[25]), .A1(n1450), .B0(n1000), .Y(n1464)
);
NOR2X2TS U1226 ( .A(shift_value_SHT2_EWR[4]), .B(n1496), .Y(n1472) );
INVX2TS U1227 ( .A(n1472), .Y(n1484) );
OAI222X1TS U1228 ( .A0(n1495), .A1(n1619), .B0(n1520), .B1(n1464), .C0(n1484), .C1(n1465), .Y(n1463) );
AO22XLTS U1229 ( .A0(n1498), .A1(n1463), .B0(final_result_ieee[7]), .B1(
n1660), .Y(n544) );
NAND2X2TS U1230 ( .A(n1520), .B(n928), .Y(n1467) );
NOR2X2TS U1231 ( .A(shift_value_SHT2_EWR[4]), .B(n1520), .Y(n1490) );
INVX2TS U1232 ( .A(n1490), .Y(n1466) );
AOI22X1TS U1233 ( .A0(Data_array_SWR[19]), .A1(n1001), .B0(
Data_array_SWR[11]), .B1(n998), .Y(n1002) );
OAI2BB1X1TS U1234 ( .A0N(Data_array_SWR[15]), .A1N(n997), .B0(n1002), .Y(
n1003) );
AOI21X1TS U1235 ( .A0(Data_array_SWR[23]), .A1(n1450), .B0(n1003), .Y(n1485)
);
OAI222X1TS U1236 ( .A0(n1467), .A1(n1615), .B0(n1466), .B1(n1483), .C0(n1496), .C1(n1485), .Y(n1509) );
AO22XLTS U1237 ( .A0(n1498), .A1(n1509), .B0(final_result_ieee[16]), .B1(
n1660), .Y(n532) );
AOI22X1TS U1238 ( .A0(Data_array_SWR[22]), .A1(n997), .B0(Data_array_SWR[18]), .B1(n998), .Y(n1478) );
AOI22X1TS U1239 ( .A0(Data_array_SWR[14]), .A1(n1492), .B0(
Data_array_SWR[11]), .B1(n1521), .Y(n1004) );
OAI221X1TS U1240 ( .A0(n1520), .A1(n1477), .B0(n1496), .B1(n1478), .C0(n1004), .Y(n1403) );
AO22XLTS U1241 ( .A0(n1498), .A1(n1403), .B0(final_result_ieee[9]), .B1(
n1660), .Y(n539) );
AOI22X1TS U1242 ( .A0(Data_array_SWR[23]), .A1(n997), .B0(Data_array_SWR[19]), .B1(n998), .Y(n1480) );
AOI22X1TS U1243 ( .A0(Data_array_SWR[10]), .A1(n1492), .B0(
Data_array_SWR[15]), .B1(n1521), .Y(n1005) );
OAI221X1TS U1244 ( .A0(n1520), .A1(n1480), .B0(n1496), .B1(n1481), .C0(n1005), .Y(n1504) );
AO22XLTS U1245 ( .A0(n1498), .A1(n1504), .B0(final_result_ieee[13]), .B1(
n1660), .Y(n535) );
NOR2BX1TS U1246 ( .AN(n1195), .B(Raw_mant_NRM_SWR[18]), .Y(n1293) );
NOR3X1TS U1247 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1294) );
NAND2X1TS U1248 ( .A(Raw_mant_NRM_SWR[14]), .B(n1292), .Y(n1193) );
NAND2X1TS U1249 ( .A(n1292), .B(n1548), .Y(n1006) );
NAND2X1TS U1250 ( .A(n1199), .B(n1549), .Y(n1007) );
NOR3X1TS U1251 ( .A(Raw_mant_NRM_SWR[12]), .B(n1554), .C(n1007), .Y(n1299)
);
NOR2XLTS U1252 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1010)
);
NOR2X1TS U1253 ( .A(Raw_mant_NRM_SWR[10]), .B(n1007), .Y(n1202) );
NAND2X1TS U1254 ( .A(n1202), .B(n1550), .Y(n1185) );
NOR3X1TS U1255 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1185),
.Y(n1008) );
NAND2X1TS U1256 ( .A(n1008), .B(n1552), .Y(n1205) );
NOR3X2TS U1257 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1205),
.Y(n1198) );
NAND2X1TS U1258 ( .A(n1198), .B(n1528), .Y(n1303) );
OAI21X1TS U1259 ( .A0(n1010), .A1(n1303), .B0(n1009), .Y(n1188) );
NOR2XLTS U1260 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1014) );
NOR2X1TS U1261 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1012) );
NOR2XLTS U1262 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1011) );
AOI211X1TS U1263 ( .A0(n1014), .A1(n1013), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1015) );
NOR2X1TS U1264 ( .A(n1228), .B(n920), .Y(n1206) );
AO21XLTS U1265 ( .A0(LZD_output_NRM2_EW[1]), .A1(n920), .B0(n1206), .Y(n559)
);
OAI21XLTS U1266 ( .A0(n1399), .A1(n1496), .B0(n920), .Y(n877) );
AOI2BB2X1TS U1267 ( .B0(DmP_mant_SFG_SWR[6]), .B1(n1661), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[6]), .Y(intadd_39_B_2_) );
AOI2BB2XLTS U1268 ( .B0(beg_OP), .B1(n1533), .A0N(n1533), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1017) );
NAND3XLTS U1269 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1533), .C(
n1578), .Y(n1316) );
OAI21XLTS U1270 ( .A0(n1318), .A1(n1017), .B0(n1316), .Y(n918) );
NOR2X1TS U1271 ( .A(n1630), .B(intDX_EWSW[25]), .Y(n1076) );
NOR2XLTS U1272 ( .A(n1076), .B(intDY_EWSW[24]), .Y(n1018) );
AOI22X1TS U1273 ( .A0(intDX_EWSW[25]), .A1(n1630), .B0(intDX_EWSW[24]), .B1(
n1018), .Y(n1022) );
OAI21X1TS U1274 ( .A0(intDX_EWSW[26]), .A1(n1581), .B0(n1019), .Y(n1077) );
NAND2BXLTS U1275 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1020) );
NOR2X1TS U1276 ( .A(n1532), .B(intDX_EWSW[30]), .Y(n1025) );
NOR2X1TS U1277 ( .A(n1564), .B(intDX_EWSW[29]), .Y(n1023) );
AOI211X1TS U1278 ( .A0(intDY_EWSW[28]), .A1(n1598), .B0(n1025), .C0(n1023),
.Y(n1075) );
NOR3X1TS U1279 ( .A(n1598), .B(n1023), .C(intDY_EWSW[28]), .Y(n1024) );
AOI221X1TS U1280 ( .A0(intDX_EWSW[30]), .A1(n1532), .B0(intDX_EWSW[29]),
.B1(n1564), .C0(n1024), .Y(n1026) );
AOI2BB2X1TS U1281 ( .B0(n1027), .B1(n1075), .A0N(n1026), .A1N(n1025), .Y(
n1081) );
NOR2X1TS U1282 ( .A(n1583), .B(intDX_EWSW[17]), .Y(n1063) );
INVX2TS U1283 ( .A(intDY_EWSW[11]), .Y(n1179) );
OAI22X1TS U1284 ( .A0(n930), .A1(intDX_EWSW[10]), .B0(n1179), .B1(
intDX_EWSW[11]), .Y(n1106) );
INVX2TS U1285 ( .A(n1106), .Y(n1047) );
OAI211XLTS U1286 ( .A0(intDX_EWSW[8]), .A1(n1588), .B0(n1044), .C0(n1047),
.Y(n1058) );
OAI2BB1X1TS U1287 ( .A0N(n1555), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1028) );
OAI22X1TS U1288 ( .A0(intDY_EWSW[4]), .A1(n1028), .B0(n1555), .B1(
intDY_EWSW[5]), .Y(n1039) );
OAI2BB1X1TS U1289 ( .A0N(n1530), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1029) );
OAI22X1TS U1290 ( .A0(intDY_EWSW[6]), .A1(n1029), .B0(n1530), .B1(
intDY_EWSW[7]), .Y(n1038) );
OAI21XLTS U1291 ( .A0(intDX_EWSW[1]), .A1(n1587), .B0(intDX_EWSW[0]), .Y(
n1030) );
OAI2BB2XLTS U1292 ( .B0(intDY_EWSW[0]), .B1(n1030), .A0N(intDX_EWSW[1]),
.A1N(n1587), .Y(n1032) );
OAI211XLTS U1293 ( .A0(n1582), .A1(intDX_EWSW[3]), .B0(n1032), .C0(n1031),
.Y(n1035) );
OAI21XLTS U1294 ( .A0(intDX_EWSW[3]), .A1(n1582), .B0(intDX_EWSW[2]), .Y(
n1033) );
AOI2BB2XLTS U1295 ( .B0(intDX_EWSW[3]), .B1(n1582), .A0N(intDY_EWSW[2]),
.A1N(n1033), .Y(n1034) );
AOI222X1TS U1296 ( .A0(intDY_EWSW[4]), .A1(n1529), .B0(n1035), .B1(n1034),
.C0(intDY_EWSW[5]), .C1(n1555), .Y(n1037) );
AOI22X1TS U1297 ( .A0(intDY_EWSW[7]), .A1(n1530), .B0(intDY_EWSW[6]), .B1(
n1560), .Y(n1036) );
OAI32X1TS U1298 ( .A0(n1039), .A1(n1038), .A2(n1037), .B0(n1036), .B1(n1038),
.Y(n1057) );
OA22X1TS U1299 ( .A0(n1592), .A1(intDX_EWSW[14]), .B0(n1537), .B1(
intDX_EWSW[15]), .Y(n1054) );
OAI21XLTS U1300 ( .A0(intDX_EWSW[13]), .A1(n1585), .B0(intDX_EWSW[12]), .Y(
n1041) );
OAI2BB2XLTS U1301 ( .B0(intDY_EWSW[12]), .B1(n1041), .A0N(intDX_EWSW[13]),
.A1N(n1585), .Y(n1053) );
NOR2XLTS U1302 ( .A(n1042), .B(intDY_EWSW[10]), .Y(n1043) );
AOI22X1TS U1303 ( .A0(intDX_EWSW[11]), .A1(n1565), .B0(intDX_EWSW[10]), .B1(
n1043), .Y(n1049) );
NAND2BXLTS U1304 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1046) );
NAND3XLTS U1305 ( .A(n1588), .B(n1044), .C(intDX_EWSW[8]), .Y(n1045) );
AOI21X1TS U1306 ( .A0(n1046), .A1(n1045), .B0(n1056), .Y(n1048) );
OAI2BB2XLTS U1307 ( .B0(n1049), .B1(n1056), .A0N(n1048), .A1N(n1047), .Y(
n1052) );
INVX2TS U1308 ( .A(intDY_EWSW[15]), .Y(n1184) );
OAI2BB2XLTS U1309 ( .B0(intDY_EWSW[14]), .B1(n1050), .A0N(intDX_EWSW[15]),
.A1N(n1184), .Y(n1051) );
AOI211X1TS U1310 ( .A0(n1054), .A1(n1053), .B0(n1052), .C0(n1051), .Y(n1055)
);
OAI31X1TS U1311 ( .A0(n1058), .A1(n1057), .A2(n1056), .B0(n1055), .Y(n1061)
);
OA22X1TS U1312 ( .A0(n1538), .A1(intDX_EWSW[22]), .B0(n1597), .B1(
intDX_EWSW[23]), .Y(n1073) );
OAI2BB2XLTS U1313 ( .B0(intDY_EWSW[20]), .B1(n1062), .A0N(intDX_EWSW[21]),
.A1N(n1586), .Y(n1072) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[17]), .A1(n1583), .B0(intDX_EWSW[16]), .B1(
n1064), .Y(n1067) );
OAI32X1TS U1315 ( .A0(n1098), .A1(n1068), .A2(n1067), .B0(n1066), .B1(n1068),
.Y(n1071) );
OAI21XLTS U1316 ( .A0(intDX_EWSW[23]), .A1(n1597), .B0(intDX_EWSW[22]), .Y(
n1069) );
OAI2BB2XLTS U1317 ( .B0(intDY_EWSW[22]), .B1(n1069), .A0N(intDX_EWSW[23]),
.A1N(n1597), .Y(n1070) );
AOI211X1TS U1318 ( .A0(n1073), .A1(n1072), .B0(n1071), .C0(n1070), .Y(n1079)
);
NAND2BXLTS U1319 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1074) );
NAND4BBX1TS U1320 ( .AN(n1077), .BN(n1076), .C(n1075), .D(n1074), .Y(n1078)
);
AOI32X1TS U1321 ( .A0(n1081), .A1(n1080), .A2(n1079), .B0(n1078), .B1(n1081),
.Y(n1082) );
INVX2TS U1322 ( .A(Shift_reg_FLAGS_7_6), .Y(n1083) );
INVX4TS U1323 ( .A(n1088), .Y(n1183) );
BUFX4TS U1324 ( .A(n1083), .Y(n1177) );
AOI22X1TS U1325 ( .A0(intDX_EWSW[4]), .A1(n1128), .B0(DMP_EXP_EWSW[4]), .B1(
n1177), .Y(n1084) );
OAI21XLTS U1326 ( .A0(n1590), .A1(n1183), .B0(n1084), .Y(n797) );
AOI22X1TS U1327 ( .A0(intDX_EWSW[6]), .A1(n1128), .B0(DMP_EXP_EWSW[6]), .B1(
n1177), .Y(n1085) );
OAI21XLTS U1328 ( .A0(n1576), .A1(n1183), .B0(n1085), .Y(n795) );
AOI22X1TS U1329 ( .A0(intDX_EWSW[7]), .A1(n1128), .B0(DMP_EXP_EWSW[7]), .B1(
n1381), .Y(n1086) );
OAI21XLTS U1330 ( .A0(n1577), .A1(n1183), .B0(n1086), .Y(n794) );
AOI22X1TS U1331 ( .A0(intDX_EWSW[5]), .A1(n1128), .B0(DMP_EXP_EWSW[5]), .B1(
n1177), .Y(n1087) );
OAI21XLTS U1332 ( .A0(n1534), .A1(n1183), .B0(n1087), .Y(n796) );
INVX3TS U1333 ( .A(n1128), .Y(n1163) );
AOI22X1TS U1334 ( .A0(intDX_EWSW[16]), .A1(n1088), .B0(DmP_EXP_EWSW[16]),
.B1(n1319), .Y(n1089) );
OAI21XLTS U1335 ( .A0(n1593), .A1(n1163), .B0(n1089), .Y(n626) );
INVX2TS U1336 ( .A(intDY_EWSW[26]), .Y(n1390) );
OAI22X1TS U1337 ( .A0(n1630), .A1(intDX_EWSW[25]), .B0(n1390), .B1(
intDX_EWSW[26]), .Y(n1090) );
AOI221X1TS U1338 ( .A0(n1630), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1390), .C0(n1090), .Y(n1096) );
OAI22X1TS U1339 ( .A0(n1595), .A1(intDX_EWSW[27]), .B0(n1598), .B1(
intDY_EWSW[28]), .Y(n1091) );
OAI22X1TS U1340 ( .A0(n1596), .A1(intDY_EWSW[29]), .B0(n1539), .B1(
intDY_EWSW[30]), .Y(n1092) );
AOI221X1TS U1341 ( .A0(n1596), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1539), .C0(n1092), .Y(n1094) );
AOI2BB2XLTS U1342 ( .B0(intDX_EWSW[7]), .B1(n1577), .A0N(n1577), .A1N(
intDX_EWSW[7]), .Y(n1093) );
NAND4XLTS U1343 ( .A(n1096), .B(n1095), .C(n1094), .D(n1093), .Y(n1124) );
OAI22X1TS U1344 ( .A0(n1587), .A1(intDX_EWSW[1]), .B0(n1583), .B1(
intDX_EWSW[17]), .Y(n1097) );
OAI22X1TS U1345 ( .A0(n1594), .A1(intDX_EWSW[20]), .B0(n1586), .B1(
intDX_EWSW[21]), .Y(n1099) );
OAI22X1TS U1346 ( .A0(n1538), .A1(intDX_EWSW[22]), .B0(n1597), .B1(
intDX_EWSW[23]), .Y(n1100) );
NAND4XLTS U1347 ( .A(n1104), .B(n1103), .C(n1102), .D(n1101), .Y(n1123) );
OAI22X1TS U1348 ( .A0(n1526), .A1(intDX_EWSW[24]), .B0(n1584), .B1(
intDX_EWSW[9]), .Y(n1105) );
AOI221X1TS U1349 ( .A0(n1526), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1584), .C0(n1105), .Y(n1112) );
OAI22X1TS U1350 ( .A0(n1591), .A1(intDX_EWSW[12]), .B0(n1585), .B1(
intDX_EWSW[13]), .Y(n1107) );
OAI22X1TS U1351 ( .A0(n1592), .A1(intDX_EWSW[14]), .B0(n1184), .B1(
intDX_EWSW[15]), .Y(n1108) );
NAND4XLTS U1352 ( .A(n1112), .B(n1111), .C(n1110), .D(n1109), .Y(n1122) );
OAI22X1TS U1353 ( .A0(n1593), .A1(intDX_EWSW[16]), .B0(n1536), .B1(
intDX_EWSW[0]), .Y(n1113) );
AOI221X1TS U1354 ( .A0(n1593), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1536), .C0(n1113), .Y(n1120) );
OAI22X1TS U1355 ( .A0(n1589), .A1(intDX_EWSW[2]), .B0(n1582), .B1(
intDX_EWSW[3]), .Y(n1114) );
OAI22X1TS U1356 ( .A0(n1590), .A1(intDX_EWSW[4]), .B0(n1534), .B1(
intDX_EWSW[5]), .Y(n1115) );
AOI221X1TS U1357 ( .A0(n1590), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1534), .C0(n1115), .Y(n1118) );
OAI22X1TS U1358 ( .A0(n1588), .A1(intDX_EWSW[8]), .B0(n1576), .B1(
intDX_EWSW[6]), .Y(n1116) );
NAND4XLTS U1359 ( .A(n1120), .B(n1119), .C(n1118), .D(n1117), .Y(n1121) );
NOR4X1TS U1360 ( .A(n1124), .B(n1123), .C(n1122), .D(n1121), .Y(n1383) );
CLKXOR2X2TS U1361 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1380) );
INVX2TS U1362 ( .A(n1380), .Y(n1127) );
INVX4TS U1363 ( .A(n1088), .Y(n1392) );
OAI21XLTS U1364 ( .A0(n1127), .A1(n1177), .B0(n1163), .Y(n1125) );
AOI22X1TS U1365 ( .A0(intDX_EWSW[31]), .A1(n1125), .B0(SIGN_FLAG_EXP), .B1(
n925), .Y(n1126) );
AOI22X1TS U1366 ( .A0(intDY_EWSW[28]), .A1(n1088), .B0(DMP_EXP_EWSW[28]),
.B1(n1177), .Y(n1129) );
OAI21XLTS U1367 ( .A0(n1598), .A1(n1389), .B0(n1129), .Y(n773) );
AOI22X1TS U1368 ( .A0(intDX_EWSW[19]), .A1(n1088), .B0(DmP_EXP_EWSW[19]),
.B1(n1319), .Y(n1130) );
OAI21XLTS U1369 ( .A0(n1540), .A1(n1389), .B0(n1130), .Y(n620) );
AOI22X1TS U1370 ( .A0(intDX_EWSW[22]), .A1(n1088), .B0(DmP_EXP_EWSW[22]),
.B1(n1319), .Y(n1131) );
OAI21XLTS U1371 ( .A0(n1538), .A1(n1389), .B0(n1131), .Y(n614) );
AOI22X1TS U1372 ( .A0(intDX_EWSW[17]), .A1(n1088), .B0(DmP_EXP_EWSW[17]),
.B1(n1319), .Y(n1132) );
OAI21XLTS U1373 ( .A0(n1583), .A1(n1389), .B0(n1132), .Y(n624) );
AOI22X1TS U1374 ( .A0(intDX_EWSW[20]), .A1(n1088), .B0(DmP_EXP_EWSW[20]),
.B1(n1319), .Y(n1133) );
OAI21XLTS U1375 ( .A0(n1594), .A1(n1389), .B0(n1133), .Y(n618) );
AOI22X1TS U1376 ( .A0(intDX_EWSW[14]), .A1(n1088), .B0(DmP_EXP_EWSW[14]),
.B1(n1083), .Y(n1134) );
OAI21XLTS U1377 ( .A0(n1592), .A1(n1163), .B0(n1134), .Y(n630) );
AOI22X1TS U1378 ( .A0(intDX_EWSW[21]), .A1(n1088), .B0(DmP_EXP_EWSW[21]),
.B1(n1319), .Y(n1135) );
OAI21XLTS U1379 ( .A0(n1586), .A1(n1389), .B0(n1135), .Y(n616) );
AOI22X1TS U1380 ( .A0(intDX_EWSW[13]), .A1(n1088), .B0(DmP_EXP_EWSW[13]),
.B1(n1319), .Y(n1136) );
OAI21XLTS U1381 ( .A0(n1585), .A1(n1163), .B0(n1136), .Y(n632) );
AOI22X1TS U1382 ( .A0(intDX_EWSW[15]), .A1(n1088), .B0(DmP_EXP_EWSW[15]),
.B1(n1319), .Y(n1138) );
OAI21XLTS U1383 ( .A0(n1184), .A1(n1163), .B0(n1138), .Y(n628) );
AOI22X1TS U1384 ( .A0(intDX_EWSW[0]), .A1(n1128), .B0(DMP_EXP_EWSW[0]), .B1(
n1381), .Y(n1139) );
OAI21XLTS U1385 ( .A0(n1536), .A1(n1392), .B0(n1139), .Y(n801) );
AOI22X1TS U1386 ( .A0(intDX_EWSW[9]), .A1(n1128), .B0(DMP_EXP_EWSW[9]), .B1(
n1177), .Y(n1140) );
OAI21XLTS U1387 ( .A0(n1584), .A1(n1183), .B0(n1140), .Y(n792) );
AOI22X1TS U1388 ( .A0(intDX_EWSW[1]), .A1(n1128), .B0(DMP_EXP_EWSW[1]), .B1(
n1381), .Y(n1141) );
OAI21XLTS U1389 ( .A0(n1587), .A1(n1183), .B0(n1141), .Y(n800) );
AOI22X1TS U1390 ( .A0(intDX_EWSW[2]), .A1(n1128), .B0(DMP_EXP_EWSW[2]), .B1(
n1177), .Y(n1142) );
OAI21XLTS U1391 ( .A0(n1589), .A1(n1183), .B0(n1142), .Y(n799) );
AOI22X1TS U1392 ( .A0(intDX_EWSW[8]), .A1(n1128), .B0(DMP_EXP_EWSW[8]), .B1(
n1319), .Y(n1143) );
OAI21XLTS U1393 ( .A0(n1588), .A1(n1183), .B0(n1143), .Y(n793) );
AOI22X1TS U1394 ( .A0(intDX_EWSW[3]), .A1(n1128), .B0(DMP_EXP_EWSW[3]), .B1(
n1381), .Y(n1144) );
OAI21XLTS U1395 ( .A0(n1582), .A1(n1392), .B0(n1144), .Y(n798) );
BUFX4TS U1396 ( .A(n1088), .Y(n1161) );
AOI22X1TS U1397 ( .A0(intDY_EWSW[30]), .A1(n1161), .B0(DMP_EXP_EWSW[30]),
.B1(n1177), .Y(n1145) );
AOI22X1TS U1398 ( .A0(intDY_EWSW[29]), .A1(n1161), .B0(DMP_EXP_EWSW[29]),
.B1(n1177), .Y(n1146) );
OAI21XLTS U1399 ( .A0(n1596), .A1(n1389), .B0(n1146), .Y(n772) );
AOI22X1TS U1400 ( .A0(intDX_EWSW[4]), .A1(n1161), .B0(DmP_EXP_EWSW[4]), .B1(
n1381), .Y(n1147) );
OAI21XLTS U1401 ( .A0(n1590), .A1(n1389), .B0(n1147), .Y(n650) );
AOI22X1TS U1402 ( .A0(intDX_EWSW[5]), .A1(n1161), .B0(DmP_EXP_EWSW[5]), .B1(
n1381), .Y(n1148) );
OAI21XLTS U1403 ( .A0(n1534), .A1(n1163), .B0(n1148), .Y(n648) );
AOI22X1TS U1404 ( .A0(intDX_EWSW[7]), .A1(n1161), .B0(DmP_EXP_EWSW[7]), .B1(
n1381), .Y(n1149) );
OAI21XLTS U1405 ( .A0(n1577), .A1(n1163), .B0(n1149), .Y(n644) );
AOI22X1TS U1406 ( .A0(intDX_EWSW[6]), .A1(n1161), .B0(DmP_EXP_EWSW[6]), .B1(
n1381), .Y(n1150) );
OAI21XLTS U1407 ( .A0(n1576), .A1(n1163), .B0(n1150), .Y(n646) );
AOI22X1TS U1408 ( .A0(intDX_EWSW[18]), .A1(n1161), .B0(DmP_EXP_EWSW[18]),
.B1(n1319), .Y(n1151) );
OAI21XLTS U1409 ( .A0(n1599), .A1(n1389), .B0(n1151), .Y(n622) );
AOI22X1TS U1410 ( .A0(intDX_EWSW[0]), .A1(n1161), .B0(DmP_EXP_EWSW[0]), .B1(
n1177), .Y(n1152) );
OAI21XLTS U1411 ( .A0(n1536), .A1(n1389), .B0(n1152), .Y(n658) );
AOI22X1TS U1412 ( .A0(intDX_EWSW[10]), .A1(n1161), .B0(DmP_EXP_EWSW[10]),
.B1(n1177), .Y(n1153) );
OAI21XLTS U1413 ( .A0(n930), .A1(n1163), .B0(n1153), .Y(n638) );
AOI22X1TS U1414 ( .A0(intDX_EWSW[1]), .A1(n1161), .B0(DmP_EXP_EWSW[1]), .B1(
n1319), .Y(n1154) );
OAI21XLTS U1415 ( .A0(n1587), .A1(n1389), .B0(n1154), .Y(n656) );
AOI22X1TS U1416 ( .A0(intDX_EWSW[9]), .A1(n1161), .B0(DmP_EXP_EWSW[9]), .B1(
n1319), .Y(n1155) );
AOI22X1TS U1417 ( .A0(intDX_EWSW[2]), .A1(n1161), .B0(DmP_EXP_EWSW[2]), .B1(
n1177), .Y(n1156) );
AOI22X1TS U1418 ( .A0(intDX_EWSW[8]), .A1(n1161), .B0(DmP_EXP_EWSW[8]), .B1(
n1083), .Y(n1157) );
OAI21XLTS U1419 ( .A0(n1588), .A1(n1163), .B0(n1157), .Y(n642) );
AOI22X1TS U1420 ( .A0(intDX_EWSW[12]), .A1(n1161), .B0(DmP_EXP_EWSW[12]),
.B1(n1083), .Y(n1158) );
OAI21XLTS U1421 ( .A0(n1591), .A1(n1163), .B0(n1158), .Y(n634) );
AOI22X1TS U1422 ( .A0(intDX_EWSW[11]), .A1(n1161), .B0(DmP_EXP_EWSW[11]),
.B1(n1083), .Y(n1159) );
OAI21XLTS U1423 ( .A0(n1179), .A1(n1163), .B0(n1159), .Y(n636) );
AOI22X1TS U1424 ( .A0(intDX_EWSW[3]), .A1(n1161), .B0(DmP_EXP_EWSW[3]), .B1(
n1083), .Y(n1160) );
OAI21XLTS U1425 ( .A0(n1582), .A1(n1389), .B0(n1160), .Y(n652) );
AOI22X1TS U1426 ( .A0(DmP_EXP_EWSW[27]), .A1(n1319), .B0(intDX_EWSW[27]),
.B1(n1161), .Y(n1162) );
OAI21XLTS U1427 ( .A0(n1595), .A1(n1163), .B0(n1162), .Y(n608) );
BUFX3TS U1428 ( .A(n1128), .Y(n1181) );
AOI22X1TS U1429 ( .A0(intDX_EWSW[16]), .A1(n1181), .B0(DMP_EXP_EWSW[16]),
.B1(n1177), .Y(n1164) );
OAI21XLTS U1430 ( .A0(n1593), .A1(n1183), .B0(n1164), .Y(n785) );
AOI222X1TS U1431 ( .A0(n1088), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1381), .C0(intDY_EWSW[23]), .C1(n1181), .Y(n1165) );
INVX2TS U1432 ( .A(n1165), .Y(n612) );
AOI22X1TS U1433 ( .A0(intDX_EWSW[22]), .A1(n1128), .B0(DMP_EXP_EWSW[22]),
.B1(n1381), .Y(n1166) );
OAI21XLTS U1434 ( .A0(n1538), .A1(n1392), .B0(n1166), .Y(n779) );
AOI22X1TS U1435 ( .A0(n955), .A1(n1319), .B0(intDX_EWSW[27]), .B1(n1128),
.Y(n1167) );
OAI21XLTS U1436 ( .A0(n1595), .A1(n1392), .B0(n1167), .Y(n774) );
AOI22X1TS U1437 ( .A0(intDX_EWSW[20]), .A1(n1128), .B0(DMP_EXP_EWSW[20]),
.B1(n1381), .Y(n1168) );
OAI21XLTS U1438 ( .A0(n1594), .A1(n1392), .B0(n1168), .Y(n781) );
AOI22X1TS U1439 ( .A0(DMP_EXP_EWSW[23]), .A1(n1319), .B0(intDX_EWSW[23]),
.B1(n1128), .Y(n1169) );
OAI21XLTS U1440 ( .A0(n1597), .A1(n1183), .B0(n1169), .Y(n778) );
AOI22X1TS U1441 ( .A0(intDX_EWSW[21]), .A1(n1128), .B0(DMP_EXP_EWSW[21]),
.B1(n1177), .Y(n1170) );
OAI21XLTS U1442 ( .A0(n1586), .A1(n1392), .B0(n1170), .Y(n780) );
AOI22X1TS U1443 ( .A0(intDX_EWSW[19]), .A1(n1181), .B0(DMP_EXP_EWSW[19]),
.B1(n1177), .Y(n1171) );
OAI21XLTS U1444 ( .A0(n1540), .A1(n1392), .B0(n1171), .Y(n782) );
AOI22X1TS U1445 ( .A0(intDX_EWSW[18]), .A1(n1181), .B0(DMP_EXP_EWSW[18]),
.B1(n1381), .Y(n1172) );
OAI21XLTS U1446 ( .A0(n1599), .A1(n1183), .B0(n1172), .Y(n783) );
AOI22X1TS U1447 ( .A0(intDX_EWSW[10]), .A1(n1181), .B0(DMP_EXP_EWSW[10]),
.B1(n1177), .Y(n1173) );
OAI21XLTS U1448 ( .A0(n930), .A1(n1183), .B0(n1173), .Y(n791) );
AOI22X1TS U1449 ( .A0(intDX_EWSW[14]), .A1(n1181), .B0(DMP_EXP_EWSW[14]),
.B1(n1319), .Y(n1174) );
OAI21XLTS U1450 ( .A0(n1592), .A1(n1183), .B0(n1174), .Y(n787) );
AOI22X1TS U1451 ( .A0(intDX_EWSW[17]), .A1(n1181), .B0(DMP_EXP_EWSW[17]),
.B1(n1381), .Y(n1175) );
OAI21XLTS U1452 ( .A0(n1583), .A1(n1183), .B0(n1175), .Y(n784) );
AOI22X1TS U1453 ( .A0(intDX_EWSW[12]), .A1(n1181), .B0(DMP_EXP_EWSW[12]),
.B1(n1319), .Y(n1176) );
OAI21XLTS U1454 ( .A0(n1591), .A1(n1183), .B0(n1176), .Y(n789) );
AOI22X1TS U1455 ( .A0(intDX_EWSW[11]), .A1(n1181), .B0(DMP_EXP_EWSW[11]),
.B1(n1381), .Y(n1178) );
OAI21XLTS U1456 ( .A0(n1179), .A1(n1183), .B0(n1178), .Y(n790) );
AOI22X1TS U1457 ( .A0(intDX_EWSW[13]), .A1(n1181), .B0(DMP_EXP_EWSW[13]),
.B1(n1381), .Y(n1180) );
AOI22X1TS U1458 ( .A0(intDX_EWSW[15]), .A1(n1181), .B0(DMP_EXP_EWSW[15]),
.B1(n1381), .Y(n1182) );
OAI21XLTS U1459 ( .A0(n1184), .A1(n1183), .B0(n1182), .Y(n786) );
NOR2XLTS U1460 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1186)
);
OAI21XLTS U1461 ( .A0(n1186), .A1(n1185), .B0(n1304), .Y(n1187) );
AOI211X1TS U1462 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1198), .B0(n1188), .C0(
n1187), .Y(n1190) );
NOR3X1TS U1463 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1303),
.Y(n1189) );
NAND2X1TS U1464 ( .A(n1189), .B(n962), .Y(n1201) );
NAND2X1TS U1465 ( .A(Raw_mant_NRM_SWR[1]), .B(n1189), .Y(n1296) );
AOI31X1TS U1466 ( .A0(n1190), .A1(n1201), .A2(n1296), .B0(n920), .Y(n1291)
);
BUFX4TS U1467 ( .A(OP_FLAG_SFG), .Y(n1425) );
AOI2BB2X1TS U1468 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1425), .A0N(n1425),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_40_B_2_) );
AOI32X1TS U1469 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n926), .A2(n1562), .B0(
Raw_mant_NRM_SWR[22]), .B1(n926), .Y(n1192) );
AOI32X1TS U1470 ( .A0(n1524), .A1(n1193), .A2(n1192), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1193), .Y(n1194) );
OAI21XLTS U1471 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1553), .B0(n1528), .Y(n1197) );
AOI21X1TS U1472 ( .A0(n1198), .A1(n1197), .B0(n1196), .Y(n1200) );
NAND2X1TS U1473 ( .A(Raw_mant_NRM_SWR[12]), .B(n1199), .Y(n1297) );
OAI211X1TS U1474 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1201), .B0(n1200), .C0(
n1297), .Y(n1307) );
OAI211X1TS U1475 ( .A0(n1558), .A1(n1205), .B0(n1204), .C0(n1203), .Y(n1210)
);
OR2X2TS U1476 ( .A(n920), .B(n1210), .Y(n1335) );
BUFX4TS U1477 ( .A(n1236), .Y(n1343) );
AOI21X1TS U1478 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n920), .B0(n1206), .Y(
n1208) );
NOR2X2TS U1479 ( .A(n923), .B(n1208), .Y(n1352) );
NAND2X2TS U1480 ( .A(n1210), .B(Shift_reg_FLAGS_7[1]), .Y(n1345) );
INVX2TS U1481 ( .A(n1345), .Y(n1333) );
AOI22X1TS U1482 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1333), .B0(n1236), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1212) );
AOI22X1TS U1483 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1353), .B0(n959), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1211) );
NAND2X1TS U1484 ( .A(n1212), .B(n1211), .Y(n1252) );
AOI22X1TS U1485 ( .A0(n1358), .A1(Data_array_SWR[3]), .B0(n1209), .B1(n1252),
.Y(n1215) );
BUFX3TS U1486 ( .A(n1213), .Y(n1263) );
NAND2X1TS U1487 ( .A(Raw_mant_NRM_SWR[19]), .B(n1263), .Y(n1214) );
AOI22X1TS U1488 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1333), .B0(n1343), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1217) );
AOI22X1TS U1489 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1353), .B0(n959), .B1(n954), .Y(n1216) );
NAND2X1TS U1490 ( .A(n1217), .B(n1216), .Y(n1351) );
AOI22X1TS U1491 ( .A0(n1358), .A1(Data_array_SWR[2]), .B0(n1209), .B1(n1351),
.Y(n1219) );
NAND2X1TS U1492 ( .A(Raw_mant_NRM_SWR[20]), .B(n1263), .Y(n1218) );
AOI22X1TS U1493 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1333), .B0(n1236), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1221) );
AOI22X1TS U1494 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1353), .B0(n959), .B1(n953), .Y(n1220) );
NAND2X1TS U1495 ( .A(n1221), .B(n1220), .Y(n1268) );
AOI22X1TS U1496 ( .A0(n923), .A1(Data_array_SWR[7]), .B0(n1209), .B1(n1268),
.Y(n1223) );
NAND2X1TS U1497 ( .A(Raw_mant_NRM_SWR[15]), .B(n1263), .Y(n1222) );
AOI22X1TS U1498 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1333), .B0(n1236), .B1(
n953), .Y(n1225) );
AOI22X1TS U1499 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1353), .B0(n959), .B1(n947), .Y(n1224) );
NAND2X1TS U1500 ( .A(n1225), .B(n1224), .Y(n1272) );
AOI22X1TS U1501 ( .A0(n1358), .A1(Data_array_SWR[6]), .B0(n1209), .B1(n1272),
.Y(n1227) );
NAND2X1TS U1502 ( .A(Raw_mant_NRM_SWR[16]), .B(n1263), .Y(n1226) );
AOI22X1TS U1503 ( .A0(n1358), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1263), .Y(n1230) );
NAND2X1TS U1504 ( .A(n1228), .B(n1333), .Y(n1278) );
AOI22X1TS U1505 ( .A0(n923), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1263), .Y(n1233) );
AOI22X1TS U1506 ( .A0(n1358), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1263), .Y(n1235) );
AOI22X1TS U1507 ( .A0(n959), .A1(DmP_mant_SHT1_SW[18]), .B0(n1236), .B1(n948), .Y(n1237) );
AOI21X1TS U1508 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1353), .B0(n1238), .Y(n1338) );
OAI22X1TS U1509 ( .A0(n1246), .A1(n957), .B0(n1558), .B1(n1278), .Y(n1239)
);
AOI21X1TS U1510 ( .A0(n923), .A1(Data_array_SWR[18]), .B0(n1239), .Y(n1240)
);
AOI22X1TS U1511 ( .A0(n1358), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1263), .Y(n1242) );
AOI22X1TS U1512 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1333), .B0(n1236), .B1(n949), .Y(n1244) );
AOI21X1TS U1513 ( .A0(n960), .A1(DmP_mant_SHT1_SW[14]), .B0(n1245), .Y(n1342) );
OAI2BB2XLTS U1514 ( .B0(n1246), .B1(n1207), .A0N(Raw_mant_NRM_SWR[6]), .A1N(
n1263), .Y(n1247) );
AOI21X1TS U1515 ( .A0(n923), .A1(Data_array_SWR[16]), .B0(n1247), .Y(n1248)
);
AOI21X1TS U1516 ( .A0(n1353), .A1(n962), .B0(n960), .Y(n1330) );
OAI22X1TS U1517 ( .A0(n1249), .A1(n957), .B0(n1360), .B1(n1613), .Y(n1250)
);
AOI21X1TS U1518 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1350), .B0(n1250), .Y(n1251) );
AOI22X1TS U1519 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1353), .B0(n1343), .B1(
n954), .Y(n1255) );
AOI22X1TS U1520 ( .A0(n1358), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1350), .Y(n1254) );
NAND2X1TS U1521 ( .A(n1352), .B(n1252), .Y(n1253) );
AOI22X1TS U1522 ( .A0(n1358), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1263), .Y(n1258) );
AOI22X1TS U1523 ( .A0(n923), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1263), .Y(n1262) );
AOI22X1TS U1524 ( .A0(n1358), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1263), .Y(n1266) );
AOI22X1TS U1525 ( .A0(n1358), .A1(Data_array_SWR[5]), .B0(n1352), .B1(n1268),
.Y(n1270) );
NAND2X1TS U1526 ( .A(Raw_mant_NRM_SWR[19]), .B(n1350), .Y(n1269) );
AOI22X1TS U1527 ( .A0(n1358), .A1(Data_array_SWR[4]), .B0(n1352), .B1(n1272),
.Y(n1274) );
NAND2X1TS U1528 ( .A(Raw_mant_NRM_SWR[20]), .B(n1350), .Y(n1273) );
AOI22X1TS U1529 ( .A0(n959), .A1(DmP_mant_SHT1_SW[8]), .B0(n1236), .B1(n952),
.Y(n1276) );
AOI21X1TS U1530 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1353), .B0(n1277), .Y(
n1348) );
OAI22X1TS U1531 ( .A0(n1279), .A1(n957), .B0(n1606), .B1(n1278), .Y(n1280)
);
AOI21X1TS U1532 ( .A0(n923), .A1(Data_array_SWR[8]), .B0(n1280), .Y(n1281)
);
AOI2BB2X1TS U1533 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1425), .A0N(n1425), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1431) );
NAND2X1TS U1534 ( .A(n1431), .B(DMP_SFG[0]), .Y(n1433) );
INVX2TS U1535 ( .A(n1433), .Y(n1282) );
NOR2XLTS U1536 ( .A(n1283), .B(SIGN_FLAG_SHT1SHT2), .Y(n1284) );
OAI2BB2XLTS U1537 ( .B0(n1284), .B1(n1315), .A0N(n1660), .A1N(
final_result_ieee[31]), .Y(n591) );
AOI22X1TS U1538 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1425), .B0(n963), .B1(n968),
.Y(intadd_40_CI) );
INVX2TS U1539 ( .A(intadd_40_B_2_), .Y(n1287) );
OAI21X1TS U1540 ( .A0(DMP_SFG[7]), .A1(intadd_40_B_1_), .B0(n1285), .Y(n1286) );
AOI222X1TS U1541 ( .A0(n1551), .A1(n1287), .B0(n1551), .B1(n1286), .C0(n1287), .C1(n1286), .Y(n1288) );
INVX2TS U1542 ( .A(n1289), .Y(n1290) );
NAND2X1TS U1543 ( .A(n1556), .B(n1290), .Y(DP_OP_15J35_125_2314_n8) );
MX2X1TS U1544 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n659) );
MX2X1TS U1545 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n664) );
MX2X1TS U1546 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n669) );
MX2X1TS U1547 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n674) );
MX2X1TS U1548 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n679) );
MX2X1TS U1549 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n684) );
MX2X1TS U1550 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n689) );
MX2X1TS U1551 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n694) );
AO21XLTS U1552 ( .A0(LZD_output_NRM2_EW[4]), .A1(n920), .B0(n1291), .Y(n574)
);
OAI211X1TS U1553 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1292), .C0(n1548), .Y(n1300) );
OAI2BB1X1TS U1554 ( .A0N(n1294), .A1N(n1548), .B0(n1293), .Y(n1295) );
NAND4XLTS U1555 ( .A(n1297), .B(n1300), .C(n1296), .D(n1295), .Y(n1298) );
OAI21X1TS U1556 ( .A0(n1299), .A1(n1298), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1361) );
OAI2BB1X1TS U1557 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n920), .B0(n1361), .Y(
n560) );
OAI22X1TS U1558 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1304), .B0(n1303), .B1(
n1604), .Y(n1306) );
OAI31X1TS U1559 ( .A0(n1308), .A1(n1307), .A2(n1306), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1356) );
OAI2BB1X1TS U1560 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n920), .B0(n1356), .Y(
n571) );
OAI2BB1X1TS U1561 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n920), .B0(n1345), .Y(
n566) );
NAND2X2TS U1562 ( .A(n1393), .B(Shift_reg_FLAGS_7[0]), .Y(n1312) );
OA22X1TS U1563 ( .A0(n1312), .A1(n1309), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n809) );
OA22X1TS U1564 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n808) );
OA22X1TS U1565 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n807) );
OA22X1TS U1566 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n806) );
OA22X1TS U1567 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n805) );
OA22X1TS U1568 ( .A0(n1312), .A1(n1310), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n804) );
OA22X1TS U1569 ( .A0(n1312), .A1(n1311), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n803) );
INVX2TS U1570 ( .A(n1315), .Y(n1314) );
AO22XLTS U1571 ( .A0(n1314), .A1(n1313), .B0(n965), .B1(
final_result_ieee[30]), .Y(n802) );
OA21XLTS U1572 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1315),
.Y(n606) );
INVX2TS U1573 ( .A(n1318), .Y(n1317) );
AOI22X1TS U1574 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1317), .B1(n1533), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1575 ( .A(n1317), .B(n1316), .Y(n919) );
AOI22X1TS U1576 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1318), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1533), .Y(n1322) );
AO22XLTS U1577 ( .A0(n1320), .A1(Shift_reg_FLAGS_7_6), .B0(n1321), .B1(n1322), .Y(n917) );
AOI22X1TS U1578 ( .A0(n1321), .A1(n1319), .B0(n1387), .B1(n1320), .Y(n916)
);
AOI22X1TS U1579 ( .A0(n1321), .A1(n1387), .B0(n1385), .B1(n1320), .Y(n915)
);
AOI22X1TS U1580 ( .A0(n1321), .A1(n1441), .B0(n920), .B1(n1320), .Y(n912) );
BUFX4TS U1581 ( .A(n1324), .Y(n1329) );
AO22XLTS U1582 ( .A0(n1329), .A1(Data_X[1]), .B0(n922), .B1(intDX_EWSW[1]),
.Y(n909) );
BUFX3TS U1583 ( .A(n1324), .Y(n1323) );
AO22XLTS U1584 ( .A0(n1323), .A1(Data_X[2]), .B0(n922), .B1(intDX_EWSW[2]),
.Y(n908) );
BUFX3TS U1585 ( .A(n1324), .Y(n1327) );
AO22XLTS U1586 ( .A0(n1327), .A1(Data_X[3]), .B0(n1328), .B1(intDX_EWSW[3]),
.Y(n907) );
AO22XLTS U1587 ( .A0(n1325), .A1(Data_X[4]), .B0(n922), .B1(intDX_EWSW[4]),
.Y(n906) );
AO22XLTS U1588 ( .A0(n1329), .A1(Data_X[5]), .B0(n922), .B1(intDX_EWSW[5]),
.Y(n905) );
AO22XLTS U1589 ( .A0(n1329), .A1(Data_X[6]), .B0(n1328), .B1(intDX_EWSW[6]),
.Y(n904) );
AO22XLTS U1590 ( .A0(n1324), .A1(Data_X[7]), .B0(n922), .B1(intDX_EWSW[7]),
.Y(n903) );
AO22XLTS U1591 ( .A0(n1327), .A1(Data_X[8]), .B0(n922), .B1(intDX_EWSW[8]),
.Y(n902) );
AO22XLTS U1592 ( .A0(n1327), .A1(Data_X[9]), .B0(n1328), .B1(intDX_EWSW[9]),
.Y(n901) );
AO22XLTS U1593 ( .A0(n1327), .A1(Data_X[11]), .B0(n922), .B1(intDX_EWSW[11]),
.Y(n899) );
INVX2TS U1594 ( .A(n1325), .Y(n1328) );
AO22XLTS U1595 ( .A0(n1329), .A1(Data_X[12]), .B0(n1328), .B1(intDX_EWSW[12]), .Y(n898) );
AO22XLTS U1596 ( .A0(n1325), .A1(Data_X[13]), .B0(n922), .B1(intDX_EWSW[13]),
.Y(n897) );
AO22XLTS U1597 ( .A0(n1324), .A1(Data_X[14]), .B0(n922), .B1(intDX_EWSW[14]),
.Y(n896) );
AO22XLTS U1598 ( .A0(n1329), .A1(Data_X[15]), .B0(n1328), .B1(intDX_EWSW[15]), .Y(n895) );
AO22XLTS U1599 ( .A0(n1323), .A1(Data_X[16]), .B0(n922), .B1(intDX_EWSW[16]),
.Y(n894) );
AO22XLTS U1600 ( .A0(n1329), .A1(Data_X[17]), .B0(n922), .B1(intDX_EWSW[17]),
.Y(n893) );
AO22XLTS U1601 ( .A0(n1324), .A1(Data_X[20]), .B0(n1328), .B1(intDX_EWSW[20]), .Y(n890) );
AO22XLTS U1602 ( .A0(n1325), .A1(Data_X[21]), .B0(n922), .B1(intDX_EWSW[21]),
.Y(n889) );
AO22XLTS U1603 ( .A0(n1325), .A1(Data_X[22]), .B0(n922), .B1(intDX_EWSW[22]),
.Y(n888) );
AO22XLTS U1604 ( .A0(n1323), .A1(Data_X[23]), .B0(n1328), .B1(intDX_EWSW[23]), .Y(n887) );
AO22XLTS U1605 ( .A0(n921), .A1(intDX_EWSW[24]), .B0(n1324), .B1(Data_X[24]),
.Y(n886) );
AO22XLTS U1606 ( .A0(n921), .A1(intDX_EWSW[25]), .B0(n1327), .B1(Data_X[25]),
.Y(n885) );
AO22XLTS U1607 ( .A0(n921), .A1(intDX_EWSW[26]), .B0(n1323), .B1(Data_X[26]),
.Y(n884) );
AO22XLTS U1608 ( .A0(n1327), .A1(Data_X[27]), .B0(n921), .B1(intDX_EWSW[27]),
.Y(n883) );
AO22XLTS U1609 ( .A0(n921), .A1(intDX_EWSW[28]), .B0(n1327), .B1(Data_X[28]),
.Y(n882) );
AO22XLTS U1610 ( .A0(n921), .A1(intDX_EWSW[29]), .B0(n1323), .B1(Data_X[29]),
.Y(n881) );
AO22XLTS U1611 ( .A0(n921), .A1(intDX_EWSW[30]), .B0(n1323), .B1(Data_X[30]),
.Y(n880) );
AO22XLTS U1612 ( .A0(n1327), .A1(add_subt), .B0(n921), .B1(intAS), .Y(n878)
);
AO22XLTS U1613 ( .A0(n921), .A1(intDY_EWSW[0]), .B0(n1323), .B1(Data_Y[0]),
.Y(n876) );
AO22XLTS U1614 ( .A0(n921), .A1(intDY_EWSW[1]), .B0(n1323), .B1(Data_Y[1]),
.Y(n875) );
AO22XLTS U1615 ( .A0(n1326), .A1(intDY_EWSW[2]), .B0(n1323), .B1(Data_Y[2]),
.Y(n874) );
AO22XLTS U1616 ( .A0(n1326), .A1(intDY_EWSW[3]), .B0(n1323), .B1(Data_Y[3]),
.Y(n873) );
AO22XLTS U1617 ( .A0(n1326), .A1(intDY_EWSW[4]), .B0(n1323), .B1(Data_Y[4]),
.Y(n872) );
AO22XLTS U1618 ( .A0(n1326), .A1(intDY_EWSW[5]), .B0(n1323), .B1(Data_Y[5]),
.Y(n871) );
AO22XLTS U1619 ( .A0(n921), .A1(intDY_EWSW[6]), .B0(n1324), .B1(Data_Y[6]),
.Y(n870) );
AO22XLTS U1620 ( .A0(n921), .A1(intDY_EWSW[7]), .B0(n1329), .B1(Data_Y[7]),
.Y(n869) );
AO22XLTS U1621 ( .A0(n921), .A1(intDY_EWSW[8]), .B0(n1329), .B1(Data_Y[8]),
.Y(n868) );
AO22XLTS U1622 ( .A0(n1326), .A1(intDY_EWSW[9]), .B0(n1324), .B1(Data_Y[9]),
.Y(n867) );
AO22XLTS U1623 ( .A0(n921), .A1(intDY_EWSW[10]), .B0(n1329), .B1(Data_Y[10]),
.Y(n866) );
AO22XLTS U1624 ( .A0(n1326), .A1(intDY_EWSW[11]), .B0(n1329), .B1(Data_Y[11]), .Y(n865) );
AO22XLTS U1625 ( .A0(n1326), .A1(intDY_EWSW[12]), .B0(n1329), .B1(Data_Y[12]), .Y(n864) );
AO22XLTS U1626 ( .A0(n1326), .A1(intDY_EWSW[13]), .B0(n1329), .B1(Data_Y[13]), .Y(n863) );
AO22XLTS U1627 ( .A0(n921), .A1(intDY_EWSW[14]), .B0(n1329), .B1(Data_Y[14]),
.Y(n862) );
AO22XLTS U1628 ( .A0(n1326), .A1(intDY_EWSW[15]), .B0(n1329), .B1(Data_Y[15]), .Y(n861) );
AO22XLTS U1629 ( .A0(n1326), .A1(intDY_EWSW[16]), .B0(n1329), .B1(Data_Y[16]), .Y(n860) );
AO22XLTS U1630 ( .A0(n921), .A1(intDY_EWSW[17]), .B0(n1329), .B1(Data_Y[17]),
.Y(n859) );
AO22XLTS U1631 ( .A0(n1326), .A1(intDY_EWSW[18]), .B0(n1329), .B1(Data_Y[18]), .Y(n858) );
AO22XLTS U1632 ( .A0(n1326), .A1(intDY_EWSW[19]), .B0(n1329), .B1(Data_Y[19]), .Y(n857) );
AO22XLTS U1633 ( .A0(n1326), .A1(intDY_EWSW[20]), .B0(n1327), .B1(Data_Y[20]), .Y(n856) );
AO22XLTS U1634 ( .A0(n921), .A1(intDY_EWSW[21]), .B0(n1327), .B1(Data_Y[21]),
.Y(n855) );
AO22XLTS U1635 ( .A0(n1326), .A1(intDY_EWSW[22]), .B0(n1327), .B1(Data_Y[22]), .Y(n854) );
AO22XLTS U1636 ( .A0(n1326), .A1(intDY_EWSW[23]), .B0(n1325), .B1(Data_Y[23]), .Y(n853) );
AO22XLTS U1637 ( .A0(n921), .A1(intDY_EWSW[24]), .B0(n1324), .B1(Data_Y[24]),
.Y(n852) );
AO22XLTS U1638 ( .A0(n921), .A1(intDY_EWSW[25]), .B0(n1324), .B1(Data_Y[25]),
.Y(n851) );
AO22XLTS U1639 ( .A0(n1326), .A1(intDY_EWSW[26]), .B0(n1324), .B1(Data_Y[26]), .Y(n850) );
AO22XLTS U1640 ( .A0(n1326), .A1(intDY_EWSW[27]), .B0(n1325), .B1(Data_Y[27]), .Y(n849) );
AO22XLTS U1641 ( .A0(n1327), .A1(Data_Y[29]), .B0(n922), .B1(intDY_EWSW[29]),
.Y(n847) );
AO22XLTS U1642 ( .A0(n1327), .A1(Data_Y[30]), .B0(n922), .B1(intDY_EWSW[30]),
.Y(n846) );
OAI22X1TS U1643 ( .A0(n1330), .A1(n958), .B0(n1360), .B1(n1535), .Y(n844) );
AOI211X1TS U1644 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n920), .B0(n1343), .C0(
n1332), .Y(n1337) );
OAI2BB2XLTS U1645 ( .B0(n1337), .B1(n957), .A0N(n923), .A1N(
Data_array_SWR[24]), .Y(n843) );
AOI22X1TS U1646 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1333), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1343), .Y(n1334) );
AOI21X1TS U1647 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n960), .B0(n1336), .Y(n1339) );
OAI222X1TS U1648 ( .A0(n1360), .A1(n1612), .B0(n1207), .B1(n1337), .C0(n957),
.C1(n1339), .Y(n841) );
OAI222X1TS U1649 ( .A0(n1625), .A1(n1360), .B0(n1207), .B1(n1339), .C0(n958),
.C1(n1338), .Y(n839) );
AOI22X1TS U1650 ( .A0(n959), .A1(DmP_mant_SHT1_SW[12]), .B0(n1343), .B1(n950), .Y(n1340) );
AOI21X1TS U1651 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1353), .B0(n1341), .Y(
n1347) );
OAI222X1TS U1652 ( .A0(n1541), .A1(n1360), .B0(n1207), .B1(n1342), .C0(n958),
.C1(n1347), .Y(n833) );
AOI22X1TS U1653 ( .A0(n959), .A1(DmP_mant_SHT1_SW[10]), .B0(n1343), .B1(n951), .Y(n1344) );
AOI21X1TS U1654 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1353), .B0(n1346), .Y(
n1349) );
OAI222X1TS U1655 ( .A0(n1617), .A1(n1360), .B0(n1207), .B1(n1347), .C0(n958),
.C1(n1349), .Y(n831) );
OAI222X1TS U1656 ( .A0(n1607), .A1(n1360), .B0(n1207), .B1(n1349), .C0(n958),
.C1(n1348), .Y(n829) );
AOI22X1TS U1657 ( .A0(n923), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1350), .Y(n1355) );
AOI22X1TS U1658 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1353), .B0(n1352), .B1(
n1351), .Y(n1354) );
NAND2X1TS U1659 ( .A(n1355), .B(n1354), .Y(n819) );
AOI32X1TS U1660 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1360), .A2(n920), .B0(
shift_value_SHT2_EWR[2]), .B1(n923), .Y(n1357) );
NAND2X1TS U1661 ( .A(n1357), .B(n1356), .Y(n818) );
AOI32X1TS U1662 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1360), .A2(n920), .B0(
shift_value_SHT2_EWR[3]), .B1(n923), .Y(n1362) );
NAND2X1TS U1663 ( .A(n1362), .B(n1361), .Y(n817) );
INVX4TS U1664 ( .A(n1387), .Y(n1396) );
AOI21X1TS U1665 ( .A0(DMP_EXP_EWSW[23]), .A1(n977), .B0(n1367), .Y(n1363) );
INVX4TS U1666 ( .A(n1387), .Y(n1398) );
AOI2BB2XLTS U1667 ( .B0(n1396), .B1(n1363), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1398), .Y(n814) );
NOR2X1TS U1668 ( .A(n1542), .B(DMP_EXP_EWSW[24]), .Y(n1366) );
AOI21X1TS U1669 ( .A0(DMP_EXP_EWSW[24]), .A1(n1542), .B0(n1366), .Y(n1364)
);
XNOR2X1TS U1670 ( .A(n1367), .B(n1364), .Y(n1365) );
AO22XLTS U1671 ( .A0(n1398), .A1(n1365), .B0(n1387), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n813) );
INVX4TS U1672 ( .A(n1387), .Y(n1384) );
OAI22X1TS U1673 ( .A0(n1367), .A1(n1366), .B0(DmP_EXP_EWSW[24]), .B1(n1543),
.Y(n1370) );
NAND2X1TS U1674 ( .A(DmP_EXP_EWSW[25]), .B(n1605), .Y(n1371) );
XNOR2X1TS U1675 ( .A(n1370), .B(n1368), .Y(n1369) );
AO22XLTS U1676 ( .A0(n1384), .A1(n1369), .B0(n1626), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n812) );
AOI22X1TS U1677 ( .A0(DMP_EXP_EWSW[25]), .A1(n1621), .B0(n1371), .B1(n1370),
.Y(n1374) );
NOR2X1TS U1678 ( .A(n1616), .B(DMP_EXP_EWSW[26]), .Y(n1375) );
AOI21X1TS U1679 ( .A0(DMP_EXP_EWSW[26]), .A1(n1616), .B0(n1375), .Y(n1372)
);
XNOR2X1TS U1680 ( .A(n1374), .B(n1372), .Y(n1373) );
AO22XLTS U1681 ( .A0(n1398), .A1(n1373), .B0(n1626), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n811) );
OAI22X1TS U1682 ( .A0(n1375), .A1(n1374), .B0(DmP_EXP_EWSW[26]), .B1(n1620),
.Y(n1377) );
XNOR2X1TS U1683 ( .A(DmP_EXP_EWSW[27]), .B(n955), .Y(n1376) );
XOR2XLTS U1684 ( .A(n1377), .B(n1376), .Y(n1378) );
BUFX3TS U1685 ( .A(n1626), .Y(n1386) );
AO22XLTS U1686 ( .A0(n1384), .A1(n1378), .B0(n1386), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n810) );
OAI222X1TS U1687 ( .A0(n1389), .A1(n1618), .B0(n1543), .B1(
Shift_reg_FLAGS_7_6), .C0(n1526), .C1(n1392), .Y(n777) );
OAI222X1TS U1688 ( .A0(n1389), .A1(n1544), .B0(n1605), .B1(
Shift_reg_FLAGS_7_6), .C0(n1630), .C1(n1392), .Y(n776) );
OAI222X1TS U1689 ( .A0(n1389), .A1(n1545), .B0(n1620), .B1(
Shift_reg_FLAGS_7_6), .C0(n1390), .C1(n1392), .Y(n775) );
OAI21XLTS U1690 ( .A0(n1380), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1379) );
AOI21X1TS U1691 ( .A0(n1380), .A1(intDX_EWSW[31]), .B0(n1379), .Y(n1382) );
AO21XLTS U1692 ( .A0(OP_FLAG_EXP), .A1(n1381), .B0(n1382), .Y(n770) );
AO22XLTS U1693 ( .A0(n1383), .A1(n1382), .B0(ZERO_FLAG_EXP), .B1(n1381), .Y(
n769) );
AO22XLTS U1694 ( .A0(n1384), .A1(DMP_EXP_EWSW[0]), .B0(n1386), .B1(
DMP_SHT1_EWSW[0]), .Y(n767) );
AO22XLTS U1695 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1628), .B1(
DMP_SHT2_EWSW[0]), .Y(n766) );
INVX2TS U1696 ( .A(n1517), .Y(n1523) );
AO22XLTS U1697 ( .A0(n1398), .A1(DMP_EXP_EWSW[1]), .B0(n1386), .B1(
DMP_SHT1_EWSW[1]), .Y(n764) );
AO22XLTS U1698 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1385), .B1(
DMP_SHT2_EWSW[1]), .Y(n763) );
INVX4TS U1699 ( .A(n980), .Y(n1516) );
AO22XLTS U1700 ( .A0(n1384), .A1(DMP_EXP_EWSW[2]), .B0(n1386), .B1(
DMP_SHT1_EWSW[2]), .Y(n761) );
AO22XLTS U1701 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1385), .B1(
DMP_SHT2_EWSW[2]), .Y(n760) );
BUFX3TS U1702 ( .A(n980), .Y(n1507) );
AO22XLTS U1703 ( .A0(n1507), .A1(DMP_SFG[2]), .B0(n1516), .B1(
DMP_SHT2_EWSW[2]), .Y(n759) );
AO22XLTS U1704 ( .A0(n1384), .A1(DMP_EXP_EWSW[3]), .B0(n1386), .B1(
DMP_SHT1_EWSW[3]), .Y(n758) );
AO22XLTS U1705 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1385), .B1(
DMP_SHT2_EWSW[3]), .Y(n757) );
AO22XLTS U1706 ( .A0(n1507), .A1(DMP_SFG[3]), .B0(n1516), .B1(
DMP_SHT2_EWSW[3]), .Y(n756) );
AO22XLTS U1707 ( .A0(n1384), .A1(DMP_EXP_EWSW[4]), .B0(n1386), .B1(
DMP_SHT1_EWSW[4]), .Y(n755) );
AO22XLTS U1708 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1385), .B1(
DMP_SHT2_EWSW[4]), .Y(n754) );
AO22XLTS U1709 ( .A0(n1507), .A1(DMP_SFG[4]), .B0(n1510), .B1(
DMP_SHT2_EWSW[4]), .Y(n753) );
AO22XLTS U1710 ( .A0(n1384), .A1(DMP_EXP_EWSW[5]), .B0(n1386), .B1(
DMP_SHT1_EWSW[5]), .Y(n752) );
AO22XLTS U1711 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1385), .B1(
DMP_SHT2_EWSW[5]), .Y(n751) );
AO22XLTS U1712 ( .A0(n1384), .A1(DMP_EXP_EWSW[6]), .B0(n1386), .B1(
DMP_SHT1_EWSW[6]), .Y(n749) );
AO22XLTS U1713 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1385), .B1(
DMP_SHT2_EWSW[6]), .Y(n748) );
AO22XLTS U1714 ( .A0(n1384), .A1(DMP_EXP_EWSW[7]), .B0(n1386), .B1(
DMP_SHT1_EWSW[7]), .Y(n746) );
AO22XLTS U1715 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1385), .B1(
DMP_SHT2_EWSW[7]), .Y(n745) );
AO22XLTS U1716 ( .A0(n1384), .A1(DMP_EXP_EWSW[8]), .B0(n1386), .B1(
DMP_SHT1_EWSW[8]), .Y(n743) );
AO22XLTS U1717 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1385), .B1(
DMP_SHT2_EWSW[8]), .Y(n742) );
AO22XLTS U1718 ( .A0(n1384), .A1(DMP_EXP_EWSW[9]), .B0(n1386), .B1(
DMP_SHT1_EWSW[9]), .Y(n740) );
AO22XLTS U1719 ( .A0(n1399), .A1(DMP_SHT1_EWSW[9]), .B0(n1385), .B1(
DMP_SHT2_EWSW[9]), .Y(n739) );
AO22XLTS U1720 ( .A0(n1384), .A1(DMP_EXP_EWSW[10]), .B0(n1386), .B1(
DMP_SHT1_EWSW[10]), .Y(n737) );
BUFX4TS U1721 ( .A(n1385), .Y(n1395) );
AO22XLTS U1722 ( .A0(n1399), .A1(DMP_SHT1_EWSW[10]), .B0(n1395), .B1(
DMP_SHT2_EWSW[10]), .Y(n736) );
AO22XLTS U1723 ( .A0(n1430), .A1(DMP_SFG[10]), .B0(n1516), .B1(
DMP_SHT2_EWSW[10]), .Y(n735) );
AO22XLTS U1724 ( .A0(n1384), .A1(DMP_EXP_EWSW[11]), .B0(n1626), .B1(
DMP_SHT1_EWSW[11]), .Y(n734) );
AO22XLTS U1725 ( .A0(n1399), .A1(DMP_SHT1_EWSW[11]), .B0(n1395), .B1(
DMP_SHT2_EWSW[11]), .Y(n733) );
BUFX3TS U1726 ( .A(n980), .Y(n1506) );
AO22XLTS U1727 ( .A0(n1506), .A1(DMP_SFG[11]), .B0(n1516), .B1(
DMP_SHT2_EWSW[11]), .Y(n732) );
BUFX4TS U1728 ( .A(n1626), .Y(n1388) );
AO22XLTS U1729 ( .A0(n1384), .A1(DMP_EXP_EWSW[12]), .B0(n1388), .B1(
DMP_SHT1_EWSW[12]), .Y(n731) );
AO22XLTS U1730 ( .A0(n1399), .A1(DMP_SHT1_EWSW[12]), .B0(n1395), .B1(
DMP_SHT2_EWSW[12]), .Y(n730) );
AO22XLTS U1731 ( .A0(n1507), .A1(DMP_SFG[12]), .B0(n1516), .B1(
DMP_SHT2_EWSW[12]), .Y(n729) );
BUFX3TS U1732 ( .A(n1626), .Y(n1397) );
AO22XLTS U1733 ( .A0(n1384), .A1(DMP_EXP_EWSW[13]), .B0(n1397), .B1(
DMP_SHT1_EWSW[13]), .Y(n728) );
AO22XLTS U1734 ( .A0(n1399), .A1(DMP_SHT1_EWSW[13]), .B0(n1395), .B1(
DMP_SHT2_EWSW[13]), .Y(n727) );
AO22XLTS U1735 ( .A0(n1430), .A1(DMP_SFG[13]), .B0(n1516), .B1(
DMP_SHT2_EWSW[13]), .Y(n726) );
AO22XLTS U1736 ( .A0(n1384), .A1(DMP_EXP_EWSW[14]), .B0(n1626), .B1(
DMP_SHT1_EWSW[14]), .Y(n725) );
AO22XLTS U1737 ( .A0(n1399), .A1(DMP_SHT1_EWSW[14]), .B0(n1395), .B1(
DMP_SHT2_EWSW[14]), .Y(n724) );
AO22XLTS U1738 ( .A0(n1507), .A1(DMP_SFG[14]), .B0(n1516), .B1(
DMP_SHT2_EWSW[14]), .Y(n723) );
AO22XLTS U1739 ( .A0(n1384), .A1(DMP_EXP_EWSW[15]), .B0(n1388), .B1(
DMP_SHT1_EWSW[15]), .Y(n722) );
AO22XLTS U1740 ( .A0(n1399), .A1(DMP_SHT1_EWSW[15]), .B0(n1395), .B1(
DMP_SHT2_EWSW[15]), .Y(n721) );
AO22XLTS U1741 ( .A0(n1430), .A1(DMP_SFG[15]), .B0(n1516), .B1(
DMP_SHT2_EWSW[15]), .Y(n720) );
AO22XLTS U1742 ( .A0(n1384), .A1(DMP_EXP_EWSW[16]), .B0(n1397), .B1(
DMP_SHT1_EWSW[16]), .Y(n719) );
AO22XLTS U1743 ( .A0(busy), .A1(DMP_SHT1_EWSW[16]), .B0(n1395), .B1(
DMP_SHT2_EWSW[16]), .Y(n718) );
AO22XLTS U1744 ( .A0(n1398), .A1(DMP_EXP_EWSW[17]), .B0(n1387), .B1(
DMP_SHT1_EWSW[17]), .Y(n716) );
AO22XLTS U1745 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n1395), .B1(
DMP_SHT2_EWSW[17]), .Y(n715) );
AO22XLTS U1746 ( .A0(n1398), .A1(DMP_EXP_EWSW[18]), .B0(n1388), .B1(
DMP_SHT1_EWSW[18]), .Y(n713) );
AO22XLTS U1747 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1395), .B1(
DMP_SHT2_EWSW[18]), .Y(n712) );
AO22XLTS U1748 ( .A0(n1398), .A1(DMP_EXP_EWSW[19]), .B0(n1397), .B1(
DMP_SHT1_EWSW[19]), .Y(n710) );
AO22XLTS U1749 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1395), .B1(
DMP_SHT2_EWSW[19]), .Y(n709) );
AO22XLTS U1750 ( .A0(n1430), .A1(DMP_SFG[19]), .B0(n1516), .B1(
DMP_SHT2_EWSW[19]), .Y(n708) );
AO22XLTS U1751 ( .A0(n1398), .A1(DMP_EXP_EWSW[20]), .B0(n1387), .B1(
DMP_SHT1_EWSW[20]), .Y(n707) );
AO22XLTS U1752 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1395), .B1(
DMP_SHT2_EWSW[20]), .Y(n706) );
AO22XLTS U1753 ( .A0(n1398), .A1(DMP_EXP_EWSW[21]), .B0(n1388), .B1(
DMP_SHT1_EWSW[21]), .Y(n704) );
AO22XLTS U1754 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1395), .B1(
DMP_SHT2_EWSW[21]), .Y(n703) );
AO22XLTS U1755 ( .A0(n1398), .A1(DMP_EXP_EWSW[22]), .B0(n1397), .B1(
DMP_SHT1_EWSW[22]), .Y(n701) );
AO22XLTS U1756 ( .A0(n1399), .A1(DMP_SHT1_EWSW[22]), .B0(n1385), .B1(
DMP_SHT2_EWSW[22]), .Y(n700) );
AO22XLTS U1757 ( .A0(n1430), .A1(DMP_SFG[22]), .B0(n1516), .B1(
DMP_SHT2_EWSW[22]), .Y(n699) );
AO22XLTS U1758 ( .A0(n1398), .A1(DMP_EXP_EWSW[23]), .B0(n1397), .B1(
DMP_SHT1_EWSW[23]), .Y(n698) );
AO22XLTS U1759 ( .A0(n1399), .A1(DMP_SHT1_EWSW[23]), .B0(n1385), .B1(
DMP_SHT2_EWSW[23]), .Y(n697) );
AO22XLTS U1760 ( .A0(n1523), .A1(DMP_SHT2_EWSW[23]), .B0(n1507), .B1(
DMP_SFG[23]), .Y(n696) );
AO22XLTS U1761 ( .A0(n1546), .A1(DMP_SFG[23]), .B0(n1629), .B1(
DMP_exp_NRM_EW[0]), .Y(n695) );
AO22XLTS U1762 ( .A0(n1398), .A1(DMP_EXP_EWSW[24]), .B0(n1397), .B1(
DMP_SHT1_EWSW[24]), .Y(n693) );
AO22XLTS U1763 ( .A0(n1399), .A1(DMP_SHT1_EWSW[24]), .B0(n1395), .B1(
DMP_SHT2_EWSW[24]), .Y(n692) );
AO22XLTS U1764 ( .A0(n1510), .A1(DMP_SHT2_EWSW[24]), .B0(n1507), .B1(
DMP_SFG[24]), .Y(n691) );
AO22XLTS U1765 ( .A0(n1546), .A1(DMP_SFG[24]), .B0(n1629), .B1(
DMP_exp_NRM_EW[1]), .Y(n690) );
AO22XLTS U1766 ( .A0(n1398), .A1(DMP_EXP_EWSW[25]), .B0(n1397), .B1(
DMP_SHT1_EWSW[25]), .Y(n688) );
AO22XLTS U1767 ( .A0(n1399), .A1(DMP_SHT1_EWSW[25]), .B0(n1395), .B1(
DMP_SHT2_EWSW[25]), .Y(n687) );
AO22XLTS U1768 ( .A0(n1516), .A1(DMP_SHT2_EWSW[25]), .B0(n1507), .B1(
DMP_SFG[25]), .Y(n686) );
AO22XLTS U1769 ( .A0(n1546), .A1(DMP_SFG[25]), .B0(n1629), .B1(
DMP_exp_NRM_EW[2]), .Y(n685) );
AO22XLTS U1770 ( .A0(n1398), .A1(DMP_EXP_EWSW[26]), .B0(n1397), .B1(
DMP_SHT1_EWSW[26]), .Y(n683) );
AO22XLTS U1771 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n1395), .B1(
DMP_SHT2_EWSW[26]), .Y(n682) );
AO22XLTS U1772 ( .A0(n1523), .A1(DMP_SHT2_EWSW[26]), .B0(n1507), .B1(
DMP_SFG[26]), .Y(n681) );
AO22XLTS U1773 ( .A0(n1546), .A1(DMP_SFG[26]), .B0(n1629), .B1(
DMP_exp_NRM_EW[3]), .Y(n680) );
AO22XLTS U1774 ( .A0(n1398), .A1(n955), .B0(n1397), .B1(DMP_SHT1_EWSW[27]),
.Y(n678) );
AO22XLTS U1775 ( .A0(n1399), .A1(DMP_SHT1_EWSW[27]), .B0(n1395), .B1(
DMP_SHT2_EWSW[27]), .Y(n677) );
AO22XLTS U1776 ( .A0(n1516), .A1(DMP_SHT2_EWSW[27]), .B0(n980), .B1(
DMP_SFG[27]), .Y(n676) );
AO22XLTS U1777 ( .A0(n1546), .A1(DMP_SFG[27]), .B0(n1629), .B1(
DMP_exp_NRM_EW[4]), .Y(n675) );
AO22XLTS U1778 ( .A0(n1398), .A1(DMP_EXP_EWSW[28]), .B0(n1397), .B1(
DMP_SHT1_EWSW[28]), .Y(n673) );
AO22XLTS U1779 ( .A0(n1399), .A1(DMP_SHT1_EWSW[28]), .B0(n1395), .B1(
DMP_SHT2_EWSW[28]), .Y(n672) );
AO22XLTS U1780 ( .A0(n1523), .A1(DMP_SHT2_EWSW[28]), .B0(n1507), .B1(
DMP_SFG[28]), .Y(n671) );
INVX4TS U1781 ( .A(n1441), .Y(n1440) );
AO22XLTS U1782 ( .A0(n1440), .A1(DMP_SFG[28]), .B0(n1629), .B1(
DMP_exp_NRM_EW[5]), .Y(n670) );
AO22XLTS U1783 ( .A0(n1398), .A1(DMP_EXP_EWSW[29]), .B0(n1397), .B1(
DMP_SHT1_EWSW[29]), .Y(n668) );
AO22XLTS U1784 ( .A0(n1399), .A1(DMP_SHT1_EWSW[29]), .B0(n1395), .B1(
DMP_SHT2_EWSW[29]), .Y(n667) );
AO22XLTS U1785 ( .A0(n1523), .A1(DMP_SHT2_EWSW[29]), .B0(n1507), .B1(
DMP_SFG[29]), .Y(n666) );
AO22XLTS U1786 ( .A0(n1546), .A1(DMP_SFG[29]), .B0(n1629), .B1(
DMP_exp_NRM_EW[6]), .Y(n665) );
AO22XLTS U1787 ( .A0(n1527), .A1(DMP_EXP_EWSW[30]), .B0(n1397), .B1(
DMP_SHT1_EWSW[30]), .Y(n663) );
AO22XLTS U1788 ( .A0(n1399), .A1(DMP_SHT1_EWSW[30]), .B0(n1395), .B1(
DMP_SHT2_EWSW[30]), .Y(n662) );
AO22XLTS U1789 ( .A0(n1523), .A1(DMP_SHT2_EWSW[30]), .B0(n1507), .B1(
DMP_SFG[30]), .Y(n661) );
AO22XLTS U1790 ( .A0(n1440), .A1(DMP_SFG[30]), .B0(n1629), .B1(
DMP_exp_NRM_EW[7]), .Y(n660) );
AO22XLTS U1791 ( .A0(n1396), .A1(DmP_EXP_EWSW[16]), .B0(n1626), .B1(
DmP_mant_SHT1_SW[16]), .Y(n625) );
AO22XLTS U1792 ( .A0(n1396), .A1(DmP_EXP_EWSW[17]), .B0(n1387), .B1(
DmP_mant_SHT1_SW[17]), .Y(n623) );
AO22XLTS U1793 ( .A0(n1396), .A1(DmP_EXP_EWSW[19]), .B0(n1387), .B1(n948),
.Y(n619) );
AO22XLTS U1794 ( .A0(n1396), .A1(DmP_EXP_EWSW[21]), .B0(n1387), .B1(
DmP_mant_SHT1_SW[21]), .Y(n615) );
OAI222X1TS U1795 ( .A0(n1392), .A1(n1618), .B0(n1542), .B1(
Shift_reg_FLAGS_7_6), .C0(n1526), .C1(n1389), .Y(n611) );
OAI222X1TS U1796 ( .A0(n1392), .A1(n1544), .B0(n1621), .B1(
Shift_reg_FLAGS_7_6), .C0(n1630), .C1(n1389), .Y(n610) );
OAI222X1TS U1797 ( .A0(n1392), .A1(n1545), .B0(n1616), .B1(
Shift_reg_FLAGS_7_6), .C0(n1390), .C1(n1389), .Y(n609) );
NOR2XLTS U1798 ( .A(n1393), .B(n1660), .Y(n1394) );
AO21XLTS U1799 ( .A0(underflow_flag), .A1(n965), .B0(n1394), .Y(n607) );
AO22XLTS U1800 ( .A0(n1396), .A1(ZERO_FLAG_EXP), .B0(n1387), .B1(
ZERO_FLAG_SHT1), .Y(n605) );
AO22XLTS U1801 ( .A0(n1399), .A1(ZERO_FLAG_SHT1), .B0(n1395), .B1(
ZERO_FLAG_SHT2), .Y(n604) );
AO22XLTS U1802 ( .A0(n1523), .A1(ZERO_FLAG_SHT2), .B0(n1517), .B1(
ZERO_FLAG_SFG), .Y(n603) );
AO22XLTS U1803 ( .A0(n1546), .A1(ZERO_FLAG_SFG), .B0(n1629), .B1(
ZERO_FLAG_NRM), .Y(n602) );
AO22XLTS U1804 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n965), .B1(zero_flag), .Y(n600) );
AO22XLTS U1805 ( .A0(n1396), .A1(OP_FLAG_EXP), .B0(OP_FLAG_SHT1), .B1(n1626),
.Y(n599) );
AO22XLTS U1806 ( .A0(n1399), .A1(OP_FLAG_SHT1), .B0(n1628), .B1(OP_FLAG_SHT2), .Y(n598) );
AO22XLTS U1807 ( .A0(n1506), .A1(OP_FLAG_SFG), .B0(n1516), .B1(OP_FLAG_SHT2),
.Y(n597) );
AO22XLTS U1808 ( .A0(n1398), .A1(SIGN_FLAG_EXP), .B0(n1397), .B1(
SIGN_FLAG_SHT1), .Y(n596) );
AO22XLTS U1809 ( .A0(n1399), .A1(SIGN_FLAG_SHT1), .B0(n1628), .B1(
SIGN_FLAG_SHT2), .Y(n595) );
AO22XLTS U1810 ( .A0(n1523), .A1(SIGN_FLAG_SHT2), .B0(n1517), .B1(
SIGN_FLAG_SFG), .Y(n594) );
AO22XLTS U1811 ( .A0(n1440), .A1(SIGN_FLAG_SFG), .B0(n1629), .B1(
SIGN_FLAG_NRM), .Y(n593) );
INVX2TS U1812 ( .A(OP_FLAG_SFG), .Y(n1400) );
AOI2BB2XLTS U1813 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n963), .A0N(n1400), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_38_CI) );
AOI22X1TS U1814 ( .A0(n1440), .A1(intadd_38_SUM_0_), .B0(n1550), .B1(n1441),
.Y(n590) );
AOI2BB2XLTS U1815 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n963), .A0N(n1400), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_38_B_1_) );
AOI2BB2XLTS U1816 ( .B0(n1440), .B1(intadd_38_SUM_1_), .A0N(
Raw_mant_NRM_SWR[13]), .A1N(n1546), .Y(n589) );
AOI2BB2XLTS U1817 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n963), .A0N(n1400), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_38_B_2_) );
AOI22X1TS U1818 ( .A0(n1446), .A1(intadd_38_SUM_2_), .B0(n1548), .B1(n1441),
.Y(n588) );
AOI2BB2XLTS U1819 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n963), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_38_B_3_) );
AOI2BB2XLTS U1820 ( .B0(n1440), .B1(intadd_38_SUM_3_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1546), .Y(n587) );
AOI2BB2XLTS U1821 ( .B0(DmP_mant_SFG_SWR[16]), .B1(n1400), .A0N(n1400),
.A1N(DmP_mant_SFG_SWR[16]), .Y(intadd_38_B_4_) );
AOI22X1TS U1822 ( .A0(n1446), .A1(intadd_38_SUM_4_), .B0(n1606), .B1(n1441),
.Y(n586) );
AOI22X1TS U1823 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1400), .B0(n1425), .B1(
n975), .Y(intadd_38_B_5_) );
AOI22X1TS U1824 ( .A0(n1446), .A1(intadd_38_SUM_5_), .B0(n1570), .B1(n1441),
.Y(n585) );
AOI2BB2XLTS U1825 ( .B0(DmP_mant_SFG_SWR[18]), .B1(n1400), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[18]), .Y(intadd_38_B_6_) );
AOI2BB2XLTS U1826 ( .B0(n1440), .B1(intadd_38_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1546), .Y(n584) );
AOI2BB2XLTS U1827 ( .B0(DmP_mant_SFG_SWR[19]), .B1(n963), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[19]), .Y(intadd_38_B_7_) );
AOI2BB2XLTS U1828 ( .B0(n1440), .B1(intadd_38_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1546), .Y(n583) );
AOI22X1TS U1829 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1661), .B0(OP_FLAG_SFG),
.B1(n974), .Y(intadd_38_B_8_) );
AOI2BB2XLTS U1830 ( .B0(n1440), .B1(intadd_38_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1546), .Y(n582) );
AOI22X1TS U1831 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n963), .B0(n1425), .B1(n973), .Y(intadd_38_B_9_) );
AOI22X1TS U1832 ( .A0(n1446), .A1(intadd_38_SUM_9_), .B0(n1562), .B1(n1441),
.Y(n581) );
AOI2BB2XLTS U1833 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1400), .A0N(n1661),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_38_B_10_) );
AOI22X1TS U1834 ( .A0(n1446), .A1(intadd_38_SUM_10_), .B0(n1525), .B1(n1441),
.Y(n580) );
AOI2BB2XLTS U1835 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n963), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[23]), .Y(intadd_38_B_11_) );
AOI22X1TS U1836 ( .A0(n1440), .A1(intadd_38_SUM_11_), .B0(n926), .B1(n1441),
.Y(n579) );
AOI22X1TS U1837 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1400), .B0(n1425), .B1(
n972), .Y(intadd_38_B_12_) );
AOI22X1TS U1838 ( .A0(n1446), .A1(intadd_38_SUM_12_), .B0(n1524), .B1(n1441),
.Y(n578) );
AOI22X1TS U1839 ( .A0(DmP_mant_SFG_SWR[25]), .A1(OP_FLAG_SFG), .B0(n1661),
.B1(n976), .Y(n1401) );
XNOR2X1TS U1840 ( .A(intadd_38_n1), .B(n1401), .Y(n1402) );
AOI22X1TS U1841 ( .A0(n1446), .A1(n1402), .B0(n1547), .B1(n1441), .Y(n577)
);
AOI22X1TS U1842 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n963), .B0(n1425), .B1(n970),
.Y(intadd_39_CI) );
INVX2TS U1843 ( .A(intadd_39_B_2_), .Y(n1406) );
NAND2BXLTS U1844 ( .AN(intadd_39_CI), .B(DMP_SFG[2]), .Y(n1404) );
AOI222X1TS U1845 ( .A0(DMP_SFG[4]), .A1(n1406), .B0(DMP_SFG[4]), .B1(n1405),
.C0(n1406), .C1(n1405), .Y(n1408) );
AOI2BB2X1TS U1846 ( .B0(DmP_mant_SFG_SWR[7]), .B1(OP_FLAG_SFG), .A0N(n1425),
.A1N(DmP_mant_SFG_SWR[7]), .Y(n1407) );
NAND2X1TS U1847 ( .A(n1407), .B(DMP_SFG[5]), .Y(n1442) );
NOR2X1TS U1848 ( .A(n1407), .B(DMP_SFG[5]), .Y(n1443) );
AOI21X1TS U1849 ( .A0(n1408), .A1(n1442), .B0(n1443), .Y(intadd_40_B_0_) );
AOI2BB2XLTS U1850 ( .B0(n1409), .B1(DMP_SFG[9]), .A0N(DMP_SFG[9]), .A1N(
n1409), .Y(n1410) );
XNOR2X1TS U1851 ( .A(intadd_40_n1), .B(n1410), .Y(n1411) );
AOI22X1TS U1852 ( .A0(n1446), .A1(n1411), .B0(n1549), .B1(n1441), .Y(n575)
);
AOI22X1TS U1853 ( .A0(Data_array_SWR[13]), .A1(n1001), .B0(Data_array_SWR[9]), .B1(n997), .Y(n1414) );
AOI22X1TS U1854 ( .A0(Data_array_SWR[5]), .A1(n998), .B0(Data_array_SWR[1]),
.B1(n928), .Y(n1413) );
OAI211X1TS U1855 ( .A0(n1419), .A1(n1531), .B0(n1414), .C0(n1413), .Y(n1499)
);
AOI22X1TS U1856 ( .A0(Data_array_SWR[24]), .A1(n1492), .B0(n1496), .B1(n1499), .Y(n1415) );
AOI22X1TS U1857 ( .A0(n961), .A1(n1415), .B0(n1506), .B1(n966), .Y(n573) );
AOI22X1TS U1858 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1661), .B0(n1425), .B1(n966), .Y(n1416) );
AOI2BB2XLTS U1859 ( .B0(n1440), .B1(n1416), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1440), .Y(n572) );
AOI22X1TS U1860 ( .A0(Data_array_SWR[12]), .A1(n998), .B0(Data_array_SWR[16]), .B1(n997), .Y(n1418) );
AOI22X1TS U1861 ( .A0(Data_array_SWR[20]), .A1(n1001), .B0(
Data_array_SWR[24]), .B1(n1450), .Y(n1417) );
NAND2X1TS U1862 ( .A(n1418), .B(n1417), .Y(n1493) );
INVX2TS U1863 ( .A(n1419), .Y(n1491) );
AOI22X1TS U1864 ( .A0(n961), .A1(n1489), .B0(n968), .B1(n1506), .Y(n570) );
AOI22X1TS U1865 ( .A0(Data_array_SWR[12]), .A1(n1001), .B0(Data_array_SWR[8]), .B1(n997), .Y(n1423) );
AOI22X1TS U1866 ( .A0(Data_array_SWR[4]), .A1(n998), .B0(Data_array_SWR[0]),
.B1(n928), .Y(n1422) );
OAI211X1TS U1867 ( .A0(n1465), .A1(n1531), .B0(n1423), .C0(n1422), .Y(n1519)
);
AOI22X1TS U1868 ( .A0(Data_array_SWR[25]), .A1(n1492), .B0(n1496), .B1(n1519), .Y(n1424) );
AOI22X1TS U1869 ( .A0(n961), .A1(n1424), .B0(n969), .B1(n980), .Y(n565) );
AOI22X1TS U1870 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n963), .B0(n1425), .B1(n969),
.Y(n1426) );
AOI2BB2XLTS U1871 ( .B0(n1440), .B1(n1426), .A0N(n962), .A1N(n1440), .Y(n564) );
OAI22X1TS U1872 ( .A0(n1541), .A1(n1427), .B0(n1607), .B1(n1448), .Y(n1429)
);
INVX2TS U1873 ( .A(n998), .Y(n1437) );
OAI22X1TS U1874 ( .A0(n1483), .A1(n1531), .B0(n1614), .B1(n1437), .Y(n1428)
);
AOI211X1TS U1875 ( .A0(Data_array_SWR[2]), .A1(n928), .B0(n1429), .C0(n1428),
.Y(n1497) );
OAI22X1TS U1876 ( .A0(n1520), .A1(n1497), .B0(n1613), .B1(n1467), .Y(n1488)
);
OAI21XLTS U1877 ( .A0(n1431), .A1(DMP_SFG[0]), .B0(n1433), .Y(n1432) );
AOI22X1TS U1878 ( .A0(n1446), .A1(n1432), .B0(n1553), .B1(n1441), .Y(n562)
);
XNOR2X1TS U1879 ( .A(DMP_SFG[1]), .B(n1433), .Y(n1435) );
XNOR2X1TS U1880 ( .A(n1435), .B(n1434), .Y(n1436) );
AOI22X1TS U1881 ( .A0(n1446), .A1(n1436), .B0(n1604), .B1(n1441), .Y(n561)
);
AO22XLTS U1882 ( .A0(Data_array_SWR[15]), .A1(n1001), .B0(Data_array_SWR[11]), .B1(n997), .Y(n1439) );
OAI22X1TS U1883 ( .A0(n1453), .A1(n1531), .B0(n1615), .B1(n1437), .Y(n1438)
);
AOI211X1TS U1884 ( .A0(Data_array_SWR[3]), .A1(n928), .B0(n1439), .C0(n1438),
.Y(n1494) );
OAI22X1TS U1885 ( .A0(n1520), .A1(n1494), .B0(n1612), .B1(n1467), .Y(n1487)
);
AO22XLTS U1886 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[3]), .B0(n1510), .B1(n1487), .Y(n558) );
AOI22X1TS U1887 ( .A0(n1446), .A1(intadd_39_SUM_0_), .B0(n1528), .B1(n1441),
.Y(n557) );
AOI2BB2XLTS U1888 ( .B0(n1440), .B1(intadd_39_SUM_1_), .A0N(
Raw_mant_NRM_SWR[5]), .A1N(n1546), .Y(n556) );
AOI22X1TS U1889 ( .A0(n1446), .A1(intadd_39_SUM_2_), .B0(n1558), .B1(n1441),
.Y(n555) );
NAND2BXLTS U1890 ( .AN(n1443), .B(n1442), .Y(n1444) );
XNOR2X1TS U1891 ( .A(intadd_39_n1), .B(n1444), .Y(n1445) );
AOI22X1TS U1892 ( .A0(n1446), .A1(n1445), .B0(n1552), .B1(n1441), .Y(n554)
);
AOI22X1TS U1893 ( .A0(Data_array_SWR[10]), .A1(n998), .B0(Data_array_SWR[18]), .B1(n1001), .Y(n1447) );
OAI21XLTS U1894 ( .A0(n1541), .A1(n1448), .B0(n1447), .Y(n1449) );
AOI21X1TS U1895 ( .A0(Data_array_SWR[22]), .A1(n1450), .B0(n1449), .Y(n1452)
);
OAI222X1TS U1896 ( .A0(n1495), .A1(n1614), .B0(n1520), .B1(n1452), .C0(n1484), .C1(n1453), .Y(n1451) );
AO22XLTS U1897 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[6]), .B0(n1510), .B1(n1451), .Y(n553) );
AO22XLTS U1898 ( .A0(n1498), .A1(n1451), .B0(final_result_ieee[4]), .B1(
n1660), .Y(n552) );
OAI222X1TS U1899 ( .A0(n1467), .A1(n1614), .B0(n1466), .B1(n1453), .C0(n1496), .C1(n1452), .Y(n1511) );
AO22XLTS U1900 ( .A0(n1498), .A1(n1511), .B0(final_result_ieee[17]), .B1(
n1660), .Y(n551) );
AOI22X1TS U1901 ( .A0(Data_array_SWR[20]), .A1(n944), .B0(Data_array_SWR[24]), .B1(n945), .Y(n1471) );
AOI22X1TS U1902 ( .A0(Data_array_SWR[12]), .A1(n997), .B0(Data_array_SWR[8]),
.B1(n998), .Y(n1455) );
NAND2X1TS U1903 ( .A(Data_array_SWR[16]), .B(n1001), .Y(n1454) );
OAI211X1TS U1904 ( .A0(n1471), .A1(n1531), .B0(n1455), .C0(n1454), .Y(n1458)
);
AOI22X1TS U1905 ( .A0(n961), .A1(n1457), .B0(n970), .B1(n980), .Y(n550) );
INVX2TS U1906 ( .A(n1498), .Y(n1500) );
OAI2BB2XLTS U1907 ( .B0(n1457), .B1(n1500), .A0N(final_result_ieee[2]),
.A1N(n1660), .Y(n549) );
OAI2BB2XLTS U1908 ( .B0(n1513), .B1(n1500), .A0N(final_result_ieee[19]),
.A1N(n1660), .Y(n548) );
AOI22X1TS U1909 ( .A0(Data_array_SWR[12]), .A1(n1521), .B0(
Data_array_SWR[13]), .B1(n1492), .Y(n1459) );
OAI221X1TS U1910 ( .A0(n1520), .A1(n1461), .B0(n1496), .B1(n1462), .C0(n1459), .Y(n1501) );
AO22XLTS U1911 ( .A0(n1498), .A1(n1501), .B0(final_result_ieee[10]), .B1(
n1660), .Y(n547) );
AOI22X1TS U1912 ( .A0(Data_array_SWR[12]), .A1(n1492), .B0(
Data_array_SWR[13]), .B1(n1521), .Y(n1460) );
OAI221X1TS U1913 ( .A0(n1520), .A1(n1462), .B0(n1496), .B1(n1461), .C0(n1460), .Y(n1502) );
AO22XLTS U1914 ( .A0(n1498), .A1(n1502), .B0(final_result_ieee[11]), .B1(
n1660), .Y(n546) );
AO22XLTS U1915 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[9]), .B0(n1510), .B1(n1463), .Y(n545) );
OAI222X1TS U1916 ( .A0(n1467), .A1(n1619), .B0(n1466), .B1(n1465), .C0(n1496), .C1(n1464), .Y(n1505) );
AO22XLTS U1917 ( .A0(n1498), .A1(n1505), .B0(final_result_ieee[14]), .B1(
n965), .Y(n543) );
AOI22X1TS U1918 ( .A0(Data_array_SWR[13]), .A1(n997), .B0(Data_array_SWR[9]),
.B1(n998), .Y(n1470) );
AOI22X1TS U1919 ( .A0(Data_array_SWR[17]), .A1(n1001), .B0(
shift_value_SHT2_EWR[4]), .B1(n1468), .Y(n1469) );
NAND2X1TS U1920 ( .A(n1470), .B(n1469), .Y(n1475) );
INVX2TS U1921 ( .A(n1471), .Y(n1474) );
AOI22X1TS U1922 ( .A0(n961), .A1(n1473), .B0(n971), .B1(n1517), .Y(n542) );
OAI2BB2XLTS U1923 ( .B0(n1473), .B1(n1500), .A0N(final_result_ieee[3]),
.A1N(n1660), .Y(n541) );
OAI2BB2XLTS U1924 ( .B0(n1512), .B1(n1500), .A0N(final_result_ieee[18]),
.A1N(n1660), .Y(n540) );
AOI22X1TS U1925 ( .A0(Data_array_SWR[14]), .A1(n1521), .B0(
Data_array_SWR[11]), .B1(n1492), .Y(n1476) );
OAI221X1TS U1926 ( .A0(n1520), .A1(n1478), .B0(n1496), .B1(n1477), .C0(n1476), .Y(n1503) );
AO22XLTS U1927 ( .A0(n1498), .A1(n1503), .B0(final_result_ieee[12]), .B1(
n965), .Y(n538) );
AOI22X1TS U1928 ( .A0(Data_array_SWR[10]), .A1(n1521), .B0(
Data_array_SWR[15]), .B1(n1492), .Y(n1479) );
OAI221X1TS U1929 ( .A0(n1520), .A1(n1481), .B0(n1496), .B1(n1480), .C0(n1479), .Y(n1482) );
AO22XLTS U1930 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[10]), .B0(n1510), .B1(
n1482), .Y(n537) );
AO22XLTS U1931 ( .A0(n1498), .A1(n1482), .B0(final_result_ieee[8]), .B1(n965), .Y(n536) );
OAI222X1TS U1932 ( .A0(n1495), .A1(n1615), .B0(n1520), .B1(n1485), .C0(n1484), .C1(n1483), .Y(n1486) );
AO22XLTS U1933 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[7]), .B0(n1510), .B1(n1486), .Y(n534) );
AO22XLTS U1934 ( .A0(n1498), .A1(n1486), .B0(final_result_ieee[5]), .B1(n965), .Y(n533) );
AO22XLTS U1935 ( .A0(n1498), .A1(n1487), .B0(final_result_ieee[1]), .B1(n965), .Y(n531) );
AO22XLTS U1936 ( .A0(n1498), .A1(n1488), .B0(final_result_ieee[0]), .B1(n965), .Y(n530) );
OAI2BB2XLTS U1937 ( .B0(n1489), .B1(n1500), .A0N(final_result_ieee[6]),
.A1N(n1660), .Y(n529) );
OAI2BB2XLTS U1938 ( .B0(n1508), .B1(n1500), .A0N(final_result_ieee[15]),
.A1N(n1660), .Y(n528) );
OAI22X1TS U1939 ( .A0(n1494), .A1(n1496), .B0(n1612), .B1(n1495), .Y(n1514)
);
AO22XLTS U1940 ( .A0(n1498), .A1(n1514), .B0(final_result_ieee[20]), .B1(
n965), .Y(n527) );
OAI22X1TS U1941 ( .A0(n1497), .A1(n1496), .B0(n1613), .B1(n1495), .Y(n1515)
);
AO22XLTS U1942 ( .A0(n1498), .A1(n1515), .B0(final_result_ieee[21]), .B1(
n965), .Y(n526) );
AOI22X1TS U1943 ( .A0(Data_array_SWR[24]), .A1(n1521), .B0(n1520), .B1(n1499), .Y(n1518) );
OAI2BB2XLTS U1944 ( .B0(n1518), .B1(n1500), .A0N(final_result_ieee[22]),
.A1N(n1660), .Y(n525) );
AO22XLTS U1945 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[12]), .B0(n1510), .B1(
n1501), .Y(n524) );
AO22XLTS U1946 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[13]), .B0(n1510), .B1(
n1502), .Y(n523) );
AO22XLTS U1947 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[14]), .B0(n1510), .B1(
n1503), .Y(n522) );
AO22XLTS U1948 ( .A0(n980), .A1(DmP_mant_SFG_SWR[15]), .B0(n1516), .B1(n1504), .Y(n521) );
AO22XLTS U1949 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[16]), .B0(n1510), .B1(
n1505), .Y(n520) );
AOI22X1TS U1950 ( .A0(n961), .A1(n1508), .B0(n1507), .B1(n975), .Y(n519) );
AO22XLTS U1951 ( .A0(n980), .A1(DmP_mant_SFG_SWR[18]), .B0(n1510), .B1(n1509), .Y(n518) );
AO22XLTS U1952 ( .A0(n980), .A1(DmP_mant_SFG_SWR[19]), .B0(n1516), .B1(n1511), .Y(n517) );
AOI22X1TS U1953 ( .A0(n961), .A1(n1512), .B0(n1517), .B1(n974), .Y(n516) );
AOI22X1TS U1954 ( .A0(n961), .A1(n1513), .B0(n1517), .B1(n973), .Y(n515) );
AO22XLTS U1955 ( .A0(n980), .A1(DmP_mant_SFG_SWR[22]), .B0(n1516), .B1(n1514), .Y(n514) );
AO22XLTS U1956 ( .A0(n980), .A1(DmP_mant_SFG_SWR[23]), .B0(n1516), .B1(n1515), .Y(n513) );
AOI22X1TS U1957 ( .A0(n961), .A1(n1518), .B0(n1517), .B1(n972), .Y(n512) );
AOI22X1TS U1958 ( .A0(Data_array_SWR[25]), .A1(n1521), .B0(n1520), .B1(n1519), .Y(n1522) );
AOI22X1TS U1959 ( .A0(n961), .A1(n1522), .B0(n976), .B1(n980), .Y(n511) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_GDAN16M4P4_syn.sdf");
endmodule |
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule |
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148;
OAI21X2TS U46 ( .A0(n113), .A1(n112), .B0(n46), .Y(res[16]) );
NAND2XLTS U47 ( .A(n68), .B(n117), .Y(n119) );
NAND2XLTS U48 ( .A(n39), .B(n114), .Y(n116) );
NAND2X4TS U49 ( .A(n113), .B(n71), .Y(n46) );
CLKBUFX2TS U50 ( .A(n137), .Y(n33) );
OR2X2TS U51 ( .A(n78), .B(in1[14]), .Y(n39) );
OAI21X1TS U52 ( .A0(n76), .A1(in2[14]), .B0(add_sub), .Y(n74) );
INVX4TS U53 ( .A(n34), .Y(n48) );
NAND2X1TS U54 ( .A(n76), .B(add_sub), .Y(n77) );
CLKXOR2X2TS U55 ( .A(n80), .B(in2[13]), .Y(n81) );
NOR2XLTS U56 ( .A(n79), .B(n101), .Y(n80) );
NAND2XLTS U57 ( .A(n82), .B(add_sub), .Y(n83) );
NAND2BX2TS U58 ( .AN(in2[13]), .B(n79), .Y(n76) );
NOR2X2TS U59 ( .A(n82), .B(in2[12]), .Y(n79) );
NAND2X1TS U60 ( .A(n86), .B(add_sub), .Y(n87) );
NAND2X2TS U61 ( .A(in1[8]), .B(n70), .Y(n31) );
NAND2BX2TS U62 ( .AN(in2[9]), .B(n102), .Y(n86) );
NOR2X4TS U63 ( .A(n99), .B(in2[8]), .Y(n102) );
NAND2X1TS U64 ( .A(n99), .B(add_sub), .Y(n100) );
NAND2X4TS U65 ( .A(n127), .B(in1[6]), .Y(n97) );
NOR2X6TS U66 ( .A(n95), .B(in2[6]), .Y(n88) );
OR2X6TS U67 ( .A(n137), .B(in1[5]), .Y(n69) );
NAND2X4TS U68 ( .A(n95), .B(add_sub), .Y(n96) );
INVX3TS U69 ( .A(n67), .Y(n54) );
INVX6TS U70 ( .A(n133), .Y(n94) );
INVX8TS U71 ( .A(in2[3]), .Y(n62) );
INVX6TS U72 ( .A(in2[2]), .Y(n63) );
INVX6TS U73 ( .A(in2[1]), .Y(n64) );
INVX6TS U74 ( .A(in2[0]), .Y(n65) );
NOR2XLTS U75 ( .A(n102), .B(n101), .Y(n103) );
NAND2X1TS U76 ( .A(add_sub), .B(in2[0]), .Y(n130) );
OR2X4TS U77 ( .A(n92), .B(n101), .Y(n93) );
NOR2XLTS U78 ( .A(n84), .B(n101), .Y(n85) );
ADDHXLTS U79 ( .A(in2[0]), .B(in1[0]), .CO(n140), .S(res[0]) );
NAND2X4TS U80 ( .A(n50), .B(n48), .Y(n47) );
XNOR2X2TS U81 ( .A(n83), .B(in2[12]), .Y(n109) );
NAND2BX4TS U82 ( .AN(in2[11]), .B(n84), .Y(n82) );
XNOR2X2TS U83 ( .A(n87), .B(in2[10]), .Y(n111) );
NOR2X4TS U84 ( .A(n86), .B(in2[10]), .Y(n84) );
NOR2X4TS U85 ( .A(in2[4]), .B(in2[3]), .Y(n72) );
XOR2X1TS U86 ( .A(n116), .B(n115), .Y(res[14]) );
AND2X2TS U87 ( .A(n71), .B(n112), .Y(n38) );
OR2X4TS U88 ( .A(n75), .B(in1[15]), .Y(n71) );
NAND2X2TS U89 ( .A(n75), .B(in1[15]), .Y(n112) );
OR2X4TS U90 ( .A(n81), .B(in1[13]), .Y(n68) );
XOR2X1TS U91 ( .A(n129), .B(n128), .Y(res[6]) );
XOR2X1TS U92 ( .A(n139), .B(n138), .Y(res[5]) );
OAI21X1TS U93 ( .A0(n33), .A1(in1[5]), .B0(n126), .Y(n129) );
NAND2BX1TS U94 ( .AN(n132), .B(n131), .Y(n134) );
OAI211X1TS U95 ( .A0(in1[2]), .A1(n143), .B0(in1[1]), .C0(n141), .Y(n132) );
OAI21X1TS U96 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n124) );
NAND2X8TS U97 ( .A(n47), .B(n49), .Y(n113) );
NAND2X8TS U98 ( .A(n44), .B(n121), .Y(n70) );
XOR3X1TS U99 ( .A(n70), .B(in1[8]), .C(n120), .Y(res[8]) );
NAND2X2TS U100 ( .A(n120), .B(n70), .Y(n30) );
NAND2X2TS U101 ( .A(in1[8]), .B(n120), .Y(n32) );
NAND3X6TS U102 ( .A(n31), .B(n30), .C(n32), .Y(n105) );
XNOR2X4TS U103 ( .A(n100), .B(in2[8]), .Y(n120) );
NOR2X4TS U104 ( .A(n101), .B(in2[4]), .Y(n60) );
AND2X8TS U105 ( .A(n145), .B(in1[3]), .Y(n66) );
NAND2X8TS U106 ( .A(n90), .B(n73), .Y(n95) );
AND2X6TS U107 ( .A(n92), .B(n72), .Y(n90) );
NOR2X2TS U108 ( .A(n88), .B(n101), .Y(n89) );
XNOR2X2TS U109 ( .A(n74), .B(in2[15]), .Y(n75) );
NOR2X4TS U110 ( .A(n51), .B(n114), .Y(n50) );
NAND2BX4TS U111 ( .AN(in2[7]), .B(n88), .Y(n99) );
NAND2X2TS U112 ( .A(n101), .B(in2[4]), .Y(n59) );
NAND2X6TS U113 ( .A(n58), .B(in2[4]), .Y(n57) );
NAND2X4TS U114 ( .A(n61), .B(n60), .Y(n56) );
AO22XLTS U115 ( .A0(n148), .A1(in1[4]), .B0(n145), .B1(in1[3]), .Y(n125) );
INVX4TS U116 ( .A(n61), .Y(n58) );
XNOR2X2TS U117 ( .A(n77), .B(in2[14]), .Y(n78) );
INVX12TS U118 ( .A(add_sub), .Y(n101) );
NAND2X2TS U119 ( .A(n78), .B(in1[14]), .Y(n114) );
XOR2XLTS U120 ( .A(n148), .B(n147), .Y(res[4]) );
XNOR2X1TS U121 ( .A(n127), .B(in1[6]), .Y(n128) );
NAND2X1TS U122 ( .A(n35), .B(n121), .Y(n123) );
INVX2TS U123 ( .A(in1[9]), .Y(n43) );
XNOR2X1TS U124 ( .A(n33), .B(n136), .Y(n138) );
OR2X1TS U125 ( .A(n145), .B(in1[3]), .Y(n131) );
NOR2X2TS U126 ( .A(n34), .B(n51), .Y(n115) );
NOR2X4TS U127 ( .A(n101), .B(n90), .Y(n91) );
XNOR2X1TS U128 ( .A(n105), .B(n42), .Y(res[9]) );
AND2X8TS U129 ( .A(n118), .B(n68), .Y(n34) );
OR2X4TS U130 ( .A(in1[7]), .B(n98), .Y(n35) );
NAND2X2TS U131 ( .A(n81), .B(in1[13]), .Y(n117) );
OR2X4TS U132 ( .A(n127), .B(in1[6]), .Y(n36) );
NAND2X2TS U133 ( .A(n137), .B(in1[5]), .Y(n37) );
NAND2X2TS U134 ( .A(n98), .B(in1[7]), .Y(n121) );
XOR2X1TS U135 ( .A(n104), .B(n43), .Y(n42) );
CLKXOR2X2TS U136 ( .A(n103), .B(in2[9]), .Y(n104) );
AOI31X1TS U137 ( .A0(n143), .A1(in1[2]), .A2(n131), .B0(n125), .Y(n135) );
XNOR2X2TS U138 ( .A(n124), .B(in2[2]), .Y(n143) );
NAND2X8TS U139 ( .A(n40), .B(n37), .Y(n52) );
NAND2X8TS U140 ( .A(n69), .B(n53), .Y(n40) );
XOR2X2TS U141 ( .A(n113), .B(n38), .Y(res[15]) );
OAI2BB1X4TS U142 ( .A0N(in1[9]), .A1N(n105), .B0(n41), .Y(n110) );
OAI21X4TS U143 ( .A0(n105), .A1(in1[9]), .B0(n104), .Y(n41) );
NAND2X8TS U144 ( .A(n122), .B(n35), .Y(n44) );
XOR2X4TS U145 ( .A(n89), .B(in2[7]), .Y(n98) );
NAND2X8TS U146 ( .A(n45), .B(n97), .Y(n122) );
NAND2X8TS U147 ( .A(n52), .B(n36), .Y(n45) );
NOR3X8TS U148 ( .A(in2[1]), .B(in2[0]), .C(in2[2]), .Y(n92) );
NOR2X8TS U149 ( .A(n118), .B(n117), .Y(n51) );
OAI21X4TS U150 ( .A0(n34), .A1(n51), .B0(n39), .Y(n49) );
NAND2X8TS U151 ( .A(n55), .B(n54), .Y(n53) );
NAND2X8TS U152 ( .A(n66), .B(n94), .Y(n55) );
NAND3X8TS U153 ( .A(n57), .B(n56), .C(n59), .Y(n148) );
NOR2X8TS U154 ( .A(n148), .B(in1[4]), .Y(n133) );
NAND4X8TS U155 ( .A(n65), .B(n64), .C(n63), .D(n62), .Y(n61) );
XNOR2X1TS U156 ( .A(n119), .B(n118), .Y(res[13]) );
XNOR2X1TS U157 ( .A(n123), .B(n122), .Y(res[7]) );
XNOR2X4TS U158 ( .A(n93), .B(in2[3]), .Y(n145) );
XNOR2X4TS U159 ( .A(n96), .B(in2[6]), .Y(n127) );
AND2X4TS U160 ( .A(n148), .B(in1[4]), .Y(n67) );
INVX2TS U161 ( .A(in2[5]), .Y(n73) );
CLKXOR2X2TS U162 ( .A(n85), .B(in2[11]), .Y(n107) );
XOR2X4TS U163 ( .A(n91), .B(in2[5]), .Y(n137) );
ADDFHX4TS U164 ( .A(n107), .B(in1[11]), .CI(n106), .CO(n108), .S(res[11]) );
ADDFHX4TS U165 ( .A(n109), .B(in1[12]), .CI(n108), .CO(n118), .S(res[12]) );
ADDFHX4TS U166 ( .A(n111), .B(in1[10]), .CI(n110), .CO(n106), .S(res[10]) );
OAI2BB2XLTS U167 ( .B0(n135), .B1(n133), .A0N(n137), .A1N(in1[5]), .Y(n126)
);
XNOR2X1TS U168 ( .A(n130), .B(in2[1]), .Y(n141) );
AOI21X1TS U169 ( .A0(n135), .A1(n134), .B0(n133), .Y(n139) );
INVX2TS U170 ( .A(in1[5]), .Y(n136) );
CMPR32X2TS U171 ( .A(in1[1]), .B(n141), .C(n140), .CO(n142), .S(res[1]) );
CMPR32X2TS U172 ( .A(in1[2]), .B(n143), .C(n142), .CO(n144), .S(res[2]) );
CMPR32X2TS U173 ( .A(in1[3]), .B(n145), .C(n144), .CO(n146), .S(res[3]) );
XOR2X1TS U174 ( .A(in1[4]), .B(n146), .Y(n147) );
initial $sdf_annotate("Approx_adder_GeArN8R1P4_syn.sdf");
endmodule |
module i2s_audio (
input clk_i,
input [15:0] left_i,
input [15:0] right_i,
output reg [3:0] i2s_o,
output reg lrclk_o,
output sclk_o
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [5:0] bit_cntr = 0;
reg [3:0] i2s = 0;
reg [63:0] shift_reg = 64'd0;
reg delayed_out = 0;
// Synchronizer chain
reg [15:0] left_buffer[0:2];
reg [15:0] right_buffer[0:2];
// Assignments ================================================================================
assign sclk_o = clk_i;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Update output lines on negative edge because HDMI chip reads on posedge
always @(negedge clk_i)
begin
lrclk_o <= bit_cntr[5];
i2s_o[0] <= i2s[0];
i2s_o[1] <= i2s[1];
i2s_o[2] <= i2s[2];
i2s_o[3] <= i2s[3];
end
// Repeatedly counts 0-63 bits out
always @(posedge clk_i)
bit_cntr <= bit_cntr + 1'b1;
// Shift the bits out
always @(negedge clk_i)
begin
if( bit_cntr == 6'd63 )
{delayed_out, shift_reg} <= {shift_reg[63],left_buffer[0],16'd0,right_buffer[0],16'd0};
else
{delayed_out,shift_reg} <= {shift_reg,1'b0};
end
// Send MSB to output, note this delays the data by one clock as required for the LRCLK
always @(posedge clk_i)
begin
i2s[0] <= delayed_out;
i2s[1] <= delayed_out;
i2s[2] <= delayed_out;
i2s[3] <= delayed_out;
end
// Synchronizer for input
always @(posedge clk_i)
begin
{left_buffer[0],left_buffer[1],left_buffer[2]} <= {left_buffer[1],left_buffer[2],left_i};
{right_buffer[0],right_buffer[1],right_buffer[2]} <= {right_buffer[1],right_buffer[2],right_i};
end
// Other logic ================================================================================
endmodule |
module sky130_fd_sc_lp__or3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule |
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hdll__o2bb2a dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module omsp_dbg (
// OUTPUTs
dbg_freeze, // Freeze peripherals
dbg_halt_cmd, // Halt CPU command
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_reset, // Reset CPU from debug interface
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_uart_rxd, // Debug interface: UART RXD
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
eu_mdb_in, // Memory data bus input
eu_mdb_out, // Memory data bus output
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
fe_mdb_in, // Frontend Memory data bus input
mclk, // Main system clock
pc, // Program counter
por, // Power on reset
puc // Main system reset
);
// OUTPUTs
//=========
output dbg_freeze; // Freeze peripherals
output dbg_halt_cmd; // Halt CPU command
output [15:0] dbg_mem_addr; // Debug address for rd/wr access
output [15:0] dbg_mem_dout; // Debug unit data output
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_reset; // Reset CPU from debug interface
output dbg_uart_txd; // Debug interface: UART TXD
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_uart_rxd; // Debug interface: UART RXD
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] eu_mdb_in; // Memory data bus input
input [15:0] eu_mdb_out; // Memory data bus output
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
input puc; // Main system reset
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
// Diverse wires and registers
wire [5:0] dbg_addr;
wire [15:0] dbg_din;
wire dbg_wr;
reg mem_burst;
wire dbg_reg_rd;
wire dbg_mem_rd;
reg dbg_mem_rd_dly;
wire dbg_swbrk;
wire dbg_rd;
reg dbg_rd_rdy;
wire mem_burst_rd;
wire mem_burst_wr;
wire brk0_halt;
wire brk0_pnd;
wire [15:0] brk0_dout;
wire brk1_halt;
wire brk1_pnd;
wire [15:0] brk1_dout;
wire brk2_halt;
wire brk2_pnd;
wire [15:0] brk2_dout;
wire brk3_halt;
wire brk3_pnd;
wire [15:0] brk3_dout;
// Register addresses
parameter CPU_ID_LO = 6'h00;
parameter CPU_ID_HI = 6'h01;
parameter CPU_CTL = 6'h02;
parameter CPU_STAT = 6'h03;
parameter MEM_CTL = 6'h04;
parameter MEM_ADDR = 6'h05;
parameter MEM_DATA = 6'h06;
parameter MEM_CNT = 6'h07;
`ifdef DBG_HWBRK_0
parameter BRK0_CTL = 6'h08;
parameter BRK0_STAT = 6'h09;
parameter BRK0_ADDR0 = 6'h0A;
parameter BRK0_ADDR1 = 6'h0B;
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL = 6'h0C;
parameter BRK1_STAT = 6'h0D;
parameter BRK1_ADDR0 = 6'h0E;
parameter BRK1_ADDR1 = 6'h0F;
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL = 6'h10;
parameter BRK2_STAT = 6'h11;
parameter BRK2_ADDR0 = 6'h12;
parameter BRK2_ADDR1 = 6'h13;
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL = 6'h14;
parameter BRK3_STAT = 6'h15;
parameter BRK3_ADDR0 = 6'h16;
parameter BRK3_ADDR1 = 6'h17;
`endif
// Register one-hot decoder
parameter CPU_ID_LO_D = (64'h1 << CPU_ID_LO);
parameter CPU_ID_HI_D = (64'h1 << CPU_ID_HI);
parameter CPU_CTL_D = (64'h1 << CPU_CTL);
parameter CPU_STAT_D = (64'h1 << CPU_STAT);
parameter MEM_CTL_D = (64'h1 << MEM_CTL);
parameter MEM_ADDR_D = (64'h1 << MEM_ADDR);
parameter MEM_DATA_D = (64'h1 << MEM_DATA);
parameter MEM_CNT_D = (64'h1 << MEM_CNT);
`ifdef DBG_HWBRK_0
parameter BRK0_CTL_D = (64'h1 << BRK0_CTL);
parameter BRK0_STAT_D = (64'h1 << BRK0_STAT);
parameter BRK0_ADDR0_D = (64'h1 << BRK0_ADDR0);
parameter BRK0_ADDR1_D = (64'h1 << BRK0_ADDR1);
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL_D = (64'h1 << BRK1_CTL);
parameter BRK1_STAT_D = (64'h1 << BRK1_STAT);
parameter BRK1_ADDR0_D = (64'h1 << BRK1_ADDR0);
parameter BRK1_ADDR1_D = (64'h1 << BRK1_ADDR1);
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL_D = (64'h1 << BRK2_CTL);
parameter BRK2_STAT_D = (64'h1 << BRK2_STAT);
parameter BRK2_ADDR0_D = (64'h1 << BRK2_ADDR0);
parameter BRK2_ADDR1_D = (64'h1 << BRK2_ADDR1);
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL_D = (64'h1 << BRK3_CTL);
parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
`endif
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Select Data register during a burst
wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
// Register address decode
reg [63:0] reg_dec;
always @(dbg_addr_in)
case (dbg_addr_in)
CPU_ID_LO : reg_dec = CPU_ID_LO_D;
CPU_ID_HI : reg_dec = CPU_ID_HI_D;
CPU_CTL : reg_dec = CPU_CTL_D;
CPU_STAT : reg_dec = CPU_STAT_D;
MEM_CTL : reg_dec = MEM_CTL_D;
MEM_ADDR : reg_dec = MEM_ADDR_D;
MEM_DATA : reg_dec = MEM_DATA_D;
MEM_CNT : reg_dec = MEM_CNT_D;
`ifdef DBG_HWBRK_0
BRK0_CTL : reg_dec = BRK0_CTL_D;
BRK0_STAT : reg_dec = BRK0_STAT_D;
BRK0_ADDR0: reg_dec = BRK0_ADDR0_D;
BRK0_ADDR1: reg_dec = BRK0_ADDR1_D;
`endif
`ifdef DBG_HWBRK_1
BRK1_CTL : reg_dec = BRK1_CTL_D;
BRK1_STAT : reg_dec = BRK1_STAT_D;
BRK1_ADDR0: reg_dec = BRK1_ADDR0_D;
BRK1_ADDR1: reg_dec = BRK1_ADDR1_D;
`endif
`ifdef DBG_HWBRK_2
BRK2_CTL : reg_dec = BRK2_CTL_D;
BRK2_STAT : reg_dec = BRK2_STAT_D;
BRK2_ADDR0: reg_dec = BRK2_ADDR0_D;
BRK2_ADDR1: reg_dec = BRK2_ADDR1_D;
`endif
`ifdef DBG_HWBRK_3
BRK3_CTL : reg_dec = BRK3_CTL_D;
BRK3_STAT : reg_dec = BRK3_STAT_D;
BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
`endif
default: reg_dec = {64{1'b0}};
endcase
// Read/Write probes
wire reg_write = dbg_wr;
wire reg_read = 1'b1;
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {64{reg_write}};
wire [511:0] reg_rd = reg_dec & {64{reg_read}};
//=============================================================================
// 3) REGISTER: CORE INTERFACE
//=============================================================================
// CPU_ID Register
//-----------------
wire [3:0] cpu_id_pmem = `PMEM_AWIDTH;
wire [3:0] cpu_id_dmem = `DMEM_AWIDTH;
wire [31:0] cpu_id = {`DBG_ID, cpu_id_pmem, cpu_id_dmem};
// CPU_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
//-----------------------------------------------------------------------------
reg [6:3] cpu_ctl;
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge mclk or posedge por)
if (por) cpu_ctl <= 4'h0;
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st;
wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st;
wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st;
// CPU_STAT Register
//------------------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
//------------------------------------------------------------------------------------
reg [3:2] cpu_stat;
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
always @ (posedge mclk or posedge por)
if (por) cpu_stat <= 2'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
cpu_stat, 1'b0, dbg_halt_st};
//=============================================================================
// 4) REGISTER: MEMORY INTERFACE
//=============================================================================
// MEM_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved B/W MEM/REG RD/WR START
//
// START : - 0 : Do nothing.
// - 1 : Initiate memory transfer.
//
// RD/WR : - 0 : Read access.
// - 1 : Write access.
//
// MEM/REG: - 0 : Memory access.
// - 1 : CPU Register access.
//
// B/W : - 0 : 16 bit access.
// - 1 : 8 bit access (not valid for CPU Registers).
//
//-----------------------------------------------------------------------------
reg [3:1] mem_ctl;
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge mclk or posedge por)
if (por) mem_ctl <= 3'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
reg mem_start;
always @ (posedge mclk or posedge por)
if (por) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
wire mem_bw = mem_ctl[3];
// MEM_DATA Register
//------------------
reg [15:0] mem_data;
reg [15:0] mem_addr;
wire mem_access;
wire mem_data_wr = reg_wr[MEM_DATA];
wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din :
mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
{8'h00, dbg_mem_din[7:0]};
always @ (posedge mclk or posedge por)
if (por) mem_data <= 16'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
// MEM_ADDR Register
//------------------
reg [15:0] mem_cnt;
wire mem_addr_wr = reg_wr[MEM_ADDR];
wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
(dbg_mem_acc & ~mem_bw) ? 16'h0002 :
(dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_addr <= 16'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
// MEM_CNT Register
//------------------
wire mem_cnt_wr = reg_wr[MEM_CNT];
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
(dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_cnt <= 16'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
//=============================================================================
// 5) BREAKPOINTS / WATCHPOINTS
//=============================================================================
`ifdef DBG_HWBRK_0
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
reg_rd[BRK0_ADDR0],
reg_rd[BRK0_STAT],
reg_rd[BRK0_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
reg_wr[BRK0_ADDR0],
reg_wr[BRK0_STAT],
reg_wr[BRK0_CTL]};
omsp_dbg_hwbrk dbg_hwbr_0 (
// OUTPUTs
.brk_halt (brk0_halt), // Hardware breakpoint command
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending
.brk_dout (brk0_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk0_halt = 1'b0;
assign brk0_pnd = 1'b0;
assign brk0_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_1
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
reg_rd[BRK1_ADDR0],
reg_rd[BRK1_STAT],
reg_rd[BRK1_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
reg_wr[BRK1_ADDR0],
reg_wr[BRK1_STAT],
reg_wr[BRK1_CTL]};
omsp_dbg_hwbrk dbg_hwbr_1 (
// OUTPUTs
.brk_halt (brk1_halt), // Hardware breakpoint command
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending
.brk_dout (brk1_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk1_halt = 1'b0;
assign brk1_pnd = 1'b0;
assign brk1_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_2
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
reg_rd[BRK2_ADDR0],
reg_rd[BRK2_STAT],
reg_rd[BRK2_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
reg_wr[BRK2_ADDR0],
reg_wr[BRK2_STAT],
reg_wr[BRK2_CTL]};
omsp_dbg_hwbrk dbg_hwbr_2 (
// OUTPUTs
.brk_halt (brk2_halt), // Hardware breakpoint command
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending
.brk_dout (brk2_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk2_halt = 1'b0;
assign brk2_pnd = 1'b0;
assign brk2_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_3
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
reg_rd[BRK3_ADDR0],
reg_rd[BRK3_STAT],
reg_rd[BRK3_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
reg_wr[BRK3_ADDR0],
reg_wr[BRK3_STAT],
reg_wr[BRK3_CTL]};
omsp_dbg_hwbrk dbg_hwbr_3 (
// OUTPUTs
.brk_halt (brk3_halt), // Hardware breakpoint command
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending
.brk_dout (brk3_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk3_halt = 1'b0;
assign brk3_pnd = 1'b0;
assign brk3_dout = 16'h0000;
`endif
//============================================================================
// 6) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}};
wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
wire [15:0] dbg_dout = cpu_id_lo_rd |
cpu_id_hi_rd |
cpu_ctl_rd |
cpu_stat_rd |
mem_ctl_rd |
mem_data_rd |
mem_addr_rd |
mem_cnt_rd |
brk0_dout |
brk1_dout |
brk2_dout |
brk3_dout;
// Tell UART/JTAG interface that the data is ready to be read
always @ (posedge mclk or posedge por)
if (por) dbg_rd_rdy <= 1'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
//============================================================================
// 7) CPU CONTROL
//============================================================================
// Reset CPU
//--------------------------
wire dbg_reset = cpu_ctl[`CPU_RST];
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge mclk or posedge por)
if (por) inc_step <= 2'b00;
else if (istep) inc_step <= 2'b11;
else inc_step <= {inc_step[0], 1'b0};
// Run / Halt
//--------------------------
reg halt_flag;
wire mem_halt_cpu;
wire mem_run_cpu;
wire halt_flag_clr = run_cpu | mem_run_cpu;
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
always @(posedge mclk or posedge por)
if (por) halt_flag <= 1'b0;
else if (halt_flag_clr) halt_flag <= 1'b0;
else if (halt_flag_set) halt_flag <= 1'b1;
wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
//============================================================================
// 8) MEMORY CONTROL
//============================================================================
// Control Memory bursts
//------------------------------
wire mem_burst_start = (mem_start & |mem_cnt);
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
// Detect when burst is on going
always @(posedge mclk or posedge por)
if (por) mem_burst <= 1'b0;
else if (mem_burst_start) mem_burst <= 1'b1;
else if (mem_burst_end) mem_burst <= 1'b0;
// Control signals for UART/JTAG interface
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge mclk or posedge por)
if (por) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
// Memory access state machine
//------------------------------
reg [1:0] mem_state;
reg [1:0] mem_state_nxt;
// State machine definition
parameter M_IDLE = 2'h0;
parameter M_SET_BRK = 2'h1;
parameter M_ACCESS_BRK = 2'h2;
parameter M_ACCESS = 2'h3;
// State transition
always @(mem_state or mem_seq_start or dbg_halt_st)
case (mem_state)
M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
dbg_halt_st ? M_ACCESS : M_SET_BRK;
M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
M_ACCESS_BRK : mem_state_nxt = M_IDLE;
M_ACCESS : mem_state_nxt = M_IDLE;
default : mem_state_nxt = M_IDLE;
endcase
// State machine
always @(posedge mclk or posedge por)
if (por) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK);
// Interface to CPU Registers and Memory bacbkone
//------------------------------------------------
assign dbg_mem_addr = mem_addr;
assign dbg_mem_dout = ~mem_bw ? mem_data :
mem_addr[0] ? {mem_data[7:0], 8'h00} :
{8'h00, mem_data[7:0]};
assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2];
assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2];
assign dbg_mem_en = mem_access & ~mem_ctl[2];
assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1];
wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 :
mem_addr[0] ? 2'b10 : 2'b01;
assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
// It takes one additional cycle to read from Memory as from registers
always @(posedge mclk or posedge por)
if (por) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
//=============================================================================
// 9) UART COMMUNICATION
//=============================================================================
`ifdef DBG_UART
omsp_dbg_uart dbg_uart_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_rd (dbg_rd), // Debug register data read
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mclk (mclk), // Main system clock
.mem_burst (mem_burst), // Burst on going
.mem_burst_end(mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw), // Burst byte width
.por (por) // Power on reset
);
`else
assign dbg_addr = 6'h00;
assign dbg_din = 16'h0000;
assign dbg_rd = 1'b0;
assign dbg_uart_txd = 1'b0;
assign dbg_wr = 1'b0;
`endif
//=============================================================================
// 10) JTAG COMMUNICATION
//=============================================================================
`ifdef DBG_JTAG
JTAG INTERFACE IS NOT SUPPORTED YET
`else
`endif
endmodule |
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bist artisan_ssp(
`else
art_hssp_2048x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x32_bist vs_ssp(
`else
vs_hdsp_2048x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
.WE(we),
.DO(doq[9:8])
);
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
.WE(we),
.DO(doq[11:10])
);
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
.WE(we),
.DO(doq[13:12])
);
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
.WE(we),
.DO(doq[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
.WE(we),
.DO(doq[17:16])
);
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
.WE(we),
.DO(doq[19:18])
);
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
.WE(we),
.DO(doq[21:20])
);
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
.WE(we),
.DO(doq[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
.WE(we),
.DO(doq[25:24])
);
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
.WE(we),
.DO(doq[27:26])
);
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
.WE(we),
.DO(doq[29:28])
);
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
.WE(we),
.DO(doq[31:30])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[7:0]),
.DOP()
);
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[15:8]),
.DOP()
);
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[23:16]),
.DOP()
);
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[31:24]),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule |
module lname_mbus_master_node_ctrl (
//Input
input CLK_EXT,
input RESETn,
input CIN,
input DIN,
input [`MBUS_BITS_WD_WIDTH-1:0] NUM_BITS_THRESHOLD,
input [`MBUS_IDLE_WD_WIDTH-1:0] WATCHDOG_THRESHOLD,
input WATCHDOG_RESET,
input WATCHDOG_RESET_REQ,
output reg WATCHDOG_RESET_ACK,
//Output
output COUT,
output reg DOUT,
//MBus Watchdog
input [`MBUS_ADDR_WIDTH-1:0] TX_ADDR_IN,
input [`MBUS_DATA_WIDTH-1:0] TX_DATA_IN,
input TX_PRIORITY_IN,
input TX_ACK_IN,
input TX_SUCC_IN,
input TX_FAIL_IN,
input TX_REQ_IN,
input TX_PEND_IN,
input TX_RESP_ACK_IN,
output [`MBUS_ADDR_WIDTH-1:0] TX_ADDR_OUT,
output [`MBUS_DATA_WIDTH-1:0] TX_DATA_OUT,
output TX_PRIORITY_OUT,
output TX_ACK_OUT,
output TX_SUCC_OUT,
output TX_FAIL_OUT,
output TX_REQ_OUT,
output TX_PEND_OUT,
output TX_RESP_ACK_OUT,
// FSM Configuration
input FORCE_IDLE_WHEN_DONE,
// MBus Msg Interrupted Flag
input MBC_IN_FWD,
input GOCEP_ACTIVE,
input CLEAR_FLAG,
output reg MSG_INTERRUPTED
);
`include "include/lname_mbus_func.v"
parameter BUS_IDLE = 0;
parameter BUS_WAIT_START = 3;
parameter BUS_START = 4;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ACTIVE = 5;
parameter BUS_INTERRUPT = 7;
parameter BUS_SWITCH_ROLE = 6;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
parameter START_CYCLES = 10;
parameter GUARD_BAND_NUM_CYCLES = 20;
parameter BUS_INTERRUPT_COUNTER = 6;
reg [log2(START_CYCLES-1)-1:0] start_cycle_cnt, next_start_cycle_cnt;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg [log2(BUS_INTERRUPT_COUNTER-1)-1:0] bus_interrupt_cnt, next_bus_interrupt_cnt;
reg clk_en, next_clk_en;
reg clkin_sampled;
reg [2:0] din_sampled_neg, din_sampled_pos;
reg [`MBUS_BITS_WD_WIDTH-1:0] num_bits_threshold_cnt, next_num_bits_threshold_cnt;
reg din_dly_1, din_dly_2;
// DIN double-latch
always @(posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_dly_1 <= `SD 1'b1;
din_dly_2 <= `SD 1'b1;
end
else if (FORCE_IDLE_WHEN_DONE) begin
if ((bus_state == BUS_IDLE) | (bus_state == BUS_WAIT_START)) begin
din_dly_1 <= `SD DIN;
din_dly_2 <= `SD din_dly_1;
end
else begin
din_dly_1 <= `SD 1'b1;
din_dly_2 <= `SD 1'b1;
end
end
else begin
din_dly_1 <= `SD DIN;
din_dly_2 <= `SD din_dly_1;
end
end
wire [1:0] CONTROL_BITS = `MBUS_CONTROL_SEQ; // EOM?, ~ACK?
//---------------------- Watch-Dog Implementation ----------------------------------//
reg WATCHDOG_RESET_REQ_DL1, WATCHDOG_RESET_REQ_DL2;
reg next_watchdog_reset_ack;
reg WATCHDOG_RESET_DL1, WATCHDOG_RESET_DL2;
reg [`MBUS_IDLE_WD_WIDTH-1:0] watchdog_cnt, next_watchdog_cnt;
reg watchdog_tx_req, next_watchdog_tx_req;
reg watchdog_tx_resp_ack, next_watchdog_tx_resp_ack;
reg watchdog_expired, next_watchdog_expired;
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
watchdog_cnt <= `SD 0;
watchdog_tx_req <= `SD 0;
watchdog_tx_resp_ack <= `SD 0;
watchdog_expired <= `SD 0;
WATCHDOG_RESET_ACK <= `SD 0;
WATCHDOG_RESET_REQ_DL1 <= `SD 0;
WATCHDOG_RESET_REQ_DL2 <= `SD 0;
WATCHDOG_RESET_DL1 <= `SD 0;
WATCHDOG_RESET_DL2 <= `SD 0;
end
else begin
watchdog_cnt <= `SD next_watchdog_cnt;
watchdog_tx_req <= `SD next_watchdog_tx_req;
watchdog_tx_resp_ack <= `SD next_watchdog_tx_resp_ack;
watchdog_expired <= `SD next_watchdog_expired;
WATCHDOG_RESET_ACK <= `SD next_watchdog_reset_ack;
WATCHDOG_RESET_REQ_DL1 <= `SD WATCHDOG_RESET_REQ;
WATCHDOG_RESET_REQ_DL2 <= `SD WATCHDOG_RESET_REQ_DL1;
WATCHDOG_RESET_DL1 <= `SD WATCHDOG_RESET;
WATCHDOG_RESET_DL2 <= `SD WATCHDOG_RESET_DL1;
end
end
always @* begin
next_watchdog_cnt = watchdog_cnt;
next_watchdog_tx_req = watchdog_tx_req;
next_watchdog_tx_resp_ack = watchdog_tx_resp_ack;
next_watchdog_expired = watchdog_expired;
next_watchdog_reset_ack = WATCHDOG_RESET_ACK;
if (watchdog_expired) begin
if (watchdog_tx_req) begin
if (TX_ACK_IN)
next_watchdog_tx_req = 0;
if (TX_FAIL_IN & (~watchdog_tx_resp_ack))
next_watchdog_tx_req = 0;
end
if (TX_SUCC_IN | TX_FAIL_IN)
next_watchdog_tx_resp_ack = 1;
if ((~(TX_SUCC_IN | TX_FAIL_IN)) & watchdog_tx_resp_ack)
next_watchdog_tx_resp_ack = 0;
end
if (WATCHDOG_RESET_REQ_DL2 & (~WATCHDOG_RESET_ACK)) next_watchdog_reset_ack = 1;
if ((~WATCHDOG_RESET_REQ_DL2) & WATCHDOG_RESET_ACK) next_watchdog_reset_ack = 0;
if (WATCHDOG_RESET_REQ_DL2 & (~WATCHDOG_RESET_ACK)) // Reset requested by CPU
next_watchdog_cnt = 0;
else if (WATCHDOG_RESET_DL2) // Pause Watchdog
next_watchdog_cnt = 0;
else if ((bus_state != BUS_IDLE) | (bus_state != BUS_IDLE)) // Reset due to non-idle state
next_watchdog_cnt = 0;
else
next_watchdog_cnt = watchdog_cnt + 1'b1;
if ((bus_state == BUS_IDLE) & (next_bus_state == BUS_IDLE)) begin
if ((WATCHDOG_THRESHOLD != 0) & (watchdog_cnt == WATCHDOG_THRESHOLD)) begin
if (~watchdog_expired) next_watchdog_tx_req = 1;
next_watchdog_expired = 1;
end
end
end
// Watch-Dog: Layer Ctrl --> MBus Node
assign TX_REQ_OUT = (watchdog_expired) ? watchdog_tx_req : TX_REQ_IN;
assign TX_PEND_OUT = (watchdog_expired) ? 1'b0 : TX_PEND_IN;
assign TX_ADDR_OUT = (watchdog_expired) ? 32'h0000_0001 : TX_ADDR_IN; // All Selective Sleep msg if watchdog expires
assign TX_DATA_OUT = (watchdog_expired) ? 32'h2FFF_F000 : TX_DATA_IN; // All Selective Sleep msg if watchdog expires
assign TX_RESP_ACK_OUT = (watchdog_expired) ? watchdog_tx_resp_ack : TX_RESP_ACK_IN;
assign TX_PRIORITY_OUT = (watchdog_expired) ? 1'b0 : TX_PRIORITY_IN;
// Watch-Dog: MBus Node --> Layer Ctrl
assign TX_ACK_OUT = (watchdog_expired) ? 1'b0 : TX_ACK_IN;
assign TX_FAIL_OUT = (watchdog_expired) ? 1'b0 : TX_FAIL_IN;
assign TX_SUCC_OUT = (watchdog_expired) ? 1'b0 : TX_SUCC_IN;
//--------------- End of Watch-Dog Implementation ----------------------------------//
//--------------- Start of MBus Message Interrupted Flag ---------------//
reg gocep_active_dl1, gocep_active_dl2;
reg tx_req_in_dl1, tx_req_in_dl2;
reg [4:0] guard_band_cnt, next_guard_band_cnt;
reg very_first_msg, next_very_first_msg;
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
gocep_active_dl1 <= `SD 0;
gocep_active_dl2 <= `SD 0;
tx_req_in_dl1 <= `SD 0;
tx_req_in_dl2 <= `SD 0;
guard_band_cnt <= `SD 0;
very_first_msg <= `SD 1;
end
else begin
gocep_active_dl1 <= `SD GOCEP_ACTIVE;
gocep_active_dl2 <= `SD gocep_active_dl1;
tx_req_in_dl1 <= `SD TX_REQ_IN;
tx_req_in_dl2 <= `SD tx_req_in_dl1;
guard_band_cnt <= `SD next_guard_band_cnt;
very_first_msg <= `SD next_very_first_msg;
end
end
always @* begin
next_guard_band_cnt = guard_band_cnt;
if ((bus_state != BUS_IDLE) & (next_bus_state == BUS_IDLE))
next_guard_band_cnt = GUARD_BAND_NUM_CYCLES;
else if (guard_band_cnt > 0) next_guard_band_cnt = guard_band_cnt - 1;
end
always @* begin
next_very_first_msg = very_first_msg;
if ((guard_band_cnt > 0) & (next_guard_band_cnt == 0))
next_very_first_msg = 0;
end
wire RESETn_FLAG = RESETn & ~CLEAR_FLAG;
// MSG_INTERRUPTED is set when GOC becomes activated while there is an on-going MBus message only if:
// - The MBus message is NOT the first message (usually this is a wake-up message)
// - The MBus message is either Tx or Rx for PRC/PRE
// If it is a forwarding message, the flag is not set.
// However, since the 'forward' message cannot be identified until it
// receives the whole MBus ADDR section, it is possible that the
// flag becomes set even if the MBus message is a forwarding message.
// This could happen if GOC becomes activated while PRC/PRE is receiving
// the ADDR section of the forwarding message.
// - The MBus message finishes, but the Guard Band counter (guard_band_cnt) is not zero.
// This is to provide some margin to cover the last RX_REQ/RX_ACK in
// a long MBus message.
// - There is an un-cleared TX_REQ
always @ (posedge CLK_EXT or negedge RESETn_FLAG) begin
if (~RESETn_FLAG) MSG_INTERRUPTED <= `SD 0;
else if (gocep_active_dl1 & ~gocep_active_dl2) begin
if (~very_first_msg & ~MBC_IN_FWD) begin
if ((bus_state != BUS_IDLE) | (guard_band_cnt > 0)) MSG_INTERRUPTED <= `SD 1;
end
else if (tx_req_in_dl2 & ~TX_ACK_IN) MSG_INTERRUPTED <= `SD 1;
end
end
//--------------- End of MBus Message Interrupted Flag ---------------//
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
bus_state <= `SD BUS_IDLE;
start_cycle_cnt <= `SD START_CYCLES - 1'b1;
clk_en <= `SD 0;
bus_interrupt_cnt <= `SD BUS_INTERRUPT_COUNTER - 1'b1;
num_bits_threshold_cnt <= `SD 0;
end
else begin
bus_state <= `SD next_bus_state;
start_cycle_cnt <= `SD next_start_cycle_cnt;
clk_en <= `SD next_clk_en;
bus_interrupt_cnt <= `SD next_bus_interrupt_cnt;
num_bits_threshold_cnt <= `SD next_num_bits_threshold_cnt;
end
end
always @* begin
next_bus_state = bus_state;
next_start_cycle_cnt = start_cycle_cnt;
next_clk_en = clk_en;
next_bus_interrupt_cnt = bus_interrupt_cnt;
next_num_bits_threshold_cnt = num_bits_threshold_cnt;
case (bus_state)
BUS_IDLE: begin
if (FORCE_IDLE_WHEN_DONE) begin
if (~din_dly_2) begin
next_bus_state = BUS_WAIT_START;
if (watchdog_cnt < 4) next_start_cycle_cnt = 0;
else next_start_cycle_cnt = START_CYCLES - 1'b1;
end
end
else begin
if (~din_dly_2) next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = START_CYCLES - 1'b1;
end
end
BUS_WAIT_START: begin
next_num_bits_threshold_cnt = 0;
if (start_cycle_cnt) next_start_cycle_cnt = start_cycle_cnt - 1'b1;
else begin
if (~din_dly_2) begin
next_clk_en = 1;
next_bus_state = BUS_START;
end
else next_bus_state = BUS_IDLE;
end
end
BUS_START: next_bus_state = BUS_ARBITRATE;
BUS_ARBITRATE: begin
next_bus_state = BUS_PRIO;
if (DIN) next_num_bits_threshold_cnt = NUM_BITS_THRESHOLD; // Glitch, reset bus immediately
end
BUS_PRIO: next_bus_state = BUS_ACTIVE;
BUS_ACTIVE: begin
if ((num_bits_threshold_cnt<NUM_BITS_THRESHOLD)&&(~clkin_sampled))
next_num_bits_threshold_cnt = num_bits_threshold_cnt + 1'b1;
else begin
next_clk_en = 0;
next_bus_state = BUS_INTERRUPT;
end
next_bus_interrupt_cnt = BUS_INTERRUPT_COUNTER - 1'b1;
end
BUS_INTERRUPT: begin
if (bus_interrupt_cnt) next_bus_interrupt_cnt = bus_interrupt_cnt - 1'b1;
else begin
if ({din_sampled_neg, din_sampled_pos}==6'b111_000) begin
next_bus_state = BUS_SWITCH_ROLE;
next_clk_en = 1;
end
end
end
BUS_SWITCH_ROLE: next_bus_state = BUS_CONTROL0;
BUS_CONTROL0: next_bus_state = BUS_CONTROL1;
BUS_CONTROL1: next_bus_state = BUS_BACK_TO_IDLE;
BUS_BACK_TO_IDLE: begin
if (FORCE_IDLE_WHEN_DONE) begin
next_bus_state = BUS_IDLE;
next_clk_en = 0;
end
else begin
if (~DIN) begin
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = 1;
end
else begin
next_bus_state = BUS_IDLE;
end
next_clk_en = 0;
end
end
endcase
end
always @ (negedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_neg <= `SD 0;
bus_state_neg <= `SD BUS_IDLE;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_neg <= `SD {din_sampled_neg[1:0], DIN};
bus_state_neg <= `SD bus_state;
end
end
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_pos <= `SD 0;
clkin_sampled <= `SD 0;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_pos <= `SD {din_sampled_pos[1:0], DIN};
clkin_sampled <= `SD CIN;
end
end
assign COUT = (clk_en)? CLK_EXT : 1'b1;
always @* begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE: DOUT = 1;
BUS_WAIT_START: DOUT = 1;
BUS_START: DOUT = 1;
BUS_INTERRUPT: DOUT = CLK_EXT;
BUS_SWITCH_ROLE: DOUT = 1;
BUS_CONTROL0: if (num_bits_threshold_cnt==NUM_BITS_THRESHOLD) DOUT = (~CONTROL_BITS[1]);
BUS_BACK_TO_IDLE: DOUT = 1;
endcase
end
endmodule |
module sky130_fd_sc_hs__dlrtn_2 (
RESET_B,
D ,
GATE_N ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__dlrtn_2 (
RESET_B,
D ,
GATE_N ,
Q
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q)
);
endmodule |
module bsg_inv #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
, parameter vertical_p=1
)
(input [width_p-1:0] i
, output [width_p-1:0] o
);
`bsg_inv_macro(85) else
`bsg_inv_macro(84) else
`bsg_inv_macro(83) else
`bsg_inv_macro(82) else
`bsg_inv_macro(81) else
`bsg_inv_macro(80) else
`bsg_inv_macro(79) else
`bsg_inv_macro(78) else
`bsg_inv_macro(77) else
`bsg_inv_macro(76) else
`bsg_inv_macro(75) else
`bsg_inv_macro(74) else
`bsg_inv_macro(73) else
`bsg_inv_macro(72) else
`bsg_inv_macro(71) else
`bsg_inv_macro(70) else
`bsg_inv_macro(69) else
`bsg_inv_macro(68) else
`bsg_inv_macro(67) else
`bsg_inv_macro(66) else
`bsg_inv_macro(65) else
`bsg_inv_macro(64) else
`bsg_inv_macro(63) else
`bsg_inv_macro(62) else
`bsg_inv_macro(61) else
`bsg_inv_macro(60) else
`bsg_inv_macro(59) else
`bsg_inv_macro(58) else
`bsg_inv_macro(57) else
`bsg_inv_macro(56) else
`bsg_inv_macro(55) else
`bsg_inv_macro(54) else
`bsg_inv_macro(53) else
`bsg_inv_macro(52) else
`bsg_inv_macro(51) else
`bsg_inv_macro(50) else
`bsg_inv_macro(49) else
`bsg_inv_macro(48) else
`bsg_inv_macro(47) else
`bsg_inv_macro(46) else
`bsg_inv_macro(45) else
`bsg_inv_macro(44) else
`bsg_inv_macro(43) else
`bsg_inv_macro(42) else
`bsg_inv_macro(41) else
`bsg_inv_macro(40) else
`bsg_inv_macro(39) else
`bsg_inv_macro(38) else
`bsg_inv_macro(37) else
`bsg_inv_macro(36) else
`bsg_inv_macro(35) else
`bsg_inv_macro(34) else
`bsg_inv_macro(33) else
`bsg_inv_macro(32) else
`bsg_inv_macro(31) else
`bsg_inv_macro(30) else
`bsg_inv_macro(29) else
`bsg_inv_macro(28) else
`bsg_inv_macro(27) else
`bsg_inv_macro(26) else
`bsg_inv_macro(25) else
`bsg_inv_macro(24) else
`bsg_inv_macro(23) else
`bsg_inv_macro(22) else
`bsg_inv_macro(21) else
`bsg_inv_macro(20) else
`bsg_inv_macro(19) else
`bsg_inv_macro(18) else
`bsg_inv_macro(17) else
`bsg_inv_macro(16) else
`bsg_inv_macro(15) else
`bsg_inv_macro(14) else
`bsg_inv_macro(13) else
`bsg_inv_macro(12) else
`bsg_inv_macro(11) else
`bsg_inv_macro(10) else
`bsg_inv_macro(9) else
`bsg_inv_macro(8) else
`bsg_inv_macro(7) else
`bsg_inv_macro(6) else
`bsg_inv_macro(5) else
`bsg_inv_macro(4) else
`bsg_inv_macro(3) else
`bsg_inv_macro(2) else
`bsg_inv_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = i;
end
endmodule |
module sky130_fd_sc_lp__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule |
module gen_pipe_1
#(
parameter PIPE_WIDTH = 9'd32,
PIPE_DEPTH = 5'd4
)
(
input clk,
input [PIPE_WIDTH -1 :0] din,
output [PIPE_WIDTH -1 :0] dout_1,
output [PIPE_WIDTH -1 :0] dout
);
reg [PIPE_WIDTH - 1:0] pipe_reg [PIPE_DEPTH - 1:0];
reg [9:0] n;
always @(posedge clk) begin
for(n=(PIPE_DEPTH[9:0] - 10'h1); n!=10'h0; n=n-10'h1)
pipe_reg[n] <= pipe_reg[n-1];
pipe_reg[0] <= din;;
end
assign dout = pipe_reg[PIPE_DEPTH - 1];
assign dout_1 = pipe_reg[PIPE_DEPTH - 2];
endmodule |
module top(
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [8:0] LEDG,
output [17:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
inout [35:0] GPIO
);
wire wClock;
clock clock0(
.iStateClock(KEY[1]),
.iState(SW[9:8]),
.iMaxClock(CLOCK_50),
.iManualClock(KEY[0]),
.iLimit(SW[7:0]),
.oClock(wClock)
);
wire [2:0] wcounter;
wire [31:0] wIP;
wire [31:0] wA;
wire [31:0] wB;
wire [31:0] wJ;
wire [31:0] wq;
wire [31:0] wsub;
wire wleq;
subleq cpu(
.iClock(wClock),
.iReset(~KEY[3]),
.ocounter(wcounter),
.oIP(wIP),
.oA(wA),
.oB(wB),
.oJ(wJ),
.oq(wq),
.osub(wsub),
.oleq(wleq)
);
wire [31:0] decoder7_num;
always @(SW[15:13], wcounter, wIP, wA, wB, wJ, wq, wsub, wleq) begin
case (SW[15:13])
3'd0: decoder7_num <= {29'b0, wcounter};
3'd1: decoder7_num <= wIP;
3'd2: decoder7_num <= wA;
3'd3: decoder7_num <= wB;
3'd4: decoder7_num <= wJ;
3'd5: decoder7_num <= wq;
3'd6: decoder7_num <= wsub;
3'd7: decoder7_num <= {31'b0, wleq};
endcase
end
decoder7 dec0(.in(decoder7_num[3:0]), .out(HEX0));
decoder7 dec1(.in(decoder7_num[7:4]), .out(HEX1));
decoder7 dec2(.in(decoder7_num[11:8]), .out(HEX2));
decoder7 dec3(.in(decoder7_num[15:12]), .out(HEX3));
decoder7 dec4(.in(decoder7_num[19:16]), .out(HEX4));
decoder7 dec5(.in(decoder7_num[23:20]), .out(HEX5));
decoder7 dec6(.in(decoder7_num[27:24]), .out(HEX6));
decoder7 dec7(.in(decoder7_num[31:28]), .out(HEX7));
assign GPIO[0] = (wcounter == 3'd0);
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module soc_system (
input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
input wire clk_clk, // clk.clk
output wire [7:0] custom_leds_0_leds_leds, // custom_leds_0_leds.leds
input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire reset_reset_n // reset.reset_n
);
wire [1:0] hps_0_h2f_axi_master_awburst; // hps_0:h2f_AWBURST -> mm_interconnect_0:hps_0_h2f_axi_master_awburst
wire [3:0] hps_0_h2f_axi_master_arlen; // hps_0:h2f_ARLEN -> mm_interconnect_0:hps_0_h2f_axi_master_arlen
wire [7:0] hps_0_h2f_axi_master_wstrb; // hps_0:h2f_WSTRB -> mm_interconnect_0:hps_0_h2f_axi_master_wstrb
wire hps_0_h2f_axi_master_wready; // mm_interconnect_0:hps_0_h2f_axi_master_wready -> hps_0:h2f_WREADY
wire [11:0] hps_0_h2f_axi_master_rid; // mm_interconnect_0:hps_0_h2f_axi_master_rid -> hps_0:h2f_RID
wire hps_0_h2f_axi_master_rready; // hps_0:h2f_RREADY -> mm_interconnect_0:hps_0_h2f_axi_master_rready
wire [3:0] hps_0_h2f_axi_master_awlen; // hps_0:h2f_AWLEN -> mm_interconnect_0:hps_0_h2f_axi_master_awlen
wire [11:0] hps_0_h2f_axi_master_wid; // hps_0:h2f_WID -> mm_interconnect_0:hps_0_h2f_axi_master_wid
wire [3:0] hps_0_h2f_axi_master_arcache; // hps_0:h2f_ARCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_arcache
wire hps_0_h2f_axi_master_wvalid; // hps_0:h2f_WVALID -> mm_interconnect_0:hps_0_h2f_axi_master_wvalid
wire [29:0] hps_0_h2f_axi_master_araddr; // hps_0:h2f_ARADDR -> mm_interconnect_0:hps_0_h2f_axi_master_araddr
wire [2:0] hps_0_h2f_axi_master_arprot; // hps_0:h2f_ARPROT -> mm_interconnect_0:hps_0_h2f_axi_master_arprot
wire [2:0] hps_0_h2f_axi_master_awprot; // hps_0:h2f_AWPROT -> mm_interconnect_0:hps_0_h2f_axi_master_awprot
wire [63:0] hps_0_h2f_axi_master_wdata; // hps_0:h2f_WDATA -> mm_interconnect_0:hps_0_h2f_axi_master_wdata
wire hps_0_h2f_axi_master_arvalid; // hps_0:h2f_ARVALID -> mm_interconnect_0:hps_0_h2f_axi_master_arvalid
wire [3:0] hps_0_h2f_axi_master_awcache; // hps_0:h2f_AWCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_awcache
wire [11:0] hps_0_h2f_axi_master_arid; // hps_0:h2f_ARID -> mm_interconnect_0:hps_0_h2f_axi_master_arid
wire [1:0] hps_0_h2f_axi_master_arlock; // hps_0:h2f_ARLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_arlock
wire [1:0] hps_0_h2f_axi_master_awlock; // hps_0:h2f_AWLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_awlock
wire [29:0] hps_0_h2f_axi_master_awaddr; // hps_0:h2f_AWADDR -> mm_interconnect_0:hps_0_h2f_axi_master_awaddr
wire [1:0] hps_0_h2f_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_axi_master_bresp -> hps_0:h2f_BRESP
wire hps_0_h2f_axi_master_arready; // mm_interconnect_0:hps_0_h2f_axi_master_arready -> hps_0:h2f_ARREADY
wire [63:0] hps_0_h2f_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_axi_master_rdata -> hps_0:h2f_RDATA
wire hps_0_h2f_axi_master_awready; // mm_interconnect_0:hps_0_h2f_axi_master_awready -> hps_0:h2f_AWREADY
wire [1:0] hps_0_h2f_axi_master_arburst; // hps_0:h2f_ARBURST -> mm_interconnect_0:hps_0_h2f_axi_master_arburst
wire [2:0] hps_0_h2f_axi_master_arsize; // hps_0:h2f_ARSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_arsize
wire hps_0_h2f_axi_master_bready; // hps_0:h2f_BREADY -> mm_interconnect_0:hps_0_h2f_axi_master_bready
wire hps_0_h2f_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_axi_master_rlast -> hps_0:h2f_RLAST
wire hps_0_h2f_axi_master_wlast; // hps_0:h2f_WLAST -> mm_interconnect_0:hps_0_h2f_axi_master_wlast
wire [1:0] hps_0_h2f_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_axi_master_rresp -> hps_0:h2f_RRESP
wire [11:0] hps_0_h2f_axi_master_awid; // hps_0:h2f_AWID -> mm_interconnect_0:hps_0_h2f_axi_master_awid
wire [11:0] hps_0_h2f_axi_master_bid; // mm_interconnect_0:hps_0_h2f_axi_master_bid -> hps_0:h2f_BID
wire hps_0_h2f_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_axi_master_bvalid -> hps_0:h2f_BVALID
wire [2:0] hps_0_h2f_axi_master_awsize; // hps_0:h2f_AWSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_awsize
wire hps_0_h2f_axi_master_awvalid; // hps_0:h2f_AWVALID -> mm_interconnect_0:hps_0_h2f_axi_master_awvalid
wire hps_0_h2f_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_axi_master_rvalid -> hps_0:h2f_RVALID
wire [31:0] fpga_only_master_master_readdata; // mm_interconnect_0:fpga_only_master_master_readdata -> fpga_only_master:master_readdata
wire fpga_only_master_master_waitrequest; // mm_interconnect_0:fpga_only_master_master_waitrequest -> fpga_only_master:master_waitrequest
wire [31:0] fpga_only_master_master_address; // fpga_only_master:master_address -> mm_interconnect_0:fpga_only_master_master_address
wire fpga_only_master_master_read; // fpga_only_master:master_read -> mm_interconnect_0:fpga_only_master_master_read
wire [3:0] fpga_only_master_master_byteenable; // fpga_only_master:master_byteenable -> mm_interconnect_0:fpga_only_master_master_byteenable
wire fpga_only_master_master_readdatavalid; // mm_interconnect_0:fpga_only_master_master_readdatavalid -> fpga_only_master:master_readdatavalid
wire fpga_only_master_master_write; // fpga_only_master:master_write -> mm_interconnect_0:fpga_only_master_master_write
wire [31:0] fpga_only_master_master_writedata; // fpga_only_master:master_writedata -> mm_interconnect_0:fpga_only_master_master_writedata
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [12:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [7:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
wire [31:0] mm_interconnect_0_custom_leds_0_s0_readdata; // custom_leds_0:avs_s0_readdata -> mm_interconnect_0:custom_leds_0_s0_readdata
wire [0:0] mm_interconnect_0_custom_leds_0_s0_address; // mm_interconnect_0:custom_leds_0_s0_address -> custom_leds_0:avs_s0_address
wire mm_interconnect_0_custom_leds_0_s0_read; // mm_interconnect_0:custom_leds_0_s0_read -> custom_leds_0:avs_s0_read
wire mm_interconnect_0_custom_leds_0_s0_write; // mm_interconnect_0:custom_leds_0_s0_write -> custom_leds_0:avs_s0_write
wire [31:0] mm_interconnect_0_custom_leds_0_s0_writedata; // mm_interconnect_0:custom_leds_0_s0_writedata -> custom_leds_0:avs_s0_writedata
wire mm_interconnect_0_dipsw_pio_s1_chipselect; // mm_interconnect_0:dipsw_pio_s1_chipselect -> dipsw_pio:chipselect
wire [31:0] mm_interconnect_0_dipsw_pio_s1_readdata; // dipsw_pio:readdata -> mm_interconnect_0:dipsw_pio_s1_readdata
wire [1:0] mm_interconnect_0_dipsw_pio_s1_address; // mm_interconnect_0:dipsw_pio_s1_address -> dipsw_pio:address
wire mm_interconnect_0_dipsw_pio_s1_write; // mm_interconnect_0:dipsw_pio_s1_write -> dipsw_pio:write_n
wire [31:0] mm_interconnect_0_dipsw_pio_s1_writedata; // mm_interconnect_0:dipsw_pio_s1_writedata -> dipsw_pio:writedata
wire mm_interconnect_0_button_pio_s1_chipselect; // mm_interconnect_0:button_pio_s1_chipselect -> button_pio:chipselect
wire [31:0] mm_interconnect_0_button_pio_s1_readdata; // button_pio:readdata -> mm_interconnect_0:button_pio_s1_readdata
wire [1:0] mm_interconnect_0_button_pio_s1_address; // mm_interconnect_0:button_pio_s1_address -> button_pio:address
wire mm_interconnect_0_button_pio_s1_write; // mm_interconnect_0:button_pio_s1_write -> button_pio:write_n
wire [31:0] mm_interconnect_0_button_pio_s1_writedata; // mm_interconnect_0:button_pio_s1_writedata -> button_pio:writedata
wire [31:0] hps_only_master_master_readdata; // mm_interconnect_1:hps_only_master_master_readdata -> hps_only_master:master_readdata
wire hps_only_master_master_waitrequest; // mm_interconnect_1:hps_only_master_master_waitrequest -> hps_only_master:master_waitrequest
wire [31:0] hps_only_master_master_address; // hps_only_master:master_address -> mm_interconnect_1:hps_only_master_master_address
wire hps_only_master_master_read; // hps_only_master:master_read -> mm_interconnect_1:hps_only_master_master_read
wire [3:0] hps_only_master_master_byteenable; // hps_only_master:master_byteenable -> mm_interconnect_1:hps_only_master_master_byteenable
wire hps_only_master_master_readdatavalid; // mm_interconnect_1:hps_only_master_master_readdatavalid -> hps_only_master:master_readdatavalid
wire hps_only_master_master_write; // hps_only_master:master_write -> mm_interconnect_1:hps_only_master_master_write
wire [31:0] hps_only_master_master_writedata; // hps_only_master:master_writedata -> mm_interconnect_1:hps_only_master_master_writedata
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awburst; // mm_interconnect_1:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_awuser; // mm_interconnect_1:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlen; // mm_interconnect_1:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire [15:0] mm_interconnect_1_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_1:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_1_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_wready
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_1:hps_0_f2h_axi_slave_rid
wire mm_interconnect_1_hps_0_f2h_axi_slave_rready; // mm_interconnect_1:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlen; // mm_interconnect_1:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_wid; // mm_interconnect_1:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arcache; // mm_interconnect_1:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire mm_interconnect_1_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_araddr; // mm_interconnect_1:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arprot; // mm_interconnect_1:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awprot; // mm_interconnect_1:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_wdata; // mm_interconnect_1:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_1_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awcache; // mm_interconnect_1:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_arid; // mm_interconnect_1:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlock; // mm_interconnect_1:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlock; // mm_interconnect_1:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_1:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_bresp
wire mm_interconnect_1_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_arready
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_1:hps_0_f2h_axi_slave_rdata
wire mm_interconnect_1_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_awready
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arburst; // mm_interconnect_1:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arsize; // mm_interconnect_1:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_bready; // mm_interconnect_1:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire mm_interconnect_1_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_1:hps_0_f2h_axi_slave_rlast
wire mm_interconnect_1_hps_0_f2h_axi_slave_wlast; // mm_interconnect_1:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_rresp
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_awid; // mm_interconnect_1:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_1:hps_0_f2h_axi_slave_bid
wire mm_interconnect_1_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_bvalid
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awsize; // mm_interconnect_1:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_aruser; // mm_interconnect_1:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire mm_interconnect_1_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_rvalid
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [button_pio:reset_n, custom_leds_0:reset, dipsw_pio:reset_n, jtag_uart:rst_n, mm_interconnect_0:fpga_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:onchip_memory2_0_reset1_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_translator:in_reset, sysid_qsys:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset]
soc_system_button_pio button_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_button_pio_s1_address), // s1.address
.write_n (~mm_interconnect_0_button_pio_s1_write), // .write_n
.writedata (mm_interconnect_0_button_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_button_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_button_pio_s1_readdata), // .readdata
.in_port (button_pio_external_connection_export) // external_connection.export
);
custom_leds custom_leds_0 (
.clk (clk_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_0_custom_leds_0_s0_address), // s0.address
.avs_s0_read (mm_interconnect_0_custom_leds_0_s0_read), // .read
.avs_s0_write (mm_interconnect_0_custom_leds_0_s0_write), // .write
.avs_s0_readdata (mm_interconnect_0_custom_leds_0_s0_readdata), // .readdata
.avs_s0_writedata (mm_interconnect_0_custom_leds_0_s0_writedata), // .writedata
.leds (custom_leds_0_leds_leds) // leds.leds
);
soc_system_dipsw_pio dipsw_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_dipsw_pio_s1_address), // s1.address
.write_n (~mm_interconnect_0_dipsw_pio_s1_write), // .write_n
.writedata (mm_interconnect_0_dipsw_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_dipsw_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_dipsw_pio_s1_readdata), // .readdata
.in_port (dipsw_pio_external_connection_export) // external_connection.export
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) fpga_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (fpga_only_master_master_address), // master.address
.master_readdata (fpga_only_master_master_readdata), // .readdata
.master_read (fpga_only_master_master_read), // .read
.master_write (fpga_only_master_master_write), // .write
.master_writedata (fpga_only_master_master_writedata), // .writedata
.master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_hps_0 #(
.F2S_Width (3),
.S2F_Width (2)
) hps_0 (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (hps_0_h2f_axi_master_awid), // h2f_axi_master.awid
.h2f_AWADDR (hps_0_h2f_axi_master_awaddr), // .awaddr
.h2f_AWLEN (hps_0_h2f_axi_master_awlen), // .awlen
.h2f_AWSIZE (hps_0_h2f_axi_master_awsize), // .awsize
.h2f_AWBURST (hps_0_h2f_axi_master_awburst), // .awburst
.h2f_AWLOCK (hps_0_h2f_axi_master_awlock), // .awlock
.h2f_AWCACHE (hps_0_h2f_axi_master_awcache), // .awcache
.h2f_AWPROT (hps_0_h2f_axi_master_awprot), // .awprot
.h2f_AWVALID (hps_0_h2f_axi_master_awvalid), // .awvalid
.h2f_AWREADY (hps_0_h2f_axi_master_awready), // .awready
.h2f_WID (hps_0_h2f_axi_master_wid), // .wid
.h2f_WDATA (hps_0_h2f_axi_master_wdata), // .wdata
.h2f_WSTRB (hps_0_h2f_axi_master_wstrb), // .wstrb
.h2f_WLAST (hps_0_h2f_axi_master_wlast), // .wlast
.h2f_WVALID (hps_0_h2f_axi_master_wvalid), // .wvalid
.h2f_WREADY (hps_0_h2f_axi_master_wready), // .wready
.h2f_BID (hps_0_h2f_axi_master_bid), // .bid
.h2f_BRESP (hps_0_h2f_axi_master_bresp), // .bresp
.h2f_BVALID (hps_0_h2f_axi_master_bvalid), // .bvalid
.h2f_BREADY (hps_0_h2f_axi_master_bready), // .bready
.h2f_ARID (hps_0_h2f_axi_master_arid), // .arid
.h2f_ARADDR (hps_0_h2f_axi_master_araddr), // .araddr
.h2f_ARLEN (hps_0_h2f_axi_master_arlen), // .arlen
.h2f_ARSIZE (hps_0_h2f_axi_master_arsize), // .arsize
.h2f_ARBURST (hps_0_h2f_axi_master_arburst), // .arburst
.h2f_ARLOCK (hps_0_h2f_axi_master_arlock), // .arlock
.h2f_ARCACHE (hps_0_h2f_axi_master_arcache), // .arcache
.h2f_ARPROT (hps_0_h2f_axi_master_arprot), // .arprot
.h2f_ARVALID (hps_0_h2f_axi_master_arvalid), // .arvalid
.h2f_ARREADY (hps_0_h2f_axi_master_arready), // .arready
.h2f_RID (hps_0_h2f_axi_master_rid), // .rid
.h2f_RDATA (hps_0_h2f_axi_master_rdata), // .rdata
.h2f_RRESP (hps_0_h2f_axi_master_rresp), // .rresp
.h2f_RLAST (hps_0_h2f_axi_master_rlast), // .rlast
.h2f_RVALID (hps_0_h2f_axi_master_rvalid), // .rvalid
.h2f_RREADY (hps_0_h2f_axi_master_rready), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready) // .rready
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) hps_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (hps_only_master_master_address), // master.address
.master_readdata (hps_only_master_master_readdata), // .readdata
.master_read (hps_only_master_master_read), // .read
.master_write (hps_only_master_master_write), // .write
.master_writedata (hps_only_master_master_writedata), // .writedata
.master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (hps_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq () // irq.irq
);
soc_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
soc_system_sysid_qsys sysid_qsys (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_qsys_control_slave_address) // .address
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_axi_master_awid (hps_0_h2f_axi_master_awid), // hps_0_h2f_axi_master.awid
.hps_0_h2f_axi_master_awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.hps_0_h2f_axi_master_awlen (hps_0_h2f_axi_master_awlen), // .awlen
.hps_0_h2f_axi_master_awsize (hps_0_h2f_axi_master_awsize), // .awsize
.hps_0_h2f_axi_master_awburst (hps_0_h2f_axi_master_awburst), // .awburst
.hps_0_h2f_axi_master_awlock (hps_0_h2f_axi_master_awlock), // .awlock
.hps_0_h2f_axi_master_awcache (hps_0_h2f_axi_master_awcache), // .awcache
.hps_0_h2f_axi_master_awprot (hps_0_h2f_axi_master_awprot), // .awprot
.hps_0_h2f_axi_master_awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.hps_0_h2f_axi_master_awready (hps_0_h2f_axi_master_awready), // .awready
.hps_0_h2f_axi_master_wid (hps_0_h2f_axi_master_wid), // .wid
.hps_0_h2f_axi_master_wdata (hps_0_h2f_axi_master_wdata), // .wdata
.hps_0_h2f_axi_master_wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.hps_0_h2f_axi_master_wlast (hps_0_h2f_axi_master_wlast), // .wlast
.hps_0_h2f_axi_master_wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.hps_0_h2f_axi_master_wready (hps_0_h2f_axi_master_wready), // .wready
.hps_0_h2f_axi_master_bid (hps_0_h2f_axi_master_bid), // .bid
.hps_0_h2f_axi_master_bresp (hps_0_h2f_axi_master_bresp), // .bresp
.hps_0_h2f_axi_master_bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.hps_0_h2f_axi_master_bready (hps_0_h2f_axi_master_bready), // .bready
.hps_0_h2f_axi_master_arid (hps_0_h2f_axi_master_arid), // .arid
.hps_0_h2f_axi_master_araddr (hps_0_h2f_axi_master_araddr), // .araddr
.hps_0_h2f_axi_master_arlen (hps_0_h2f_axi_master_arlen), // .arlen
.hps_0_h2f_axi_master_arsize (hps_0_h2f_axi_master_arsize), // .arsize
.hps_0_h2f_axi_master_arburst (hps_0_h2f_axi_master_arburst), // .arburst
.hps_0_h2f_axi_master_arlock (hps_0_h2f_axi_master_arlock), // .arlock
.hps_0_h2f_axi_master_arcache (hps_0_h2f_axi_master_arcache), // .arcache
.hps_0_h2f_axi_master_arprot (hps_0_h2f_axi_master_arprot), // .arprot
.hps_0_h2f_axi_master_arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.hps_0_h2f_axi_master_arready (hps_0_h2f_axi_master_arready), // .arready
.hps_0_h2f_axi_master_rid (hps_0_h2f_axi_master_rid), // .rid
.hps_0_h2f_axi_master_rdata (hps_0_h2f_axi_master_rdata), // .rdata
.hps_0_h2f_axi_master_rresp (hps_0_h2f_axi_master_rresp), // .rresp
.hps_0_h2f_axi_master_rlast (hps_0_h2f_axi_master_rlast), // .rlast
.hps_0_h2f_axi_master_rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.hps_0_h2f_axi_master_rready (hps_0_h2f_axi_master_rready), // .rready
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.fpga_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.onchip_memory2_0_reset1_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // onchip_memory2_0_reset1_reset_bridge_in_reset.reset
.fpga_only_master_master_address (fpga_only_master_master_address), // fpga_only_master_master.address
.fpga_only_master_master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.fpga_only_master_master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.fpga_only_master_master_read (fpga_only_master_master_read), // .read
.fpga_only_master_master_readdata (fpga_only_master_master_readdata), // .readdata
.fpga_only_master_master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.fpga_only_master_master_write (fpga_only_master_master_write), // .write
.fpga_only_master_master_writedata (fpga_only_master_master_writedata), // .writedata
.button_pio_s1_address (mm_interconnect_0_button_pio_s1_address), // button_pio_s1.address
.button_pio_s1_write (mm_interconnect_0_button_pio_s1_write), // .write
.button_pio_s1_readdata (mm_interconnect_0_button_pio_s1_readdata), // .readdata
.button_pio_s1_writedata (mm_interconnect_0_button_pio_s1_writedata), // .writedata
.button_pio_s1_chipselect (mm_interconnect_0_button_pio_s1_chipselect), // .chipselect
.custom_leds_0_s0_address (mm_interconnect_0_custom_leds_0_s0_address), // custom_leds_0_s0.address
.custom_leds_0_s0_write (mm_interconnect_0_custom_leds_0_s0_write), // .write
.custom_leds_0_s0_read (mm_interconnect_0_custom_leds_0_s0_read), // .read
.custom_leds_0_s0_readdata (mm_interconnect_0_custom_leds_0_s0_readdata), // .readdata
.custom_leds_0_s0_writedata (mm_interconnect_0_custom_leds_0_s0_writedata), // .writedata
.dipsw_pio_s1_address (mm_interconnect_0_dipsw_pio_s1_address), // dipsw_pio_s1.address
.dipsw_pio_s1_write (mm_interconnect_0_dipsw_pio_s1_write), // .write
.dipsw_pio_s1_readdata (mm_interconnect_0_dipsw_pio_s1_readdata), // .readdata
.dipsw_pio_s1_writedata (mm_interconnect_0_dipsw_pio_s1_writedata), // .writedata
.dipsw_pio_s1_chipselect (mm_interconnect_0_dipsw_pio_s1_chipselect), // .chipselect
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.sysid_qsys_control_slave_address (mm_interconnect_0_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.hps_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_only_master_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
.hps_only_master_master_address (hps_only_master_master_address), // hps_only_master_master.address
.hps_only_master_master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.hps_only_master_master_byteenable (hps_only_master_master_byteenable), // .byteenable
.hps_only_master_master_read (hps_only_master_master_read), // .read
.hps_only_master_master_readdata (hps_only_master_master_readdata), // .readdata
.hps_only_master_master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.hps_only_master_master_write (hps_only_master_master_write), // .write
.hps_only_master_master_writedata (hps_only_master_master_writedata) // .writedata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module glbl ();
//parameter ROC_WIDTH = 100000;
parameter ROC_WIDTH = 1000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_io__top_xres4v2 (
//# {{data|Data Signals}}
input FILT_IN_H ,
input INP_SEL_H ,
inout PAD ,
inout PAD_A_ESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input DISABLE_PULLUP_H,
input ENABLE_H ,
input ENABLE_VDDIO ,
input EN_VDDIO_SIG_H ,
output XRES_H_N ,
//# {{power|Power}}
inout PULLUP_H ,
input VSWITCH ,
input VCCD ,
input VCCHIB ,
input VDDA ,
input VDDIO ,
input VDDIO_Q ,
output TIE_HI_ESD ,
inout TIE_WEAK_HI_H ,
input VSSA ,
input VSSD ,
input VSSIO ,
input VSSIO_Q ,
output TIE_LO_ESD
);
endmodule |
module finalproject_mm_interconnect_1 (
input wire clocks_c1_clk, // clocks_c1.clk
input wire clock_crossing_io_m0_reset_reset_bridge_in_reset_reset, // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset
input wire [21:0] clock_crossing_io_m0_address, // clock_crossing_io_m0.address
output wire clock_crossing_io_m0_waitrequest, // .waitrequest
input wire [0:0] clock_crossing_io_m0_burstcount, // .burstcount
input wire [3:0] clock_crossing_io_m0_byteenable, // .byteenable
input wire clock_crossing_io_m0_read, // .read
output wire [31:0] clock_crossing_io_m0_readdata, // .readdata
output wire clock_crossing_io_m0_readdatavalid, // .readdatavalid
input wire clock_crossing_io_m0_write, // .write
input wire [31:0] clock_crossing_io_m0_writedata, // .writedata
input wire clock_crossing_io_m0_debugaccess, // .debugaccess
output wire [1:0] CY7C67200_IF_0_hpi_address, // CY7C67200_IF_0_hpi.address
output wire CY7C67200_IF_0_hpi_write, // .write
output wire CY7C67200_IF_0_hpi_read, // .read
input wire [31:0] CY7C67200_IF_0_hpi_readdata, // .readdata
output wire [31:0] CY7C67200_IF_0_hpi_writedata, // .writedata
output wire CY7C67200_IF_0_hpi_chipselect // .chipselect
);
wire clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest; // CY7C67200_IF_0_hpi_translator:uav_waitrequest -> clock_crossing_io_m0_translator:uav_waitrequest
wire [31:0] clock_crossing_io_m0_translator_avalon_universal_master_0_readdata; // CY7C67200_IF_0_hpi_translator:uav_readdata -> clock_crossing_io_m0_translator:uav_readdata
wire clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess; // clock_crossing_io_m0_translator:uav_debugaccess -> CY7C67200_IF_0_hpi_translator:uav_debugaccess
wire [21:0] clock_crossing_io_m0_translator_avalon_universal_master_0_address; // clock_crossing_io_m0_translator:uav_address -> CY7C67200_IF_0_hpi_translator:uav_address
wire clock_crossing_io_m0_translator_avalon_universal_master_0_read; // clock_crossing_io_m0_translator:uav_read -> CY7C67200_IF_0_hpi_translator:uav_read
wire [3:0] clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable; // clock_crossing_io_m0_translator:uav_byteenable -> CY7C67200_IF_0_hpi_translator:uav_byteenable
wire clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid; // CY7C67200_IF_0_hpi_translator:uav_readdatavalid -> clock_crossing_io_m0_translator:uav_readdatavalid
wire clock_crossing_io_m0_translator_avalon_universal_master_0_lock; // clock_crossing_io_m0_translator:uav_lock -> CY7C67200_IF_0_hpi_translator:uav_lock
wire clock_crossing_io_m0_translator_avalon_universal_master_0_write; // clock_crossing_io_m0_translator:uav_write -> CY7C67200_IF_0_hpi_translator:uav_write
wire [31:0] clock_crossing_io_m0_translator_avalon_universal_master_0_writedata; // clock_crossing_io_m0_translator:uav_writedata -> CY7C67200_IF_0_hpi_translator:uav_writedata
wire [2:0] clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount; // clock_crossing_io_m0_translator:uav_burstcount -> CY7C67200_IF_0_hpi_translator:uav_burstcount
altera_merlin_master_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) clock_crossing_io_m0_translator (
.clk (clocks_c1_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_crossing_io_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_crossing_io_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_crossing_io_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_crossing_io_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (clock_crossing_io_m0_address), // avalon_anti_master_0.address
.av_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest
.av_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.av_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.av_read (clock_crossing_io_m0_read), // .read
.av_readdata (clock_crossing_io_m0_readdata), // .readdata
.av_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.av_write (clock_crossing_io_m0_write), // .write
.av_writedata (clock_crossing_io_m0_writedata), // .writedata
.av_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (2),
.AV_WRITE_WAIT_CYCLES (2),
.AV_SETUP_WAIT_CYCLES (2),
.AV_DATA_HOLD_CYCLES (2)
) cy7c67200_if_0_hpi_translator (
.clk (clocks_c1_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_m0_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_crossing_io_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_crossing_io_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_crossing_io_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_crossing_io_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (CY7C67200_IF_0_hpi_address), // avalon_anti_slave_0.address
.av_write (CY7C67200_IF_0_hpi_write), // .write
.av_read (CY7C67200_IF_0_hpi_read), // .read
.av_readdata (CY7C67200_IF_0_hpi_readdata), // .readdata
.av_writedata (CY7C67200_IF_0_hpi_writedata), // .writedata
.av_chipselect (CY7C67200_IF_0_hpi_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule |
module pcie_axi_trn_bridge # (
parameter C_DATA_WIDTH = 64,
parameter RBAR_WIDTH = 7,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
)
(
// Common
input user_clk,
input user_reset,
input user_lnk_up,
// AXI TX
//-----------
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
output s_axis_tx_tvalid, // TX data is valid
input s_axis_tx_tready, // TX ready for data
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
output s_axis_tx_tlast, // TX data is last
output [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
output m_axis_rx_tready, // RX ready for data
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Usrapp I/O //
//---------------------------------------------//
// TRN TX
//-----------
input [C_DATA_WIDTH-1:0] trn_td, // TX data from usrapp
input trn_tsof, // TX start of packet
input trn_teof, // TX end of packet
input trn_tsrc_rdy, // TX source ready
output trn_tdst_rdy, // TX destination ready
input trn_tsrc_dsc, // TX source discontinue
input [REM_WIDTH-1:0] trn_trem, // TX remainder
input trn_terrfwd, // TX error forward
input trn_tstr, // TX streaming enable
input trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
output [C_DATA_WIDTH-1:0] trn_rd, // RX data to usrapp
output trn_rsof, // RX start of packet
output trn_reof, // RX end of packet
output trn_rsrc_rdy, // RX source ready
input trn_rdst_rdy, // RX destination ready
output reg trn_rsrc_dsc, // RX source discontinue
output [REM_WIDTH-1:0] trn_rrem, // RX remainder
output wire trn_rerrfwd, // RX error forward
output [RBAR_WIDTH-1:0] trn_rbar_hit // RX BAR hit
);
//DWORD Reordering between AXI and TRN interface//
generate begin:gen_axis_txdata
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32]};
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32],trn_td[95:64],trn_td[127:96]};
end
end
endgenerate
//Coversion from trn_rem to s_axis_tkeep[7:0]//
generate begin: gen_axis_tx_tkeep
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tkeep = (trn_teof && ~trn_trem) ? 8'h0F : 8'hFF;
// always @*
// begin
// if (trn_teof && ~trn_trem) begin
// s_axis_tx_tkeep <= 8'h0F;
// end else begin
// s_axis_tx_tkeep <= 8'hFF;
// end
// end
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tkeep = (trn_teof) ? ((trn_trem == 2'b11) ? 16'hFFFF :
((trn_trem == 2'b10) ? 16'h0FFF :
((trn_trem == 2'b01) ? 16'h00FF : 16'h000F ))) :
16'hFFFF;
// always @*
// begin
// if (trn_teof)
// begin
// case (trn_trem)
// 2'b11: begin s_axis_tx_tkeep <= 16'hFFFF; end
// 2'b10: begin s_axis_tx_tkeep <= 16'h0FFF; end
// 2'b01: begin s_axis_tx_tkeep <= 16'h00FF; end
// 2'b00: begin s_axis_tx_tkeep <= 16'h000F; end
// endcase
// end
// else
// begin
// s_axis_tx_tkeep <= 16'hFFFF;
// end
// end
end
end
endgenerate
//Connection of s_axis_tx_tuser with trn_tsrc_dsc,trn_tstr,trn_terr_fwd and trn_terr_fwd
assign s_axis_tx_tuser [3] = trn_tsrc_dsc;
assign s_axis_tx_tuser [2] = trn_tstr;
assign s_axis_tx_tuser [1] = trn_terrfwd;
assign s_axis_tx_tuser [0] = trn_tecrc_gen;
//Constraint trn_tsrc_rdy. If constrained, testbench keep trn_tsrc_rdy constantly asserted. This makes axi bridge to generate trn_tsof immeditely after trn_teof of previous packet.//
reg trn_tsrc_rdy_derived = 1'b0;
always @*
begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof)
begin
trn_tsrc_rdy_derived <= 1'b1;
end
else if(trn_tsrc_rdy_derived && trn_teof && trn_tsrc_rdy && trn_tdst_rdy)
begin
trn_tsrc_rdy_derived <= 1'b0;
end
end
assign s_axis_tx_tvalid = trn_tsrc_rdy_derived || trn_tsof || trn_teof;
assign trn_tdst_rdy = s_axis_tx_tready;
assign s_axis_tx_tlast = trn_teof;
assign m_axis_rx_tready = trn_rdst_rdy;
generate begin:gen_trn_rd
if (C_DATA_WIDTH == 64) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata[63:32]};
end else if (C_DATA_WIDTH == 128) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata [63:32],m_axis_rx_tdata [95:64],m_axis_rx_tdata [127:96]};
end
end
endgenerate
//Regenerate trn_rsof
//Used clock. Latency may have been added
reg in_packet_reg;
generate begin:gen_trn_rsof
if (C_DATA_WIDTH == 64)
begin
always @(posedge user_clk)
begin
if (user_reset)
in_packet_reg <= 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready)
in_packet_reg <= ~m_axis_rx_tlast;
end
assign trn_rsof = m_axis_rx_tvalid & ~in_packet_reg;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rsof = m_axis_rx_tuser [14];
end
end
endgenerate
generate begin: gen_trn_reof
if (C_DATA_WIDTH == 64)
begin
assign trn_reof = m_axis_rx_tlast;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_reof = m_axis_rx_tuser[21]; //is_eof[4];
end
end
endgenerate
assign trn_rsrc_rdy = m_axis_rx_tvalid;
//Regenerate trn_rsrc_dsc
//Used clock. Latency may have been added
always @(posedge user_clk)
begin
if (user_reset)
trn_rsrc_dsc <= 1'b1;
else
trn_rsrc_dsc <= ~user_lnk_up;
end
wire [4:0] is_sof;
wire [4:0] is_eof;
assign is_sof = m_axis_rx_tuser[14:10];
assign is_eof = m_axis_rx_tuser[21:17];
generate begin:gen_trn_rrem
if (C_DATA_WIDTH == 64)
begin
assign trn_rrem = m_axis_rx_tlast ? (m_axis_rx_tkeep == 8'hFF) ? 1'b1 : 1'b0: 1'b1;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rrem[0] = is_eof[2];
assign trn_rrem[1] = (is_eof[4] || is_sof[4] ) ? ( (is_sof[4] && is_eof[4] && is_eof[3]) || (!is_sof[4] && is_eof[4] && is_eof[3]) || (is_sof[4] && !is_eof[4] && !is_sof[3]) ) : 1'b1;
end
end
endgenerate
assign trn_rerrfwd = m_axis_rx_tuser[1];
assign trn_rbar_hit = m_axis_rx_tuser[8:2];
endmodule |
module _90_lut_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL_A_ = 0;
parameter _TECHMAP_CONSTMSK_B_ = 0;
parameter _TECHMAP_CONSTVAL_B_ = 0;
function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
input integer width;
input integer operation;
input integer swap;
input integer sign;
input integer operand;
integer n, i_var, i_cst, lhs, rhs, o_bit;
begin
gen_lut = width'b0;
for (n = 0; n < (1 << width); n++) begin
if (sign)
i_var = n[width-1:0];
else
i_var = n;
i_cst = operand;
if (swap) begin
lhs = i_cst;
rhs = i_var;
end else begin
lhs = i_var;
rhs = i_cst;
end
if (operation == 0)
o_bit = (lhs < rhs);
if (operation == 1)
o_bit = (lhs <= rhs);
if (operation == 2)
o_bit = (lhs > rhs);
if (operation == 3)
o_bit = (lhs >= rhs);
gen_lut = gen_lut | (o_bit << n);
end
end
endfunction
generate
if (_TECHMAP_CELLTYPE_ == "$lt")
localparam operation = 0;
if (_TECHMAP_CELLTYPE_ == "$le")
localparam operation = 1;
if (_TECHMAP_CELLTYPE_ == "$gt")
localparam operation = 2;
if (_TECHMAP_CELLTYPE_ == "$ge")
localparam operation = 3;
if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
wire _TECHMAP_FAIL_ = 1;
else if (&_TECHMAP_CONSTMSK_B_)
\$lut #(
.WIDTH(A_WIDTH),
.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
) _TECHMAP_REPLACE_ (
.A(A),
.Y(Y)
);
else if (&_TECHMAP_CONSTMSK_A_)
\$lut #(
.WIDTH(B_WIDTH),
.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
) _TECHMAP_REPLACE_ (
.A(B),
.Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule |
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int
);
parameter MEM_SEL_0 = 0;
parameter MEM_OFFSET_0 = 32'h00000000;
parameter MEM_SIZE_0 = 32'h800000;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from mem slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 1'b0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 4'b0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 32'h0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 32'h0;
endmodule |
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module sysgen_constant_828adcadae (
output [(8 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 8'b00000001;
endmodule |
module sysgen_inverter_dea83a2b38 (
input [(1 - 1):0] ip,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire ip_1_26;
reg op_mem_22_20[0:(1 - 1)];
initial
begin
op_mem_22_20[0] = 1'b0;
end
wire op_mem_22_20_front_din;
wire op_mem_22_20_back;
wire op_mem_22_20_push_front_pop_back_en;
localparam [(1 - 1):0] const_value = 1'b1;
wire internal_ip_12_1_bitnot;
assign ip_1_26 = ip;
assign op_mem_22_20_back = op_mem_22_20[0];
always @(posedge clk)
begin:proc_op_mem_22_20
integer i;
if (((ce == 1'b1) && (op_mem_22_20_push_front_pop_back_en == 1'b1)))
begin
op_mem_22_20[0] <= op_mem_22_20_front_din;
end
end
assign internal_ip_12_1_bitnot = ~ip_1_26;
assign op_mem_22_20_push_front_pop_back_en = 1'b0;
assign op = internal_ip_12_1_bitnot;
endmodule |
module sysgen_logical_8b7810a2aa (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign fully_2_1_bit = d0_1_24 | d1_1_27;
assign y = fully_2_1_bit;
endmodule |
module sysgen_logical_f9d74a72d1 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign fully_2_1_bit = d0_1_24 & d1_1_27;
assign y = fully_2_1_bit;
endmodule |
module sysgen_reinterpret_ad93f43143 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr);
wire [(16 - 1):0] input_port_1_40;
wire signed [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule |
module channelizer_xlslice (x, y);
//Parameter Definitions
parameter new_msb= 9;
parameter new_lsb= 1;
parameter x_width= 16;
parameter y_width= 8;
//Port Declartions
input [x_width-1:0] x;
output [y_width-1:0] y;
assign y = x[new_msb:new_lsb];
endmodule |
module sysgen_constant_fa8d4b3e6d (
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 1'b1;
endmodule |
module sysgen_concat_c4ee67c59a (
input [(16 - 1):0] in0,
input [(16 - 1):0] in1,
output [(32 - 1):0] y,
input clk,
input ce,
input clr);
wire [(16 - 1):0] in0_1_23;
wire [(16 - 1):0] in1_1_27;
wire [(32 - 1):0] y_2_1_concat;
assign in0_1_23 = in0;
assign in1_1_27 = in1;
assign y_2_1_concat = {in0_1_23, in1_1_27};
assign y = y_2_1_concat;
endmodule |
module channelizer_xlconvert (din, clk, ce, clr, en, dout);
//Parameter Definitions
parameter din_width= 16;
parameter din_bin_pt= 4;
parameter din_arith= `xlUnsigned;
parameter dout_width= 8;
parameter dout_bin_pt= 2;
parameter dout_arith= `xlUnsigned;
parameter en_width = 1;
parameter en_bin_pt = 0;
parameter en_arith = `xlUnsigned;
parameter bool_conversion = 0;
parameter latency = 0;
parameter quantization= `xlTruncate;
parameter overflow= `xlWrap;
//Port Declartions
input [din_width-1:0] din;
input clk, ce, clr;
input [en_width-1:0] en;
output [dout_width-1:0] dout;
//Wire Declartions
wire [dout_width-1:0] result;
wire internal_ce;
assign internal_ce = ce & en[0];
generate
if (bool_conversion == 1)
begin:bool_converion_generate
assign result = din;
end
else
begin:std_conversion
convert_type #(din_width,
din_bin_pt,
din_arith,
dout_width,
dout_bin_pt,
dout_arith,
quantization,
overflow)
conv_udp (.inp(din), .res(result));
end
endgenerate
generate
if (latency > 0)
begin:latency_test
synth_reg # (dout_width, latency)
reg1 (
.i(result),
.ce(internal_ce),
.clr(clr),
.clk(clk),
.o(dout));
end
else
begin:latency0
assign dout = result;
end
endgenerate
endmodule |
module sysgen_reinterpret_af1a0b71e1 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr);
wire signed [(16 - 1):0] input_port_1_40;
wire [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule |
module sysgen_constant_ff57ff80b6 (
output [(32 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 32'b00000000000000000000000000000000;
endmodule |
module sysgen_constant_9b3be16c34 (
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 1'b0;
endmodule |
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