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notti/schaltungstechnik_vertiefung | Assignement/Task1/enable.vhd | 1 | 1248 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tb_package.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity enable_gen is
Port ( command_i : in command_rec;
enable_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
end enable_gen;
architecture Behavioral of enable_gen is
signal s_enable : std_logic:='0';
signal s_done_o : std_logic;
begin
done_o(0) <= 'Z';
done_o(1) <= 'Z';
done_o(2) <= 'Z';
done_o(3) <= 'Z';
done_o(4) <= 'Z';
done_o(5) <= s_done_o;
done_o(6) <= 'Z';
enable_o <= s_enable;
p_main: process
variable value1 : string(1 to 8);
begin
s_done_o <= '0';
wait on command_i;
if command_i.gen_number=5 then
if command_i.mnemonic(1 to 6)="enable" then
if command_i.value1(8)='1' then
s_enable <= '1';
else
s_enable <= '0';
end if;
elsif command_i.mnemonic(1 to 4)="stop" then
-- start <= false;
end if;
s_done_o <= '1';
wait on s_done_o;
end if;
end process p_main;
end Behavioral;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/benchmark/pwm.vhd | 15 | 1069 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/svga_hello_world/serial_out.vhd | 23 | 3390 | --------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/knight_rider/serial_out.vhd | 23 | 3390 | --------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | demo/bsp/nexys_4/bsp.vhd | 15 | 24719 | -------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+
--- | USER DESIGN |
--- +-------------+
--- | |
--- | <-------< SWITCHES
--- | |
--- | >-------> LEDS
--- | |
--- | <-------< BUTTONS
--- | |
--- | >-------> SEVEN_SEGMENT_CATHODE
--- | |
--- | >-------> SEVEN_SEGMENT_ANNODE
--- | |
--- | | +--------------+
--- | | | UART |
--- | | +--------------+
--- | >-----> >-----> RS232-TX
--- | | | |
--- | | | <-------< RS232-RX
--- +---v-----^---+ +--------------+
--- | |
--- | |
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- | |
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity BSP is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
ETH_CLK : out std_logic;
PHY_RESET_N : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXD : in std_logic_vector(1 downto 0);
TXD : out std_logic_vector(1 downto 0);
TXEN : out std_logic;
JC : inout std_logic_vector(7 downto 0);
--I2C
SDA : inout std_logic;
SCL : inout std_logic;
--PS2 keyboard interface
KD : in std_logic;
KC : in std_logic;
--AUDIO interface
AUDIO : out std_logic;
AUDIO_EN : out std_logic;
--VGA interface
VGA_R : out Std_logic_vector(3 downto 0);
VGA_G : out Std_logic_vector(3 downto 0);
VGA_B : out Std_logic_vector(3 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(15 downto 0);
GPIO_SWITCHES : in std_logic_vector(15 downto 0);
GPIO_BUTTONS : in std_logic_vector(4 downto 0);
--RGB LED
LED_R_PWM : out std_logic;
LED_G_PWM : out std_logic;
LED_B_PWM : out std_logic;
SEVEN_SEGMENT_CATHODE : out std_logic_vector(6 downto 0);
SEVEN_SEGMENT_ANNODE : out std_logic_vector(7 downto 0);
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity BSP;
architecture RTL of BSP is
component rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
PHY_RESET : out std_logic;
--MII IF
TXD : out std_logic_vector(1 downto 0);
TXER : out std_logic;
TXEN : out std_logic;
RXD : in std_logic_vector(1 downto 0);
RXER : in std_logic;
RXDV : in std_logic;
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component rmii_ethernet;
component CHARSVGA is
port (
CLK : in Std_logic;
DATA : in Std_logic_vector(31 downto 0);
DATA_ACK : out Std_logic;
DATA_STB : in Std_logic;
--VGA interface
VGACLK : in Std_logic;
RST : in Std_logic;
R : out Std_logic;
G : out Std_logic;
B : out Std_logic;
HSYNCH : out Std_logic;
VSYNCH : out Std_logic
);
end component CHARSVGA;
component PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end component PWM;
component KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end component KEYBOARD;
component I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end component I2C;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(31 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(31 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(31 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
OUTPUT_VGA : out Std_logic_vector(31 downto 0);
OUTPUT_VGA_ACK : in Std_logic;
OUTPUT_VGA_STB : out Std_logic;
OUTPUT_AUDIO : out std_logic_vector(31 downto 0);
OUTPUT_AUDIO_STB : out std_logic;
OUTPUT_AUDIO_ACK : in std_logic;
OUTPUT_LED_R : out std_logic_vector(31 downto 0);
OUTPUT_LED_R_STB : out std_logic;
OUTPUT_LED_R_ACK : in std_logic;
OUTPUT_LED_G : out std_logic_vector(31 downto 0);
OUTPUT_LED_G_STB : out std_logic;
OUTPUT_LED_G_ACK : in std_logic;
OUTPUT_LED_B : out std_logic_vector(31 downto 0);
OUTPUT_LED_B_STB : out std_logic;
OUTPUT_LED_B_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_CATHODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_ANNODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : in std_logic;
INPUT_PS2 : in std_logic_vector(31 downto 0);
INPUT_PS2_STB : in std_logic;
INPUT_PS2_ACK : out std_logic;
INPUT_I2C : in std_logic_vector(31 downto 0);
INPUT_I2C_STB : in std_logic;
INPUT_I2C_ACK : out std_logic;
OUTPUT_I2C : out std_logic_vector(31 downto 0);
OUTPUT_I2C_STB : out std_logic;
OUTPUT_I2C_ACK : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(31 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
OUTPUT_ETH_TX : out std_logic_vector(31 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(31 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(31 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component SERIAL_OUTPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
component pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44100;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end component pwm_audio;
--chips signals
signal CLK : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal RST_INV : std_logic;
signal INTERNAL_RST : std_logic;
--GPIO signals
signal OUTPUT_LEDS : std_logic_vector(31 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(31 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS : std_logic_vector(31 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(4 downto 0);
--SEVEN SEGMENT DISPLAY STREAM
signal OUTPUT_SEVEN_SEGMENT_CATHODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_CATHODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_ANNODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : std_logic;
--AUDIO
signal OUTPUT_AUDIO : std_logic_vector(31 downto 0);
signal OUTPUT_AUDIO_STB : std_logic;
signal OUTPUT_AUDIO_ACK : std_logic;
--Interface for SVGA
signal VGACLK : std_logic;
signal VGA_RR : std_logic;
signal VGA_GG : std_logic;
signal VGA_BB : std_logic;
signal OUTPUT_VGA : std_logic_vector(31 downto 0);
signal OUTPUT_VGA_ACK : std_logic;
signal OUTPUT_VGA_STB : std_logic;
--PS2 interface for kb/mouse
signal PS2_STB : std_logic;
signal PS2_ACK : std_logic;
signal PS2 : std_logic_vector (31 downto 0);
--I2C interface for temperature monitor
signal INPUT_I2C : std_logic_vector(31 downto 0);
signal INPUT_I2C_STB : std_logic;
signal INPUT_I2C_ACK : std_logic;
signal OUTPUT_I2C : std_logic_vector(31 downto 0);
signal OUTPUT_I2C_STB : std_logic;
signal OUTPUT_I2C_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(31 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--ETH RX STREAM
signal ETH_RX : std_logic_vector(31 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(31 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(31 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--tri color LED signals
signal LED_R : std_logic_vector(31 downto 0);
signal LED_R_STB : std_logic;
signal LED_R_ACK : std_logic;
signal LED_G : std_logic_vector(31 downto 0);
signal LED_G_STB : std_logic;
signal LED_G_ACK : std_logic;
signal LED_B : std_logic_vector(31 downto 0);
signal LED_B_STB : std_logic;
signal LED_B_ACK : std_logic;
begin
ethernet_inst_1 : rmii_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--GMII IF
ETH_CLK => CLK_OUT1,
TXD => TXD,
TXER => open,
TXEN => TXEN,
PHY_RESET => PHY_RESET_N,
RXD => RXD,
RXER => RXER,
RXDV => RXDV,
--RX STREAM
TX => ETH_TX(15 downto 0),
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX(15 downto 0),
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
CHARSVGA_INST_1 : CHARSVGA port map(
CLK => CLK,
DATA => OUTPUT_VGA,
DATA_ACK => OUTPUT_VGA_ACK,
DATA_STB => OUTPUT_VGA_STB,
--VGA interface
VGACLK => VGACLK,
RST => INTERNAL_RST,
R => VGA_RR,
G => VGA_GG,
B => VGA_BB,
HSYNCH => HSYNCH,
VSYNCH => VSYNCH
);
generate_vga : for I in 0 to 3 generate
VGA_R(I) <= VGA_RR;
VGA_G(I) <= VGA_GG;
VGA_B(I) <= VGA_BB;
end generate;
pwm_audio_inst_1 : pwm_audio
generic map(
CLOCK_FREQUENCY => 50000000,
SAMPLE_RATE => 44100,
AUDIO_BITS => 8
) port map (
CLK => CLK,
RST => INTERNAL_RST,
DATA_IN => OUTPUT_AUDIO,
DATA_IN_STB => OUTPUT_AUDIO_STB,
DATA_IN_ACK => OUTPUT_AUDIO_ACK,
AUDIO => AUDIO
);
AUDIO_EN <= '1';
JC(0) <= OUTPUT_AUDIO_STB;
JC(1) <= OUTPUT_AUDIO_ACK;
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
--GPIO interfaces
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--VGA interfave
OUTPUT_VGA => OUTPUT_VGA,
OUTPUT_VGA_ACK => OUTPUT_VGA_ACK,
OUTPUT_VGA_STB => OUTPUT_VGA_STB,
--TRI color LED interface
OUTPUT_LED_R => LED_R,
OUTPUT_LED_R_STB => LED_R_STB,
OUTPUT_LED_R_ACK => LED_R_ACK,
OUTPUT_LED_G => LED_G,
OUTPUT_LED_G_STB => LED_G_STB,
OUTPUT_LED_G_ACK => LED_G_ACK,
OUTPUT_LED_B => LED_B,
OUTPUT_LED_B_STB => LED_B_STB,
OUTPUT_LED_B_ACK => LED_B_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--AUDIO OUT
OUTPUT_AUDIO => OUTPUT_AUDIO,
OUTPUT_AUDIO_STB => OUTPUT_AUDIO_STB,
OUTPUT_AUDIO_ACK => OUTPUT_AUDIO_ACK,
--SEVEN SEGMENT DISPLAY INTERFACE
OUTPUT_SEVEN_SEGMENT_CATHODE => OUTPUT_SEVEN_SEGMENT_CATHODE,
OUTPUT_SEVEN_SEGMENT_CATHODE_STB => OUTPUT_SEVEN_SEGMENT_CATHODE_STB,
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK => OUTPUT_SEVEN_SEGMENT_CATHODE_ACK,
OUTPUT_SEVEN_SEGMENT_ANNODE => OUTPUT_SEVEN_SEGMENT_ANNODE,
OUTPUT_SEVEN_SEGMENT_ANNODE_STB => OUTPUT_SEVEN_SEGMENT_ANNODE_STB,
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK => OUTPUT_SEVEN_SEGMENT_ANNODE_ACK,
--PS2 KEYBOAD INTERFACE
INPUT_PS2_STB => PS2_STB,
INPUT_PS2_ACK => PS2_ACK,
INPUT_PS2 => PS2,
--I2C interface for temperature monitor
INPUT_I2C => OUTPUT_I2C,
INPUT_I2C_STB => OUTPUT_I2C_STB,
INPUT_I2C_ACK => OUTPUT_I2C_ACK,
OUTPUT_I2C => INPUT_I2C,
OUTPUT_I2C_STB => INPUT_I2C_STB,
OUTPUT_I2C_ACK => INPUT_I2C_ACK,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK
);
SERIAL_OUTPUT_INST_1 : SERIAL_OUTPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
I2C_INST_1 : I2C generic map(
CLOCKS_PER_SECOND => 50000000,
SPEED => 10000
) port map (
CLK => CLK,
RST => INTERNAL_RST,
SDA => SDA,
SCL => SCL,
I2C_IN => INPUT_I2C,
I2C_IN_STB => INPUT_I2C_STB,
I2C_IN_ACK =>INPUT_I2C_ACK,
I2C_OUT => OUTPUT_I2C,
I2C_OUT_STB => OUTPUT_I2C_STB,
I2C_OUT_ACK => OUTPUT_I2C_ACK
);
PWM_INST_1 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_R,
DATA_STB => LED_R_STB,
DATA_ACK => LED_R_ACK,
OUT_BIT => LED_R_PWM
);
PWM_INST_2 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_G,
DATA_STB => LED_G_STB,
DATA_ACK => LED_G_ACK,
OUT_BIT => LED_G_PWM
);
PWM_INST_3 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_B,
DATA_STB => LED_B_STB,
DATA_ACK => LED_B_ACK,
OUT_BIT => LED_B_PWM
);
KEYBOARD_INST1 : KEYBOARD port map(
CLK => CLK,
RST => INTERNAL_RST,
DATA_STB => PS2_STB,
DATA_ACK => PS2_ACK,
DATA => PS2,
KD => KD,
KC => KC
);
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= OUTPUT_LEDS(15 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_ANNODE_STB = '1' then
SEVEN_SEGMENT_ANNODE <= not OUTPUT_SEVEN_SEGMENT_ANNODE(7 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_CATHODE_STB = '1' then
SEVEN_SEGMENT_CATHODE <= not OUTPUT_SEVEN_SEGMENT_CATHODE(6 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES <= (others => '0');
INPUT_SWITCHES(15 downto 0) <= GPIO_SWITCHES_D;
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS <= (others => '0');
INPUT_BUTTONS(4 downto 0) <= GPIO_BUTTONS_D;
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 100.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => LOCKED_INTERNAL,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
RST_INV <= not RST;
ETH_CLK <= CLK_OUT1;
VGACLK <= CLK_OUT1;
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/seven_segment/bsp.vhd | 15 | 24719 | -------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+
--- | USER DESIGN |
--- +-------------+
--- | |
--- | <-------< SWITCHES
--- | |
--- | >-------> LEDS
--- | |
--- | <-------< BUTTONS
--- | |
--- | >-------> SEVEN_SEGMENT_CATHODE
--- | |
--- | >-------> SEVEN_SEGMENT_ANNODE
--- | |
--- | | +--------------+
--- | | | UART |
--- | | +--------------+
--- | >-----> >-----> RS232-TX
--- | | | |
--- | | | <-------< RS232-RX
--- +---v-----^---+ +--------------+
--- | |
--- | |
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- | |
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity BSP is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
ETH_CLK : out std_logic;
PHY_RESET_N : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXD : in std_logic_vector(1 downto 0);
TXD : out std_logic_vector(1 downto 0);
TXEN : out std_logic;
JC : inout std_logic_vector(7 downto 0);
--I2C
SDA : inout std_logic;
SCL : inout std_logic;
--PS2 keyboard interface
KD : in std_logic;
KC : in std_logic;
--AUDIO interface
AUDIO : out std_logic;
AUDIO_EN : out std_logic;
--VGA interface
VGA_R : out Std_logic_vector(3 downto 0);
VGA_G : out Std_logic_vector(3 downto 0);
VGA_B : out Std_logic_vector(3 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(15 downto 0);
GPIO_SWITCHES : in std_logic_vector(15 downto 0);
GPIO_BUTTONS : in std_logic_vector(4 downto 0);
--RGB LED
LED_R_PWM : out std_logic;
LED_G_PWM : out std_logic;
LED_B_PWM : out std_logic;
SEVEN_SEGMENT_CATHODE : out std_logic_vector(6 downto 0);
SEVEN_SEGMENT_ANNODE : out std_logic_vector(7 downto 0);
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity BSP;
architecture RTL of BSP is
component rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
PHY_RESET : out std_logic;
--MII IF
TXD : out std_logic_vector(1 downto 0);
TXER : out std_logic;
TXEN : out std_logic;
RXD : in std_logic_vector(1 downto 0);
RXER : in std_logic;
RXDV : in std_logic;
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component rmii_ethernet;
component CHARSVGA is
port (
CLK : in Std_logic;
DATA : in Std_logic_vector(31 downto 0);
DATA_ACK : out Std_logic;
DATA_STB : in Std_logic;
--VGA interface
VGACLK : in Std_logic;
RST : in Std_logic;
R : out Std_logic;
G : out Std_logic;
B : out Std_logic;
HSYNCH : out Std_logic;
VSYNCH : out Std_logic
);
end component CHARSVGA;
component PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end component PWM;
component KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end component KEYBOARD;
component I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end component I2C;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(31 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(31 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(31 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
OUTPUT_VGA : out Std_logic_vector(31 downto 0);
OUTPUT_VGA_ACK : in Std_logic;
OUTPUT_VGA_STB : out Std_logic;
OUTPUT_AUDIO : out std_logic_vector(31 downto 0);
OUTPUT_AUDIO_STB : out std_logic;
OUTPUT_AUDIO_ACK : in std_logic;
OUTPUT_LED_R : out std_logic_vector(31 downto 0);
OUTPUT_LED_R_STB : out std_logic;
OUTPUT_LED_R_ACK : in std_logic;
OUTPUT_LED_G : out std_logic_vector(31 downto 0);
OUTPUT_LED_G_STB : out std_logic;
OUTPUT_LED_G_ACK : in std_logic;
OUTPUT_LED_B : out std_logic_vector(31 downto 0);
OUTPUT_LED_B_STB : out std_logic;
OUTPUT_LED_B_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_CATHODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_ANNODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : in std_logic;
INPUT_PS2 : in std_logic_vector(31 downto 0);
INPUT_PS2_STB : in std_logic;
INPUT_PS2_ACK : out std_logic;
INPUT_I2C : in std_logic_vector(31 downto 0);
INPUT_I2C_STB : in std_logic;
INPUT_I2C_ACK : out std_logic;
OUTPUT_I2C : out std_logic_vector(31 downto 0);
OUTPUT_I2C_STB : out std_logic;
OUTPUT_I2C_ACK : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(31 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
OUTPUT_ETH_TX : out std_logic_vector(31 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(31 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(31 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component SERIAL_OUTPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
component pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44100;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end component pwm_audio;
--chips signals
signal CLK : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal RST_INV : std_logic;
signal INTERNAL_RST : std_logic;
--GPIO signals
signal OUTPUT_LEDS : std_logic_vector(31 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(31 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS : std_logic_vector(31 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(4 downto 0);
--SEVEN SEGMENT DISPLAY STREAM
signal OUTPUT_SEVEN_SEGMENT_CATHODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_CATHODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_ANNODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : std_logic;
--AUDIO
signal OUTPUT_AUDIO : std_logic_vector(31 downto 0);
signal OUTPUT_AUDIO_STB : std_logic;
signal OUTPUT_AUDIO_ACK : std_logic;
--Interface for SVGA
signal VGACLK : std_logic;
signal VGA_RR : std_logic;
signal VGA_GG : std_logic;
signal VGA_BB : std_logic;
signal OUTPUT_VGA : std_logic_vector(31 downto 0);
signal OUTPUT_VGA_ACK : std_logic;
signal OUTPUT_VGA_STB : std_logic;
--PS2 interface for kb/mouse
signal PS2_STB : std_logic;
signal PS2_ACK : std_logic;
signal PS2 : std_logic_vector (31 downto 0);
--I2C interface for temperature monitor
signal INPUT_I2C : std_logic_vector(31 downto 0);
signal INPUT_I2C_STB : std_logic;
signal INPUT_I2C_ACK : std_logic;
signal OUTPUT_I2C : std_logic_vector(31 downto 0);
signal OUTPUT_I2C_STB : std_logic;
signal OUTPUT_I2C_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(31 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--ETH RX STREAM
signal ETH_RX : std_logic_vector(31 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(31 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(31 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--tri color LED signals
signal LED_R : std_logic_vector(31 downto 0);
signal LED_R_STB : std_logic;
signal LED_R_ACK : std_logic;
signal LED_G : std_logic_vector(31 downto 0);
signal LED_G_STB : std_logic;
signal LED_G_ACK : std_logic;
signal LED_B : std_logic_vector(31 downto 0);
signal LED_B_STB : std_logic;
signal LED_B_ACK : std_logic;
begin
ethernet_inst_1 : rmii_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--GMII IF
ETH_CLK => CLK_OUT1,
TXD => TXD,
TXER => open,
TXEN => TXEN,
PHY_RESET => PHY_RESET_N,
RXD => RXD,
RXER => RXER,
RXDV => RXDV,
--RX STREAM
TX => ETH_TX(15 downto 0),
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX(15 downto 0),
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
CHARSVGA_INST_1 : CHARSVGA port map(
CLK => CLK,
DATA => OUTPUT_VGA,
DATA_ACK => OUTPUT_VGA_ACK,
DATA_STB => OUTPUT_VGA_STB,
--VGA interface
VGACLK => VGACLK,
RST => INTERNAL_RST,
R => VGA_RR,
G => VGA_GG,
B => VGA_BB,
HSYNCH => HSYNCH,
VSYNCH => VSYNCH
);
generate_vga : for I in 0 to 3 generate
VGA_R(I) <= VGA_RR;
VGA_G(I) <= VGA_GG;
VGA_B(I) <= VGA_BB;
end generate;
pwm_audio_inst_1 : pwm_audio
generic map(
CLOCK_FREQUENCY => 50000000,
SAMPLE_RATE => 44100,
AUDIO_BITS => 8
) port map (
CLK => CLK,
RST => INTERNAL_RST,
DATA_IN => OUTPUT_AUDIO,
DATA_IN_STB => OUTPUT_AUDIO_STB,
DATA_IN_ACK => OUTPUT_AUDIO_ACK,
AUDIO => AUDIO
);
AUDIO_EN <= '1';
JC(0) <= OUTPUT_AUDIO_STB;
JC(1) <= OUTPUT_AUDIO_ACK;
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
--GPIO interfaces
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--VGA interfave
OUTPUT_VGA => OUTPUT_VGA,
OUTPUT_VGA_ACK => OUTPUT_VGA_ACK,
OUTPUT_VGA_STB => OUTPUT_VGA_STB,
--TRI color LED interface
OUTPUT_LED_R => LED_R,
OUTPUT_LED_R_STB => LED_R_STB,
OUTPUT_LED_R_ACK => LED_R_ACK,
OUTPUT_LED_G => LED_G,
OUTPUT_LED_G_STB => LED_G_STB,
OUTPUT_LED_G_ACK => LED_G_ACK,
OUTPUT_LED_B => LED_B,
OUTPUT_LED_B_STB => LED_B_STB,
OUTPUT_LED_B_ACK => LED_B_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--AUDIO OUT
OUTPUT_AUDIO => OUTPUT_AUDIO,
OUTPUT_AUDIO_STB => OUTPUT_AUDIO_STB,
OUTPUT_AUDIO_ACK => OUTPUT_AUDIO_ACK,
--SEVEN SEGMENT DISPLAY INTERFACE
OUTPUT_SEVEN_SEGMENT_CATHODE => OUTPUT_SEVEN_SEGMENT_CATHODE,
OUTPUT_SEVEN_SEGMENT_CATHODE_STB => OUTPUT_SEVEN_SEGMENT_CATHODE_STB,
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK => OUTPUT_SEVEN_SEGMENT_CATHODE_ACK,
OUTPUT_SEVEN_SEGMENT_ANNODE => OUTPUT_SEVEN_SEGMENT_ANNODE,
OUTPUT_SEVEN_SEGMENT_ANNODE_STB => OUTPUT_SEVEN_SEGMENT_ANNODE_STB,
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK => OUTPUT_SEVEN_SEGMENT_ANNODE_ACK,
--PS2 KEYBOAD INTERFACE
INPUT_PS2_STB => PS2_STB,
INPUT_PS2_ACK => PS2_ACK,
INPUT_PS2 => PS2,
--I2C interface for temperature monitor
INPUT_I2C => OUTPUT_I2C,
INPUT_I2C_STB => OUTPUT_I2C_STB,
INPUT_I2C_ACK => OUTPUT_I2C_ACK,
OUTPUT_I2C => INPUT_I2C,
OUTPUT_I2C_STB => INPUT_I2C_STB,
OUTPUT_I2C_ACK => INPUT_I2C_ACK,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK
);
SERIAL_OUTPUT_INST_1 : SERIAL_OUTPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
I2C_INST_1 : I2C generic map(
CLOCKS_PER_SECOND => 50000000,
SPEED => 10000
) port map (
CLK => CLK,
RST => INTERNAL_RST,
SDA => SDA,
SCL => SCL,
I2C_IN => INPUT_I2C,
I2C_IN_STB => INPUT_I2C_STB,
I2C_IN_ACK =>INPUT_I2C_ACK,
I2C_OUT => OUTPUT_I2C,
I2C_OUT_STB => OUTPUT_I2C_STB,
I2C_OUT_ACK => OUTPUT_I2C_ACK
);
PWM_INST_1 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_R,
DATA_STB => LED_R_STB,
DATA_ACK => LED_R_ACK,
OUT_BIT => LED_R_PWM
);
PWM_INST_2 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_G,
DATA_STB => LED_G_STB,
DATA_ACK => LED_G_ACK,
OUT_BIT => LED_G_PWM
);
PWM_INST_3 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_B,
DATA_STB => LED_B_STB,
DATA_ACK => LED_B_ACK,
OUT_BIT => LED_B_PWM
);
KEYBOARD_INST1 : KEYBOARD port map(
CLK => CLK,
RST => INTERNAL_RST,
DATA_STB => PS2_STB,
DATA_ACK => PS2_ACK,
DATA => PS2,
KD => KD,
KC => KC
);
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= OUTPUT_LEDS(15 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_ANNODE_STB = '1' then
SEVEN_SEGMENT_ANNODE <= not OUTPUT_SEVEN_SEGMENT_ANNODE(7 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_CATHODE_STB = '1' then
SEVEN_SEGMENT_CATHODE <= not OUTPUT_SEVEN_SEGMENT_CATHODE(6 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES <= (others => '0');
INPUT_SWITCHES(15 downto 0) <= GPIO_SWITCHES_D;
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS <= (others => '0');
INPUT_BUTTONS(4 downto 0) <= GPIO_BUTTONS_D;
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 100.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => LOCKED_INTERNAL,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
RST_INV <= not RST;
ETH_CLK <= CLK_OUT1;
VGACLK <= CLK_OUT1;
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | demo/bsp/atlys/bsp.vhd | 1 | 21809 | --------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- BSP for Digilent Atlys
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +---------------------------+
--- | USER DESIGN |
--- +---------------------------+
--- | |
--- | <-------< SWITCHES
--- | |
--- | >-------> LEDS
--- | |
--- | <-------< BUTTONS
--- | |
--- | |
--- | >-------> RS232-TX
--- | |
--- | <-------< RS232-RX
--- | |
--- | >-------> RS232-TX
--- | |
--- +------v-----^--------------+
--- | |
--- +---v-----^--------------+
--- | ETHERNET |
--- | MAC |
--- +------------------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- 125MHZ ----->+ +------> open
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +------------------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity BSP is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
TX : out std_logic;
RX : in std_logic;
PHY_RESET : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXCLK : in std_logic;
RXD : in std_logic_vector(7 downto 0);
TXCLK : in std_logic;
GTXCLK : out std_logic;
TXD : out std_logic_vector(7 downto 0);
TXEN : out std_logic;
TXER : out std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(7 downto 0);
GPIO_SWITCHES : in std_logic_vector(7 downto 0);
GPIO_BUTTONS : in std_logic_vector(3 downto 0);
--PS2 KEYBOARD
KD : in Std_logic;
KC : in Std_logic;
--make these inputs and pull them up
MKD : in Std_logic;
MKC : in Std_logic;
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity BSP;
architecture RTL of BSP is
component gigabit_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_125_MHZ : in std_logic;
--GMII IF
GTXCLK : out std_logic;
TXCLK : in std_logic;
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(7 downto 0);
PHY_RESET : out std_logic;
RXCLK : in std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(7 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component gigabit_ethernet;
component KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end component KEYBOARD;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
EXCEPTION : out std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(31 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
output_eth_tx : out std_logic_vector(31 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
OUTPUT_LEDS : out std_logic_vector(31 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(31 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(31 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
INPUT_TIMER : in std_logic_vector(31 downto 0);
INPUT_TIMER_STB : in std_logic;
INPUT_TIMER_ACK : out std_logic;
INPUT_PS2_STB : in Std_logic;
INPUT_PS2_ACK : out Std_logic;
INPUT_PS2 : in Std_logic_vector (31 downto 0);
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(31 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(31 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
--chips signals
signal CLK : std_logic;
signal RST_INV : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal INTERNAL_RST : std_logic;
signal RXD1 : std_logic;
signal TX_LOCKED : std_logic;
signal INTERNAL_RXCLK : std_logic;
signal INTERNAL_RXCLK_BUF: std_logic;
signal RXCLK_BUF : std_logic;
signal INTERNAL_TXD : std_logic_vector(7 downto 0);
signal INTERNAL_TXEN : std_logic;
signal INTERNAL_TXER : std_logic;
signal OUTPUT_LEDS : std_logic_vector(31 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(31 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
signal INPUT_BUTTONS : std_logic_vector(31 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
signal EXCEPTION : std_logic;
--TIMER
signal TIMER : std_logic_vector(31 downto 0) := X"00000000";
signal INPUT_TIMER : std_logic_vector(31 downto 0);
signal INPUT_TIMER_STB : std_logic;
signal INPUT_TIMER_ACK : std_logic;
--ETH RX STREAM
signal ETH_RX : std_logic_vector(31 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(31 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(31 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(31 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--PS2 DATA
signal PS2_DATA_STB : Std_logic;
signal PS2_DATA_ACK : Std_logic;
signal PS2_DATA : Std_logic_vector (31 downto 0);
begin
gigabit_ethernet_inst_1 : gigabit_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--Ethernet Clock
CLK_125_MHZ => CLK_OUT3,
--GMII IF
GTXCLK => open,
TXCLK => TXCLK,
TXER => INTERNAL_TXER,
TXEN => INTERNAL_TXEN,
TXD => INTERNAL_TXD,
PHY_RESET => PHY_RESET,
RXCLK => INTERNAL_RXCLK,
RXER => RXER,
RXDV => RXDV,
RXD => RXD,
--RX STREAM
TX => ETH_TX(15 downto 0),
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX(15 downto 0),
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
ETH_TX(31 downto 16) <= (others => '0');
ETH_RX(31 downto 16) <= (others => '0');
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
EXCEPTION => EXCEPTION,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--PS2 KEYBOARD
INPUT_PS2_STB => PS2_DATA_STB,
INPUT_PS2_ACK => PS2_DATA_ACK,
INPUT_PS2 => PS2_DATA,
--TIMER
INPUT_TIMER => INPUT_TIMER,
INPUT_TIMER_STB => INPUT_TIMER_STB,
INPUT_TIMER_ACK => INPUT_TIMER_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_OUTPUT_INST_1 : SERIAL_OUTPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(31 downto 8) <= (others => '0');
KEYBOARD_INST_1 : KEYBOARD port map(
CLK => CLK,
RST => INTERNAL_RST,
DATA_STB => PS2_DATA_STB,
DATA_ACK => PS2_DATA_ACK,
DATA => PS2_DATA,
KD => KD,
KC => KC
);
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS(7 downto 0) <= OUTPUT_LEDS(7 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
INPUT_SWITCHES(31 downto 8) <= (others => '0');
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
INPUT_BUTTONS(31 downto 4) <= (others => '0');
TIMER <= std_logic_vector(unsigned(TIMER) + 1);
INPUT_TIMER <= TIMER;
INPUT_TIMER_STB <= '1';
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 200.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => TX_LOCKED,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
RST_INV <= not RST;
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
ODDR2_INST1 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => GTXCLK, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Input buffering
--------------------------------------
BUFG_INST6 : IBUFG
port map
(O => RXCLK_BUF,
I => RXCLK);
-- DCM
--------------------------------------
dcm_sp_inst2: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 14,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => RXCLK_BUF,
CLKFB => INTERNAL_RXCLK,
-- Output clocks
CLK0 => INTERNAL_RXCLK_BUF,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => open,
STATUS => open,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
--------------------------------------
BUFG_INST7 : BUFG
port map
(O => INTERNAL_RXCLK,
I => INTERNAL_RXCLK_BUF);
LOCKED_INTERNAL <= TX_LOCKED;
-- Use ODDRs for clock/data forwarding
--------------------------------------
ODDR2_INST2_GENERATE : for I in 0 to 7 generate
ODDR2_INST2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXD(I), -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate;
ODDR2_INST3 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXEN, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_INST4 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC"
) port map (
Q => TXER, -- 1-bit output data
C0 => CLK_OUT3, -- 1-bit clock input
C1 => CLK_OUT3_N, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => INTERNAL_TXER, -- 1-bit data input (associated with C0)
D1 => INTERNAL_TXER, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
| mit |
HSCD-SS16/HSCD-SS16 | VHDL/FDSx2.vhd | 1 | 775 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FDSx2 IS
PORT(D : IN std_ulogic; -- data input
Q : OUT std_ulogic; -- data output
S : IN std_ulogic; -- preset, high active
C : IN std_ulogic); -- clock, rising edge active
END FDSx2;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
ARCHITECTURE structure OF FDSx2 IS
SIGNAL T: std_ulogic;
BEGIN
ff1: FDS
--synthesis translate_off
generic map (INIT => '1')
--synthesis translate_on
PORT MAP(D => D,
Q => T,
S => S,
C => C);
ff2: FDS
--synthesis translate_off
generic map (INIT => '1')
--synthesis translate_on
PORT MAP(D => T,
Q => Q,
S => S,
C => C);
END structure; | mit |
HSCD-SS16/HSCD-SS16 | Aufgabe1/software/ROM_form.vhd | 6 | 12443 | ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/temperature/serial_in.vhd | 20 | 4970 | --------------------------------------------------------------------------------
---
--- SERIAL INPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Component
---
--------------------------------------------------------------------------------
---
---Serial Input
---============
---
---Read a stream of data from a serial UART
---
---Outputs
-----------
---
--- + OUT1 : Serial data stream
---
---Generics
-----------
---
--- + baud_rate
--- + clock frequency
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end entity SERIAL_INPUT;
architecture RTL of SERIAL_INPUT is
type SERIAL_IN_STATE_TYPE is (IDLE, START, RX0, RX1, RX2, RX3, RX4, RX5, RX6, RX7, STOP, OUTPUT_DATA);
signal STATE : SERIAL_IN_STATE_TYPE;
signal STREAM : std_logic_vector(7 downto 0);
signal STREAM_STB : std_logic;
signal STREAM_ACK : std_logic;
signal COUNT : integer Range 0 to 3;
signal BIT_SPACING : integer Range 0 to 15;
signal INT_SERIAL : std_logic;
signal SERIAL_DEGLITCH : std_logic_Vector(1 downto 0);
constant CLOCK_DIVIDER : unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/(BAUD_RATE * 16), 12);
signal BAUD_COUNT : unsigned(11 downto 0);
signal X16CLK_EN : std_logic;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
SERIAL_DEGLITCH <= SERIAL_DEGLITCH(0) & RX;
if X16CLK_EN = '1' then
if SERIAL_DEGLITCH(1) = '0' then
if COUNT = 0 then
INT_SERIAL <= '0';
else
COUNT <= COUNT - 1;
end if;
else
if COUNT = 3 then
INT_SERIAL <= '1';
else
COUNT <= COUNT + 1;
end if;
end if;
end if;
if RST = '1' then
SERIAL_DEGLITCH <= "11";
end if;
end process;
process
begin
wait until rising_edge(CLK);
if X16CLK_EN = '1' then
if BIT_SPACING = 15 then
BIT_SPACING <= 0;
else
BIT_SPACING <= BIT_SPACING + 1;
end if;
end if;
case STATE is
when IDLE =>
BIT_SPACING <= 0;
if X16CLK_EN = '1' and INT_SERIAL = '0' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' and BIT_SPACING = 7 then
BIT_SPACING <= 0;
STATE <= RX0;
end if;
when RX0 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(0) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX1;
end if;
when RX1 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(1) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX2;
end if;
when RX2 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(2) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX3;
end if;
when RX3 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(3) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX4;
end if;
when RX4 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(4) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX5;
end if;
when RX5 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(5) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX6;
end if;
when RX6 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(6) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX7;
end if;
when RX7 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(7) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= STOP;
end if;
when STOP =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
BIT_SPACING <= 0;
STATE <= OUTPUT_DATA;
OUT1_STB <= '1';
end if;
when OUTPUT_DATA =>
if OUT1_ACK = '1' then
OUT1_STB <= '0';
STATE <= IDLE;
end if;
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
OUT1_STB <= '0';
end if;
end process;
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/knight_rider/svga_timing_gen.vhd | 15 | 5488 | -- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :Generates video timings for a caracter maped video
-- display. Generates sync signals, the address of a
-- character within the screen and the address of a pixel
-- within a character.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
use Ieee.numeric_std.all;
entity VIDEO_TIME_GEN is
port (
CLK : in Std_logic;
RST : in Std_logic;
CHARADDR : out Std_logic_vector(12 downto 0);
PIXROW : out Std_logic_vector(2 downto 0);
PIXCOL : out Std_logic_vector(2 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
BLANK : out Std_logic);
end VIDEO_TIME_GEN;
architecture RTL of VIDEO_TIME_GEN is
signal PIX_ROW_ADDRESS : Unsigned(2 downto 0);
signal PIX_COL_ADDRESS : Unsigned(2 downto 0);
signal ROW_ADDRESS : Unsigned(12 downto 0);
signal COL_ADDRESS : Unsigned(6 downto 0);
signal VTIMER : Unsigned(9 downto 0);
signal HTIMER : Unsigned(10 downto 0);
signal VTIMER_EN : Std_logic;
signal VBLANK : Std_logic;
signal HBLANK : Std_logic;
signal INTVSYNCH : Std_logic;
signal INTHSYNCH : Std_logic;
constant HSYNCHTIME : Integer := 120;
constant HACTIVETIME : Integer := 800;
constant FPORCHTIME : Integer := 64;
constant BPORCHTIME : Integer := 56;
constant VSYNCHTIME : Integer := 6;
constant VACTIVETIME : Integer := 600;
constant VFPORCHTIME : Integer := 35;
constant VBPORCHTIME : Integer := 21;
begin
process
begin
wait until rising_edge(CLK);
if VBLANK = '0' and HBLANK = '0' then
if PIX_COL_ADDRESS = To_unsigned(7, 3) then
PIX_COL_ADDRESS <= (others => '0');
if COL_ADDRESS = To_unsigned(99, 7) then
COL_ADDRESS <= (others => '0');
if PIX_ROW_ADDRESS = To_unsigned(7, 3) then
PIX_ROW_ADDRESS <= (others => '0');
if ROW_ADDRESS = To_unsigned(7400, 13) then
ROW_ADDRESS <= (others => '0');
else
ROW_ADDRESS <= ROW_ADDRESS + 100;
end if;
else
PIX_ROW_ADDRESS <= PIX_ROW_ADDRESS + 1;
end if;
else
COL_ADDRESS <= COL_ADDRESS + 1;
end if;
else
PIX_COL_ADDRESS <= PIX_COL_ADDRESS +1;
end if;
end if;
if RST = '1' then
PIX_COL_ADDRESS <= (others => '0');
PIX_ROW_ADDRESS <= (others => '0');
COL_ADDRESS <= (others => '0');
ROW_ADDRESS <= (others => '0');
end if;
end process;
process
begin
wait until rising_edge(CLK);
if VTIMER_EN = '1' then
VTIMER <= VTIMER + 1;
if VTIMER = To_unsigned(VSYNCHTIME, 10) then
INTVSYNCH <= '1';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME, 10) then
VBLANK <= '0';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME
+ VACTIVETIME, 10) then
VBLANK <= '1';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME
+ VACTIVETIME
+ VBPORCHTIME, 10) then
INTVSYNCH <= '0';
VTIMER <= (others => '0');
end if;
end if;
if RST = '1' then
VTIMER <= (others => '0');
INTVSYNCH <= '0';
VBLANK <= '1';
end if;
end process;
process
begin
wait until Rising_edge(CLK);
HTIMER <= HTIMER + 1;
VTIMER_EN <= '0';
if HTIMER = To_unsigned(HSYNCHTIME, 11) then
INTHSYNCH <= '1';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME, 11) then
HBLANK <= '0';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME
+ HACTIVETIME, 11) then
HBLANK <= '1';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME
+ HACTIVETIME
+ BPORCHTIME, 11) then
INTHSYNCH <= '0';
VTIMER_EN <= '1';
HTIMER <= (others => '0');
end if;
if RST = '1' then
HTIMER <= (others => '0');
INTHSYNCH <= '0';
HBLANK <= '1';
VTIMER_EN <= '1';
end if;
end process;
HSYNCH <= INTHSYNCH;
VSYNCH <= INTVSYNCH;
BLANK <= HBLANK or VBLANK;
CHARADDR <= Std_logic_vector(ROW_ADDRESS + COL_ADDRESS);
PIXCOL <= Std_logic_vector(PIX_COL_ADDRESS);
PIXROW <= Std_logic_vector(PIX_ROW_ADDRESS);
end RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/image_processor/svga_timing_gen.vhd | 15 | 5488 | -- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :Generates video timings for a caracter maped video
-- display. Generates sync signals, the address of a
-- character within the screen and the address of a pixel
-- within a character.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
use Ieee.numeric_std.all;
entity VIDEO_TIME_GEN is
port (
CLK : in Std_logic;
RST : in Std_logic;
CHARADDR : out Std_logic_vector(12 downto 0);
PIXROW : out Std_logic_vector(2 downto 0);
PIXCOL : out Std_logic_vector(2 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
BLANK : out Std_logic);
end VIDEO_TIME_GEN;
architecture RTL of VIDEO_TIME_GEN is
signal PIX_ROW_ADDRESS : Unsigned(2 downto 0);
signal PIX_COL_ADDRESS : Unsigned(2 downto 0);
signal ROW_ADDRESS : Unsigned(12 downto 0);
signal COL_ADDRESS : Unsigned(6 downto 0);
signal VTIMER : Unsigned(9 downto 0);
signal HTIMER : Unsigned(10 downto 0);
signal VTIMER_EN : Std_logic;
signal VBLANK : Std_logic;
signal HBLANK : Std_logic;
signal INTVSYNCH : Std_logic;
signal INTHSYNCH : Std_logic;
constant HSYNCHTIME : Integer := 120;
constant HACTIVETIME : Integer := 800;
constant FPORCHTIME : Integer := 64;
constant BPORCHTIME : Integer := 56;
constant VSYNCHTIME : Integer := 6;
constant VACTIVETIME : Integer := 600;
constant VFPORCHTIME : Integer := 35;
constant VBPORCHTIME : Integer := 21;
begin
process
begin
wait until rising_edge(CLK);
if VBLANK = '0' and HBLANK = '0' then
if PIX_COL_ADDRESS = To_unsigned(7, 3) then
PIX_COL_ADDRESS <= (others => '0');
if COL_ADDRESS = To_unsigned(99, 7) then
COL_ADDRESS <= (others => '0');
if PIX_ROW_ADDRESS = To_unsigned(7, 3) then
PIX_ROW_ADDRESS <= (others => '0');
if ROW_ADDRESS = To_unsigned(7400, 13) then
ROW_ADDRESS <= (others => '0');
else
ROW_ADDRESS <= ROW_ADDRESS + 100;
end if;
else
PIX_ROW_ADDRESS <= PIX_ROW_ADDRESS + 1;
end if;
else
COL_ADDRESS <= COL_ADDRESS + 1;
end if;
else
PIX_COL_ADDRESS <= PIX_COL_ADDRESS +1;
end if;
end if;
if RST = '1' then
PIX_COL_ADDRESS <= (others => '0');
PIX_ROW_ADDRESS <= (others => '0');
COL_ADDRESS <= (others => '0');
ROW_ADDRESS <= (others => '0');
end if;
end process;
process
begin
wait until rising_edge(CLK);
if VTIMER_EN = '1' then
VTIMER <= VTIMER + 1;
if VTIMER = To_unsigned(VSYNCHTIME, 10) then
INTVSYNCH <= '1';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME, 10) then
VBLANK <= '0';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME
+ VACTIVETIME, 10) then
VBLANK <= '1';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME
+ VACTIVETIME
+ VBPORCHTIME, 10) then
INTVSYNCH <= '0';
VTIMER <= (others => '0');
end if;
end if;
if RST = '1' then
VTIMER <= (others => '0');
INTVSYNCH <= '0';
VBLANK <= '1';
end if;
end process;
process
begin
wait until Rising_edge(CLK);
HTIMER <= HTIMER + 1;
VTIMER_EN <= '0';
if HTIMER = To_unsigned(HSYNCHTIME, 11) then
INTHSYNCH <= '1';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME, 11) then
HBLANK <= '0';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME
+ HACTIVETIME, 11) then
HBLANK <= '1';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME
+ HACTIVETIME
+ BPORCHTIME, 11) then
INTHSYNCH <= '0';
VTIMER_EN <= '1';
HTIMER <= (others => '0');
end if;
if RST = '1' then
HTIMER <= (others => '0');
INTHSYNCH <= '0';
HBLANK <= '1';
VTIMER_EN <= '1';
end if;
end process;
HSYNCH <= INTHSYNCH;
VSYNCH <= INTVSYNCH;
BLANK <= HBLANK or VBLANK;
CHARADDR <= Std_logic_vector(ROW_ADDRESS + COL_ADDRESS);
PIXCOL <= Std_logic_vector(PIX_COL_ADDRESS);
PIXROW <= Std_logic_vector(PIX_ROW_ADDRESS);
end RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/svga_hello_world/pwm_audio.vhd | 15 | 1817 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/raw_ethernet/pwm_audio.vhd | 15 | 1817 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/raw_ethernet/rmii_ethernet.vhd | 15 | 25834 | --------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/temperature/svga_core.vhd | 15 | 4875 | -- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :A wishbone compatible VGA core. The core is implemented
-- using BLOCK RAMs to create character maped graphics. An
-- SVGA (800x600 75hz) display is generated consisting of
-- 100x75 characters of 8x8 pixels each. Each character is set
-- to an 8-bit value. At present ASCII glyphs have been
-- generated.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
use Ieee.numeric_std.all;
use WORK.PIXPACKAGE.all;
entity CHARSVGA is
port (
CLK : in Std_logic;
DATA : in Std_logic_vector(31 downto 0);
DATA_ACK : out Std_logic;
DATA_STB : in Std_logic;
--VGA interface
VGACLK : in Std_logic;
RST : in Std_logic;
R : out Std_logic;
G : out Std_logic;
B : out Std_logic;
HSYNCH : out Std_logic;
VSYNCH : out Std_logic
);
end CHARSVGA;
architecture RTL of CHARSVGA is
component VIDEO_TIME_GEN is
port (
CLK : in Std_logic;
RST : in Std_logic;
CHARADDR : out Std_logic_vector(12 downto 0);
PIXROW : out Std_logic_vector(2 downto 0);
PIXCOL : out Std_logic_vector(2 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
BLANK : out Std_logic);
end component;
component BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end component BRAM;
type CHAR_ARRAY_TYPE is array (0 to 7499) of Std_logic_vector(7 downto 0);
shared variable CHARARRAY : CHAR_ARRAY_TYPE;
signal INTHSYNCH, INTVSYNCH : Std_logic;
signal HSYNCH_DEL, VSYNCH_DEL : Std_logic;
signal BLANK, BLANK_DEL, BLANK_DEL_DEL
: Std_logic;
signal PIX, WR : Std_logic;
signal PIXROW, PIXROW_DEL : Std_logic_vector(2 downto 0);
signal PIXCOL, PIXCOL_DEL, PIXCOL_DEL_DEL
: Std_logic_vector(2 downto 0);
signal CHARADDR : Std_logic_vector(12 downto 0);
signal CHAR, PIXELS : Std_logic_vector(7 downto 0);
signal AIN : std_logic_vector(12 downto 0);
signal DIN : std_logic_vector(7 downto 0);
signal WE : std_logic;
begin
TIMEING1: VIDEO_TIME_GEN port map(
CLK => VGACLK,
RST => RST,
CHARADDR => CHARADDR,
PIXROW => PIXROW,
PIXCOL => PIXCOL,
HSYNCH => INTHSYNCH,
VSYNCH => INTVSYNCH,
BLANK => BLANK
);
BRAM_INST_1 : BRAM generic map(
DEPTH => 7500,
WIDTH => 8
) port map(
CLK_IN => CLK,
CLK_OUT => VGACLK,
WE => WE,
DIN => DIN,
AIN => AIN,
DOUT => CHAR,
AOUT => CHARADDR
);
process
begin
wait until rising_edge(CLK);
WE <= '0';
if DATA_STB = '1' then
WE <= '1';
AIN <= DATA(20 downto 8);
DIN <= DATA(7 downto 0);
end if;
end process;
DATA_ACK <= '1';
process
variable PIXADDRESS :Integer;
variable PIXVECTOR : Std_logic_vector(10 downto 0);
begin
wait until rising_edge(VGACLK);
PIXVECTOR := CHAR & PIXROW_DEL;
PIXADDRESS := To_integer(Unsigned(PIXVECTOR));
PIXELS <= PIXARRAY(PIXADDRESS);
end process;
process
begin
wait until rising_edge(VGACLK);
HSYNCH_DEL <= INTHSYNCH;
HSYNCH <= HSYNCH_DEL;
VSYNCH_DEL <= INTVSYNCH;
VSYNCH <= VSYNCH_DEL;
BLANK_DEL <= BLANK;
BLANK_DEL_DEL <= BLANK_DEL;
PIXROW_DEL <= PIXROW;
PIXCOL_DEL <= PIXCOL;
PIXCOL_DEL_DEL <= PIXCOL_DEL;
end process;
PIX <= PIXELS(to_integer(unsigned(PIXCOL_DEL_DEL)));
R <= PIX and not(BLANK_DEL_DEL);
G <= PIX and not(BLANK_DEL_DEL);
B <= PIX and not(BLANK_DEL_DEL);
end RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/tri_color/svga_core.vhd | 15 | 4875 | -- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :A wishbone compatible VGA core. The core is implemented
-- using BLOCK RAMs to create character maped graphics. An
-- SVGA (800x600 75hz) display is generated consisting of
-- 100x75 characters of 8x8 pixels each. Each character is set
-- to an 8-bit value. At present ASCII glyphs have been
-- generated.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
use Ieee.numeric_std.all;
use WORK.PIXPACKAGE.all;
entity CHARSVGA is
port (
CLK : in Std_logic;
DATA : in Std_logic_vector(31 downto 0);
DATA_ACK : out Std_logic;
DATA_STB : in Std_logic;
--VGA interface
VGACLK : in Std_logic;
RST : in Std_logic;
R : out Std_logic;
G : out Std_logic;
B : out Std_logic;
HSYNCH : out Std_logic;
VSYNCH : out Std_logic
);
end CHARSVGA;
architecture RTL of CHARSVGA is
component VIDEO_TIME_GEN is
port (
CLK : in Std_logic;
RST : in Std_logic;
CHARADDR : out Std_logic_vector(12 downto 0);
PIXROW : out Std_logic_vector(2 downto 0);
PIXCOL : out Std_logic_vector(2 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
BLANK : out Std_logic);
end component;
component BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end component BRAM;
type CHAR_ARRAY_TYPE is array (0 to 7499) of Std_logic_vector(7 downto 0);
shared variable CHARARRAY : CHAR_ARRAY_TYPE;
signal INTHSYNCH, INTVSYNCH : Std_logic;
signal HSYNCH_DEL, VSYNCH_DEL : Std_logic;
signal BLANK, BLANK_DEL, BLANK_DEL_DEL
: Std_logic;
signal PIX, WR : Std_logic;
signal PIXROW, PIXROW_DEL : Std_logic_vector(2 downto 0);
signal PIXCOL, PIXCOL_DEL, PIXCOL_DEL_DEL
: Std_logic_vector(2 downto 0);
signal CHARADDR : Std_logic_vector(12 downto 0);
signal CHAR, PIXELS : Std_logic_vector(7 downto 0);
signal AIN : std_logic_vector(12 downto 0);
signal DIN : std_logic_vector(7 downto 0);
signal WE : std_logic;
begin
TIMEING1: VIDEO_TIME_GEN port map(
CLK => VGACLK,
RST => RST,
CHARADDR => CHARADDR,
PIXROW => PIXROW,
PIXCOL => PIXCOL,
HSYNCH => INTHSYNCH,
VSYNCH => INTVSYNCH,
BLANK => BLANK
);
BRAM_INST_1 : BRAM generic map(
DEPTH => 7500,
WIDTH => 8
) port map(
CLK_IN => CLK,
CLK_OUT => VGACLK,
WE => WE,
DIN => DIN,
AIN => AIN,
DOUT => CHAR,
AOUT => CHARADDR
);
process
begin
wait until rising_edge(CLK);
WE <= '0';
if DATA_STB = '1' then
WE <= '1';
AIN <= DATA(20 downto 8);
DIN <= DATA(7 downto 0);
end if;
end process;
DATA_ACK <= '1';
process
variable PIXADDRESS :Integer;
variable PIXVECTOR : Std_logic_vector(10 downto 0);
begin
wait until rising_edge(VGACLK);
PIXVECTOR := CHAR & PIXROW_DEL;
PIXADDRESS := To_integer(Unsigned(PIXVECTOR));
PIXELS <= PIXARRAY(PIXADDRESS);
end process;
process
begin
wait until rising_edge(VGACLK);
HSYNCH_DEL <= INTHSYNCH;
HSYNCH <= HSYNCH_DEL;
VSYNCH_DEL <= INTVSYNCH;
VSYNCH <= VSYNCH_DEL;
BLANK_DEL <= BLANK;
BLANK_DEL_DEL <= BLANK_DEL;
PIXROW_DEL <= PIXROW;
PIXCOL_DEL <= PIXCOL;
PIXCOL_DEL_DEL <= PIXCOL_DEL;
end process;
PIX <= PIXELS(to_integer(unsigned(PIXCOL_DEL_DEL)));
R <= PIX and not(BLANK_DEL_DEL);
G <= PIX and not(BLANK_DEL_DEL);
B <= PIX and not(BLANK_DEL_DEL);
end RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/image_processor/svga_core.vhd | 15 | 4875 | -- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :A wishbone compatible VGA core. The core is implemented
-- using BLOCK RAMs to create character maped graphics. An
-- SVGA (800x600 75hz) display is generated consisting of
-- 100x75 characters of 8x8 pixels each. Each character is set
-- to an 8-bit value. At present ASCII glyphs have been
-- generated.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
use Ieee.numeric_std.all;
use WORK.PIXPACKAGE.all;
entity CHARSVGA is
port (
CLK : in Std_logic;
DATA : in Std_logic_vector(31 downto 0);
DATA_ACK : out Std_logic;
DATA_STB : in Std_logic;
--VGA interface
VGACLK : in Std_logic;
RST : in Std_logic;
R : out Std_logic;
G : out Std_logic;
B : out Std_logic;
HSYNCH : out Std_logic;
VSYNCH : out Std_logic
);
end CHARSVGA;
architecture RTL of CHARSVGA is
component VIDEO_TIME_GEN is
port (
CLK : in Std_logic;
RST : in Std_logic;
CHARADDR : out Std_logic_vector(12 downto 0);
PIXROW : out Std_logic_vector(2 downto 0);
PIXCOL : out Std_logic_vector(2 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
BLANK : out Std_logic);
end component;
component BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end component BRAM;
type CHAR_ARRAY_TYPE is array (0 to 7499) of Std_logic_vector(7 downto 0);
shared variable CHARARRAY : CHAR_ARRAY_TYPE;
signal INTHSYNCH, INTVSYNCH : Std_logic;
signal HSYNCH_DEL, VSYNCH_DEL : Std_logic;
signal BLANK, BLANK_DEL, BLANK_DEL_DEL
: Std_logic;
signal PIX, WR : Std_logic;
signal PIXROW, PIXROW_DEL : Std_logic_vector(2 downto 0);
signal PIXCOL, PIXCOL_DEL, PIXCOL_DEL_DEL
: Std_logic_vector(2 downto 0);
signal CHARADDR : Std_logic_vector(12 downto 0);
signal CHAR, PIXELS : Std_logic_vector(7 downto 0);
signal AIN : std_logic_vector(12 downto 0);
signal DIN : std_logic_vector(7 downto 0);
signal WE : std_logic;
begin
TIMEING1: VIDEO_TIME_GEN port map(
CLK => VGACLK,
RST => RST,
CHARADDR => CHARADDR,
PIXROW => PIXROW,
PIXCOL => PIXCOL,
HSYNCH => INTHSYNCH,
VSYNCH => INTVSYNCH,
BLANK => BLANK
);
BRAM_INST_1 : BRAM generic map(
DEPTH => 7500,
WIDTH => 8
) port map(
CLK_IN => CLK,
CLK_OUT => VGACLK,
WE => WE,
DIN => DIN,
AIN => AIN,
DOUT => CHAR,
AOUT => CHARADDR
);
process
begin
wait until rising_edge(CLK);
WE <= '0';
if DATA_STB = '1' then
WE <= '1';
AIN <= DATA(20 downto 8);
DIN <= DATA(7 downto 0);
end if;
end process;
DATA_ACK <= '1';
process
variable PIXADDRESS :Integer;
variable PIXVECTOR : Std_logic_vector(10 downto 0);
begin
wait until rising_edge(VGACLK);
PIXVECTOR := CHAR & PIXROW_DEL;
PIXADDRESS := To_integer(Unsigned(PIXVECTOR));
PIXELS <= PIXARRAY(PIXADDRESS);
end process;
process
begin
wait until rising_edge(VGACLK);
HSYNCH_DEL <= INTHSYNCH;
HSYNCH <= HSYNCH_DEL;
VSYNCH_DEL <= INTVSYNCH;
VSYNCH <= VSYNCH_DEL;
BLANK_DEL <= BLANK;
BLANK_DEL_DEL <= BLANK_DEL;
PIXROW_DEL <= PIXROW;
PIXCOL_DEL <= PIXCOL;
PIXCOL_DEL_DEL <= PIXCOL_DEL;
end process;
PIX <= PIXELS(to_integer(unsigned(PIXCOL_DEL_DEL)));
R <= PIX and not(BLANK_DEL_DEL);
G <= PIX and not(BLANK_DEL_DEL);
B <= PIX and not(BLANK_DEL_DEL);
end RTL;
| mit |
dawsonjon/Chips-Demo | demo/bsp/atlys/keyboard.vhd | 16 | 2713 | -- ****************************************************************************
-- Filename :keyboard.vhd
-- Project :Wishbone SOC
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2006-04-14
-- ****************************************************************************
-- Description :PS/2 keyboard decoder
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2006-04-14
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end KEYBOARD;
architecture RTL of KEYBOARD is
type STATETYPE is (
INITIALISE,
SEND_DATA,
GET_DATA);
signal STATE : STATETYPE;
signal LAST_KC, INT_KC, INT_KD, KC_DEL, KD_DEL, S_DATA_STB : std_logic;
signal INT_DATA : std_logic_vector(10 downto 0);
signal BIT_COUNT : integer range 0 to 10;
signal TIMEOUT : integer range 0 to 50000000;
begin
process
begin
wait until rising_edge(CLK);
KD_DEL <= KD;
KC_DEL <= KC;
INT_KD <= KD_DEL;
INT_KC <= KC_DEL;
end process;
process
begin
wait until rising_edge(CLK);
LAST_KC <= INT_KC;
case STATE is
when INITIALISE =>
STATE <= GET_DATA;
BIT_COUNT <= 0;
when GET_DATA =>
if TIMEOUT = 0 then
STATE <= INITIALISE;
TIMEOUT <= 50000000;
else
TIMEOUT <= TIMEOUT - 1;
end if;
if LAST_KC = '1' and INT_KC = '0' then
INT_DATA(BIT_COUNT) <= INT_KD;
if BIT_COUNT = 10 then
BIT_COUNT <= 0;
STATE <= SEND_DATA;
else
BIT_COUNT <= BIT_COUNT + 1;
end if;
end if;
when SEND_DATA =>
S_DATA_STB <= '1';
DATA(7 downto 0) <= INT_DATA(8 downto 1);
if S_DATA_STB = '1' and DATA_ACK = '1' then
S_DATA_STB <= '0';
STATE <= GET_DATA;
end if;
end case;
if RST = '1' then
STATE <= INITIALISE;
S_DATA_STB <= '0';
end if;
end process;
DATA_STB <= S_DATA_STB;
end RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/svga_hello_world/keyboard.vhd | 16 | 2713 | -- ****************************************************************************
-- Filename :keyboard.vhd
-- Project :Wishbone SOC
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2006-04-14
-- ****************************************************************************
-- Description :PS/2 keyboard decoder
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2006-04-14
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end KEYBOARD;
architecture RTL of KEYBOARD is
type STATETYPE is (
INITIALISE,
SEND_DATA,
GET_DATA);
signal STATE : STATETYPE;
signal LAST_KC, INT_KC, INT_KD, KC_DEL, KD_DEL, S_DATA_STB : std_logic;
signal INT_DATA : std_logic_vector(10 downto 0);
signal BIT_COUNT : integer range 0 to 10;
signal TIMEOUT : integer range 0 to 50000000;
begin
process
begin
wait until rising_edge(CLK);
KD_DEL <= KD;
KC_DEL <= KC;
INT_KD <= KD_DEL;
INT_KC <= KC_DEL;
end process;
process
begin
wait until rising_edge(CLK);
LAST_KC <= INT_KC;
case STATE is
when INITIALISE =>
STATE <= GET_DATA;
BIT_COUNT <= 0;
when GET_DATA =>
if TIMEOUT = 0 then
STATE <= INITIALISE;
TIMEOUT <= 50000000;
else
TIMEOUT <= TIMEOUT - 1;
end if;
if LAST_KC = '1' and INT_KC = '0' then
INT_DATA(BIT_COUNT) <= INT_KD;
if BIT_COUNT = 10 then
BIT_COUNT <= 0;
STATE <= SEND_DATA;
else
BIT_COUNT <= BIT_COUNT + 1;
end if;
end if;
when SEND_DATA =>
S_DATA_STB <= '1';
DATA(7 downto 0) <= INT_DATA(8 downto 1);
if S_DATA_STB = '1' and DATA_ACK = '1' then
S_DATA_STB <= '0';
STATE <= GET_DATA;
end if;
end case;
if RST = '1' then
STATE <= INITIALISE;
S_DATA_STB <= '0';
end if;
end process;
DATA_STB <= S_DATA_STB;
end RTL;
| mit |
HSCD-SS16/HSCD-SS16 | Aufgabe3/VHDL/insertsort.vhd | 1 | 3241 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY insertsort IS
GENERIC(RSTDEF: std_logic := '1');
PORT(rst: IN std_logic; -- reset, RSTDEF active
clk: IN std_logic; -- clock, rising edge active
-- interface to PicoBlaze
rsel: IN std_logic_vector(7 DOWNTO 0); -- register select
din: IN std_logic_vector(7 DOWNTO 0); -- data input
dout: OUT std_logic_vector(7 DOWNTO 0); -- data output
ena: IN std_logic; -- enable, high active
wre: IN std_logic; -- write strobe, high active
-- interface to RAM block through port B
WEB: OUT std_logic; -- Port B Write Enable Output, high active
ENB: OUT std_logic; -- Port B RAM Enable, high active
ADDRB: OUT std_logic_vector(10 DOWNTO 0); -- Port B 11-bit Address Output
DIB: IN std_logic_vector(7 DOWNTO 0); -- Port B 8-bit Data Input
DOB: OUT std_logic_vector(7 DOWNTO 0)); -- Port B 8-bit Data Output
END insertsort;
ARCHITECTURE behaviour OF insertsort IS
COMPONENT insertcore
GENERIC(RSTDEF: std_logic);
PORT(rst: IN std_logic; -- reset, RSTDEF active
clk: IN std_logic; -- clock, rising edge active
-- handshake signals
strt: IN std_logic; -- start bit, high active
done: OUT std_logic; -- done bit, high active
ptr: IN std_logic_vector(10 DOWNTO 0); -- pointer to vector
len: IN std_logic_vector( 7 DOWNTO 0); -- length of vector
WEB: OUT std_logic; -- Port B Write Enable Output, high active
ENB: OUT std_logic; -- Port B RAM Enable, high active
ADR: OUT std_logic_vector(10 DOWNTO 0); -- Port B 11-bit Address Output
DIB: IN std_logic_vector( 7 DOWNTO 0); -- Port B 8-bit Data Input
DOB: OUT std_logic_vector( 7 DOWNTO 0)); -- Port B 8-bit Data Output
END COMPONENT;
SIGNAL strt: std_logic; -- Startbit
SIGNAL done: std_logic;
SIGNAL ptr: std_logic_vector(10 DOWNTO 0);
SIGNAL len: std_logic_vector( 7 DOWNTO 0);
BEGIN
PROCESS (rst, clk) IS
BEGIN
IF rst=RSTDEF THEN
strt <= '0';
len <= (OTHERS => '0');
ptr <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
IF ena='1' AND wre='1' THEN
CASE rsel(1 DOWNTO 0) IS
WHEN "00" => strt <= din(0);
WHEN "01" => ptr( 7 DOWNTO 0) <= din;
WHEN "10" => ptr(10 DOWNTO 8) <= din(2 DOWNTO 0);
WHEN OTHERS => len <= din;
END CASE;
END IF;
END IF;
END PROCESS;
WITH rsel(1 DOWNTO 0) SELECT
dout <= "0000000" & done WHEN "00",
ptr( 7 DOWNTO 0) WHEN "01",
"00000" & ptr(10 DOWNTO 8) WHEN "10",
len WHEn OTHERS;
u1: insertcore
GENERIC MAP(RSTDEF => RSTDEF)
PORT MAP(rst => rst,
clk => clk,
strt => strt,
done => done,
ptr => ptr,
len => len,
WEB => WEB,
ENB => ENB,
ADR => ADDRB,
DIB => DIB,
DOB => DOB);
END behaviour;
| mit |
onkelthomas/HW_SW_LU_Gr3_2015 | template/template/vhdl/common/synchronizer/sync.vhd | 2 | 782 | library ieee;
use ieee.std_logic_1164.all;
entity sync is
generic
(
SYNC_STAGES : integer range 2 to integer'high;
RESET_VALUE : std_logic
);
port
(
sys_clk : in std_logic;
sys_res_n : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end entity sync;
architecture beh of sync is
signal sync : std_logic_vector(1 to SYNC_STAGES);
begin
process(sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
sync <= (others => RESET_VALUE);
elsif rising_edge(sys_clk) then
sync(1) <= data_in;
for i in 2 to SYNC_STAGES loop
sync(i) <= sync(i-1);
end loop;
end if;
end process;
data_out <= sync(SYNC_STAGES);
end architecture beh;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/hello_world/bram.vhd | 15 | 847 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
| mit |
onkelthomas/HW_SW_LU_Gr3_2015 | template/template/vhdl/textmode_controller/font_rom_beh.vhd | 2 | 2047 | ----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Thomas Polzer --
-- --
-- Create Date: 21.09.2010 --
-- Design Name: DIDELU --
-- Module Name: font_rom_beh --
-- Project Name: DIDELU --
-- Description: Font ROM - Architecture --
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.font_pkg.all;
----------------------------------------------------------------------------------
-- ARCHITECTURE --
----------------------------------------------------------------------------------
architecture beh of font_rom is
begin
--------------------------------------------------------------------
-- PROCESS : SYNC --
--------------------------------------------------------------------
process(vga_clk)
variable address : std_logic_vector(log2c(CHAR_COUNT) + log2c(CHAR_HEIGHT) - 1 downto 0);
begin
if rising_edge(vga_clk) then
address := char & char_height_pixel;
decoded_char <= FONT_TABLE(to_integer(unsigned(address)));
end if;
end process;
end architecture beh;
--- EOF ---
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/keyboard/i2c.vhd | 15 | 8318 | --- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 = SEND_ACK
---
--- RESPONSE
--- ========
---
--- Bits (7:0)
--- ----------
--- (For read byte only) data payload byte
---
--- Bit (0)
--- -------
--- (For write byte only) 1 = NACK, 0 = ACK
---
library ieee;
use ieee.std_logic_1164.all;
entity I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end entity I2C;
architecture RTL of I2C is
constant I2C_DELAY : integer := CLOCKS_PER_SECOND / (2*SPEED);
type STATE_TYPE is (
MAIN_0, MAIN_1, MAIN_2, MAIN_3, GET_BYTE_0, GET_BYTE_1, GET_BYTE_2,
GET_BYTE_3, SEND_BYTE_0, SEND_BYTE_1, SEND_BYTE_2, SEND_BYTE_3, SEND_BYTE_4,
SEND_BIT_0, SEND_BIT_1, SEND_BIT_2, GET_BIT_0, GET_BIT_1, GET_BIT_2,
SEND_START_0, SEND_START_1, SEND_START_2, SEND_START_3, SEND_START_4,
SEND_STOP_0, SEND_STOP_1, SEND_STOP_2, SEND_STOP_3, SEND_STOP_4
);
signal STATE, GET_BYTE_RETURN, SEND_BYTE_RETURN, SEND_BIT_RETURN, GET_BIT_RETURN,
SEND_STOP_RETURN, SEND_START_RETURN : STATE_TYPE;
signal TIMER : integer range 0 to I2C_DELAY;
signal COUNT : integer range 0 to 7;
signal COMMAND : std_logic_vector(31 downto 0);
signal RESPONSE : std_logic_vector(31 downto 0);
signal STARTED : std_logic;
signal S_I2C_IN_ACK : std_logic;
signal S_I2C_OUT_STB : std_logic;
signal SDA_I_D, SDA_I_SYNCH, SDA_I, SDA_O : std_logic;
signal SCL_I_D, SCL_I_SYNCH, SCL_I, SCL_O : std_logic;
signal BIT : std_logic;
begin
SDA <= 'Z' when SDA_O = '1' else '0';
SDA_I <= '1' when SDA /= '0' else '0';
SCL <= 'Z' when SCL_O = '1' else '0';
SCL_I <= '1' when SCL /= '0' else '0';
process
begin
wait until rising_edge(CLK);
SDA_I_D <= SDA_I;
SDA_I_SYNCH <= SDA_I_D;
SCL_I_D <= SCL_I;
SCL_I_SYNCH <= SCL_I_D;
case STATE is
--MAIN SUBROUTINE
when MAIN_0 =>
COUNT <= 7;
TIMER <= I2C_DELAY;
STATE <= MAIN_1;
STARTED <= '0';
when MAIN_1 =>
S_I2C_IN_ACK <= '1';
if I2C_IN_STB = '1' and S_I2C_IN_ACK = '1' then
S_I2C_IN_ACK <= '0';
COMMAND <= I2C_IN;
STATE <= MAIN_2;
end if;
when MAIN_2 =>
if COMMAND(8) = '1' then
RESPONSE <= (others => '0');
STATE <= GET_BYTE_0;
GET_BYTE_RETURN <= MAIN_3;
else
RESPONSE <= (others => '0');
STATE <= SEND_BYTE_0;
SEND_BYTE_RETURN <= MAIN_3;
end if;
when MAIN_3 =>
S_I2C_OUT_STB <= '1';
I2C_OUT <= RESPONSE;
if I2C_OUT_ACK = '1' and S_I2C_OUT_STB = '1' then
S_I2C_OUT_STB <= '0';
STATE <= MAIN_1;
end if;
--GET BYTE SUBROUTINE
when GET_BYTE_0 =>
STATE <= GET_BIT_0;
GET_BIT_RETURN <= GET_BYTE_1;
when GET_BYTE_1 =>
RESPONSE(COUNT) <= BIT;
if COUNT = 0 then
COUNT <= 7;
STATE <= GET_BYTE_2;
else
COUNT <= COUNT - 1;
STATE <= GET_BYTE_0;
end if;
when GET_BYTE_2 =>
--SEND NACK ACK = 0 NACK = 1
BIT <= COMMAND(11);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= GET_BYTE_3;
when GET_BYTE_3 =>
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_STOP_RETURN <= GET_BYTE_RETURN;
else
STATE <= GET_BYTE_RETURN;
end if;
--SEND BYTE SUBROUTINE
when SEND_BYTE_0 =>
if COMMAND(9) = '1' then
STATE <= SEND_START_0;
SEND_START_RETURN <= SEND_BYTE_1;
else
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_1 =>
BIT <= COMMAND(COUNT);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= SEND_BYTE_2;
when SEND_BYTE_2 =>
if COUNT = 0 then
COUNT <= 7;
STATE <= SEND_BYTE_3;
else
COUNT <= COUNT - 1;
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_3 =>
--GET ACK
STATE <= GET_BIT_0;
GET_BIT_RETURN <= SEND_BYTE_4;
when SEND_BYTE_4 =>
--1 = NACK, 0 = ACK
RESPONSE(0) <= BIT;
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_START_RETURN <= SEND_BYTE_RETURN;
else
STATE <= SEND_BYTE_RETURN;
end if;
--SEND START SUBROUTINE
when SEND_START_0 =>
if STARTED = '0' then
STATE <= SEND_START_1;
else
STATE <= SEND_START_4;
end if;
when SEND_START_1 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_2;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_2 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_START_3;
end if;
when SEND_START_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_4 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_RETURN;
SCL_O <= '0';
STARTED <= '1';
else
TIMER <= TIMER - 1;
end if;
--SEND STOP SUBROUTINE
when SEND_STOP_0 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_1 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_STOP_2;
end if;
when SEND_STOP_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_3;
SDA_O <= '1';
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_4 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_RETURN;
STARTED <= '0';
else
TIMER <= TIMER - 1;
end if;
--SEND BIT SUBROUTINE
when SEND_BIT_0 =>
SDA_O <= BIT;
SCL_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_BIT_2;
end if;
when SEND_BIT_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
SCL_O <= '0';
STATE <= SEND_BIT_RETURN;
else
TIMER <= TIMER - 1;
end if;
--GET BIT SUBROUTINE
when GET_BIT_0 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when GET_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= GET_BIT_2;
end if;
when GET_BIT_2 =>
BIT <= SDA_I_SYNCH;
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_RETURN;
SCL_O <= '0';
else
TIMER <= TIMER - 1;
end if;
end case;
if RST = '1' then
STATE <= MAIN_0;
S_I2C_OUT_STB <= '0';
SDA_O <= '1';
SCL_O <= '1';
end if;
end process;
I2C_OUT_STB <= S_I2C_OUT_STB;
I2C_IN_ACK <= S_I2C_IN_ACK;
end RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/enigma_machine/i2c.vhd | 15 | 8318 | --- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 = SEND_ACK
---
--- RESPONSE
--- ========
---
--- Bits (7:0)
--- ----------
--- (For read byte only) data payload byte
---
--- Bit (0)
--- -------
--- (For write byte only) 1 = NACK, 0 = ACK
---
library ieee;
use ieee.std_logic_1164.all;
entity I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end entity I2C;
architecture RTL of I2C is
constant I2C_DELAY : integer := CLOCKS_PER_SECOND / (2*SPEED);
type STATE_TYPE is (
MAIN_0, MAIN_1, MAIN_2, MAIN_3, GET_BYTE_0, GET_BYTE_1, GET_BYTE_2,
GET_BYTE_3, SEND_BYTE_0, SEND_BYTE_1, SEND_BYTE_2, SEND_BYTE_3, SEND_BYTE_4,
SEND_BIT_0, SEND_BIT_1, SEND_BIT_2, GET_BIT_0, GET_BIT_1, GET_BIT_2,
SEND_START_0, SEND_START_1, SEND_START_2, SEND_START_3, SEND_START_4,
SEND_STOP_0, SEND_STOP_1, SEND_STOP_2, SEND_STOP_3, SEND_STOP_4
);
signal STATE, GET_BYTE_RETURN, SEND_BYTE_RETURN, SEND_BIT_RETURN, GET_BIT_RETURN,
SEND_STOP_RETURN, SEND_START_RETURN : STATE_TYPE;
signal TIMER : integer range 0 to I2C_DELAY;
signal COUNT : integer range 0 to 7;
signal COMMAND : std_logic_vector(31 downto 0);
signal RESPONSE : std_logic_vector(31 downto 0);
signal STARTED : std_logic;
signal S_I2C_IN_ACK : std_logic;
signal S_I2C_OUT_STB : std_logic;
signal SDA_I_D, SDA_I_SYNCH, SDA_I, SDA_O : std_logic;
signal SCL_I_D, SCL_I_SYNCH, SCL_I, SCL_O : std_logic;
signal BIT : std_logic;
begin
SDA <= 'Z' when SDA_O = '1' else '0';
SDA_I <= '1' when SDA /= '0' else '0';
SCL <= 'Z' when SCL_O = '1' else '0';
SCL_I <= '1' when SCL /= '0' else '0';
process
begin
wait until rising_edge(CLK);
SDA_I_D <= SDA_I;
SDA_I_SYNCH <= SDA_I_D;
SCL_I_D <= SCL_I;
SCL_I_SYNCH <= SCL_I_D;
case STATE is
--MAIN SUBROUTINE
when MAIN_0 =>
COUNT <= 7;
TIMER <= I2C_DELAY;
STATE <= MAIN_1;
STARTED <= '0';
when MAIN_1 =>
S_I2C_IN_ACK <= '1';
if I2C_IN_STB = '1' and S_I2C_IN_ACK = '1' then
S_I2C_IN_ACK <= '0';
COMMAND <= I2C_IN;
STATE <= MAIN_2;
end if;
when MAIN_2 =>
if COMMAND(8) = '1' then
RESPONSE <= (others => '0');
STATE <= GET_BYTE_0;
GET_BYTE_RETURN <= MAIN_3;
else
RESPONSE <= (others => '0');
STATE <= SEND_BYTE_0;
SEND_BYTE_RETURN <= MAIN_3;
end if;
when MAIN_3 =>
S_I2C_OUT_STB <= '1';
I2C_OUT <= RESPONSE;
if I2C_OUT_ACK = '1' and S_I2C_OUT_STB = '1' then
S_I2C_OUT_STB <= '0';
STATE <= MAIN_1;
end if;
--GET BYTE SUBROUTINE
when GET_BYTE_0 =>
STATE <= GET_BIT_0;
GET_BIT_RETURN <= GET_BYTE_1;
when GET_BYTE_1 =>
RESPONSE(COUNT) <= BIT;
if COUNT = 0 then
COUNT <= 7;
STATE <= GET_BYTE_2;
else
COUNT <= COUNT - 1;
STATE <= GET_BYTE_0;
end if;
when GET_BYTE_2 =>
--SEND NACK ACK = 0 NACK = 1
BIT <= COMMAND(11);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= GET_BYTE_3;
when GET_BYTE_3 =>
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_STOP_RETURN <= GET_BYTE_RETURN;
else
STATE <= GET_BYTE_RETURN;
end if;
--SEND BYTE SUBROUTINE
when SEND_BYTE_0 =>
if COMMAND(9) = '1' then
STATE <= SEND_START_0;
SEND_START_RETURN <= SEND_BYTE_1;
else
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_1 =>
BIT <= COMMAND(COUNT);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= SEND_BYTE_2;
when SEND_BYTE_2 =>
if COUNT = 0 then
COUNT <= 7;
STATE <= SEND_BYTE_3;
else
COUNT <= COUNT - 1;
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_3 =>
--GET ACK
STATE <= GET_BIT_0;
GET_BIT_RETURN <= SEND_BYTE_4;
when SEND_BYTE_4 =>
--1 = NACK, 0 = ACK
RESPONSE(0) <= BIT;
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_START_RETURN <= SEND_BYTE_RETURN;
else
STATE <= SEND_BYTE_RETURN;
end if;
--SEND START SUBROUTINE
when SEND_START_0 =>
if STARTED = '0' then
STATE <= SEND_START_1;
else
STATE <= SEND_START_4;
end if;
when SEND_START_1 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_2;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_2 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_START_3;
end if;
when SEND_START_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_4 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_RETURN;
SCL_O <= '0';
STARTED <= '1';
else
TIMER <= TIMER - 1;
end if;
--SEND STOP SUBROUTINE
when SEND_STOP_0 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_1 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_STOP_2;
end if;
when SEND_STOP_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_3;
SDA_O <= '1';
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_4 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_RETURN;
STARTED <= '0';
else
TIMER <= TIMER - 1;
end if;
--SEND BIT SUBROUTINE
when SEND_BIT_0 =>
SDA_O <= BIT;
SCL_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_BIT_2;
end if;
when SEND_BIT_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
SCL_O <= '0';
STATE <= SEND_BIT_RETURN;
else
TIMER <= TIMER - 1;
end if;
--GET BIT SUBROUTINE
when GET_BIT_0 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when GET_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= GET_BIT_2;
end if;
when GET_BIT_2 =>
BIT <= SDA_I_SYNCH;
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_RETURN;
SCL_O <= '0';
else
TIMER <= TIMER - 1;
end if;
end case;
if RST = '1' then
STATE <= MAIN_0;
S_I2C_OUT_STB <= '0';
SDA_O <= '1';
SCL_O <= '1';
end if;
end process;
I2C_OUT_STB <= S_I2C_OUT_STB;
I2C_IN_ACK <= S_I2C_IN_ACK;
end RTL;
| mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/benchmark/i2c.vhd | 15 | 8318 | --- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 = SEND_ACK
---
--- RESPONSE
--- ========
---
--- Bits (7:0)
--- ----------
--- (For read byte only) data payload byte
---
--- Bit (0)
--- -------
--- (For write byte only) 1 = NACK, 0 = ACK
---
library ieee;
use ieee.std_logic_1164.all;
entity I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end entity I2C;
architecture RTL of I2C is
constant I2C_DELAY : integer := CLOCKS_PER_SECOND / (2*SPEED);
type STATE_TYPE is (
MAIN_0, MAIN_1, MAIN_2, MAIN_3, GET_BYTE_0, GET_BYTE_1, GET_BYTE_2,
GET_BYTE_3, SEND_BYTE_0, SEND_BYTE_1, SEND_BYTE_2, SEND_BYTE_3, SEND_BYTE_4,
SEND_BIT_0, SEND_BIT_1, SEND_BIT_2, GET_BIT_0, GET_BIT_1, GET_BIT_2,
SEND_START_0, SEND_START_1, SEND_START_2, SEND_START_3, SEND_START_4,
SEND_STOP_0, SEND_STOP_1, SEND_STOP_2, SEND_STOP_3, SEND_STOP_4
);
signal STATE, GET_BYTE_RETURN, SEND_BYTE_RETURN, SEND_BIT_RETURN, GET_BIT_RETURN,
SEND_STOP_RETURN, SEND_START_RETURN : STATE_TYPE;
signal TIMER : integer range 0 to I2C_DELAY;
signal COUNT : integer range 0 to 7;
signal COMMAND : std_logic_vector(31 downto 0);
signal RESPONSE : std_logic_vector(31 downto 0);
signal STARTED : std_logic;
signal S_I2C_IN_ACK : std_logic;
signal S_I2C_OUT_STB : std_logic;
signal SDA_I_D, SDA_I_SYNCH, SDA_I, SDA_O : std_logic;
signal SCL_I_D, SCL_I_SYNCH, SCL_I, SCL_O : std_logic;
signal BIT : std_logic;
begin
SDA <= 'Z' when SDA_O = '1' else '0';
SDA_I <= '1' when SDA /= '0' else '0';
SCL <= 'Z' when SCL_O = '1' else '0';
SCL_I <= '1' when SCL /= '0' else '0';
process
begin
wait until rising_edge(CLK);
SDA_I_D <= SDA_I;
SDA_I_SYNCH <= SDA_I_D;
SCL_I_D <= SCL_I;
SCL_I_SYNCH <= SCL_I_D;
case STATE is
--MAIN SUBROUTINE
when MAIN_0 =>
COUNT <= 7;
TIMER <= I2C_DELAY;
STATE <= MAIN_1;
STARTED <= '0';
when MAIN_1 =>
S_I2C_IN_ACK <= '1';
if I2C_IN_STB = '1' and S_I2C_IN_ACK = '1' then
S_I2C_IN_ACK <= '0';
COMMAND <= I2C_IN;
STATE <= MAIN_2;
end if;
when MAIN_2 =>
if COMMAND(8) = '1' then
RESPONSE <= (others => '0');
STATE <= GET_BYTE_0;
GET_BYTE_RETURN <= MAIN_3;
else
RESPONSE <= (others => '0');
STATE <= SEND_BYTE_0;
SEND_BYTE_RETURN <= MAIN_3;
end if;
when MAIN_3 =>
S_I2C_OUT_STB <= '1';
I2C_OUT <= RESPONSE;
if I2C_OUT_ACK = '1' and S_I2C_OUT_STB = '1' then
S_I2C_OUT_STB <= '0';
STATE <= MAIN_1;
end if;
--GET BYTE SUBROUTINE
when GET_BYTE_0 =>
STATE <= GET_BIT_0;
GET_BIT_RETURN <= GET_BYTE_1;
when GET_BYTE_1 =>
RESPONSE(COUNT) <= BIT;
if COUNT = 0 then
COUNT <= 7;
STATE <= GET_BYTE_2;
else
COUNT <= COUNT - 1;
STATE <= GET_BYTE_0;
end if;
when GET_BYTE_2 =>
--SEND NACK ACK = 0 NACK = 1
BIT <= COMMAND(11);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= GET_BYTE_3;
when GET_BYTE_3 =>
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_STOP_RETURN <= GET_BYTE_RETURN;
else
STATE <= GET_BYTE_RETURN;
end if;
--SEND BYTE SUBROUTINE
when SEND_BYTE_0 =>
if COMMAND(9) = '1' then
STATE <= SEND_START_0;
SEND_START_RETURN <= SEND_BYTE_1;
else
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_1 =>
BIT <= COMMAND(COUNT);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= SEND_BYTE_2;
when SEND_BYTE_2 =>
if COUNT = 0 then
COUNT <= 7;
STATE <= SEND_BYTE_3;
else
COUNT <= COUNT - 1;
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_3 =>
--GET ACK
STATE <= GET_BIT_0;
GET_BIT_RETURN <= SEND_BYTE_4;
when SEND_BYTE_4 =>
--1 = NACK, 0 = ACK
RESPONSE(0) <= BIT;
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_START_RETURN <= SEND_BYTE_RETURN;
else
STATE <= SEND_BYTE_RETURN;
end if;
--SEND START SUBROUTINE
when SEND_START_0 =>
if STARTED = '0' then
STATE <= SEND_START_1;
else
STATE <= SEND_START_4;
end if;
when SEND_START_1 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_2;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_2 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_START_3;
end if;
when SEND_START_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_4 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_RETURN;
SCL_O <= '0';
STARTED <= '1';
else
TIMER <= TIMER - 1;
end if;
--SEND STOP SUBROUTINE
when SEND_STOP_0 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_1 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_STOP_2;
end if;
when SEND_STOP_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_3;
SDA_O <= '1';
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_4 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_RETURN;
STARTED <= '0';
else
TIMER <= TIMER - 1;
end if;
--SEND BIT SUBROUTINE
when SEND_BIT_0 =>
SDA_O <= BIT;
SCL_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_BIT_2;
end if;
when SEND_BIT_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
SCL_O <= '0';
STATE <= SEND_BIT_RETURN;
else
TIMER <= TIMER - 1;
end if;
--GET BIT SUBROUTINE
when GET_BIT_0 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when GET_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= GET_BIT_2;
end if;
when GET_BIT_2 =>
BIT <= SDA_I_SYNCH;
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_RETURN;
SCL_O <= '0';
else
TIMER <= TIMER - 1;
end if;
end case;
if RST = '1' then
STATE <= MAIN_0;
S_I2C_OUT_STB <= '0';
SDA_O <= '1';
SCL_O <= '1';
end if;
end process;
I2C_OUT_STB <= S_I2C_OUT_STB;
I2C_IN_ACK <= S_I2C_IN_ACK;
end RTL;
| mit |
mikeek/FIT | INC/proj_1/fsm.vhd | 1 | 8367 | -- fsm.vhd: Finite State Machine
-- Author(s):
--
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity fsm is
port(
CLK : in std_logic;
RESET : in std_logic;
-- Input signals
KEY : in std_logic_vector(15 downto 0);
CNT_OF : in std_logic;
-- Output signals
FSM_CNT_CE : out std_logic;
FSM_MX_MEM : out std_logic;
FSM_MX_LCD : out std_logic;
FSM_LCD_WR : out std_logic;
FSM_LCD_CLR : out std_logic
);
end entity fsm;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of fsm is
type t_state is (IDLE, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7_1, ST7_2, ST8_1,
ST8_2, ST9_1, ST9_2, ST10_1, ST10_2, ST11, SKIP, PRINT_OK, PRINT_WRONG);
signal present_state, next_state : t_state;
begin
-- -------------------------------------------------------
sync_logic : process(RESET, CLK)
begin
if (RESET = '1') then
present_state <= ST0;
elsif (CLK'event AND CLK = '1') then
present_state <= next_state;
end if;
end process sync_logic;
-- -------------------------------------------------------
next_state_logic : process(present_state, KEY, CNT_OF)
begin
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when IDLE =>
next_state <= IDLE;
if (KEY(15) = '1') then
next_state <= ST0;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST0 =>
next_state <= ST0;
if (KEY(1) = '1') then
next_state <= ST1;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST1 =>
next_state <= ST1;
if (KEY(4) = '1') then
next_state <= ST2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST2 =>
next_state <= ST2;
if (KEY(6) = '1') then
next_state <= ST3;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST3 =>
next_state <= ST3;
if (KEY(0) = '1') then
next_state <= ST4;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST4 =>
next_state <= ST4;
if (KEY(6) = '1') then
next_state <= ST5;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST5 =>
next_state <= ST5;
if (KEY(4) = '1') then
next_state <= ST6;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST6 =>
next_state <= ST6;
if (KEY(7) = '1') then
next_state <= ST7_1;
elsif (KEY(8) = '1') then
next_state <= ST7_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST7_1 =>
next_state <= ST7_1;
if (KEY(2) = '1') then
next_state <= ST8_1;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST7_2 =>
next_state <= ST7_2;
if (KEY(9) = '1') then
next_state <= ST8_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST8_1 =>
next_state <= ST8_1;
if (KEY(6) = '1') then
next_state <= ST9_1;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST8_2 =>
next_state <= ST8_2;
if (KEY(4) = '1') then
next_state <= ST9_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST9_1 =>
next_state <= ST9_1;
if (KEY(2) = '1') then
next_state <= ST10_1;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST9_2 =>
next_state <= ST9_2;
if (KEY(6) = '1') then
next_state <= ST10_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST10_1 =>
next_state <= ST10_1;
if (KEY(4) = '1') then
next_state <= ST11;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST10_2 =>
next_state <= ST10_2;
if (KEY(15) = '1') then
next_state <= PRINT_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST11 =>
next_state <= ST11;
if (KEY(15) = '1') then
next_state <= PRINT_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when SKIP =>
next_state <= SKIP;
if (KEY(15) = '1') then
next_state <= PRINT_WRONG;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_OK =>
next_state <= PRINT_OK;
if (CNT_OF = '1') then
next_state <= IDLE;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_WRONG =>
next_state <= PRINT_WRONG;
if (CNT_OF = '1') then
next_state <= IDLE;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
next_state <= IDLE;
end case;
end process next_state_logic;
-- -------------------------------------------------------
output_logic : process(present_state, KEY)
begin
FSM_CNT_CE <= '0';
FSM_MX_MEM <= '0';
FSM_MX_LCD <= '0';
FSM_LCD_WR <= '0';
FSM_LCD_CLR <= '0';
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_OK =>
FSM_MX_MEM <= '1';
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_WRONG =>
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
-- - - - - - - - - - - - - - - - - - - - - - -
when IDLE =>
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
if (KEY(14 downto 0) /= "000000000000000") then
FSM_LCD_WR <= '1';
end if;
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
end case;
end process output_logic;
end architecture behavioral;
| mit |
16-bit-risc/16-bit-risc | vhdl/dcd3x8.vhd | 4 | 539 | -- DCD3x8
-- 3-to-8 decoder
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity dcd3x8 is
port(en : in std_logic_vector(2 downto 0);
de : out std_logic_vector(7 downto 0)
);
end dcd3x8;
architecture logic of dcd3x8 is
begin
with en select de <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
end logic; | mit |
glenux/contrib-linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
16-bit-risc/16-bit-risc | vhdl/sgnext6x16.vhd | 4 | 341 | library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN;
end Logic; | mit |
0a-/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
agural/AVR-Processor | src/AVR/opcodes.vhd | 1 | 7639 | -----------------------------------------------------------------------------
--
-- AVR opcode package
--
-- This package defines opcode constants for the complete AVR instruction
-- set. Not all variants of the AVR implement all instructions.
--
-- Revision History
-- 4/27/98 Glen George initial revision
-- 4/14/00 Glen George updated comments
-- 4/22/02 Glen George added new instructions
-- 4/22/02 Glen George updated comments
-- 5/16/02 Glen George fixed LPM instruction constant
--
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package opcodes is
subtype opcode_word is std_logic_vector(15 downto 0);
-- ALU opcodes
constant OpADC : opcode_word := "000111----------"; -- ADC Rd, Rr
constant OpADD : opcode_word := "000011----------"; -- ADD Rd, Rr
constant OpADIW : opcode_word := "10010110--------"; -- ADIW Rdl, K
constant OpAND : opcode_word := "001000----------"; -- AND Rd, Rr
constant OpANDI : opcode_word := "0111------------"; -- ANDI Rd, K
constant OpASR : opcode_word := "1001010-----0101"; -- ASR Rd
constant OpBCLR : opcode_word := "100101001---1000"; -- BCLR s
constant OpBLD : opcode_word := "1111100-----0---"; -- BLD Rd, b
constant OpBSET : opcode_word := "100101000---1000"; -- BSET s
constant OpBST : opcode_word := "1111101---------"; -- BST Rr, b
constant OpCOM : opcode_word := "1001010-----0000"; -- COM Rd
constant OpCP : opcode_word := "000101----------"; -- CP Rd, Rr
constant OpCPC : opcode_word := "000001----------"; -- CPC Rd, Rr
constant OpCPI : opcode_word := "0011------------"; -- CPI Rd, K
constant OpDEC : opcode_word := "1001010-----1010"; -- DEC Rd
constant OpEOR : opcode_word := "001001----------"; -- EOR Rd, Rr
constant OpFMUL : opcode_word := "000000110---1---"; -- FMUL Rd, Rr
constant OpFMULS : opcode_word := "000000111---0---"; -- FMULS Rd, Rr
constant OpFMULSU : opcode_word := "000000111---1---"; -- FMULSU Rd, Rr
constant OpINC : opcode_word := "1001010-----0011"; -- INC Rd
constant OpLSR : opcode_word := "1001010-----0110"; -- LSR Rd
constant OpMUL : opcode_word := "100111----------"; -- MUL Rd, Rr
constant OpMULS : opcode_word := "00000010--------"; -- MULS Rd, Rr
constant OpMULSU : opcode_word := "000000110---0---"; -- MULSU Rd, Rr
constant OpNEG : opcode_word := "1001010-----0001"; -- NEG Rd
constant OpOR : opcode_word := "001010----------"; -- OR Rd, Rr
constant OpORI : opcode_word := "0110------------"; -- ORI Rd, K
constant OpROR : opcode_word := "1001010-----0111"; -- ROR Rd
constant OpSBC : opcode_word := "000010----------"; -- SBC Rd, Rr
constant OpSBCI : opcode_word := "0100------------"; -- SBCI Rd, K
constant OpSBIW : opcode_word := "10010111--------"; -- SBIW Rdl, K
constant OpSUB : opcode_word := "000110----------"; -- SUB Rd, Rr
constant OpSUBI : opcode_word := "0101------------"; -- SUBI Rd, K
constant OpSWAP : opcode_word := "1001010-----0010"; -- SWAP Rd
-- Load and Store Opcodes
constant OpELPM : opcode_word := "1001010111011000"; -- ELPM
constant OpELPMZ : opcode_word := "1001000-----0110"; -- ELPM Rd, Z
constant OpELPMZI : opcode_word := "1001000-----0111"; -- ELPM Rd, Z+
constant OpLDX : opcode_word := "1001000-----1100"; -- LD Rd, X
constant OpLDXI : opcode_word := "1001000-----1101"; -- LD Rd, X+
constant OpLDXD : opcode_word := "1001000-----1110"; -- LD Rd, -X
constant OpLDYI : opcode_word := "1001000-----1001"; -- LD Rd, Y+
constant OpLDYD : opcode_word := "1001000-----1010"; -- LD Rd, -Y
constant OpLDDY : opcode_word := "10-0--0-----1---"; -- LDD Rd, Y + q
constant OpLDZI : opcode_word := "1001000-----0001"; -- LD Rd, Z+
constant OpLDZD : opcode_word := "1001000-----0010"; -- LD Rd, -Z
constant OpLDDZ : opcode_word := "10-0--0-----0---"; -- LDD Rd, Z + q
constant OpLDI : opcode_word := "1110------------"; -- LDI Rd, k
constant OpLDS : opcode_word := "1001000-----0000"; -- LDS Rd, m
constant OpLPM : opcode_word := "1001010111001000"; -- LPM
constant OpLPMZ : opcode_word := "1001000-----0100"; -- LPM Rd, Z
constant OpLPMZI : opcode_word := "1001000-----0101"; -- LPM Rd, Z+
constant OpMOV : opcode_word := "001011----------"; -- MOV Rd, Rr
constant OpMOVW : opcode_word := "00000001--------"; -- MOVW Rd, Rr
constant OpSPM : opcode_word := "1001010111101000"; -- SPM
constant OpSTX : opcode_word := "1001001-----1100"; -- ST X, Rr
constant OpSTXI : opcode_word := "1001001-----1101"; -- ST X+, Rr
constant OpSTXD : opcode_word := "1001001-----1110"; -- ST -X, Rr
constant OpSTYI : opcode_word := "1001001-----1001"; -- ST Y+, Rr
constant OpSTYD : opcode_word := "1001001-----1010"; -- ST -Y, Rr
constant OpSTDY : opcode_word := "10-0--1-----1---"; -- STD Y + q, Rr
constant OpSTZI : opcode_word := "1001001-----0001"; -- ST Z+, Rr
constant OpSTZD : opcode_word := "1001001-----0010"; -- ST -Z, Rr
constant OpSTDZ : opcode_word := "10-0--1-----0---"; -- STD Z + q, Rr
constant OpSTS : opcode_word := "1001001-----0000"; -- STS m, Rr
-- Push and Pop Opcodes
constant OpPOP : opcode_word := "1001000-----1111"; -- POP Rd
constant OpPUSH : opcode_word := "1001001-----1111"; -- PUSH Rd
-- Unconditional Branches
constant OpEICALL : opcode_word := "1001010100011001"; -- EICALL
constant OpEIJMP : opcode_word := "1001010000011001"; -- EIJMP
constant OpJMP : opcode_word := "1001010-----110-"; -- JMP a
constant OpRJMP : opcode_word := "1100------------"; -- RJMP j
constant OpIJMP : opcode_word := "10010100----1001"; -- IJMP
constant OpCALL : opcode_word := "1001010-----111-"; -- CALL a
constant OpRCALL : opcode_word := "1101------------"; -- RCALL j
constant OpICALL : opcode_word := "10010101----1001"; -- ICALL
constant OpRET : opcode_word := "100101010--01000"; -- RET
constant OpRETI : opcode_word := "100101010--11000"; -- RETI
-- Conditional Branches
constant OpBRBC : opcode_word := "111101----------"; -- BRBC s, r
constant OpBRBS : opcode_word := "111100----------"; -- BRBS s, r
-- Skip Instructions
constant OpCPSE : opcode_word := "000100----------"; -- CPSE Rd, Rr
constant OpSBIC : opcode_word := "10011001--------"; -- SBIC p, b
constant OpSBIS : opcode_word := "10011011--------"; -- SBIS p, b
constant OpSBRC : opcode_word := "1111110---------"; -- SBRC Rr, b
constant OpSBRS : opcode_word := "1111111---------"; -- SBRS Rr, b
-- I/O Instructions
constant OpCBI : opcode_word := "10011000--------"; -- CBI p, b
constant OpIN : opcode_word := "10110-----------"; -- IN Rd, p
constant OpOUT : opcode_word := "10111-----------"; -- OUT p, Rr
constant OpSBI : opcode_word := "10011010--------"; -- SBI p, b
-- Miscellaneous Instructions
constant OpBREAK : opcode_word := "1001010110011000"; -- BREAK
constant OpNOP : opcode_word := "0000000000000000"; -- NOP
constant OpSLP : opcode_word := "10010101100-1000"; -- SLEEP
constant OpWDR : opcode_word := "10010101101-1000"; -- WDR
end package;
| mit |
AndyMcC0/UVVM_All | uvvm_vvc_framework/src/ti_data_stack_pkg.vhd | 3 | 8489 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_data_queue_pkg.all;
package ti_data_stack_pkg is
shared variable shared_data_stack : t_data_queue;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the stack.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the stack
--
-- - Returns: The index of the initiated stack (natural).
-- Returns 0 on error.
--
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the stack
--
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_stack_push
------------------------------------------
-- This procedure puts data into a stack with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the stack size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_stack_pop
------------------------------------------
-- This function returns the data from the stack
-- and removes the returned data from the stack.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the stack size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_flush
------------------------------------------
-- This procedure empties the stack given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be flushed.
--
procedure uvvm_stack_flush(
buffer_index : natural
);
------------------------------------------
-- uvvm_stack_peek
------------------------------------------
-- This function returns the data from the stack
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the stack size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The number of elements occupying the stack (natural).
--
--
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_stack_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the stack (natural).
--
--
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural;
end package ti_data_stack_pkg;
package body ti_data_stack_pkg is
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_stack.init_queue(buffer_size_in_bits, "UVVM_STACK");
end function;
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_stack.init_queue(buffer_index, buffer_size_in_bits, "UVVM_STACK");
end procedure;
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
) is
begin
shared_data_stack.push_back(buffer_index,data);
end procedure;
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.pop_back(buffer_index, entry_size_in_bits);
end function;
procedure uvvm_stack_flush(
buffer_index : natural
) is
begin
shared_data_stack.flush(buffer_index);
end procedure;
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.peek_back(buffer_index, entry_size_in_bits);
end function;
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_stack.get_count(buffer_idx);
end function;
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural is
begin
return shared_data_stack.get_queue_count_max(buffer_index);
end function;
end package body ti_data_stack_pkg;
| mit |
AndyMcC0/UVVM_All | bitvis_irqc/src/irqc.vhd | 3 | 3092 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc is
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- CPU interface
cs : in std_logic;
addr: in unsigned(2 downto 0);
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout: out std_logic_vector(7 downto 0) := (others => '0');
-- Interrupt related signals
irq_source : in std_logic_vector(C_NUM_SOURCES-1 downto 0);
irq2cpu : out std_logic;
irq2cpu_ack : in std_logic
);
end irqc;
architecture rtl of irqc is
-- PIF-core interface
signal p2c : t_p2c; --
signal c2p : t_c2p; --
begin
i_irqc_pif: entity work.irqc_pif
port map (
arst => arst, --
clk => clk, --
-- CPU interface
cs => cs, --
addr => addr, --
wr => wr, --
rd => rd, --
din => din, --
dout => dout, --
--
p2c => p2c, --
c2p => c2p --
);
i_irqc_core: entity work.irqc_core
port map (
clk => clk, --
arst => arst, --
-- PIF-core interface
p2c => p2c, --
c2p => c2p, --
-- Interrupt related signals
irq_source => irq_source, --
irq2cpu => irq2cpu, --
irq2cpu_ack => irq2cpu_ack --
);
end rtl;
| mit |
AndyMcC0/UVVM_All | uvvm_util/src/types_pkg.vhd | 1 | 6000 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
constant C_NUM_SYNC_FLAGS : positive := 10;
constant C_FLAG_NAME_LENGTH : positive := 20;
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NO_ALERT, NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, KEEP_LEADING_0, SKIP_LEADING_0); -- AS_IS is deprecated and will be removed. Use KEEP_LEADING_0.
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE); -- Deprecated, will be removed.
type t_format_spaces is (KEEP_LEADING_SPACE, SKIP_LEADING_SPACE);
type t_truncate_string is (ALLOW_TRUNCATE, DISALLOW_TRUNCATE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_log_destination is (CONSOLE_AND_LOG, CONSOLE_ONLY, LOG_ONLY);
type t_match_strictness is (MATCH_STD, MATCH_EXACT);
type t_alert_counters is array (NOTE to t_alert_level'right) of natural;
type t_alert_attention is array (NOTE to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (NOTE to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_action_when_transfer_is_done is (RELEASE_LINE_AFTER_TRANSFER, HOLD_LINE_AFTER_TRANSFER);
type t_active_level is (ACTIVE_HIGH, ACTIVE_LOW);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-- type for await_unblock_flag whether the method should set the flag back to blocked or not
type t_flag_returning is (KEEP_UNBLOCKED, RETURN_TO_BLOCK); -- value after unblock
type t_sync_flag_record is record
flag_name : string(1 to C_FLAG_NAME_LENGTH);
is_active : boolean;
end record;
constant C_SYNC_FLAG_DEFAULT : t_sync_flag_record := (
flag_name => (others => ' '),
is_active => true
);
type t_sync_flag_record_array is array (1 to C_NUM_SYNC_FLAGS) of t_sync_flag_record;
type t_uvvm_status is record
no_unexpected_simulation_warnings_or_worse : natural range 0 to 1;
no_unexpected_simulation_errors_or_worse : natural range 0 to 1;
end record t_uvvm_status;
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
type t_hierarchy_alert_level_print is array (NOTE to t_alert_level'right) of boolean;
constant C_HIERARCHY_NODE_NAME_LENGTH : natural := 20;
type t_hierarchy_node is
record
name : string(1 to C_HIERARCHY_NODE_NAME_LENGTH);
alert_attention_counters : t_alert_attention_counters;
alert_stop_limit : t_alert_counters;
alert_level_print : t_hierarchy_alert_level_print;
end record;
type t_bfm_delay_type is (NO_DELAY, TIME_FINISH2START, TIME_START2START);
type t_inter_bfm_delay is
record
delay_type : t_bfm_delay_type;
delay_in_time : time;
inter_bfm_delay_violation_severity : t_alert_level;
end record;
end package types_pkg;
package body types_pkg is
end package body types_pkg;
| mit |
AndyMcC0/UVVM_All | bitvis_irqc/tb/irqc_tb.vhd | 1 | 20216 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_tb
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.env.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
use work.irqc_pif_pkg.all;
-- Test case entity
entity irqc_tb is
end entity;
-- Test case architecture
architecture func of irqc_tb is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- CPU interface
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
-- Interrupt related signals
signal irq_source : std_logic_vector(C_NUM_SOURCES-1 downto 0) := (others => '0');
signal irq2cpu : std_logic := '0';
signal irq2cpu_ack : std_logic := '0';
signal clock_ena : boolean := false;
constant C_CLK_PERIOD : time := 10 ns;
procedure clock_gen(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time
) is
variable v_first_half_clk_period : time := C_CLK_PERIOD / 2;
begin
loop
if not clock_ena then
wait until clock_ena;
end if;
wait for v_first_half_clk_period;
clock_signal <= not clock_signal;
wait for (clock_period - v_first_half_clk_period);
clock_signal <= not clock_signal;
end loop;
end;
subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0);
-- Trim (cut) a given vector to fit the number of irq sources (i.e. pot. reduce width)
function trim(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return t_irq_source is
variable v_result : std_logic_vector(source'length-1 downto 0) := source;
begin
return v_result(num_bits-1 downto 0);
end;
-- Fit a given vector to the number of irq sources by masking with zeros above irq width
function fit(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return std_logic_vector is
variable v_result : std_logic_vector(source'length-1 downto 0) := (others => '0');
variable v_source : std_logic_vector(source'length-1 downto 0) := source;
begin
v_result(num_bits-1 downto 0) := v_source(num_bits-1 downto 0);
return v_result;
end;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_irqc: entity work.irqc
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
din => sbi_if.wdata,
dout => sbi_if.rdata,
-- Interrupt related signals
irq_source => irq_source,
irq2cpu => irq2cpu,
irq2cpu_ack => irq2cpu_ack
);
sbi_if.ready <= '1'; -- always ready in the same clock cycle.
-- Set upt clock generator
clock_gen(clk, clock_ena, 10 ns);
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
procedure pulse(
signal target : inout std_logic;
signal clock_signal : in std_logic;
constant num_periods : in natural;
constant msg : in string
) is
begin
if num_periods > 0 then
wait until falling_edge(clock_signal);
target <= '1';
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else
target <= '1';
wait for 0 ns; -- Delta cycle only
end if;
target <= '0';
log(ID_SEQUENCER_SUB, msg, C_SCOPE);
end;
procedure pulse(
signal target : inout std_logic_vector;
constant pulse_value : in std_logic_vector;
signal clock_signal : in std_logic;
constant num_periods : in natural;
constant msg : in string) is
begin
if num_periods > 0 then
wait until falling_edge(clock_signal);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else
target <= pulse_value;
wait for 0 ns; -- Delta cycle only
end if;
target(target'range) <= (others => '0');
log(ID_SEQUENCER_SUB, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & ". " & add_msg_delimiter(msg), C_SCOPE);
end;
-- Log overloads for simplification
procedure log(
msg : string) is
begin
log(ID_SEQUENCER, msg, C_SCOPE);
end;
-- Overloads for PIF BFMs for SBI (Simple Bus Interface)
procedure write(
constant addr_value : in natural;
constant data_value : in std_logic_vector;
constant msg : in string) is
begin
sbi_write(to_unsigned(addr_value, sbi_if.addr'length), data_value, msg,
clk, sbi_if, C_SCOPE);
end;
procedure check(
constant addr_value : in natural;
constant data_exp : in std_logic_vector;
constant alert_level : in t_alert_level;
constant msg : in string) is
begin
sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, msg,
clk, sbi_if, alert_level, C_SCOPE);
end;
procedure set_inputs_passive(
dummy : t_void) is
begin
sbi_if.cs <= '0';
sbi_if.addr <= (others => '0');
sbi_if.wena <= '0';
sbi_if.rena <= '0';
sbi_if.wdata <= (others => '0');
irq_source <= (others => '0');
irq2cpu_ack <= '0';
log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE);
end;
variable v_time_stamp : time := 0 ns;
variable v_irq_mask : std_logic_vector(7 downto 0);
variable v_irq_mask_inv : std_logic_vector(7 downto 0);
begin
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
enable_log_msg(ALL_MESSAGES);
--disable_log_msg(ALL_MESSAGES);
--enable_log_msg(ID_LOG_HDR);
log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE);
------------------------------------------------------------
set_inputs_passive(VOID);
clock_ena <= true; -- to start clock generator
pulse(arst, clk, 10, "Pulsed reset-signal - active for 10T");
v_time_stamp := now; -- time from which irq2cpu should be stable off until triggered
check_value(C_NUM_SOURCES > 0, FAILURE, "Must be at least 1 interrupt source", C_SCOPE);
check_value(C_NUM_SOURCES <= 8, TB_WARNING, "This TB is only checking IRQC with up to 8 interrupt sources", C_SCOPE);
log(ID_LOG_HDR, "Check defaults on output ports", C_SCOPE);
------------------------------------------------------------
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must be default inactive", C_SCOPE);
check_value(sbi_if.rdata, x"00", ERROR, "Register data bus output must be default passive");
log(ID_LOG_HDR, "Check register defaults and access (write + read)", C_SCOPE);
------------------------------------------------------------
log("\nChecking Register defaults");
check(C_ADDR_IRR, x"00", ERROR, "IRR default");
check(C_ADDR_IER, x"00", ERROR, "IER default");
check(C_ADDR_IPR, x"00", ERROR, "IPR default");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED default");
log("\nChecking Register Write/Read");
write(C_ADDR_IER, fit(x"55"), "IER");
check(C_ADDR_IER, fit(x"55"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"AA"), "IER");
check(C_ADDR_IER, fit(x"AA"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"00"), "IER");
check(C_ADDR_IER, fit(x"00"), ERROR, "IER pure readback");
log(ID_LOG_HDR, "Check register trigger/clear mechanism", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ITR, fit(x"AA"), "ITR : Set interrupts");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"71"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"8E"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"85"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"0A"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"5F"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"5F"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR");
log(ID_LOG_HDR, "Check interrupt sources, IER, IPR and irq2cpu", C_SCOPE);
------------------------------------------------------------
log("\nChecking interrupts and IRR");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
pulse(irq_source, trim(x"AA"), clk, 1, "Pulse irq_source 1T");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR after irq pulses");
pulse(irq_source, trim(x"01"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
pulse(irq_source, trim(x"A1"), clk, 1, "Repeat same interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
pulse(irq_source, trim(x"54"), clk, 1, "Add remaining interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"AA"), "ICR : Clear half the interrupts");
pulse(irq_source, trim(x"A0"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"F5"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR after clearing all");
log("\nChecking IER, IPR and irq2cpu");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"55"), "IER : Enable some interrupts");
write(C_ADDR_ITR, fit(x"AA"), "ITR : Trigger non-enable interrupts");
check(C_ADDR_IPR, fit(x"00"), ERROR, "IPR should not be active");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED should not be active");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Enable main interrupt to CPU");
check(C_ADDR_IRQ2CPU_ALLOWED, x"01", ERROR, "IRQ2CPU_ALLOWED should now be active");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
pulse(irq_source, trim(x"01"), clk, 1, "Add a single enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR should now be active");
check(C_ADDR_IPR, fit(x"01"), ERROR, "IPR should now be active");
log("\nMore details checked in the autonomy section below");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU must still be active", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
log(ID_LOG_HDR, "Check autonomy for all interrupts", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Disable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
for i in 0 to C_NUM_SOURCES-1 loop
log(" ");
log("- Checking irq_source(" & to_string(i) & ") and all corresponding functionality");
log("- - Check interrupt activation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable inactive irq2cpu
v_irq_mask := (others => '0');
v_irq_mask(i) := '1';
v_irq_mask_inv := (others => '1');
v_irq_mask_inv(i) := '0';
write(C_ADDR_IER, v_irq_mask, "IER : Enable selected interrupt");
pulse(irq_source, trim(v_irq_mask_inv), clk, 1, "Pulse all non-enabled interrupts");
write(C_ADDR_ITR, v_irq_mask_inv, "ITR : Trigger all non-enabled interrupts");
check(C_ADDR_IRR, fit(v_irq_mask_inv), ERROR, "IRR not yet triggered");
check(C_ADDR_IPR, x"00", ERROR, "IPR not yet triggered");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
pulse(irq_source, trim(v_irq_mask), clk, 1, "Pulse the enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "All IRR triggered");
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR triggered for selected");
log("\n- - Check interrupt deactivation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable active irq2cpu
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Enable all interrupts");
write(C_ADDR_IER, v_irq_mask, "IER : Disable non-selected interrupts");
pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
write(C_ADDR_ITR, x"FF", "ITR : Trigger all interrupts");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
write(C_ADDR_IER, v_irq_mask_inv, "IER : Enable all interrupts but disable selected");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU still active", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR still active for all");
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected immediately", C_SCOPE);
write(C_ADDR_IER, v_irq_mask, "IER : Re-enable selected interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected immediately", C_SCOPE);
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR still active for selected");
write(C_ADDR_ICR, v_irq_mask, "ICR : Clear selected interrupt");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must go inactive", C_SCOPE);
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
write(C_ADDR_IER, x"00", "IER : Disable all interrupts");
end loop;
report_alert_counters(INTERMEDIATE); -- Report intermediate counters
log(ID_LOG_HDR, "Check irq acknowledge and re-enable", C_SCOPE);
------------------------------------------------------------
log("- Activate interrupt");
write(C_ADDR_ITR, v_irq_mask, "ICR : Set single upper interrupt");
write(C_ADDR_IER, v_irq_mask, "IER : Enable single upper interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
log("\n- Try potential malfunction");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
log("\n- Acknowledge and deactivate interrupt");
pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable inactive irq2cpu
log("\n- Test for potential malfunction");
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Disable interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_ITR, x"FF", "ICR : Trigger all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='0')", C_SCOPE);
log("\n- Re-/de-activation");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Deactivate interrupt to CPU");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
log(ID_LOG_HDR, "Check Reset", C_SCOPE);
------------------------------------------------------------
log("- Activate all interrupts");
write(C_ADDR_ITR, x"FF", "ICR : Set all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
pulse(arst, clk, 1, "Pulse reset");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation", C_SCOPE);
check(C_ADDR_IER, x"00", ERROR, "IER all inactive");
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
| mit |
AndyMcC0/UVVM_All | uvvm_util/src/hierarchy_linked_list_pkg.vhd | 1 | 41905 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
package hierarchy_linked_list_pkg is
type t_hierarchy_linked_list is protected
procedure initialize_hierarchy(
base_scope : string := "";
stop_limit : t_alert_counters);
procedure insert_in_tree(
hierarchy_node : t_hierarchy_node;
parent_scope : string);
impure function is_empty
return boolean;
impure function is_not_empty
return boolean;
impure function get_size
return natural;
procedure clear;
impure function contains_scope(
scope : string
) return boolean;
procedure contains_scope_return_data(
scope : string;
variable result : out boolean;
variable hierarchy_node : out t_hierarchy_node);
procedure alert (
constant scope : string;
constant alert_level : t_alert_level;
constant attention : t_attention := REGARD;
constant msg : string := "");
procedure increment_expected_alerts(
scope : string;
alert_level: t_alert_level;
amount : natural := 1);
procedure set_expected_alerts(
scope : string;
alert_level: t_alert_level;
expected_alerts : natural);
impure function get_expected_alerts(
scope : string;
alert_level : t_alert_level
) return natural;
procedure increment_stop_limit(
scope : string;
alert_level: t_alert_level;
amount : natural := 1);
procedure set_stop_limit(
scope : string;
alert_level: t_alert_level;
stop_limit : natural);
impure function get_stop_limit(
scope : string;
alert_level : t_alert_level
) return natural;
procedure print_hierarchical_log(
order : t_order := FINAL);
impure function get_parent_scope(
scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH))
return string;
procedure change_parent(
scope : string;
parent_scope : string
);
procedure set_top_level_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_top_level_stop_limit(
alert_level : t_alert_level
) return natural;
procedure enable_alert_level(
scope : string;
alert_level : t_alert_level
);
procedure disable_alert_level(
scope : string;
alert_level : t_alert_level
);
procedure enable_all_alert_levels(
scope : string
);
procedure disable_all_alert_levels(
scope : string
);
end protected;
end package hierarchy_linked_list_pkg;
package body hierarchy_linked_list_pkg is
type t_hierarchy_linked_list is protected body
-- Types and control variables for the linked list implementation
type t_element;
type t_element_ptr is access t_element;
type t_element is
record
first_child : t_element_ptr; -- Pointer to the first element in a linked list of children
next_sibling : t_element_ptr; -- Pointer to the next element in a linked list of siblings
prev_sibling : t_element_ptr; -- Pointer to the previous element in a linked list of siblings
parent : t_element_ptr;
element_data : t_hierarchy_node;
hierarchy_level : natural; -- How far down the tree this node is. Used when printing summary.
end record;
variable vr_top_element_ptr : t_element_ptr;
variable vr_num_elements_in_tree : natural := 0;
variable vr_max_hierarchy_level : natural := 0;
-- Initialization variables
variable vr_has_been_initialized : boolean := false;
variable vr_base_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH);
procedure initialize_hierarchy(
base_scope : string := "";
stop_limit : t_alert_counters) is
variable v_base_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(base_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
variable base_node : t_hierarchy_node := (v_base_scope,
(others => (others => 0)),
stop_limit,
(others => true));
begin
if not vr_has_been_initialized then
-- Generate a base node.
insert_in_tree(base_node, "");
vr_base_scope := v_base_scope;
vr_has_been_initialized := true;
end if;
end procedure;
procedure search_for_scope(
variable starting_node : in t_element_ptr;
scope : string;
variable result_node : out t_element_ptr;
variable found : out boolean
) is
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
begin
found := false;
-- is this the correct scope?
if starting_node.element_data.name = v_scope then
result_node := starting_node;
found := true;
return;
end if;
-- Go downwards in the tree.
if starting_node.first_child /= null then
search_for_scope(starting_node.first_child, v_scope, v_current_ptr, v_found);
if v_found then
result_node := v_current_ptr;
found := true;
return;
end if;
end if;
-- Go sideways in the tree
if starting_node.next_sibling /= null then
search_for_scope(starting_node.next_sibling, v_scope, v_current_ptr, v_found);
if v_found then
result_node := v_current_ptr;
found := true;
return;
end if;
end if;
-- No candidate found
end procedure;
procedure search_for_scope(
variable starting_node : in t_element_ptr;
hierarchy_node : t_hierarchy_node;
variable result_node : out t_element_ptr;
variable found : out boolean
) is
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
found := false;
-- is this the correct node?
if starting_node.element_data = hierarchy_node then
result_node := starting_node;
found := true;
return;
end if;
-- Go downwards in the tree.
if starting_node.first_child /= null then
search_for_scope(starting_node.first_child, hierarchy_node, v_current_ptr, v_found);
if v_found then
result_node := v_current_ptr;
found := true;
return;
end if;
end if;
-- Go sideways in the tree
if starting_node.next_sibling /= null then
search_for_scope(starting_node.next_sibling, hierarchy_node, v_current_ptr, v_found);
if v_found then
result_node := v_current_ptr;
found := true;
return;
end if;
end if;
-- No candidate found
end procedure;
--
-- insert_in_tree
--
-- Insert a new element in the tree.
--
--
procedure insert_in_tree(
hierarchy_node : t_hierarchy_node;
parent_scope : string
) is
variable v_parent_ptr : t_element_ptr;
variable v_child_ptr : t_element_ptr;
variable v_found : boolean := false;
variable v_parent_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(parent_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
variable v_hierarchy_node : t_hierarchy_node;
begin
v_hierarchy_node := hierarchy_node;
v_hierarchy_node.name := justify(hierarchy_node.name, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
-- Set read and write pointers when appending element to existing list
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
-- Search for the parent.
search_for_scope(vr_top_element_ptr, v_parent_scope, v_parent_ptr, v_found);
if v_found then
-- Parent found.
if v_parent_ptr.first_child = null then
-- Parent has no children. This node shall be the first child.
v_parent_ptr.first_child := new t_element'(first_child => null, next_sibling => null, prev_sibling => null, parent => v_parent_ptr, element_data => v_hierarchy_node, hierarchy_level => v_parent_ptr.hierarchy_level + 1);
else
-- Parent has at least one child. This node shall be a sibling of the other child(ren).
v_child_ptr := v_parent_ptr.first_child;
-- Find last current sibling
while v_child_ptr.next_sibling /= null loop
v_child_ptr := v_child_ptr.next_sibling;
end loop;
-- Insert this node as a new sibling
v_child_ptr.next_sibling := new t_element'(first_child => null, next_sibling => null, prev_sibling => v_child_ptr, parent => v_parent_ptr, element_data => v_hierarchy_node, hierarchy_level => v_parent_ptr.hierarchy_level + 1);
end if;
-- Update max hierarchy level
if vr_max_hierarchy_level < v_parent_ptr.hierarchy_level + 1 then
vr_max_hierarchy_level := v_parent_ptr.hierarchy_level + 1;
end if;
else
-- parent not in tree
-- Register to top level
insert_in_tree(v_hierarchy_node, C_BASE_HIERARCHY_LEVEL);
end if;
else
-- tree is empty, create top element in tree
vr_top_element_ptr := new t_element'(first_child => null, next_sibling => null, prev_sibling => null, parent => null, element_data => v_hierarchy_node, hierarchy_level => 0);
end if;
-- Increment number of elements
vr_num_elements_in_tree := vr_num_elements_in_tree + 1;
end procedure;
procedure clear_recursively(variable element_ptr : inout t_element_ptr) is
begin
assert element_ptr /= null report "Attempting to clear null pointer!" severity error ;
if element_ptr.first_child /= null then
clear_recursively(element_ptr.first_child);
end if;
if element_ptr.next_sibling /= null then
clear_recursively(element_ptr.next_sibling);
end if;
DEALLOCATE(element_ptr);
end procedure;
procedure clear is
variable v_to_be_deallocated_ptr : t_element_ptr;
begin
-- Deallocate all nodes in the tree
if vr_top_element_ptr /= null then
clear_recursively(vr_top_element_ptr);
end if;
-- Reset the linked_list counter
vr_num_elements_in_tree := 0;
-- Reset the hierarchy variables
vr_max_hierarchy_level := 0;
vr_has_been_initialized := false;
end procedure;
impure function is_empty
return boolean is
begin
if vr_num_elements_in_tree = 0 then
return true;
else
return false;
end if;
end function;
impure function is_not_empty
return boolean is
begin
return not is_empty;
end function;
impure function get_size
return natural is
begin
return vr_num_elements_in_tree;
end function;
impure function contains_scope(
scope : string
) return boolean is
variable v_candidate_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
search_for_scope(vr_top_element_ptr, scope, v_candidate_ptr, v_found);
return v_found;
end function;
procedure contains_scope_return_data(
scope : string;
variable result : out boolean;
variable hierarchy_node : out t_hierarchy_node
) is
variable v_candidate_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
search_for_scope(vr_top_element_ptr, scope, v_candidate_ptr, v_found);
result := v_found;
if v_found then
hierarchy_node := v_candidate_ptr.element_data;
end if;
end procedure;
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all);
writeline(file_handle, v_line);
end procedure tee;
procedure alert (
constant scope : string;
constant alert_level : t_alert_level;
constant attention : t_attention := REGARD;
constant msg : string := ""
) is
variable v_starting_node_ptr : t_element_ptr;
variable v_current_ptr : t_element_ptr;
variable v_found : boolean := false;
variable v_is_in_tree : boolean := false;
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
variable v_hierarchy : line; -- stores the hierarchy propagation
variable v_parent_node : t_hierarchy_node;
variable v_do_print : boolean := false; -- Enable/disable print of alert message
begin
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
-- search for tree node that contains scope
search_for_scope(vr_top_element_ptr, scope, v_starting_node_ptr, v_found);
if not v_found then
-- If the scope was not found, register automatically
-- with the default base level scope as parent.
-- Stop limit set to default.
insert_in_tree((scope, (others => (others => 0)), (others => 0), (others => true)), justify(C_BASE_HIERARCHY_LEVEL, LEFT, C_HIERARCHY_NODE_NAME_LENGTH));
-- Search again to get ptr
search_for_scope(vr_top_element_ptr, scope, v_starting_node_ptr, v_found);
end if;
v_current_ptr := v_starting_node_ptr;
assert v_found
report "Node not found!"
severity failure;
write(v_msg, replace_backslash_n_with_lf(msg));
-- Only print of alert level print is enabled for this alert level
-- for the node where the alert is called.
if attention /= IGNORE then
if v_current_ptr.element_data.alert_level_print(alert_level) = true then
v_do_print := true;
end if;
-- Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
end if;
-- 4. Propagate alert and build alert message
while v_current_ptr /= null loop
if attention = IGNORE then
-- Increment alert counter for this node at alert attention IGNORE
v_current_ptr.element_data.alert_attention_counters(alert_level)(IGNORE) := v_current_ptr.element_data.alert_attention_counters(alert_level)(IGNORE)+ 1;
else
-- Increment alert counter for this node at alert attention REGARD
v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) := v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)+ 1;
write(v_hierarchy, v_current_ptr.element_data.name(1 to pos_of_rightmost_non_whitespace(v_current_ptr.element_data.name)));
if v_current_ptr.parent /= null then
write(v_hierarchy, string'(" -> "));
end if;
-- Exit loop if stop-limit is reached for number of this alert
if (v_current_ptr.element_data.alert_stop_limit(alert_level) /= 0) and
(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= v_current_ptr.element_data.alert_stop_limit(alert_level)) then
exit;
end if;
end if;
v_current_ptr := v_current_ptr.parent;
end loop;
if v_current_ptr = null then -- Nothing went wrong in the previous loop
v_current_ptr := v_starting_node_ptr;
end if;
if attention /= IGNORE then
-- 3. Write body of alert message
-- Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & v_hierarchy.all & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & v_hierarchy.all &
" " & v_msg.all);
end if;
end if;
if v_msg /= null then
deallocate(v_msg);
end if;
-- Write stop message if stop-limit is reached for number of this alert
if (v_current_ptr.element_data.alert_stop_limit(alert_level) /= 0) and
(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= v_current_ptr.element_data.alert_stop_limit(alert_level)) then
v_do_print := true; -- If the alert limit has been reached, print alert message anyway.
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & " " &
to_upper(to_string(alert_level)) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
if v_hierarchy /= null then
deallocate(v_hierarchy);
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
if v_do_print then -- Only print if alert level print enabled for this alert level.
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
else
if v_info /= null then
deallocate(v_info);
end if;
end if;
-- Stop simulation if stop-limit is reached for number of this alert
if v_current_ptr /= null then
if (v_current_ptr.element_data.alert_stop_limit(alert_level) /= 0) then
if (v_current_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= v_current_ptr.element_data.alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end if;
end procedure;
procedure increment_expected_alerts(
scope : string;
alert_level: t_alert_level;
amount : natural := 1
) is
variable v_current_ptr : t_element_ptr;
variable v_new_expected_alerts : natural;
variable v_found : boolean := false;
begin
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
-- search for tree node that contains scope
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
assert v_found report "Scope not found!" severity warning;
if v_found then
-- Increment expected alerts for this node.
v_new_expected_alerts := v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) + amount;
v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := v_new_expected_alerts;
-- Change pointer to parent element
v_current_ptr := v_current_ptr.parent;
-- Propagate expected alerts
while v_current_ptr /= null loop
if v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) < v_new_expected_alerts then
v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := v_new_expected_alerts;
end if;
v_current_ptr := v_current_ptr.parent;
end loop;
end if;
end if;
end procedure;
procedure set_expected_alerts(
scope : string;
alert_level: t_alert_level;
expected_alerts : natural
) is
variable v_current_ptr : t_element_ptr;
variable v_found : boolean := false;
variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
begin
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
-- search for tree node that contains scope
search_for_scope(vr_top_element_ptr, v_scope, v_current_ptr, v_found);
assert v_found report "Scope not found!" severity warning;
if v_found then
-- Set stop limit for this node
v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := expected_alerts;
-- Change pointer to parent element
v_current_ptr := v_current_ptr.parent;
-- Propagate stop limit
while v_current_ptr /= null loop
if v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) < expected_alerts then
v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) := expected_alerts;
end if;
v_current_ptr := v_current_ptr.parent;
end loop;
end if;
end if;
end procedure;
impure function get_expected_alerts(
scope : string;
alert_level : t_alert_level
) return natural is
variable v_current_ptr : t_element_ptr;
variable v_found : boolean := false;
variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
begin
search_for_scope(vr_top_element_ptr, v_scope, v_current_ptr, v_found);
if v_found then
return v_current_ptr.element_data.alert_attention_counters(alert_level)(EXPECT);
else
return 0;
end if;
end function;
procedure increment_stop_limit(
scope : string;
alert_level: t_alert_level;
amount : natural := 1
) is
variable v_current_ptr : t_element_ptr;
variable v_new_stop_limit : natural;
variable v_found : boolean := false;
begin
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
-- search for tree node that contains scope
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
assert v_found report "Scope not found!" severity warning;
if v_found then
-- Increment stop limit for this node.
v_new_stop_limit := v_current_ptr.element_data.alert_stop_limit(alert_level) + amount;
v_current_ptr.element_data.alert_stop_limit(alert_level) := v_new_stop_limit;
-- Change pointer to parent element
v_current_ptr := v_current_ptr.parent;
-- Propagate stop limit
while v_current_ptr /= null loop
if v_current_ptr.element_data.alert_stop_limit(alert_level) < v_new_stop_limit then
v_current_ptr.element_data.alert_stop_limit(alert_level) := v_new_stop_limit;
end if;
v_current_ptr := v_current_ptr.parent;
end loop;
end if;
end if;
end procedure;
procedure set_stop_limit(
scope : string;
alert_level: t_alert_level;
stop_limit : natural
) is
variable v_current_ptr : t_element_ptr;
variable v_found : boolean := false;
begin
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
-- search for tree node that contains scope
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
assert v_found report "Scope not found!" severity warning;
if v_found then
-- Set stop limit for this node
v_current_ptr.element_data.alert_stop_limit(alert_level) := stop_limit;
v_current_ptr := v_current_ptr.parent;
-- Propagate stop limit
while v_current_ptr /= null loop
if v_current_ptr.element_data.alert_stop_limit(alert_level) < stop_limit then
v_current_ptr.element_data.alert_stop_limit(alert_level) := stop_limit;
end if;
v_current_ptr := v_current_ptr.parent;
end loop;
end if;
end if;
end procedure;
impure function get_stop_limit(
scope : string;
alert_level : t_alert_level
) return natural is
variable v_current_ptr : t_element_ptr;
variable v_found : boolean := false;
begin
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
if v_found then
return v_current_ptr.element_data.alert_stop_limit(alert_level);
else
return 0;
end if;
end function;
procedure generate_hierarchy_prefix(
variable starting_node_ptr : in t_element_ptr;
variable calling_node_ptr : in t_element_ptr;
variable origin_node_ptr : in t_element_ptr;
variable v_line : inout line
) is
variable v_indent_correction_amount : natural := 0;
begin
if starting_node_ptr.parent = null then
-- This is the top level
-- Write a '|' as first character if the calling node (child)
-- has another sibling, else nothing.
if origin_node_ptr.parent /= starting_node_ptr
and calling_node_ptr.next_sibling /= null then
write(v_line, string'("|"));
end if;
else
-- This starting_node is not the top node
-- Create prefix for parent first.
generate_hierarchy_prefix(starting_node_ptr.parent, starting_node_ptr, origin_node_ptr, v_line);
-- All that have received a '|' as the first character in the buffer
-- has one space too many afterwards. Special case for the first character.
if starting_node_ptr.parent.parent = null then
if starting_node_ptr.next_sibling /= null then
v_indent_correction_amount := 1;
end if;
end if;
if starting_node_ptr.next_sibling /= null then
-- Has another sibling
if calling_node_ptr.next_sibling /= null then
write(v_line, fill_string(' ', 2 - v_indent_correction_amount));
write(v_line, string'("|"));
else
write(v_line, fill_string(' ', 3 - v_indent_correction_amount));
end if;
else
-- No next sibling
write(v_line, fill_string(' ', 3 - v_indent_correction_amount));
end if;
end if;
end procedure;
procedure print_node(
variable starting_node_ptr : in t_element_ptr;
variable v_status_ok : inout boolean;
variable v_mismatch : inout boolean;
variable v_line : inout line
) is
variable v_current_ptr : t_element_ptr;
begin
-- Write indentation according to hierarchy level
if starting_node_ptr.hierarchy_level > 0 then
generate_hierarchy_prefix(starting_node_ptr.parent, starting_node_ptr, starting_node_ptr, v_line);
if starting_node_ptr.next_sibling /= null then
write(v_line, string'("|- "));
else
write(v_line, string'("`- "));
end if;
end if;
-- Print name of node
write(v_line, starting_node_ptr.element_data.name);
-- Adjust the columns according to max hierarchy level
if vr_max_hierarchy_level > 0 then
if starting_node_ptr.hierarchy_level /= vr_max_hierarchy_level then
write(v_line, fill_string(' ', (vr_max_hierarchy_level - starting_node_ptr.hierarchy_level)*3));
end if;
end if;
-- Print colon to signify the end of the name
write(v_line, string'(":"));
-- Print counters for each of the alert levels.
for alert_level in NOTE to t_alert_level'right loop
write(v_line, justify(integer'image(starting_node_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & "/" &
integer'image(starting_node_ptr.element_data.alert_attention_counters(alert_level)(EXPECT)) & "/" &
integer'image(starting_node_ptr.element_data.alert_attention_counters(alert_level)(IGNORE))
,RIGHT, 11) & " ");
if v_status_ok = true then
if starting_node_ptr.element_data.alert_attention_counters(alert_level)(REGARD) /=
starting_node_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) then
if alert_level > MANUAL_CHECK then
if starting_node_ptr.element_data.alert_attention_counters(alert_level)(REGARD) <
starting_node_ptr.element_data.alert_attention_counters(alert_level)(EXPECT) then
v_mismatch := true;
else
v_status_ok := false;
end if;
end if;
end if;
end if;
end loop;
write(v_line, LF);
if starting_node_ptr.first_child /= null then
print_node(starting_node_ptr.first_child, v_status_ok, v_mismatch, v_line);
end if;
if starting_node_ptr.next_sibling /= null then
print_node(starting_node_ptr.next_sibling, v_status_ok, v_mismatch, v_line);
end if;
end procedure;
procedure print_hierarchical_log(
order : t_order := FINAL
) is
variable v_header : string(1 to 80);
variable v_line : line;
variable v_line_copy : line;
constant prefix : string := C_LOG_PREFIX & " ";
variable v_status_ok : boolean := true;
variable v_mismatch : boolean := false;
begin
if order = INTERMEDIATE then
v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS *** Format: REGARDED/EXPECTED/IGNORED";
else -- order=FINAL
v_header := "*** FINAL SUMMARY OF ALL ALERTS *** Format: REGARDED/EXPECTED/IGNORED ";
end if;
-- Write header
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
v_header & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify(" ", RIGHT, 3+ C_HIERARCHY_NODE_NAME_LENGTH + vr_max_hierarchy_level*3) & "NOTE" & justify(" ", RIGHT, 6) & "TB_NOTE" & justify(" ", RIGHT, 5) & "WARNING" & justify(" ", RIGHT, 3) & "TB_WARNING" & justify(" ", RIGHT, 2) & "MANUAL_CHECK" & justify(" ", RIGHT, 3) & "ERROR" & justify(" ", RIGHT, 5) & "TB_ERROR" & justify(" ", RIGHT, 5) & "FAILURE" & justify(" ", RIGHT, 3) & "TB_FAILURE" & LF);
-- Print all nodes
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
print_node(vr_top_element_ptr, v_status_ok, v_mismatch, v_line);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequencer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if not v_status_ok then
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
elsif v_mismatch then
write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all & lf); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end procedure;
impure function get_parent_scope(
scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH))
return string is
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
assert v_found report "Scope not found. Exiting get_parent_scope()..." severity warning;
if not v_found then return justify("", LEFT, C_HIERARCHY_NODE_NAME_LENGTH); end if;
if v_current_ptr.parent /= null then
return v_current_ptr.parent.element_data.name;
end if;
end if;
return "";
end function;
procedure propagate_hierarchy_level(
variable node_ptr : inout t_element_ptr
) is
begin
if node_ptr /= null then
if node_ptr.parent /= null then
node_ptr.hierarchy_level := node_ptr.parent.hierarchy_level + 1;
else -- No parent
node_ptr.hierarchy_level := 0;
end if;
if vr_max_hierarchy_level < node_ptr.hierarchy_level then
vr_max_hierarchy_level := node_ptr.hierarchy_level;
end if;
if node_ptr.next_sibling /= null then
propagate_hierarchy_level(node_ptr.next_sibling);
end if;
if node_ptr.first_child /= null then
propagate_hierarchy_level(node_ptr.first_child);
end if;
end if;
end procedure;
procedure change_parent(
scope : string;
parent_scope : string
) is
variable v_old_parent_ptr : t_element_ptr := null;
variable v_new_parent_ptr : t_element_ptr := null;
variable v_child_ptr : t_element_ptr := null;
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
if vr_num_elements_in_tree > 0 and vr_has_been_initialized then
search_for_scope(vr_top_element_ptr, scope, v_child_ptr, v_found);
assert v_found report "Child not found. Exiting change_parent()..." severity warning;
if not v_found then return; end if;
search_for_scope(vr_top_element_ptr, parent_scope, v_new_parent_ptr, v_found);
assert v_found report "Parent not found. Exiting change_parent()..." severity warning;
if not v_found then return; end if;
if v_child_ptr.first_child /= null then
search_for_scope(v_child_ptr.first_child, parent_scope, v_current_ptr, v_found);
assert not v_found report "New parent is the descendant of the node that shall be moved! Illegal operation!" severity failure;
end if;
-- Clean up
-- Need to check the current parent of the child for any other children,
-- then clean up the next_sibling, prev_sibling and first_child pointers.
v_old_parent_ptr := v_child_ptr.parent;
if v_old_parent_ptr /= null then
if v_old_parent_ptr.first_child = v_child_ptr then
-- First_child is this child. Check if any siblings.
-- Prev_sibling is null since this is first child.
-- Next sibling can be something else.
-- Correct first_child for old parent
if v_child_ptr.next_sibling /= null then
-- Set next_sibling to be first child
v_old_parent_ptr.first_child := v_child_ptr.next_sibling;
-- Clear prev_sibling for the sibling that will now be first_child of old_parent
v_child_ptr.next_sibling.prev_sibling := null;
else
-- No siblings, clear first_child
v_old_parent_ptr.first_child := null;
end if;
else
-- This child must be one of the siblings.
-- Remove this child and glue together the other siblings
-- Create pointer from previous sibling to next sibling
v_child_ptr.prev_sibling.next_sibling := v_child_ptr.next_sibling;
-- Create pointer from next sibling to previous sibling
if v_child_ptr.next_sibling /= null then
v_child_ptr.next_sibling.prev_sibling := v_child_ptr.prev_sibling;
end if;
end if;
-- Clear siblings to prepare for another parent
v_child_ptr.prev_sibling := null;
v_child_ptr.next_sibling := null;
end if;
-- Set new parent and prev_sibling for the child.
if v_new_parent_ptr.first_child = null then
-- No children previously created for this parent
v_new_parent_ptr.first_child := v_child_ptr;
else
-- There is at least 1 child belonging to the new parent
v_current_ptr := v_new_parent_ptr.first_child;
while v_current_ptr.next_sibling /= null loop
v_current_ptr := v_current_ptr.next_sibling;
end loop;
-- v_current_ptr is now the final sibling belonging to
-- the new parent
v_current_ptr.next_sibling := v_child_ptr;
v_child_ptr.prev_sibling := v_current_ptr;
end if;
-- Set parent correctly
v_child_ptr.parent := v_new_parent_ptr;
-- Update hierarchy levels for the whole tree
vr_max_hierarchy_level := 0;
propagate_hierarchy_level(vr_top_element_ptr);
end if;
end procedure;
procedure set_top_level_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
--
--
vr_top_element_ptr.element_data.alert_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if vr_top_element_ptr.element_data.alert_stop_limit(alert_level) /= 0 and
(vr_top_element_ptr.element_data.alert_attention_counters(alert_level)(REGARD) >= vr_top_element_ptr.element_data.alert_stop_limit(alert_level)) then
assert false
report "Alert stop limit for scope " & vr_top_element_ptr.element_data.name & " at alert level " & to_upper(to_string(alert_level)) & " set to " & to_string(value) &
", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(vr_top_element_ptr.element_data.alert_attention_counters(alert_level)(REGARD)) & ")."
severity failure;
end if;
end procedure;
impure function get_top_level_stop_limit(
alert_level : t_alert_level
) return natural is
begin
return vr_top_element_ptr.element_data.alert_stop_limit(alert_level);
end function;
procedure propagate_alert_level(
variable node_ptr : inout t_element_ptr;
constant alert_level : t_alert_level;
constant setting : boolean
) is
begin
if node_ptr /= null then
node_ptr.element_data.alert_level_print(alert_level) := setting;
if node_ptr.next_sibling /= null then
propagate_alert_level(node_ptr.next_sibling, alert_level, setting);
end if;
if node_ptr.first_child /= null then
propagate_alert_level(node_ptr.first_child, alert_level, setting);
end if;
end if;
end procedure;
procedure enable_alert_level(
scope : string;
alert_level : t_alert_level
) is
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
if v_found then
propagate_alert_level(v_current_ptr, alert_level, true);
end if;
end procedure;
procedure disable_alert_level(
scope : string;
alert_level : t_alert_level
) is
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
if v_found then
propagate_alert_level(v_current_ptr, alert_level, false);
end if;
end procedure;
procedure enable_all_alert_levels(
scope : string
) is
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
if v_found then
for alert_level in NOTE to t_alert_level'right loop
propagate_alert_level(v_current_ptr, alert_level, true);
end loop;
end if;
end procedure;
procedure disable_all_alert_levels(
scope : string
) is
variable v_current_ptr : t_element_ptr := null;
variable v_found : boolean := false;
begin
search_for_scope(vr_top_element_ptr, scope, v_current_ptr, v_found);
if v_found then
for alert_level in NOTE to t_alert_level'right loop
propagate_alert_level(v_current_ptr, alert_level, false);
end loop;
end if;
end procedure;
end protected body;
end package body hierarchy_linked_list_pkg; | mit |
AndyMcC0/UVVM_All | uvvm_util/src/uvvm_util_context.vhd | 1 | 1596 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context uvvm_util_context is
library uvvm_util;
use uvvm_util.types_pkg.all;
use uvvm_util.hierarchy_linked_list_pkg.all;
use uvvm_util.string_methods_pkg.all;
use uvvm_util.adaptations_pkg.all;
use uvvm_util.methods_pkg.all;
use uvvm_util.bfm_common_pkg.all;
use uvvm_util.alert_hierarchy_pkg.all;
use uvvm_util.license_pkg.all;
use uvvm_util.protected_types_pkg.all;
end context;
| mit |
Wynjones1/gbvhdl | src/common.vhd | 1 | 4491 | library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use work.types.all;
package common is
-- impure function init_mem(input_file : in string) return
function r_table(input : std_logic_vector(2 downto 0)) return register_t;
function d_table(input : std_logic_vector(1 downto 0)) return register_t;
function s_table(input : std_logic_vector(1 downto 0)) return register_t;
function q_table(input : std_logic_vector(1 downto 0)) return register_t;
function f_table(input : std_logic_vector(2 downto 0)) return alu_op_t;
function l_table(input : std_logic_vector(2 downto 0)) return alu_op_t;
function need_to_jump(cc : std_logic_vector(1 downto 0); flags : std_logic_vector(7 downto 4)) return boolean;
function read_slv(file fp : text) return std_logic_vector;
end;
-- TODO: Maybe add report for invalid values.
package body common is
function r_table(input : std_logic_vector(2 downto 0)) return register_t is
begin
case input is
when "111" => return register_a;
when "000" => return register_b;
when "001" => return register_c;
when "010" => return register_d;
when "011" => return register_e;
when "100" => return register_h;
when "101" => return register_l;
when others => return register_l; -- TODO: Fix
end case;
end function;
function d_table(input : std_logic_vector(1 downto 0)) return register_t is
begin
case input is
when "00" => return register_bc;
when "01" => return register_de;
when "10" => return register_hl;
when "11" => return register_sp;
when others => return register_sp; -- TODO: Fix
end case;
end function;
function s_table(input : std_logic_vector(1 downto 0)) return register_t is
begin
return d_table(input);
end function;
function q_table(input : std_logic_vector(1 downto 0)) return register_t is
begin
case input is
when "00" => return register_bc;
when "01" => return register_de;
when "10" => return register_hl;
when "11" => return register_af;
when others => return register_af; -- TODO: Fix
end case;
end function;
function f_table(input : std_logic_vector(2 downto 0)) return alu_op_t is
begin
case input is
when "000" => return alu_op_add;
when "001" => return alu_op_adc;
when "010" => return alu_op_sub;
when "011" => return alu_op_sbc;
when "100" => return alu_op_and;
when "101" => return alu_op_xor;
when "110" => return alu_op_or;
when "111" => return alu_op_cp;
when others => return alu_op_invalid;
end case;
end function;
function l_table(input : std_logic_vector(2 downto 0)) return alu_op_t is
begin
case input is
when "000" => return alu_op_rlc;
when "001" => return alu_op_rrc;
when "010" => return alu_op_rl;
when "011" => return alu_op_rr;
when "100" => return alu_op_sla;
when "101" => return alu_op_sra;
when "110" => return alu_op_swap;
when "111" => return alu_op_srl;
when others => return alu_op_invalid;
end case;
end function;
function need_to_jump(
cc : std_logic_vector(1 downto 0);
flags : std_logic_vector(7 downto 4))
return boolean is
begin
return ((cc = "00") and (flags(ZERO_BIT) = '0')) or -- NZ
((cc = "01") and (flags(ZERO_BIT) = '1')) or -- Z
((cc = "10") and (flags(CARRY_BIT) = '0')) or -- NC
((cc = "11") and (flags(CARRY_BIT) = '1')); -- C
end function;
function read_slv(file fp : text) return std_logic_vector is
variable bv : bit_vector(15 downto 0);
variable slv : std_logic_vector(15 downto 0);
variable li : line;
begin
if endfile(fp) then
return "UUUUUUUUUUUUUUUU";
end if;
readline(fp, li);
read(li, bv);
for i in 0 to 15 loop
if bv(i) = '1' then
slv(i) := '1';
else
slv(i) := '0';
end if;
end loop;
return slv;
end function;
end common;
| mit |
AndyMcC0/UVVM_All | bitvis_vip_uart/src/uart_rx_vvc.vhd | 1 | 16486 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.uart_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity uart_rx_vvc is
generic (
GC_DATA_WIDTH : natural := 8;
GC_INSTANCE_IDX : natural := 1;
GC_CHANNEL : t_channel := RX;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic
);
end entity uart_rx_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of uart_rx_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX) & "," & to_upper(to_string(GC_CHANNEL));
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, GC_CHANNEL);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_uart_vvc_config(RX, GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_uart_vvc_status(RX, GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_uart_transaction_info(RX, GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(RX, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(RX, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = RECEIVE or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
when RECEIVE =>
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_cmd.data(GC_DATA_WIDTH - 1 downto 0);
-- Call the corresponding procedure in the BFM package.
uart_receive(data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
rx => uart_vvc_rx,
terminate_loop => terminate_current_cmd.is_active,
config => vvc_config.bfm_config,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data );
when EXPECT =>
-- Normalise address and data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "uart_expect() called with to wide data. " & add_msg_delimiter(v_cmd.msg));
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
-- Call the corresponding procedure in the BFM package.
uart_expect(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
rx => uart_vvc_rx,
terminate_loop => terminate_current_cmd.is_active,
max_receptions => v_cmd.max_receptions,
timeout => v_cmd.timeout,
alert_level => v_cmd.alert_level,
config => vvc_config.bfm_config,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.bit_time;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
| mit |
JackyRen/vimrc | template/vhdl/basic.vhd | 1 | 304 | LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE work.GlobalDefines.ALL;
entity <name> is
port(
);
end <name>;
architecture bhv of <name> is
component <bla> is
port(
);
end component;
begin
end bhv;
| mit |
kiwih/subleq-vhdl | clk_div.vhd | 1 | 580 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_div is
generic(
CLOCK_DIVIDE : integer := 5000000
);
port (
CLK_50: in std_logic;
CLK_SLOW: out std_logic
);
end entity clk_div;
architecture beh of clk_div is
begin
-- clk_out <= clk_in;
process (CLK_50)
variable count: integer range 0 to (CLOCK_DIVIDE - 1) := 0;
begin
if(rising_edge(CLK_50)) then
if(count = (CLOCK_DIVIDE - 1)) then
count := 0;
CLK_SLOW <= '1';
else
CLK_SLOW <= '0';
count := count + 1;
end if;
end if;
end process;
end architecture beh; | mit |
AndyMcC0/UVVM_All | uvvm_util/src/methods_pkg.vhd | 1 | 237364 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.license_pkg.all;
use work.alert_hierarchy_pkg.all;
use work.protected_types_pkg.all;
use std.env.all;
package methods_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_MSG_ID_PANEL_DEFAULT;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
shared variable shared_flag_array : t_sync_flag_record_array := (others => C_SYNC_FLAG_DEFAULT);
shared variable protected_semaphore : t_protected_semaphore;
shared variable protected_broadcast_semaphore : t_protected_semaphore;
shared variable protected_response_semaphore : t_protected_semaphore;
shared variable shared_uvvm_status : t_uvvm_status;
signal global_trigger : std_logic := 'L';
signal global_barrier : std_logic := 'X';
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
);
-- Enable and Disable do not have a Scope parameter as they are only allowed from main test sequencer
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) ;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
);
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Warning! This function should NOT be used outside the UVVM library.
-- Function is only included to support internal functionality.
-- The function can be removed without notification.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock count and duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock enable and clock name
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name
-- and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name,
-- clock count and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
-- ============================================================================
-- Synchronisation methods
-- ============================================================================
-- method to block a global flag with the name flag_name
procedure block_flag(
constant flag_name : in string;
constant msg : in string
);
-- method to unblock a global flag with the name flag_name
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic
);
-- method to wait for the global flag with the name flag_name
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR
);
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR
);
-------------------------------------------
-- await_semaphore_in_delta_cycles
-------------------------------------------
-- tries to lock the semaphore for C_NUM_SEMAPHORE_LOCK_TRIES in adaptations_pkg
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
);
-------------------------------------------
-- release_semaphore
-------------------------------------------
-- releases the semaphore
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_uvvm_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_uvvm_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
variable v_minimum_log_line_width : natural := 0;
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME);
end if;
if C_ENABLE_HIERARCHICAL_ALERTS then
initialize_hierarchy;
end if;
-- Check that all log widths are valid
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_PREFIX_WIDTH + C_LOG_TIME_WIDTH + 5; -- Add 5 for spaces
if not (C_SHOW_LOG_ID or C_SHOW_LOG_SCOPE) then
v_minimum_log_line_width := v_minimum_log_line_width + 10; -- Minimum length in order to wrap lines properly
else
if C_SHOW_LOG_ID then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_MSG_ID_WIDTH;
end if;
if C_SHOW_LOG_SCOPE then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_SCOPE_WIDTH;
end if;
end if;
bitvis_assert(C_LOG_LINE_WIDTH >= v_minimum_log_line_width, failure, "C_LOG_LINE_WIDTH is too low. Needs to higher than " & to_string(v_minimum_log_line_width) & ". ", C_SCOPE);
--show_license(VOID);
-- if C_SHOW_uvvm_utilITY_LIBRARY_INFO then
-- show_uvvm_utility_library_info(VOID);
-- end if;
-- if C_SHOW_uvvm_utilITY_LIBRARY_RELEASE_INFO then
-- show_uvvm_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_alert_file_name_is_set then
warning("alert file name already set. Setting new alert file " & file_name);
end if;
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
) is
variable v_file_open_status: file_open_status;
begin
deprecate(get_procedure_name_from_instance_name(file_name'instance_name), "msg_id parameter is no longer in use. Please call this procedure without the msg_id parameter.");
set_alert_file_name(file_name);
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_log_file_name_is_set then
warning("log file name already set. Setting new log file " & file_name);
end if;
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
) is
begin
-- msg_id is no longer in use. However, can not call deprecate() since Util may not
-- have opened a log file yet. Attempting to call deprecate() when there is no open
-- log file will cause a fatal error. Leaving this alone with no message.
set_log_file_name(file_name);
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all);
writeline(file_handle, v_line);
end procedure tee;
-- Open, append/write to and close file. Also deallocates contents of the line
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
) is
file v_specified_file_pointer : text;
begin
file_open(v_specified_file_pointer, file_name, open_mode);
writeline(v_specified_file_pointer, my_line);
file_close(v_specified_file_pointer);
end procedure write_to_file;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), LEFT, C_LOG_MSG_ID_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
else
v_log_scope := justify(to_string(scope), LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, C_SHOW_LOG_ID) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, C_SHOW_LOG_SCOPE) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if C_USE_BACKSLASH_R_AS_LF and (msg(1 to 2) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
write(v_msg, remove_initial_chars(msg, 2));
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, to_string(replace_backslash_n_with_lf(v_msg.all)));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, v_info_final); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
end case;
end if;
end if;
end;
-- Logging for multi line text. Also deallocates the text_block, for consistency.
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
if ((log_file_name = "") and ((log_destination = CONSOLE_AND_LOG) or (log_destination = LOG_ONLY))) then
alert(TB_ERROR, "log_text_block called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
-- Check if message ID is enabled
elsif (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, text_block); -- Write to console, but keep text_block
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, text_block); -- Write to console and deallocate text_block
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
end case;
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
-- Add header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
case log_destination is
when CONSOLE_AND_LOG =>
-- Write header to console
tee(OUTPUT, v_header_line);
-- Write header to file, and open/close if not default log file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
else
write_to_file(log_file_name, open_mode, v_header_line);
end if;
-- Write header message to specified destination
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_AND_LOG, log_file_name, append_mode);
-- Write log body to console
tee(OUTPUT, v_log_body);
-- Write log body to specified file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, append_mode, v_log_body);
end if;
when CONSOLE_ONLY =>
-- Write to console and deallocate all lines
writeline(OUTPUT, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_ONLY);
writeline(OUTPUT, v_log_body);
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY);
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, open_mode, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY, log_file_name, append_mode);
write_to_file(log_file_name, append_mode, v_log_body);
end if;
end case;
-- Deallocate text block to give writeline()-like behaviour
-- for formatted output
deallocate(text_block);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
tb_warning("enable_log_msg() ignored for " & to_upper(to_string(msg_id)) & " (not allowed). " & add_msg_delimiter(msg), scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
msg_id_panel(ID_BITVIS_DEBUG) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
when others =>
msg_id_panel(msg_id) := ENABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, "", C_TB_SCOPE_DEFAULT, quietness);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, "", C_TB_SCOPE_DEFAULT, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
) is
begin
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "Changing log destination to " & to_string(log_destination) & ". Was " & to_string(shared_default_log_destination) & ". ", C_TB_SCOPE_DEFAULT);
end if;
shared_default_log_destination := log_destination;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
-- Shared variable for all the alert counters for different attention
shared variable protected_alert_attention_counters : t_protected_alert_attention_counters;
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
constant C_ATTENTION : t_attention := get_alert_attention(alert_level);
begin
if alert_level /= NO_ALERT then
pot_initialise_util(VOID); -- Only executed the first time called
if C_ENABLE_HIERARCHICAL_ALERTS then
-- Call the hierarchical alert function
hierarchical_alert(alert_level, to_string(msg), to_string(scope), C_ATTENTION);
else
-- Perform the non-hierarchical alert function
write(v_msg, replace_backslash_n_with_lf(to_string(msg)));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_upper(to_string(alert_level)) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
if alert_level = NO_ALERT then
alert(TB_WARNING, "increment_expected_alerts not allowed for alert_level NO_ALERT. " & add_msg_delimiter(msg), scope);
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_upper(to_string(alert_level)) & "s by " & to_string(number) & ". " & add_msg_delimiter(msg), scope);
else
increment_expected_alerts(C_BASE_HIERARCHY_LEVEL, alert_level, number);
end if;
end if;
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
pot_initialise_util(VOID); -- Only executed the first time called
if not C_ENABLE_HIERARCHICAL_ALERTS then
protected_alert_attention_counters.to_string(order);
else
print_hierarchical_log(order);
end if;
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT " & LF);
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT, KEEP_LEADING_SPACE) & " " & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", LEFT, C_LOG_MSG_ID_WIDTH) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if ((i /= ALL_MESSAGES) and ((i /= NO_ID) and (i /= ID_NEVER))) then -- report all but ID_NEVER, NO_ID and ALL_MESSAGES
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_upper(to_string(shared_msg_id_panel(i))) & " " & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_attention not allowed for alert_level NO_ALERT (always IGNORE).");
else
check_value(attention = IGNORE or attention = REGARD, TB_WARNING,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_upper(to_string(alert_level)) & ", " & to_string(attention) & "). " & add_msg_delimiter(msg));
end if;
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
if alert_level = NO_ALERT then
return IGNORE;
else
return shared_alert_attention(alert_level);
end if;
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_stop_limit not allowed for alert_level NO_ALERT (stop limit always 0).");
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_upper(to_string(alert_level)) & " set to " & to_string(value) &
", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
else
-- If hierarchical alerts enabled, update top level
-- alert stop limit.
set_hierarchical_alert_top_level_stop_limit(alert_level, value);
end if;
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
if alert_level = NO_ALERT then
return 0;
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
return shared_stop_limit(alert_level);
else
return get_hierarchical_alert_top_level_stop_limit(alert_level);
end if;
end if;
end;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return protected_alert_attention_counters.get(alert_level, attention);
end;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
type alert_array is array (1 to 6) of t_alert_level;
constant alert_check_array : alert_array := (WARNING, TB_WARNING, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
alias warning_and_worse is shared_uvvm_status.no_unexpected_simulation_warnings_or_worse;
alias error_and_worse is shared_uvvm_status.no_unexpected_simulation_errors_or_worse;
begin
protected_alert_attention_counters.increment(alert_level, attention, number);
-- Update simulation status
if (attention = REGARD) or (attention = EXPECT) then
if (alert_level /= NO_ALERT) and (alert_level /= NOTE) and (alert_level /= TB_NOTE) and (alert_level /= MANUAL_CHECK) then
warning_and_worse := 1; -- default
error_and_worse := 1; -- default
-- Compare expected and current allerts
for i in 1 to alert_check_array'high loop
if (get_alert_counter(alert_check_array(i), REGARD) > get_alert_counter(alert_check_array(i), EXPECT)) then
-- warning and worse
warning_and_worse := 0;
-- error and worse
if not(alert_check_array(i) = WARNING) and not(alert_check_array(i) = TB_WARNING) then
error_and_worse := 0;
end if;
end if;
end loop;
end if;
end if;
end;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, RIGHT, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", RIGHT, 100) then
deprecated_subprogram_list(i) := justify(caller_name, RIGHT, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, caller_name & " => OK, for boolean true. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Boolean was false. " & add_msg_delimiter(msg), scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for boolean " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if std_match(value, exp) then
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end if;
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format,INCL_RADIX);
constant v_exp_str : string := to_string(a_exp, radix, format,INCL_RADIX);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(value'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
v_check_ok := matching_values(a_value, a_exp);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "' (exp: " & v_exp_str & "'). " & add_msg_delimiter(msg),
scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & "'. Expected " & v_exp_str & "'" & LF & msg, scope);
end if;
end if;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & "'. Expected " & v_exp_str & "'" & LF & msg, scope);
end if;
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & value & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
v_target(i downto i) := std_logic_vector(to_unsigned(random(0,1),1));
end loop;
end;
-- Set target to a random SL, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
v_random_slv := std_logic_vector(to_unsigned(random(0,1),1));
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable success : boolean := false;
begin
success := false;
if match_strictness = MATCH_EXACT then
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
if (target = exp) then
success := true;
end if;
else
if ((exp = '1' or exp = 'H') and (target /= '1') and (target /= 'H')) then
wait until (target = '1' or target = 'H') for max_time;
elsif ((exp = '0' or exp = 'L') and (target /= '0') and (target /= 'L')) then
wait until (target = '0' or target = 'L') for max_time;
end if;
if ((exp = '1' or exp = 'H') and (target = '1' or target = 'H')) then
success := true;
elsif ((exp = '0' or exp = 'L') and (target = '0' or target = 'L')) then
success := true;
end if;
end if;
check_time_window(success, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_EXACT, min_time, max_time, alert_level, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if match_strictness = MATCH_STD then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_STD, min_time, max_time, alert_level, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, caller_name & " => Unknown stable_req_from. " & add_msg_delimiter(msg), scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, caller_name & " => Unknown timeout_from. " & add_msg_delimiter(msg), scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, caller_name & " => OK. Condition occurred immediately. " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, caller_name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, caller_name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, caller_name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Generate a pulse on a boolean for a certain number of clock cycles
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
variable v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if pulse_value(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
constant v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = (others => '1') by default
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
clock_count <= 0;
loop
clock_signal <= '0'; -- Should start on 0
wait for C_FIRST_HALF_CLK_PERIOD;
-- Update clock_count when clock_signal is set to '1'
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Counter clock_count is given as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
clock_count <= 0;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '0';
wait for clock_high_time;
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
-- ============================================================================
-- Synchronisation methods
-- ============================================================================
procedure block_flag(
constant flag_name : in string;
constant msg : in string
) is
begin
-- Block the flag if it was used before
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
shared_flag_array(i).is_active := true;
exit;
end if;
end loop;
log(ID_BLOCKING, "Blocking " & flag_name & ". " & add_msg_delimiter(msg), C_SCOPE);
end procedure;
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic
) is
variable found : boolean := false;
begin
-- check if the flag has already been added. If not add it.
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
shared_flag_array(i).is_active := false;
found := true;
log(ID_BLOCKING, "Unblocking " & flag_name & ". " & add_msg_delimiter(msg), C_SCOPE);
gen_pulse(trigger, 0 ns, "pulsing global_trigger. " & add_msg_delimiter(msg), C_TB_SCOPE_DEFAULT, ID_NEVER);
exit;
end if;
end loop;
if found = false then
log(ID_BLOCKING, "The flag " & flag_name & " was not found and the maximum of flags were used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), C_SCOPE);
end if;
end procedure;
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR
) is
variable v_flag_is_active : boolean := true;
constant start_time : time := now;
begin
-- check if flag was not unblocked before
for i in shared_flag_array'range loop
-- check if the flag was already in the global_flag array. If it was not -> add it to the first free space
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
v_flag_is_active := shared_flag_array(i).is_active;
if v_flag_is_active = false then
log(ID_BLOCKING, flag_name & " was not blocked. " & add_msg_delimiter(msg), C_SCOPE);
if flag_returning = RETURN_TO_BLOCK then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(i).is_active := true;
end if;
end if;
exit;
end if;
end loop;
if v_flag_is_active = true then
-- log before while loop. Otherwise the message will be printed everytime the global_trigger was triggered.
log(ID_BLOCKING, "Waiting for " & flag_name & " to be unblocked. " & add_msg_delimiter(msg), C_SCOPE);
end if;
while v_flag_is_active = true loop
if timeout /= 0 ns then
wait until rising_edge(global_trigger) for ((start_time + timeout) - now);
check_value(global_trigger = '1', timeout_severity, flag_name & " timed out" & add_msg_delimiter(msg), C_SCOPE, ID_NEVER);
if global_trigger /= '1' then
exit;
end if;
else
wait until rising_edge(global_trigger);
end if;
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name then
v_flag_is_active := shared_flag_array(i).is_active;
if v_flag_is_active = false then
log(ID_BLOCKING, flag_name & " was unblocked. " & add_msg_delimiter(msg), C_SCOPE);
if flag_returning = RETURN_TO_BLOCK then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(i).is_active := true;
end if;
end if;
end if;
end loop;
end loop;
end procedure;
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR
)is
begin
-- set barrier signal to 0
barrier_signal <= '0';
log(ID_BLOCKING, "Waiting for barrier. " & add_msg_delimiter(msg), C_SCOPE);
-- wait until all sequencer using that barrier_signal wait for it
if timeout = 0 ns then
wait until barrier_signal = '0';
else
wait until barrier_signal = '0' for timeout;
end if;
if barrier_signal /= '0' then
-- timeout
alert(timeout_severity, "Timeout while waiting for barrier signal. " & add_msg_delimiter(msg), C_SCOPE);
else
log(ID_BLOCKING, "Barrier received. " & add_msg_delimiter(msg), C_SCOPE);
end if;
barrier_signal <= '1';
end procedure;
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
) is
variable v_cnt_lock_tries : natural := 0;
begin
while semaphore.get_semaphore = false and v_cnt_lock_tries < C_NUM_SEMAPHORE_LOCK_TRIES loop
wait for 0 ns;
v_cnt_lock_tries := v_cnt_lock_tries + 1;
end loop;
if v_cnt_lock_tries = C_NUM_SEMAPHORE_LOCK_TRIES then
tb_error("Failed to acquire semaphore when sending command to VVC", C_SCOPE);
end if;
end procedure;
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
) is
begin
semaphore.release_semaphore;
end procedure;
end package body methods_pkg;
| mit |
AndyMcC0/UVVM_All | bitvis_vip_spi/src/vvc_cmd_pkg.vhd | 1 | 7098 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_cmd_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY,
SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
-- Common VVC fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data => (others => '0'),
data_exp => (others => '0'),
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => failure,
delay => 0 ns,
quietness => NON_QUIET
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
--=================================================================================================
--=================================================================================================
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
| mit |
AndyMcC0/UVVM_All | bitvis_vip_sbi/src/sbi_bfm_pkg.vhd | 1 | 32317 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Important : For systems not using 'ready' a dummy signal must be declared and set to '1'
-- For systems not using 'terminate' a dummy signal must be declared and set to '1' if using sbi_poll_until()
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package sbi_bfm_pkg is
--===============================================================================================
-- Types and constants for SBI BFMs
--===============================================================================================
constant C_SCOPE : string := "SBI BFM";
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rena : std_logic; -- to dut
wena : std_logic; -- to dut
wdata : std_logic_vector; -- to dut
ready : std_logic; -- from dut
rdata : std_logic_vector; -- from dut
end record;
-- Configuration record to be assigned in the test harness.
type t_sbi_bfm_config is
record
max_wait_cycles : integer; -- The maximum number of clock cycles to wait for the DUT ready signal before reporting a timeout alert.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
use_fixed_wait_cycles_read : boolean; -- When true, wait 'fixed_wait_cycles_read' after asserting rena, before sampling rdata
fixed_wait_cycles_read : natural; -- Number of clock cycles to wait after asserting rd signal, before sampling rdata from DUT.
clock_period : time; -- Period of the clock signal
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the SBI BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the SBI BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the SBI BFM
use_ready_signal : boolean; -- Whether or not to use the interface ready signal
end record;
constant C_SBI_BFM_CONFIG_DEFAULT : t_sbi_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => failure,
use_fixed_wait_cycles_read => false,
fixed_wait_cycles_read => 0,
clock_period => 10 ns,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
use_ready_signal => true
);
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_sbi_if_signals
------------------------------------------
-- - This function returns an SBI interface with initialized signals.
-- - All SBI input signals are initialized to 0
-- - All SBI output signals are initialized to Z
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if;
------------------------------------------
-- sbi_write
------------------------------------------
-- - This procedure writes data to the SBI DUT
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal wdata : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_write
------------------------------------------
-- - This procedure writes data 'data_value' to the SBI DUT address 'addr_value'
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_read
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- returns the read data in the output 'data_value'
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
);
------------------------------------------
-- sbi_read
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and returns
-- the read data in the output 'data_value'
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
);
------------------------------------------
-- sbi_check
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_check
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_poll_until
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, a new read
-- will be performed, and the new read data will be compared with the
-- 'data_exp'. This process will continue until one of the following
-- conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_polls'
-- c) The time spent polling is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_polls' is set to 0, it will be interpreted as no limitation on number of polls
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_poll_until
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, a new read
-- will be performed, and the new read data will be compared with the
-- 'data_exp'. This process will continue until one of the following
-- conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_polls'
-- c) The time spent polling is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_polls' is set to 0, it will be interpreted as no limitation on number of polls
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
end package sbi_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body sbi_bfm_pkg is
---------------------------------------------------------------------------------
-- initialize sbi to dut signals
---------------------------------------------------------------------------------
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if is
variable result : t_sbi_if(addr(addr_width - 1 downto 0),
wdata(data_width - 1 downto 0),
rdata(data_width - 1 downto 0));
begin
result.cs := '0';
result.rena := '0';
result.wena := '0';
result.addr := (result.addr'range => '0');
result.wdata := (result.wdata'range => '0');
result.ready := 'Z';
result.rdata := (result.rdata'range => 'Z');
return result;
end function;
---------------------------------------------------------------------------------
-- write
---------------------------------------------------------------------------------
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal wdata : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_write";
constant proc_call : string := "sbi_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalise to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
variable v_normalised_data : std_logic_vector(wdata'length-1 downto 0) :=
normalize_and_check(data_value, wdata, ALLOW_NARROWER, "data_value", "sbi_core_in.wdata", msg);
variable v_clk_cycles_waited : natural := 0;
begin
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
cs <= '1';
wena <= '1';
rena <= '0';
addr <= v_normalised_addr;
wdata <= v_normalised_data;
if config.use_ready_signal then
check_value(ready = '1' or ready = '0', failure, "Verifying that ready signal is set to either '1' or '0' when in use", scope, ID_NEVER, msg_id_panel);
end if;
wait until rising_edge(clk);
while (config.use_ready_signal and ready = '0') loop
if v_clk_cycles_waited = 0 then
log(config.id_for_bfm_wait, proc_call & " waiting for response (sbi ready=0) " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
wait until rising_edge(clk);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, proc_call);
end loop;
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
cs <= '0';
wena <= '0';
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_write(addr_value, data_value, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.wdata,
scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- sbi_read
---------------------------------------------------------------------------------
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
) is
-- local_proc_* used if called from sequencer or VVC
constant local_proc_name : string := "sbi_read";
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalize to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
variable v_data_value : std_logic_vector(data_value'range);
variable v_clk_cycles_waited : natural := 0;
variable v_proc_call : line;
begin
if ext_proc_call = "" then
-- called directly from sequencer/VVC, show 'sbi_read...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like sbi_check, log 'sbi_check(..) while executing sbi_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
cs <= '1';
wena <= '0';
rena <= '1';
addr <= v_normalised_addr;
if config.use_ready_signal then
check_value(ready = '1' or ready = '0', failure, "Verifying that ready signal is set to either '1' or '0' when in use", scope, ID_NEVER, msg_id_panel);
end if;
wait until rising_edge(clk);
if config.use_fixed_wait_cycles_read then
-- Wait for a fixed number of clk cycles
for i in 1 to config.fixed_wait_cycles_read loop
v_clk_cycles_waited := v_clk_cycles_waited + 1;
wait until rising_edge(clk);
end loop;
else
-- If configured, wait for ready = '1'
while (config.use_ready_signal and ready = '0') loop
if v_clk_cycles_waited = 0 then
log(config.id_for_bfm_wait, v_proc_call.all & " waiting for response (sbi ready=0) " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
wait until rising_edge(clk);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end loop;
end if;
v_data_value := rdata;
data_value := v_data_value;
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
cs <= '0';
rena <= '0';
if ext_proc_call = "" then -- proc_name = "sbi_read"
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. sbi_check)
end if;
end procedure;
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
) is
begin
sbi_read(addr_value, data_value, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
scope, msg_id_panel, config, ext_proc_call);
end procedure;
---------------------------------------------------------------------------------
-- sbi_check
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the POLL_UNTILed value.
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_check";
constant proc_call : string := "sbi_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalize to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
-- Helper variables
variable v_data_value : std_logic_vector(rdata'length - 1 downto 0);
variable v_check_ok : boolean;
variable v_clk_cycles_waited : natural := 0;
begin
sbi_read(addr_value, v_data_value, msg, clk, cs, addr, rena, wena, ready, rdata, scope, msg_id_panel, config, proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_data_value, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_check(addr_value, data_exp, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
alert_level, scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- sbi_poll_until
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the POLL_UNTILed value.
-- The checking is repeated until timeout or N occurrences (reads) without POLL_UNTILed data.
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_poll_until";
constant proc_call : string := proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ", " & to_string(max_polls) & ", " & to_string(timeout, ns) & ")";
constant start_time : time := now;
-- Normalise to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
-- Helper variables
variable v_data_value : std_logic_vector(rdata'length - 1 downto 0);
variable v_check_ok : boolean;
variable v_timeout_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_num_of_occurrences : integer := 0;
variable v_clk_cycles_waited : natural := 0;
variable v_config : t_sbi_bfm_config := config;
begin
-- Check for timeout = 0 and max_polls = 0. This combination can result in an infinite loop if the POLL_UNTILed data does not appear.
if max_polls = 0 and timeout = 0 ns then
alert(TB_WARNING, proc_name & " called with timeout=0 and max_polls=0. This can result in an infinite loop. " & add_msg_delimiter(msg), scope);
end if;
-- Initial status of the checks
v_check_ok := false;
v_timeout_ok := true;
v_num_of_occurrences_ok := true;
v_config.id_for_bfm := ID_BFM_POLL;
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Read data on SBI register
sbi_read(v_normalised_addr, v_data_value, "As a part of " & proc_call & ". " & add_msg_delimiter(msg), clk, cs, addr, rena, wena, ready, rdata, scope, msg_id_panel, v_config,
return_string1_if_true_otherwise_string2("", proc_call, is_log_msg_enabled(ID_BFM_POLL, msg_id_panel))); -- ID_BFM_POLL will allow the logging inside sbi_read to be executed
-- Evaluate data
v_check_ok := matching_values(v_data_value, data_exp);
-- Evaluate number of occurrences, if limited by user
v_num_of_occurrences := v_num_of_occurrences + 1;
if max_polls > 0 then
v_num_of_occurrences_ok := v_num_of_occurrences < max_polls;
end if;
-- Evaluate timeout, if specified by user
if timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := (now - start_time) < timeout;
end if;
end loop;
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time), ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(alert_level, proc_call & "=> Failed due to timeout. Did not get POLL_UNTILed value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(timeout, ns) & ". " & add_msg_delimiter(msg), scope);
elsif terminate_loop = '1' then
log(ID_TERMINATE_CMD, proc_call & " Terminated from outside this BFM. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, proc_call & "=> Failed. POLL_UNTILed value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_polls) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
end procedure;
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_poll_until(addr_value, data_exp, max_polls, timeout, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
terminate_loop, alert_level, scope, msg_id_panel, config);
end procedure;
end package body sbi_bfm_pkg;
| mit |
AndyMcC0/UVVM_All | bitvis_uart/src/uart_core.vhd | 1 | 13866 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : This is NOT an example of how to implement a UART core. This is just
-- a simple test vehicle that can be used to demonstrate the functionality
-- of the UVVM VVC Framework.
--
-- See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.uart_pif_pkg.all;
use work.uart_pkg.all;
entity uart_core is
generic (
GC_START_BIT : std_logic := '0';
GC_STOP_BIT : std_logic := '1';
GC_CLOCKS_PER_BIT : integer := 16);
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- PIF-core interface
p2c : in t_p2c;
c2p : out t_c2p;
-- Interrupt related signals
rx_a : in std_logic;
tx : out std_logic
);
end entity uart_core;
architecture rtl of uart_core is
type t_slv_array is array (3 downto 0) of std_logic_vector(7 downto 0);
-- tx signals
signal tx_data : t_slv_array:= (others => (others => '0'));
signal tx_buffer : std_logic_vector(7 downto 0) := (others => '0');
signal tx_data_valid : std_logic := '0';
signal tx_ready : std_logic := '0';
signal tx_active : std_logic := '0';
signal tx_clk_counter : unsigned(f_log2(GC_CLOCKS_PER_BIT)-1 downto 0) := (others => '0');
-- count through the bits (12 total)
signal tx_bit_counter : unsigned(3 downto 0) := (others => '0');
-- receive signals
signal rx_buffer : std_logic_vector(7 downto 0) := (others => '0');
signal rx_active : std_logic := '0';
signal rx_clk_counter : unsigned(f_log2(GC_CLOCKS_PER_BIT)-1 downto 0) := (others => '0');
-- count through the bits (12 total)
signal rx_bit_counter : unsigned(3 downto 0) := (others => '0');
signal rx_bit_samples : std_logic_vector(GC_CLOCKS_PER_BIT-1 downto 0) := (others => '0');
signal rx_data : t_slv_array := (others => (others => '0'));
signal rx_data_valid : std_logic := '0';
signal rx_data_full : std_logic := '0';
-- rx synced to clk
signal rx_s : std_logic_vector(1 downto 0) := (others => '1'); -- synchronized serial data input
signal rx_just_active : boolean; -- helper signal when we start receiving
signal parity_err : std_logic := '0'; -- parity error detected
signal stop_err : std_logic := '0'; -- stop error detected
signal transient_err : std_logic := '0'; -- data value is transient
signal c2p_i : t_c2p; -- Internal version of output
begin
c2p <= c2p_i;
c2p_i.aro_tx_ready <= tx_ready;
c2p_i.aro_rx_data_valid <= rx_data_valid;
-- synchronize rx input (async)
p_rx_s : process(clk, arst) is
begin
if arst = '1' then
rx_s <= (others => '1');
elsif rising_edge(clk) then
rx_s <= rx_s(0) & rx_a;
end if;
end process p_rx_s;
---------------------------------------------------------------------------
-- Transmit process; drives tx serial output.
--
-- Stores 4 pending bytes in the tx_data array, and the byte currently
-- being output in the tx_buffer register.
--
-- Tx_buffer is filled with data from tx_data(0) if there is valid data
-- available (tx_data_valid is active), and no other byte is currently
-- being output (tx_active is inactive).
--
-- Data received via SBI is inserted in tx_data at the index pointed to
-- by vr_tx_data_idx. vr_tx_data_idx is incremented when a new byte is
-- received via SBI, and decremented when a new byte is loaded into
-- tx_buffer.
---------------------------------------------------------------------------
uart_tx : process (clk, arst) is
variable vr_tx_data_idx : unsigned(2 downto 0) := (others => '0');
begin -- process uart_tx
if arst = '1' then -- asynchronous reset (active high)
tx_data <= (others => (others => '0'));
tx_buffer <= (others => '0');
tx_data_valid <= '0';
tx_ready <= '1';
tx_active <= '0';
tx_bit_counter <= (others => '0');
tx_clk_counter <= (others => '0');
tx <= '1';
vr_tx_data_idx := (others => '0');
elsif rising_edge(clk) then -- rising clock edge
-- There is valid data in tx_data.
-- Load the tx_buffer and activate TX operation.
-- Decrement vr_tx_data_idx.
if tx_data_valid = '1' and tx_active = '0' then
tx_active <= '1';
tx_buffer <= tx_data(0);
tx_data <= x"00" & tx_data(3 downto 1);
if vr_tx_data_idx > 0 then
-- Decrement idx
if vr_tx_data_idx < 3 then
vr_tx_data_idx := vr_tx_data_idx - 1;
else -- vr_tx_data_idx = 3
-- Special case for idx=3 (max).
-- When tx_data is full (tx_ready = '0'), we do not wish to
-- decrement the idx. The reason is that the idx points
-- to where the next incoming data byte shall be stored,
-- which is still idx 3.
-- Therefore, only decrement when tx_ready = '1'.
if tx_ready = '1' then
vr_tx_data_idx := vr_tx_data_idx - 1;
end if;
end if;
else
-- vr_tx_data_idx already at 0,
-- which means that the final byte in tx_data
-- was just loaded into tx_buffer, no more valid
-- data left in tx_data.
tx_data_valid <= '0';
tx_active <= '0';
end if;
-- Tx is now ready to receive another byte.
tx_ready <= '1';
end if;
-- loading the tx_data shift reg
if tx_ready = '1' then
if p2c.awo_tx_data_we = '1' then
tx_data(to_integer(vr_tx_data_idx)) <= p2c.awo_tx_data;
tx_data_valid <= '1';
-- Increment idx if tx_data not full.
if vr_tx_data_idx < 3 then
vr_tx_data_idx := vr_tx_data_idx + 1;
else -- tx_data full
tx_ready <= '0';
end if;
end if;
end if;
if tx_active = '0' then
-- default
tx_clk_counter <= (others => '0');
tx_bit_counter <= (others => '0');
tx <= '1'; -- idle as default
else
-- tx clock counter keeps running when active
if tx_clk_counter <= GC_CLOCKS_PER_BIT - 1 then
tx_clk_counter <= tx_clk_counter + 1;
else
tx_clk_counter <= (others => '0');
end if;
-- GC_CLOCKS_PER_BIT tx clocks per tx bit
if tx_clk_counter >= GC_CLOCKS_PER_BIT - 1 then
tx_bit_counter <= tx_bit_counter + 1;
end if;
case to_integer(tx_bit_counter) is
when 0 =>
tx <= GC_START_BIT;
when 1 to 8 =>
-- mux out the correct tx bit
tx <= tx_buffer(to_integer(tx_bit_counter)-1);
when 9 =>
tx <= odd_parity(tx_buffer);
when 10 =>
tx <= GC_STOP_BIT;
when others =>
tx <= '1';
tx_active <= '0';
end case;
end if;
end if;
end process uart_tx;
-- Data is set on the output when available on rx_data(0)
c2p_i.aro_rx_data <= rx_data(0);
---------------------------------------------------------------------------
-- Receive process
---------------------------------------------------------------------------
uart_rx : process (clk, arst) is
variable vr_rx_data_idx : unsigned(2 downto 0) := (others => '0');
begin -- process uart_tx
if arst = '1' then -- asynchronous reset (active high)
rx_active <= '0';
rx_just_active <= false;
rx_data <= (others => (others => '0'));
rx_data_valid <= '0';
rx_bit_samples <= (others => '1');
rx_buffer <= (others => '0');
rx_clk_counter <= (others => '0');
rx_bit_counter <= (others => '0');
stop_err <= '0';
parity_err <= '0';
transient_err <= '0';
vr_rx_data_idx := (others => '0');
rx_data_full <= '1';
elsif rising_edge(clk) then -- rising clock edge
-- Perform read.
-- When there is data available in rx_data,
-- output the data when read enable detected.
if p2c.aro_rx_data_re = '1' and rx_data_valid = '1' then
rx_data <= x"00" & rx_data(3 downto 1);
rx_data_full <= '0';
if vr_rx_data_idx > 0 then
vr_rx_data_idx := vr_rx_data_idx - 1;
if vr_rx_data_idx = 0 then -- rx_data empty
rx_data_valid <= '0';
end if;
end if;
end if;
-- always shift in new synchronized serial data
rx_bit_samples <= rx_bit_samples(GC_CLOCKS_PER_BIT-2 downto 0) & rx_s(1);
-- look for enough GC_START_BITs in rx_bit_samples vector
if rx_active = '0' and
(find_num_hits(rx_bit_samples, GC_START_BIT) >= GC_CLOCKS_PER_BIT-1) then
rx_active <= '1';
rx_just_active <= true;
end if;
if rx_active = '0' then
-- defaults
stop_err <= '0';
parity_err <= '0';
transient_err <= '0';
rx_clk_counter <= (others => '0');
rx_bit_counter <= (others => '0');
else
-- We could check when we first enter whether we find the full number
-- of start samples and adjust the time we start rx_clk_counter by a
-- clock cycle - to hit the eye of the rx data best possible.
if rx_just_active then
if find_num_hits(rx_bit_samples, GC_START_BIT) = GC_CLOCKS_PER_BIT then
-- reset rx_clk_counter
rx_clk_counter <= (others => '0');
end if;
rx_just_active <= false;
else
-- loop clk counter
if rx_clk_counter <= GC_CLOCKS_PER_BIT - 1 then
rx_clk_counter <= rx_clk_counter + 1;
else
rx_clk_counter <= (others => '0');
end if;
end if;
-- shift in data, check for consistency and forward
if rx_clk_counter >= GC_CLOCKS_PER_BIT - 1 then
rx_bit_counter <= rx_bit_counter + 1;
if transient_error(rx_bit_samples, GC_CLOCKS_PER_BIT - 2) then
transient_err <= '1';
end if;
-- are we done? not counting the start bit
if to_integer(rx_bit_counter) >= 9 then
rx_active <= '0';
end if;
case to_integer(rx_bit_counter) is
when 0 to 7 =>
-- mux in new bit
rx_buffer(to_integer(rx_bit_counter)) <= find_most_repeated_bit(rx_bit_samples);
when 8 =>
-- check parity
if (odd_parity(rx_buffer) /= find_most_repeated_bit(rx_bit_samples)) then
parity_err <= '1';
end if;
when 9 =>
-- check stop bit, and end byte receive
if find_most_repeated_bit(rx_bit_samples) /= GC_STOP_BIT then
stop_err <= '1';
end if;
rx_data(to_integer(vr_rx_data_idx)) <= rx_buffer;
rx_data_valid <= '1'; -- ready for higher level protocol
if vr_rx_data_idx < 3 then
vr_rx_data_idx := vr_rx_data_idx + 1;
else
rx_data_full <= '1';
end if;
when others =>
rx_active <= '0';
end case;
end if;
end if;
end if;
end process uart_rx;
p_busy_assert : process(clk) is
begin
if rising_edge(clk) then
assert not (p2c.awo_tx_data_we = '1' and tx_ready = '0')
report "Trying to transmit new UART data while transmitter is busy"
severity error;
end if;
end process;
assert stop_err /= '1'
report "Stop bit error detected!"
severity error;
assert parity_err /= '1'
report "Parity error detected!"
severity error;
assert transient_err /= '1'
report "Transient error detected!"
severity error;
end architecture rtl;
| mit |
elainemielas/CVUT_BI-PNO | cvika/had/decoder.vhd | 1 | 670 | library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER is
port (
BIN_VALUE : in std_logic_vector (2 downto 0);
ONE_HOT : out std_logic_vector (7 downto 0)
);
end entity DECODER;
architecture DECODER_BODY of DECODER is
begin
DECODE : process (BIN_VALUE)
begin
case BIN_VALUE is
when "000" => ONE_HOT <= "00000001";
when "001" => ONE_HOT <= "00000010";
when "010" => ONE_HOT <= "00000100";
when "011" => ONE_HOT <= "00001000";
when "100" => ONE_HOT <= "00010000";
when "101" => ONE_HOT <= "00100000";
when "110" => ONE_HOT <= "01000000";
when others => ONE_HOT <= "10000000";
end case;
end process;
end architecture;
| mit |
Wynjones1/gbvhdl | scripts/out.vhd | 1 | 4142 | elsif mem_dout = "00000000" then -- NOP
elsif mem_dout = "00000111" then -- RLCA
elsif mem_dout = "00001111" then -- RRCA
elsif mem_dout = "00010000" then -- STOP
elsif mem_dout = "00010111" then -- RLA
elsif mem_dout = "00011000" then -- JR r8
elsif mem_dout = "00011111" then -- RRA
elsif mem_dout = "00100111" then -- DDA
elsif mem_dout = "00101111" then -- CPL
elsif mem_dout = "00110100" then -- INC (HL)
elsif mem_dout = "00110101" then -- DEC (HL)
elsif mem_dout = "00110111" then -- SCF
elsif mem_dout = "00111111" then -- CCF
elsif mem_dout = "01110110" then -- HALT
elsif mem_dout = "11000011" then -- JP d16
elsif mem_dout = "11001001" then -- RET
elsif mem_dout = "11001011" then -- CB
elsif mem_dout = "11001101" then -- CALL d16
elsif mem_dout = "11011001" then -- RETI
elsif mem_dout = "11101000" then -- ADD SP r8
elsif mem_dout = "11101001" then -- JP PC (HL)
elsif mem_dout = "11110011" then -- DI
elsif mem_dout = "11111011" then -- EI
elsif mem_dout = "00000010" then -- LD (BC) A
elsif mem_dout = "00001000" then -- LD (d16) SP
elsif mem_dout = "00001010" then -- LD A (BC)
elsif mem_dout = "00010010" then -- LD (DE) A
elsif mem_dout = "00011010" then -- LD A (DE)
elsif mem_dout = "00100010" then -- LD (HL++) A
elsif mem_dout = "00101010" then -- LD A (HL++)
elsif mem_dout = "00110010" then -- LD (HL--) A
elsif mem_dout = "00110110" then -- LD (HL) d8
elsif mem_dout = "00111010" then -- LD A (HL--)
elsif mem_dout = "11100010" then -- LD (C) A
elsif mem_dout = "11101010" then -- LD (d16) A
elsif mem_dout = "11110010" then -- LD A (C)
elsif mem_dout = "11111000" then -- LD HL SP + r8
elsif mem_dout = "11111001" then -- LD SP HL
elsif mem_dout = "11111010" then -- LD A (d16)
elsif mem_dout = "11100000" then -- LDH (d8) A
elsif mem_dout = "11110000" then -- LDH A (d8)
elsif mem_dout = "11010011" then -- INVALID
elsif mem_dout = "11011011" then -- INVALID
elsif mem_dout = "11011101" then -- INVALID
elsif mem_dout = "11100011" then -- INVALID
elsif mem_dout = "11100100" then -- INVALID
elsif mem_dout = "11101011" then -- INVALID
elsif mem_dout = "11101100" then -- INVALID
elsif mem_dout = "11101101" then -- INVALID
elsif mem_dout = "11110100" then -- INVALID
elsif mem_dout = "11111100" then -- INVALID
elsif mem_dout = "11111101" then -- INVALID
elsif mem_dout(7 downto 3) = "01110" then -- LD (HL) r'
elsif mem_dout(7 downto 5) = "001" and mem_dout(2 downto 0) = "000" then -- JR cc r8
elsif mem_dout(7 downto 5) = "110" and mem_dout(2 downto 0) = "000" then -- RET cc
elsif mem_dout(7 downto 5) = "110" and mem_dout(2 downto 0) = "010" then -- JP cc d16
elsif mem_dout(7 downto 5) = "110" and mem_dout(2 downto 0) = "100" then -- CALL cc d16
elsif mem_dout(7 downto 6) = "00" and mem_dout(2 downto 0) = "100" then -- INC r
elsif mem_dout(7 downto 6) = "00" and mem_dout(2 downto 0) = "101" then -- DEC r
elsif mem_dout(7 downto 6) = "00" and mem_dout(2 downto 0) = "110" then -- LD r n
elsif mem_dout(7 downto 6) = "01" and mem_dout(2 downto 0) = "110" then -- LD r (HL)
elsif mem_dout(7 downto 6) = "10" and mem_dout(2 downto 0) = "110" then -- f A (HL)
elsif mem_dout(7 downto 6) = "11" and mem_dout(2 downto 0) = "110" then -- f A n
elsif mem_dout(7 downto 6) = "11" and mem_dout(2 downto 0) = "111" then -- RST t
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "0001" then -- LD dd d16
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "0011" then -- INC ss
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "1001" then -- ADD HL ss
elsif mem_dout(7 downto 6) = "00" and mem_dout(3 downto 0) = "1011" then -- DEC ss
elsif mem_dout(7 downto 6) = "11" and mem_dout(3 downto 0) = "0001" then -- POP qq
elsif mem_dout(7 downto 6) = "11" and mem_dout(3 downto 0) = "0101" then -- PUSH qq
elsif mem_dout(7 downto 6) = "01" then -- LD r r'
elsif mem_dout(7 downto 6) = "10" then -- f A r'
| mit |
elainemielas/CVUT_BI-PNO | cvika/scit1/CONTROLLER.vhd | 2 | 1208 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CONTROLLER is
port(
CLK : in std_logic;
RESET : in std_logic;
TOP : in std_logic;
BOTTOM : in std_logic;
UP : out std_logic
);
end CONTROLLER;
architecture CONTROLLER_BODY of CONTROLLER is
type TYP_STAV is (NAHORU, DOLU);
signal STAV, DALSI_STAV : TYP_STAV;
begin
PRECHODY : process (TOP, BOTTOM, STAV)
begin
DALSI_STAV <= STAV;
case STAV is
when NAHORU => if TOP = '1' then DALSI_STAV <= DOLU;
--else DALSI_STAV <= NAHORU;
end if;
when DOLU => if BOTTOM = '1' then DALSI_STAV <= NAHORU;
--else DALSI_STAV <= DOLU;
end if;
end case;
end process;
VYSTUP : process (STAV, TOP, BOTTOM)
begin
case STAV is
when NAHORU => if TOP = '1' then UP <= '0';
else UP <= '1';
end if;
when DOLU => if BOTTOM = '1' then UP <= '1';
else UP <= '0';
end if;
end case;
end process;
REG : process (CLK)
begin
if CLK'event and CLK = '1' then
if RESET = '1' then STAV <= NAHORU;
else STAV <= DALSI_STAV;
end if;
end if;
end process;
end architecture;
| mit |
elainemielas/CVUT_THESIS | Spartan-3E/led_controller.vhd | 1 | 2156 | ----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 14:34:10 05/08/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: led_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity led_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end led_controller;
architecture Behavioral of led_controller is
type t_state is (read1, read2, read3, idle);
signal state, state_next : t_state;
signal delay, delay_next : integer range 0 to 2147483647;
signal addr, addr_next : std_logic_vector(rf_addr_w - 1 downto 0);
signal sum, sum_next : std_logic_vector(reg_width - 1 downto 0);
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= idle;
delay <= 0;
addr <= (others => '0');
sum <= (others => '0');
else
state <= state_next;
delay <= delay_next;
addr <= addr_next;
sum <= sum_next;
end if;
end if;
end process;
--reg 5 & 17 or 0
routing : process (state, delay, rf_data, addr, sum)
begin
state_next <= state;
delay_next <= delay;
addr_next <= addr;
sum_next <= sum;
case state is
when read1 =>
sum_next <= rf_data;
addr_next <= "10001";
state_next <= read2;
when read2 =>
sum_next <= sum and rf_data;
addr_next <= "00000";
state_next <= read3;
when read3 =>
sum_next <= sum or rf_data;
state_next <= idle;
when idle =>
if delay = 100 then
delay_next <= 0;
state_next <= read1;
addr_next <= "00101";
else delay_next <= delay + 1;
end if;
end case;
end process;
led <= sum(3 downto 0);
rf_addr <= addr;
end Behavioral;
| mit |
elainemielas/CVUT_THESIS | Spartan-3E/rate_generator.vhd | 1 | 1715 | ----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 15:21:19 03/20/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: rate_generator - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rate_generator is
generic(
dvsr : integer := 2604
-- divisor = 50000000 / (16 * baud)
-- 1200 -> 2604 +
-- 2400 -> 1302 +
-- 4800 -> 651 +
-- 9600 -> 326
-- 19200 -> 163
-- 38400 -> 81
-- 57600 -> 54 +
-- 115200 -> 27 +
-- 230400 -> 14
-- 460800 -> 7
-- 500000 -> 6
-- 576000 -> 5
-- 921600 -> 3
-- 1000000 -> 3 +
-- 1152000 -> 3
-- 1500000 -> 2 +
-- 2000000 -> 2
-- 2500000 -> 1
-- 3000000 -> 1 +
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : out std_logic
);
end rate_generator;
architecture Behavioral of rate_generator is
signal b_count : integer range 1 to dvsr := 1;
begin
b_clock : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
b_count <= 1;
b_edge <= '0';
elsif b_count = dvsr then
b_count <= 1;
b_edge <= '1';
else
b_count <= b_count + 1;
b_edge <= '0';
end if;
end if;
end process;
end Behavioral;
| mit |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_wrapper.vhd | 2 | 66283 | `protect begin_protected
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`protect end_protected
| mit |
touilleMan/scrips | instmemory.vhd | 1 | 12315 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:35 05/08/2012
-- Design Name:
-- Module Name: instmemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity instmemory is
Port ( Address : in STD_LOGIC_VECTOR (31 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end instmemory;
architecture Behavioral of instmemory is
begin
process (Address)
begin
case Address is
-- Main program
when "00000000000000000000000000000000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000000000100"=>Instruction<="00000000000000000011100000100101";
when "00000000000000000000000000001000"=>Instruction<="00000000000000000011000000100101";
when "00000000000000000000000000001100"=>Instruction<="00000000000000000010100000100101";
when "00000000000000000000000000010000"=>Instruction<="00000000000000000010000000100101";
when "00000000000000000000000000010100"=>Instruction<="00000000000000000001100000100101";
when "00000000000000000000000000011000"=>Instruction<="00000000000000000001000000100101";
when "00000000000000000000000000011100"=>Instruction<="00000000000000000000100000100101";
when "00000000000000000000000000100000"=>Instruction<="10101100000000000000000000010000";
when "00000000000000000000000000100100"=>Instruction<="10101100000000000000000000110001";
when "00000000000000000000000000101000"=>Instruction<="10101100000000000000000000110010";
when "00000000000000000000000000101100"=>Instruction<="10101100000000000000000000110011";
when "00000000000000000000000000110000"=>Instruction<="00110100000001000000000000000011";
when "00000000000000000000000000110100"=>Instruction<="00001000000000000000000000101111";
when "00000000000000000000000000111000"=>Instruction<="00110100000000010000000000011001";
when "00000000000000000000000000111100"=>Instruction<="00010000000000010000000000001001";
when "00000000000000000000000001000000"=>Instruction<="00100000001000011111111111111111";
when "00000000000000000000000001000100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001001000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001001100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001010000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001010100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001011000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001011100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001100000"=>Instruction<="00001000000000000000000000001111";
when "00000000000000000000000001100100"=>Instruction<="00010000000000110000000000000100";
when "00000000000000000000000001101000"=>Instruction<="00100000011000111111111111111111";
when "00000000000000000000000001101100"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000001110000"=>Instruction<="10101100000000010000000000110001";
when "00000000000000000000000001110100"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000001111000"=>Instruction<="10101100000000000000000000110001";
when "00000000000000000000000001111100"=>Instruction<="00010000100000001111111111111111";
when "00000000000000000000000010000000"=>Instruction<="10001100000000010000000000110100";
when "00000000000000000000000010000100"=>Instruction<="00110000001000010000000000111111";
when "00000000000000000000000010001000"=>Instruction<="00010000001000000000000000011000";
when "00000000000000000000000010001100"=>Instruction<="00100000100001001111111111111111";
when "00000000000000000000000010010000"=>Instruction<="00110100000000010000000000000011";
when "00000000000000000000000010010100"=>Instruction<="00010000001001000000000000001001";
when "00000000000000000000000010011000"=>Instruction<="00110100000000010000000000000010";
when "00000000000000000000000010011100"=>Instruction<="00010000001001000000000000001010";
when "00000000000000000000000010100000"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000010100100"=>Instruction<="00010000001001000000000000001011";
when "00000000000000000000000010101000"=>Instruction<="00001000000000000000000000111000";
when "00000000000000000000000010101100"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000010110000"=>Instruction<="10101100000000010000000000110001";
when "00000000000000000000000010110100"=>Instruction<="00110100000000110110000110101000";
when "00000000000000000000000010111000"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000010111100"=>Instruction<="00110100000000010000000001001111";
when "00000000000000000000000011000000"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011000100"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011001000"=>Instruction<="00110100000000010000000001011011";
when "00000000000000000000000011001100"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011010000"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011010100"=>Instruction<="00110100000000010000000000000110";
when "00000000000000000000000011011000"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011011100"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011100000"=>Instruction<="00110100000000010000000000111111";
when "00000000000000000000000011100100"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011101000"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011101100"=>Instruction<="10001100000001010000000000110000";
when "00000000000000000000000011110000"=>Instruction<="00110000101000010000000000000001";
when "00000000000000000000000011110100"=>Instruction<="00010000001000000000000000000011";
when "00000000000000000000000011111000"=>Instruction<="00110100000000010000000000000111";
when "00000000000000000000000011111100"=>Instruction<="10101100000000010000000000110011";
when "00000000000000000000000100000000"=>Instruction<="00001000000000000000000001000010";
when "00000000000000000000000100000100"=>Instruction<="10101100000000000000000000110011";
when "00000000000000000000000100001000"=>Instruction<="00010000110000000000000000000010";
when "00000000000000000000000100001100"=>Instruction<="00100000110001101111111111111111";
when "00000000000000000000000100010000"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000100010100"=>Instruction<="00110000101000010000000000000010";
when "00000000000000000000000100011000"=>Instruction<="00010000001000000000000000000001";
when "00000000000000000000000100011100"=>Instruction<="00001000000000000000000001100000";
when "00000000000000000000000100100000"=>Instruction<="00110000101000010000000000000100";
when "00000000000000000000000100100100"=>Instruction<="00010000001000000000000000000001";
when "00000000000000000000000100101000"=>Instruction<="00001000000000000000000001001110";
when "00000000000000000000000100101100"=>Instruction<="00110100000001100000000010100111";
when "00000000000000000000000100110000"=>Instruction<="10101100000001110000000000010000";
when "00000000000000000000000100110100"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000100111000"=>Instruction<="00110000111000010000000000001111";
when "00000000000000000000000100111100"=>Instruction<="00110100000000100000000000000001";
when "00000000000000000000000101000000"=>Instruction<="00010000001000100000000000000110";
when "00000000000000000000000101000100"=>Instruction<="00110100000000100000000000000010";
when "00000000000000000000000101001000"=>Instruction<="00010000001000100000000000000110";
when "00000000000000000000000101001100"=>Instruction<="00110100000000100000000000000100";
when "00000000000000000000000101010000"=>Instruction<="00010000001000100000000000000110";
when "00000000000000000000000101010100"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000101011000"=>Instruction<="00010000000000000000000000000110";
when "00000000000000000000000101011100"=>Instruction<="00110100000000010000000000000010";
when "00000000000000000000000101100000"=>Instruction<="00010000000000000000000000000100";
when "00000000000000000000000101100100"=>Instruction<="00110100000000010000000000000100";
when "00000000000000000000000101101000"=>Instruction<="00010000000000000000000000000010";
when "00000000000000000000000101101100"=>Instruction<="00110100000000010000000000001000";
when "00000000000000000000000101110000"=>Instruction<="00010000000000000000000000000000";
when "00000000000000000000000101110100"=>Instruction<="00110000111001111111111111110000";
when "00000000000000000000000101111000"=>Instruction<="00000000111000010011100000100101";
when "00000000000000000000000101111100"=>Instruction<="00010000000000001111111111101011";
when "00000000000000000000000110000000"=>Instruction<="00110000111000010000000011110000";
when "00000000000000000000000110000100"=>Instruction<="00110100000000100000000000010000";
when "00000000000000000000000110001000"=>Instruction<="00010000001000100000000000001100";
when "00000000000000000000000110001100"=>Instruction<="00110100000000100000000000100000";
when "00000000000000000000000110010000"=>Instruction<="00010000001000100000000000000100";
when "00000000000000000000000110010100"=>Instruction<="00110100000000100000000001000000";
when "00000000000000000000000110011000"=>Instruction<="00010000001000100000000000000100";
when "00000000000000000000000110011100"=>Instruction<="00110100000000100000000010000000";
when "00000000000000000000000110100000"=>Instruction<="00010000001000100000000000000100";
when "00000000000000000000000110100100"=>Instruction<="00110100000000010000000000010000";
when "00000000000000000000000110101000"=>Instruction<="00010000000000000000000000000110";
when "00000000000000000000000110101100"=>Instruction<="00110100000000010000000000100000";
when "00000000000000000000000110110000"=>Instruction<="00010000000000000000000000000100";
when "00000000000000000000000110110100"=>Instruction<="00110100000000010000000001000000";
when "00000000000000000000000110111000"=>Instruction<="00010000000000000000000000000010";
when "00000000000000000000000110111100"=>Instruction<="00110100000000010000000010000000";
when "00000000000000000000000111000000"=>Instruction<="00010000000000000000000000000000";
when "00000000000000000000000111000100"=>Instruction<="00110000111001111111111100001111";
when "00000000000000000000000111001000"=>Instruction<="00000000111000010011100000100101";
when "00000000000000000000000111001100"=>Instruction<="00010000000000001111111111010100";
when others => Instruction <= "00000000000000000000000000000000";
End case;
end process;
end Behavioral;
| mit |
dtysky/LD3320_AXI | src/LIST/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_fsm.vhd | 2 | 83900 | `protect begin_protected
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`protect encrypt_agent = "XILINX"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
| mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_wb_controller.vhd | 1 | 10257 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_wb_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_wb_controller.vhd |
-- |
-- Description The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to |
-- the user's STBs. |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 21/01/2011 |
-- Version v0.01 |
-- Depends on wf_production |
---------------- |
-- Last changes |
-- 21/01/2011 v0.011 EG changed registering |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_wb_controller
--=================================================================================================
entity wf_wb_controller is port(
-- INPUTS
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; -- WISHBONE clock
wb_rst_i : in std_logic; -- WISHBONE reset
wb_stb_i : in std_logic; -- WISHBONE strobe
wb_cyc_i : in std_logic; -- WISHBONE cycle
wb_we_i : in std_logic; -- WISHBONE write enable
wb_adr_id_i : in std_logic_vector (2 downto 0); -- 3 first bits of WISHBONE address
-- OUTPUTS
-- Signal from the wf_production_unit
wb_ack_prod_p_o : out std_logic; -- response to a write cycle
-- latching moment of wb_dat_i
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_p_o : out std_logic); -- WISHBONE acknowledge
end entity wf_wb_controller;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_wb_controller is
signal s_wb_ack_write_p, s_wb_ack_read_p, s_wb_stb_r_edge_p : std_logic;
signal s_wb_we_synch, s_wb_cyc_synch : std_logic_vector (2 downto 0);
signal s_wb_stb_synch : std_logic_vector (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
-- Synchronization of the WISHBONE control signals: stb, cyc, we.
WISHBONE_inputs_synchronization: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then -- wb_rst is not buffered to comply with WISHBONE rule 3.15
s_wb_stb_synch <= (others => '0');
s_wb_cyc_synch <= (others => '0');
s_wb_we_synch <= (others => '0');
else
s_wb_stb_synch <= s_wb_stb_synch (2 downto 0) & wb_stb_i;
s_wb_cyc_synch <= s_wb_cyc_synch (1 downto 0) & wb_cyc_i;
s_wb_we_synch <= s_wb_we_synch (1 downto 0) & wb_we_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_wb_stb_r_edge_p <= (not s_wb_stb_synch(3)) and s_wb_stb_synch(2);
---------------------------------------------------------------------------------------------------
-- ACK outputs Generation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Generation of the wb_ack_write_p signal (acknowledgement from WISHBONE Slave of the write cycle,
-- as a response to the master's storbe). The 1 wb_clk-wide pulse is generated if the wb_cyc and
-- wb_we are asserted and the WISHBONE input address corresponds to an address in the Produced
-- memory block.
s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_synch (2) = '1') and
(s_wb_cyc_synch(2) = '1') and
(wb_adr_id_i = "010")) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Generation of the wb_ack_read_p signal (acknowledgement from WISHBONE Slave of the read cycle,
-- as a response to the master's strobe). The 1 wb_clk-wide pulse is generated if the wb_cyc is
-- asserted, the wb_we is deasserted and the WISHBONE input address corresponds to an address in
-- the Consumed memory block.
s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_synch(2) = '1') and
(s_wb_we_synch(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00")) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output registrers
WB_ACK_Output_Reg: process (wb_clk_i)
begin
if rising_edge (wb_clk_i) then
if wb_rst_i = '1' then
wb_ack_p_o <= '0';
wb_ack_prod_p_o <= '0';
else
wb_ack_p_o <= s_wb_ack_read_p or s_wb_ack_write_p;
wb_ack_prod_p_o <= s_wb_ack_write_p;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit |
touilleMan/scrips | control_bench.vhd | 1 | 2967 | -- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/control.sch - Thu Jun 7 17:34:08 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY control_control_sch_tb IS
END control_control_sch_tb;
ARCHITECTURE behavioral OF control_control_sch_tb IS
COMPONENT control
PORT( Opcode : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
ALUOp : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
ALUSrc : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC;
RegDst : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
Jump : OUT STD_LOGIC);
END COMPONENT;
SIGNAL Opcode : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL ALUOp : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL ALUSrc : STD_LOGIC;
SIGNAL MemtoReg : STD_LOGIC;
SIGNAL RegWrite : STD_LOGIC;
SIGNAL RegDst : STD_LOGIC;
SIGNAL MemRead : STD_LOGIC;
SIGNAL MemWrite : STD_LOGIC;
SIGNAL Branch : STD_LOGIC;
SIGNAL Jump : STD_LOGIC;
BEGIN
UUT: control PORT MAP(
Opcode => Opcode,
ALUOp => ALUOp,
ALUSrc => ALUSrc,
MemtoReg => MemtoReg,
RegWrite => RegWrite,
RegDst => RegDst,
MemRead => MemRead,
MemWrite => MemWrite,
Branch => Branch,
Jump => Jump
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
-- Test simple R add instruction
-- ALUOp : 010, enabled : RegDst, RegWrite
Opcode <= "000000";
wait for 1us;
-- Test lw
-- ALUOp : 000, enabled : ALUSrc, MemtoReg, RegWrite, MemRead
Opcode <= "100011";
wait for 1us;
-- Test sw
-- ALUOp : 000, enabled : ALUSrc, MemWrite
Opcode <= "101011";
wait for 1us;
-- Test addi
-- ALUOp : 000, enabled : ALUSrc, RegWrite
Opcode <= "001000";
wait for 1us;
-- Test ori
-- ALUOp : 101, enabled : ALUSrc, RegWrite
Opcode <= "001101";
wait for 1us;
-- Test andi
-- ALUOp : 100, enabled : ALUSrc, RegWrite
Opcode <= "001100";
wait for 1us;
-- Test beq
-- ALUOp : 001, enabled : Branch
Opcode <= "000100";
wait for 1us;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
| mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_reset_unit.vhd | 1 | 39205 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_reset_unit |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_reset_unit.vhd |
-- |
-- Description The unit is responsible for the generation of the: |
-- |
-- o nanoFIP internal reset that resets all nanoFIP's logic, apart from WISHBONE. |
-- It is asserted: |
-- - after the assertion of the "nanoFIP User Interface General signal" RSTIN; |
-- in this case it stays active for 4 uclk cycles |
-- - after the reception of a var_rst with its 1st application-data byte |
-- containing the station's address; in this case as well it stays active for |
-- 4 uclk cycles |
-- - during the activation of the "nanoFIP User Interface General signal" RSTPON;|
-- in this case it stays active for as long as the RSTPON is active. |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | nFIP_rst |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- |
-- o FIELDRIVE reset: nanoFIP FIELDRIVE output FD_RSTN |
-- Same as the nanoFIP internal reset, it can be activated by the RSTIN, |
-- the var_rst or the RSTPON. |
-- Regarding the activation time, for the first two cases (RSTIN, var_rst) it stays|
-- asserted for 4 FD_TXCK cycles whereas in the case of the RSTPON, it stays active|
-- for as long as the RSTPON is active. |
-- |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | FD_RSTN |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- o reset to the external logic: "nanoFIP User Interface, General signal" RSTON |
-- It is asserted after the reception of a var_rst with its 2nd data byte |
-- containing the station's address. |
-- It stays active for 8 uclk cycles. |
-- _________ |
-- assert_RSTON_p | | RSTON |
-- ________| FSM |_________________________________ |
-- | var_rst | |
-- |__________| |
-- |
-- o nanoFIP internal reset for the WISHBONE logic: |
-- It is asserted after the assertion of the "nanoFIP User Interface, WISHBONE |
-- Slave" input RST_I or of the "nanoFIP User Interface General signal" RSTPON. |
-- It stays asserted for as long as the RST_I or RSTPON stay asserted. |
-- |
-- RSTPON |
-- __________________________ \ \ |
-- \ \ wb_rst |
-- RST_I |OR|____________________ |
-- __________________________ / / |
-- / / |
-- |
-- Notes: |
-- - The input signal RSTIN is considered only if it has been active for at least |
-- 4 uclk cycles; the functional specs define 8 uclks, but in reality we check for 4.|
-- - The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the wf_cons_outcome |
-- unit only after the sucessful validation of the frame structure and of the |
-- application-data bytes of the var_rst. |
-- - The RSTPON (Power On Reset generated with an RC circuit) removal is synchronized |
-- with both uclk and wb_clk. |
-- |
-- The unit implements 2 state machines: one for resets coming from RSTIN |
-- and one for resets coming from a var_rst. |
-- |
-- |
-- Authors Erik van der Bij ([email protected]) |
-- Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 11/2011 |
-- Version v0.03 |
-- Depends on wf_consumption |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added |
-- fd_rstn_o, nfip_rst_o enabled only if rstin has been active for>4 uclk |
-- 01/2011 v0.03 EG PoR added; signals assert_rston_p_i & rst_nfip_and_fd_p_i are inputs |
-- treated in the wf_cons_outcome; 2 state machines created; clean-up |
-- PoR also for internal WISHBONE resets |
-- 02/2011 v0.031 EG state nFIP_OFF_FD_OFF added |
-- 11/2011 v0.032 EG added s_rstin_c_is_full, s_var_rst_c_is_full signals that reset FSMs |
-- corrections on # cycles nFIP_rst is activated (was 6, now 4) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_reset_unit
--=================================================================================================
entity wf_reset_unit is port(
-- INPUTS
-- nanoFIP User Interface General signals
uclk_i : in std_logic; -- 40 MHz clock
rstin_a_i : in std_logic; -- initialization control, active low
rstpon_a_i : in std_logic; -- Power On Reset, active low
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- nanoFIP User Interface WISHBONE Slave
rst_i : in std_logic; -- WISHBONE reset
wb_clk_i : in std_logic; -- WISHBONE clock
-- Signal from the wf_consumption unit
rst_nfip_and_fd_p_i : in std_logic; -- indicates that a var_rst with its 1st byte
-- containing the station's address has been
-- correctly received
assert_rston_p_i : in std_logic; -- indicates that a var_rst with its 2nd byte
-- containing the station's address has been
-- correctly received
-- OUTPUTS
-- nanoFIP internal reset, to all the units
nfip_rst_o : out std_logic; -- nanoFIP internal reset, active high
-- resets all nanoFIP logic, apart from the WISHBONE
-- Signal to the wf_wb_controller
wb_rst_o : out std_logic; -- reset of the WISHBONE logic
-- nanoFIP User Interface General signal output
rston_o : out std_logic; -- reset output, active low
-- nanoFIP FIELDRIVE output
fd_rstn_o : out std_logic); -- FIELDRIVE reset, active low
end entity wf_reset_unit;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_reset_unit is
-- RSTIN and RSTPON synchronizers
signal s_rsti_synch : std_logic_vector (2 downto 0);
signal s_wb_por_synch, s_u_por_synch : std_logic_vector (1 downto 0);
-- FSM for RSTIN
type rstin_st_t is (IDLE, RSTIN_EVAL, nFIP_ON_FD_ON, nFIP_OFF_FD_ON, nFIP_OFF_FD_OFF);
signal rstin_st, nx_rstin_st : rstin_st_t;
-- RSTIN counter
signal s_rstin_c, s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_three : std_logic;
signal s_rstin_c_is_seven, s_rstin_c_is_4txck : std_logic;
signal s_rstin_c_is_full : std_logic;
-- resets generated after a RSTIN
signal s_rstin_nfip, s_rstin_fd : std_logic;
-- FSM for var_rst
type var_rst_st_t is (VAR_RST_IDLE, VAR_RST_RSTON_ON, VAR_RST_nFIP_ON_FD_ON_RSTON_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_ON, VAR_RST_nFIP_ON_FD_ON,
VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF);
signal var_rst_st, nx_var_rst_st : var_rst_st_t;
-- var_rst counter
signal s_var_rst_c_reinit, s_var_rst_c_is_three : std_logic;
signal s_var_rst_c_is_seven, s_var_rst_c_is_4txck : std_logic;
signal s_var_rst_c_is_full : std_logic;
-- resets generated after a var_rst
signal s_var_rst_fd, s_var_rst_nfip, s_rston : std_logic;
-- info needed to define the length of the FD_RSTN
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_transm_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks of a
-- transmission period
s_txck_four_periods <= resize(s_transm_period, s_txck_four_periods'length) sll 1;-- # uclk ticks
-- of 2 transm.
-- periods = 4
-- FD_TXCK periods
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTIN synchronization with the uclk, using a set of 3 registers.
RSTIN_uclk_Synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
s_rsti_synch <= s_rsti_synch (1 downto 0) & not rstin_a_i;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTPON synchronization, with the wb_clk.
-- The second flip-flop is used to remove metastabilities.
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_wb_por_synch <= (others => '1');
elsif rising_edge (wb_clk_i) then
s_wb_por_synch <= s_wb_por_synch(0) & '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTPON synchronization, with the uclk.
-- The second flip-flop is used to remove metastabilities.
PoR_uclk_Synchronizer: process (uclk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_u_por_synch <= (others => '1');
elsif rising_edge (uclk_i) then
s_u_por_synch <= s_u_por_synch(0) & '0';
end if;
end process;
---------------------------------------------------------------------------------------------------
-- RSTIN --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RSTIN FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- The FSM is following the "User Interface, General signal" RSTIN and checks whether it stays
-- active for at least 4 uclk cycles; if so, it enables the nanoFIP internal reset (s_rstin_nfip)
-- and the FIELDRIVE reset (s_rstin_fd). The nanoFIP internal reset stays active for 4 uclk cycles
-- and the FIELDRIVE for 4 FD_TXCK cycles.
-- The state machine can be reset by the Power On Reset and the variable reset.
-- Note: The same counter is used for the evaluation of the RSTIN (if it is >= 4 uclk) and for the
-- generation of the two reset signals.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process RSTIN_FSM_Sync: Storage of the current state of the FSM.
RSTIN_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or rst_nfip_and_fd_p_i = '1' or s_rstin_c_is_full = '1' then
rstin_st <= IDLE;
else
rstin_st <= nx_rstin_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_State_Transitions: definition of the state
-- transitions of the FSM.
RSTIN_FSM_Comb_State_Transitions: process (rstin_st, s_rsti_synch(2), s_rstin_c_is_three,
s_rstin_c_is_seven, s_rstin_c_is_4txck)
begin
case rstin_st is
when IDLE =>
if s_rsti_synch(2) = '1' then -- RSTIN active
nx_rstin_st <= RSTIN_EVAL;
else
nx_rstin_st <= IDLE;
end if;
when RSTIN_EVAL =>
if s_rsti_synch(2) = '0' then -- RSTIN deactivated
nx_rstin_st <= IDLE;
else
if s_rstin_c_is_three = '1' then -- counting the uclk cycles that
nx_rstin_st <= nFIP_ON_FD_ON; -- RSTIN is active
else
nx_rstin_st <= RSTIN_EVAL;
end if;
end if;
when nFIP_ON_FD_ON =>
if s_rstin_c_is_seven = '1' then -- nanoFIP internal reset and
nx_rstin_st <= nFIP_OFF_FD_ON; -- FIELDRIVE reset active for
-- 4 uclk cycles
else
nx_rstin_st <= nFIP_ON_FD_ON;
end if;
when nFIP_OFF_FD_ON =>
-- nanoFIP internal reset deactivated
if s_rstin_c_is_4txck = '1' then -- FIELDRIVE reset continues being active
nx_rstin_st <= nFIP_OFF_FD_OFF;-- until 4 FD_TXCK cycles have passed
else
nx_rstin_st <= nFIP_OFF_FD_ON;
end if;
when nFIP_OFF_FD_OFF =>
if s_rsti_synch(2) = '1' then -- RSTIN still active
nx_rstin_st <= nFIP_OFF_FD_OFF;
else
nx_rstin_st <= IDLE;
end if;
when OTHERS =>
nx_rstin_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
-- the FSM. The process is handling the signals for the nanoFIP internal reset (s_rstin_nfip)
-- and the FIELDRIVE reset (s_rstin_fd), as well as the inputs of the RSTIN_free_counter.
RSTIN_FSM_Comb_Output_Signals: process (rstin_st)
begin
case rstin_st is
when IDLE =>
s_rstin_c_reinit <= '1'; -- counter initialized
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when RSTIN_EVAL =>
s_rstin_c_reinit <= '0'; -- counting until 4
-- if RSTIN is active
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when nFIP_ON_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting 4 uclk cycles
-------------------------------------
s_rstin_fd <= '1'; -- FIELDRIVE active
s_rstin_nfip <= '1'; -- nFIP internal active
-------------------------------------
when nFIP_OFF_FD_ON =>
s_rstin_c_reinit <= '0'; -- free counter counting until 4 FD_TXCK
s_rstin_nfip <= '0';
-------------------------------------
s_rstin_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when nFIP_OFF_FD_OFF =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_nfip <= '0';
s_rstin_fd <= '0';
when OTHERS =>
s_rstin_c_reinit <= '1'; -- no counting
s_rstin_fd <= '0';
s_rstin_nfip <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter: the counter counts from 0 to 4 FD_TXCK.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_rstin_c_is_full will be activated and the FSM will be reset.
RSTIN_free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_rstin_c_reinit,
counter_incr_i => '1',
----------------------------------------
counter_is_full_o => s_rstin_c_is_full,
counter_o => s_rstin_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_rstin_c_is_three <= '1' when s_rstin_c = to_unsigned(3, s_rstin_c'length) else '0';
s_rstin_c_is_seven <= '1' when s_rstin_c = to_unsigned(7, s_rstin_c'length) else '0';
s_rstin_c_is_4txck <= '1' when s_rstin_c = s_txck_four_periods + 3 else '0';
-- +3 bc of the first 4 RSTIN evaluation cycles
---------------------------------------------------------------------------------------------------
-- var_rst --
---------------------------------------------------------------------------------------------------
-- Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- If after the reception of a var_rst the signal assert_rston_p_i is asserted, the FSM
-- asserts the "nanoFIP user Interface General signal" RSTON for 8 uclk cycles.
-- If after the reception of a var_rst the signal rst_nfip_and_fd_p_i is asserted, the FSM
-- asserts the nanoFIP internal reset (s_var_rst_nfip) for 4 uclk cycles and the
-- "nanoFIP FIELDRIVE" output (s_var_rst_fd) for 4 FD_TXCK cycles.
-- If after the reception of a var_rst both assert_rston_p_i and rst_nfip_and_fd_p_i
-- are asserted, the FSM asserts the s_var_rst_nfip for 2 uclk cycles, the RSTON for 8
-- uclk cycles and the s_var_rst_fd for 4 FD_TXCK cycles.
-- The same counter is used for all the countings!
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Resets_after_a_var_rst_synch: Storage of the current state of the FSM
-- The state machine can be reset by the Power On Reset and the nanoFIP internal reset from RSTIN.
Resets_after_a_var_rst_synch: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por_synch(1) = '1' or s_rstin_nfip = '1' or s_var_rst_c_is_full = '1' then
var_rst_st <= VAR_RST_IDLE;
else
var_rst_st <= nx_var_rst_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Resets_after_a_var_rst_Comb_State_Transitions: definition of the
-- state transitions of the FSM.
Resets_after_a_var_rst_Comb_State_Transitions: process (var_rst_st, rst_nfip_and_fd_p_i,
assert_rston_p_i, s_var_rst_c_is_three,
s_var_rst_c_is_seven,
s_var_rst_c_is_4txck)
begin
case var_rst_st is
when VAR_RST_IDLE =>
if assert_rston_p_i = '1' and rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
elsif assert_rston_p_i = '1' then
nx_var_rst_st <= VAR_RST_RSTON_ON;
elsif rst_nfip_and_fd_p_i = '1' then
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
else
nx_var_rst_st <= VAR_RST_IDLE;
end if;
when VAR_RST_RSTON_ON => -- for 8 uclk cycles
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= VAR_RST_RSTON_ON;
end if;
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON => -- for 4 uclk cycles
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
else
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON_RSTON_ON;
end if;
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON => -- for 4 more uclk cycles
if s_var_rst_c_is_seven = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_ON;
end if;
when VAR_RST_nFIP_ON_FD_ON => -- for 4 uclk cycles
if s_var_rst_c_is_three = '1' then
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
else
nx_var_rst_st <= VAR_RST_nFIP_ON_FD_ON;
end if;
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF => -- until 4 TXCK
if s_var_rst_c_is_4txck = '1' then
nx_var_rst_st <= VAR_RST_IDLE;
else
nx_var_rst_st <= VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF;
end if;
when OTHERS =>
nx_var_rst_st <= VAR_RST_IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process RSTIN_FSM_Comb_Output_Signals: definition of the output signals of
-- the FSM. The process is managing the signals for the nanoFIP internal reset and the FIELDRIVE
-- reset, as well as the arguments of the counter.
rst_var_FSM_Comb_Output_Signals: process (var_rst_st)
begin
case var_rst_st is
when VAR_RST_IDLE =>
s_var_rst_c_reinit <= '1'; -- counter initialized
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
when VAR_RST_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 8 uclk cycles
-------------------------------------
s_rston <= '0'; -- RSTON active
-------------------------------------
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
when VAR_RST_nFIP_ON_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
-------------------------------------
s_rston <= '0'; -- RSTON active
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_OFF_FD_ON_RSTON_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_var_rst_nfip <= '0';
-------------------------------------
s_rston <= '0'; -- RSTON active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_ON_FD_ON =>
s_var_rst_c_reinit <= '0'; -- counting 4 uclk cycles
s_rston <= '1';
-------------------------------------
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when VAR_RST_nFIP_OFF_FD_ON_RSTON_OFF =>
s_var_rst_c_reinit <= '0'; -- counting until 4 FD_TXCK cycles
s_rston <= '1';
s_var_rst_nfip <= '0';
-------------------------------------
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
when OTHERS =>
s_var_rst_c_reinit <= '1'; -- no counting
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter:
-- the counter counts from 0 to 8, if only assert_RSTON_p has been activated, or
-- from 0 to 4 * FD_TXCK, if rst_nfip_and_fd_p_i has been activated.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_var_rst_c_is_full will be activated and the FSM will be reset.
free_counter: wf_incr_counter
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var_rst_c_reinit,
counter_incr_i => '1',
----------------------------------------
counter_is_full_o => s_var_rst_c_is_full,
counter_o => s_var_rst_c);
----------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_var_rst_c_is_seven <= '1' when s_var_rst_c = to_unsigned(7, s_var_rst_c'length) else '0';
s_var_rst_c_is_three <= '1' when s_var_rst_c = to_unsigned(3, s_var_rst_c'length) else '0';
s_var_rst_c_is_4txck <= '1' when s_var_rst_c = s_txck_four_periods -1 else '0';
---------------------------------------------------------------------------------------------------
-- Output Signals --
---------------------------------------------------------------------------------------------------
wb_rst_o <= rst_i or s_wb_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
nfip_rst_o <= s_rstin_nfip or s_var_rst_nfip or s_u_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Flip-flop with asynchronous reset to be sure that whenever nanoFIP is reset the user is not
RSTON_Buffering: process (uclk_i, s_u_por_synch(1), s_rstin_nfip, s_var_rst_nfip)
begin
if s_rstin_nfip = '1' or s_var_rst_nfip = '1' or s_u_por_synch(1) = '1' then
rston_o <= '1';
elsif rising_edge (uclk_i) then
rston_o <= s_rston;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE reset
FD_RST_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
fd_rstn_o <= not (s_rstin_fd or s_var_rst_fd or s_u_por_synch(1));
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/nf/nf_transmitter.vhd | 1 | 3866 | -------------------------------------------------------------------------------
--! @file nf_transmitter.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-23
--! @brief NanoFIP transmitter.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.nf_pkg.all;
--! @brief Entity declaration of nf_transmitter
--! @details
--! All critical registers and the paged memory are concatenated and
--! transmitted to the gateway.
entity nf_transmitter is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Control signals
--! @{
--! Start transmission
start_i : in std_ulogic;
--! @}
--! @name Transmitter
--! @{
--! Address
tx_addr_o : out std_ulogic_vector(6 downto 0);
--! Data
tx_data_o : out std_ulogic_vector(7 downto 0);
--! Data enable
tx_data_en_o : out std_ulogic;
--! Busy flag
tx_busy_i : in std_ulogic;
--! Done flag
tx_done_i : in std_ulogic;
--! @}
--! @name Memory
--! @{
--! Read enable
mem_rd_en_o : out std_ulogic;
--! Address
mem_addr_o : out std_ulogic_vector(6 downto 0);
--! Data
mem_data_i : in std_ulogic_vector(7 downto 0);
--! Data enable
mem_data_en_i : in std_ulogic);
--! @}
end entity nf_transmitter;
--! RTL implementation of nf_transmitter
architecture rtl of nf_transmitter is
---------------------------------------------------------------------------
--! @name Types and Constants
---------------------------------------------------------------------------
--! @{
constant nf_addr_offset_c : natural := 2;
constant num_bytes_c : natural := 124;
--! @}
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal addr : unsigned(tx_addr_o'range);
signal rd_en : std_ulogic;
signal busy : std_ulogic;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
tx_addr_o <= std_ulogic_vector(addr + nf_addr_offset_c);
tx_data_o <= mem_data_i;
tx_data_en_o <= mem_data_en_i;
mem_rd_en_o <= rd_en;
mem_addr_o <= std_ulogic_vector(addr);
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
addr <= to_unsigned(0, addr'length);
rd_en <= '0';
busy <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Defaults
rd_en <= '0';
if busy = '0' and tx_busy_i = '0' and start_i = '1' then
rd_en <= '1';
busy <= '1';
elsif busy = '1' and tx_done_i = '1' then
busy <= '0';
if to_integer(addr) < num_bytes_c - 1 then
rd_en <= '1';
busy <= '1';
end if;
end if;
if start_i = '1' then
addr <= to_unsigned(0, addr'length);
elsif tx_done_i = '1' then
addr <= addr + 1;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| mit |
touilleMan/scrips | datamemory.vhd | 1 | 3243 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:55:03 05/08/2012
-- Design Name:
-- Module Name: datamemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity datamemory is
Port ( Address : in STD_LOGIC_VECTOR (31 downto 0);
WriteData : in STD_LOGIC_VECTOR (31 downto 0);
MemWrite : in STD_LOGIC;
MemRead : in STD_LOGIC;
ReadData : out STD_LOGIC_VECTOR (31 downto 0);
O_LMotor : out STD_LOGIC_VECTOR (3 downto 0);
O_RMotor : out STD_LOGIC_VECTOR (3 downto 0);
I_Sensors : in STD_LOGIC_VECTOR (6 downto 0);
O_Leds : out STD_LOGIC_VECTOR (6 downto 0);
I_Rf : in STD_LOGIC_VECTOR (2 downto 0);
O_Buzzer : out STD_LOGIC;
O_Seg : out STD_LOGIC_VECTOR (7 downto 0);
O_El_7l :out STD_LOGIC_VECTOR (2 downto 0);
I_St_7l : in STD_LOGIC_VECTOR (5 downto 0);
I_Clock : in STD_LOGIC
);
end datamemory;
architecture Behavioral of datamemory is
begin
-- Memory Map
-- 0x000
-- 0x001
-- 0x010 Set motors
-- 0x020 Set leds
-- 0x021 Get Sensors
-- 0x030 Get RF
-- 0x031 Set BUZZER
-- 0x032 Set SEG
-- 0x033 Set EL_7L
-- 0x034 Get ST_7L
read : process (I_Clock)
begin
if (I_Clock'Event and I_Clock = '1') then
if (MemRead = '1') then
case Address is
when "00000000000000000000000000100001"=>
ReadData(6 downto 0) <= I_Sensors(6 downto 0);
ReadData(31 downto 7) <= "0000000000000000000000000";
when "00000000000000000000000000110000"=>
ReadData(2 downto 0) <= I_Rf(2 downto 0);
ReadData(31 downto 3) <= "00000000000000000000000000000";
when "00000000000000000000000000110100"=>
ReadData(5 downto 0) <= I_St_7l(5 downto 0);
ReadData(31 downto 6) <= "00000000000000000000000000";
when others => ReadData <= "00000000000000000000000000000000";
end case;
end if;
end if;
end process;
write : process(I_Clock)
begin
if (I_Clock'Event and I_Clock = '1') then
if (MemWrite = '1') then
case Address is
when "00000000000000000000000000010000"=>
O_RMotor <= WriteData(3 downto 0);
O_LMotor <= WriteData(7 downto 4);
when "00000000000000000000000000100000"=>
O_Leds <= WriteData(6 downto 0);
when "00000000000000000000000000110001"=>
O_Buzzer <= WriteData(0);
when "00000000000000000000000000110010"=>
O_Seg <= WriteData(7 downto 0);
when "00000000000000000000000000110011"=>
O_El_7l <= WriteData(2 downto 0);
when others =>
end case;
end if;
end if;
end process;
end Behavioral;
| mit |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/fetch_page/fetch_page_ow.vhd | 1 | 5203 | -------------------------------------------------------------------------------
--! @file fetch_page_ow.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare one-wire page for NanoFIP communication.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! @brief Entity declaration of fetch_page_ow
--! @details
--! This component prepares the one-wire page for the NanoFIP response.
entity fetch_page_ow is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Commands
--! @{
--! Start flag
start_i : in std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! Memory index
idx_i : in std_ulogic_vector(14 downto 0);
--! @}
--! @name Memory page interface
--! @{
--! Address
page_addr_o : out std_ulogic_vector(5 downto 0);
--! Write enable
page_wr_en_o : out std_ulogic;
--! Data output
page_data_o : out std_ulogic_vector(7 downto 0);
--! Done flag
page_done_i : in std_ulogic;
--! @}
--! @name One-wire data
--! @{
--! Address
ow_addr_o : out std_ulogic_vector(5 downto 0);
--! Read enable
ow_rd_en_o : out std_ulogic;
--! Data input
ow_data_i : in std_ulogic_vector(79 downto 0);
--! Data input enable
ow_data_en_i : in std_ulogic);
--! @}
end entity fetch_page_ow;
--! RTL implementation of fetch_page_ow
architecture rtl of fetch_page_ow is
---------------------------------------------------------------------------
--! @name Types and Constants
---------------------------------------------------------------------------
--! @{
type state_t is (IDLE, STORE, DONE);
type reg_t is record
state : state_t;
addr : unsigned(5 downto 0);
data : std_ulogic_vector(79 downto 0);
wr_en : std_ulogic;
rd_en : std_ulogic;
done : std_ulogic;
end record;
constant init_c : reg_t := (
state => IDLE,
addr => (others => '0'),
data => (others => '0'),
wr_en => '0',
rd_en => '0',
done => '0');
--! @}
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal next_reg : reg_t;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
page_addr_o <= std_ulogic_vector(reg.addr);
page_wr_en_o <= reg.wr_en;
page_data_o <= reg.data(7 downto 0);
ow_addr_o <= idx_i(3 downto 0) & std_ulogic_vector(reg.addr(5 downto 4));
ow_rd_en_o <= reg.rd_en;
done_o <= reg.done;
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
---------------------------------------------------------------------------
-- Combinatorics
---------------------------------------------------------------------------
comb : process (reg, start_i, page_done_i, ow_data_i, ow_data_en_i) is
begin -- comb
-- Defaults
next_reg <= reg;
next_reg.rd_en <= '0';
next_reg.wr_en <= '0';
next_reg.done <= '0';
case reg.state is
when IDLE =>
if start_i = '1' then
next_reg.rd_en <= '1';
next_reg.state <= STORE;
end if;
when STORE =>
if ow_data_en_i = '1' then
next_reg.data <= ow_data_i;
next_reg.wr_en <= '1';
next_reg.state <= DONE;
end if;
when DONE =>
if page_done_i = '1' then
if to_integer(reg.addr) < 63 then
next_reg.addr <= reg.addr + 1;
if to_integer(reg.addr(3 downto 0)) < 15 then
next_reg.wr_en <= '1';
next_reg.data <= x"00" & reg.data(reg.data'high downto reg.data'low + 8);
else
next_reg.rd_en <= '1';
next_reg.state <= STORE;
end if;
else
next_reg <= init_c;
next_reg.done <= '1';
end if;
end if;
end case;
end process comb;
end architecture rtl;
| mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_prod_data_lgth_calc.vhd | 1 | 13111 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_prod_data_lgth_calc |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_prod_data_lgth_calc.vhd |
-- |
-- Description Calculation of the number of bytes, after the FSS and before the FCS, that have to|
-- be transferred when a variable is produced (var_pres, var_identif, var_3, var_5) |
-- As the following figure indicates, in detail, the unit adds-up: |
-- o 1 byte RP_DAT.CTRL, |
-- o 1 byte RP_DAT.Data.PDU_TYPE, |
-- o 1 byte RP_DAT.Data.LGTH, |
-- o 1-124 RP_DAT.Data.User_Data bytes according to the variable type: |
-- - var_pres: 5 bytes |
-- - var_pres: 8 bytes |
-- - var_5 : 1 byte |
-- - var_3 : 2-124 bytes defined by the "nanoFIP User Interface,General signal"|
-- SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH, |
-- o 1 byte RP_DAT.Data.nanoFIP_status, always for a var_5 |
-- and for a var_3, if the "nanoFIP User |
-- Interface General signal"NOSTAT is negated,|
-- o 1 byte RP_DAT.Data.MPS_status, for a var_3 and a var_5 |
-- |
-- |
-- Reminder: |
-- |
-- Produced RP_DAT frame structure : |
-- ||--------------------- Data ---------------------|| |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- |-----P3_LGTH-----| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 09/12/2010 |
-- Version v0.02 |
-- Depends on wf_engine_control |
---------------- |
-- Last changes |
-- 12/2010 v0.02 EG code cleaned-up+commented |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_prod_data_lgth_calc
--=================================================================================================
entity wf_prod_data_lgth_calc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); -- produced var user-data length
-- User Interface, General signals
nostat_i : in std_logic; -- if negated, nFIP status is sent
slone_i : in std_logic; -- stand-alone mode
-- Signal from the wf_engine_control unit
var_i : in t_var; -- variable type that is being treated
-- OUTPUT
-- Signal to the wf_engine_control and wf_production units
prod_data_lgth_o : out std_logic_vector (7 downto 0));
end entity wf_prod_data_lgth_calc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture behavior of wf_prod_data_lgth_calc is
signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Combinatorial process data_length_calcul: calculation of the amount of bytes, after the
-- FSS and before the FCS, that have to be transferred when a variable is produced. In the case
-- of the presence, the identification and the var5 variables, the data length is predefined in the
-- WF_PACKAGE. In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the
-- calculation.
data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i)
begin
s_p3_lgth_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
case var_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_3 =>
-- data length calculation according to the operational mode (memory or stand-alone)
-- in slone mode 2 bytes of user-data are produced (independently of P3_LGTH)
-- to these there should be added: 1 byte CTRL
-- 1 byte PDU_TYPE
-- 1 byte LGTH
-- 1 byte MPS status
-- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data;
-- to these, there should be added 1 byte CTRL
-- 1 byte PDU_TYPE
-- 1 byte LGTH
-- 1 byte MPS status
-- optionally 1 byte nFIP status
if slone_i = '1' then
if nostat_i = '1' then -- 6 bytes (counting starts from 0!)
s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length);
else -- 7 bytes
s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length);
end if;
else
if nostat_i = '0' then
s_prod_data_lgth <= s_p3_lgth_decoded + 4;
else
s_prod_data_lgth <= s_p3_lgth_decoded + 3;
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_5 =>
-- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_5_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when others =>
s_prod_data_lgth <= (others => '0');
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Registration of the output (coz of slack)
Prod_Data_Lgth_Reg: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
prod_data_lgth_o <= (others =>'0');
else
prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth);
end if;
end if;
end process;
end architecture behavior;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit |
touilleMan/scrips | sign_extend_bench.vhd | 1 | 1757 | -- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/sign_extend.sch - Thu Jun 7 17:52:26 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY sign_extend_sign_extend_sch_tb IS
END sign_extend_sign_extend_sch_tb;
ARCHITECTURE behavioral OF sign_extend_sign_extend_sch_tb IS
COMPONENT sign_extend
PORT( I : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
END COMPONENT;
SIGNAL I : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL O : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
UUT: sign_extend PORT MAP(
I => I,
O => O
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
-- Test positive number
I <= "0111111111111111";
wait for 1ms;
-- Test negative number
I <= "1111111111111111";
wait for 1ms;
I <= "1000000000000000";
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
| mit |
touilleMan/scrips | ALU_bench.vhd | 1 | 2756 | -- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/ALU.sch - Fri Jun 8 12:08:08 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY ALU_ALU_sch_tb IS
END ALU_ALU_sch_tb;
ARCHITECTURE behavioral OF ALU_ALU_sch_tb IS
COMPONENT ALU
PORT( Reg2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Reg1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ALUControl : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Zero : OUT STD_LOGIC);
END COMPONENT;
SIGNAL Reg2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL Reg1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL Result : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL ALUControl : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL Zero : STD_LOGIC;
BEGIN
UUT: ALU PORT MAP(
Reg2 => Reg2,
Reg1 => Reg1,
Result => Result,
ALUControl => ALUControl,
Zero => Zero
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
-- Test add : 2 + 3 = 5
Reg1 <= "00000000000000000000000000000010";
Reg2 <= "00000000000000000000000000000011";
ALUControl <= "0010";
wait for 1ms;
-- Test sub : 3 - 3 = 0
Reg1 <= "00000000000000000000000000000011";
Reg2 <= "00000000000000000000000000000011";
ALUControl <= "0110";
wait for 1ms;
-- Test and 15 & 6 = 6
Reg1 <= "00000000000000000000000000001111";
Reg2 <= "00000000000000000000000000000110";
ALUControl <= "0000";
wait for 1ms;
-- Test or : 15 | 6 = 15
Reg1 <= "00000000000000000000000000001111";
Reg2 <= "00000000000000000000000000000110";
ALUControl <= "0001";
wait for 1ms;
-- Test xor : 7 xor 5 = 2
Reg1 <= "00000000000000000000000000000111";
Reg2 <= "00000000000000000000000000000101";
ALUControl <= "0011";
wait for 1ms;
-- Test slt : 1 slt 4 = 1
Reg1 <= "00000000000000000000000000000001";
Reg2 <= "00000000000000000000000000000100";
ALUControl <= "0111";
wait for 1ms;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
| mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_status_bytes_gen.vhd | 1 | 26557 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_status_bytes_gen |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_status_bytes_gen.vhd |
-- |
-- Description Generation of the nanoFIP status and MPS status bytes. |
-- The unit is also responsible for outputting the "nanoFIP User Interface, |
-- NON_WISHBONE" signals U_CACER, U_PACER, R_TLER, R_FCSER, that correspond to |
-- nanoFIP status bits 2 to 5. |
-- |
-- The information contained in the nanoFIP status byte is coming from : |
-- o the wf_consumption unit, for the bits 4 and 5 |
-- o the "nanoFIP FIELDRIVE" inputs FD_WDGN and FD_TXER, for the bits 6 and 7 |
-- o the "nanoFIP User Interface, NON_WISHBONE" inputs (VAR_ACC) and outputs |
-- (VAR_RDY), for the bits 2 and 3. |
-- |
-- For the MPS byte, in memory mode, the refreshment and significance bits are set to|
-- 1 if the user has updated the produced variable var3 since its last transmission; |
-- the signal "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC,is used for this.|
-- In stand-alone mode the MPS status byte has the refreshment and significance set |
-- to 1. The same happens for the JTAG produced variable var_5, regardless of the |
-- mode. |
-- |
-- The MPS and the nanoFIP status byte are reset after having been sent or after a |
-- nanoFIP internal reset. |
-- |
-- Reminder: |
-- ______________________ __________ ____________________________________________ |
-- | nanoFIP STATUS BIT | NAME | CONTENTS | |
-- |______________________|__________|____________________________________________| |
-- | 0 | r1 | reserved | |
-- |______________________|__________|____________________________________________| |
-- | 1 | r2 | reserved | |
-- |______________________|__________|____________________________________________| |
-- | 2 | u_cacer | user cons var access error | |
-- |______________________|__________|____________________________________________| |
-- | 3 | u_pacer | user prod var access error | |
-- |______________________|__________|____________________________________________| |
-- | 4 | r_tler | received CTRL, PDU_TYPE or LGTH error | |
-- |______________________|__________|____________________________________________| |
-- | 5 | r_fcser | received FCS or bit number error | |
-- |______________________|__________|____________________________________________| |
-- | 6 | t_txer | transmit error (FIELDRIVE) | |
-- |______________________|__________|____________________________________________| |
-- | 7 | t_wder | watchdog error (FIELDRIVE) | |
-- |______________________|__________|____________________________________________| |
-- |
-- --------------------------------------------------------------------------- |
-- __________________ ______________ ______________ |
-- | MPS STATUS BIT | NAME | CONTENTS | |
-- |__________________|______________|______________| |
-- | 0 | refreshment | 1/0 | |
-- |__________________|______________|______________| |
-- | 1 | | 0 | |
-- |__________________|______________|______________| |
-- | 2 | significance | 1/0 | |
-- |__________________|______________|______________| |
-- | 3 | | 0 | |
-- |__________________|_____________ |______________| |
-- | 4-7 | | 000 | |
-- |__________________|_____________ |______________| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 06/2011 |
-- Version v0.04 |
-- Depends on wf_reset_unit |
-- wf_consumption |
-- wf_prod_bytes_retriever |
-- wf_prod_permit |
---------------- |
-- Last changes |
-- 07/07/2009 v0.01 PA First version |
-- 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status |
-- errors few cycles after var_rdy deactivation |
-- 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i |
-- for nanoFIP status bit 4; var_i input not needed as the signals |
-- nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var |
-- 06/2011 v0.04 EG all bits of nanoFIP status byte are reset upon rst_status_bytes_p_i |
-- var_i added for the jtag_var1 treatment; |
-- r_fcser, r_tler_o considered only for a cons variable (bf a wrong |
-- crc on an id-dat could give r_fcser) |
-- 11/2011 v0.042 EG the var3_acc_a_i and not the s_var3_acc_synch(3) was used for |
-- the refreshment:s |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_status_bytes_gen
--=================================================================================================
entity wf_status_bytes_gen is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz Clock
slone_i : in std_logic; -- stand-alone mode
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanaoFIP internal reset
-- nanoFIP FIELDRIVE
fd_txer_a_i : in std_logic; -- transmitter error
fd_wdgn_a_i : in std_logic; -- watchdog on transmitter
-- nanoFIP User Interface, NON-WISHBONE
var1_acc_a_i : in std_logic; -- variable 1 access
var2_acc_a_i : in std_logic; -- variable 2 access
var3_acc_a_i : in std_logic; -- variable 3 access
-- Signals from the wf_consumption unit
nfip_status_r_fcser_p_i : in std_logic; -- wrong CRC bytes received
nfip_status_r_tler_p_i : in std_logic; -- wrong PDU_TYPE, CTRL or LGTH bytes received
var1_rdy_i : in std_logic; -- variable 1 ready
var2_rdy_i : in std_logic; -- variable 2 ready
-- Signals from the wf_prod_bytes_retriever unit
rst_status_bytes_p_i : in std_logic; -- reset for both status bytes;
-- they are reset right after having been delivered
-- Signals from the wf_prod_permit unit
var3_rdy_i : in std_logic; -- variable 3 ready
-- Signal from the wf_engine_control unit
var_i : in t_var; -- variable type that is being treated
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
r_fcser_o : out std_logic; -- nanoFIP status byte, bit 5
r_tler_o : out std_logic; -- nanoFIP status byte, bit 4
u_cacer_o : out std_logic; -- nanoFIP status byte, bit 2
u_pacer_o : out std_logic; -- nanoFIP status byte, bit 3
-- Signal to the wf_prod_bytes_retriever
mps_status_byte_o : out std_logic_vector (7 downto 0); -- MPS status byte
nFIP_status_byte_o : out std_logic_vector (7 downto 0));-- nanoFIP status byte
end entity wf_status_bytes_gen;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_status_bytes_gen is
-- synchronizers
signal s_fd_txer_synch, s_fd_wdg_synch, s_var1_acc_synch : std_logic_vector (2 downto 0);
signal s_var2_acc_synch, s_var3_acc_synch : std_logic_vector (2 downto 0);
-- MPS refreshment/ significance bit
signal s_refreshment : std_logic;
-- nanoFIP status byte
signal s_nFIP_status_byte : std_logic_vector (7 downto 0);
-- extension of var_rdy signals
signal s_var1_rdy_c, s_var2_rdy_c, s_var3_rdy_c : unsigned (3 downto 0);
signal s_var1_rdy_c_incr,s_var1_rdy_c_reinit,s_var1_rdy_extended : std_logic;
signal s_var2_rdy_c_incr,s_var2_rdy_c_reinit,s_var2_rdy_extended : std_logic;
signal s_var3_rdy_c_incr,s_var3_rdy_c_reinit,s_var3_rdy_extended : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FD_TXER, FD_WDGN, VARx_ACC Synchronizers --
---------------------------------------------------------------------------------------------------
FIELDRIVE_inputs_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fd_wdg_synch <= (others => '0');
s_fd_txer_synch <= (others => '0');
else
s_fd_wdg_synch <= s_fd_wdg_synch (1 downto 0) & not fd_wdgn_a_i;
s_fd_txer_synch <= s_fd_txer_synch (1 downto 0) & fd_txer_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
VAR_ACC_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var1_acc_synch <= (others => '0');
s_var2_acc_synch <= (others => '0');
s_var3_acc_synch <= (others => '0');
else
s_var1_acc_synch <= s_var1_acc_synch(1 downto 0) & var1_acc_a_i;
s_var2_acc_synch <= s_var2_acc_synch(1 downto 0) & var2_acc_a_i;
s_var3_acc_synch <= s_var3_acc_synch(1 downto 0) & var3_acc_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- MPS status byte --
---------------------------------------------------------------------------------------------------
-- Synchronous process Refreshment_bit_Creation: Creation of the refreshment bit (used in
-- the MPS status byte). The bit is set to 1 if the user has updated the produced variable since
-- its last transmission. The process is checking if the signal VAR3_ACC has been asserted since
-- the last production of a variable.
Refreshment_bit_Creation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_refreshment <= '0';
else
if rst_status_bytes_p_i = '1' then -- bit reinitialized after a production
s_refreshment <= '0';
elsif s_var3_acc_synch(2) = '1' then -- indication that the memory has been accessed
s_refreshment <= '1';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process MPS_byte_Generation: Creation of the MPS byte (Table 2, functional specs)
MPS_byte_Generation: process (slone_i, s_refreshment, var_i)
begin -- var_5, regardless of the mode, has signif. & refresh. set to 1
if slone_i = '1' or var_i = var_5 then -- stand-alone mode has signif. & refresh. set to 1
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= '1';
mps_status_byte_o (1) <= '0';
mps_status_byte_o (c_REFRESHMENT_INDEX) <= '1';
else
mps_status_byte_o (7 downto 3) <= (others => '0');
mps_status_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_status_byte_o (1) <= '0';
mps_status_byte_o (c_SIGNIFICANCE_INDEX) <= s_refreshment;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- nanoFIP status byte --
---------------------------------------------------------------------------------------------------
-- Synchronous process nFIP_status_byte_Generation: Creation of the nanoFIP status byte (Table 8,
-- functional specs)
nFIP_status_byte_Generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_nFIP_status_byte <= (others => '0');
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reinitialization after the transmission of a produced variable
if rst_status_bytes_p_i = '1' then
s_nFIP_status_byte <= (others => '0');
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_cacer
if ((s_var1_rdy_extended = '0' and s_var1_acc_synch(2) = '1') or
(s_var2_rdy_extended = '0' and s_var2_acc_synch(2) = '1')) then
-- since the last time the status
-- byte was delivered,
s_nFIP_status_byte(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cons.
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- u_pacer
if (s_var3_rdy_extended = '0' and s_var3_acc_synch(2) = '1') then
-- since the last time the status
s_nFIP_status_byte(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
-- the user logic accessed a prod.
-- var. when it was not ready
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_wder
if (s_fd_wdg_synch(2) = '1') then -- FIELDRIVE transmission error
s_nFIP_status_byte(c_T_WDER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- t_rxer
if (s_fd_txer_synch(2) = '1') then -- FIELDRIVE watchdog timer problem
s_nFIP_status_byte(c_T_TXER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler -- PDU_TYPE or LGTH error on a consumed var
if (nfip_status_r_tler_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_4) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_TLER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_fcser -- CRC or bit number error on a consumed var
if (nfip_status_r_fcser_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_4) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_FCSER_INDEX) <= '1';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of 3 wf_incr_counters used for the internal extension of each one of the
-- signals VAR1_RDY, VAR2_RDY, VAR3_RDY for 15 uclk cycles.
-- Enabled VAR_ACC during this period will not trigger a nanoFIP status byte error.
-- Note: actually it is the var_acc_synch(2) rather than the VAR_ACC used to check for access errors;
-- var_acc_synch(2) is 3 cycles later than VAR_ACC and therefore enabled VAR_ACC is ignored up to 12
-- uclk cycles (not 15 uclk cycles!) after the deassertion of the VAR_RDY.
Extend_VAR1_RDY: wf_incr_counter -- VAR1_RDY : __|---...---|___________________
generic map(g_counter_lgth => 4) -- s_var1_rdy_extended: __|---...------------------|____
port map( -- --> VAR_ACC here is OK! <--
uclk_i => uclk_i,
counter_reinit_i => s_var1_rdy_c_reinit,
counter_incr_i => s_var1_rdy_c_incr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_var1_rdy_c);
------------------------------------------
s_var1_rdy_c_reinit <= var1_rdy_i or nfip_rst_i;
s_var1_rdy_c_incr <= '1' when s_var1_rdy_c < "1111" else '0';
s_var1_rdy_extended <= '1' when var1_rdy_i= '1' or s_var1_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR2_RDY: wf_incr_counter
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var2_rdy_c_reinit,
counter_incr_i => s_var2_rdy_c_incr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_var2_rdy_c);
------------------------------------------
s_var2_rdy_c_reinit <= var2_rdy_i or nfip_rst_i;
s_var2_rdy_c_incr <= '1' when s_var2_rdy_c < "1111" else '0';
s_var2_rdy_extended <= '1' when var2_rdy_i= '1' or s_var2_rdy_c_incr = '1' else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR3_RDY: wf_incr_counter
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_var3_rdy_c_reinit,
counter_incr_i => s_var3_rdy_c_incr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_var3_rdy_c);
------------------------------------------
s_var3_rdy_c_reinit <= var3_rdy_i or nfip_rst_i;
s_var3_rdy_c_incr <= '1' when s_var3_rdy_c < "1111" else '0';
s_var3_rdy_extended <= '1' when VAR3_RDY_i= '1' or s_var3_rdy_c_incr = '1' else '0';
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
nFIP_status_byte_o <= s_nFIP_status_byte;
u_cacer_o <= s_nFIP_status_byte(c_U_CACER_INDEX);
u_pacer_o <= s_nFIP_status_byte(c_U_PACER_INDEX);
r_tler_o <= s_nFIP_status_byte(c_R_TLER_INDEX);
r_fcser_o <= s_nFIP_status_byte(c_R_FCSER_INDEX);
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/Synthesize/DataPath/Vhdl/c_adder.vhd | 1 | 952 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_adder is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_adder;
architecture behavior of c_adder is
function bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop;
return ret_val;
end bits_to_int;
begin
process (input1, input2)
variable value : integer;
variable result : std_logic_vector((width - 1) downto 0);
begin
value := bits_to_int(input1) + bits_to_int(input2);
for i in 0 to width - 1 loop
if (value rem 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
value := value / 2;
end loop;
output <= result;
end process;
end behavior; | mit |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/meu_projeto.vhd | 1 | 1818 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:20:16 11/04/2014
-- Design Name:
-- Module Name: meu_projeto - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity meu_projeto is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
botao : in STD_LOGIC;
saida : out STD_LOGIC_VECTOR (15 downto 0);
led : out STD_LOGIC);
end meu_projeto;
architecture Behavioral of meu_projeto is
signal clk1s : std_logic;
signal cnt : integer range 0 to 9999;
begin
conta_botao : process (reset, botao)
begin
if reset = '1' then
cnt <= 0;
elsif botao'event and botao='1' then
cnt <= cnt +1;
else
cnt <= cnt;
end if;
end process;
saida <= conv_std_logic_vector(cnt,16);
pisca_led : process (reset, clock)
variable cnt : integer range 0 to 25000001;
begin
if reset = '1' then
clk1s <= '0';
cnt := 0;
elsif clock'event and clock ='1' then
if(cnt >= 25000000) then
clk1s <= not clk1s;
cnt := 0;
else
cnt := cnt +1;
end if;
else
cnt := cnt;
end if;
end process;
led <= clk1s;
end Behavioral;
| mit |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/disp7segx4.vhd | 1 | 2430 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:13:01 06/13/2012
-- Design Name:
-- Module Name: disp7segx4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
entity disp7segx4 is
Port ( entrada : in STD_LOGIC_VECTOR (15 downto 0);
clock : in std_logic;
clk_1k : out std_logic;
reset : in std_logic;
saida_8segmentos : out STD_LOGIC_VECTOR (7 downto 0);
-- disp_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
disp_sel_o : out STD_LOGIC_VECTOR (3 downto 0));
end disp7segx4;
architecture Behavioral of disp7segx4 is
type vetor_de_std_logic_vector is array (3 downto 0) of std_logic_vector (7 downto 0);
type vetor_de_10_std_logic_vector is array (9 downto 0) of std_logic_vector (7 downto 0);
signal display : vetor_de_std_logic_vector;
signal cont : integer range 0 to 3 := 0;
signal disp_sel : std_logic_vector (3 downto 0) := "1110";
signal clk_1k_sgn : std_logic:='0';
signal clock_1k : integer range 0 to 26000 :=0;
begin
clock_div : process (reset, clock)
begin
if reset = '1' then
clock_1k <= 0;
elsif clock'event and clock ='1' then
if(clock_1k > 25000) then
clk_1k_sgn <= not clk_1k_sgn;
clock_1k <= 0;
else
clock_1k <= clock_1k +1;
end if;
else
clock_1k <= clock_1k;
end if;
end process;
process (clk_1k_sgn, reset)
begin
if reset = '1' then
disp_sel <= "1110";
cont <= 0;
elsif clk_1k_sgn'event and clk_1k_sgn = '1' then
disp_sel(3 downto 1) <= disp_sel(2 downto 0);
disp_sel(0) <= disp_sel(3);
cont <= cont +1;
else
disp_sel <= disp_sel;
cont <= cont;
end if;
end process;
disp_sel_o <= disp_sel;
laco_for : for i in 0 to 3 generate
display1 : entity work.disp7seg
port map ( entrada => entrada((i+1)*4 -1 downto i*4),
clock => clock,
reset => reset,
saida_8segmentos => display(i));
saida_8segmentos <= display(cont REM 4);
end generate;
clk_1k <= clk_1k_sgn;
end Behavioral;
| mit |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/input_tb.vhd | 1 | 1598 | ---------------------------------------------------------------------
--
-- Inputs: a, b, c, d, e, f, g, h
-- Output(s): i
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity test_me_tb is
end test_me_tb;
architecture test_me of test_me_tb is
component input
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
clear, clock, s_tart : IN std_logic;
finish : OUT std_logic
);
end component;
for all : input use entity work.input(rtl2);
signal a, b, c, d, e, f, g, h, i : std_logic_vector(3 downto 0) := "0000";
signal clear, clock, finish, s_tart : std_logic := '0';
begin
test_input : input port map (a, b, c, d, e, f, g, h, i, clear, clock, s_tart, finish);
process
begin
wait for 1 ns;
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
a <= "0010"; -- 2
b <= "0001"; -- 1
c <= "0010"; -- 2
d <= "0011"; -- 3
e <= "0010"; -- 2
f <= "0001"; -- 1
g <= "0010"; -- 2
h <= "0010"; -- 2
s_tart <= '1';
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
assert i = "0110" report "6 = f(2, 1, 2, 3, 2, 1, 2, 2) = (2 * 1 * 2 * 3) - 2 - (2 * 2 * 1)" severity failure;
wait;
end process;
end test_me;
| mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_nor.vhd | 2 | 568 | library ieee;
use ieee.std_logic_1164.all;
entity c_nor is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_nor;
architecture behavior of c_nor is
begin
P0 : process (input1, input2)
variable result : std_logic_vector(width - 1 downto 0);
begin
outer : for n in width - 1 downto 0 loop
result(n) := input1(n) nor input2(n);
end loop outer;
output <= result;
end process P0;
end behavior; | mit |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample/input_dp.vhd | 1 | 14195 | ---------------------------------------------------------------------
-- --
-- This file is generated automatically by AUDI (AUtomatic --
-- Design Instantiation) system, a behavioral synthesis system, --
-- developed at the University of South Florida. This project --
-- is supported by the National Science Foundation (NSF) under --
-- the project number XYZ. If you have any questions, contact --
-- Dr. Srinivas Katkoori ([email protected]), Computer --
-- Science & Engineering Department, University of South Florida, --
-- Tampa, FL 33647. --
-- --
---------------------------------------------------------------------
--
-- Date & Time:
-- User login id/name:
--
-- File name:
-- Type:
--
-- Input aif file name:
--
-- CDFG statistics:
-- * Number of PI's:
-- * Number of PO's:
-- * Number of internal edges:
-- * Number of Operations:
-- * Conditionals:
-- * Loops:
-- * Types of Operations:
--
-- Design Flow/Algorithm Information:
-- * Scheduling Algorithm:
-- * Allocation:
-- * Binding:
-- Interconnect style: Multiplexor-Based or Bus-based
--
-- Design Information:
--
-- Datapath:
-- * Registers:
-- * Functional units:
-- * Number of Multiplexors:
-- * Number of Buses:
--
-- * Operator Binding Information:
--
-- * Register Optimization Information:
--
-- * Register Binding Information:
--
--
-- Controller:
-- * Type: Moore/Mealy
-- * Number of states:
-- * Number of control bits:
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Beh_Lib;
use Beh_Lib.all;
entity input_dp is
port( a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
c : IN std_logic_vector(3 downto 0);
d : IN std_logic_vector(3 downto 0);
e : IN std_logic_vector(3 downto 0);
f : IN std_logic_vector(3 downto 0);
g : IN std_logic_vector(3 downto 0);
h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl: IN std_logic_vector(14 downto 0);
clear: IN std_logic;
clock: IN std_logic
);
end input_dp;
architecture RTL of input_dp is
component c_register
generic (width : integer := 4);
port (input : in std_logic_vector((width-1) downto 0);
WR: in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width -1) downto 0));
end component;
-- for all : c_register use entity Beh_Lib.c_register(behavior);
component C_Latch
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
ENABLE : in Std_logic;
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Latch use entity Beh_Lib.C_Latch(Behavior);
component Constant_Reg
generic (width : integer;
const : integer);
port( output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Constant_Reg use entity Beh_Lib.Constant_Reg(Behavior);
component Shift_Reg
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
CONTROL : in Std_logic_vector (1 downto 0);
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Shift_Reg use entity Beh_Lib.Shift_Reg(Behavior);
component C_Signal
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
STORE : in Std_logic;
UPDATE : in Std_logic;
CLEAR : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width + 1) downto 0));
end component;
-- for all : C_Signal use entity Beh_Lib.C_Signal(Behavior);
component Ram
generic (width : integer;
ram_select : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((ram_select - 1) downto 0);
WR : in Std_logic;
RD : in Std_logic;
CLOCK : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Ram use entity Beh_Lib.Ram(Behavior);
component C_Adder
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (width downto 0));
end component;
-- for all : C_Adder use entity Beh_Lib.C_Adder(Behavior);
component C_subtractor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (width downto 0));
end component;
-- for all : C_Subtractor use entity Beh_Lib.C_Subtractor(Behavior);
component C_Comparator
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (2 downto 0));
end component;
-- for all : C_Comparator use entity Beh_Lib.C_Comparator(Behavior);
component C_multiplier
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector (((width * 2) - 2) downto 0));
end component;
-- for all : C_Multiplier use entity Beh_Lib.C_Multiplier(Behavior);
component C_Divider
generic (width : integer;
const : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Divider use entity Beh_Lib.C_Divider(Behavior);
component C_Concat
generic (width1: integer;
width2 : integer);
port( input1 : in Std_logic_vector ((width1 - 1) downto 0);
input2 : in Std_logic_vector ((width2 - 1) downto 0);
output : out Std_logic_vector (((width1 + width2) - 1) downto 0));
end component;
-- for all : C_Concat use entity Beh_Lib.C_Concat(Behavior);
component C_Multiplexer
generic (width : integer;
no_of_inputs : integer;
select_size : integer);
port( input : in Std_logic_vector (((width*no_of_inputs) - 1) downto 0);
MUX_SELECT : in Std_logic_vector ((select_size - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Multiplexer use entity Beh_Lib.C_Multiplexer(Behavior);
component C_Bus
generic (width : integer;
no_of_inputs : integer);
port( input : in Std_logic_vector (((width*no_of_inputs) - 1) downto 0);
BUS_SELECT : in Std_logic_vector ((no_of_inputs - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Bus use entity Beh_Lib.C_Bus(Behavior);
component C_And
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_And use entity Beh_Lib.C_And(Behavior);
component C_Or
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Or use entity Beh_Lib.C_Or(Behavior);
component C_Nand
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Nand use entity Beh_Lib.C_Nand(Behavior);
component C_Nor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Nor use entity Beh_Lib.C_Nor(Behavior);
component C_XNor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_XNor use entity Beh_Lib.C_XNor(Behavior);
component C_Xor
generic (width : integer);
port( input1 : in Std_logic_vector ((width - 1) downto 0);
input2 : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Xor use entity Beh_Lib.C_Xor(Behavior);
component C_Not
generic (width : integer);
port( input : in Std_logic_vector ((width - 1) downto 0);
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : C_Not use entity Beh_Lib.C_Not(Behavior);
component Tri_State_Buf
generic (width : integer);
port (input : in Std_logic_vector ((width - 1) downto 0);
enable : in Std_logic;
output : out Std_logic_vector ((width - 1) downto 0));
end component;
-- for all : Tri_State_Buf use entity Beh_Lib.Tri_State_Buf(Behavior);
-- Outputs of registers
signal R0_out : Std_logic_vector(3 downto 0);
signal R1_out : Std_logic_vector(3 downto 0);
signal R2_out : Std_logic_vector(3 downto 0);
signal R3_out : Std_logic_vector(3 downto 0);
signal R4_out : Std_logic_vector(3 downto 0);
signal R5_out : Std_logic_vector(3 downto 0);
signal R6_out : Std_logic_vector(3 downto 0);
signal R7_out : Std_logic_vector(3 downto 0);
signal R8_out : Std_logic_vector(3 downto 0);
signal R9_out : Std_logic_vector(3 downto 0);
-- Outputs of FUs
signal FU0_0_out : Std_logic_vector(4 downto 0);
signal FU0_1_out : Std_logic_vector(4 downto 0);
signal FU0_2_out : Std_logic_vector(4 downto 0);
signal FU0_3_out : Std_logic_vector(4 downto 0);
signal FU0_4_out : Std_logic_vector(4 downto 0);
signal FU1_0_out : Std_logic_vector(4 downto 0);
signal FU1_1_out : Std_logic_vector(4 downto 0);
-- Outputs of Interconnect Units
signal Mux0_out : Std_logic_vector(3 downto 0);
signal Mux1_out : Std_logic_vector(3 downto 0);
signal Mux2_out : Std_logic_vector(3 downto 0);
begin
R0 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux0_out(3 downto 0),
WR => ctrl(0),
CLEAR => clear,
CLOCK => clock,
output => R0_out);
R1 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux1_out(3 downto 0),
WR => ctrl(1),
CLEAR => clear,
CLOCK => clock,
output => R1_out);
R2 : C_Register
generic map(4)
port map (
input(3 downto 0) => h(3 downto 0),
WR => ctrl(2),
CLEAR => clear,
CLOCK => clock,
output => R2_out);
R3 : C_Register
generic map(4)
port map (
input(3 downto 0) => g(3 downto 0),
WR => ctrl(3),
CLEAR => clear,
CLOCK => clock,
output => R3_out);
R4 : C_Register
generic map(4)
port map (
input(3 downto 0) => f(3 downto 0),
WR => ctrl(4),
CLEAR => clear,
CLOCK => clock,
output => R4_out);
R5 : C_Register
generic map(4)
port map (
input(3 downto 0) => e(3 downto 0),
WR => ctrl(5),
CLEAR => clear,
CLOCK => clock,
output => R5_out);
R6 : C_Register
generic map(4)
port map (
input(3 downto 0) => d(3 downto 0),
WR => ctrl(6),
CLEAR => clear,
CLOCK => clock,
output => R6_out);
R7 : C_Register
generic map(4)
port map (
input(3 downto 0) => c(3 downto 0),
WR => ctrl(7),
CLEAR => clear,
CLOCK => clock,
output => R7_out);
R8 : C_Register
generic map(4)
port map (
input(3 downto 0) => Mux2_out(3 downto 0),
WR => ctrl(8),
CLEAR => clear,
CLOCK => clock,
output => R8_out);
R9 : C_Register
generic map(4)
port map (
input(3 downto 0) => b(3 downto 0),
WR => ctrl(9),
CLEAR => clear,
CLOCK => clock,
output => R9_out);
MULT0_0 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R0_out(3 downto 0),
input2(3 downto 0) => R9_out(3 downto 0),
output(4 downto 0) => FU0_0_out(4 downto 0));
MULT0_1 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R7_out(3 downto 0),
input2(3 downto 0) => R6_out(3 downto 0),
output(4 downto 0) => FU0_1_out(4 downto 0));
MULT0_2 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R5_out(3 downto 0),
input2(3 downto 0) => R4_out(3 downto 0),
output(4 downto 0) => FU0_2_out(4 downto 0));
MULT0_3 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R8_out(3 downto 0),
input2(3 downto 0) => R1_out(3 downto 0),
output(4 downto 0) => FU0_3_out(4 downto 0));
MULT0_4 : C_Multiplier
generic map(4)
port map (
input1(3 downto 0) => R3_out(3 downto 0),
input2(3 downto 0) => R8_out(3 downto 0),
output(4 downto 0) => FU0_4_out(4 downto 0));
SUB1_0 : C_Subtractor
generic map(4)
port map (
input1(3 downto 0) => R1_out(3 downto 0),
input2(3 downto 0) => R2_out(3 downto 0),
output(4 downto 0) => FU1_0_out(4 downto 0));
SUB1_1 : C_Subtractor
generic map(4)
port map (
input1(3 downto 0) => R1_out(3 downto 0),
input2(3 downto 0) => R8_out(3 downto 0),
output(4 downto 0) => FU1_1_out(4 downto 0));
Mux0 : C_Multiplexer
generic map(4, 2, 1)
port map(
input(3 downto 0) => FU1_1_out(3 downto 0),
input(7 downto 4) => a(3 downto 0),
MUX_SELECT(0 downto 0) => ctrl(10 downto 10),
output => Mux0_out);
Mux1 : C_Multiplexer
generic map(4, 3, 2)
port map(
input(3 downto 0) => FU1_0_out(3 downto 0),
input(7 downto 4) => FU0_1_out(3 downto 0),
input(11 downto 8) => FU0_3_out(3 downto 0),
MUX_SELECT(1 downto 0) => ctrl(12 downto 11),
output => Mux1_out);
Mux2 : C_Multiplexer
generic map(4, 3, 2)
port map(
input(3 downto 0) => FU0_0_out(3 downto 0),
input(7 downto 4) => FU0_2_out(3 downto 0),
input(11 downto 8) => FU0_4_out(3 downto 0),
MUX_SELECT(1 downto 0) => ctrl(14 downto 13),
output => Mux2_out);
-- Primary outputs
i(3 downto 0) <= R0_out(3 downto 0);
end RTL;
| mit |
Abeergit/UART | UART_TX.vhd | 1 | 4351 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
generic(
DBIT: integer := 8; -- Anzahl Datenbits
PARITY_EN: std_logic := '1'; -- Parity bit (1 = enable, 0 = disable)
SB_TICK: integer := 16 -- Anzahl s_tick f stopbbit
);
port(
clk, reset: in std_logic;
tx_start: in std_logic;
s_tick: in std_logic;
din: in std_logic_vector(7 downto 0);
tx_done_tick: out std_logic;
tx: out std_logic;
parity_bit: in std_logic
);
end uart_tx ;
architecture main of uart_tx is
type state_type is (idle, start, data, parity, stop);-- FSM status typen
signal state_reg, state_next: state_type; -- Status Register
signal s_reg, s_next: unsigned(4 downto 0); -- Register für Stop Bit
signal n_reg, n_next: unsigned(3 downto 0); -- Anzahl empfangener bits
signal b_reg, b_next: std_logic_vector(7 downto 0); -- Datenwort
signal tx_reg, tx_next: std_logic; -- tx_reg: transmission register, routed to tx
begin
-- register
process(clk,reset)
begin
if (rising_edge(clk) and clk='1') then
if reset = '1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
tx_reg <= '1';
elsif reset = '0' then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end if;
end if;
end process;
-- next-state logic & data path functional units/routing
process(state_reg,s_reg,n_reg,b_reg,s_tick,
tx_reg,tx_start,din, parity_bit)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg ;
tx_done_tick <= '0';
case state_reg is -- state machine (idle, start, data, stop)
when idle => --idle
tx_next <= '1'; -- tx = 1 während idle
if tx_start='1' then -- tx_start = 1 => state: data
state_next <= start;
s_next <= (others=>'0');
b_next <= din; --b_next = 8 bit Datenwort aus din
end if;
when start => --start
tx_next <= '0'; --startbit
if (s_tick = '1') then
if s_reg=7 then --nach 15 sample ticks status => data
state_next <= data;
s_next <= (others=>'0');
n_next <= (others=>'0');
else
s_next <= s_reg + 1;
end if;
end if;
when data => --data
tx_next <= b_reg(0);
if (s_tick = '1') then
if s_reg=15 then
s_next <= (others=>'0');
b_next <= '0' & b_reg(7 downto 1) ; --shift register
if n_reg=(DBIT-1) then --then n_reg = 8 => stop
if PARITY_EN = '1' then
state_next <= parity;
elsif PARITY_EN = '0' then
state_next <= stop;
end if;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when parity =>
tx_next <= parity_bit;
if s_tick = '1' then
if s_reg = 15 then
s_next <= (others=>'0');
state_next <= stop;
else
s_next <= s_reg + 1;
end if;
end if;
when stop => --stop
tx_next <= '1';
if (s_tick = '1') then
if s_reg=(SB_TICK-1) then
state_next <= idle;
tx_done_tick <= '1';
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
tx <= tx_reg;
end main;
| mit |
marceloboeira/vhdl-examples | 008-state-machine-calculator/seven_segment_display_mux.vhd | 1 | 1839 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity SevenSegmentDisplayMux is
Port (entrada: in STD_LOGIC_VECTOR (15 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
output_h: out STD_LOGIC_VECTOR (7 downto 0);
current_display: out STD_LOGIC_VECTOR (3 downto 0);
clk_1k: out STD_LOGIC);
end SevenSegmentDisplayMux;
architecture Behavioral of SevenSegmentDisplayMux is
type STD_LOGIC_ARRAY_4 is array (3 downto 0) of STD_LOGIC_VECTOR (7 downto 0);
signal display : STD_LOGIC_ARRAY_4;
signal cont : INTEGER range 0 to 3 := 0;
signal disp_sel : STD_LOGIC_VECTOR (3 downto 0) := "1110";
signal clk_1k_sgn : STD_LOGIC := '0';
signal clock_1k : INTEGER range 0 to 26000 :=0;
begin
clock_div : process (reset, clock)
begin
if reset = '1' then
clock_1k <= 0;
elsif clock'event and clock ='1' then
if(clock_1k > 25000) then
clk_1k_sgn <= not clk_1k_sgn;
clock_1k <= 0;
else
clock_1k <= clock_1k +1;
end if;
else
clock_1k <= clock_1k;
end if;
end process;
process(clk_1k_sgn, reset)
begin
if reset = '1' then
disp_sel <= "1110";
cont <= 0;
elsif clk_1k_sgn'event and clk_1k_sgn = '1' then
disp_sel(3 downto 1) <= disp_sel(2 downto 0);
disp_sel(0) <= disp_sel(3);
cont <= cont +1;
else
disp_sel <= disp_sel;
cont <= cont;
end if;
end process;
current_display <= disp_sel;
laco_for : for i in 0 to 3 generate
display1 : entity work.SevenSegmentDisplayDriver
port map (entrada((i+1)*4 -1 downto i*4),
clock,
reset,
display(i));
output_h <= display(cont REM 4);
end generate;
clk_1k <= clk_1k_sgn;
end Behavioral;
| mit |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/input_des.vhd | 1 | 2075 | ---------------------------------------------------------------------
--
-- Inputs: a, b, c, d, e, f, g, h
-- Output(s): i
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity input is
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
clear, clock, s_tart : IN std_logic;
finish : OUT std_logic
);
end input;
architecture rtl2 of input is
component input_controller
port
(
clock, reset, s_tart : IN std_logic;
finish : OUT std_logic;
control_out : OUT std_logic_vector(0 to 18)
);
end component;
for all : input_controller use entity work.input_controller(moore);
component input_dp
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
ctrl : IN std_logic_vector(0 to 18);
clear, clock : IN std_logic
);
end component;
for all : input_dp use entity work.input_dp(rtl1);
signal sig_con_out : std_logic_vector(0 to 18);
begin
inputcon : input_controller
port map
(
clock => clock,
s_tart => s_tart,
reset => clear,
finish => finish,
control_out => sig_con_out
);
inputdp : input_dp
port map
(
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
h => h,
i => i,
ctrl(0) => sig_con_out(0),
ctrl(1) => sig_con_out(1),
ctrl(2) => sig_con_out(2),
ctrl(3) => sig_con_out(3),
ctrl(4) => sig_con_out(4),
ctrl(5) => sig_con_out(5),
ctrl(6) => sig_con_out(6),
ctrl(7) => sig_con_out(7),
ctrl(8) => sig_con_out(8),
ctrl(9) => sig_con_out(9),
ctrl(10) => sig_con_out(10),
ctrl(11) => sig_con_out(11),
ctrl(12) => sig_con_out(12),
ctrl(13) => sig_con_out(13),
ctrl(14) => sig_con_out(14),
ctrl(15) => sig_con_out(15),
ctrl(16) => sig_con_out(16),
ctrl(17) => sig_con_out(17),
ctrl(18) => sig_con_out(18),
clock => clock,
clear => clear
);
end rtl2;
| mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_or.vhd | 2 | 564 | library ieee;
use ieee.std_logic_1164.all;
entity c_or is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_or;
architecture behavior of c_or is
begin
P0 : process (input1, input2)
variable result : std_logic_vector(width - 1 downto 0);
begin
outer : for n in width - 1 downto 0 loop
result(n) := input1(n) or input2(n);
end loop outer;
output <= result;
end process P0;
end behavior; | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_signal.vhd | 1 | 1482 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_signal is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
store, update, clear, clock : in std_logic;
output : out std_logic_vector((width + 1) downto 0)
);
end c_signal;
architecture behavior of c_signal is
begin
P0 : process (clock, store, update, input, clear)
variable In_latch : std_logic_Vector((width - 1) downto 0);
variable Out_latch : std_logic_Vector((width - 1) downto 0);
variable out_var : std_logic_Vector((width - 1) downto 0);
variable sig_stable : std_logic;
variable sig_quiet : std_logic;
begin
if (clock = '1' and not clock'STABLE and store = '1') then
In_latch := Input;
sig_quiet := '0';
end if;
if (clock = '1' and not clock'STABLE and update = '1') then
sig_stable := '1';
L1 : for I in width - 1 downto 0 loop
if not (In_latch(I) = Out_latch(I)) then
sig_stable := '0';
exit L1;
end if;
end loop L1;
Out_latch := In_latch;
output((width - 1) downto 0) <= Out_latch;
output(width) <= sig_stable;
output(width + 1) <= sig_quiet;
sig_quiet := '1';
end if;
if (clear = '1') then
L2 : for I in (width - 1) downto 0 loop
In_latch(I) := '0';
Out_latch(I) := '0';
end loop L2;
output((width - 1) downto 0) <= Out_latch;
output(width) <= '1';
output(width + 1) <= '1';
sig_quiet := '1';
end if;
end process P0;
end behavior; | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/test_shiftreg.vhd | 1 | 2541 | use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_shiftreg is end;
architecture test_shiftreg of test_shiftreg is
component shift_reg
generic (width : INTEGER := 4);
port (input : in std_logic_vector((width - 1) downto 0);
control:in std_logic_vector(1 downto 0);
Clear :in std_logic; clock : in std_logic;
Output : out std_logic_vector((width - 1) downto 0));
end component;
for all : shift_reg use entity work.shift_reg(behavior);
signal INPUT : std_logic_vector(3 downto 0);
signal control : std_logic_vector(1 downto 0);
signal CLEAR : std_logic ;
SIGNAL clock : std_logic;
signal OUTPUT : std_logic_vector(3 downto 0);
begin
Latch1 : shift_reg generic map(4)
port map( input, control, clear, clock , output);
test_process : process
begin
----------- check clear ----------------
CLEAR <= '1';
control <= "01" ;
clock <= '1';
control <= "01";
input <= "1101";
wait for 10 ns;
clock <= '0';
wait for 10 ns;
CLEAR <= '1';
control <= "01" ;
clock <= '1';
control <= "01";
input <= "0111";
wait for 10 ns;
clock <= '0';
wait for 10 ns;
----------- check Control ---------------
CLEAR <= '0';
control <= "01";
clock <= '1';
input <= "0100";
wait for 10 ns;
clock <= '0';
wait for 10 ns;
control <= "10";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
control <= "01";
wait for 10 ns;
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
control <= "11";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
CLEAR <= '1';
control <= "11";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
wait;
end process test_process ;
end test_shiftreg;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
| mit |
skrasser/papilio_synth | hdl/dac.vhd | 1 | 530 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac is
port (pulse : out STD_LOGIC;
data : in STD_LOGIC_VECTOR(7 downto 0);
clk : in STD_LOGIC
);
end dac;
architecture behavioral of dac is
signal sum : STD_LOGIC_VECTOR(8 downto 0) := (others => '0');
begin
pulse <= sum(8);
process(clk)
begin
if rising_edge(clk) then
sum <= std_logic_vector(unsigned("0" & sum(7 downto 0)) + unsigned("0" & data));
end if;
end process;
end behavioral;
| mit |
jamesots/learnfpga | midi/tb/shift_out_tb.vhdl | 1 | 2508 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:19 01/31/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/midi/tb/shift_out_tb.vhdl
-- Project Name: midi
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: shift_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY shift_out_tb IS
END shift_out_tb;
ARCHITECTURE behavior OF shift_out_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shift_out
PORT(
par_in : IN std_logic_vector(9 downto 0);
load : IN std_logic;
ser_out : OUT std_logic;
clk : IN std_logic;
ce : IN std_logic
);
END COMPONENT;
--Inputs
signal par_in : std_logic_vector(9 downto 0) := (others => '0');
signal load : std_logic := '0';
signal clk : std_logic := '0';
signal ce : std_logic := '0';
--Outputs
signal ser_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shift_out PORT MAP (
par_in => par_in,
load => load,
ser_out => ser_out,
clk => clk,
ce => ce
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
load <= '0';
ce <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
par_in <= "0001110001";
load <= '1';
wait for clk_period*10;
load <= '0';
ce <= '1';
-- insert stimulus here
wait;
end process;
END;
| mit |
gustapp/labdig | exp4/transmissão/unidade_controle_transmissao.vhd | 1 | 1906 | library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_transmissao is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
CTS : in std_logic;
DTR : out std_logic;
RTS : out std_logic;
enable_transmissao : out std_logic;
envioOk : out std_logic;
s_estado : out std_logic_vector(1 downto 0)); -- depuracao
end unidade_controle_transmissao;
architecture unidade_controle_transmissao_arch of unidade_controle_transmissao is
type tipo_estado is (inicial, ligado, transmissao, espera);
signal estado : tipo_estado;
begin
envioOk <= CTS;
process (clock, estado, reset, liga, enviar)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial =>
if liga = '1' then
estado <= ligado;
end if;
when ligado =>
if liga = '1' then
if enviar = '1' then
estado <= espera;
end if;
else
estado <= inicial;
end if;
when espera =>
if enviar = '1' then
if CTS = '1' then
estado <= transmissao;
end if;
else
estado <= ligado;
end if;
when transmissao =>
if enviar = '0' then
estado <= ligado;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when inicial =>
s_estado <= "00";
DTR <= '0';
RTS <= '0';
enable_transmissao <= '0';
when ligado =>
s_estado <= "01";
DTR <= '1';
RTS <= '0';
enable_transmissao <= '0';
when espera =>
s_estado <= "10";
DTR <= '1';
RTS <= '1';
enable_transmissao <= '0';
when transmissao =>
s_estado <= "11";
DTR <= '1';
RTS <= '1';
enable_transmissao <= '1';
end case;
end process;
end unidade_controle_transmissao_arch; | mit |
gustapp/labdig | Exp4/FD_receptor.vhd | 1 | 343 | library IEEE;
use IEEE.std_logic_1164.all;
entity FD_receptor is
port(
CD, RD, enable_recepcao : in std_logic;
temDadoRecebido, DadoRecebido : out std_logic
);
end FD_receptor;
architecture fluxo_dados of FD_receptor is
begin
temDadoRecebido <= CD;
DadoRecebido <= enable_recepcao and RD;
end fluxo_dados;
| mit |
jamesots/learnfpga | oscilloscope/vhdl/shift_in.vhdl | 2 | 720 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- shifts data into the LSB
entity shift_in is
generic (
width : positive
);
port (
reset : in std_logic;
clk : in std_logic;
ce : in std_logic;
ser_in : in std_logic;
par_out : out std_logic_vector(width - 1 downto 0)
);
end shift_in;
architecture behavioral of shift_in is
signal par : std_logic_vector(width - 1 downto 0) := (others => '0');
begin
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
par <= (others => '0');
elsif (ce = '1') then
par <= par(width - 2 downto 0) & ser_in;
end if;
end if;
end process;
par_out <= par;
end behavioral;
| mit |
jamesots/learnfpga | drum1/vhdl/clock_divider.vhdl | 1 | 810 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
generic (
divisor : positive
);
Port (
clk_in : in std_logic;
clk_out : out std_logic;
reset : in std_logic
);
end clock_divider;
architecture behavioral of clock_divider is
begin
process(clk_in)
variable t : std_logic := '0';
variable counter : integer range 0 to divisor + 1 := 0;
begin
if rising_edge(clk_in) then
if (reset = '1') then
counter := 0;
t := '0';
else
if counter = divisor then
counter := 0;
if t = '0' then
t := '1';
else
t := '0';
end if;
else
counter := counter + 1;
end if;
clk_out <= t;
end if;
end if;
end process;
end behavioral;
| mit |
gustapp/labdig | Exp5/cronometro/contador_min_seg_bcd.vhd | 1 | 2259 | -- contador_min_seg_bcd.vhd
-- contador de minutos e segundos com saida bcd
-- com suporte a sinal de tick enable
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.alL;
entity contador_min_seg_bcd is
port (
CLK, zera, conta, tick: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR (15 downto 0); -- saída em decimal -> minutos e segundos
fim: out STD_LOGIC
);
end contador_min_seg_bcd;
architecture contador_min_seg_bcd_arch of contador_min_seg_bcd is
type int_array is array(0 to 3) of integer;
signal dig: int_array; -- digitos do contador em integer
begin
process (CLK,zera,conta,tick,dig)
begin
if zera='1' then
for i in 0 to 3 loop dig(i) <= 0; end loop; -- zera digitos
elsif CLK'event and CLK='1' then
if conta='1' and tick='1' then
if dig(3)=5 and dig(2)=9 and dig(1)=5 and dig(0)=9 then -- fim da contagem
for i in 0 to 3 loop dig(i) <= 0; end loop;
else
-- atualiza digitos (tempo+1)
if dig(0)=9 then
dig(0) <= 0; dig(1) <= dig(1)+1;
if dig(1)=5 then
dig(1) <= 0; dig(2) <= dig(2)+1;
if dig(2)=9 then
dig(2) <= 0; dig(3) <= dig(3)+1;
if dig(3)=5 then
dig(3) <= 0;
else
dig(3) <= dig(3)+1;
end if;
else
dig(2) <= dig(2)+1;
end if;
else
dig(1) <= dig(1)+1;
end if;
else
dig(0) <= dig(0)+1;
end if;
end if;
end if;
end if;
-- saida fim=1 quando em 59min50seg
if dig(3)=5 and dig(2)=9 and dig(1)=5 and dig(0)=9 then fim <= '1'; else fim <= '0'; end if;
-- converte contagem interna para a saida em bcd
Q(3 downto 0) <= conv_std_logic_vector(dig(0), 4);
Q(7 downto 4) <= conv_std_logic_vector(dig(1), 4);
Q(11 downto 8) <= conv_std_logic_vector(dig(2), 4);
Q(15 downto 12) <= conv_std_logic_vector(dig(3), 4);
end process;
end contador_min_seg_bcd_arch; | mit |
jamesots/learnfpga | analogue2/vhdl/analogue2.vhdl | 1 | 2208 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity analogue2 is
Port (
clk50 : in STD_LOGIC;
ad_dout : in STD_LOGIC;
ad_din : out STD_LOGIC;
ad_cs : out STD_LOGIC;
ad_sclk : out STD_LOGIC;
leds : out STD_LOGIC_VECTOR(7 downto 0)
);
end analogue2;
architecture Behavioral of analogue2 is
component clock_divider
generic (
divisor : positive
);
port (
clk_in : in std_logic;
clk_out : out std_logic;
reset : in std_logic
);
end component;
component adc
port (
ad_port : in STD_LOGIC_VECTOR (2 downto 0);
ad_value : out STD_LOGIC_VECTOR (11 downto 0);
ad_newvalue : out STD_LOGIC;
clk : in STD_LOGIC;
ad_dout : in STD_LOGIC;
ad_din : out STD_LOGIC;
ad_cs : out STD_LOGIC
);
end component;
signal clk_adc : std_logic;
signal newvalue : std_logic;
signal value : std_logic_vector(11 downto 0);
begin
div : clock_divider
generic map (
divisor => 1
)
port map (
clk_in => clk50,
clk_out => clk_adc,
reset => '0'
);
adc1 : adc port map (
ad_port => "111",
ad_value => value,
ad_newvalue => newvalue,
clk => clk_adc,
ad_dout => ad_dout,
ad_din => ad_din,
ad_cs => ad_cs
);
ad_sclk <= clk_adc;
process(clk50)
begin
if rising_edge(clk50) then
if newvalue = '1' then
if (unsigned(value) < 1) then -- was 256, changed to 1 to check if we actually get a zero at all
leds <= "00000000";
elsif (unsigned(value) < 768) then
leds <= "00000001";
elsif (unsigned(value) < 1280) then
leds <= "00000011";
elsif (unsigned(value) < 1792) then
leds <= "00000111";
elsif (unsigned(value) < 2304) then
leds <= "00001111";
elsif (unsigned(value) < 2816) then
leds <= "00011111";
elsif (unsigned(value) < 3328) then
leds <= "00111111";
elsif (unsigned(value) < 4095) then -- changed to 4095 to seee if we actually get a 4095
leds <= "01111111";
else
leds <= "11111111";
end if;
end if;
end if;
end process;
end Behavioral;
| mit |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/Miscellaneous/kcpsm6_without_slice_packing_attributes.vhd | 2 | 109641 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
--
-- 4th July 2012 - ** SPECIAL VERSION **
--
-- Only use this version if problems are encountered during MAP and all
-- other workarounds described in the 'READ_ME_FIRST.txt' file have been
-- considered.
--
-- In this version all the Slice packing attributes have been commented out
-- and it should be expected that the implementation will be larger than the
-- 26-30 Slices normally achieved. Lower performance may also result.
--
-- Version 1.3 - 21st May 2014.
-- Addition of WebTalk information.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
-- attribute hblknm : string;
-- attribute hblknm of reset_lut : label is "kcpsm6_control";
-- attribute hblknm of run_flop : label is "kcpsm6_control";
-- attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state_lut : label is "kcpsm6_control";
-- attribute hblknm of t_state1_flop : label is "kcpsm6_control";
-- attribute hblknm of t_state2_flop : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
-- attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
-- attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
-- attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
-- attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
-- attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
-- attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
-- attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
-- attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
-- attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
-- attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
-- attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
-- attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
-- attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
-- attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
-- attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
-- attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
-- attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
-- attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
-- attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
-- attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
-- attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
-- attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
-- attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
-- attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_lut : label is "kcpsm6_stack1";
-- attribute hblknm of bank_flop : label is "kcpsm6_stack1";
-- attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
-- attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
-- attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
-- attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
-- attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
-- attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
-- attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
-- attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
-- attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
-- attribute hblknm : string;
-- attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
-- attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
-- attribute hblknm : string;
-- attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
-- attribute hblknm : string;
-- attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
-- attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
-- attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
-- attribute hblknm : string;
-- attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
-- attribute hblknm : string;
-- attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
-- attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
| mit |
bravo95/SecondProcessor | register.vhd | 1 | 974 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity regis is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC := '0' ;
datain : in STD_LOGIC_VECTOR (31 downto 0) := x"00000000" ;
dataout : out STD_LOGIC_VECTOR (31 downto 0) := x"00000000" );
end regis;
architecture Behavioral of regis is
signal res: std_logic_vector(31 downto 0):= x"00000000";
begin
res <= datain;
process (clk, rst)
begin
if (clk'event and clk = '1' and rst = '0') then
if datain = "00000000000000000000000001000000" then
dataout<= "00000000000000000000000000000000";
else
dataout <= res;
end if;
end if;
if (rst = '1') then
dataout <= "00000000000000000000000000000000";
end if;
end process;
--process (rst)
--begin
-- if (rst'event and rst = '1') then
-- res <= x"00000000";
-- dataout <= res;
-- end if;
--end process;
end Behavioral;
| mit |
gustapp/labdig | Exp4/InterfaceModem.vhd | 1 | 1581 | library IEEE;
use IEEE.std_logic_1164.all;
entity InterfaceModem is
port (CLOCK, RESET, LIGA, DadoSerial, CD, RD, CTS : in std_logic;
Enviar : in std_logic;
DTR, RTS, TD, temDadoRecebido, DadoRecebido : out std_logic;
envioOK : out std_logic;
estado_transmissao, estado_recepcao : out std_logic_vector(1 downto 0));
end InterfaceModem;
architecture hierarquico of InterfaceModem is
component transmissor is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
dado_serial : in std_logic;
CTS : in std_logic;
envioOk : out std_logic;
DTR : out std_logic;
RTS : out std_logic;
TD : out std_logic;
d_estado : out std_logic_vector(1 downto 0));
end component;
component receptor is
port (
CLOCK, RESET, LIGA, CD, RD : in std_logic;
DTR, temDadoRecebido, DadoRecebido : out std_logic;
dep_estado : out std_logic_vector(1 downto 0)
);
end component;
signal s_dtr_1, s_dtr_2 : std_logic;
begin
R: transmissor port map(LIGA, Enviar, RESET, CLOCK, DadoSerial, CTS, envioOK, s_dtr_1, RTS, TD, estado_transmissao);
T: receptor port map(CLOCK, RESET, LIGA, CD, RD, s_dtr_2, temDadoRecebido, DadoRecebido, estado_recepcao);
DTR <= s_dtr_1 or s_dtr_2;
end hierarquico;
| mit |
bravo95/SecondProcessor | PSR_modifier_tb.vhd | 1 | 2122 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
ENTITY PSR_modifier_tb IS
END PSR_modifier_tb;
ARCHITECTURE behavior OF PSR_modifier_tb IS
COMPONENT PSR_modifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
RESULT : IN std_logic_vector(31 downto 0);
RS1 : IN std_logic_vector(31 downto 0);
RS2 : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal RESULT : std_logic_vector(31 downto 0) := (others => '0');
signal RS1 : std_logic_vector(31 downto 0) := (others => '0');
signal RS2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal NZVC : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSR_modifier PORT MAP (
ALUOP => ALUOP,
RESULT => RESULT,
RS1 => RS1,
RS2 => RS2,
NZVC => NZVC
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
ALUOP <= "010000" ; -- addcc
RESULT <= "11111111111111111111111111111110" ;
RS1 <= "11111111111111111111111111111111" ;
RS2 <= "11111111111111111111111111111111" ;
wait for 10 ns;
ALUOP <= "010100" ; --SUBCC
RESULT <= "00000000000000000000000000000000" ;
RS1 <= "01111111111111111111111111111111" ;
RS2 <= "01111111111111111111111111111111";
wait for 10 ns;
ALUOP <= "010001" ; -- andcc
RESULT <= "00000000000000000000000000000000" ;
RS1 <= "11111111111111111111111111111111" ;
RS2 <= "00000000000000000000000000000000" ;
wait for 10 ns;
ALUOP <= "010010" ;--orcc
RESULT <= "10000000000000000000000000000000" ;
RS1 <= "00000000000000000000000000000000" ;
RS2 <= "10000000000000000000000000000000" ;
wait for 10 ns;
--hola
wait;
end process;
END;
| mit |
jamesots/learnfpga | midi2/tb/midi2_tb.vhdl | 1 | 2109 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:40 01/31/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/midi/tb/midi_tb.vhdl
-- Project Name: midi
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: midi
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY midi2_tb IS
END midi2_tb;
ARCHITECTURE behavior OF midi2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT midi2
PORT(
clk32 : IN std_logic;
portc11 : OUT std_logic;
leds : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk32 : std_logic := '0';
--Outputs
signal portc11 : std_logic;
signal leds : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk32_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: midi2 PORT MAP (
clk32 => clk32,
portc11 => portc11,
leds => leds
);
-- Clock process definitions
clk32_process :process
begin
clk32 <= '0';
wait for clk32_period/2;
clk32 <= '1';
wait for clk32_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk32_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit |
bravo95/SecondProcessor | SEU.vhd | 1 | 470 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SEU is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
seuout : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture Behavioral of SEU is
begin
process( imm13)
begin
if(imm13(12) = '1') then
seuout <= "1111111111111111111" & imm13;
else
seuout <= "0000000000000000000" & imm13;
end if;
end process;
end Behavioral;
| mit |
bravo95/SecondProcessor | InstruccionMemory.vhd | 1 | 1526 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
--int k = 6
entity InstruccionMemory is
Port ( address : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstruccionMemory;
architecture syn of InstruccionMemory is
type rom_type is array (0 to 63) of std_logic_vector (31 downto 0);
signal ROM : rom_type:= ("10000010000100000010000000000101",
"10100000000100000011111111111000",
"10100010000100000010000000000100",
"10110001001010000110000000000010",
"10110011001101000110000000000001",
"10000001111010000010000000000000",
"10100000000000000110000000000011",
"10000001111000000010000000000000",
"10000000101000000010000000000100",
"10000100010000000000000000000001",
"10010000000100000000000000010000",
others => "00000000000000000000000000000000");
begin
process (rst,Address)
begin
if (rst = '1') then
instruction <= "00000000000000000000000000000000";
-- Address => "00000000000000000000000000000000"; la salida se pone en 0 mientras reset es 1
-- pero cuando este valor es 0 vuelve y toma el actual del address.
else
instruction <= ROM(conv_integer(address));
end if;
end process;
end syn;
| mit |
bravo95/SecondProcessor | Processor_tb.vhd | 1 | 1108 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Processor_tb IS
END Processor_tb;
ARCHITECTURE behavior OF Processor_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Processor
PORT(
CLK : IN std_logic;
RST : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Processor PORT MAP (
CLK => CLK,
RST => RST,
ALURESULT => ALURESULT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
-- insert stimulus here
wait;
end process;
END;
| mit |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/ROM_form_templates/ROM_form_7S_2K_with_error_detection_14March13.vhd | 1 | 52574 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 2K program for KCPSM6 in a 7-Series device using a
RAMB36E1 primitive with a content verifying CRC-16 circuit.
PLEASE READ THE DESCRIPTIONS AND ADVICE LATER IN THIS TEMPLATE OR CONTAINED IN THE
ASSEMBLED FILE.
Ken Chapman (Xilinx Ltd)
9th August 2012 - Initial Release
8th October 2012 - Optimised implementation.
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 2K program for KCPSM6 in a 7-Series device using a
-- RAMB36E1 primitive with a content verifying CRC-16 error detection circuit.
--
-- NOTE - Compared with any of the normal program memory definitions for KCPSM6 this
-- module has additional inputs and outputs associated with the error detection
-- feature. Only use this module if there is a clear requirement to perform
-- error detection and do consider all the factors described below when
-- incorporating it in a design.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_7S_2K_with_error_detection_14March13.vhd
--
--
-- Error Detection Feature
-- -----------------------
--
-- In this application the BRAM is being used as a ROM and therefore the contents should
-- not change during normal operation. If for any reason the contents of the memory should
-- change then there is the potential for KCPSM6 to execute an instruction that is either
-- different to that expected or even an invalid op-code neither of which would be
-- desirable. Obviously this should not happen and in majority of cases it will be more
-- than acceptable to assume that it never will. However, designs in which extreme levels
-- of reliability or design security are required may consider that the special error
-- detection feature provided in this memory definition is useful.
--
-- This memory definition provides KCPSM6 with access to the program in the conventional
-- way using the first port of the BRAM. Then the second port of the BRAM is used to
-- continuously scan the whole memory and compute the CRC-16 of the entire contents. At
-- the end of each scan the result of each CRC calculation is compared with the expected
-- value (which was computed by the KCPSM6 assembler). If the value does not match then
-- the 'scan_error' output is forced High to inform the system of a potential corruption
-- somewhere within the memory.
--
--
-- SEU Mitigation
-- --------------
--
-- One concern for the very highest reliability systems are Single Event Upsets (SEU)
-- caused by radiation. FIT rates for BRAM are published and updated quarterly in UG116
-- and these should be used to evaluate the potential failure rates prior to using this
-- memory with its error detection circuit. It is vital to remember that everything in a
-- system contributes to the overall reliability. As such, the thoughtless addition of
-- features such as BRAM content error detection could in fact lower the overall
-- reliability of the system which obviously wouldn't be the intention! Two of the factors
-- to consider are as follows:-
--
-- a) Configuration memory is also susceptible to SEU and may impact the operation of
-- a design. Again the FIT rates are published in UG116 and the failure rates need
-- to be estimated. PicoBlaze itself, the error detection circuit defined in this
-- file and whatever you monitor and control the error detection circuit with are
-- all associated with configuration memory and therefore the potential exists for
-- a 'false alarm'. For example, and SEU could flip a configuration memory cell that
-- altered the logic of the error detection circuit resulting in a 'scan_error' even
-- though the BRAM contents are good.
--
-- b) If one bit within the BRAM is flipped by an SEU (the typical effect), it could
-- take up to ~73,740 'scan_clk' cycles for the error to be detected and reported.
-- This worst case detection time is equivalent two complete scans of the memory
-- and would only occur if the SEU flips a bit very close to the start of the
-- memory (address zero) just after the scan has just passed that location. Hence,
-- the average detection time will be one complete scan (36,873 'scan_clk' cycles).
-- During the time taken to detect and report the error, and any time leading up to
-- your decision to take some suitable action, KCPSM6 may execute the instruction
-- that has been corrupted. The impact of executing that corrupted instruction is
-- anyone's guess! However, in terms of estimating the failure rate it is important
-- to recognise that KCPSM6 must actually read and execute the corrupted instruction
-- for anything unexpected to occur. So whilst the error detection circuit will
-- report when an error is present in the memory it definitely does not mean that
-- KCPSM6 has or will definitely go wrong. KCPSM6 programs rarely occupy all the
-- memory locations so the failure rate estimate should be scaled accordingly.
-- Likewise, most programs consist of some code that is used frequently and other
-- code which is only used occasionally (e.g. some code is only used during
-- initialisation). So once again the failure rate can often be scaled appropriately
-- to reflect the actual code. Due to these scaling factors there is quite a high
-- probability that a real upset will be detected and reported but for there to be
-- no effect on the program execution. Whilst this is not a 'false alarm' is may
-- appear to be. Detection of any error is valuable in a fail-safe system but it can
-- adversely impact the overall availability of systems if every alarm results in
-- an interruption to service. Therefore, deciding what action to take when an error
-- is detected is critical before opting to us this memory module with KCPSM6.
--
--
-- Design Security
-- ---------------
--
-- Devices of the 7-Series which this memory definition is intended to service provide
-- Bitstream Security in the form of AES encryption so obviously this should be of
-- high relevance for anyone concerned with design security. However, there may be
-- reasons not to use that feature or a desire to further enhance security in other ways.
-- Whilst it would be a significant challenge to reverse engineer a bitstream (assuming it
-- wasn't encrypted or was somehow decrypted), it is feasible to alter or tamper with the
-- bits in what is often referred to as 'side attacks'.
--
-- On a scale of difficulty it should be recognised that BRAM contents are one of the
-- easier targets for such attacks. Note that the DATA2MEM tool (see UG658) intended to
-- help accelerate design development would also be a useful tool for an attacker!
-- Obviously the ability to tamper with BRAM contents means that the program for a KCPSM6
-- processor could be altered or replaced. Depending on the purpose of that code it could
-- definitely compromise security.
--
-- Since the error detection circuit will report any changes to the memory contents this
-- scheme can also be used to detect attacks and somehow disable the design to prevent the
-- attacker making progress. For example, the 'scan_error' signal could be used to
-- permanently reset KCPSM6 or be used to disable something else in the design such as
-- putting critical output pins of the device into a high impedance state.
--
--
-- Using the Error Detection Feature in a Design
-- ---------------------------------------------
--
-- Whether this feature is used for SEU mitigation or design security it is highly
-- recommended that signals and logic associated with the error detection feature remain
-- isolated from the KCPSM6 processor; i.e. it certainly wouldn't be a good idea to
-- monitor the error signal with the same KCPSM6 given that any change to the
-- program may prevent KCPSM6 from reacting as intended in the first place. However,
-- it would be a valid arrangement for two or more KCPSM6 processors to monitor the
-- health of each other's memory providing they too had a reasonable degree of
-- independence(e.g. avoiding a common point such as using the same clock).
--
-- As with most digital circuits the clock is critical for reliable operation. In terms
-- failure rates then SEU are so rare that things like an irregular clock cycle or glitch
-- possibly caused by power surge could be as likely to impact the integrity of the
-- CRC-16 calculation and result in a false alarm. So always give consideration to the
-- source of your clock including any use of clock division or multiplication schemes
-- implemented within the FPGA before it is applied to the 'scan_clk' input of this module.
--
-- In most applications the 'scan_reset' control can be driven or tied Low. The report of
-- any error would be a rare event but would generally be considered a permanent error
-- until the device is reconfigured. However, there is the small possibility that an SEU
-- or clock glitch could impact the logical operation of the error detection circuit
-- resulting in a 'false alarm'. In these situations, the device level SEU mitigation
-- measures would detect and subsequently correct the configuration memory error or the
-- clock source would recover. Applying a synchronous pulse to 'scan_reset' would then
-- clear the false alarm and allow the memory checking to continue. Ultimately, design
-- for reliability must consider the interaction between all elements of the system and
-- can not simply focus on one issue like the BRAM contents.
--
-- In situations where the clock may take time to settle following device configuration
-- the error detection circuit should be held in reset until the integrity of the clock
-- can be assured.
--
-- Note that the 'scan_error' signal has be deliberately designed to 'latch' any error
-- that is detected (i.e. false alarms are not cleared automatically by a subsequent good
-- scan of the memory). This scheme ensures that no error reports can be missed by a
-- monitor which only checks occasionally. It is always the responsibility of the system
-- to decide what action to take when an error is reported. Some systems may initially
-- reset the error detection circuit in order to confirm the error is permanent before
-- taking more significant actions.
--
-- The 'scan_complete' signal is a single clock cycle pulse generated at the end of each
-- CRC-16 calculation. This signal could be ignored but for both reliability and security
-- purposes it is extremely useful to know that the error detection circuit is actually
-- working and these pulses will confirm that it is (one pulse every 36,873 'scan_clk'
-- cycles). For example, these pulses confirm that the clock is being supplied and has not
-- been disabled by an SEU, oscillator failure, board defect or a malicious attacker.
--
--
-------------------------------------------------------------------------------------------
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic;
scan_error : out std_logic;
scan_complete : out std_logic;
scan_reset : in std_logic;
scan_clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
--
signal previous_scan_address : std_logic_vector(11 downto 0);
signal sa_carry_primer : std_logic_vector(11 downto 0);
signal scan_address_carry : std_logic_vector(11 downto 0);
signal scan_address_value : std_logic_vector(11 downto 0);
signal scan_address : std_logic_vector(11 downto 0);
signal scan_address_ce_value : std_logic;
signal scan_address_ce : std_logic;
signal scan_data : std_logic_vector(8 downto 0);
signal scan_bit_value : std_logic_vector(3 downto 0);
signal scan_bit : std_logic_vector(3 downto 0);
signal scan_mid : std_logic;
signal scan_high : std_logic;
signal scan_byte : std_logic;
signal crc_reset_value : std_logic;
signal crc_reset : std_logic;
signal crc : std_logic_vector(16 downto 1);
signal crc1_value : std_logic;
signal crc2_value : std_logic;
signal crc3_value : std_logic;
signal crc16_value : std_logic;
signal serial_data_value : std_logic;
signal serial_data : std_logic;
signal last_address_value : std_logic;
signal last_address : std_logic;
signal last_bit : std_logic;
signal end_of_scan : std_logic;
signal crc_test : std_logic;
signal crc_check_value : std_logic;
signal crc_check : std_logic;
--
attribute hblknm : string;
attribute hblknm of crc16_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc1_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc2_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc3_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc4_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc5_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc6_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc7_flop : label is "kcpsm6_program_crc1";
attribute hblknm of crc1_lut : label is "kcpsm6_program_crc1";
attribute hblknm of crc3_lut : label is "kcpsm6_program_crc1";
--
attribute hblknm of crc8_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc9_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc10_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc11_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc12_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc13_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc14_flop : label is "kcpsm6_program_crc2";
attribute hblknm of crc15_flop : label is "kcpsm6_program_crc2";
--
attribute hblknm of scan_bit0_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit1_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit2_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit3_flop : label is "kcpsm6_program_crc3";
attribute hblknm of crc_reset_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_address_ce_flop : label is "kcpsm6_program_crc3";
attribute hblknm of crc_check_flop : label is "kcpsm6_program_crc3";
attribute hblknm of last_address_flop : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit01_lut : label is "kcpsm6_program_crc3";
attribute hblknm of scan_bit23_lut : label is "kcpsm6_program_crc3";
attribute hblknm of crc_reset_lut : label is "kcpsm6_program_crc3";
attribute hblknm of crc_check_lut : label is "kcpsm6_program_crc3";
--
attribute hblknm of serial_data_flop : label is "kcpsm6_program_crc4";
attribute hblknm of last_bit_flop : label is "kcpsm6_program_crc4";
attribute hblknm of end_of_scan_flop : label is "kcpsm6_program_crc4";
attribute hblknm of scan_complete_flop : label is "kcpsm6_program_crc4";
attribute hblknm of serial_data_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_mid_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_high_lut : label is "kcpsm6_program_crc4";
attribute hblknm of scan_byte_muxf7 : label is "kcpsm6_program_crc4";
--
attribute hblknm of scan_address0_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address0_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address1_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address2_muxcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_flop : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_lut : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_xorcy : label is "kcpsm6_program_crc5";
attribute hblknm of scan_address3_muxcy : label is "kcpsm6_program_crc5";
--
attribute hblknm of scan_address4_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address4_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address5_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address6_muxcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_flop : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_lut : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_xorcy : label is "kcpsm6_program_crc6";
attribute hblknm of scan_address7_muxcy : label is "kcpsm6_program_crc6";
--
attribute hblknm of scan_address8_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address8_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address9_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address10_muxcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_flop : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_lut : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_xorcy : label is "kcpsm6_program_crc7";
attribute hblknm of scan_address11_muxcy : label is "kcpsm6_program_crc7";
--
begin
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
--
address_b <= '1' & scan_address(11 downto 0) & "111";
data_in_b <= "000000000000000000000000000000000000";
scan_data <= data_out_b(32) & data_out_b(7 downto 0);
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => '1',
CLKBWRCLK => scan_clk,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => "00000000",
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
-- Error Detection Circuit
--
scan_mid_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => scan_data(1),
I1 => scan_data(2),
I2 => scan_data(3),
I3 => scan_data(4),
I4 => scan_bit(0),
I5 => scan_bit(1),
O => scan_mid);
--
scan_high_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => scan_data(5),
I1 => scan_data(6),
I2 => scan_data(7),
I3 => scan_data(8),
I4 => scan_bit(0),
I5 => scan_bit(1),
O => scan_high);
--
scan_byte_muxf7: MUXF7
port map( I0 => scan_mid,
I1 => scan_high,
S => scan_bit(2),
O => scan_byte);
--
crc1_lut: LUT6_2
generic map (INIT => X"F0F0F0F066666666")
port map( I0 => serial_data,
I1 => crc(16),
I2 => crc(1),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => crc1_value,
O6 => crc2_value);
--
crc3_lut: LUT6_2
generic map (INIT => X"C33C0000A55A0000")
port map( I0 => crc(2),
I1 => crc(15),
I2 => crc(16),
I3 => serial_data,
I4 => '1',
I5 => '1',
O5 => crc3_value,
O6 => crc16_value);
--
crc1_flop: FDR
port map ( D => crc1_value,
Q => crc(1),
R => crc_reset,
C => scan_clk);
--
crc2_flop: FDR
port map ( D => crc2_value,
Q => crc(2),
R => crc_reset,
C => scan_clk);
--
crc3_flop: FDR
port map ( D => crc3_value,
Q => crc(3),
R => crc_reset,
C => scan_clk);
--
crc4_flop: FDR
port map ( D => crc(3),
Q => crc(4),
R => crc_reset,
C => scan_clk);
--
crc5_flop: FDR
port map ( D => crc(4),
Q => crc(5),
R => crc_reset,
C => scan_clk);
--
crc6_flop: FDR
port map ( D => crc(5),
Q => crc(6),
R => crc_reset,
C => scan_clk);
--
crc7_flop: FDR
port map ( D => crc(6),
Q => crc(7),
R => crc_reset,
C => scan_clk);
--
crc8_flop: FDR
port map ( D => crc(7),
Q => crc(8),
R => crc_reset,
C => scan_clk);
--
crc9_flop: FDR
port map ( D => crc(8),
Q => crc(9),
R => crc_reset,
C => scan_clk);
--
crc10_flop: FDR
port map ( D => crc(9),
Q => crc(10),
R => crc_reset,
C => scan_clk);
--
crc11_flop: FDR
port map ( D => crc(10),
Q => crc(11),
R => crc_reset,
C => scan_clk);
--
crc12_flop: FDR
port map ( D => crc(11),
Q => crc(12),
R => crc_reset,
C => scan_clk);
--
crc13_flop: FDR
port map ( D => crc(12),
Q => crc(13),
R => crc_reset,
C => scan_clk);
--
crc14_flop: FDR
port map ( D => crc(13),
Q => crc(14),
R => crc_reset,
C => scan_clk);
--
crc15_flop: FDR
port map ( D => crc(14),
Q => crc(15),
R => crc_reset,
C => scan_clk);
--
crc16_flop: FDR
port map ( D => crc16_value,
Q => crc(16),
R => crc_reset,
C => scan_clk);
--
scan_bit01_lut: LUT6_2
generic map (INIT => X"0000E6660000D555")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => end_of_scan,
I5 => '1',
O5 => scan_bit_value(0),
O6 => scan_bit_value(1));
--
scan_bit23_lut: LUT6_2
generic map (INIT => X"00007F800000F878")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => end_of_scan,
I5 => '1',
O5 => scan_bit_value(2),
O6 => scan_bit_value(3));
--
scan_bit0_flop: FDR
port map ( D => scan_bit_value(0),
Q => scan_bit(0),
R => scan_reset,
C => scan_clk);
--
scan_bit1_flop: FDR
port map ( D => scan_bit_value(1),
Q => scan_bit(1),
R => scan_reset,
C => scan_clk);
--
scan_bit2_flop: FDR
port map ( D => scan_bit_value(2),
Q => scan_bit(2),
R => scan_reset,
C => scan_clk);
--
scan_bit3_flop: FDR
port map ( D => scan_bit_value(3),
Q => scan_bit(3),
R => scan_reset,
C => scan_clk);
--
crc_reset_lut: LUT6_2
generic map (INIT => X"007F000020000000")
port map( I0 => scan_bit(0),
I1 => scan_bit(1),
I2 => scan_bit(2),
I3 => scan_bit(3),
I4 => '1',
I5 => '1',
O5 => scan_address_ce_value,
O6 => crc_reset_value);
--
scan_address_ce_flop: FDR
port map ( D => scan_address_ce_value,
Q => scan_address_ce,
R => scan_reset,
C => scan_clk);
--
crc_reset_flop: FDR
port map ( D => crc_reset_value,
Q => crc_reset,
R => scan_reset,
C => scan_clk);
--
crc_check_lut: LUT6_2
generic map (INIT => X"FF00F0F088888888")
port map( I0 => scan_address_carry(11),
I1 => scan_address_ce,
I2 => crc_check,
I3 => crc_test,
I4 => end_of_scan,
I5 => '1',
O5 => last_address_value,
O6 => crc_check_value);
--
crc_check_flop: FDR
port map ( D => crc_check_value,
Q => crc_check,
R => scan_reset,
C => scan_clk);
--
last_address_flop: FDR
port map ( D => last_address_value,
Q => last_address,
R => scan_reset,
C => scan_clk);
--
scan_address0_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(0),
I5 => '1',
O5 => sa_carry_primer(0),
O6 => previous_scan_address(0));
--
scan_address0_xorcy: XORCY
port map( LI => previous_scan_address(0),
CI => '1',
O => scan_address_value(0));
--
scan_address0_muxcy: MUXCY
port map( DI => sa_carry_primer(0),
CI => '1',
S => previous_scan_address(0),
O => scan_address_carry(0));
--
scan_address0_flop: FDRE
port map ( D => scan_address_value(0),
Q => scan_address(0),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address1_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(1),
I5 => '1',
O5 => sa_carry_primer(1),
O6 => previous_scan_address(1));
--
scan_address1_xorcy: XORCY
port map( LI => previous_scan_address(1),
CI => scan_address_carry(0),
O => scan_address_value(1));
--
scan_address1_muxcy: MUXCY
port map( DI => sa_carry_primer(1),
CI => scan_address_carry(0),
S => previous_scan_address(1),
O => scan_address_carry(1));
--
scan_address1_flop: FDRE
port map ( D => scan_address_value(1),
Q => scan_address(1),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address2_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(2),
I5 => '1',
O5 => sa_carry_primer(2),
O6 => previous_scan_address(2));
--
scan_address2_xorcy: XORCY
port map( LI => previous_scan_address(2),
CI => scan_address_carry(1),
O => scan_address_value(2));
--
scan_address2_muxcy: MUXCY
port map( DI => sa_carry_primer(2),
CI => scan_address_carry(1),
S => previous_scan_address(2),
O => scan_address_carry(2));
--
scan_address2_flop: FDRE
port map ( D => scan_address_value(2),
Q => scan_address(2),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address3_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(3),
I5 => '1',
O5 => sa_carry_primer(3),
O6 => previous_scan_address(3));
--
scan_address3_xorcy: XORCY
port map( LI => previous_scan_address(3),
CI => scan_address_carry(2),
O => scan_address_value(3));
--
scan_address3_muxcy: MUXCY
port map( DI => sa_carry_primer(3),
CI => scan_address_carry(2),
S => previous_scan_address(3),
O => scan_address_carry(3));
--
scan_address3_flop: FDRE
port map ( D => scan_address_value(3),
Q => scan_address(3),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address4_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(4),
I5 => '1',
O5 => sa_carry_primer(4),
O6 => previous_scan_address(4));
--
scan_address4_xorcy: XORCY
port map( LI => previous_scan_address(4),
CI => scan_address_carry(3),
O => scan_address_value(4));
--
scan_address4_muxcy: MUXCY
port map( DI => sa_carry_primer(4),
CI => scan_address_carry(3),
S => previous_scan_address(4),
O => scan_address_carry(4));
--
scan_address4_flop: FDRE
port map ( D => scan_address_value(4),
Q => scan_address(4),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address5_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(5),
I5 => '1',
O5 => sa_carry_primer(5),
O6 => previous_scan_address(5));
--
scan_address5_xorcy: XORCY
port map( LI => previous_scan_address(5),
CI => scan_address_carry(4),
O => scan_address_value(5));
--
scan_address5_muxcy: MUXCY
port map( DI => sa_carry_primer(5),
CI => scan_address_carry(4),
S => previous_scan_address(5),
O => scan_address_carry(5));
--
scan_address5_flop: FDRE
port map ( D => scan_address_value(5),
Q => scan_address(5),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address6_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(6),
I5 => '1',
O5 => sa_carry_primer(6),
O6 => previous_scan_address(6));
--
scan_address6_xorcy: XORCY
port map( LI => previous_scan_address(6),
CI => scan_address_carry(5),
O => scan_address_value(6));
--
scan_address6_muxcy: MUXCY
port map( DI => sa_carry_primer(6),
CI => scan_address_carry(5),
S => previous_scan_address(6),
O => scan_address_carry(6));
--
scan_address6_flop: FDRE
port map ( D => scan_address_value(6),
Q => scan_address(6),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address7_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(7),
I5 => '1',
O5 => sa_carry_primer(7),
O6 => previous_scan_address(7));
--
scan_address7_xorcy: XORCY
port map( LI => previous_scan_address(7),
CI => scan_address_carry(6),
O => scan_address_value(7));
--
scan_address7_muxcy: MUXCY
port map( DI => sa_carry_primer(7),
CI => scan_address_carry(6),
S => previous_scan_address(7),
O => scan_address_carry(7));
--
scan_address7_flop: FDRE
port map ( D => scan_address_value(7),
Q => scan_address(7),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address8_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(8),
I5 => '1',
O5 => sa_carry_primer(8),
O6 => previous_scan_address(8));
--
scan_address8_xorcy: XORCY
port map( LI => previous_scan_address(8),
CI => scan_address_carry(7),
O => scan_address_value(8));
--
scan_address8_muxcy: MUXCY
port map( DI => sa_carry_primer(8),
CI => scan_address_carry(7),
S => previous_scan_address(8),
O => scan_address_carry(8));
--
scan_address8_flop: FDRE
port map ( D => scan_address_value(8),
Q => scan_address(8),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address9_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(9),
I5 => '1',
O5 => sa_carry_primer(9),
O6 => previous_scan_address(9));
--
scan_address9_xorcy: XORCY
port map( LI => previous_scan_address(9),
CI => scan_address_carry(8),
O => scan_address_value(9));
--
scan_address9_muxcy: MUXCY
port map( DI => sa_carry_primer(9),
CI => scan_address_carry(8),
S => previous_scan_address(9),
O => scan_address_carry(9));
--
scan_address9_flop: FDRE
port map ( D => scan_address_value(9),
Q => scan_address(9),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address10_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(10),
I5 => '1',
O5 => sa_carry_primer(10),
O6 => previous_scan_address(10));
--
scan_address10_xorcy: XORCY
port map( LI => previous_scan_address(10),
CI => scan_address_carry(9),
O => scan_address_value(10));
--
scan_address10_muxcy: MUXCY
port map( DI => sa_carry_primer(10),
CI => scan_address_carry(9),
S => previous_scan_address(10),
O => scan_address_carry(10));
--
scan_address10_flop: FDRE
port map ( D => scan_address_value(10),
Q => scan_address(10),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
scan_address11_lut: LUT6_2
generic map (INIT => X"FFFF000000000000")
port map( I0 => '1',
I1 => '1',
I2 => '1',
I3 => '1',
I4 => scan_address(11),
I5 => '1',
O5 => sa_carry_primer(11),
O6 => previous_scan_address(11));
--
scan_address11_xorcy: XORCY
port map( LI => previous_scan_address(11),
CI => scan_address_carry(10),
O => scan_address_value(11));
--
scan_address11_muxcy: MUXCY
port map( DI => sa_carry_primer(11),
CI => scan_address_carry(10),
S => previous_scan_address(11),
O => scan_address_carry(11));
--
scan_address11_flop: FDRE
port map ( D => scan_address_value(11),
Q => scan_address(11),
CE => scan_address_ce,
R => crc_reset,
C => scan_clk);
--
serial_data_lut: LUT6
generic map (INIT => X"CACACACACACACACA")
port map( I0 => scan_data(0),
I1 => scan_byte,
I2 => scan_bit(3),
I3 => '1',
I4 => '1',
I5 => '1',
O => serial_data_value);
--
serial_data_flop: FD
port map ( D => serial_data_value,
Q => serial_data,
C => scan_clk);
--
last_bit_flop: FD
port map ( D => last_address,
Q => last_bit,
C => scan_clk);
--
end_of_scan_flop: FD
port map ( D => last_bit,
Q => end_of_scan,
C => scan_clk);
--
scan_complete_flop: FD
port map ( D => end_of_scan,
Q => scan_complete,
C => scan_clk);
--
crc_test <= '0' when (crc = "{CRC_2K}") else '1';
--
scan_error <= crc_check;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
| mit |
jamesots/learnfpga | analogue2/vhdl/adc.vhdl | 1 | 2255 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity adc is
port (
ad_port : in std_logic_vector (2 downto 0);
ad_value : out std_logic_vector (11 downto 0);
ad_newvalue : out std_logic := '0';
clk : in std_logic;
ad_dout : in std_logic;
ad_din : out std_logic := '0';
ad_cs : out std_logic := '0'
);
end adc;
architecture behavioral of adc is
component shift_in
generic (
width : positive
);
port (
reset : in std_logic;
clk : in std_logic;
ce : in std_logic;
ser_in : in std_logic;
par_out : out std_logic_vector(width - 1 downto 0)
);
end component;
component shift_out is
generic (
width : positive
);
port (
par_in : in std_logic_vector((width - 1) downto 0);
load : in std_logic;
ser_out : out std_logic;
clk : in std_logic;
ce : in std_logic
);
end component;
signal step : integer range 0 to 18 := 16;
signal si_par_out : std_logic_vector(11 downto 0);
signal so_load : std_logic;
signal so_clk : std_logic;
begin
si : shift_in
generic map (
width => 12
)
port map (
reset => '0',
clk => clk,
ce => '1',
ser_in => ad_dout,
par_out => si_par_out
);
so : shift_out
generic map (
width => 3
)
port map (
par_in => ad_port,
load => so_load,
ser_out => ad_din,
clk => so_clk,
ce => '1'
);
so_clk <= not clk;
process(clk)
begin
if falling_edge(clk) then
case step is
when 16 =>
ad_value <= si_par_out;
ad_cs <= '1';
step <= 0;
when 0 =>
-- send cs high for one clock cycle to make sure
-- we know where our frames start
ad_cs <= '0';
ad_newvalue <= '1';
step <= 1;
when others =>
ad_cs <= '0';
ad_newvalue <= '0';
step <= step + 1;
end case;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
case step is
when 1 =>
so_load <= '1';
when others =>
so_load <= '0';
end case;
end if;
end process;
end behavioral;
| mit |
JavierRizzoA/Sacagawea | sources/DECODIFICADOR.vhd | 1 | 1494 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:18:59 06/05/2016
-- Design Name:
-- Module Name: DECODIFICADOR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DECODIFICADOR is
Port ( dir_ar : in STD_LOGIC_VECTOR (1 downto 0);
enable_ROM : out STD_LOGIC;
enable_RAM : out STD_LOGIC;
enable_LEDS : out STD_LOGIC;
enable_SWITCHES : out STD_LOGIC
);
end DECODIFICADOR;
architecture Behavioral of DECODIFICADOR is
signal temp : std_logic_vector(3 downto 0);
begin
temp <= "1000" when (dir_ar = "00") else
"0100" when (dir_ar = "01") else
"0010" when (dir_ar = "10") else
"0001";
enable_ROM <= temp(3);
enable_RAM <= temp(2);
enable_LEDS <= temp(1);
enable_SWITCHES <= temp(0);
end Behavioral;
| mit |
masaruohashi/tic-tac-toe | interface_jogo/contador_tabuleiro.vhd | 1 | 844 | -- VHDL de um contador para a impressao do tabuleiro
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_tabuleiro is
port(
clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(6 downto 0);
fim : out std_logic
);
end contador_tabuleiro;
architecture exemplo of contador_tabuleiro is
signal IQ: unsigned(6 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if zera = '1' then
IQ <= (others => '0');
elsif clock'event and clock = '1' then
if (conta = '1') then
IQ <= IQ + 1;
end if;
end if;
if IQ = 77 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
| mit |
masaruohashi/tic-tac-toe | uart/registrador_dado_recebido.vhd | 1 | 705 | -- VHDL de um Registrador de dados para a recepcao
library ieee;
use ieee.std_logic_1164.all;
entity registrador_dado_recebido is
port(
clock: in std_logic;
enable: in std_logic;
clear: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end registrador_dado_recebido;
architecture exemplo of registrador_dado_recebido is
signal IQ : std_logic_vector(11 downto 0);
begin
process (clock, enable, clear, IQ)
begin
if (clock'event and clock = '1') then
if clear = '1' then
IQ <= (others => '0');
elsif enable = '1' then
IQ <= entrada;
end if;
end if;
saida <= IQ;
end process;
end exemplo;
| mit |
JavierRizzoA/Sacagawea | sources/RAM.vhd | 1 | 1054 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM is
port (
clk : in std_logic;
write_read : in std_logic; -- write = 1 read = 0
ram_enable : in std_logic;
direccion : in std_logic_vector(9 downto 0);
ram_datos_escritura : out std_logic_vector(7 downto 0);
ram_datos_lectura : in std_logic_vector(7 downto 0)
);
end RAM;
architecture syn of RAM is
type ram_type is array (0 to 1023) of std_logic_vector (7 downto 0);
signal RAM: ram_type;
attribute ram_style : string;
attribute ram_style of RAM : signal is "block";
begin
process (clk)
begin
if clk'event and clk = '1' then
if ram_enable = '1' then
if write_read = '1' then
RAM(conv_integer(direccion)) <= ram_datos_lectura;
else
ram_datos_escritura <= RAM(conv_integer(direccion)) ;
end if;
else
ram_datos_escritura <= "ZZZZZZZZ";
end if;
end if;
end process;
end syn;
| mit |
masaruohashi/tic-tac-toe | uart/gerador_tick.vhd | 1 | 737 | -- gerador_tick.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gerador_tick is
generic(
M: integer := 454545 -- para transmissao de 110 bauds
);
port(
clock, reset: in std_logic;
tick: out std_logic
);
end gerador_tick;
architecture arch of gerador_tick is
signal contagem, prox_contagem: integer;
begin
process(clock,reset)
begin
if (reset='1') then
contagem <= 0;
elsif (clock'event and clock='1') then
contagem <= prox_contagem;
end if;
end process;
-- logica de proximo estado
prox_contagem <= 0 when contagem=(M-1) else contagem + 1;
-- logica de saida
tick <= '1' when contagem=(M-1) else '0';
end arch;
| mit |
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