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egk696/InterNoC | ip_repo/axi_i2c_master_1.0/hdl/axi_i2c_master_v1_0.vhd | 1 | 3723 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_i2c_master_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_i2c_master_v1_0;
architecture arch_imp of axi_i2c_master_v1_0 is
-- component declaration
component axi_i2c_master_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_i2c_master_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_i2c_master_v1_0_S00_AXI_inst : axi_i2c_master_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_rsftpipe32_sv.vhd | 20 | 4318 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE32.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftpipe32;
ARCHITECTURE rtl OF hcc_rsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k+16) AND shiftff);
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(32) AND shiftff);
END GENERATE;
levthr(32) <= levtwoff(32);
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_rsftpipe32_sv.vhd | 20 | 4318 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE32.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftpipe32;
ARCHITECTURE rtl OF hcc_rsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k+16) AND shiftff);
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(32) AND shiftff);
END GENERATE;
levthr(32) <= levtwoff(32);
outbus <= levthr;
END rtl;
| mit |
dtysky/LD3320_FPGA_CONTROLLER | VOICE_CLOCK.vhd | 1 | 239 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity VOICE_CLOCK is
port(inclk0:in std_logic;
c0,c1:out std_logic);
end entity;
architecture clkx of VOICE_CLOCK is
begin
c0<=inclk0;
c1<=not inclk0;
end clkx;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/dp_pos.vhd | 10 | 5994 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION MULTIPLIER - CORE LEVEL ***
--*** ***
--*** DP_POS.VHD ***
--*** ***
--*** Function: Local Count Leading Zeroes ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_pos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END dp_pos;
ARCHITECTURE rtl of dp_pos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_ln_core.vhd | 10 | 16472 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(e) - CORE ***
--*** ***
--*** FP_LN_CORE.VHD ***
--*** ***
--*** Function: Single Precision LOG (LN) Core ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 19 ***
--***************************************************
ENTITY fp_ln_core IS
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_ln_core;
ARCHITECTURE rtl OF fp_ln_core IS
signal zerovec : STD_LOGIC_VECTOR (32 DOWNTO 1);
-- input
signal aamanff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal aaexpff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaexppos, aaexpneg : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal aaexpabs, aaexpabsff : STD_LOGIC_VECTOR (7 DOWNTO 1);
-- range reduction
signal lutpowaddff : STD_LOGIC_VECTOR (7 DOWNTO 1);
signal lutoneaddff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lutpowmanff, lutonemanff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal lutpowexpff, lutoneexpff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lutoneinvff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lutpowmannode, lutonemannode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal lutpowexpnode, lutoneexpnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lutoneinvnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal aanum, aanumdel : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mulonenode : STD_LOGIC_VECTOR (35 DOWNTO 1);
signal mulonenormff : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- series
signal squared : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal cubed : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal scaled : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal onethird : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulonedel : STD_LOGIC_VECTOR (26 DOWNTO 1);
signal oneterm, twoterm, thrterm : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal seriesoneff, seriesonedelff, seriestwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal numtwo : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exptwo : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- addition
signal zeroone, zeropow : STD_LOGIC;
signal numberone, numberonedel : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal numpow, numone : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal numpowsigned : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exppow, expone : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numpowone, numpowonedel : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exppowone, exppowonedel : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numsum : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal numsumabs : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal expsum : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal ccmannode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal ccexpnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (18 DOWNTO 1);
component fp_lnlutpow
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
end component;
component fp_lnlut8
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_lnadd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
bbman : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
end component;
component fp_lnnorm
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inman : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
inexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
outman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
outexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
zero : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 32 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*******************
--*** INPUT BLOCK ***
--*******************
ppin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
aamanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
aaexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 7 LOOP
aaexpabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aaman; -- level 1
aaexpff <= aaexp; -- level 1
aaexpabsff <= aaexpabs; -- level 2
END IF;
END IF;
END PROCESS;
aaexppos <= ('0' & aaexpff) - "001111111";
aaexpneg <= "001111111" - ('0' & aaexpff);
gaba: FOR k IN 1 TO 7 GENERATE
aaexpabs(k) <= (aaexppos(k) AND NOT(aaexppos(9))) OR (aaexpneg(k) AND aaexppos(9));
END GENERATE;
--******************************************
--*** RANGE REDUCTION THROUGH LUT SERIES ***
--******************************************
plut: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 7 LOOP
lutpowaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
lutoneaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
lutpowmanff(k) <= '0';
lutonemanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
lutpowexpff(k) <= '0';
lutoneexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
lutoneinvff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lutpowaddff <= aaexpabsff; -- level 3
lutoneaddff <= aamanff(23 DOWNTO 16); -- level 2
lutpowmanff <= lutpowmannode; -- level 4
lutpowexpff <= lutpowexpnode; -- level 4
lutoneinvff <= lutoneinvnode; -- level 3
lutonemanff <= lutonemannode; -- level 3
lutoneexpff <= lutoneexpnode; -- level 3
END IF;
END IF;
END PROCESS;
lutpow: fp_lnlutpow
PORT MAP (add=>lutpowaddff,
logman=>lutpowmannode,logexp=>lutpowexpnode);
lutone: fp_lnlut8
PORT MAP (add=>lutoneaddff,
inv=>lutoneinvnode,logman=>lutonemannode,logexp=>lutoneexpnode);
aanum <= '1' & aamanff;
-- level 1 in, level 3 out
delone: fp_del
GENERIC MAP (width=>24,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanum,cc=>aanumdel);
--mulone <= aanum * invone; -- 24*11 = 35
-- level 3 in, level 6 out
mulone: fp_fxmul
GENERIC MAP (widthaa=>24,widthbb=>11,widthcc=>35,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>aanumdel,databb=>lutoneinvff,
result=>mulonenode);
pmna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 34 LOOP
mulonenormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- normalize in case input is 1.000000 and inv is 0.5
-- level 7
FOR k IN 1 TO 34 LOOP
mulonenormff(k) <= (mulonenode(k+1) AND mulonenode(35)) OR
(mulonenode(k) AND NOT(mulonenode(35)));
END LOOP;
END IF;
END IF;
END PROCESS;
--***********************************************************
--*** taylor series expansion of subrange (15 bits) ***
--*** x - x*x/2 ***
--*** 7 leading bits, so x*x 7 bits down, +1 bit for 1/2 ***
--***********************************************************
--square <= mulonenorm(25 DOWNTO 8) * mulonenorm(25 DOWNTO 8);
--cubed <= square(36 DOWNTO 19) * mulonenorm(25 DOWNTO 8);
--cubedscale <= cubed(36 DOWNTO 19) * onethird;
onethird <= "010101010101010101";
-- level 7 in, level 9 out
multwo: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulonenormff(26 DOWNTO 9),databb=>mulonenormff(26 DOWNTO 9),
result=>squared);
-- level 7 in, level 9 out
multhr: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulonenormff(26 DOWNTO 9),databb=>onethird,
result=>scaled);
-- level 9 in, level 11 out
mulfor: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>squared(36 DOWNTO 19),databb=>scaled(36 DOWNTO 19),
result=>cubed);
oneterm <= mulonenormff(26 DOWNTO 1) & zerovec(6 DOWNTO 1);
twoterm <= zerovec(7 DOWNTO 1) & squared(36 DOWNTO 12);
thrterm <= zerovec(14 DOWNTO 1) & cubed(36 DOWNTO 19);
--numtwo <= '0' & ((mulonenorm(25 DOWNTO 1) & zerovec(6 DOWNTO 1)) -
-- (zerovec(9 DOWNTO 1) & square(36 DOWNTO 15)) +
-- (zerovec(16 DOWNTO 1) & cubedscale(36 DOWNTO 22)));
-- level 7 in, level 9 out
deltwo: fp_del
GENERIC MAP (width=>26,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulonenormff(26 DOWNTO 1),cc=>mulonedel);
ptay: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
seriesoneff(k) <= '0';
seriesonedelff(k) <= '0';
seriestwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- level 10
seriesoneff <= (mulonedel & zerovec(6 DOWNTO 1)) -
(zerovec(8 DOWNTO 1) & squared(36 DOWNTO 13));
seriesonedelff <= seriesoneff;
-- level 12
seriestwoff <= seriesonedelff + (zerovec(14 DOWNTO 1) & cubed(36 DOWNTO 19));
END IF;
END IF;
END PROCESS;
numtwo <= '0' & seriestwoff(32 DOWNTO 2);
-- exponent for subrange 127-8 = 119
exptwo <= "01110111";
--***********************************************************
--*** add logarithm values ***
--***********************************************************
zeroone <= lutoneexpff(8) OR lutoneexpff(7) OR lutoneexpff(6) OR lutoneexpff(5) OR
lutoneexpff(4) OR lutoneexpff(3) OR lutoneexpff(2) OR lutoneexpff(1);
numberone <= zeroone & lutonemanff & lutoneexpff;
-- level 3 in, level 4 out
delthr: fp_del
GENERIC MAP (width=>32,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numberone,cc=>numberonedel);
numone <= '0' & numberonedel(32 DOWNTO 9) & zerovec(7 DOWNTO 1);
expone <= numberonedel(8 DOWNTO 1);
zeropow <= lutpowexpff(8) OR lutpowexpff(7) OR lutpowexpff(6) OR lutpowexpff(5) OR
lutpowexpff(4) OR lutpowexpff(3) OR lutpowexpff(2) OR lutpowexpff(1);
numpow <= '0' & zeropow & lutpowmanff & zerovec(7 DOWNTO 1);
exppow <= lutpowexpff;
gmpz: FOR k IN 1 TO 32 GENERATE
numpowsigned(k) <= numpow(k) XOR signff(3);
END GENERATE;
-- level 4 in, level 8 out
addone: fp_lnadd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>numpowsigned,aaexp=>exppow,
bbman=>numone,bbexp=>expone,
ccman=>numpowone,ccexp=>exppowone);
-- level 8 in, level 12 out
delfor: fp_del
GENERIC MAP (width=>32,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numpowone,cc=>numpowonedel);
delfiv: fp_del
GENERIC MAP (width=>8,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exppowone,cc=>exppowonedel);
-- level 12 in, level 16 out
addtwo: fp_lnadd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>numpowonedel,aaexp=>exppowonedel,
bbman=>numtwo,bbexp=>exptwo,
ccman=>numsum,ccexp=>expsum);
gmsa: FOR k IN 1 TO 32 GENERATE
numsumabs(k) <= numsum(k) XOR signff(15);
END GENERATE;
-- level 16 in, level 19 out
norm: fp_lnnorm
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inman=>numsumabs,inexp=>expsum,
outman=>ccmannode,outexp=>ccexpnode,
zero=>zeroout);
psgna: PROCESS (sysclk)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signff(1) <= aaexppos(9);
FOR k IN 2 TO 18 LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END PROCESS;
ccsgn <= signff(18);
ccman <= ccmannode;
ccexp <= ccexpnode;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_castltoy.vhd | 10 | 2035 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOY.VHD ***
--*** ***
--*** Function: Cast Long to Internal Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltoy IS
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castltoy;
ARCHITECTURE rtl OF hcc_castltoy IS
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(77 DOWNTO 73) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(77 DOWNTO 73) <= "00000";
END GENERATE;
cc(72 DOWNTO 41) <= aa;
gza: FOR k IN 14 TO 40 GENERATE
cc(k) <= '0';
END GENERATE;
cc(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
ccsat <= '0';
cczip <= '0';
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_invsqr_trig1.vhd | 10 | 4091 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-- for 36 bit mantissa for trig library
--***************************************************
--*** Notes: Latency = 17 ***
--***************************************************
ENTITY fp_invsqr_trig1 IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_invsqr_trig1;
ARCHITECTURE rtl OF fp_invsqr_trig1 IS
constant manwidth : positive := 36;
constant expwidth : positive := 8;
constant coredepth : positive := 17;
type expfftype IS ARRAY (coredepth DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal oddexponent : STD_LOGIC;
signal invroot : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
component fp_invsqr_core IS
GENERIC (synthesize : integer := 1); -- 0/1
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
expff(1)(expwidth DOWNTO 1) <= exponentin;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) - offset;
expff(3)(expwidth DOWNTO 1) <= expff(2)(expwidth) & expff(2)(expwidth DOWNTO 2);
expff(4)(expwidth DOWNTO 1) <= offset - expff(3)(expwidth DOWNTO 1);
expff(5)(expwidth DOWNTO 1) <= expff(4)(expwidth DOWNTO 1) - 1;
FOR k IN 6 TO coredepth LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
radicand <= mantissain; -- already with leading '1'
-- sub 127, so 127 (odd) = 2^0 => even
oddexponent <= NOT(exponentin(1));
-- does not require rounding, output of core rounded already, LSB always 0
isqr: fp_invsqr_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand,odd=>oddexponent,
invroot=>invroot);
--***************
--*** OUTPUTS ***
--***************
exponentout <= expff(coredepth)(expwidth DOWNTO 1);
mantissaout <= invroot;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/CosPiDPStratixVf400_safe_path.vhd | 10 | 437 | -- safe_path for CosPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosPiDPStratixVf400_safe_path;
PACKAGE body CosPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosPiDPStratixVf400_safe_path;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/dp_inv.vhd | 10 | 12634 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** DP_INV.VHD ***
--*** ***
--*** Function: IEEE754 DP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 12/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 20 + 2*DoubleSpeed + ***
--*** RoundConvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 20 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 22 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 21 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 24 ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 19 + DoubleSpeed + ***
--*** Roundconvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 19 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 20 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 20 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 22 ***
--*** ***
--***************************************************
ENTITY dp_inv IS
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END dp_inv;
ARCHITECTURE rtl OF dp_inv IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
-- SII Latency = 19 + 2*speed
-- SIII Latency = 18 + speed
constant coredepth : positive := 19+2*doublespeed - device*(1+doublespeed);
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component dp_inv_core
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
end component;
component dp_divnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component dp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component dp_divrndpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- quotient always <1, so decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & '0';
invcore: dp_inv_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
-- quotient always <1
--************************
--*** ROUND AND OUTPUT ***
--************************
-- in depth coredepth+1 (core + normalff)
gra: IF (roundconvert = 0) GENERATE
norndout: dp_divnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END GENERATE;
grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
rndout: dp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END GENERATE;
grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
rndoutpipe: dp_divrndpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/dp_exprnd.vhd | 10 | 6808 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPRND.VHD ***
--*** ***
--*** Function: DP Exponent Output Block - ***
--*** Rounded ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_exprnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END dp_exprnd;
ARCHITECTURE rtl OF dp_exprnd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal rangeerrorff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
rangeerrorff <= '0';
overflowff <= "00";
underflowff <= "00";
manoverflowbitff <= '0';
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
rangeerrorff <= rangeerror;
overflowff(1) <= overflownode;
overflowff(2) <= overflowff(1);
underflowff(1) <= underflownode;
underflowff(2) <= underflowff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1));
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaexp(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- '1' if infinity
-- zero if exponent == 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanff(1) OR infinitygen(expwidth+1) OR rangeerrorff;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= overflowff(2);
underflowout <= underflowff(2);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/dp_fxsub.vhd | 10 | 2876 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_div_lut1.vhd | 10 | 35988 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT1.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END fp_div_lut1;
ARCHITECTURE rtl OF fp_div_lut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(2044,11);
WHEN "000000001" => data <= conv_std_logic_vector(2036,11);
WHEN "000000010" => data <= conv_std_logic_vector(2028,11);
WHEN "000000011" => data <= conv_std_logic_vector(2020,11);
WHEN "000000100" => data <= conv_std_logic_vector(2012,11);
WHEN "000000101" => data <= conv_std_logic_vector(2005,11);
WHEN "000000110" => data <= conv_std_logic_vector(1997,11);
WHEN "000000111" => data <= conv_std_logic_vector(1989,11);
WHEN "000001000" => data <= conv_std_logic_vector(1982,11);
WHEN "000001001" => data <= conv_std_logic_vector(1974,11);
WHEN "000001010" => data <= conv_std_logic_vector(1967,11);
WHEN "000001011" => data <= conv_std_logic_vector(1959,11);
WHEN "000001100" => data <= conv_std_logic_vector(1952,11);
WHEN "000001101" => data <= conv_std_logic_vector(1944,11);
WHEN "000001110" => data <= conv_std_logic_vector(1937,11);
WHEN "000001111" => data <= conv_std_logic_vector(1929,11);
WHEN "000010000" => data <= conv_std_logic_vector(1922,11);
WHEN "000010001" => data <= conv_std_logic_vector(1915,11);
WHEN "000010010" => data <= conv_std_logic_vector(1908,11);
WHEN "000010011" => data <= conv_std_logic_vector(1900,11);
WHEN "000010100" => data <= conv_std_logic_vector(1893,11);
WHEN "000010101" => data <= conv_std_logic_vector(1886,11);
WHEN "000010110" => data <= conv_std_logic_vector(1879,11);
WHEN "000010111" => data <= conv_std_logic_vector(1872,11);
WHEN "000011000" => data <= conv_std_logic_vector(1865,11);
WHEN "000011001" => data <= conv_std_logic_vector(1858,11);
WHEN "000011010" => data <= conv_std_logic_vector(1851,11);
WHEN "000011011" => data <= conv_std_logic_vector(1845,11);
WHEN "000011100" => data <= conv_std_logic_vector(1838,11);
WHEN "000011101" => data <= conv_std_logic_vector(1831,11);
WHEN "000011110" => data <= conv_std_logic_vector(1824,11);
WHEN "000011111" => data <= conv_std_logic_vector(1817,11);
WHEN "000100000" => data <= conv_std_logic_vector(1811,11);
WHEN "000100001" => data <= conv_std_logic_vector(1804,11);
WHEN "000100010" => data <= conv_std_logic_vector(1798,11);
WHEN "000100011" => data <= conv_std_logic_vector(1791,11);
WHEN "000100100" => data <= conv_std_logic_vector(1785,11);
WHEN "000100101" => data <= conv_std_logic_vector(1778,11);
WHEN "000100110" => data <= conv_std_logic_vector(1772,11);
WHEN "000100111" => data <= conv_std_logic_vector(1765,11);
WHEN "000101000" => data <= conv_std_logic_vector(1759,11);
WHEN "000101001" => data <= conv_std_logic_vector(1752,11);
WHEN "000101010" => data <= conv_std_logic_vector(1746,11);
WHEN "000101011" => data <= conv_std_logic_vector(1740,11);
WHEN "000101100" => data <= conv_std_logic_vector(1734,11);
WHEN "000101101" => data <= conv_std_logic_vector(1727,11);
WHEN "000101110" => data <= conv_std_logic_vector(1721,11);
WHEN "000101111" => data <= conv_std_logic_vector(1715,11);
WHEN "000110000" => data <= conv_std_logic_vector(1709,11);
WHEN "000110001" => data <= conv_std_logic_vector(1703,11);
WHEN "000110010" => data <= conv_std_logic_vector(1697,11);
WHEN "000110011" => data <= conv_std_logic_vector(1691,11);
WHEN "000110100" => data <= conv_std_logic_vector(1685,11);
WHEN "000110101" => data <= conv_std_logic_vector(1679,11);
WHEN "000110110" => data <= conv_std_logic_vector(1673,11);
WHEN "000110111" => data <= conv_std_logic_vector(1667,11);
WHEN "000111000" => data <= conv_std_logic_vector(1661,11);
WHEN "000111001" => data <= conv_std_logic_vector(1655,11);
WHEN "000111010" => data <= conv_std_logic_vector(1650,11);
WHEN "000111011" => data <= conv_std_logic_vector(1644,11);
WHEN "000111100" => data <= conv_std_logic_vector(1638,11);
WHEN "000111101" => data <= conv_std_logic_vector(1632,11);
WHEN "000111110" => data <= conv_std_logic_vector(1627,11);
WHEN "000111111" => data <= conv_std_logic_vector(1621,11);
WHEN "001000000" => data <= conv_std_logic_vector(1615,11);
WHEN "001000001" => data <= conv_std_logic_vector(1610,11);
WHEN "001000010" => data <= conv_std_logic_vector(1604,11);
WHEN "001000011" => data <= conv_std_logic_vector(1599,11);
WHEN "001000100" => data <= conv_std_logic_vector(1593,11);
WHEN "001000101" => data <= conv_std_logic_vector(1588,11);
WHEN "001000110" => data <= conv_std_logic_vector(1582,11);
WHEN "001000111" => data <= conv_std_logic_vector(1577,11);
WHEN "001001000" => data <= conv_std_logic_vector(1571,11);
WHEN "001001001" => data <= conv_std_logic_vector(1566,11);
WHEN "001001010" => data <= conv_std_logic_vector(1561,11);
WHEN "001001011" => data <= conv_std_logic_vector(1555,11);
WHEN "001001100" => data <= conv_std_logic_vector(1550,11);
WHEN "001001101" => data <= conv_std_logic_vector(1545,11);
WHEN "001001110" => data <= conv_std_logic_vector(1540,11);
WHEN "001001111" => data <= conv_std_logic_vector(1534,11);
WHEN "001010000" => data <= conv_std_logic_vector(1529,11);
WHEN "001010001" => data <= conv_std_logic_vector(1524,11);
WHEN "001010010" => data <= conv_std_logic_vector(1519,11);
WHEN "001010011" => data <= conv_std_logic_vector(1514,11);
WHEN "001010100" => data <= conv_std_logic_vector(1509,11);
WHEN "001010101" => data <= conv_std_logic_vector(1504,11);
WHEN "001010110" => data <= conv_std_logic_vector(1499,11);
WHEN "001010111" => data <= conv_std_logic_vector(1494,11);
WHEN "001011000" => data <= conv_std_logic_vector(1489,11);
WHEN "001011001" => data <= conv_std_logic_vector(1484,11);
WHEN "001011010" => data <= conv_std_logic_vector(1479,11);
WHEN "001011011" => data <= conv_std_logic_vector(1474,11);
WHEN "001011100" => data <= conv_std_logic_vector(1469,11);
WHEN "001011101" => data <= conv_std_logic_vector(1464,11);
WHEN "001011110" => data <= conv_std_logic_vector(1460,11);
WHEN "001011111" => data <= conv_std_logic_vector(1455,11);
WHEN "001100000" => data <= conv_std_logic_vector(1450,11);
WHEN "001100001" => data <= conv_std_logic_vector(1445,11);
WHEN "001100010" => data <= conv_std_logic_vector(1440,11);
WHEN "001100011" => data <= conv_std_logic_vector(1436,11);
WHEN "001100100" => data <= conv_std_logic_vector(1431,11);
WHEN "001100101" => data <= conv_std_logic_vector(1426,11);
WHEN "001100110" => data <= conv_std_logic_vector(1422,11);
WHEN "001100111" => data <= conv_std_logic_vector(1417,11);
WHEN "001101000" => data <= conv_std_logic_vector(1413,11);
WHEN "001101001" => data <= conv_std_logic_vector(1408,11);
WHEN "001101010" => data <= conv_std_logic_vector(1403,11);
WHEN "001101011" => data <= conv_std_logic_vector(1399,11);
WHEN "001101100" => data <= conv_std_logic_vector(1394,11);
WHEN "001101101" => data <= conv_std_logic_vector(1390,11);
WHEN "001101110" => data <= conv_std_logic_vector(1385,11);
WHEN "001101111" => data <= conv_std_logic_vector(1381,11);
WHEN "001110000" => data <= conv_std_logic_vector(1377,11);
WHEN "001110001" => data <= conv_std_logic_vector(1372,11);
WHEN "001110010" => data <= conv_std_logic_vector(1368,11);
WHEN "001110011" => data <= conv_std_logic_vector(1363,11);
WHEN "001110100" => data <= conv_std_logic_vector(1359,11);
WHEN "001110101" => data <= conv_std_logic_vector(1355,11);
WHEN "001110110" => data <= conv_std_logic_vector(1351,11);
WHEN "001110111" => data <= conv_std_logic_vector(1346,11);
WHEN "001111000" => data <= conv_std_logic_vector(1342,11);
WHEN "001111001" => data <= conv_std_logic_vector(1338,11);
WHEN "001111010" => data <= conv_std_logic_vector(1334,11);
WHEN "001111011" => data <= conv_std_logic_vector(1329,11);
WHEN "001111100" => data <= conv_std_logic_vector(1325,11);
WHEN "001111101" => data <= conv_std_logic_vector(1321,11);
WHEN "001111110" => data <= conv_std_logic_vector(1317,11);
WHEN "001111111" => data <= conv_std_logic_vector(1313,11);
WHEN "010000000" => data <= conv_std_logic_vector(1309,11);
WHEN "010000001" => data <= conv_std_logic_vector(1305,11);
WHEN "010000010" => data <= conv_std_logic_vector(1301,11);
WHEN "010000011" => data <= conv_std_logic_vector(1297,11);
WHEN "010000100" => data <= conv_std_logic_vector(1292,11);
WHEN "010000101" => data <= conv_std_logic_vector(1288,11);
WHEN "010000110" => data <= conv_std_logic_vector(1284,11);
WHEN "010000111" => data <= conv_std_logic_vector(1281,11);
WHEN "010001000" => data <= conv_std_logic_vector(1277,11);
WHEN "010001001" => data <= conv_std_logic_vector(1273,11);
WHEN "010001010" => data <= conv_std_logic_vector(1269,11);
WHEN "010001011" => data <= conv_std_logic_vector(1265,11);
WHEN "010001100" => data <= conv_std_logic_vector(1261,11);
WHEN "010001101" => data <= conv_std_logic_vector(1257,11);
WHEN "010001110" => data <= conv_std_logic_vector(1253,11);
WHEN "010001111" => data <= conv_std_logic_vector(1249,11);
WHEN "010010000" => data <= conv_std_logic_vector(1246,11);
WHEN "010010001" => data <= conv_std_logic_vector(1242,11);
WHEN "010010010" => data <= conv_std_logic_vector(1238,11);
WHEN "010010011" => data <= conv_std_logic_vector(1234,11);
WHEN "010010100" => data <= conv_std_logic_vector(1231,11);
WHEN "010010101" => data <= conv_std_logic_vector(1227,11);
WHEN "010010110" => data <= conv_std_logic_vector(1223,11);
WHEN "010010111" => data <= conv_std_logic_vector(1220,11);
WHEN "010011000" => data <= conv_std_logic_vector(1216,11);
WHEN "010011001" => data <= conv_std_logic_vector(1212,11);
WHEN "010011010" => data <= conv_std_logic_vector(1209,11);
WHEN "010011011" => data <= conv_std_logic_vector(1205,11);
WHEN "010011100" => data <= conv_std_logic_vector(1201,11);
WHEN "010011101" => data <= conv_std_logic_vector(1198,11);
WHEN "010011110" => data <= conv_std_logic_vector(1194,11);
WHEN "010011111" => data <= conv_std_logic_vector(1191,11);
WHEN "010100000" => data <= conv_std_logic_vector(1187,11);
WHEN "010100001" => data <= conv_std_logic_vector(1184,11);
WHEN "010100010" => data <= conv_std_logic_vector(1180,11);
WHEN "010100011" => data <= conv_std_logic_vector(1177,11);
WHEN "010100100" => data <= conv_std_logic_vector(1173,11);
WHEN "010100101" => data <= conv_std_logic_vector(1170,11);
WHEN "010100110" => data <= conv_std_logic_vector(1166,11);
WHEN "010100111" => data <= conv_std_logic_vector(1163,11);
WHEN "010101000" => data <= conv_std_logic_vector(1159,11);
WHEN "010101001" => data <= conv_std_logic_vector(1156,11);
WHEN "010101010" => data <= conv_std_logic_vector(1153,11);
WHEN "010101011" => data <= conv_std_logic_vector(1149,11);
WHEN "010101100" => data <= conv_std_logic_vector(1146,11);
WHEN "010101101" => data <= conv_std_logic_vector(1142,11);
WHEN "010101110" => data <= conv_std_logic_vector(1139,11);
WHEN "010101111" => data <= conv_std_logic_vector(1136,11);
WHEN "010110000" => data <= conv_std_logic_vector(1133,11);
WHEN "010110001" => data <= conv_std_logic_vector(1129,11);
WHEN "010110010" => data <= conv_std_logic_vector(1126,11);
WHEN "010110011" => data <= conv_std_logic_vector(1123,11);
WHEN "010110100" => data <= conv_std_logic_vector(1120,11);
WHEN "010110101" => data <= conv_std_logic_vector(1116,11);
WHEN "010110110" => data <= conv_std_logic_vector(1113,11);
WHEN "010110111" => data <= conv_std_logic_vector(1110,11);
WHEN "010111000" => data <= conv_std_logic_vector(1107,11);
WHEN "010111001" => data <= conv_std_logic_vector(1104,11);
WHEN "010111010" => data <= conv_std_logic_vector(1100,11);
WHEN "010111011" => data <= conv_std_logic_vector(1097,11);
WHEN "010111100" => data <= conv_std_logic_vector(1094,11);
WHEN "010111101" => data <= conv_std_logic_vector(1091,11);
WHEN "010111110" => data <= conv_std_logic_vector(1088,11);
WHEN "010111111" => data <= conv_std_logic_vector(1085,11);
WHEN "011000000" => data <= conv_std_logic_vector(1082,11);
WHEN "011000001" => data <= conv_std_logic_vector(1079,11);
WHEN "011000010" => data <= conv_std_logic_vector(1076,11);
WHEN "011000011" => data <= conv_std_logic_vector(1073,11);
WHEN "011000100" => data <= conv_std_logic_vector(1070,11);
WHEN "011000101" => data <= conv_std_logic_vector(1067,11);
WHEN "011000110" => data <= conv_std_logic_vector(1064,11);
WHEN "011000111" => data <= conv_std_logic_vector(1061,11);
WHEN "011001000" => data <= conv_std_logic_vector(1058,11);
WHEN "011001001" => data <= conv_std_logic_vector(1055,11);
WHEN "011001010" => data <= conv_std_logic_vector(1052,11);
WHEN "011001011" => data <= conv_std_logic_vector(1049,11);
WHEN "011001100" => data <= conv_std_logic_vector(1046,11);
WHEN "011001101" => data <= conv_std_logic_vector(1043,11);
WHEN "011001110" => data <= conv_std_logic_vector(1040,11);
WHEN "011001111" => data <= conv_std_logic_vector(1037,11);
WHEN "011010000" => data <= conv_std_logic_vector(1034,11);
WHEN "011010001" => data <= conv_std_logic_vector(1031,11);
WHEN "011010010" => data <= conv_std_logic_vector(1028,11);
WHEN "011010011" => data <= conv_std_logic_vector(1026,11);
WHEN "011010100" => data <= conv_std_logic_vector(1023,11);
WHEN "011010101" => data <= conv_std_logic_vector(1020,11);
WHEN "011010110" => data <= conv_std_logic_vector(1017,11);
WHEN "011010111" => data <= conv_std_logic_vector(1014,11);
WHEN "011011000" => data <= conv_std_logic_vector(1012,11);
WHEN "011011001" => data <= conv_std_logic_vector(1009,11);
WHEN "011011010" => data <= conv_std_logic_vector(1006,11);
WHEN "011011011" => data <= conv_std_logic_vector(1003,11);
WHEN "011011100" => data <= conv_std_logic_vector(1001,11);
WHEN "011011101" => data <= conv_std_logic_vector(998,11);
WHEN "011011110" => data <= conv_std_logic_vector(995,11);
WHEN "011011111" => data <= conv_std_logic_vector(992,11);
WHEN "011100000" => data <= conv_std_logic_vector(990,11);
WHEN "011100001" => data <= conv_std_logic_vector(987,11);
WHEN "011100010" => data <= conv_std_logic_vector(984,11);
WHEN "011100011" => data <= conv_std_logic_vector(982,11);
WHEN "011100100" => data <= conv_std_logic_vector(979,11);
WHEN "011100101" => data <= conv_std_logic_vector(976,11);
WHEN "011100110" => data <= conv_std_logic_vector(974,11);
WHEN "011100111" => data <= conv_std_logic_vector(971,11);
WHEN "011101000" => data <= conv_std_logic_vector(969,11);
WHEN "011101001" => data <= conv_std_logic_vector(966,11);
WHEN "011101010" => data <= conv_std_logic_vector(963,11);
WHEN "011101011" => data <= conv_std_logic_vector(961,11);
WHEN "011101100" => data <= conv_std_logic_vector(958,11);
WHEN "011101101" => data <= conv_std_logic_vector(956,11);
WHEN "011101110" => data <= conv_std_logic_vector(953,11);
WHEN "011101111" => data <= conv_std_logic_vector(951,11);
WHEN "011110000" => data <= conv_std_logic_vector(948,11);
WHEN "011110001" => data <= conv_std_logic_vector(946,11);
WHEN "011110010" => data <= conv_std_logic_vector(943,11);
WHEN "011110011" => data <= conv_std_logic_vector(941,11);
WHEN "011110100" => data <= conv_std_logic_vector(938,11);
WHEN "011110101" => data <= conv_std_logic_vector(936,11);
WHEN "011110110" => data <= conv_std_logic_vector(933,11);
WHEN "011110111" => data <= conv_std_logic_vector(931,11);
WHEN "011111000" => data <= conv_std_logic_vector(928,11);
WHEN "011111001" => data <= conv_std_logic_vector(926,11);
WHEN "011111010" => data <= conv_std_logic_vector(923,11);
WHEN "011111011" => data <= conv_std_logic_vector(921,11);
WHEN "011111100" => data <= conv_std_logic_vector(919,11);
WHEN "011111101" => data <= conv_std_logic_vector(916,11);
WHEN "011111110" => data <= conv_std_logic_vector(914,11);
WHEN "011111111" => data <= conv_std_logic_vector(911,11);
WHEN "100000000" => data <= conv_std_logic_vector(909,11);
WHEN "100000001" => data <= conv_std_logic_vector(907,11);
WHEN "100000010" => data <= conv_std_logic_vector(904,11);
WHEN "100000011" => data <= conv_std_logic_vector(902,11);
WHEN "100000100" => data <= conv_std_logic_vector(900,11);
WHEN "100000101" => data <= conv_std_logic_vector(897,11);
WHEN "100000110" => data <= conv_std_logic_vector(895,11);
WHEN "100000111" => data <= conv_std_logic_vector(893,11);
WHEN "100001000" => data <= conv_std_logic_vector(890,11);
WHEN "100001001" => data <= conv_std_logic_vector(888,11);
WHEN "100001010" => data <= conv_std_logic_vector(886,11);
WHEN "100001011" => data <= conv_std_logic_vector(884,11);
WHEN "100001100" => data <= conv_std_logic_vector(881,11);
WHEN "100001101" => data <= conv_std_logic_vector(879,11);
WHEN "100001110" => data <= conv_std_logic_vector(877,11);
WHEN "100001111" => data <= conv_std_logic_vector(875,11);
WHEN "100010000" => data <= conv_std_logic_vector(872,11);
WHEN "100010001" => data <= conv_std_logic_vector(870,11);
WHEN "100010010" => data <= conv_std_logic_vector(868,11);
WHEN "100010011" => data <= conv_std_logic_vector(866,11);
WHEN "100010100" => data <= conv_std_logic_vector(864,11);
WHEN "100010101" => data <= conv_std_logic_vector(861,11);
WHEN "100010110" => data <= conv_std_logic_vector(859,11);
WHEN "100010111" => data <= conv_std_logic_vector(857,11);
WHEN "100011000" => data <= conv_std_logic_vector(855,11);
WHEN "100011001" => data <= conv_std_logic_vector(853,11);
WHEN "100011010" => data <= conv_std_logic_vector(851,11);
WHEN "100011011" => data <= conv_std_logic_vector(848,11);
WHEN "100011100" => data <= conv_std_logic_vector(846,11);
WHEN "100011101" => data <= conv_std_logic_vector(844,11);
WHEN "100011110" => data <= conv_std_logic_vector(842,11);
WHEN "100011111" => data <= conv_std_logic_vector(840,11);
WHEN "100100000" => data <= conv_std_logic_vector(838,11);
WHEN "100100001" => data <= conv_std_logic_vector(836,11);
WHEN "100100010" => data <= conv_std_logic_vector(834,11);
WHEN "100100011" => data <= conv_std_logic_vector(832,11);
WHEN "100100100" => data <= conv_std_logic_vector(830,11);
WHEN "100100101" => data <= conv_std_logic_vector(827,11);
WHEN "100100110" => data <= conv_std_logic_vector(825,11);
WHEN "100100111" => data <= conv_std_logic_vector(823,11);
WHEN "100101000" => data <= conv_std_logic_vector(821,11);
WHEN "100101001" => data <= conv_std_logic_vector(819,11);
WHEN "100101010" => data <= conv_std_logic_vector(817,11);
WHEN "100101011" => data <= conv_std_logic_vector(815,11);
WHEN "100101100" => data <= conv_std_logic_vector(813,11);
WHEN "100101101" => data <= conv_std_logic_vector(811,11);
WHEN "100101110" => data <= conv_std_logic_vector(809,11);
WHEN "100101111" => data <= conv_std_logic_vector(807,11);
WHEN "100110000" => data <= conv_std_logic_vector(805,11);
WHEN "100110001" => data <= conv_std_logic_vector(803,11);
WHEN "100110010" => data <= conv_std_logic_vector(801,11);
WHEN "100110011" => data <= conv_std_logic_vector(799,11);
WHEN "100110100" => data <= conv_std_logic_vector(797,11);
WHEN "100110101" => data <= conv_std_logic_vector(796,11);
WHEN "100110110" => data <= conv_std_logic_vector(794,11);
WHEN "100110111" => data <= conv_std_logic_vector(792,11);
WHEN "100111000" => data <= conv_std_logic_vector(790,11);
WHEN "100111001" => data <= conv_std_logic_vector(788,11);
WHEN "100111010" => data <= conv_std_logic_vector(786,11);
WHEN "100111011" => data <= conv_std_logic_vector(784,11);
WHEN "100111100" => data <= conv_std_logic_vector(782,11);
WHEN "100111101" => data <= conv_std_logic_vector(780,11);
WHEN "100111110" => data <= conv_std_logic_vector(778,11);
WHEN "100111111" => data <= conv_std_logic_vector(777,11);
WHEN "101000000" => data <= conv_std_logic_vector(775,11);
WHEN "101000001" => data <= conv_std_logic_vector(773,11);
WHEN "101000010" => data <= conv_std_logic_vector(771,11);
WHEN "101000011" => data <= conv_std_logic_vector(769,11);
WHEN "101000100" => data <= conv_std_logic_vector(767,11);
WHEN "101000101" => data <= conv_std_logic_vector(765,11);
WHEN "101000110" => data <= conv_std_logic_vector(764,11);
WHEN "101000111" => data <= conv_std_logic_vector(762,11);
WHEN "101001000" => data <= conv_std_logic_vector(760,11);
WHEN "101001001" => data <= conv_std_logic_vector(758,11);
WHEN "101001010" => data <= conv_std_logic_vector(756,11);
WHEN "101001011" => data <= conv_std_logic_vector(755,11);
WHEN "101001100" => data <= conv_std_logic_vector(753,11);
WHEN "101001101" => data <= conv_std_logic_vector(751,11);
WHEN "101001110" => data <= conv_std_logic_vector(749,11);
WHEN "101001111" => data <= conv_std_logic_vector(747,11);
WHEN "101010000" => data <= conv_std_logic_vector(746,11);
WHEN "101010001" => data <= conv_std_logic_vector(744,11);
WHEN "101010010" => data <= conv_std_logic_vector(742,11);
WHEN "101010011" => data <= conv_std_logic_vector(740,11);
WHEN "101010100" => data <= conv_std_logic_vector(739,11);
WHEN "101010101" => data <= conv_std_logic_vector(737,11);
WHEN "101010110" => data <= conv_std_logic_vector(735,11);
WHEN "101010111" => data <= conv_std_logic_vector(734,11);
WHEN "101011000" => data <= conv_std_logic_vector(732,11);
WHEN "101011001" => data <= conv_std_logic_vector(730,11);
WHEN "101011010" => data <= conv_std_logic_vector(728,11);
WHEN "101011011" => data <= conv_std_logic_vector(727,11);
WHEN "101011100" => data <= conv_std_logic_vector(725,11);
WHEN "101011101" => data <= conv_std_logic_vector(723,11);
WHEN "101011110" => data <= conv_std_logic_vector(722,11);
WHEN "101011111" => data <= conv_std_logic_vector(720,11);
WHEN "101100000" => data <= conv_std_logic_vector(718,11);
WHEN "101100001" => data <= conv_std_logic_vector(717,11);
WHEN "101100010" => data <= conv_std_logic_vector(715,11);
WHEN "101100011" => data <= conv_std_logic_vector(713,11);
WHEN "101100100" => data <= conv_std_logic_vector(712,11);
WHEN "101100101" => data <= conv_std_logic_vector(710,11);
WHEN "101100110" => data <= conv_std_logic_vector(708,11);
WHEN "101100111" => data <= conv_std_logic_vector(707,11);
WHEN "101101000" => data <= conv_std_logic_vector(705,11);
WHEN "101101001" => data <= conv_std_logic_vector(704,11);
WHEN "101101010" => data <= conv_std_logic_vector(702,11);
WHEN "101101011" => data <= conv_std_logic_vector(700,11);
WHEN "101101100" => data <= conv_std_logic_vector(699,11);
WHEN "101101101" => data <= conv_std_logic_vector(697,11);
WHEN "101101110" => data <= conv_std_logic_vector(696,11);
WHEN "101101111" => data <= conv_std_logic_vector(694,11);
WHEN "101110000" => data <= conv_std_logic_vector(692,11);
WHEN "101110001" => data <= conv_std_logic_vector(691,11);
WHEN "101110010" => data <= conv_std_logic_vector(689,11);
WHEN "101110011" => data <= conv_std_logic_vector(688,11);
WHEN "101110100" => data <= conv_std_logic_vector(686,11);
WHEN "101110101" => data <= conv_std_logic_vector(685,11);
WHEN "101110110" => data <= conv_std_logic_vector(683,11);
WHEN "101110111" => data <= conv_std_logic_vector(682,11);
WHEN "101111000" => data <= conv_std_logic_vector(680,11);
WHEN "101111001" => data <= conv_std_logic_vector(679,11);
WHEN "101111010" => data <= conv_std_logic_vector(677,11);
WHEN "101111011" => data <= conv_std_logic_vector(676,11);
WHEN "101111100" => data <= conv_std_logic_vector(674,11);
WHEN "101111101" => data <= conv_std_logic_vector(672,11);
WHEN "101111110" => data <= conv_std_logic_vector(671,11);
WHEN "101111111" => data <= conv_std_logic_vector(669,11);
WHEN "110000000" => data <= conv_std_logic_vector(668,11);
WHEN "110000001" => data <= conv_std_logic_vector(667,11);
WHEN "110000010" => data <= conv_std_logic_vector(665,11);
WHEN "110000011" => data <= conv_std_logic_vector(664,11);
WHEN "110000100" => data <= conv_std_logic_vector(662,11);
WHEN "110000101" => data <= conv_std_logic_vector(661,11);
WHEN "110000110" => data <= conv_std_logic_vector(659,11);
WHEN "110000111" => data <= conv_std_logic_vector(658,11);
WHEN "110001000" => data <= conv_std_logic_vector(656,11);
WHEN "110001001" => data <= conv_std_logic_vector(655,11);
WHEN "110001010" => data <= conv_std_logic_vector(653,11);
WHEN "110001011" => data <= conv_std_logic_vector(652,11);
WHEN "110001100" => data <= conv_std_logic_vector(650,11);
WHEN "110001101" => data <= conv_std_logic_vector(649,11);
WHEN "110001110" => data <= conv_std_logic_vector(648,11);
WHEN "110001111" => data <= conv_std_logic_vector(646,11);
WHEN "110010000" => data <= conv_std_logic_vector(645,11);
WHEN "110010001" => data <= conv_std_logic_vector(643,11);
WHEN "110010010" => data <= conv_std_logic_vector(642,11);
WHEN "110010011" => data <= conv_std_logic_vector(641,11);
WHEN "110010100" => data <= conv_std_logic_vector(639,11);
WHEN "110010101" => data <= conv_std_logic_vector(638,11);
WHEN "110010110" => data <= conv_std_logic_vector(636,11);
WHEN "110010111" => data <= conv_std_logic_vector(635,11);
WHEN "110011000" => data <= conv_std_logic_vector(634,11);
WHEN "110011001" => data <= conv_std_logic_vector(632,11);
WHEN "110011010" => data <= conv_std_logic_vector(631,11);
WHEN "110011011" => data <= conv_std_logic_vector(630,11);
WHEN "110011100" => data <= conv_std_logic_vector(628,11);
WHEN "110011101" => data <= conv_std_logic_vector(627,11);
WHEN "110011110" => data <= conv_std_logic_vector(625,11);
WHEN "110011111" => data <= conv_std_logic_vector(624,11);
WHEN "110100000" => data <= conv_std_logic_vector(623,11);
WHEN "110100001" => data <= conv_std_logic_vector(621,11);
WHEN "110100010" => data <= conv_std_logic_vector(620,11);
WHEN "110100011" => data <= conv_std_logic_vector(619,11);
WHEN "110100100" => data <= conv_std_logic_vector(617,11);
WHEN "110100101" => data <= conv_std_logic_vector(616,11);
WHEN "110100110" => data <= conv_std_logic_vector(615,11);
WHEN "110100111" => data <= conv_std_logic_vector(613,11);
WHEN "110101000" => data <= conv_std_logic_vector(612,11);
WHEN "110101001" => data <= conv_std_logic_vector(611,11);
WHEN "110101010" => data <= conv_std_logic_vector(610,11);
WHEN "110101011" => data <= conv_std_logic_vector(608,11);
WHEN "110101100" => data <= conv_std_logic_vector(607,11);
WHEN "110101101" => data <= conv_std_logic_vector(606,11);
WHEN "110101110" => data <= conv_std_logic_vector(604,11);
WHEN "110101111" => data <= conv_std_logic_vector(603,11);
WHEN "110110000" => data <= conv_std_logic_vector(602,11);
WHEN "110110001" => data <= conv_std_logic_vector(601,11);
WHEN "110110010" => data <= conv_std_logic_vector(599,11);
WHEN "110110011" => data <= conv_std_logic_vector(598,11);
WHEN "110110100" => data <= conv_std_logic_vector(597,11);
WHEN "110110101" => data <= conv_std_logic_vector(595,11);
WHEN "110110110" => data <= conv_std_logic_vector(594,11);
WHEN "110110111" => data <= conv_std_logic_vector(593,11);
WHEN "110111000" => data <= conv_std_logic_vector(592,11);
WHEN "110111001" => data <= conv_std_logic_vector(591,11);
WHEN "110111010" => data <= conv_std_logic_vector(589,11);
WHEN "110111011" => data <= conv_std_logic_vector(588,11);
WHEN "110111100" => data <= conv_std_logic_vector(587,11);
WHEN "110111101" => data <= conv_std_logic_vector(586,11);
WHEN "110111110" => data <= conv_std_logic_vector(584,11);
WHEN "110111111" => data <= conv_std_logic_vector(583,11);
WHEN "111000000" => data <= conv_std_logic_vector(582,11);
WHEN "111000001" => data <= conv_std_logic_vector(581,11);
WHEN "111000010" => data <= conv_std_logic_vector(580,11);
WHEN "111000011" => data <= conv_std_logic_vector(578,11);
WHEN "111000100" => data <= conv_std_logic_vector(577,11);
WHEN "111000101" => data <= conv_std_logic_vector(576,11);
WHEN "111000110" => data <= conv_std_logic_vector(575,11);
WHEN "111000111" => data <= conv_std_logic_vector(574,11);
WHEN "111001000" => data <= conv_std_logic_vector(572,11);
WHEN "111001001" => data <= conv_std_logic_vector(571,11);
WHEN "111001010" => data <= conv_std_logic_vector(570,11);
WHEN "111001011" => data <= conv_std_logic_vector(569,11);
WHEN "111001100" => data <= conv_std_logic_vector(568,11);
WHEN "111001101" => data <= conv_std_logic_vector(566,11);
WHEN "111001110" => data <= conv_std_logic_vector(565,11);
WHEN "111001111" => data <= conv_std_logic_vector(564,11);
WHEN "111010000" => data <= conv_std_logic_vector(563,11);
WHEN "111010001" => data <= conv_std_logic_vector(562,11);
WHEN "111010010" => data <= conv_std_logic_vector(561,11);
WHEN "111010011" => data <= conv_std_logic_vector(560,11);
WHEN "111010100" => data <= conv_std_logic_vector(558,11);
WHEN "111010101" => data <= conv_std_logic_vector(557,11);
WHEN "111010110" => data <= conv_std_logic_vector(556,11);
WHEN "111010111" => data <= conv_std_logic_vector(555,11);
WHEN "111011000" => data <= conv_std_logic_vector(554,11);
WHEN "111011001" => data <= conv_std_logic_vector(553,11);
WHEN "111011010" => data <= conv_std_logic_vector(552,11);
WHEN "111011011" => data <= conv_std_logic_vector(551,11);
WHEN "111011100" => data <= conv_std_logic_vector(549,11);
WHEN "111011101" => data <= conv_std_logic_vector(548,11);
WHEN "111011110" => data <= conv_std_logic_vector(547,11);
WHEN "111011111" => data <= conv_std_logic_vector(546,11);
WHEN "111100000" => data <= conv_std_logic_vector(545,11);
WHEN "111100001" => data <= conv_std_logic_vector(544,11);
WHEN "111100010" => data <= conv_std_logic_vector(543,11);
WHEN "111100011" => data <= conv_std_logic_vector(542,11);
WHEN "111100100" => data <= conv_std_logic_vector(541,11);
WHEN "111100101" => data <= conv_std_logic_vector(540,11);
WHEN "111100110" => data <= conv_std_logic_vector(538,11);
WHEN "111100111" => data <= conv_std_logic_vector(537,11);
WHEN "111101000" => data <= conv_std_logic_vector(536,11);
WHEN "111101001" => data <= conv_std_logic_vector(535,11);
WHEN "111101010" => data <= conv_std_logic_vector(534,11);
WHEN "111101011" => data <= conv_std_logic_vector(533,11);
WHEN "111101100" => data <= conv_std_logic_vector(532,11);
WHEN "111101101" => data <= conv_std_logic_vector(531,11);
WHEN "111101110" => data <= conv_std_logic_vector(530,11);
WHEN "111101111" => data <= conv_std_logic_vector(529,11);
WHEN "111110000" => data <= conv_std_logic_vector(528,11);
WHEN "111110001" => data <= conv_std_logic_vector(527,11);
WHEN "111110010" => data <= conv_std_logic_vector(526,11);
WHEN "111110011" => data <= conv_std_logic_vector(525,11);
WHEN "111110100" => data <= conv_std_logic_vector(524,11);
WHEN "111110101" => data <= conv_std_logic_vector(523,11);
WHEN "111110110" => data <= conv_std_logic_vector(522,11);
WHEN "111110111" => data <= conv_std_logic_vector(521,11);
WHEN "111111000" => data <= conv_std_logic_vector(520,11);
WHEN "111111001" => data <= conv_std_logic_vector(519,11);
WHEN "111111010" => data <= conv_std_logic_vector(518,11);
WHEN "111111011" => data <= conv_std_logic_vector(517,11);
WHEN "111111100" => data <= conv_std_logic_vector(516,11);
WHEN "111111101" => data <= conv_std_logic_vector(515,11);
WHEN "111111110" => data <= conv_std_logic_vector(514,11);
WHEN "111111111" => data <= conv_std_logic_vector(513,11);
WHEN others => data <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_cos.vhd | 10 | 12425 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
| mit |
dtysky/LD3320_FPGA_CONTROLLER | VOICE.vhd | 1 | 15545 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity VOICE is
port
(
start:in std_logic;
clk:in std_logic;
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
voice_result:out std_logic_vector(7 downto 0):=x"00";
reco_rqu:in std_logic:='0';
reco_fin:out std_logic:='0'
);
end entity;
architecture voicex of VOICE is
component voice_clock is
port
(
inclk0:in std_logic;
c0:out std_logic;
c1:out std_logic
);
end component;
component voice_rom_init is
port
(
clock:in std_logic;
address:in std_logic_vector(5 downto 0);
q:out std_logic_vector(15 downto 0)
);
end component;
component list is
port
(
clock:in std_logic;
address:in std_logic_vector(8 downto 0);
q:out std_logic_vector(7 downto 0)
);
end component;
component VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end component;
-------------------时钟、40MHz---------------------
signal clk_self,clk_out:std_logic;
-----------------------复位------------------------
signal reset:std_logic:='0';
--------------------初始化ROM----------------------
signal rom_init_addr:std_logic_vector(5 downto 0);
signal rom_init_data:std_logic_vector(15 downto 0);
---------------------列表ROM-----------------------
signal rom_list_addr:std_logic_vector(8 downto 0);
signal rom_list_data:std_logic_vector(7 downto 0);
-----------------------延时------------------------
signal delay_start,delay_finish:std_logic:='0';
signal delay_total:std_logic_vector(7 downto 0);
----------------------配置状态----------------------
signal init_done,list_done,all_wait,all_done,all_done_last:std_logic:='0';
----------------------识别状态----------------------
signal reco_allow,reco_allow_last,reco_start:std_logic:='0';
signal reco_rqu_last:std_logic:='0';
signal n_int_last:std_logic:='1';
signal add_en_s:std_logic:='1';
begin
clk_voice<=clk_self;
add_en<=add_en_s;
VOICE_CLOCKX:voice_clock port map(inclk0=>clk,c0=>clk_self,c1=>clk_out);
VOICE_ROM_INITX:voice_rom_init port map(clock=>clk_out,address=>rom_init_addr,q=>rom_init_data);
VOICE_ROM_LIST:list port map(clock=>clk_out,address=>rom_list_addr,q=>rom_list_data);
VOICE_DLLAYX:voice_delay port map(clk=>clk_self,start=>delay_start,finish=>delay_finish,total=>delay_total);
process(clk_self,reset)
variable con_reset:integer range 0 to 127:=0;
variable con_init_start:integer range 0 to 2047:=0;
variable con:integer range 0 to 5:=0;
variable con_total:integer range 0 to 26:=0;
variable con_type:integer range 0 to 31:=0;
variable con_init_fin_start:integer range 0 to 3:=0;
begin
if clk_self'event and clk_self='1' then
--------------------复位-----------------------
if con_reset=127 then
reset<='1';
end if;
if reset='1' then
con_reset:=0;
reset<='0';
reco_fin<='0';
init_done<='0';
list_done<='0';
all_wait<='0';
all_done<='0';
reco_allow<='0';
rom_init_addr<="000000";
rom_list_addr<="000000000";
con_init_start:=0;
end if;
---------------------初始化----------------------
if start='1' then
if con_init_start=2047 then
con_init_start:=2047;
else
con_init_start:=con_init_start+1;
con:=0;
con_type:=0;
con_total:=0;
con_init_fin_start:=0;
end if;
end if;
if con_init_start=500 then
n_rst<='0';
elsif con_init_start=1000 then
n_rst<='1';
elsif con_init_start=1500 then
n_cs<='0';
elsif con_init_start=2000 then
n_cs<='1';
delay_start<='1';
delay_total<=x"5F";
end if;
--------------------初始化---------------------
if con_init_start=2047 and init_done='0' and delay_finish='1' then
if con=5 then
con:=0;
elsif con=0 then
if con_total=26 then
init_done<='1';
con:=0;
con_type:=0;
con_total:=0;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
-------------------------------------------------------
if con_total=0 or con_total=2 then
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=x"06";
else
add_en_s<='0';
data_voice<="ZZZZZZZZ";
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_type=0 then
n_wr<='0';
else
n_rd<='0';
end if;
elsif con=4 then
if add_en_s='0' then
delay_total<=x"0A";
delay_start<='1';
end if;
if con_type=0 then
n_wr<='1';
else
n_rd<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
-------------------------------------------------------
else
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
delay_total<=x"0A";
delay_start<='1';
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
-------------------待识别列表写入----------------
if init_done='1' and list_done='0' and delay_finish='1' then
if con=0 then
delay_start<='0';
con:=con+1;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
elsif con_type=10 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=1 then
if rom_list_data=x"FF" then
con_type:=20;
--list_done<='1';
delay_total<=x"5F";
delay_start<='1';
con:=0;
--con_type:=0;
else
add_en_s<='1';
data_voice<=x"C1";
con:=con+1;
con_type:=2;
end if;
elsif con_type=20 then
add_en_s<='1';
data_voice<=x"BF";
con:=con+1;
elsif con_type=21 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=2 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=12;
elsif con_type=12 then
add_en_s<='1';
data_voice<=x"C3";
con:=con+1;
con_type:=13;
elsif con_type=13 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=14;
elsif con_type=14 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=15;
elsif con_type=15 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=16;
elsif con_type=16 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=17;
elsif con_type=17 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=3;
elsif con_type=3 then
add_en_s<='1';
data_voice<=x"05";
con:=con+1;
con_type:=11;
rom_list_addr<=rom_list_addr+1;
elsif con_type=4 then
add_en_s<='1';
data_voice<=x"B9";
con:=con+1;
con_type:=5;
rom_list_addr<=rom_list_addr+1;
elsif con_type=5 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=6;
elsif con_type=6 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
con_type:=7;
elsif con_type=7 then
add_en_s<='0';
data_voice<=x"FF";
con:=con+1;
con_type:=8;
elsif con_type=8 then
add_en_s<='1';
data_voice<=x"37";
con:=con+1;
con_type:=9;
elsif con_type=9 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=0;
rom_list_addr<=rom_list_addr+1;
elsif con_type=11 then
if rom_list_data=x"FF" then
con_type:=4;
con:=0;
else
add_en_s<='0';
data_voice<=rom_list_data;
rom_list_addr<=rom_list_addr+1;
con:=con+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
con:=con+1;
elsif con=3 then
con:=con+1;
if con_type=10 or con_type=21 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
con:=con+1;
if add_en_s='0' and con_type/=11 then
delay_total<=x"01";
delay_start<='1';
end if;
if con_type=21 or con_type=10 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
con:=0;
if con_type=10 then
if data_voice=x"21" then
con_type:=1;
else
delay_total<=x"0A";
delay_start<='1';
con_type:=0;
con_reset:=con_reset+1;
end if;
elsif con_type=0 then
con_type:=10;
elsif con_type=20 then
con_type:=21;
elsif con_type=21 then
if data_voice=x"31" then
con_type:=0;
list_done<='1';
con:=0;
con_type:=0;
else
reset<='1';
end if;
end if;
end if;
end if;
-------------------------识别准备------------------------
reco_rqu_last<=reco_rqu;
if reco_rqu_last='0' and reco_rqu='1' then
reco_start<='1';
end if;
if list_done='1' and all_wait='0' and reco_start='1' and delay_finish='1' then
if con_init_fin_start=3 then
con_init_fin_start:=3;
else
rom_init_addr<="100000";
con_init_fin_start:=con_init_fin_start+1;
end if;
if con_init_fin_start=3 then
if con=5 then
con:=0;
elsif con=0 then
if con_total=5 then
all_wait<='1';
reco_start<='0';
con:=0;
con_type:=0;
con_total:=0;
con_reset:=0;
elsif con_total=0 then
con:=con+1;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
if add_en_s='0' then
delay_total<=x"01";
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
---------------------------识别--------------------------
if all_wait='1' and delay_finish='1' then
if con=5 then
con:=0;
elsif con=0 then
if con_total=7 then
con_total:=0;
con_type:=0;
con:=0;
all_wait<='0';
all_done<='1';
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"B2";
elsif con_total=3 then
data_voice<=x"BF";
else
data_voice<=rom_init_data(15 downto 8);
end if;
else
add_en_s<='0';
if con_total=0 or con_total=3 then
data_voice<="ZZZZZZZZ";
else
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
if add_en_s='0' then
if con_total=2 then
delay_total<=x"05";
else
delay_total<=x"01";
end if;
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_total=0 and con_type=1 then
if data_voice=x"21" then
con_total:=con_total+1;
else
con_reset:=con_reset+1;
con_total:=0;
end if;
elsif con_total=3 and con_type=1 then
if data_voice=x"31" then
con_total:=con_total+1;
else
reco_fin<='1';
data_voice<=x"FF";
reset<='1';
end if;
elsif con_type=1 then
con_total:=con_total+1;
end if;
if con_type=1 then
con_type:=0;
else
con_type:=con_type+1;
end if;
end if;
end if;
-----------------------识别结果---------------------
if all_done='1' and delay_finish='1' then
n_int_last<=n_int;
if n_int_last='1' and n_int='0' then
reco_allow<='1';
end if;
end if;
reco_allow_last<=reco_allow;
if reco_allow_last='1' and reco_allow='0' then
reco_fin<='0';
end if;
if reco_allow='1' then
if con=5 then
con:=0;
else
con:=con+1;
end if;
if con=0 then
if con_total=6 then
reco_allow<='0';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"29";
elsif con_total=1 then
data_voice<=x"02";
elsif con_total=2 then
data_voice<=x"BF";
elsif con_total=3 then
data_voice<=x"2B";
elsif con_total=4 then
data_voice<=x"BA";
elsif con_total=5 then
data_voice<=x"C5";
end if;
else
add_en_s<='0';
if con_total<2 then
data_voice<=x"00";
else
data_voice<="ZZZZZZZZ";
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_total>1 and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if con_total>1 and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
if con_total<2 then
con_total:=con_total+1;
elsif con_total=2 and data_voice=x"35" then
con_total:=con_total+1;
elsif con_total=3 and data_voice(3)='0' then
con_total:=con_total+1;
elsif con_total=4 then
if data_voice>x"00" and data_voice<x"05" then
con_total:=con_total+1;
else
voice_result<=x"FD";
reco_allow<='0';
reco_fin<='1';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con_total=5 then
reco_fin<='1';
voice_result<=data_voice;
con_total:=con_total+1;
else
reset<='1';
end if;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
end process;
end voicex;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_mul3236b.vhd | 10 | 2219 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236B.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (behavioral) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236b IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236b;
ARCHITECTURE rtl OF hcc_mul3236b IS
signal aaff, bbff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal mulff, muloutff : STD_LOGIC_VECTOR (2*width DOWNTO 1);
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2*width LOOP
mulff(k) <= '0';
muloutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= aaff * bbff;
muloutff <= mulff;
END IF;
END IF;
END PROCESS;
cc <= muloutff;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_mul54us_29s.vhd | 10 | 11459 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_29S.VHD ***
--*** ***
--*** Function: 5/6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 29S: Stratix 2, 9 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Identical to HCC_MUL54US_29S, except 5 ***
--*** or 6 pipeline parameter and 72 outputs ***
--***************************************************
ENTITY fp_mul54us_29s IS
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_29s;
ARCHITECTURE syn of fp_mul54us_29s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulsixaa, mulsixbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout, mulsixout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal vecsix, vecsev, vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(36 DOWNTO 1);
mulonebb <= mulbb(36 DOWNTO 1);
multwoaa <= mulaa(54 DOWNTO 37);
multwobb <= mulbb(18 DOWNTO 1);
multhraa <= mulaa(54 DOWNTO 37);
multhrbb <= mulbb(36 DOWNTO 19);
mulforaa <= mulbb(54 DOWNTO 37);
mulforbb <= mulaa(18 DOWNTO 1);
mulfivaa <= mulbb(54 DOWNTO 37);
mulfivbb <= mulaa(36 DOWNTO 19);
mulsixaa <= mulbb(54 DOWNTO 37);
mulsixbb <= mulaa(54 DOWNTO 37);
-- {C,A) * {D,B}
-- CAA
-- DBB
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
-- C*D 18*18 = 36, latency = 3
mulsix : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => mulsixaa,
datab => mulsixbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulsixout
);
vecone <= zerovec(36 DOWNTO 1) & multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(36 DOWNTO 1) & mulforout;
vecfor <= zerovec(18 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 72 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(71 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 72 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(71 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= sumoneff;
vecnin <= caroneff;
vecten <= mulsixout & muloneout(72 DOWNTO 37);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => latency-4,
lpm_type => "LPM_ADD_SUB",
lpm_width => 72
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 1),
datab => cartwoff(72 DOWNTO 1),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_mul54us_29s.vhd | 10 | 11459 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_29S.VHD ***
--*** ***
--*** Function: 5/6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 29S: Stratix 2, 9 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Identical to HCC_MUL54US_29S, except 5 ***
--*** or 6 pipeline parameter and 72 outputs ***
--***************************************************
ENTITY fp_mul54us_29s IS
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_29s;
ARCHITECTURE syn of fp_mul54us_29s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulsixaa, mulsixbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout, mulsixout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal vecsix, vecsev, vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(36 DOWNTO 1);
mulonebb <= mulbb(36 DOWNTO 1);
multwoaa <= mulaa(54 DOWNTO 37);
multwobb <= mulbb(18 DOWNTO 1);
multhraa <= mulaa(54 DOWNTO 37);
multhrbb <= mulbb(36 DOWNTO 19);
mulforaa <= mulbb(54 DOWNTO 37);
mulforbb <= mulaa(18 DOWNTO 1);
mulfivaa <= mulbb(54 DOWNTO 37);
mulfivbb <= mulaa(36 DOWNTO 19);
mulsixaa <= mulbb(54 DOWNTO 37);
mulsixbb <= mulaa(54 DOWNTO 37);
-- {C,A) * {D,B}
-- CAA
-- DBB
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
-- C*D 18*18 = 36, latency = 3
mulsix : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => mulsixaa,
datab => mulsixbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulsixout
);
vecone <= zerovec(36 DOWNTO 1) & multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(36 DOWNTO 1) & mulforout;
vecfor <= zerovec(18 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 72 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(71 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 72 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(71 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= sumoneff;
vecnin <= caroneff;
vecten <= mulsixout & muloneout(72 DOWNTO 37);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => latency-4,
lpm_type => "LPM_ADD_SUB",
lpm_width => 72
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 1),
datab => cartwoff(72 DOWNTO 1),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_mul54us_29s.vhd | 10 | 11459 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_29S.VHD ***
--*** ***
--*** Function: 5/6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 29S: Stratix 2, 9 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Identical to HCC_MUL54US_29S, except 5 ***
--*** or 6 pipeline parameter and 72 outputs ***
--***************************************************
ENTITY fp_mul54us_29s IS
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_29s;
ARCHITECTURE syn of fp_mul54us_29s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulsixaa, mulsixbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout, mulsixout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal vecsix, vecsev, vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(36 DOWNTO 1);
mulonebb <= mulbb(36 DOWNTO 1);
multwoaa <= mulaa(54 DOWNTO 37);
multwobb <= mulbb(18 DOWNTO 1);
multhraa <= mulaa(54 DOWNTO 37);
multhrbb <= mulbb(36 DOWNTO 19);
mulforaa <= mulbb(54 DOWNTO 37);
mulforbb <= mulaa(18 DOWNTO 1);
mulfivaa <= mulbb(54 DOWNTO 37);
mulfivbb <= mulaa(36 DOWNTO 19);
mulsixaa <= mulbb(54 DOWNTO 37);
mulsixbb <= mulaa(54 DOWNTO 37);
-- {C,A) * {D,B}
-- CAA
-- DBB
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
-- C*D 18*18 = 36, latency = 3
mulsix : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => mulsixaa,
datab => mulsixbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulsixout
);
vecone <= zerovec(36 DOWNTO 1) & multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(36 DOWNTO 1) & mulforout;
vecfor <= zerovec(18 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 72 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(71 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 72 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(71 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= sumoneff;
vecnin <= caroneff;
vecten <= mulsixout & muloneout(72 DOWNTO 37);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => latency-4,
lpm_type => "LPM_ADD_SUB",
lpm_width => 72
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 1),
datab => cartwoff(72 DOWNTO 1),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_mul54us_29s.vhd | 10 | 11459 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_29S.VHD ***
--*** ***
--*** Function: 5/6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 29S: Stratix 2, 9 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Identical to HCC_MUL54US_29S, except 5 ***
--*** or 6 pipeline parameter and 72 outputs ***
--***************************************************
ENTITY fp_mul54us_29s IS
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_29s;
ARCHITECTURE syn of fp_mul54us_29s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulsixaa, mulsixbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout, mulsixout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal vecsix, vecsev, vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(36 DOWNTO 1);
mulonebb <= mulbb(36 DOWNTO 1);
multwoaa <= mulaa(54 DOWNTO 37);
multwobb <= mulbb(18 DOWNTO 1);
multhraa <= mulaa(54 DOWNTO 37);
multhrbb <= mulbb(36 DOWNTO 19);
mulforaa <= mulbb(54 DOWNTO 37);
mulforbb <= mulaa(18 DOWNTO 1);
mulfivaa <= mulbb(54 DOWNTO 37);
mulfivbb <= mulaa(36 DOWNTO 19);
mulsixaa <= mulbb(54 DOWNTO 37);
mulsixbb <= mulaa(54 DOWNTO 37);
-- {C,A) * {D,B}
-- CAA
-- DBB
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
-- C*D 18*18 = 36, latency = 3
mulsix : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => mulsixaa,
datab => mulsixbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulsixout
);
vecone <= zerovec(36 DOWNTO 1) & multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(36 DOWNTO 1) & mulforout;
vecfor <= zerovec(18 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 72 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(71 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 72 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(71 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= sumoneff;
vecnin <= caroneff;
vecten <= mulsixout & muloneout(72 DOWNTO 37);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => latency-4,
lpm_type => "LPM_ADD_SUB",
lpm_width => 72
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 1),
datab => cartwoff(72 DOWNTO 1),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_castxtof_sv.vhd | 10 | 11806 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOF.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 17/04/09 - add NAN support, also fixed zero/infinity/nan mantissa ***
--*** 29/04/09 - zero output if mantissa in zero ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: 5 + 2*(swSingleNormSpeed-1) ***
--******************************************************************************
ENTITY hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castxtof;
ARCHITECTURE rtl OF hcc_castxtof IS
-- latency = 5 if normspeed = 1
-- latency = 7 if normspeed = 2 (extra pipe in normusgn3236 and output stage)
type exptopfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type expbotfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal count : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal absnode, absroundnode, absff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : expbotfftype;
signal roundoverflow : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal satff, zipff, nanff : STD_LOGIC_VECTOR (3+normspeed DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2+2*normspeed DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal preexpnode, expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal roundbit : STD_LOGIC;
signal mantissaroundff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode, maxmantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal zeromantissaff, maxmantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
signal ccsgn : STD_LOGIC;
signal aaexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (23 DOWNTO 1);
component hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
absff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 10 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
roundoverflowff <= '0';
FOR k IN 1 TO 3+normspeed LOOP
satff(k) <= '0';
zipff(k) <= '0';
nanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2+2*normspeed LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 1+normspeed LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
absff <= absnode + absroundnode;
fracoutff <= fracout;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
-- add 4 because of maximum 4 bits wordgrowth in X mantissa
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) + "0000000100";
exptopff(3)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1) - ("0000" & count);
roundoverflowff <= roundoverflow(24);
satff(1) <= aasat;
FOR k IN 2 TO 3+normspeed LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO 3+normspeed LOOP
zipff(k) <= zipff(k-1);
END LOOP;
nanff(1) <= aanan;
FOR k IN 2 TO 3+normspeed LOOP
nanff(k) <= nanff(k-1);
END LOOP;
signff(1) <= aaff(mantissa+10);
FOR k IN 2 TO 2+2*normspeed LOOP
signff(k) <= signff(k-1);
END LOOP;
zeronumberff(1) <= NOT(zeronumber(mantissa));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsa: IF (normspeed = 1) GENERATE
pna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= (mantissanode(k) AND NOT(zeromantissanode)) OR maxmantissanode;
END LOOP;
END IF;
END IF;
END PROCESS;
preexpnode <= exptopff(3)(10 DOWNTO 1);
END GENERATE;
-- if normspeed = 1, latency = 5. if normspeed > 1, latency = 7
gsb: IF (normspeed = 2) GENERATE
pnb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
expbotff(1)(10 DOWNTO 1) <= "0000000000";
expbotff(2)(10 DOWNTO 1) <= "0000000000";
exponentff <= "00000000";
FOR k IN 1 TO 23 LOOP
mantissaroundff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
maxmantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(1)(10 DOWNTO 1) <= exptopff(3)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expnode;
FOR k IN 1 TO 8 LOOP
exponentff(k) <= (expbotff(2)(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
mantissaroundff <= mantissanode;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= (mantissaroundff(k) AND NOT(zeromantissaff)) OR maxmantissaff;
END LOOP;
zeromantissaff <= zeromantissanode;
maxmantissaff <= maxmantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END IF;
END PROCESS;
preexpnode <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
-- round absolute value any way - need register on input of cntusgn
gaa: FOR k IN 1 TO mantissa GENERATE
absnode(k) <= aaff(k+10) XOR aaff(mantissa+10);
END GENERATE;
absroundnode <= zerovec(mantissa-1 DOWNTO 1) & aaff(mantissa+10);
zeronumber(1) <= absff(1);
gzma: FOR k IN 2 TO mantissa GENERATE
zeronumber(k) <= zeronumber(k-1) OR absff(k);
END GENERATE;
core: hcc_normusgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absff(mantissa DOWNTO 1),countout=>count,
fracout=>fracout);
roundoverflow(1) <= fracout(7);
gna: FOR k IN 2 TO 24 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+6);
END GENERATE;
expnode <= preexpnode(10 DOWNTO 1) + ("000000000" & roundoverflowff);
-- always round single output (round to nearest even)
roundbit <= (fracoutff(mantissa-24) AND fracoutff(mantissa-25)) OR
(NOT(fracoutff(mantissa-24)) AND fracoutff(mantissa-25) AND
(fracoutff(mantissa-26) OR fracoutff(mantissa-27) OR fracoutff(mantissa-28)));
mantissanode <= fracoutff(mantissa-2 DOWNTO mantissa-24) +
(zerovec(22 DOWNTO 1) & roundbit);
--ML March 8, 2011 consider expnode(10 DOWNTO 9) for zeroexpnode and maxexpnode calculation
zeroexpnode <= NOT(expnode(10) OR
expnode(9) OR expnode(8) OR expnode(7) OR
expnode(6) OR expnode(5) OR expnode(4) OR
expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(10)) AND NOT(expnode(9)) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- all following '1' when true
-- 24/03/09 - zeroexpnode, maxexpnode also zeros mantissa (SRC bug)
zeromantissanode <= roundoverflowff OR zeroexpnode OR maxexpnode OR
expnode(9) OR expnode(10) OR
zipff(3+normspeed) OR satff(3+normspeed) OR
zeronumberff(1+normspeed);
maxmantissanode <= nanff(3+normspeed);
zeroexponentnode <= zeroexpnode OR expnode(10) OR
zipff(3+normspeed) OR zeronumberff(1+normspeed);
maxexponentnode <= maxexpnode OR (expnode(9) AND NOT(expnode(10))) OR
satff(3+normspeed) OR nanff(3+normspeed);
--*** OUTPUTS ***
cc(32) <= signff(2+2*normspeed);
cc(31 DOWNTO 24) <= exponentff;
cc(23 DOWNTO 1) <= mantissaff(23 DOWNTO 1);
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccsgn <= signff(2+2*normspeed);
ccexp <= exponentff;
ccman <= mantissaff(23 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_acos_prep1.vhd | 10 | 11182 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ACOS_PREP1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** ACOS/ASIN Setup - generate 1-x, 1-x*x ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 8 ***
--***************************************************
ENTITY fp_acos_prep1 IS
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_acos_prep1 ;
ARCHITECTURE rtl OF fp_acos_prep1 IS
type denominator_shiftfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (8 DOWNTO 1);
type numerator_fixedpointfftype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
type denominator_fixedpointfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaextendff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_shiftff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_shiftff : denominator_shiftfftype;
signal x_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_squared_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_fixedpointff : numerator_fixedpointfftype;
signal denominator_fixedpointff : denominator_fixedpointfftype;
signal numerator_leadingff, denominator_leadingff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numerator_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaextend : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_squared : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal x_squared_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_leading : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominator_leading : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
pinx: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
mantissaextendff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
numerator_shiftff(k) <= '0';
denominator_shiftff(1)(k) <= '0';
denominator_shiftff(2)(k) <= '0';
denominator_shiftff(3)(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
x_fixedpointff(k) <= '0';
x_squared_fixedpointff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
FOR j IN 1 TO 36 LOOP
numerator_fixedpointff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 36 LOOP
denominator_fixedpointff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 6 LOOP
numerator_leadingff(k) <= '0';
denominator_leadingff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numerator_mantissaff(k) <= '0';
denominator_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
numerator_exponentff(k) <= '0';
denominator_exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 8 LOOP
signff(k) <= signff(k-1);
END LOOP;
mantissainff <= mantissain; -- level 1
exponentinff <= exponentin; -- level 1
mantissaextendff <= mantissaextend; -- level 2
numerator_shiftff <= 127 - exponentinff; -- exponent will always be 127 or less, level 2
denominator_shiftff(1)(8 DOWNTO 1) <= 253 - (exponentinff(7 DOWNTO 1) & '0'); -- level 2
denominator_shiftff(2)(8 DOWNTO 1) <= denominator_shiftff(1)(8 DOWNTO 1); -- level 3
denominator_shiftff(3)(8 DOWNTO 1) <= denominator_shiftff(2)(8 DOWNTO 1); -- level 4
x_fixedpointff <= x_fixedpoint; -- level 3
numerator_fixedpointff(1)(36 DOWNTO 1) <= ('1' & zerovec(35 DOWNTO 1)) - x_fixedpointff; -- level 4
numerator_fixedpointff(2)(36 DOWNTO 1) <= numerator_fixedpointff(1)(36 DOWNTO 1); -- level 5
numerator_fixedpointff(3)(36 DOWNTO 1) <= numerator_fixedpointff(2)(36 DOWNTO 1); -- level 6
numerator_fixedpointff(4)(36 DOWNTO 1) <= numerator_fixedpointff(3)(36 DOWNTO 1); -- level 7
x_squared_fixedpointff <= x_squared_fixedpoint; -- level 5
denominator_fixedpointff(1)(36 DOWNTO 1) <= ('1' & zerovec(35 DOWNTO 1)) - x_squared_fixedpointff; -- level 6
denominator_fixedpointff(2)(36 DOWNTO 1) <= denominator_fixedpointff(1)(36 DOWNTO 1); -- level 7
numerator_leadingff <= numerator_leading; -- level 7
denominator_leadingff <= denominator_leading; -- level 7
numerator_mantissaff <= numerator_mantissanode;
numerator_exponentff <= numerator_exponentnode;
denominator_mantissaff <= denominator_mantissanode;
denominator_exponentff <= denominator_exponentnode;
END IF;
END IF;
END PROCESS;
mantissaextend <= '1' & mantissainff & zerovec(12 DOWNTO 1);
numsr: fp_rsft36
PORT MAP (inbus=>mantissaextendff,shift=>numerator_shiftff(6 DOWNTO 1),
outbus=>x_fixedpoint);
mulxx: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mantissaextend,databb=>mantissaextend,
result=>x_squared);
-- if x^2 <0.5, 1 bit normalization shift, output exp = 126
densr: fp_rsft36
PORT MAP (inbus=>x_squared,shift=>denominator_shiftff(3)(6 DOWNTO 1),
outbus=>x_squared_fixedpoint);
ccznum: fp_clz36
PORT MAP (mantissa=>numerator_fixedpointff(3)(36 DOWNTO 1),
leading=>numerator_leading);
csftnum: fp_lsft36
PORT MAP (inbus=>numerator_fixedpointff(4)(36 DOWNTO 1),shift=>numerator_leadingff,
outbus=>numerator_mantissanode);
numerator_exponentnode <= 127 - ("00" & numerator_leadingff);
cczd: fp_clz36
PORT MAP (mantissa=>denominator_fixedpointff(1)(36 DOWNTO 1),
leading=>denominator_leading);
cnd: fp_lsft36
PORT MAP (inbus=>denominator_fixedpointff(2)(36 DOWNTO 1),shift=>denominator_leadingff,
outbus=>denominator_mantissanode);
denominator_exponentnode <= 127 - ("00" & denominator_leadingff);
--*** OUTPUTS ***
signout <= signff(8);
numerator_mantissa <= numerator_mantissaff;
numerator_exponent <= numerator_exponentff;
denominator_mantissa <= denominator_mantissaff;
denominator_exponent <= denominator_exponentff;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_acos_prep1.vhd | 10 | 11182 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ACOS_PREP1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** ACOS/ASIN Setup - generate 1-x, 1-x*x ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 8 ***
--***************************************************
ENTITY fp_acos_prep1 IS
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_acos_prep1 ;
ARCHITECTURE rtl OF fp_acos_prep1 IS
type denominator_shiftfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (8 DOWNTO 1);
type numerator_fixedpointfftype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
type denominator_fixedpointfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaextendff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_shiftff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_shiftff : denominator_shiftfftype;
signal x_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_squared_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_fixedpointff : numerator_fixedpointfftype;
signal denominator_fixedpointff : denominator_fixedpointfftype;
signal numerator_leadingff, denominator_leadingff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numerator_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaextend : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_squared : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal x_squared_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_leading : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominator_leading : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
pinx: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
mantissaextendff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
numerator_shiftff(k) <= '0';
denominator_shiftff(1)(k) <= '0';
denominator_shiftff(2)(k) <= '0';
denominator_shiftff(3)(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
x_fixedpointff(k) <= '0';
x_squared_fixedpointff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
FOR j IN 1 TO 36 LOOP
numerator_fixedpointff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 36 LOOP
denominator_fixedpointff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 6 LOOP
numerator_leadingff(k) <= '0';
denominator_leadingff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numerator_mantissaff(k) <= '0';
denominator_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
numerator_exponentff(k) <= '0';
denominator_exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 8 LOOP
signff(k) <= signff(k-1);
END LOOP;
mantissainff <= mantissain; -- level 1
exponentinff <= exponentin; -- level 1
mantissaextendff <= mantissaextend; -- level 2
numerator_shiftff <= 127 - exponentinff; -- exponent will always be 127 or less, level 2
denominator_shiftff(1)(8 DOWNTO 1) <= 253 - (exponentinff(7 DOWNTO 1) & '0'); -- level 2
denominator_shiftff(2)(8 DOWNTO 1) <= denominator_shiftff(1)(8 DOWNTO 1); -- level 3
denominator_shiftff(3)(8 DOWNTO 1) <= denominator_shiftff(2)(8 DOWNTO 1); -- level 4
x_fixedpointff <= x_fixedpoint; -- level 3
numerator_fixedpointff(1)(36 DOWNTO 1) <= ('1' & zerovec(35 DOWNTO 1)) - x_fixedpointff; -- level 4
numerator_fixedpointff(2)(36 DOWNTO 1) <= numerator_fixedpointff(1)(36 DOWNTO 1); -- level 5
numerator_fixedpointff(3)(36 DOWNTO 1) <= numerator_fixedpointff(2)(36 DOWNTO 1); -- level 6
numerator_fixedpointff(4)(36 DOWNTO 1) <= numerator_fixedpointff(3)(36 DOWNTO 1); -- level 7
x_squared_fixedpointff <= x_squared_fixedpoint; -- level 5
denominator_fixedpointff(1)(36 DOWNTO 1) <= ('1' & zerovec(35 DOWNTO 1)) - x_squared_fixedpointff; -- level 6
denominator_fixedpointff(2)(36 DOWNTO 1) <= denominator_fixedpointff(1)(36 DOWNTO 1); -- level 7
numerator_leadingff <= numerator_leading; -- level 7
denominator_leadingff <= denominator_leading; -- level 7
numerator_mantissaff <= numerator_mantissanode;
numerator_exponentff <= numerator_exponentnode;
denominator_mantissaff <= denominator_mantissanode;
denominator_exponentff <= denominator_exponentnode;
END IF;
END IF;
END PROCESS;
mantissaextend <= '1' & mantissainff & zerovec(12 DOWNTO 1);
numsr: fp_rsft36
PORT MAP (inbus=>mantissaextendff,shift=>numerator_shiftff(6 DOWNTO 1),
outbus=>x_fixedpoint);
mulxx: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mantissaextend,databb=>mantissaextend,
result=>x_squared);
-- if x^2 <0.5, 1 bit normalization shift, output exp = 126
densr: fp_rsft36
PORT MAP (inbus=>x_squared,shift=>denominator_shiftff(3)(6 DOWNTO 1),
outbus=>x_squared_fixedpoint);
ccznum: fp_clz36
PORT MAP (mantissa=>numerator_fixedpointff(3)(36 DOWNTO 1),
leading=>numerator_leading);
csftnum: fp_lsft36
PORT MAP (inbus=>numerator_fixedpointff(4)(36 DOWNTO 1),shift=>numerator_leadingff,
outbus=>numerator_mantissanode);
numerator_exponentnode <= 127 - ("00" & numerator_leadingff);
cczd: fp_clz36
PORT MAP (mantissa=>denominator_fixedpointff(1)(36 DOWNTO 1),
leading=>denominator_leading);
cnd: fp_lsft36
PORT MAP (inbus=>denominator_fixedpointff(2)(36 DOWNTO 1),shift=>denominator_leadingff,
outbus=>denominator_mantissanode);
denominator_exponentnode <= 127 - ("00" & denominator_leadingff);
--*** OUTPUTS ***
signout <= signff(8);
numerator_mantissa <= numerator_mantissaff;
numerator_exponent <= numerator_exponentff;
denominator_mantissa <= denominator_mantissaff;
denominator_exponent <= denominator_exponentff;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/dp_lsftpipe64.vhd | 10 | 4808 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL **
--*** ***
--*** DP_LSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift 64 Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsftpipe64;
ARCHITECTURE rtl of dp_lsftpipe64 IS
signal levzip, levone, levtwo, levtwoff, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_rsqrt_s5.vhd | 10 | 93680 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_arcsinpi_s5.vhd | 10 | 575341 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arcsinpi_s5
-- VHDL created on Thu Feb 28 17:21:04 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arcsinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arcsinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(10 downto 0);
signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(10 downto 0);
signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (10 downto 0);
signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0);
signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n : std_logic_vector (0 downto 0);
signal shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (12 downto 0);
signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a : std_logic_vector (23 downto 0);
signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (25 downto 0);
signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 : std_logic_vector (49 downto 0);
signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr : UNSIGNED (49 downto 0);
signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (49 downto 0);
signal z2_uid93_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (1 downto 0);
signal piO2_uid101_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (27 downto 0);
signal fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0);
signal InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0);
signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (15 downto 0);
signal maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_b : std_logic_vector (24 downto 0);
signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 : std_logic_vector (41 downto 0);
signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr : SIGNED (42 downto 0);
signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_q : std_logic_vector (41 downto 0);
signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid400_arcsinXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid400_arcsinXTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_arcsinXTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_arcsinXTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid401_arcsinXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid401_arcsinXTabGen_lutmem_ia : std_logic_vector (22 downto 0);
signal memoryC1_uid401_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid401_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid401_arcsinXTabGen_lutmem_iq : std_logic_vector (22 downto 0);
signal memoryC1_uid401_arcsinXTabGen_lutmem_q : std_logic_vector (22 downto 0);
signal memoryC2_uid402_arcsinXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid402_arcsinXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid402_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid402_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid402_arcsinXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid402_arcsinXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid422_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid422_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid422_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid422_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid422_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid422_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid423_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid423_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid423_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid423_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid423_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid423_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid424_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid424_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid424_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid424_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid424_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid424_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (25 downto 0);
signal reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (25 downto 0);
signal reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q : std_logic_vector (25 downto 0);
signal reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q : std_logic_vector (25 downto 0);
signal reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q : std_logic_vector (24 downto 0);
signal reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (27 downto 0);
signal reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q : std_logic_vector (7 downto 0);
signal ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (25 downto 0);
signal ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : signal is true;
signal ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : signal is true;
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 : std_logic;
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : signal is true;
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : signal is true;
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 : std_logic;
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : signal is true;
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia : std_logic_vector (16 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq : std_logic_vector (16 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q : std_logic_vector (16 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q : signal is true;
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic;
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (35 downto 0);
signal excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n : std_logic_vector (0 downto 0);
signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c : std_logic_vector (0 downto 0);
signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (32 downto 0);
signal InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal expX_uid15_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0);
signal expL_uid82_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0);
signal expL_uid82_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0);
signal expL_uid82_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0);
signal expL_uid82_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0);
signal srVal_uid89_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0);
signal srVal_uid89_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0);
signal srVal_uid89_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0);
signal srVal_uid89_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0);
signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(28 downto 0);
signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(28 downto 0);
signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (28 downto 0);
signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (28 downto 0);
signal fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid125_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid125_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid125_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (35 downto 0);
signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (49 downto 0);
signal normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0);
signal piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in : std_logic_vector (41 downto 0);
signal prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (17 downto 0);
signal mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (16 downto 0);
signal concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0);
signal R_uid227_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (15 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid126_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (3 downto 0);
signal expLRange_uid84_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid84_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid92_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid92_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (4 downto 0);
signal normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (27 downto 0);
signal normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0);
signal path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (11 downto 0);
signal InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (36 downto 0);
signal arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid59_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid59_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (18 downto 0);
signal vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0);
signal vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (32 downto 0);
signal vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (8 downto 0);
signal expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (24 downto 0);
signal fpOOPi_uid11_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (24 downto 0);
signal X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (17 downto 0);
signal X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (9 downto 0);
signal X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0);
signal fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid258_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid258_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid259_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid259_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid264_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid264_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid265_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid265_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid405_arcsinXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid405_arcsinXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid406_arcsinXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid406_arcsinXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid411_arcsinXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid411_arcsinXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid412_arcsinXPolyEval_in : std_logic_vector (25 downto 0);
signal highBBits_uid412_arcsinXPolyEval_b : std_logic_vector (23 downto 0);
signal lowRangeB_uid427_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid427_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid428_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid428_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid433_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid433_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid434_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid434_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid403_arcsinXPolyEval_in : std_logic_vector (16 downto 0);
signal yT1_uid403_arcsinXPolyEval_b : std_logic_vector (12 downto 0);
signal yT1_uid425_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid425_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0);
signal fpL_uid85_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal Y34_uid60_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal Y34_uid60_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal yAddr_uid63_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid63_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (17 downto 0);
signal oMy_uid78_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(36 downto 0);
signal oMy_uid78_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(36 downto 0);
signal oMy_uid78_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (36 downto 0);
signal oMy_uid78_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (32 downto 0);
signal rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid260_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid260_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid260_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid260_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid266_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid266_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid266_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid266_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid407_arcsinXPolyEval_a : std_logic_vector(23 downto 0);
signal sumAHighB_uid407_arcsinXPolyEval_b : std_logic_vector(23 downto 0);
signal sumAHighB_uid407_arcsinXPolyEval_o : std_logic_vector (23 downto 0);
signal sumAHighB_uid407_arcsinXPolyEval_q : std_logic_vector (23 downto 0);
signal sumAHighB_uid413_arcsinXPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid413_arcsinXPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid413_arcsinXPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid413_arcsinXPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid429_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid429_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid435_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid435_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid435_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid435_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (24 downto 0);
signal InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal path2_uid61_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal path2_uid61_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid256_arcsinXO2XPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid256_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal l_uid80_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal l_uid80_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0);
signal vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid258_uid261_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid264_uid267_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid405_uid408_arcsinXPolyEval_q : std_logic_vector (24 downto 0);
signal s2_uid411_uid414_arcsinXPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid427_uid430_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid433_uid436_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (0 downto 0);
signal expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (6 downto 0);
signal RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0);
signal RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (19 downto 0);
signal pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0);
signal rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (2 downto 0);
signal rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0);
signal vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0);
signal vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal mAddr_uid97_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0);
signal mAddr_uid97_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (25 downto 0);
signal fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (27 downto 0);
signal fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (28 downto 0);
signal fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0);
signal InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (33 downto 0);
signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0);
signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0);
signal fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0);
signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (25 downto 0);
signal SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0);
signal SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0);
signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (3 downto 0);
signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest(CONSTANT,18)
cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000000";
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable(LOGICAL,1059)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a <= en;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q <= not ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a;
--ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor(LOGICAL,1162)
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q <= not (ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a or ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b);
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top(CONSTANT,1082)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q <= "011110";
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp(LOGICAL,1083)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q);
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q <= "1" when ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a = ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b else "0";
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg(REG,1084)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena(REG,1163)
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q = "1") THEN
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd(LOGICAL,1164)
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b <= en;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a and ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b;
--fracX_uid16_asinX_uid8_fpArcsinPiTest(BITSELECT,15)@0
fracX_uid16_asinX_uid8_fpArcsinPiTest_in <= a(22 downto 0);
fracX_uid16_asinX_uid8_fpArcsinPiTest_b <= fracX_uid16_asinX_uid8_fpArcsinPiTest_in(22 downto 0);
--fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest(LOGICAL,34)@0
fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a <= fracX_uid16_asinX_uid8_fpArcsinPiTest_b;
fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q <= "1" when fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a = fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b else "0";
--InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a <= fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q;
InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q <= not InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a;
--cstBias_uid22_asinX_uid8_fpArcsinPiTest(CONSTANT,21)
cstBias_uid22_asinX_uid8_fpArcsinPiTest_q <= "01111111";
--expX_uid15_asinX_uid8_fpArcsinPiTest(BITSELECT,14)@0
expX_uid15_asinX_uid8_fpArcsinPiTest_in <= a(30 downto 0);
expX_uid15_asinX_uid8_fpArcsinPiTest_b <= expX_uid15_asinX_uid8_fpArcsinPiTest_in(30 downto 23);
--expEQ0_uid45_asinX_uid8_fpArcsinPiTest(LOGICAL,44)@0
expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b;
expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q;
expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q <= "1" when expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a = expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b else "0";
--exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest(LOGICAL,46)@0
exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a <= expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q;
exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q;
exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q <= exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a and exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b;
--GND(CONSTANT,0)
GND_q <= "0";
--expGT0_uid44_asinX_uid8_fpArcsinPiTest(COMPARE,43)@0
expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin <= GND_q;
expGT0_uid44_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid22_asinX_uid8_fpArcsinPiTest_q) & '0';
expGT0_uid44_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_asinX_uid8_fpArcsinPiTest_b) & expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin(0);
expGT0_uid44_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid44_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(expGT0_uid44_asinX_uid8_fpArcsinPiTest_b));
expGT0_uid44_asinX_uid8_fpArcsinPiTest_c(0) <= expGT0_uid44_asinX_uid8_fpArcsinPiTest_o(10);
--inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest(LOGICAL,47)@0
inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a <= expGT0_uid44_asinX_uid8_fpArcsinPiTest_c;
inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b <= exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q;
inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q <= inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a or inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b;
--InvExc_N_uid39_asinX_uid8_fpArcsinPiTest(LOGICAL,38)@0
InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_q;
InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q <= not InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a;
--InvExc_I_uid40_asinX_uid8_fpArcsinPiTest(LOGICAL,39)@0
InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_q;
InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q <= not InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a;
--cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest(CONSTANT,20)
cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q <= "00000000";
--expXIsZero_uid31_asinX_uid8_fpArcsinPiTest(LOGICAL,30)@0
expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b;
expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a = expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b else "0";
--InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest(LOGICAL,40)@0
InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q;
InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q <= not InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a;
--exc_R_uid42_asinX_uid8_fpArcsinPiTest(LOGICAL,41)@0
exc_R_uid42_asinX_uid8_fpArcsinPiTest_a <= InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q;
exc_R_uid42_asinX_uid8_fpArcsinPiTest_b <= InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q;
exc_R_uid42_asinX_uid8_fpArcsinPiTest_c <= InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q;
exc_R_uid42_asinX_uid8_fpArcsinPiTest_q <= exc_R_uid42_asinX_uid8_fpArcsinPiTest_a and exc_R_uid42_asinX_uid8_fpArcsinPiTest_b and exc_R_uid42_asinX_uid8_fpArcsinPiTest_c;
--xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest(LOGICAL,117)@0
xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a <= exc_R_uid42_asinX_uid8_fpArcsinPiTest_q;
xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b <= inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q;
xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q <= xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a and xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b;
--cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest(CONSTANT,17)
cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q <= "11111111";
--expXIsMax_uid33_asinX_uid8_fpArcsinPiTest(LOGICAL,32)@0
expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b;
expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a = expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b else "0";
--exc_I_uid36_asinX_uid8_fpArcsinPiTest(LOGICAL,35)@0
exc_I_uid36_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q;
exc_I_uid36_asinX_uid8_fpArcsinPiTest_b <= fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q;
exc_I_uid36_asinX_uid8_fpArcsinPiTest_q <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_a and exc_I_uid36_asinX_uid8_fpArcsinPiTest_b;
--exc_N_uid38_asinX_uid8_fpArcsinPiTest(LOGICAL,37)@0
exc_N_uid38_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q;
exc_N_uid38_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q;
exc_N_uid38_asinX_uid8_fpArcsinPiTest_q <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_a and exc_N_uid38_asinX_uid8_fpArcsinPiTest_b;
--excRNaN_uid119_asinX_uid8_fpArcsinPiTest(LOGICAL,118)@0
excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_q;
excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_q;
excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c <= xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q;
excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a or excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b or excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c;
--InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest(LOGICAL,123)@0
InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a <= excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q;
InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q <= not InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a;
END IF;
END PROCESS;
--singX_uid17_asinX_uid8_fpArcsinPiTest(BITSELECT,16)@0
singX_uid17_asinX_uid8_fpArcsinPiTest_in <= a;
singX_uid17_asinX_uid8_fpArcsinPiTest_b <= singX_uid17_asinX_uid8_fpArcsinPiTest_in(31 downto 31);
--reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1(REG,512)@0
reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q <= singX_uid17_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--signR_uid125_asinX_uid8_fpArcsinPiTest(LOGICAL,124)@1
signR_uid125_asinX_uid8_fpArcsinPiTest_a <= reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q;
signR_uid125_asinX_uid8_fpArcsinPiTest_b <= InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q;
signR_uid125_asinX_uid8_fpArcsinPiTest_q <= signR_uid125_asinX_uid8_fpArcsinPiTest_a and signR_uid125_asinX_uid8_fpArcsinPiTest_b;
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt(COUNTER,1078)
-- every=1, low=0, high=30, step=1, init=1
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i = 29 THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i - 30;
ELSE
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i,5));
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg(REG,1079)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux(MUX,1080)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s <= en;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux: PROCESS (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s, ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q, ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem(DUALMEM,1153)
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia <= signR_uid125_asinX_uid8_fpArcsinPiTest_q;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q;
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 31,
width_b => 1,
widthad_b => 5,
numwords_b => 31,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq,
address_a => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa,
data_a => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia
);
ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq(0 downto 0);
--cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest(CONSTANT,22)
cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q <= "01111110";
--RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,393)@19
RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 1);
--rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,395)@19
rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= GND_q & RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
--rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(CONSTANT,389)
rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(CONSTANT,378)
rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= "000000000000000000000000";
--X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,377)@18
X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q;
X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 24);
--rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,379)@18
rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q & X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
--zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,275)
zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "0000000000000000";
--X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,374)@18
X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q;
X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 16);
--rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,376)@18
rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
--X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,371)@18
X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q;
X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 8);
--rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,373)@18
rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q & X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
--maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,311)
maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "100011";
--zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,268)
zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000000000000000";
--X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,236)@0
X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(24 downto 0);
X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,235)
leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,237)@0
leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
--X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,233)@0
X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(28 downto 0);
X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,234)@0
leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
--X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,230)@0
X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(32 downto 0);
X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,229)
leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "0000";
--leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,231)@0
leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
--cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest(CONSTANT,53)
cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q <= "0000000000000";
--oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest(BITJOIN,48)@0
oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q <= VCC_q & fracX_uid16_asinX_uid8_fpArcsinPiTest_b;
--oFracXExt_uid55_asinX_uid8_fpArcsinPiTest(BITJOIN,54)@0
oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q <= cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q & oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q;
--shiftBias_uid52_asinX_uid8_fpArcsinPiTest(CONSTANT,51)
shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q <= "01110010";
--shiftValue_uid53_asinX_uid8_fpArcsinPiTest(SUB,52)@0
shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid15_asinX_uid8_fpArcsinPiTest_b);
shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q);
shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b));
shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q <= shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o(8 downto 0);
--fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest(BITSELECT,55)@0
fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in <= shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q(3 downto 0);
fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,238)@0
leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b;
leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(3 downto 2);
--leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest(MUX,239)@0
leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s <= leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b;
leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest: PROCESS (leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s, en, oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
WHEN "10" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,247)@0
LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(33 downto 0);
--leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,246)
leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "000";
--leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,248)@0
leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
--reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5(REG,463)@0
reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q <= leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,244)@0
LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(34 downto 0);
--leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,245)@0
leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & z2_uid93_asinX_uid8_fpArcsinPiTest_q;
--reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4(REG,462)@0
reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q <= leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,241)@0
LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(35 downto 0);
--leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,242)@0
leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & GND_q;
--reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3(REG,461)@0
reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q <= leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2(REG,460)@0
reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,249)@0
leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1(REG,459)@0
reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q <= leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest(MUX,250)@1
leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s <= reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q;
leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest: PROCESS (leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s, en, reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q, reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q, reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q, reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q;
WHEN "10" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q;
WHEN "11" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid59_asinX_uid8_fpArcsinPiTest(BITSELECT,58)@1
y_uid59_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(35 downto 0);
y_uid59_asinX_uid8_fpArcsinPiTest_b <= y_uid59_asinX_uid8_fpArcsinPiTest_in(35 downto 1);
--pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest(BITJOIN,77)@1
pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--oMy_uid78_asinX_uid8_fpArcsinPiTest(SUB,78)@1
oMy_uid78_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q);
oMy_uid78_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & y_uid59_asinX_uid8_fpArcsinPiTest_b);
oMy_uid78_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid78_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(oMy_uid78_asinX_uid8_fpArcsinPiTest_b));
oMy_uid78_asinX_uid8_fpArcsinPiTest_q <= oMy_uid78_asinX_uid8_fpArcsinPiTest_o(36 downto 0);
--l_uid80_asinX_uid8_fpArcsinPiTest(BITSELECT,79)@1
l_uid80_asinX_uid8_fpArcsinPiTest_in <= oMy_uid78_asinX_uid8_fpArcsinPiTest_q(34 downto 0);
l_uid80_asinX_uid8_fpArcsinPiTest_b <= l_uid80_asinX_uid8_fpArcsinPiTest_in(34 downto 0);
--rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,269)@1
rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= l_uid80_asinX_uid8_fpArcsinPiTest_b;
rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 3);
--reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,473)@1
reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,270)@2
vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q;
vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0";
--ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f(DELAY,842)@2
ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,272)@1
vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= l_uid80_asinX_uid8_fpArcsinPiTest_b(2 downto 0);
vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(2 downto 0);
--cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,273)@1
cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
--reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,475)@1
reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,474)@1
reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= l_uid80_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,274)@2
vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q)
BEGIN
CASE vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q;
WHEN "1" => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q;
WHEN OTHERS => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,276)@2
rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 19);
--reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,476)@2
reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,277)@3
vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q;
vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0";
--ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e(DELAY,841)@3
ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,279)@2
vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(18 downto 0);
vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(18 downto 0);
--cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,280)@2
cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
--reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,478)@2
reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,477)@2
reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,281)@3
vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q)
BEGIN
CASE vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q;
WHEN "1" => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q;
WHEN OTHERS => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,283)@3
rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 27);
--vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,284)@3
vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b;
vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0";
--reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,482)@3
reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,286)@3
vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(26 downto 0);
vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(26 downto 0);
--cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,287)@3
cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
--vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,288)@3
vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
WHEN "1" => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,290)@3
rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 31);
--reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,479)@3
reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,291)@4
vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q;
vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0";
--vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,293)@3
vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(30 downto 0);
vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(30 downto 0);
--cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,294)@3
cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
--reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,481)@3
reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,480)@3
reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,295)@4
vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q)
BEGIN
CASE vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q;
WHEN "1" => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q;
WHEN OTHERS => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,297)@4
rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 33);
--vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,298)@4
vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b;
vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= z2_uid93_asinX_uid8_fpArcsinPiTest_q;
vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0";
--vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,300)@4
vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(32 downto 0);
vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(32 downto 0);
--cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,301)@4
cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & z2_uid93_asinX_uid8_fpArcsinPiTest_q;
--vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,302)@4
vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
WHEN "1" => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,304)@4
rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 34);
--vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,305)@4
vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b;
vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= GND_q;
vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0";
--vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,310)@4
vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q & ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q & reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q & vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
--ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c(DELAY,845)@4
ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,483)@4
reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(COMPARE,312)@5
vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin <= GND_q;
vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) & '0';
vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q) & vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin(0);
vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b));
vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c(0) <= vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o(8);
--vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,314)@5
vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c;
vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q;
WHEN "1" => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid6_fpArcsinPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArcsinPiTest_q <= "01111101";
--expL_uid82_asinX_uid8_fpArcsinPiTest(SUB,81)@6
expL_uid82_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid6_fpArcsinPiTest_q);
expL_uid82_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q);
expL_uid82_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid82_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(expL_uid82_asinX_uid8_fpArcsinPiTest_b));
expL_uid82_asinX_uid8_fpArcsinPiTest_q <= expL_uid82_asinX_uid8_fpArcsinPiTest_o(8 downto 0);
--expLRange_uid84_asinX_uid8_fpArcsinPiTest(BITSELECT,83)@6
expLRange_uid84_asinX_uid8_fpArcsinPiTest_in <= expL_uid82_asinX_uid8_fpArcsinPiTest_q(7 downto 0);
expLRange_uid84_asinX_uid8_fpArcsinPiTest_b <= expLRange_uid84_asinX_uid8_fpArcsinPiTest_in(7 downto 0);
--vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,307)@4
vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(33 downto 0);
vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(33 downto 0);
--cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,308)@4
cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & GND_q;
--vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,309)@4
vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
WHEN "1" => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest(BITSELECT,82)@4
fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(33 downto 0);
fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b <= fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in(33 downto 11);
--reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0(REG,484)@4
reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q <= fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a(DELAY,581)@5
ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q, xout => ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--fpL_uid85_asinX_uid8_fpArcsinPiTest(BITJOIN,84)@6
fpL_uid85_asinX_uid8_fpArcsinPiTest_q <= GND_q & expLRange_uid84_asinX_uid8_fpArcsinPiTest_b & ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q;
--signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,319)@6
signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q;
signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(31 downto 31);
--expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,317)@6
expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q(30 downto 0);
expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(30 downto 23);
--expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,324)@6
expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b else "0";
--negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,367)@6
negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
END IF;
END PROCESS;
--ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c(DELAY,901)@7
ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor(LOGICAL,1176)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q <= not (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a or ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b);
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top(CONSTANT,1172)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp(LOGICAL,1173)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a = ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg(REG,1174)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena(REG,1177)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd(LOGICAL,1178)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a and ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b;
--reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0(REG,494)@6
reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(ADD,340)@7
expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q);
expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q);
expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b));
expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o(8 downto 0);
--expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,341)@7
expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(8 downto 1);
--expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(ADD,337)@7
expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q);
expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid22_asinX_uid8_fpArcsinPiTest_q);
expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b));
expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o(8 downto 0);
--expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,338)@7
expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(8 downto 1);
--expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,342)@6
expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(0 downto 0);
expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(0 downto 0);
--expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,343)@6
expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a;
--ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(DELAY,869)@6
ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,344)@7
expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q;
expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
WHEN "1" => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
WHEN OTHERS => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,877)@6
ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,332)@7
InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a;
--fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,318)@6
fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q(22 downto 0);
fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(22 downto 0);
--reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1(REG,485)@6
reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,328)@7
fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q;
fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1" when fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b else "0";
--expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,326)@6
expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b) THEN
expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1";
ELSE
expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,329)@7
exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
--InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,333)@7
InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a;
--InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,334)@6
InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a;
END IF;
END PROCESS;
--exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,335)@7
exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c <= InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b and exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c;
--minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,353)@7
minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q;
minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
--minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,354)@7
minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q;
minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
--InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,330)@7
InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a;
--exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,331)@7
exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
--excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,355)@7
excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c <= minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a or excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b or excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c;
--InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,351)@7
InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q;
InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a;
--inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,352)@7
inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
--ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,887)@6
ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,356)@7
join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q;
--fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,357)@7
fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q & join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
--reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0(REG,486)@7
reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOOKUP,358)@8
fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q) IS
WHEN "0000" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "0001" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "0010" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "10";
WHEN "0011" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "0100" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "0101" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "0110" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "10";
WHEN "0111" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "1000" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "1001" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "1010" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "1011" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "1100" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "1101" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "1110" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "1111" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN OTHERS =>
fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,362)@8
expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
WHEN "10" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg(DELAY,1166)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt(COUNTER,1168)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg(REG,1169)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux(MUX,1170)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s, ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q, ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem(DUALMEM,1167)
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest(CONSTANT,19)
cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000001";
--fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,346)@6
fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(22 downto 16);
--addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,347)@6
addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
--reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0(REG,487)@6
reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q <= addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid424_sqrtTableGenerator_lutmem(DUALMEM,457)@7
memoryC2_uid424_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid424_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid424_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid424_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid424_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC2_uid424_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid424_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid424_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid424_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid424_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid424_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid424_sqrtTableGenerator_lutmem_q <= memoryC2_uid424_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1(REG,489)@9
reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q <= memoryC2_uid424_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1165)
ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,875)@6
ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q, xout => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,348)@9
FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q(15 downto 0);
FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(15 downto 0);
--yT1_uid425_sqrtPolynomialEvaluator(BITSELECT,424)@9
yT1_uid425_sqrtPolynomialEvaluator_in <= FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
yT1_uid425_sqrtPolynomialEvaluator_b <= yT1_uid425_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0(REG,488)@9
reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q <= yT1_uid425_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator(MULT,443)@10
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b);
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a <= reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q;
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q;
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q <= prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator(BITSELECT,444)@13
prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in <= prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid428_sqrtPolynomialEvaluator(BITSELECT,427)@13
highBBits_uid428_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b;
highBBits_uid428_sqrtPolynomialEvaluator_b <= highBBits_uid428_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a(DELAY,983)@7
ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1217)
ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q, xout => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid423_sqrtTableGenerator_lutmem(DUALMEM,456)@11
memoryC1_uid423_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid423_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid423_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid423_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC1_uid423_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC1_uid423_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid423_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid423_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid423_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid423_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid423_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid423_sqrtTableGenerator_lutmem_q <= memoryC1_uid423_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid429_sqrtPolynomialEvaluator(ADD,428)@13
sumAHighB_uid429_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid423_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid423_sqrtTableGenerator_lutmem_q);
sumAHighB_uid429_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid428_sqrtPolynomialEvaluator_b(11)) & highBBits_uid428_sqrtPolynomialEvaluator_b);
sumAHighB_uid429_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid429_sqrtPolynomialEvaluator_b));
sumAHighB_uid429_sqrtPolynomialEvaluator_q <= sumAHighB_uid429_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid427_sqrtPolynomialEvaluator(BITSELECT,426)@13
lowRangeB_uid427_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid427_sqrtPolynomialEvaluator_b <= lowRangeB_uid427_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid427_uid430_sqrtPolynomialEvaluator(BITJOIN,429)@13
s1_uid427_uid430_sqrtPolynomialEvaluator_q <= sumAHighB_uid429_sqrtPolynomialEvaluator_q & lowRangeB_uid427_sqrtPolynomialEvaluator_b;
--reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1(REG,492)@13
reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q <= s1_uid427_uid430_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,1240)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a or ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b);
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg(REG,1238)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,1241)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,1242)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b;
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,1232)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,1234)
-- every=1, low=0, high=1, step=1, init=1
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,1));
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,1235)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,1236)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS
WHEN "0" => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
WHEN "1" => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,1233)
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q;
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq,
address_a => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa,
data_a => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia
);
ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq(15 downto 0);
--reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0(REG,491)@13
reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator(MULT,446)@14
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b);
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a <= reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q;
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b <= reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q;
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q <= prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator(BITSELECT,447)@17
prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in <= prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid434_sqrtPolynomialEvaluator(BITSELECT,433)@17
highBBits_uid434_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b;
highBBits_uid434_sqrtPolynomialEvaluator_b <= highBBits_uid434_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,1253)
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top(CONSTANT,1184)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q <= "0101";
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp(LOGICAL,1185)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg(REG,1186)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,1254)
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1255)
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1243)
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt(COUNTER,1180)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i = 4 THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i - 5;
ELSE
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg(REG,1181)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux(MUX,1182)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1244)
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q;
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0(REG,493)@14
reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid422_sqrtTableGenerator_lutmem(DUALMEM,455)@15
memoryC0_uid422_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid422_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid422_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid422_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid422_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC0_uid422_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid422_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid422_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid422_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid422_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid422_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid422_sqrtTableGenerator_lutmem_q <= memoryC0_uid422_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid435_sqrtPolynomialEvaluator(ADD,434)@17
sumAHighB_uid435_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid422_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid422_sqrtTableGenerator_lutmem_q);
sumAHighB_uid435_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid434_sqrtPolynomialEvaluator_b(21)) & highBBits_uid434_sqrtPolynomialEvaluator_b);
sumAHighB_uid435_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid435_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid435_sqrtPolynomialEvaluator_b));
sumAHighB_uid435_sqrtPolynomialEvaluator_q <= sumAHighB_uid435_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid433_sqrtPolynomialEvaluator(BITSELECT,432)@17
lowRangeB_uid433_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid433_sqrtPolynomialEvaluator_b <= lowRangeB_uid433_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid433_uid436_sqrtPolynomialEvaluator(BITJOIN,435)@17
s2_uid433_uid436_sqrtPolynomialEvaluator_q <= sumAHighB_uid435_sqrtPolynomialEvaluator_q & lowRangeB_uid433_sqrtPolynomialEvaluator_b;
--fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,350)@17
fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= s2_uid433_uid436_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(28 downto 6);
--ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(DELAY,895)@8
ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,366)@17
fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q;
fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b;
WHEN "10" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,368)@17
RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q & ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q & fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q;
--SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest(BITSELECT,89)@17
SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in <= RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q(22 downto 0);
SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b <= SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in(22 downto 0);
--ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a(DELAY,586)@17
ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b, xout => ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest(BITJOIN,90)@18
oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q <= VCC_q & ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q;
--z2_uid93_asinX_uid8_fpArcsinPiTest(CONSTANT,92)
z2_uid93_asinX_uid8_fpArcsinPiTest_q <= "00";
--oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest(BITJOIN,93)@18
oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q <= oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q & z2_uid93_asinX_uid8_fpArcsinPiTest_q;
--SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest(BITSELECT,87)@17
SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in <= RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q(30 downto 0);
SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b <= SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1(REG,496)@17
reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q <= SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--srVal_uid89_asinX_uid8_fpArcsinPiTest(SUB,88)@18
srVal_uid89_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q);
srVal_uid89_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q);
srVal_uid89_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid89_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(srVal_uid89_asinX_uid8_fpArcsinPiTest_b));
srVal_uid89_asinX_uid8_fpArcsinPiTest_q <= srVal_uid89_asinX_uid8_fpArcsinPiTest_o(8 downto 0);
--srValRange_uid92_asinX_uid8_fpArcsinPiTest(BITSELECT,91)@18
srValRange_uid92_asinX_uid8_fpArcsinPiTest_in <= srVal_uid89_asinX_uid8_fpArcsinPiTest_q(4 downto 0);
srValRange_uid92_asinX_uid8_fpArcsinPiTest_b <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,380)@18
rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b;
rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(4 downto 3);
--rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,381)@18
rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
WHEN "10" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,388)@18
RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 6);
--rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,390)@18
rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
--reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5(REG,501)@18
reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q <= rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,385)@18
RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 4);
--rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,387)@18
rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
--reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4(REG,500)@18
reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q <= rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,382)@18
RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 2);
--rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,384)@18
rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= z2_uid93_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
--reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3(REG,499)@18
reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q <= rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2(REG,498)@18
reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,391)@18
rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1(REG,497)@18
reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,392)@19
rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q;
rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q, reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q, reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q, reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q)
BEGIN
CASE rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q;
WHEN "01" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q;
WHEN "10" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q;
WHEN "11" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q;
WHEN OTHERS => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,396)@18
rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1(REG,502)@18
reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,397)@19
rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q;
rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
WHEN "1" => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--mAddr_uid97_asinX_uid8_fpArcsinPiTest(BITSELECT,96)@19
mAddr_uid97_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q;
mAddr_uid97_asinX_uid8_fpArcsinPiTest_b <= mAddr_uid97_asinX_uid8_fpArcsinPiTest_in(25 downto 18);
--reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0(REG,503)@19
reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q <= mAddr_uid97_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid402_arcsinXTabGen_lutmem(DUALMEM,454)@20
memoryC2_uid402_arcsinXTabGen_lutmem_reset0 <= areset;
memoryC2_uid402_arcsinXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid402_arcsinXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid402_arcsinXTabGen_lutmem_ab <= reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q;
memoryC2_uid402_arcsinXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC2_uid402_arcsinXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid402_arcsinXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid402_arcsinXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid402_arcsinXTabGen_lutmem_iq,
address_a => memoryC2_uid402_arcsinXTabGen_lutmem_aa,
data_a => memoryC2_uid402_arcsinXTabGen_lutmem_ia
);
memoryC2_uid402_arcsinXTabGen_lutmem_q <= memoryC2_uid402_arcsinXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1(REG,505)@22
reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q <= memoryC2_uid402_arcsinXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1063)
ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, xout => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a(DELAY,590)@19
ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 26, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q, xout => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest(BITSELECT,97)@22
mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in <= ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q(17 downto 0);
mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in(17 downto 1);
--yT1_uid403_arcsinXPolyEval(BITSELECT,402)@22
yT1_uid403_arcsinXPolyEval_in <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b;
yT1_uid403_arcsinXPolyEval_b <= yT1_uid403_arcsinXPolyEval_in(16 downto 4);
--reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0(REG,504)@22
reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q <= yT1_uid403_arcsinXPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid438_pT1_uid404_arcsinXPolyEval(MULT,437)@23
prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid438_pT1_uid404_arcsinXPolyEval_a),14)) * SIGNED(prodXY_uid438_pT1_uid404_arcsinXPolyEval_b);
prodXY_uid438_pT1_uid404_arcsinXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid438_pT1_uid404_arcsinXPolyEval_a <= (others => '0');
prodXY_uid438_pT1_uid404_arcsinXPolyEval_b <= (others => '0');
prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid438_pT1_uid404_arcsinXPolyEval_a <= reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q;
prodXY_uid438_pT1_uid404_arcsinXPolyEval_b <= reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q;
prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid438_pT1_uid404_arcsinXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid438_pT1_uid404_arcsinXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid438_pT1_uid404_arcsinXPolyEval_q <= prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval(BITSELECT,438)@26
prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in <= prodXY_uid438_pT1_uid404_arcsinXPolyEval_q;
prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in(25 downto 12);
--highBBits_uid406_arcsinXPolyEval(BITSELECT,405)@26
highBBits_uid406_arcsinXPolyEval_in <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b;
highBBits_uid406_arcsinXPolyEval_b <= highBBits_uid406_arcsinXPolyEval_in(13 downto 1);
--ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a(DELAY,980)@20
ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q, xout => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg(DELAY,1216)
ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q, xout => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid401_arcsinXTabGen_lutmem(DUALMEM,453)@24
memoryC1_uid401_arcsinXTabGen_lutmem_reset0 <= areset;
memoryC1_uid401_arcsinXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid401_arcsinXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid401_arcsinXTabGen_lutmem_ab <= ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q;
memoryC1_uid401_arcsinXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 8,
numwords_a => 256,
width_b => 23,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC1_uid401_arcsinXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid401_arcsinXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid401_arcsinXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid401_arcsinXTabGen_lutmem_iq,
address_a => memoryC1_uid401_arcsinXTabGen_lutmem_aa,
data_a => memoryC1_uid401_arcsinXTabGen_lutmem_ia
);
memoryC1_uid401_arcsinXTabGen_lutmem_q <= memoryC1_uid401_arcsinXTabGen_lutmem_iq(22 downto 0);
--sumAHighB_uid407_arcsinXPolyEval(ADD,406)@26
sumAHighB_uid407_arcsinXPolyEval_a <= STD_LOGIC_VECTOR((23 downto 23 => memoryC1_uid401_arcsinXTabGen_lutmem_q(22)) & memoryC1_uid401_arcsinXTabGen_lutmem_q);
sumAHighB_uid407_arcsinXPolyEval_b <= STD_LOGIC_VECTOR((23 downto 13 => highBBits_uid406_arcsinXPolyEval_b(12)) & highBBits_uid406_arcsinXPolyEval_b);
sumAHighB_uid407_arcsinXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid407_arcsinXPolyEval_a) + SIGNED(sumAHighB_uid407_arcsinXPolyEval_b));
sumAHighB_uid407_arcsinXPolyEval_q <= sumAHighB_uid407_arcsinXPolyEval_o(23 downto 0);
--lowRangeB_uid405_arcsinXPolyEval(BITSELECT,404)@26
lowRangeB_uid405_arcsinXPolyEval_in <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b(0 downto 0);
lowRangeB_uid405_arcsinXPolyEval_b <= lowRangeB_uid405_arcsinXPolyEval_in(0 downto 0);
--s1_uid405_uid408_arcsinXPolyEval(BITJOIN,407)@26
s1_uid405_uid408_arcsinXPolyEval_q <= sumAHighB_uid407_arcsinXPolyEval_q & lowRangeB_uid405_arcsinXPolyEval_b;
--reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1(REG,508)@26
reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q <= s1_uid405_uid408_arcsinXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor(LOGICAL,1200)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q <= not (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a or ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b);
--roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest(CONSTANT,185)
roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q <= "010";
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp(LOGICAL,1197)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a <= roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q);
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q <= "1" when ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a = ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b else "0";
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg(REG,1198)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena(REG,1201)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q = "1") THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd(LOGICAL,1202)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b <= en;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a and ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b;
--reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0(REG,507)@22
reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt(COUNTER,1192)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i,2));
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg(REG,1193)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux(MUX,1194)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s <= en;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux: PROCESS (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s, ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q, ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem(DUALMEM,1191)
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia <= reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q;
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 2,
numwords_a => 3,
width_b => 17,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq,
address_a => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa,
data_a => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia
);
ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq(16 downto 0);
--prodXY_uid441_pT2_uid410_arcsinXPolyEval(MULT,440)@27
prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid441_pT2_uid410_arcsinXPolyEval_a),18)) * SIGNED(prodXY_uid441_pT2_uid410_arcsinXPolyEval_b);
prodXY_uid441_pT2_uid410_arcsinXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid441_pT2_uid410_arcsinXPolyEval_a <= (others => '0');
prodXY_uid441_pT2_uid410_arcsinXPolyEval_b <= (others => '0');
prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid441_pT2_uid410_arcsinXPolyEval_a <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q;
prodXY_uid441_pT2_uid410_arcsinXPolyEval_b <= reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q;
prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr,42));
END IF;
END IF;
END PROCESS;
prodXY_uid441_pT2_uid410_arcsinXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid441_pT2_uid410_arcsinXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid441_pT2_uid410_arcsinXPolyEval_q <= prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval(BITSELECT,441)@30
prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in <= prodXY_uid441_pT2_uid410_arcsinXPolyEval_q;
prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in(41 downto 16);
--highBBits_uid412_arcsinXPolyEval(BITSELECT,411)@30
highBBits_uid412_arcsinXPolyEval_in <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b;
highBBits_uid412_arcsinXPolyEval_b <= highBBits_uid412_arcsinXPolyEval_in(25 downto 2);
--ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor(LOGICAL,1266)
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a or ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b);
--ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena(REG,1267)
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd(LOGICAL,1268)
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b;
--ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg(DELAY,1256)
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid97_asinX_uid8_fpArcsinPiTest_b, xout => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem(DUALMEM,1257)
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q;
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia
);
ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0(REG,509)@27
reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_arcsinXTabGen_lutmem(DUALMEM,452)@28
memoryC0_uid400_arcsinXTabGen_lutmem_reset0 <= areset;
memoryC0_uid400_arcsinXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid400_arcsinXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid400_arcsinXTabGen_lutmem_ab <= reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q;
memoryC0_uid400_arcsinXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC0_uid400_arcsinXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_arcsinXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_arcsinXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_arcsinXTabGen_lutmem_iq,
address_a => memoryC0_uid400_arcsinXTabGen_lutmem_aa,
data_a => memoryC0_uid400_arcsinXTabGen_lutmem_ia
);
memoryC0_uid400_arcsinXTabGen_lutmem_q <= memoryC0_uid400_arcsinXTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid413_arcsinXPolyEval(ADD,412)@30
sumAHighB_uid413_arcsinXPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid400_arcsinXTabGen_lutmem_q(29)) & memoryC0_uid400_arcsinXTabGen_lutmem_q);
sumAHighB_uid413_arcsinXPolyEval_b <= STD_LOGIC_VECTOR((30 downto 24 => highBBits_uid412_arcsinXPolyEval_b(23)) & highBBits_uid412_arcsinXPolyEval_b);
sumAHighB_uid413_arcsinXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid413_arcsinXPolyEval_a) + SIGNED(sumAHighB_uid413_arcsinXPolyEval_b));
sumAHighB_uid413_arcsinXPolyEval_q <= sumAHighB_uid413_arcsinXPolyEval_o(30 downto 0);
--lowRangeB_uid411_arcsinXPolyEval(BITSELECT,410)@30
lowRangeB_uid411_arcsinXPolyEval_in <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b(1 downto 0);
lowRangeB_uid411_arcsinXPolyEval_b <= lowRangeB_uid411_arcsinXPolyEval_in(1 downto 0);
--s2_uid411_uid414_arcsinXPolyEval(BITJOIN,413)@30
s2_uid411_uid414_arcsinXPolyEval_q <= sumAHighB_uid413_arcsinXPolyEval_q & lowRangeB_uid411_arcsinXPolyEval_b;
--fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest(BITSELECT,99)@30
fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in <= s2_uid411_uid414_arcsinXPolyEval_q(30 downto 0);
fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b <= fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in(30 downto 3);
--reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1(REG,510)@30
reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q <= fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--piO2_uid101_asinX_uid8_fpArcsinPiTest(CONSTANT,100)
piO2_uid101_asinX_uid8_fpArcsinPiTest_q <= "1100100100001111110110101010";
--path3Diff_uid102_asinX_uid8_fpArcsinPiTest(SUB,101)@31
path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid101_asinX_uid8_fpArcsinPiTest_q);
path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q);
path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b));
path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o(28 downto 0);
--normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest(BITSELECT,102)@31
normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(27 downto 0);
normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in(27 downto 27);
--expRPath3_uid107_asinX_uid8_fpArcsinPiTest(MUX,106)@31
expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b;
expRPath3_uid107_asinX_uid8_fpArcsinPiTest: PROCESS (expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s, en, cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q, cstBias_uid22_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q;
WHEN "1" => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest(BITSELECT,103)@31
path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(26 downto 0);
path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b <= path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in(26 downto 3);
--path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest(BITSELECT,104)@31
path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(25 downto 0);
path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b <= path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in(25 downto 2);
--fracRPath3_uid106_asinX_uid8_fpArcsinPiTest(MUX,105)@31
fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b;
fracRPath3_uid106_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s, en, path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b, path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b)
BEGIN
CASE fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b;
WHEN "1" => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b;
WHEN OTHERS => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest(BITJOIN,107)@31
expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q <= expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q & fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q;
--reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0(REG,511)@31
reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q <= expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest(ADD,108)@32
expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q);
expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b));
expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o(32 downto 0);
--expRPath3_uid111_asinX_uid8_fpArcsinPiTest(BITSELECT,110)@32
expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q(31 downto 0);
expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b <= expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in(31 downto 24);
--ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor(LOGICAL,1124)
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q <= not (ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a or ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b);
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top(CONSTANT,1056)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q <= "01101";
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp(LOGICAL,1057)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q);
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q <= "1" when ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a = ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b else "0";
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg(REG,1058)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena(REG,1125)
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q = "1") THEN
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd(LOGICAL,1126)
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b <= en;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a and ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b;
--yAddr_uid63_asinX_uid8_fpArcsinPiTest(BITSELECT,62)@1
yAddr_uid63_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b;
yAddr_uid63_asinX_uid8_fpArcsinPiTest_b <= yAddr_uid63_asinX_uid8_fpArcsinPiTest_in(34 downto 27);
--reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0(REG,464)@1
reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q <= yAddr_uid63_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid255_arcsinXO2XTabGen_lutmem(DUALMEM,451)@2
memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid255_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC2_uid255_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid255_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1(REG,466)@4
reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q <= memoryC2_uid255_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest(BITSELECT,63)@1
yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b(26 downto 0);
yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in(26 downto 9);
--yT1_uid256_arcsinXO2XPolyEval(BITSELECT,255)@1
yT1_uid256_arcsinXO2XPolyEval_in <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b;
yT1_uid256_arcsinXO2XPolyEval_b <= yT1_uid256_arcsinXO2XPolyEval_in(17 downto 6);
--ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1218)
ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid256_arcsinXO2XPolyEval_b, xout => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a(DELAY,992)@1
ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q, xout => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0(REG,465)@4
reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q <= ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval(MULT,415)@5
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b);
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a <= reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q;
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b <= reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q;
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q <= prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval(BITSELECT,416)@8
prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in <= prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid259_arcsinXO2XPolyEval(BITSELECT,258)@8
highBBits_uid259_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b;
highBBits_uid259_arcsinXO2XPolyEval_b <= highBBits_uid259_arcsinXO2XPolyEval_in(12 downto 1);
--ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1219)
ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid63_asinX_uid8_fpArcsinPiTest_b, xout => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a(DELAY,994)@1
ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, xout => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0(REG,467)@5
reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q <= ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid254_arcsinXO2XTabGen_lutmem(DUALMEM,450)@6
memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q;
memoryC1_uid254_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC1_uid254_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid254_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid260_arcsinXO2XPolyEval(ADD,259)@8
sumAHighB_uid260_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid254_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid254_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid260_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid259_arcsinXO2XPolyEval_b(11)) & highBBits_uid259_arcsinXO2XPolyEval_b);
sumAHighB_uid260_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid260_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid260_arcsinXO2XPolyEval_b));
sumAHighB_uid260_arcsinXO2XPolyEval_q <= sumAHighB_uid260_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid258_arcsinXO2XPolyEval(BITSELECT,257)@8
lowRangeB_uid258_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid258_arcsinXO2XPolyEval_b <= lowRangeB_uid258_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid258_uid261_arcsinXO2XPolyEval(BITJOIN,260)@8
s1_uid258_uid261_arcsinXO2XPolyEval_q <= sumAHighB_uid260_arcsinXO2XPolyEval_q & lowRangeB_uid258_arcsinXO2XPolyEval_b;
--reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1(REG,469)@8
reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q <= s1_uid258_uid261_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor(LOGICAL,1188)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a or ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena(REG,1189)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd(LOGICAL,1190)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0(REG,468)@1
reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem(DUALMEM,1179)
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia <= reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 6,
width_b => 18,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval(MULT,418)@9
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a),19)) * SIGNED(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b);
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q;
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b <= reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q;
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q <= prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval(BITSELECT,419)@12
prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in <= prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in(38 downto 17);
--highBBits_uid265_arcsinXO2XPolyEval(BITSELECT,264)@12
highBBits_uid265_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b;
highBBits_uid265_arcsinXO2XPolyEval_b <= highBBits_uid265_arcsinXO2XPolyEval_in(21 downto 2);
--ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor(LOGICAL,1213)
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b);
--ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena(REG,1214)
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd(LOGICAL,1215)
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem(DUALMEM,1204)
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1203)
ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q, xout => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid253_arcsinXO2XTabGen_lutmem(DUALMEM,449)@10
memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q;
memoryC0_uid253_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arcsinpi_s5_memoryC0_uid253_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid253_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid266_arcsinXO2XPolyEval(ADD,265)@12
sumAHighB_uid266_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid253_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid253_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid266_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid265_arcsinXO2XPolyEval_b(19)) & highBBits_uid265_arcsinXO2XPolyEval_b);
sumAHighB_uid266_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid266_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid266_arcsinXO2XPolyEval_b));
sumAHighB_uid266_arcsinXO2XPolyEval_q <= sumAHighB_uid266_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid264_arcsinXO2XPolyEval(BITSELECT,263)@12
lowRangeB_uid264_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid264_arcsinXO2XPolyEval_b <= lowRangeB_uid264_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid264_uid267_arcsinXO2XPolyEval(BITJOIN,266)@12
s2_uid264_uid267_arcsinXO2XPolyEval_q <= sumAHighB_uid266_arcsinXO2XPolyEval_q & lowRangeB_uid264_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest(BITSELECT,65)@12
fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in <= s2_uid264_uid267_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b <= fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in(30 downto 5);
--reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1(REG,472)@12
reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q <= fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor(LOGICAL,1229)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q <= not (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a or ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b);
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top(CONSTANT,1225)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q <= "01010";
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp(LOGICAL,1226)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q);
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q <= "1" when ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a = ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b else "0";
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg(REG,1227)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena(REG,1230)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q = "1") THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd(LOGICAL,1231)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b <= en;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a and ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b;
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt(COUNTER,1221)
-- every=1, low=0, high=10, step=1, init=1
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i = 9 THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i - 10;
ELSE
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i,4));
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg(REG,1222)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux(MUX,1223)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s <= en;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux: PROCESS (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s, ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q, ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem(DUALMEM,1220)
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0 <= areset;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia <= oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q;
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq,
address_a => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa,
data_a => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia
);
ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq(23 downto 0);
--reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0(REG,471)@12
reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest(MULT,66)@13
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr <= UNSIGNED(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a) * UNSIGNED(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b);
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a <= (others => '0');
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b <= (others => '0');
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a <= reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q;
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b <= reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q;
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 <= STD_LOGIC_VECTOR(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBitPath2_uid68_asinX_uid8_fpArcsinPiTest(BITSELECT,67)@16
normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q;
normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in(49 downto 49);
--add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest(BITJOIN,72)@16
add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b & cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q & VCC_q;
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor(LOGICAL,1060)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q <= not (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a or ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b);
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena(REG,1061)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q = "1") THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd(LOGICAL,1062)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b <= en;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a and ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b;
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem(DUALMEM,1051)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 <= areset;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia <= expX_uid15_asinX_uid8_fpArcsinPiTest_b;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 14,
width_b => 8,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq,
address_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa,
data_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia
);
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq(7 downto 0);
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg(DELAY,1050)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q, xout => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest(BITSELECT,68)@16
fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q(48 downto 0);
fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b <= fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in(48 downto 25);
--fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest(BITSELECT,69)@16
fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q(47 downto 0);
fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b <= fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in(47 downto 24);
--fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest(MUX,70)@16
fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b;
fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s, en, fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b, fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b)
BEGIN
CASE fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s IS
WHEN "0" => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b;
WHEN "1" => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b;
WHEN OTHERS => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest(BITJOIN,73)@16
expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q & fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q;
--expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest(ADD,74)@16
expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q);
expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00000000" & add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q);
expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b));
expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o(32 downto 0);
--expRPath2_uid77_asinX_uid8_fpArcsinPiTest(BITSELECT,76)@16
expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q(31 downto 0);
expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b <= expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in(31 downto 24);
--ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg(DELAY,1114)
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b, xout => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt(COUNTER,1052)
-- every=1, low=0, high=13, step=1, init=1
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i = 12 THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i,4));
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg(REG,1053)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux(MUX,1054)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s <= en;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux: PROCESS (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s, ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q, ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem(DUALMEM,1115)
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 <= areset;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q;
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 14,
width_b => 8,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq,
address_a => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa,
data_a => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia
);
ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq(7 downto 0);
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor(LOGICAL,1111)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q <= not (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a or ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b);
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena(REG,1112)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q = "1") THEN
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd(LOGICAL,1113)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b <= en;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a and ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b;
--ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem(DUALMEM,1102)
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia <= expX_uid15_asinX_uid8_fpArcsinPiTest_b;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q;
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 31,
width_b => 8,
widthad_b => 5,
numwords_b => 31,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq,
address_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa,
data_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia
);
ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq(7 downto 0);
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor(LOGICAL,1074)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q <= not (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a or ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b);
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top(CONSTANT,1070)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q <= "011100";
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp(LOGICAL,1071)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q);
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q <= "1" when ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a = ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b else "0";
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg(REG,1072)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena(REG,1075)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q = "1") THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd(LOGICAL,1076)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b <= en;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a and ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b;
--arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest(BITSELECT,57)@1
arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q;
arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b <= arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in(36 downto 36);
--biasMwShift_uid50_asinX_uid8_fpArcsinPiTest(CONSTANT,49)
biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q <= "01110011";
--arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest(COMPARE,50)@0
arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin <= GND_q;
arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q) & '0';
arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_asinX_uid8_fpArcsinPiTest_b) & arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin(0);
arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b));
END IF;
END IF;
END PROCESS;
arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n(0) <= not arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o(10);
--Y34_uid60_asinX_uid8_fpArcsinPiTest(BITSELECT,59)@1
Y34_uid60_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b;
Y34_uid60_asinX_uid8_fpArcsinPiTest_b <= Y34_uid60_asinX_uid8_fpArcsinPiTest_in(34 downto 34);
--path2_uid61_asinX_uid8_fpArcsinPiTest(LOGICAL,60)@1
path2_uid61_asinX_uid8_fpArcsinPiTest_a <= Y34_uid60_asinX_uid8_fpArcsinPiTest_b;
path2_uid61_asinX_uid8_fpArcsinPiTest_q <= not path2_uid61_asinX_uid8_fpArcsinPiTest_a;
--pathSelBits_uid112_asinX_uid8_fpArcsinPiTest(BITJOIN,111)@1
pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q <= arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b & arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n & path2_uid61_asinX_uid8_fpArcsinPiTest_q;
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1064)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q, xout => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt(COUNTER,1066)
-- every=1, low=0, high=28, step=1, init=1
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i = 27 THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i - 28;
ELSE
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i,5));
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg(REG,1067)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux(MUX,1068)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s, ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q, ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem(DUALMEM,1065)
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q;
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 29,
width_b => 3,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia
);
ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest(LOOKUP,112)@32
fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest: PROCESS (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "001" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "10";
WHEN "010" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "011" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "101" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "111" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN OTHERS =>
fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRCalc_uid117_asinX_uid8_fpArcsinPiTest(MUX,116)@32
expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s <= fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q;
expRCalc_uid117_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q;
WHEN "10" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q;
WHEN "11" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b;
WHEN OTHERS => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor(LOGICAL,1150)
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q <= not (ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a or ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b);
--ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena(REG,1151)
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q = "1") THEN
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd(LOGICAL,1152)
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b <= en;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a and ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b;
--ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg(DELAY,1140)
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q, xout => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem(DUALMEM,1141)
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q;
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia
);
ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor(LOGICAL,1137)
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q <= not (ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a or ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b);
--ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena(REG,1138)
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd(LOGICAL,1139)
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a and ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1127)
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q, xout => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem(DUALMEM,1128)
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q;
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid120_asinX_uid8_fpArcsinPiTest(BITJOIN,119)@31
excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q;
--reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0(REG,458)@31
reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q <= excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest(LOOKUP,120)@32
outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRPostExc_uid123_asinX_uid8_fpArcsinPiTest(MUX,122)@33
expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s <= outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q;
expRPostExc_uid123_asinX_uid8_fpArcsinPiTest: PROCESS (expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q;
WHEN "10" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPath3_uid110_asinX_uid8_fpArcsinPiTest(BITSELECT,109)@32
fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q(23 downto 0);
fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b <= fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in(23 downto 1);
--ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor(LOGICAL,1099)
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q <= not (ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a or ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b);
--ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena(REG,1100)
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q = "1") THEN
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd(LOGICAL,1101)
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b <= en;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a and ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b;
--fracRPath2_uid76_asinX_uid8_fpArcsinPiTest(BITSELECT,75)@16
fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q(23 downto 0);
fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b <= fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in(23 downto 1);
--ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg(DELAY,1089)
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b, xout => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem(DUALMEM,1090)
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 <= areset;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q;
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 14,
width_b => 23,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq,
address_a => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa,
data_a => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia
);
ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq(22 downto 0);
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor(LOGICAL,1086)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q <= not (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a or ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b);
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena(REG,1087)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q = "1") THEN
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd(LOGICAL,1088)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b <= en;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a and ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b;
--ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem(DUALMEM,1077)
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 <= areset;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia <= fracX_uid16_asinX_uid8_fpArcsinPiTest_b;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q;
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 31,
width_b => 23,
widthad_b => 5,
numwords_b => 31,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq,
address_a => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa,
data_a => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia
);
ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq(22 downto 0);
--piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest(BITSELECT,113)@32
piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in <= piO2_uid101_asinX_uid8_fpArcsinPiTest_q(26 downto 0);
piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b <= piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in(26 downto 4);
--fracRCalc_uid115_asinX_uid8_fpArcsinPiTest(MUX,114)@32
fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s <= fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q;
fracRCalc_uid115_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b;
WHEN "01" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q;
WHEN "10" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b;
WHEN OTHERS => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest(MUX,121)@33
fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s <= outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q;
fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s IS
WHEN "00" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q;
WHEN "10" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid126_asinX_uid8_fpArcsinPiTest(BITJOIN,125)@33
R_uid126_asinX_uid8_fpArcsinPiTest_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q & expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q & fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q;
--fracX_uid132_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,131)@33
fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q(22 downto 0);
fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b <= fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 0);
--fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,143)@33
fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a <= fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b;
fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a = fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--expX_uid128_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,127)@33
expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q(30 downto 0);
expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in(30 downto 23);
--expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,141)@33
expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b;
expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a = expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,144)@33
exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q;
exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b <= fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q;
exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a and exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b;
--ooPi_uid9_fpArcsinPiTest(CONSTANT,8)
ooPi_uid9_fpArcsinPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArcsinPiTest(BITSELECT,9)@33
fracOOPi_uid10_fpArcsinPiTest_in <= ooPi_uid9_fpArcsinPiTest_q(22 downto 0);
fracOOPi_uid10_fpArcsinPiTest_b <= fracOOPi_uid10_fpArcsinPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArcsinPiTest(BITJOIN,10)@33
fpOOPi_uid11_fpArcsinPiTest_q <= GND_q & cstBiasM2_uid6_fpArcsinPiTest_q & fracOOPi_uid10_fpArcsinPiTest_b;
--expY_uid129_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,128)@33
expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q(30 downto 0);
expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in(30 downto 23);
--expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,155)@33
expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b;
expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a = expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,209)@33
excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q;
excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q;
excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q <= excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a and excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b;
--fracY_uid134_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,133)@33
fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q(22 downto 0);
fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b <= fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 0);
--fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,159)@33
fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a <= fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b;
fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a = fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,157)@33
expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b;
expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a = expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,160)@33
exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q;
exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b <= fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q;
exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a and exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b;
--expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,139)@33
expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b;
expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a = expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,210)@33
excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q;
excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q;
excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b;
--ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,211)@33
ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a <= excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q;
ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b <= excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q;
ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q <= ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a or ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b;
END IF;
END PROCESS;
--InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,161)@33
InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a <= fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q;
InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q <= not InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a;
--exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,162)@33
exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q;
exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b <= InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q;
exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q <= exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a and exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,742)@33
ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,145)@33
InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a <= fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q;
InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q <= not InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a;
--exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,146)@33
exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q;
exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b <= InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q;
exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a and exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b;
--reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1(REG,519)@33
reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,212)@34
excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a <= reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q;
excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q;
excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c <= ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q;
excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q <= excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a or excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b or excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,224)@34
InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a <= excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q;
InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a;
--signY_uid131_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,130)@33
signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q;
signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b <= signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in(31 downto 31);
--signX_uid130_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,129)@33
signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q;
signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b <= signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in(31 downto 31);
--signR_uid196_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,195)@33
signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a <= signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b;
signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b <= signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b;
signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q <= signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a xor signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,753)@33
ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,225)@34
signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a <= ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q;
signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b <= InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q;
signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q <= signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a and signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,757)@34
ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,134)@33
add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q <= VCC_q & fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b;
--add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,132)@33
add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q <= VCC_q & fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b;
--prod_uid171_rAsinPi_uid13_fpArcsinPiTest(MULT,170)@33
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr <= UNSIGNED(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a) * UNSIGNED(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b);
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a <= (others => '0');
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b <= (others => '0');
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a <= add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q;
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b <= add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q;
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid171_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,171)@36
normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q;
normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in(47 downto 47);
--fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,173)@36
fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(46 downto 0);
fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in(46 downto 23);
--fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,174)@36
fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(45 downto 0);
fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in(45 downto 22);
--fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest(MUX,175)@36
fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b;
fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest: PROCESS (fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s, en, fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b, fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b)
BEGIN
CASE fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s IS
WHEN "0" => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b;
WHEN "1" => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b;
WHEN OTHERS => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,183)@36
FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in <= fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b <= FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in(1 downto 0);
--Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,177)@36
Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(22 downto 0);
Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b <= Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 22);
--extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest(MUX,178)@36
extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b;
extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest: PROCESS (extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s, en, GND_q, Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b)
BEGIN
CASE extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s IS
WHEN "0" => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b;
WHEN OTHERS => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,176)@36
stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(21 downto 0);
stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b <= stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in(21 downto 0);
--stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,179)@36
stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q <= extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q & stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b;
--stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,181)@36
stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a <= stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q;
stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a = stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--sticky_uid183_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,182)@36
sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a <= stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q;
sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q <= not sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a;
--lrs_uid185_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,184)@36
lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q <= FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b & sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q;
--roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,186)@36
roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a <= lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q;
roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b <= roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q;
roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a = roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b else "0";
--roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,187)@36
roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a <= roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q;
roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q <= not roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a;
--roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,190)@36
roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q <= GND_q & normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b & cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q & roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q;
--reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1(REG,514)@36
reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q <= roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest(CONSTANT,168)
biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q <= "0001111111";
--expSum_uid168_rAsinPi_uid13_fpArcsinPiTest(ADD,167)@33
expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b);
expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b);
expSum_uid168_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a) + UNSIGNED(expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q <= expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o(8 downto 0);
--ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,674)@34
ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest(SUB,169)@35
expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q);
expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q(9)) & biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q);
expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q <= expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o(10 downto 0);
--expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,188)@36
expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q <= expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q & fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q;
--reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0(REG,513)@36
reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q <= expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest(ADD,191)@37
expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q(34)) & reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q);
expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q);
expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a) + SIGNED(expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b));
expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o(35 downto 0);
--expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,193)@37
expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q;
expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in(35 downto 24);
--expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,194)@37
expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b(7 downto 0);
expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b <= expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in(7 downto 0);
--ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a(DELAY,1049)@37
ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b, xout => ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3(REG,522)@38
reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q <= ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,746)@34
ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1(REG,515)@37
reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest(COMPARE,198)@38
expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin <= GND_q;
expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q(11)) & reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q) & '0';
expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) & expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin(0);
expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b));
expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n(0) <= not expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o(14);
--InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,163)@33
InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a <= exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q;
InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a;
--InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,164)@33
InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q;
InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a;
--InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,165)@33
InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q;
InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a;
--exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,166)@33
exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a <= InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q;
exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b <= InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q;
exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c <= InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q;
exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a and exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b and exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c;
--ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,716)@33
ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,147)@33
InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q;
InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a;
--InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,148)@33
InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q;
InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a;
--InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,149)@33
InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q;
InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a;
--exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,150)@33
exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a <= InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q;
exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b <= InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q;
exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c <= InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q;
exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a and exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b and exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c;
--ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a(DELAY,1045)@33
ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1(REG,518)@37
reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q <= ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,207)@38
ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a <= reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q;
ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q;
ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c <= expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n;
ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q <= ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a and ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b and ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c;
--excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,206)@33
excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q;
excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q;
excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q <= excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a and excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,733)@33
ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,205)@33
excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q;
excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q;
excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q <= excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a and excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,732)@33
ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,204)@33
excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q;
excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q;
excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q <= excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a and excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,731)@33
ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,208)@38
excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a <= ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q;
excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b <= ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q;
excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c <= ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q;
excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d <= ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q;
excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q <= excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d;
--expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest(COMPARE,196)@38
expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin <= GND_q;
expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q(11)) & reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q) & expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin(0);
expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b));
expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n(0) <= not expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o(14);
--reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1(REG,516)@33
reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,715)@34
ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q, xout => ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,202)@38
excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a <= ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q;
excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q;
excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c <= expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n;
excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q <= excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a and excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b and excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c;
--excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,201)@33
excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q;
excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q;
excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q <= excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a and excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,720)@33
ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,200)@33
excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q;
excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q;
excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,719)@33
ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,199)@33
excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q;
excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q;
excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b;
--ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,718)@33
ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,203)@38
excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a <= ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q;
excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b <= ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q;
excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c <= ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q;
excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d <= excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q;
excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q <= excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d;
--concExc_uid214_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,213)@38
concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q <= ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q & excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q & excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q;
--reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0(REG,520)@38
reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q <= concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest(LOOKUP,214)@39
excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest: PROCESS (reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q) IS
WHEN "000" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "01";
WHEN "001" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00";
WHEN "010" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "10";
WHEN "011" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00";
WHEN "100" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "11";
WHEN "101" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00";
WHEN "110" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00";
WHEN "111" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest(MUX,223)@39
expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s <= excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q;
expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest: PROCESS (expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s IS
WHEN "00" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q;
WHEN "10" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,192)@37
fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q(23 downto 0);
fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in(23 downto 1);
--ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a(DELAY,1048)@37
ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b, xout => ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3(REG,521)@38
reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q <= ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest(MUX,218)@39
fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s <= excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q;
fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest: PROCESS (fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q)
BEGIN
CASE fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s IS
WHEN "00" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
WHEN "01" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q;
WHEN "10" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q;
WHEN "11" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q;
WHEN OTHERS => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid227_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,226)@39
R_uid227_rAsinPi_uid13_fpArcsinPiTest_q <= ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q & expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q & fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q;
--xOut(GPOUT,4)@39
q <= R_uid227_rAsinPi_uid13_fpArcsinPiTest_q;
end normal;
| mit |
QuantumRipple/VHDL | basic/wide_uns_comparator_dsp.vhd | 1 | 15681 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wide_uns_comparator_dsp is
generic (
n : positive := 48
);
port (
clk : in std_logic;
a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
gt : out std_logic; --3 cycle delay
eq : out std_logic
);
end wide_uns_comparator_dsp;
architecture rtl of wide_uns_comparator_dsp is
component dsp48e1plus is
generic (
-- Feature Control Attributes: Data Path Selection
A_INPUT : string := "DIRECT"; -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT : string := "DIRECT"; -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT : boolean := FALSE; -- Select D port usage (TRUE or FALSE)
USE_MULT : string := "MULTIPLY"; -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD : string := "ONE48"; -- SIMD selection ("ONE48", "TWO24", "FOUR12")
IS_ALUMODE_INVERTED : std_logic_vector (3 downto 0) := "0000";
IS_CARRYIN_INVERTED : bit := '0';
IS_CLK_INVERTED : bit := '0';
IS_INMODE_INVERTED : std_logic_vector (4 downto 0) := "00000";
IS_OPMODE_INVERTED : std_logic_vector (6 downto 0) := "0000000";
AUTORESET_PATDET : string := "NO_RESET"; -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK : bit_vector := X"3fffffffffff"; -- 48-bit mask value for pattern detect (1=ignore)
PATTERN : bit_vector := X"000000000000"; -- 48-bit pattern match for pattern detect
SEL_MASK : string := "MASK"; -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN : string := "PATTERN"; -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT : string := "NO_PATDET"; -- Enable pattern detect ("PATDET" or "NO_PATDET")
ACASCREG : integer := 1; -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG : integer := 1; -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG : integer := 1; -- Number of pipeline stages for ALUMODE (0 or 1)
AREG : integer := 1; -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG : integer := 1; -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG : integer := 1; -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG : integer := 1; -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG : integer := 1; -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG : integer := 1; -- Number of pipeline stages for C (0 or 1)
DREG : integer := 1; -- Number of pipeline stages for D (0 or 1)
INMODEREG : integer := 1; -- Number of pipeline stages for INMODE (0 or 1)
MREG : integer := 1; -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG : integer := 1; -- Number of pipeline stages for OPMODE (0 or 1)
PREG : integer := 1 -- Number of pipeline stages for P (0 or 1)
);
port (
ACOUT : out std_logic_vector(29 downto 0); -- 30-bit output: A port cascade output
BCOUT : out std_logic_vector(17 downto 0); -- 18-bit output: B port cascade output
CARRYCASCOUT : out std_ulogic; -- 1-bit output: Cascade carry output
MULTSIGNOUT : out std_ulogic; -- 1-bit output: Multiplier sign cascade output
PCOUT : out std_logic_vector(47 downto 0); -- 48-bit output: Cascade output
OVERFLOW : out std_ulogic; -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT : out std_ulogic; -- 1-bit output: Pattern bar detect output
PATTERNDETECT : out std_ulogic; -- 1-bit output: Pattern detect output
UNDERFLOW : out std_ulogic; -- 1-bit output: Underflow in add/acc output
CARRYOUT : out std_logic_vector(3 downto 0); -- 4-bit output: Carry output
P : out std_logic_vector(47 downto 0); -- 48-bit output: Primary data output
ACIN : in std_logic_vector(29 downto 0) := (others=>'0'); -- 30-bit input: A cascade data input
BCIN : in std_logic_vector(17 downto 0) := (others=>'0'); -- 18-bit input: B cascade input
CARRYCASCIN : in std_ulogic := '0'; -- 1-bit input: Cascade carry input
MULTSIGNIN : in std_ulogic := '0'; -- 1-bit input: Multiplier sign input
PCIN : in std_logic_vector(47 downto 0) := (others=>'0'); -- 48-bit input: P cascade input
ALUMODE : in std_logic_vector(3 downto 0) := (others=>'0'); -- 4-bit input: ALU control input
CARRYINSEL : in std_logic_vector(2 downto 0) := (others=>'0'); -- 3-bit input: Carry select input
CLK : in std_ulogic := '0'; -- 1-bit input: Clock input
INMODE : in std_logic_vector(4 downto 0) := (others=>'0'); -- 5-bit input: INMODE control input
OPMODE : in std_logic_vector(6 downto 0) := (others=>'0'); -- 7-bit input: Operation mode input
A : in std_logic_vector(29 downto 0) := (others=>'0'); -- 30-bit input: A data input
B : in std_logic_vector(17 downto 0) := (others=>'0'); -- 18-bit input: B data input
C : in std_logic_vector(47 downto 0) := (others=>'0'); -- 48-bit input: C data input
CARRYIN : in std_ulogic := '0'; -- 1-bit input: Carry input signal
D : in std_logic_vector(24 downto 0) := (others=>'0'); -- 25-bit input: D data input
CEA1 : in std_ulogic := '1'; -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 : in std_ulogic := '1'; -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD : in std_ulogic := '1'; -- 1-bit input: Clock enable input for ADREG
CEALUMODE : in std_ulogic := '1'; -- 1-bit input: Clock enable input for ALUMODE
CEB1 : in std_ulogic := '1'; -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 : in std_ulogic := '1'; -- 1-bit input: Clock enable input for 2nd stage BREG
CEC : in std_ulogic := '1'; -- 1-bit input: Clock enable input for CREG
CECARRYIN : in std_ulogic := '1'; -- 1-bit input: Clock enable input for CARRYINREG
CECTRL : in std_ulogic := '1'; -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED : in std_ulogic := '1'; -- 1-bit input: Clock enable input for DREG
CEINMODE : in std_ulogic := '1'; -- 1-bit input: Clock enable input for INMODEREG
CEM : in std_ulogic := '1'; -- 1-bit input: Clock enable input for MREG
CEP : in std_ulogic := '1'; -- 1-bit input: Clock enable input for PREG
RSTA : in std_ulogic := '0'; -- 1-bit input: Reset input for AREG
RSTALLCARRYIN : in std_ulogic := '0'; -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE : in std_ulogic := '0'; -- 1-bit input: Reset input for ALUMODEREG
RSTB : in std_ulogic := '0'; -- 1-bit input: Reset input for BREG
RSTC : in std_ulogic := '0'; -- 1-bit input: Reset input for CREG
RSTCTRL : in std_ulogic := '0'; -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD : in std_ulogic := '0'; -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE : in std_ulogic := '0'; -- 1-bit input: Reset input for INMODEREG
RSTM : in std_ulogic := '0'; -- 1-bit input: Reset input for MREG
RSTP : in std_ulogic := '0' -- 1-bit input: Reset input for PREG
);
end component;
constant c_num_dsp : integer := (n-1)/48 + 1;
signal gt_i : std_logic_vector(0 to c_num_dsp-1);
signal eq_i : std_logic_vector(0 to c_num_dsp-1);
signal a_i : std_logic_vector(48*c_num_dsp-1 downto 0) := (others=>'0');
signal b_i : std_logic_vector(48*c_num_dsp-1 downto 0) := (others=>'0');
begin
a_i(a'range) <= a;
b_i(b'range) <= b;
g_dsps : for i in 0 to c_num_dsp-1 generate
signal cout : std_logic_vector(3 downto 0);
begin
u_dsp : dsp48e1plus
generic map(
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "NONE", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
IS_ALUMODE_INVERTED => "0000",
IS_CARRYIN_INVERTED => '0',
IS_CLK_INVERTED => '0',
IS_INMODE_INVERTED => "00000",
IS_OPMODE_INVERTED => "0000000",
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"000000000000", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map(
ACOUT => open,
BCOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
PCOUT => open,
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => eq_i(i),
UNDERFLOW => open,
CARRYOUT => cout,-- 4-bit output: Carry output
P => open,
ACIN => (others=>'0'),
BCIN => (others=>'0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
PCIN => (others=>'0'),
ALUMODE => "0011", -- z-(x+y+cin) ... c-a:b
CARRYINSEL => (others=>'0'),
CLK => clk,
INMODE => (others=>'0'),
OPMODE => "0110011", --x=a:b, z=c
A => a_i(48*i+29 downto 48*i), -- : in std_logic_vector(29 downto 0) := (others=>'0'); -- 30-bit input: A data input
B => a_i(48*i+47 downto 48*i+30), -- : in std_logic_vector(17 downto 0) := (others=>'0'); -- 18-bit input: B data input
C => b_i(48*i+47 downto 48*i), -- : in std_logic_vector(47 downto 0) := (others=>'0'); -- 48-bit input: C data input
CARRYIN => '0',
D => (others=>'0'),
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEINMODE => '0', -- 1-bit input: Clock enable input for INMODEREG
CEM => '0', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
g_eq_checks : if i=c_num_dsp-1 generate
gt_i(i) <= cout(3); --cout shold trigger on borrow, meaning a was greater than b to cause the borrow since we're doing b-a in the DSP
else generate
gt_i(i) <= cout(3) and and( eq_i(i+1 to eq_i'right) ); --if we care about the higher order bits, and_reduce their equality checks
end generate;
end generate;
process(clk)
begin
if rising_edge(clk) then
gt <= or(gt_i);
eq <= and(eq_i);
end if;
end process;
end architecture rtl; | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_fxmul.vhd | 10 | 10945 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXMUL.VHD ***
--*** ***
--*** Function: Parameterized Fixed Point ***
--*** Multiplier ***
--*** (behavioral and synthesizable support) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - change 54x18 to >54 outputs ***
--*** 23/04/09 - change 54x54 to SII & SIII ***
--*** versions with both 8&9(10) multipliers ***
--*** ***
--***************************************************
--***************************************************
--*** valid supported cores ***
--*** ***
--*** 1: SII/SIII, 18-36 bit inputs, ***
--*** any output width, 2 pipes ***
--*** 2: SII/SIII, 18-36 bit inputs, ***
--*** any output width, 3 pipes ***
--*** 3: SII/SIII 54x18 inputs, ***
--*** up to 72 bit output, 3 or 4 pipes ***
--*** 4: SII 54x54 inputs, 72 bit outputs, ***
--*** 8 or 9 multiplier core 5 or 6 pipes ***
--*** 5: SIII/IV 54x54 inputs, 72 bit outputs, ***
--*** 8 or 9 (10) multiplier core 4 pipes ***
--*** ***
--***************************************************
ENTITY fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_fxmul;
ARCHITECTURE rtl OF fp_fxmul IS
component fp_mul2s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_mul5418s
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_mul54us_3xs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54us_28s
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54us_29s
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54us_38s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54usb
GENERIC (
latency : positive := 5; -- 4/5/6
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
prune : integer := 0 -- 0 = pruned multiplier, 1 = normal multiplier
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul7218s
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (72 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gone: IF ((widthaa < 37) AND
(widthbb < 37) AND
(widthcc <= (widthaa + widthbb)) AND
(pipes = 2)) GENERATE
mulone: fp_mul2s
GENERIC MAP (widthaa=>widthaa,widthbb=>widthbb,widthcc=>widthcc)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
gtwo: IF ((widthaa < 37) AND
(widthbb < 37) AND
(widthcc <= (widthaa + widthbb)) AND
(pipes = 3)) GENERATE
multwo: fp_mul3s
GENERIC MAP (widthaa=>widthaa,widthbb=>widthbb,widthcc=>widthcc)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
gthr: IF ((widthaa = 54) AND
(widthbb = 18) AND
(widthcc < 73) AND
((pipes = 3) OR (pipes = 4))) GENERATE
multhr: fp_mul5418s
GENERIC MAP (widthcc=>widthcc,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
gforone: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 1) AND
(device = 1) AND
(synthesize = 1)) GENERATE
mulforone: fp_mul54us_3xs
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gfortwo: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 0) AND
(device = 1) AND
(synthesize = 1)) GENERATE
mulfortwo: fp_mul54us_38s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gforthr: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 0) AND
(device = 0) AND
(synthesize = 1) AND
((pipes = 5) OR (pipes = 6))) GENERATE
mulforthr: fp_mul54us_28s
GENERIC MAP (latency=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gforfor: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 1) AND
(device = 0) AND
(synthesize = 1) AND
((pipes = 5) OR (pipes = 6))) GENERATE
mulforfor: fp_mul54us_29s
GENERIC MAP (latency=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gforfiv: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(synthesize = 0)) GENERATE
mulforfiv: fp_mul54usb
GENERIC MAP (latency=>pipes,device=>device,prune=>accuracy)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dataaa,bb=>databb,
cc=>result);
END GENERATE;
gfiv: IF ((widthaa = 72) AND
(widthbb = 18) AND
(widthcc < 90) AND
((pipes = 3) OR (pipes = 4))) GENERATE
multhr: fp_mul7218s
GENERIC MAP (widthcc=>widthcc,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_cntuscomb64.vhd | 10 | 6369 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSCOMB64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuscomb64 IS
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuscomb64;
ARCHITECTURE rtl of hcc_cntuscomb64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzero(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzero(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzero(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzero(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzero(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/hcc_cntuscomb64.vhd | 10 | 6369 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSCOMB64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuscomb64 IS
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuscomb64;
ARCHITECTURE rtl of hcc_cntuscomb64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzero(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzero(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzero(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzero(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzero(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_sqrt_double_s5.vhd | 10 | 321991 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sqrt_double_s5
-- VHDL created on Tue Apr 9 15:17:30 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sqrt_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sqrt_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0);
signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0);
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type;
attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type;
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0);
signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0);
signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0);
signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0);
signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0);
signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0);
signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0);
signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0);
signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0);
signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0);
signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0);
signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0);
signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0);
signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0);
signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0);
signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0);
signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0);
signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0);
signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0);
signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0);
signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0);
signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0);
signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0);
signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0);
signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0);
signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0);
signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0);
signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0);
signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0);
signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0);
signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0);
signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0);
signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0);
signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0);
signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0);
signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0);
signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0);
signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0);
signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0);
signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0);
signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0);
signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0);
signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0);
signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0);
signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0);
signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0);
signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0);
signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0);
signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0);
signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b);
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000";
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0";
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b;
--signX_uid8_fpSqrtTest(BITSELECT,7)@0
signX_uid8_fpSqrtTest_in <= a;
signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63);
--cstAllZWE_uid11_fpSqrtTest(CONSTANT,10)
cstAllZWE_uid11_fpSqrtTest_q <= "00000000000";
--expX_uid6_fpSqrtTest(BITSELECT,5)@0
expX_uid6_fpSqrtTest_in <= a(62 downto 0);
expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52);
--expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0
expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q;
expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0";
--negZero_uid56_fpSqrtTest(LOGICAL,55)@0
negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b;
negZero_uid56_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427)
-- every=1, low=0, high=24, step=1, init=1
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24;
ELSE
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5));
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q)
BEGIN
CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS
WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q;
WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 25,
width_b => 1,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq,
address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa,
data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia
);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0);
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b);
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b;
--cstAllOWE_uid9_fpSqrtTest(CONSTANT,8)
cstAllOWE_uid9_fpSqrtTest_q <= "11111111111";
--sBiasM1_uid28_fpSqrtTest(CONSTANT,27)
sBiasM1_uid28_fpSqrtTest_q <= "01111111110";
--expOddSig_uid29_fpSqrtTest(ADD,28)@0
expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q);
expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b));
expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0);
--expROdd_uid30_fpSqrtTest(BITSELECT,29)@0
expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q;
expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1);
--sBias_uid25_fpSqrtTest(CONSTANT,24)
sBias_uid25_fpSqrtTest_q <= "01111111111";
--expEvenSig_uid26_fpSqrtTest(ADD,25)@0
expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q);
expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b));
expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0);
--expREven_uid27_fpSqrtTest(BITSELECT,26)@0
expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q;
expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1);
--expX0_uid31_fpSqrtTest(BITSELECT,30)@0
expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0);
expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0);
--expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0
expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b;
expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a;
--expRMux_uid33_fpSqrtTest(MUX,32)@0
expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q;
expRMux_uid33_fpSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid33_fpSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid33_fpSqrtTest_s IS
WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b;
WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b;
WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1
ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0
ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid10_fpSqrtTest(CONSTANT,9)
cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000";
--fracX_uid7_fpSqrtTest(BITSELECT,6)@0
fracX_uid7_fpSqrtTest_in <= a(51 downto 0);
fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0);
--fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0
fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b;
fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q;
fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0";
--InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0
InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q;
InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a;
--expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0
expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q;
expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0";
--exc_N_uid20_fpSqrtTest(LOGICAL,19)@0
exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b;
--InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0
InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q;
InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a;
--exc_I_uid18_fpSqrtTest(LOGICAL,17)@0
exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b;
--InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0
InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a;
--InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0
InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a;
--exc_R_uid24_fpSqrtTest(LOGICAL,23)@0
exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c;
--minReg_uid42_fpSqrtTest(LOGICAL,41)@0
minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q;
minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b;
minReg_uid42_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--minInf_uid43_fpSqrtTest(LOGICAL,42)@0
minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b;
minInf_uid43_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1
excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q;
excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c;
--InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0
InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a;
--inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0
inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b;
inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--join_uid45_fpSqrtTest(BITJOIN,44)@1
join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q;
--fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1
fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q;
--fracSel_uid47_fpSqrtTest(LOOKUP,46)@1
fracSel_uid47_fpSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracSel_uid47_fpSqrtTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (fracSelIn_uid46_fpSqrtTest_q) IS
WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01";
WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN OTHERS =>
fracSel_uid47_fpSqrtTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid51_fpSqrtTest(MUX,50)@2
expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q;
expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q)
BEGIN
CASE expRPostExc_uid51_fpSqrtTest_s IS
WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q;
WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q;
WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401)
-- every=1, low=0, high=23, step=1, init=1
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23;
ELSE
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5));
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 24,
width_b => 11,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0);
--fracNaN_uid52_fpSqrtTest(CONSTANT,51)
fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0
fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b;
fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45);
--addrTable_uid36_fpSqrtTest(BITJOIN,35)@0
addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b;
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1
memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q;
memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 8,
numwords_a => 256,
width_b => 17,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq,
address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa,
data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia
);
memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0);
--reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398)
ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0
ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3
FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0);
FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0);
--yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3
yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28);
--reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b);
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7
prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16);
--highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7
highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b;
highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4
memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q;
memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 8,
numwords_a => 256,
width_b => 24,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq,
address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa,
data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia
);
memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0);
--reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7
sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b);
sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b));
sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0);
--lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7
lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7
s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b;
--reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b);
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b;
--yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3
yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21);
--reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1));
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0);
--prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b);
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50));
END IF;
END IF;
END PROCESS;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11
prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23);
--highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11
highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b;
highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8
memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q;
memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 8,
numwords_a => 256,
width_b => 33,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq,
address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa,
data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia
);
memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0);
--reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11
sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b);
sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b));
sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0);
--lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11
lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0);
--s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11
s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b;
--reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b);
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101";
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0";
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b;
--yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3
yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12);
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516)
-- every=1, low=0, high=5, step=1, init=1
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5;
ELSE
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3));
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 3,
numwords_a => 6,
width_b => 33,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq,
address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa,
data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia
);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0);
--reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b);
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68));
END IF;
END IF;
END PROCESS;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15
prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34);
--highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15
highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b;
highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529)
-- every=1, low=0, high=8, step=1, init=1
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8;
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4));
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12
memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15
sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b);
sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b));
sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0);
--lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15
lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0);
--s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15
s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b;
--yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15
yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q;
yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24);
--reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b);
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440)
-- every=1, low=0, high=9, step=1, init=1
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9;
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4));
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 10,
width_b => 45,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0);
--yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15
yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q;
yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5);
--xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15
xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0);
xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15
pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15
yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0);
yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0);
--spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15
spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b;
--pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15
pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15
xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b;
xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22);
--reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q;
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2);
--highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19
highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b;
highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6);
--yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15
yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q;
yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15);
--reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15
xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b;
xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13);
--reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b);
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0');
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0');
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q);
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b);
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b));
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0);
--lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19
lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0);
lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0);
--add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19
add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b;
--R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19
R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0);
R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17);
--reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503)
-- every=1, low=0, high=12, step=1, init=1
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12;
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4));
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 13,
width_b => 8,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16
memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 8,
numwords_a => 256,
width_b => 9,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0);
--reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16
memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid64_sqrtTableGenerator(BITJOIN,63)@19
os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q;
--rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92)
rndBit_uid93_sqrtPolynomialEvaluator_q <= "01";
--cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19
cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q;
--reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20
ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q);
ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q);
ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b));
ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0);
--s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20
s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q;
s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b);
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490)
-- every=1, low=0, high=14, step=1, init=1
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14;
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4));
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS
WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q;
WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 15,
width_b => 45,
widthad_b => 4,
numwords_b => 15,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq,
address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa,
data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia
);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24
ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54));
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b));
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0);
--ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24
ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000";
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b));
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b));
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0);
--prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26
prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0);
prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44);
--highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26
highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b;
highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2);
--reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464)
-- every=1, low=0, high=19, step=1, init=1
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19;
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5));
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 20,
width_b => 8,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23
memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q;
memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 8,
numwords_a => 256,
width_b => 17,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0);
--reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 20,
width_b => 8,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23
memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid61_sqrtTableGenerator(BITJOIN,60)@26
os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q;
--reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27
sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b));
sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0);
--lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26
lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0);
--reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27
s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q;
--fracR_uid39_fpSqrtTest(BITSELECT,38)@27
fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0);
fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5);
--reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b);
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 24,
width_b => 2,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq,
address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa,
data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia
);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid55_fpSqrtTest(MUX,54)@28
fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q;
fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q)
BEGIN
CASE fracRPostExc_uid55_fpSqrtTest_s IS
WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q;
WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28
RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q;
--xOut(GPOUT,4)@28
q <= RSqrt_uid57_fpSqrtTest_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/fp_cordic_m1.vhd | 10 | 13050 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_ln1p_double_s5.vhd | 10 | 825320 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_cntsgn32.vhd | 20 | 5981 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn32;
ARCHITECTURE rtl OF hcc_cntsgn32 IS
type positiontype IS ARRAY (8 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(2) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(4) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(5) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(6) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(7) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(8) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(2) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(3) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(4) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(5) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(6) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(7) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(8) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 8 GENERATE
sec(k) <= (possec(k) AND NOT(frac(32))) OR (NOT(negsec(k)) AND frac(32));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(31 DOWNTO 28),
position=>position(1)(5 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(27 DOWNTO 24),
position=>position(2)(5 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(23 DOWNTO 20),
position=>position(3)(5 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(19 DOWNTO 16),
position=>position(4)(5 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(15 DOWNTO 12),
position=>position(5)(5 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(11 DOWNTO 8),
position=>position(6)(5 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(7 DOWNTO 4),
position=>position(7)(5 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>5)
PORT MAP (signbit=>frac(32),inbus=>lastfrac,
position=>position(8)(5 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(32);
gmc: FOR k IN 1 TO 5 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8));
END GENERATE;
count(6) <= '0';
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_exp2_double_s5.vhd | 10 | 562595 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp2_double_s5
-- VHDL created on Mon Apr 8 15:27:49 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp2_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp2_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid9_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid13_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid15_fpExp2Test_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid16_fpExp2Test_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid17_fpExp2Test_q : std_logic_vector (51 downto 0);
signal exc_R_uid31_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_c : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid31_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid71_fpExp2Test_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid78_fpExp2Test_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid78_fpExp2Test_q : std_logic_vector (10 downto 0);
signal z_uid82_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (31 downto 0);
signal z_uid86_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(64 downto 0);
signal rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(64 downto 0);
signal z_uid94_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(7 downto 0);
signal z_uid98_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(15 downto 0);
signal z_uid102_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(23 downto 0);
signal z_uid108_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(1 downto 0);
signal z_uid112_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(3 downto 0);
signal z_uid116_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(0 downto 0);
signal rndBit_uid169_exp2PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid187_exp2PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid192_pT1_uid162_exp2PolyEval_q : std_logic_vector (35 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid197_pT2_uid168_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_a : std_logic_vector (1 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid200_pT2_uid168_exp2PolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid200_pT2_uid168_exp2PolyEval_pr: signal is "logic";
signal sm0_uid200_pT2_uid168_exp2PolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid208_pT3_uid174_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid225_pT4_uid180_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid240_pT5_uid186_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid252_pT5_uid186_exp2PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle of sm0_uid252_pT5_uid186_exp2PolyEval_pr: signal is "logic";
signal sm0_uid252_pT5_uid186_exp2PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y_type;
type multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s : multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s_type;
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s : multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y_type;
type multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s : multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s_type;
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q : std_logic_vector (11 downto 0);
signal reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q : std_logic_vector (64 downto 0);
signal reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q : std_logic_vector (0 downto 0);
signal reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q : std_logic_vector (12 downto 0);
signal reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q : std_logic_vector (13 downto 0);
signal reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q : std_logic_vector (2 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q : std_logic_vector (17 downto 0);
signal reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q : std_logic_vector (5 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q : std_logic_vector (1 downto 0);
signal reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q : std_logic_vector (4 downto 0);
signal reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q : std_logic_vector (37 downto 0);
signal reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q : std_logic_vector (30 downto 0);
signal reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q : std_logic_vector (37 downto 0);
signal reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q : std_logic_vector (59 downto 0);
signal reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q : std_logic_vector (51 downto 0);
signal ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q : std_logic_vector (6 downto 0);
signal ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q : std_logic_vector (51 downto 0);
signal ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q : std_logic_vector (0 downto 0);
signal ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q : std_logic_vector (10 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (56 downto 0);
signal ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (48 downto 0);
signal ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (40 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (62 downto 0);
signal ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q : std_logic_vector (58 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (1 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q : std_logic_vector (5 downto 0);
signal ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq : std_logic;
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q : signal is true;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q : signal is true;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 : std_logic;
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q : signal is true;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid40_fpExp2Test_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid40_fpExp2Test_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid40_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid40_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expUdf_uid53_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expUdf_uid53_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expUdf_uid53_fpExp2Test_n : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_a : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_b : std_logic_vector(16 downto 0);
signal expOvf_uid55_fpExp2Test_o : std_logic_vector (16 downto 0);
signal expOvf_uid55_fpExp2Test_cin : std_logic_vector (0 downto 0);
signal expOvf_uid55_fpExp2Test_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q : std_logic_vector (26 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid59_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvSignX_uid62_fpExp2Test_q : std_logic_vector(0 downto 0);
signal oFracX_uid33_uid33_fpExp2Test_q : std_logic_vector (52 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpExp2Test_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExp2Test_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExp2Test_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExp2Test_b : std_logic_vector (0 downto 0);
signal frac_uid23_fpExp2Test_in : std_logic_vector (51 downto 0);
signal frac_uid23_fpExp2Test_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid20_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid20_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid22_fpExp2Test_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid22_fpExp2Test_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid24_fpExp2Test_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid24_fpExp2Test_q : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_I_uid25_fpExp2Test_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid38_fpExp2Test_q : std_logic_vector (11 downto 0);
signal shiftVal_uid42_fpExp2Test_s : std_logic_vector (0 downto 0);
signal shiftVal_uid42_fpExp2Test_q : std_logic_vector (6 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_a : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_b : std_logic_vector(14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_o : std_logic_vector (14 downto 0);
signal expRPostBiasPreExc_uid51_fpExp2Test_q : std_logic_vector (13 downto 0);
signal negInf_uid57_fpExp2Test_a : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_b : std_logic_vector(0 downto 0);
signal negInf_uid57_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid58_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid60_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRZero_uid61_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid63_fpExp2Test_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid65_fpExp2Test_q : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_a : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_b : std_logic_vector(0 downto 0);
signal posInf_uid67_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_a : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_b : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_c : std_logic_vector(0 downto 0);
signal excRInf_uid68_fpExp2Test_q : std_logic_vector(0 downto 0);
signal excREnc_uid70_fpExp2Test_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid74_fpExp2Test_q : std_logic_vector (51 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal memoryC0_uid129_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid130_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid131_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid132_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid133_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC0_uid134_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC1_uid136_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid137_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid138_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid139_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC1_uid140_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid143_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid144_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid145_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid146_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC2_uid147_exp2TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid149_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid150_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid151_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC3_uid152_exp2TabGen_q : std_logic_vector(5 downto 0);
signal memoryC4_uid154_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid155_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC4_uid156_exp2TabGen_q : std_logic_vector(6 downto 0);
signal memoryC5_uid158_exp2TabGen_q : std_logic_vector(9 downto 0);
signal memoryC5_uid159_exp2TabGen_q : std_logic_vector(7 downto 0);
signal ts2_uid171_exp2PolyEval_a : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_b : std_logic_vector(38 downto 0);
signal ts2_uid171_exp2PolyEval_o : std_logic_vector (38 downto 0);
signal ts2_uid171_exp2PolyEval_q : std_logic_vector (38 downto 0);
signal ts3_uid177_exp2PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid177_exp2PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid177_exp2PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid183_exp2PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid183_exp2PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid183_exp2PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid189_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal ts5_uid189_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal ts5_uid189_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal oFracXZwE_uid34_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_in : std_logic_vector (19 downto 0);
signal lowRangeA_uid201_pT2_uid168_exp2PolyEval_b : std_logic_vector (19 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highABits_uid202_pT2_uid168_exp2PolyEval_b : std_logic_vector (33 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b : std_logic_vector(35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o : std_logic_vector (35 downto 0);
signal sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q : std_logic_vector (34 downto 0);
signal TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_a : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_b : std_logic_vector(64 downto 0);
signal onesCmpFxpIn_uid35_fpExp2Test_q : std_logic_vector(64 downto 0);
signal fxpInExt_uid36_fpExp2Test_a : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_b : std_logic_vector(66 downto 0);
signal fxpInExt_uid36_fpExp2Test_o : std_logic_vector (66 downto 0);
signal fxpInExt_uid36_fpExp2Test_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid48_fpExp2Test_in : std_logic_vector (45 downto 0);
signal yPPolyEval_uid48_fpExp2Test_b : std_logic_vector (45 downto 0);
signal concExc_uid69_fpExp2Test_q : std_logic_vector (2 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal RExp2_uid79_fpExp2Test_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal os_uid148_exp2TabGen_q : std_logic_vector (42 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT2_uid167_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT2_uid167_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid173_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT3_uid173_exp2PolyEval_b : std_logic_vector (35 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid179_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT4_uid179_exp2PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid30_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid26_fpExp2Test_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid29_fpExp2Test_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid39_fpExp2Test_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid39_fpExp2Test_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid41_fpExp2Test_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal expR_uid56_fpExp2Test_in : std_logic_vector (10 downto 0);
signal expR_uid56_fpExp2Test_b : std_logic_vector (10 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (56 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (48 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (40 downto 0);
signal os_uid135_exp2TabGen_q : std_logic_vector (56 downto 0);
signal os_uid142_exp2TabGen_q : std_logic_vector (50 downto 0);
signal os_uid153_exp2TabGen_q : std_logic_vector (35 downto 0);
signal os_uid157_exp2TabGen_q : std_logic_vector (26 downto 0);
signal os_uid160_exp2TabGen_q : std_logic_vector (17 downto 0);
signal s2_uid172_exp2PolyEval_in : std_logic_vector (38 downto 0);
signal s2_uid172_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal s3_uid178_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid178_exp2PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid184_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid184_exp2PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid190_exp2PolyEval_in : std_logic_vector (60 downto 0);
signal s5_uid190_exp2PolyEval_b : std_logic_vector (59 downto 0);
signal lowRangeB_uid163_exp2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid163_exp2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid164_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid164_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal add0_uid201_uid204_pT2_uid168_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid218_pT3_uid174_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_in : std_logic_vector (30 downto 0);
signal highBBits_uid219_pT3_uid174_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid233_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid234_pT4_uid180_exp2PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid254_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid255_pT5_uid186_exp2PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (62 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (60 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (58 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (63 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_in : std_logic_vector (64 downto 0);
signal fxpInPreAlign_uid37_fpExp2Test_b : std_logic_vector (64 downto 0);
signal yT1_uid161_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal yT1_uid161_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal xBottomBits_uid242_pT5_uid186_exp2PolyEval_b : std_logic_vector (18 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in : std_logic_vector (45 downto 0);
signal xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_in : std_logic_vector (18 downto 0);
signal sSM0W_uid251_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal cIncludingRoundingBit_uid176_exp2PolyEval_q : std_logic_vector (44 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_in : std_logic_vector (26 downto 0);
signal sSM0W_uid199_pT2_uid168_exp2PolyEval_b : std_logic_vector (4 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in : std_logic_vector (35 downto 0);
signal xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_in : std_logic_vector (8 downto 0);
signal xBottomBits_uid211_pT3_uid174_exp2PolyEval_b : std_logic_vector (8 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid227_pT4_uid180_exp2PolyEval_b : std_logic_vector (15 downto 0);
signal exc_N_uid27_fpExp2Test_a : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_b : std_logic_vector(0 downto 0);
signal exc_N_uid27_fpExp2Test_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid188_exp2PolyEval_q : std_logic_vector (59 downto 0);
signal cIncludingRoundingBit_uid182_exp2PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid170_exp2PolyEval_q : std_logic_vector (37 downto 0);
signal sumAHighB_uid165_exp2PolyEval_a : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_b : std_logic_vector(27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_o : std_logic_vector (27 downto 0);
signal sumAHighB_uid165_exp2PolyEval_q : std_logic_vector (27 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_in : std_logic_vector (10 downto 0);
signal yBottomBits_uid210_pT3_uid174_exp2PolyEval_b : std_logic_vector (10 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in : std_logic_vector (37 downto 0);
signal yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid226_pT4_uid180_exp2PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid241_pT5_uid186_exp2PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid250_pT5_uid186_exp2PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid50_fpExp2Test_in : std_logic_vector (57 downto 0);
signal peOR_uid50_fpExp2Test_b : std_logic_vector (52 downto 0);
signal s1_uid163_uid166_exp2PolyEval_q : std_logic_vector (28 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_in : std_logic_vector (53 downto 0);
signal R_uid205_pT2_uid168_exp2PolyEval_b : std_logic_vector (30 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid220_pT3_uid174_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid235_pT4_uid180_exp2PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid256_pT5_uid186_exp2PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (0 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in : std_logic_vector (64 downto 0);
signal X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector (32 downto 0);
signal pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q : std_logic_vector (25 downto 0);
signal InvExc_N_uid28_fpExp2Test_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid28_fpExp2Test_q : std_logic_vector(0 downto 0);
signal spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q : std_logic_vector (11 downto 0);
signal fracR_uid52_fpExp2Test_in : std_logic_vector (51 downto 0);
signal fracR_uid52_fpExp2Test_b : std_logic_vector (51 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in : std_logic_vector (28 downto 0);
signal yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_in : std_logic_vector (1 downto 0);
signal sSM0H_uid198_pT2_uid168_exp2PolyEval_b : std_logic_vector (1 downto 0);
signal add0_uid218_uid221_pT3_uid174_exp2PolyEval_q : std_logic_vector (56 downto 0);
signal add0_uid233_uid236_pT4_uid180_exp2PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid254_uid257_pT5_uid186_exp2PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q : std_logic_vector (64 downto 0);
signal pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q : std_logic_vector (17 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_in : std_logic_vector (55 downto 0);
signal R_uid222_pT3_uid174_exp2PolyEval_b : std_logic_vector (37 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid237_pT4_uid180_exp2PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid258_pT5_uid186_exp2PolyEval_b : std_logic_vector (54 downto 0);
signal ePre_uid44_fpExp2Test_in : std_logic_vector (64 downto 0);
signal ePre_uid44_fpExp2Test_b : std_logic_vector (12 downto 0);
signal y_uid45_fpExp2Test_in : std_logic_vector (51 downto 0);
signal y_uid45_fpExp2Test_b : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_in : std_logic_vector (51 downto 0);
signal addr_uid47_fpExp2Test_b : std_logic_vector (5 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable(LOGICAL,723)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q <= not ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_a;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor(LOGICAL,737)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q <= not (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_a or ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top(CONSTANT,720)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q <= "010101";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp(LOGICAL,721)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_mem_top_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q <= "1" when ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_a = ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_b else "0";
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg(REG,722)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena(REG,738)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_nor_q = "1") THEN
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd(LOGICAL,739)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_sticky_ena_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b <= en;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_a and ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_b;
--cstAllOWE_uid16_fpExp2Test(CONSTANT,15)
cstAllOWE_uid16_fpExp2Test_q <= "11111111111";
--cstBias_uid9_fpExp2Test(CONSTANT,8)
cstBias_uid9_fpExp2Test_q <= "01111111111";
--signX_uid7_fpExp2Test(BITSELECT,6)@0
signX_uid7_fpExp2Test_in <= a;
signX_uid7_fpExp2Test_b <= signX_uid7_fpExp2Test_in(63 downto 63);
--ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b(DELAY,360)@0
ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExp2Test_b, xout => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid23_fpExp2Test(BITSELECT,22)@0
frac_uid23_fpExp2Test_in <= a(51 downto 0);
frac_uid23_fpExp2Test_b <= frac_uid23_fpExp2Test_in(51 downto 0);
--ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a(DELAY,357)@0
ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid23_fpExp2Test_b, xout => ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid33_uid33_fpExp2Test(BITJOIN,32)@1
oFracX_uid33_uid33_fpExp2Test_q <= VCC_q & ld_frac_uid23_fpExp2Test_b_to_oFracX_uid33_uid33_fpExp2Test_a_q;
--oFracXZwE_uid34_fpExp2Test(BITJOIN,33)@1
oFracXZwE_uid34_fpExp2Test_q <= GND_q & oFracX_uid33_uid33_fpExp2Test_q & cstZeroWE_uid13_fpExp2Test_q;
--onesCmpFxpIn_uid35_fpExp2Test(LOGICAL,34)@1
onesCmpFxpIn_uid35_fpExp2Test_a <= oFracXZwE_uid34_fpExp2Test_q;
onesCmpFxpIn_uid35_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q(0)) & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
onesCmpFxpIn_uid35_fpExp2Test_q <= onesCmpFxpIn_uid35_fpExp2Test_a xor onesCmpFxpIn_uid35_fpExp2Test_b;
--fxpInExt_uid36_fpExp2Test(ADD,35)@1
fxpInExt_uid36_fpExp2Test_a <= STD_LOGIC_VECTOR((66 downto 65 => onesCmpFxpIn_uid35_fpExp2Test_q(64)) & onesCmpFxpIn_uid35_fpExp2Test_q);
fxpInExt_uid36_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "00000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q);
fxpInExt_uid36_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid36_fpExp2Test_a) + SIGNED(fxpInExt_uid36_fpExp2Test_b));
fxpInExt_uid36_fpExp2Test_q <= fxpInExt_uid36_fpExp2Test_o(65 downto 0);
--fxpInPreAlign_uid37_fpExp2Test(BITSELECT,36)@1
fxpInPreAlign_uid37_fpExp2Test_in <= fxpInExt_uid36_fpExp2Test_q(64 downto 0);
fxpInPreAlign_uid37_fpExp2Test_b <= fxpInPreAlign_uid37_fpExp2Test_in(64 downto 0);
--msbx_uid81_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,80)@1
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b <= msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 64);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,447)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,122)@3
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a <= GND_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b <= ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,123)@4
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 1);
--rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,124)@4
rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1Pad1_uid123_fxpInPostAlign_uid43_fpExp2Test_q & RightShiftStage264dto1_uid124_fxpInPostAlign_uid43_fpExp2Test_b;
--z_uid116_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,115)
z_uid116_fxpInPostAlign_uid43_fpExp2Test_q <= "000000";
--rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,116)@3
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid116_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,429)@1
ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid102_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,101)
z_uid102_fxpInPostAlign_uid43_fpExp2Test_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,102)@2
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid102_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,89)
rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,90)@1
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a <= rightShiftStage0Idx3_uid90_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((64 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 65, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid86_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,85)
z_uid86_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,86)@1
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid86_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_b;
--rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,88)@1
rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx2Pad64_uid87_fxpInPostAlign_uid43_fpExp2Test_q & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4(REG,266)@1
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q <= rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--z_uid82_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,81)
z_uid82_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,82)@1
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid82_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b(0)) & msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b);
rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_b;
--X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,83)@1
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in <= fxpInPreAlign_uid37_fpExp2Test_b;
X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b <= X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 32);
--rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,84)@1
rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx1Pad32_uid83_fxpInPostAlign_uid43_fpExp2Test_q & X64dto32_uid84_fxpInPostAlign_uid43_fpExp2Test_b;
--reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3(REG,265)@1
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q <= rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2(REG,264)@1
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q <= fxpInPreAlign_uid37_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid15_fpExp2Test(CONSTANT,14)
cstBiasPWE_uid15_fpExp2Test_q <= "1000001";
--expX_uid6_fpExp2Test(BITSELECT,5)@0
expX_uid6_fpExp2Test_in <= a(62 downto 0);
expX_uid6_fpExp2Test_b <= expX_uid6_fpExp2Test_in(62 downto 52);
--cstBiasPWE_uid14_fpExp2Test(CONSTANT,13)
cstBiasPWE_uid14_fpExp2Test_q <= "10000001010";
--shiftValuePreSat_uid38_fpExp2Test(SUB,37)@0
shiftValuePreSat_uid38_fpExp2Test_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid14_fpExp2Test_q);
shiftValuePreSat_uid38_fpExp2Test_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExp2Test_b);
shiftValuePreSat_uid38_fpExp2Test_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_a) - UNSIGNED(shiftValuePreSat_uid38_fpExp2Test_b));
shiftValuePreSat_uid38_fpExp2Test_q <= shiftValuePreSat_uid38_fpExp2Test_o(11 downto 0);
--shiftValuePreSatRed_uid41_fpExp2Test(BITSELECT,40)@0
shiftValuePreSatRed_uid41_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q(6 downto 0);
shiftValuePreSatRed_uid41_fpExp2Test_b <= shiftValuePreSatRed_uid41_fpExp2Test_in(6 downto 0);
--ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c(DELAY,369)@0
ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid41_fpExp2Test_b, xout => ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0(REG,262)@0
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q <= shiftValuePreSat_uid38_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid40_fpExp2Test(COMPARE,39)@1
shiftUdf_uid40_fpExp2Test_cin <= GND_q;
shiftUdf_uid40_fpExp2Test_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q(11)) & reg_shiftValuePreSat_uid38_fpExp2Test_0_to_shiftUdf_uid40_fpExp2Test_0_q) & '0';
shiftUdf_uid40_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid15_fpExp2Test_q) & shiftUdf_uid40_fpExp2Test_cin(0);
shiftUdf_uid40_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid40_fpExp2Test_a) - SIGNED(shiftUdf_uid40_fpExp2Test_b));
shiftUdf_uid40_fpExp2Test_n(0) <= not shiftUdf_uid40_fpExp2Test_o(14);
--shiftVal_uid42_fpExp2Test(MUX,41)@1
shiftVal_uid42_fpExp2Test_s <= shiftUdf_uid40_fpExp2Test_n;
shiftVal_uid42_fpExp2Test: PROCESS (shiftVal_uid42_fpExp2Test_s, en, ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q, cstBiasPWE_uid15_fpExp2Test_q)
BEGIN
CASE shiftVal_uid42_fpExp2Test_s IS
WHEN "0" => shiftVal_uid42_fpExp2Test_q <= ld_shiftValuePreSatRed_uid41_fpExp2Test_b_to_shiftVal_uid42_fpExp2Test_c_q;
WHEN "1" => shiftVal_uid42_fpExp2Test_q <= cstBiasPWE_uid15_fpExp2Test_q;
WHEN OTHERS => shiftVal_uid42_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,91)@1
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q;
rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1(REG,263)@1
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test(MUX,92)@2
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s <= reg_rightShiftStageSel6Dto5_uid92_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_1_q;
rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q, reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q, reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q, rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_fxpInPreAlign_uid37_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx1_uid85_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_3_q;
WHEN "10" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0Idx2_uid89_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_4_q;
WHEN "11" => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage0Idx3_uid91_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,103)@2
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 24);
--ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,439)@2
ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 41, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,104)@3
rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3Pad24_uid103_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto24_uid104_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid98_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,97)
z_uid98_fxpInPostAlign_uid43_fpExp2Test_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,98)@2
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid98_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,99)@2
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 16);
--ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,435)@2
ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,100)@3
rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2Pad16_uid99_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto16_uid100_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid94_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,93)
z_uid94_fxpInPostAlign_uid43_fpExp2Test_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,94)@2
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid94_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,95)@2
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 8);
--ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,431)@2
ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,96)@3
rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1Pad8_uid95_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage064dto8_uid96_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2(REG,268)@2
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,105)@1
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(4 downto 0);
rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1(REG,267)@1
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,442)@2
ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test(MUX,106)@3
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel4Dto3_uid106_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage0_uid93_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx1_uid97_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx2_uid101_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage1Idx3_uid105_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,117)@3
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 6);
--ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,457)@3
ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,118)@4
rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3Pad6_uid117_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto6_uid118_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid112_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,111)
z_uid112_fxpInPostAlign_uid43_fpExp2Test_q <= "0000";
--rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,112)@3
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid112_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,113)@3
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 4);
--ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,453)@3
ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,114)@4
rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2Pad4_uid113_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto4_uid114_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_a_q;
--z_uid108_fxpInPostAlign_uid43_fpExp2Test(CONSTANT,107)
z_uid108_fxpInPostAlign_uid43_fpExp2Test_q <= "00";
--rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test(LOGICAL,108)@3
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a <= z_uid108_fxpInPostAlign_uid43_fpExp2Test_q;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q(0)) & ld_msbx_uid81_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b_q);
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_a or rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_b;
rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q, xin => rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,109)@3
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b <= RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_in(64 downto 2);
--ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a(DELAY,449)@3
ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b, xout => ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test(BITJOIN,110)@4
rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1Pad2_uid109_fxpInPostAlign_uid43_fpExp2Test_q & ld_RightShiftStage164dto2_uid110_fxpInPostAlign_uid43_fpExp2Test_b_to_rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_a_q;
--reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2(REG,270)@3
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q <= rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,119)@1
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(2 downto 0);
rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1(REG,269)@1
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,460)@2
ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test(MUX,120)@4
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel2Dto1_uid120_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s, en, reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q, rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "00" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= reg_rightShiftStage1_uid107_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_2_q;
WHEN "01" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx1_uid111_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "10" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx2_uid115_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "11" => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2Idx3_uid119_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test(BITSELECT,125)@1
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in <= shiftVal_uid42_fpExp2Test_q(0 downto 0);
rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1(REG,271)@1
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q <= rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b(DELAY,470)@2
ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test(MUX,126)@4
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s <= ld_reg_rightShiftStageSel0Dto0_uid126_fxpInPostAlign_uid43_fpExp2Test_0_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_1_q_to_rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_b_q;
rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test: PROCESS (rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s, en, rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q, rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q)
BEGIN
CASE rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_s IS
WHEN "0" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage2_uid121_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN "1" => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= rightShiftStage3Idx1_uid125_fxpInPostAlign_uid43_fpExp2Test_q;
WHEN OTHERS => rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--ePre_uid44_fpExp2Test(BITSELECT,43)@4
ePre_uid44_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q;
ePre_uid44_fpExp2Test_b <= ePre_uid44_fpExp2Test_in(64 downto 52);
--reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0(REG,272)@4
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q <= ePre_uid44_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--expRPostBiasPreExc_uid51_fpExp2Test(ADD,50)@5
expRPostBiasPreExc_uid51_fpExp2Test_a <= STD_LOGIC_VECTOR((14 downto 13 => reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q(12)) & reg_ePre_uid44_fpExp2Test_0_to_expRPostBiasPreExc_uid51_fpExp2Test_0_q);
expRPostBiasPreExc_uid51_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "000" & cstBias_uid9_fpExp2Test_q);
expRPostBiasPreExc_uid51_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_a) + SIGNED(expRPostBiasPreExc_uid51_fpExp2Test_b));
expRPostBiasPreExc_uid51_fpExp2Test_q <= expRPostBiasPreExc_uid51_fpExp2Test_o(13 downto 0);
--expR_uid56_fpExp2Test(BITSELECT,55)@5
expR_uid56_fpExp2Test_in <= expRPostBiasPreExc_uid51_fpExp2Test_q(10 downto 0);
expR_uid56_fpExp2Test_b <= expR_uid56_fpExp2Test_in(10 downto 0);
--ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d(DELAY,411)@5
ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid56_fpExp2Test_b, xout => ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid13_fpExp2Test(CONSTANT,12)
cstZeroWE_uid13_fpExp2Test_q <= "00000000000";
--cstAllZWF_uid17_fpExp2Test(CONSTANT,16)
cstAllZWF_uid17_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid24_fpExp2Test(LOGICAL,23)@0
fracXIsZero_uid24_fpExp2Test_a <= frac_uid23_fpExp2Test_b;
fracXIsZero_uid24_fpExp2Test_b <= cstAllZWF_uid17_fpExp2Test_q;
fracXIsZero_uid24_fpExp2Test_q <= "1" when fracXIsZero_uid24_fpExp2Test_a = fracXIsZero_uid24_fpExp2Test_b else "0";
--InvFracXIsZero_uid26_fpExp2Test(LOGICAL,25)@0
InvFracXIsZero_uid26_fpExp2Test_a <= fracXIsZero_uid24_fpExp2Test_q;
InvFracXIsZero_uid26_fpExp2Test_q <= not InvFracXIsZero_uid26_fpExp2Test_a;
--expXIsMax_uid22_fpExp2Test(LOGICAL,21)@0
expXIsMax_uid22_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsMax_uid22_fpExp2Test_b <= cstAllOWE_uid16_fpExp2Test_q;
expXIsMax_uid22_fpExp2Test_q <= "1" when expXIsMax_uid22_fpExp2Test_a = expXIsMax_uid22_fpExp2Test_b else "0";
--exc_N_uid27_fpExp2Test(LOGICAL,26)@0
exc_N_uid27_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_N_uid27_fpExp2Test_b <= InvFracXIsZero_uid26_fpExp2Test_q;
exc_N_uid27_fpExp2Test_q <= exc_N_uid27_fpExp2Test_a and exc_N_uid27_fpExp2Test_b;
--ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c(DELAY,406)@0
ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_N_uid27_fpExp2Test_q, xout => ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid62_fpExp2Test(LOGICAL,61)@1
InvSignX_uid62_fpExp2Test_a <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
InvSignX_uid62_fpExp2Test_q <= not InvSignX_uid62_fpExp2Test_a;
--expOvfInitial_uid39_fpExp2Test(BITSELECT,38)@0
expOvfInitial_uid39_fpExp2Test_in <= shiftValuePreSat_uid38_fpExp2Test_q;
expOvfInitial_uid39_fpExp2Test_b <= expOvfInitial_uid39_fpExp2Test_in(11 downto 11);
--reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2(REG,274)@0
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q <= expOvfInitial_uid39_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid28_fpExp2Test(LOGICAL,27)@0
InvExc_N_uid28_fpExp2Test_a <= exc_N_uid27_fpExp2Test_q;
InvExc_N_uid28_fpExp2Test_q <= not InvExc_N_uid28_fpExp2Test_a;
--exc_I_uid25_fpExp2Test(LOGICAL,24)@0
exc_I_uid25_fpExp2Test_a <= expXIsMax_uid22_fpExp2Test_q;
exc_I_uid25_fpExp2Test_b <= fracXIsZero_uid24_fpExp2Test_q;
exc_I_uid25_fpExp2Test_q <= exc_I_uid25_fpExp2Test_a and exc_I_uid25_fpExp2Test_b;
--InvExc_I_uid29_fpExp2Test(LOGICAL,28)@0
InvExc_I_uid29_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
InvExc_I_uid29_fpExp2Test_q <= not InvExc_I_uid29_fpExp2Test_a;
--expXIsZero_uid20_fpExp2Test(LOGICAL,19)@0
expXIsZero_uid20_fpExp2Test_a <= expX_uid6_fpExp2Test_b;
expXIsZero_uid20_fpExp2Test_b <= cstZeroWE_uid13_fpExp2Test_q;
expXIsZero_uid20_fpExp2Test_q <= "1" when expXIsZero_uid20_fpExp2Test_a = expXIsZero_uid20_fpExp2Test_b else "0";
--InvExpXIsZero_uid30_fpExp2Test(LOGICAL,29)@0
InvExpXIsZero_uid30_fpExp2Test_a <= expXIsZero_uid20_fpExp2Test_q;
InvExpXIsZero_uid30_fpExp2Test_q <= not InvExpXIsZero_uid30_fpExp2Test_a;
--exc_R_uid31_fpExp2Test(LOGICAL,30)@0
exc_R_uid31_fpExp2Test_a <= InvExpXIsZero_uid30_fpExp2Test_q;
exc_R_uid31_fpExp2Test_b <= InvExc_I_uid29_fpExp2Test_q;
exc_R_uid31_fpExp2Test_c <= InvExc_N_uid28_fpExp2Test_q;
exc_R_uid31_fpExp2Test_q_i <= exc_R_uid31_fpExp2Test_a and exc_R_uid31_fpExp2Test_b and exc_R_uid31_fpExp2Test_c;
exc_R_uid31_fpExp2Test_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid31_fpExp2Test_q, xin => exc_R_uid31_fpExp2Test_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid63_fpExp2Test(LOGICAL,62)@1
regXAndExpOverflowAndPos_uid63_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_c <= InvSignX_uid62_fpExp2Test_q;
regXAndExpOverflowAndPos_uid63_fpExp2Test_q <= regXAndExpOverflowAndPos_uid63_fpExp2Test_a and regXAndExpOverflowAndPos_uid63_fpExp2Test_b and regXAndExpOverflowAndPos_uid63_fpExp2Test_c;
--ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c(DELAY,403)@1
ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid63_fpExp2Test_q, xout => ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a(DELAY,385)@0
ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => expOvfInitial_uid39_fpExp2Test_b, xout => ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpOvfInitial_uid59_fpExp2Test(LOGICAL,58)@6
InvExpOvfInitial_uid59_fpExp2Test_a <= ld_expOvfInitial_uid39_fpExp2Test_b_to_InvExpOvfInitial_uid59_fpExp2Test_a_q;
InvExpOvfInitial_uid59_fpExp2Test_q <= not InvExpOvfInitial_uid59_fpExp2Test_a;
--reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1(REG,273)@5
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q <= expRPostBiasPreExc_uid51_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid55_fpExp2Test(COMPARE,54)@6
expOvf_uid55_fpExp2Test_cin <= GND_q;
expOvf_uid55_fpExp2Test_a <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & '0';
expOvf_uid55_fpExp2Test_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid16_fpExp2Test_q) & expOvf_uid55_fpExp2Test_cin(0);
expOvf_uid55_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid55_fpExp2Test_a) - SIGNED(expOvf_uid55_fpExp2Test_b));
expOvf_uid55_fpExp2Test_n(0) <= not expOvf_uid55_fpExp2Test_o(16);
--ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a(DELAY,386)@1
ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid31_fpExp2Test_q, xout => ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--regInAndOvf_uid65_fpExp2Test(LOGICAL,64)@6
regInAndOvf_uid65_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regInAndOvf_uid65_fpExp2Test_b <= expOvf_uid55_fpExp2Test_n;
regInAndOvf_uid65_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regInAndOvf_uid65_fpExp2Test_q <= regInAndOvf_uid65_fpExp2Test_a and regInAndOvf_uid65_fpExp2Test_b and regInAndOvf_uid65_fpExp2Test_c;
--ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a(DELAY,399)@0
ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid25_fpExp2Test_q, xout => ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid67_fpExp2Test(LOGICAL,66)@1
posInf_uid67_fpExp2Test_a <= ld_exc_I_uid25_fpExp2Test_q_to_posInf_uid67_fpExp2Test_a_q;
posInf_uid67_fpExp2Test_b <= InvSignX_uid62_fpExp2Test_q;
posInf_uid67_fpExp2Test_q <= posInf_uid67_fpExp2Test_a and posInf_uid67_fpExp2Test_b;
--ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a(DELAY,401)@1
ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => posInf_uid67_fpExp2Test_q, xout => ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid68_fpExp2Test(LOGICAL,67)@6
excRInf_uid68_fpExp2Test_a <= ld_posInf_uid67_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_a_q;
excRInf_uid68_fpExp2Test_b <= regInAndOvf_uid65_fpExp2Test_q;
excRInf_uid68_fpExp2Test_c <= ld_regXAndExpOverflowAndPos_uid63_fpExp2Test_q_to_excRInf_uid68_fpExp2Test_c_q;
excRInf_uid68_fpExp2Test_q <= excRInf_uid68_fpExp2Test_a or excRInf_uid68_fpExp2Test_b or excRInf_uid68_fpExp2Test_c;
--negInf_uid57_fpExp2Test(LOGICAL,56)@0
negInf_uid57_fpExp2Test_a <= exc_I_uid25_fpExp2Test_q;
negInf_uid57_fpExp2Test_b <= signX_uid7_fpExp2Test_b;
negInf_uid57_fpExp2Test_q <= negInf_uid57_fpExp2Test_a and negInf_uid57_fpExp2Test_b;
--ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c(DELAY,391)@0
ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => negInf_uid57_fpExp2Test_q, xout => ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q, ena => en(0), clk => clk, aclr => areset );
--regXAndExpOverflowAndNeg_uid58_fpExp2Test(LOGICAL,57)@1
regXAndExpOverflowAndNeg_uid58_fpExp2Test_a <= exc_R_uid31_fpExp2Test_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_b <= reg_expOvfInitial_uid39_fpExp2Test_0_to_regXAndExpOverflowAndNeg_uid58_fpExp2Test_2_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_c <= ld_signX_uid7_fpExp2Test_b_to_onesCmpFxpIn_uid35_fpExp2Test_b_q;
regXAndExpOverflowAndNeg_uid58_fpExp2Test_q <= regXAndExpOverflowAndNeg_uid58_fpExp2Test_a and regXAndExpOverflowAndNeg_uid58_fpExp2Test_b and regXAndExpOverflowAndNeg_uid58_fpExp2Test_c;
--ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b(DELAY,390)@1
ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid58_fpExp2Test_q, xout => ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid53_fpExp2Test(COMPARE,52)@6
expUdf_uid53_fpExp2Test_cin <= GND_q;
expUdf_uid53_fpExp2Test_a <= STD_LOGIC_VECTOR('0' & "00000000000000" & GND_q) & '0';
expUdf_uid53_fpExp2Test_b <= STD_LOGIC_VECTOR((15 downto 14 => reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q(13)) & reg_expRPostBiasPreExc_uid51_fpExp2Test_0_to_expUdf_uid53_fpExp2Test_1_q) & expUdf_uid53_fpExp2Test_cin(0);
expUdf_uid53_fpExp2Test_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid53_fpExp2Test_a) - SIGNED(expUdf_uid53_fpExp2Test_b));
expUdf_uid53_fpExp2Test_n(0) <= not expUdf_uid53_fpExp2Test_o(16);
--regXAndUdf_uid60_fpExp2Test(LOGICAL,59)@6
regXAndUdf_uid60_fpExp2Test_a <= ld_exc_R_uid31_fpExp2Test_q_to_regXAndUdf_uid60_fpExp2Test_a_q;
regXAndUdf_uid60_fpExp2Test_b <= expUdf_uid53_fpExp2Test_n;
regXAndUdf_uid60_fpExp2Test_c <= InvExpOvfInitial_uid59_fpExp2Test_q;
regXAndUdf_uid60_fpExp2Test_q <= regXAndUdf_uid60_fpExp2Test_a and regXAndUdf_uid60_fpExp2Test_b and regXAndUdf_uid60_fpExp2Test_c;
--excRZero_uid61_fpExp2Test(LOGICAL,60)@6
excRZero_uid61_fpExp2Test_a <= regXAndUdf_uid60_fpExp2Test_q;
excRZero_uid61_fpExp2Test_b <= ld_regXAndExpOverflowAndNeg_uid58_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_b_q;
excRZero_uid61_fpExp2Test_c <= ld_negInf_uid57_fpExp2Test_q_to_excRZero_uid61_fpExp2Test_c_q;
excRZero_uid61_fpExp2Test_q <= excRZero_uid61_fpExp2Test_a or excRZero_uid61_fpExp2Test_b or excRZero_uid61_fpExp2Test_c;
--concExc_uid69_fpExp2Test(BITJOIN,68)@6
concExc_uid69_fpExp2Test_q <= ld_exc_N_uid27_fpExp2Test_q_to_concExc_uid69_fpExp2Test_c_q & excRInf_uid68_fpExp2Test_q & excRZero_uid61_fpExp2Test_q;
--reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0(REG,277)@6
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q <= concExc_uid69_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid70_fpExp2Test(LOOKUP,69)@7
excREnc_uid70_fpExp2Test: PROCESS (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid69_fpExp2Test_0_to_excREnc_uid70_fpExp2Test_0_q) IS
WHEN "000" => excREnc_uid70_fpExp2Test_q <= "01";
WHEN "001" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "010" => excREnc_uid70_fpExp2Test_q <= "10";
WHEN "011" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "100" => excREnc_uid70_fpExp2Test_q <= "11";
WHEN "101" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "110" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN "111" => excREnc_uid70_fpExp2Test_q <= "00";
WHEN OTHERS =>
excREnc_uid70_fpExp2Test_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid78_fpExp2Test(MUX,77)@7
expRPostExc_uid78_fpExp2Test_s <= excREnc_uid70_fpExp2Test_q;
expRPostExc_uid78_fpExp2Test: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid78_fpExp2Test_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid78_fpExp2Test_s IS
WHEN "00" => expRPostExc_uid78_fpExp2Test_q <= cstZeroWE_uid13_fpExp2Test_q;
WHEN "01" => expRPostExc_uid78_fpExp2Test_q <= ld_expR_uid56_fpExp2Test_b_to_expRPostExc_uid78_fpExp2Test_d_q;
WHEN "10" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN "11" => expRPostExc_uid78_fpExp2Test_q <= cstAllOWE_uid16_fpExp2Test_q;
WHEN OTHERS => expRPostExc_uid78_fpExp2Test_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg(DELAY,727)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid78_fpExp2Test_q, xout => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt(COUNTER,716)
-- every=1, low=0, high=21, step=1, init=1
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i = 20 THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_eq = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i - 21;
ELSE
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_i,5));
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg(REG,717)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux(MUX,718)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux: PROCESS (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q, ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_s IS
WHEN "0" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
WHEN "1" => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem(DUALMEM,728)
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_inputreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 22,
width_b => 11,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq,
address_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_aa,
data_a => ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_ia
);
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q <= ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_iq(10 downto 0);
--oneFracRPostExc2_uid71_fpExp2Test(CONSTANT,70)
oneFracRPostExc2_uid71_fpExp2Test_q <= "0000000000000000000000000000000000000000000000000001";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor(LOGICAL,813)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg(REG,811)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena(REG,814)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd(LOGICAL,815)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_b;
--y_uid45_fpExp2Test(BITSELECT,44)@4
y_uid45_fpExp2Test_in <= rightShiftStage3_uid127_fxpInPostAlign_uid43_fpExp2Test_q(51 downto 0);
y_uid45_fpExp2Test_b <= y_uid45_fpExp2Test_in(51 downto 0);
--ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a(DELAY,373)@4
ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => y_uid45_fpExp2Test_b, xout => ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid48_fpExp2Test(BITSELECT,47)@5
yPPolyEval_uid48_fpExp2Test_in <= ld_y_uid45_fpExp2Test_b_to_yPPolyEval_uid48_fpExp2Test_a_q(45 downto 0);
yPPolyEval_uid48_fpExp2Test_b <= yPPolyEval_uid48_fpExp2Test_in(45 downto 0);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg(DELAY,805)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid48_fpExp2Test_b, xout => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt(COUNTER,807)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg(REG,808)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux(MUX,809)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem(DUALMEM,806)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT2_uid167_exp2PolyEval(BITSELECT,166)@9
yT2_uid167_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_replace_mem_q;
yT2_uid167_exp2PolyEval_b <= yT2_uid167_exp2PolyEval_in(45 downto 19);
--sSM0W_uid199_pT2_uid168_exp2PolyEval(BITSELECT,198)@9
sSM0W_uid199_pT2_uid168_exp2PolyEval_in <= yT2_uid167_exp2PolyEval_b;
sSM0W_uid199_pT2_uid168_exp2PolyEval_b <= sSM0W_uid199_pT2_uid168_exp2PolyEval_in(26 downto 22);
--reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1(REG,308)@9
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q <= sSM0W_uid199_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--addr_uid47_fpExp2Test(BITSELECT,46)@4
addr_uid47_fpExp2Test_in <= y_uid45_fpExp2Test_b;
addr_uid47_fpExp2Test_b <= addr_uid47_fpExp2Test_in(51 downto 46);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0(REG,280)@4
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q <= addr_uid47_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid159_exp2TabGen(LOOKUP,158)@5
memoryC5_uid159_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid159_exp2TabGen_q <= "00101011";
WHEN "000001" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000010" => memoryC5_uid159_exp2TabGen_q <= "00101100";
WHEN "000011" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000100" => memoryC5_uid159_exp2TabGen_q <= "00101101";
WHEN "000101" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000110" => memoryC5_uid159_exp2TabGen_q <= "00101110";
WHEN "000111" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001000" => memoryC5_uid159_exp2TabGen_q <= "00101111";
WHEN "001001" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001010" => memoryC5_uid159_exp2TabGen_q <= "00110000";
WHEN "001011" => memoryC5_uid159_exp2TabGen_q <= "00110001";
WHEN "001100" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001101" => memoryC5_uid159_exp2TabGen_q <= "00110010";
WHEN "001110" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "001111" => memoryC5_uid159_exp2TabGen_q <= "00110011";
WHEN "010000" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010001" => memoryC5_uid159_exp2TabGen_q <= "00110100";
WHEN "010010" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010011" => memoryC5_uid159_exp2TabGen_q <= "00110101";
WHEN "010100" => memoryC5_uid159_exp2TabGen_q <= "00110110";
WHEN "010101" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010110" => memoryC5_uid159_exp2TabGen_q <= "00110111";
WHEN "010111" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011000" => memoryC5_uid159_exp2TabGen_q <= "00111000";
WHEN "011001" => memoryC5_uid159_exp2TabGen_q <= "00111001";
WHEN "011010" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011011" => memoryC5_uid159_exp2TabGen_q <= "00111010";
WHEN "011100" => memoryC5_uid159_exp2TabGen_q <= "00111011";
WHEN "011101" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011110" => memoryC5_uid159_exp2TabGen_q <= "00111100";
WHEN "011111" => memoryC5_uid159_exp2TabGen_q <= "00111101";
WHEN "100000" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100001" => memoryC5_uid159_exp2TabGen_q <= "00111110";
WHEN "100010" => memoryC5_uid159_exp2TabGen_q <= "00111111";
WHEN "100011" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100100" => memoryC5_uid159_exp2TabGen_q <= "01000000";
WHEN "100101" => memoryC5_uid159_exp2TabGen_q <= "01000001";
WHEN "100110" => memoryC5_uid159_exp2TabGen_q <= "01000010";
WHEN "100111" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101000" => memoryC5_uid159_exp2TabGen_q <= "01000011";
WHEN "101001" => memoryC5_uid159_exp2TabGen_q <= "01000100";
WHEN "101010" => memoryC5_uid159_exp2TabGen_q <= "01000101";
WHEN "101011" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101100" => memoryC5_uid159_exp2TabGen_q <= "01000110";
WHEN "101101" => memoryC5_uid159_exp2TabGen_q <= "01000111";
WHEN "101110" => memoryC5_uid159_exp2TabGen_q <= "01001000";
WHEN "101111" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110000" => memoryC5_uid159_exp2TabGen_q <= "01001001";
WHEN "110001" => memoryC5_uid159_exp2TabGen_q <= "01001010";
WHEN "110010" => memoryC5_uid159_exp2TabGen_q <= "01001011";
WHEN "110011" => memoryC5_uid159_exp2TabGen_q <= "01001100";
WHEN "110100" => memoryC5_uid159_exp2TabGen_q <= "01001101";
WHEN "110101" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110110" => memoryC5_uid159_exp2TabGen_q <= "01001110";
WHEN "110111" => memoryC5_uid159_exp2TabGen_q <= "01001111";
WHEN "111000" => memoryC5_uid159_exp2TabGen_q <= "01010000";
WHEN "111001" => memoryC5_uid159_exp2TabGen_q <= "01010001";
WHEN "111010" => memoryC5_uid159_exp2TabGen_q <= "01010010";
WHEN "111011" => memoryC5_uid159_exp2TabGen_q <= "01010011";
WHEN "111100" => memoryC5_uid159_exp2TabGen_q <= "01010100";
WHEN "111101" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111110" => memoryC5_uid159_exp2TabGen_q <= "01010101";
WHEN "111111" => memoryC5_uid159_exp2TabGen_q <= "01010110";
WHEN OTHERS =>
memoryC5_uid159_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC5_uid158_exp2TabGen(LOOKUP,157)@5
memoryC5_uid158_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC5_uid158_exp2TabGen_q <= "1110111001";
WHEN "000001" => memoryC5_uid158_exp2TabGen_q <= "0111011010";
WHEN "000010" => memoryC5_uid158_exp2TabGen_q <= "1101101110";
WHEN "000011" => memoryC5_uid158_exp2TabGen_q <= "0110010100";
WHEN "000100" => memoryC5_uid158_exp2TabGen_q <= "1101111010";
WHEN "000101" => memoryC5_uid158_exp2TabGen_q <= "0101110101";
WHEN "000110" => memoryC5_uid158_exp2TabGen_q <= "1110000101";
WHEN "000111" => memoryC5_uid158_exp2TabGen_q <= "0101110000";
WHEN "001000" => memoryC5_uid158_exp2TabGen_q <= "1110011110";
WHEN "001001" => memoryC5_uid158_exp2TabGen_q <= "0110010110";
WHEN "001010" => memoryC5_uid158_exp2TabGen_q <= "1111000101";
WHEN "001011" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "001100" => memoryC5_uid158_exp2TabGen_q <= "0000100010";
WHEN "001101" => memoryC5_uid158_exp2TabGen_q <= "1001100001";
WHEN "001110" => memoryC5_uid158_exp2TabGen_q <= "0010011111";
WHEN "001111" => memoryC5_uid158_exp2TabGen_q <= "1010111011";
WHEN "010000" => memoryC5_uid158_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC5_uid158_exp2TabGen_q <= "1101001001";
WHEN "010010" => memoryC5_uid158_exp2TabGen_q <= "0110101100";
WHEN "010011" => memoryC5_uid158_exp2TabGen_q <= "1111101110";
WHEN "010100" => memoryC5_uid158_exp2TabGen_q <= "0111111111";
WHEN "010101" => memoryC5_uid158_exp2TabGen_q <= "0001111010";
WHEN "010110" => memoryC5_uid158_exp2TabGen_q <= "1011111100";
WHEN "010111" => memoryC5_uid158_exp2TabGen_q <= "0101010101";
WHEN "011000" => memoryC5_uid158_exp2TabGen_q <= "1111100000";
WHEN "011001" => memoryC5_uid158_exp2TabGen_q <= "1010000000";
WHEN "011010" => memoryC5_uid158_exp2TabGen_q <= "0011000111";
WHEN "011011" => memoryC5_uid158_exp2TabGen_q <= "1101100000";
WHEN "011100" => memoryC5_uid158_exp2TabGen_q <= "0111101101";
WHEN "011101" => memoryC5_uid158_exp2TabGen_q <= "0010110001";
WHEN "011110" => memoryC5_uid158_exp2TabGen_q <= "1011111101";
WHEN "011111" => memoryC5_uid158_exp2TabGen_q <= "0111111100";
WHEN "100000" => memoryC5_uid158_exp2TabGen_q <= "0010100100";
WHEN "100001" => memoryC5_uid158_exp2TabGen_q <= "1100010111";
WHEN "100010" => memoryC5_uid158_exp2TabGen_q <= "0111100110";
WHEN "100011" => memoryC5_uid158_exp2TabGen_q <= "0010100001";
WHEN "100100" => memoryC5_uid158_exp2TabGen_q <= "1101101101";
WHEN "100101" => memoryC5_uid158_exp2TabGen_q <= "1010001111";
WHEN "100110" => memoryC5_uid158_exp2TabGen_q <= "0101001110";
WHEN "100111" => memoryC5_uid158_exp2TabGen_q <= "0000100001";
WHEN "101000" => memoryC5_uid158_exp2TabGen_q <= "1011111010";
WHEN "101001" => memoryC5_uid158_exp2TabGen_q <= "1000000100";
WHEN "101010" => memoryC5_uid158_exp2TabGen_q <= "0011011100";
WHEN "101011" => memoryC5_uid158_exp2TabGen_q <= "0000010100";
WHEN "101100" => memoryC5_uid158_exp2TabGen_q <= "1011110001";
WHEN "101101" => memoryC5_uid158_exp2TabGen_q <= "0111010100";
WHEN "101110" => memoryC5_uid158_exp2TabGen_q <= "0101000110";
WHEN "101111" => memoryC5_uid158_exp2TabGen_q <= "0001100111";
WHEN "110000" => memoryC5_uid158_exp2TabGen_q <= "1101101011";
WHEN "110001" => memoryC5_uid158_exp2TabGen_q <= "1010000101";
WHEN "110010" => memoryC5_uid158_exp2TabGen_q <= "1000001111";
WHEN "110011" => memoryC5_uid158_exp2TabGen_q <= "0101001100";
WHEN "110100" => memoryC5_uid158_exp2TabGen_q <= "0010000110";
WHEN "110101" => memoryC5_uid158_exp2TabGen_q <= "0000001011";
WHEN "110110" => memoryC5_uid158_exp2TabGen_q <= "1101000111";
WHEN "110111" => memoryC5_uid158_exp2TabGen_q <= "1011011011";
WHEN "111000" => memoryC5_uid158_exp2TabGen_q <= "1001010010";
WHEN "111001" => memoryC5_uid158_exp2TabGen_q <= "1000000101";
WHEN "111010" => memoryC5_uid158_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC5_uid158_exp2TabGen_q <= "0011100111";
WHEN "111100" => memoryC5_uid158_exp2TabGen_q <= "0010000100";
WHEN "111101" => memoryC5_uid158_exp2TabGen_q <= "0000000110";
WHEN "111110" => memoryC5_uid158_exp2TabGen_q <= "1111111111";
WHEN "111111" => memoryC5_uid158_exp2TabGen_q <= "1111001001";
WHEN OTHERS =>
memoryC5_uid158_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid160_exp2TabGen(BITJOIN,159)@5
os_uid160_exp2TabGen_q <= memoryC5_uid159_exp2TabGen_q & memoryC5_uid158_exp2TabGen_q;
--reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1(REG,301)@5
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q <= os_uid160_exp2TabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid161_exp2PolyEval(BITSELECT,160)@5
yT1_uid161_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
yT1_uid161_exp2PolyEval_b <= yT1_uid161_exp2PolyEval_in(45 downto 28);
--reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0(REG,300)@5
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q <= yT1_uid161_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid192_pT1_uid162_exp2PolyEval(MULT,191)@6
prodXY_uid192_pT1_uid162_exp2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_a),19)) * SIGNED(prodXY_uid192_pT1_uid162_exp2PolyEval_b);
prodXY_uid192_pT1_uid162_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= (others => '0');
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_a <= reg_yT1_uid161_exp2PolyEval_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_0_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_b <= reg_os_uid160_exp2TabGen_0_to_prodXY_uid192_pT1_uid162_exp2PolyEval_1_q;
prodXY_uid192_pT1_uid162_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid192_pT1_uid162_exp2PolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid192_pT1_uid162_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid192_pT1_uid162_exp2PolyEval_q <= prodXY_uid192_pT1_uid162_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval(BITSELECT,192)@9
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in <= prodXY_uid192_pT1_uid162_exp2PolyEval_q;
prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_in(35 downto 17);
--highBBits_uid164_exp2PolyEval(BITSELECT,163)@9
highBBits_uid164_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b;
highBBits_uid164_exp2PolyEval_b <= highBBits_uid164_exp2PolyEval_in(18 downto 1);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a(DELAY,679)@4
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0(REG,304)@8
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid156_exp2TabGen(LOOKUP,155)@9
memoryC4_uid156_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid156_exp2TabGen_0_q) IS
WHEN "000000" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000001" => memoryC4_uid156_exp2TabGen_q <= "0010011";
WHEN "000010" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000011" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000100" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000101" => memoryC4_uid156_exp2TabGen_q <= "0010100";
WHEN "000110" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "000111" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001000" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001001" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001010" => memoryC4_uid156_exp2TabGen_q <= "0010101";
WHEN "001011" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001100" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001101" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001110" => memoryC4_uid156_exp2TabGen_q <= "0010110";
WHEN "001111" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010000" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010001" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010010" => memoryC4_uid156_exp2TabGen_q <= "0010111";
WHEN "010011" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010100" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010101" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010110" => memoryC4_uid156_exp2TabGen_q <= "0011000";
WHEN "010111" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011000" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011001" => memoryC4_uid156_exp2TabGen_q <= "0011001";
WHEN "011010" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011011" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011100" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011101" => memoryC4_uid156_exp2TabGen_q <= "0011010";
WHEN "011110" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "011111" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100000" => memoryC4_uid156_exp2TabGen_q <= "0011011";
WHEN "100001" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100010" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100011" => memoryC4_uid156_exp2TabGen_q <= "0011100";
WHEN "100100" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100101" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100110" => memoryC4_uid156_exp2TabGen_q <= "0011101";
WHEN "100111" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101000" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101001" => memoryC4_uid156_exp2TabGen_q <= "0011110";
WHEN "101010" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101011" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101100" => memoryC4_uid156_exp2TabGen_q <= "0011111";
WHEN "101101" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101110" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "101111" => memoryC4_uid156_exp2TabGen_q <= "0100000";
WHEN "110000" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110001" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110010" => memoryC4_uid156_exp2TabGen_q <= "0100001";
WHEN "110011" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110100" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110101" => memoryC4_uid156_exp2TabGen_q <= "0100010";
WHEN "110110" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "110111" => memoryC4_uid156_exp2TabGen_q <= "0100011";
WHEN "111000" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111001" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111010" => memoryC4_uid156_exp2TabGen_q <= "0100100";
WHEN "111011" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111100" => memoryC4_uid156_exp2TabGen_q <= "0100101";
WHEN "111101" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111110" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN "111111" => memoryC4_uid156_exp2TabGen_q <= "0100110";
WHEN OTHERS =>
memoryC4_uid156_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a(DELAY,513)@5
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid155_exp2TabGen(LOOKUP,154)@9
memoryC4_uid155_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid155_exp2TabGen_q <= "1011001010";
WHEN "000001" => memoryC4_uid155_exp2TabGen_q <= "1110100101";
WHEN "000010" => memoryC4_uid155_exp2TabGen_q <= "0010000100";
WHEN "000011" => memoryC4_uid155_exp2TabGen_q <= "0101100100";
WHEN "000100" => memoryC4_uid155_exp2TabGen_q <= "1001000111";
WHEN "000101" => memoryC4_uid155_exp2TabGen_q <= "1100101100";
WHEN "000110" => memoryC4_uid155_exp2TabGen_q <= "0000010100";
WHEN "000111" => memoryC4_uid155_exp2TabGen_q <= "0011111111";
WHEN "001000" => memoryC4_uid155_exp2TabGen_q <= "0111101011";
WHEN "001001" => memoryC4_uid155_exp2TabGen_q <= "1011011011";
WHEN "001010" => memoryC4_uid155_exp2TabGen_q <= "1111001101";
WHEN "001011" => memoryC4_uid155_exp2TabGen_q <= "0011000010";
WHEN "001100" => memoryC4_uid155_exp2TabGen_q <= "0110111001";
WHEN "001101" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "001110" => memoryC4_uid155_exp2TabGen_q <= "1110110000";
WHEN "001111" => memoryC4_uid155_exp2TabGen_q <= "0010110000";
WHEN "010000" => memoryC4_uid155_exp2TabGen_q <= "0110110010";
WHEN "010001" => memoryC4_uid155_exp2TabGen_q <= "1010110111";
WHEN "010010" => memoryC4_uid155_exp2TabGen_q <= "1110111111";
WHEN "010011" => memoryC4_uid155_exp2TabGen_q <= "0011001010";
WHEN "010100" => memoryC4_uid155_exp2TabGen_q <= "0111011000";
WHEN "010101" => memoryC4_uid155_exp2TabGen_q <= "1011101001";
WHEN "010110" => memoryC4_uid155_exp2TabGen_q <= "1111111101";
WHEN "010111" => memoryC4_uid155_exp2TabGen_q <= "0100010100";
WHEN "011000" => memoryC4_uid155_exp2TabGen_q <= "1000101101";
WHEN "011001" => memoryC4_uid155_exp2TabGen_q <= "1101001010";
WHEN "011010" => memoryC4_uid155_exp2TabGen_q <= "0001101010";
WHEN "011011" => memoryC4_uid155_exp2TabGen_q <= "0110001101";
WHEN "011100" => memoryC4_uid155_exp2TabGen_q <= "1010110011";
WHEN "011101" => memoryC4_uid155_exp2TabGen_q <= "1111011101";
WHEN "011110" => memoryC4_uid155_exp2TabGen_q <= "0100001010";
WHEN "011111" => memoryC4_uid155_exp2TabGen_q <= "1000111001";
WHEN "100000" => memoryC4_uid155_exp2TabGen_q <= "1101101101";
WHEN "100001" => memoryC4_uid155_exp2TabGen_q <= "0010100011";
WHEN "100010" => memoryC4_uid155_exp2TabGen_q <= "0111011101";
WHEN "100011" => memoryC4_uid155_exp2TabGen_q <= "1100011011";
WHEN "100100" => memoryC4_uid155_exp2TabGen_q <= "0001011100";
WHEN "100101" => memoryC4_uid155_exp2TabGen_q <= "0110100000";
WHEN "100110" => memoryC4_uid155_exp2TabGen_q <= "1011101000";
WHEN "100111" => memoryC4_uid155_exp2TabGen_q <= "0000110011";
WHEN "101000" => memoryC4_uid155_exp2TabGen_q <= "0110000011";
WHEN "101001" => memoryC4_uid155_exp2TabGen_q <= "1011010101";
WHEN "101010" => memoryC4_uid155_exp2TabGen_q <= "0000101100";
WHEN "101011" => memoryC4_uid155_exp2TabGen_q <= "0110000110";
WHEN "101100" => memoryC4_uid155_exp2TabGen_q <= "1011100100";
WHEN "101101" => memoryC4_uid155_exp2TabGen_q <= "0001000110";
WHEN "101110" => memoryC4_uid155_exp2TabGen_q <= "0110101011";
WHEN "101111" => memoryC4_uid155_exp2TabGen_q <= "1100010100";
WHEN "110000" => memoryC4_uid155_exp2TabGen_q <= "0010000010";
WHEN "110001" => memoryC4_uid155_exp2TabGen_q <= "0111110011";
WHEN "110010" => memoryC4_uid155_exp2TabGen_q <= "1101101001";
WHEN "110011" => memoryC4_uid155_exp2TabGen_q <= "0011100010";
WHEN "110100" => memoryC4_uid155_exp2TabGen_q <= "1001100000";
WHEN "110101" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN "110110" => memoryC4_uid155_exp2TabGen_q <= "0101101000";
WHEN "110111" => memoryC4_uid155_exp2TabGen_q <= "1011110010";
WHEN "111000" => memoryC4_uid155_exp2TabGen_q <= "0010000000";
WHEN "111001" => memoryC4_uid155_exp2TabGen_q <= "1000010011";
WHEN "111010" => memoryC4_uid155_exp2TabGen_q <= "1110101010";
WHEN "111011" => memoryC4_uid155_exp2TabGen_q <= "0101000110";
WHEN "111100" => memoryC4_uid155_exp2TabGen_q <= "1011100110";
WHEN "111101" => memoryC4_uid155_exp2TabGen_q <= "0010001011";
WHEN "111110" => memoryC4_uid155_exp2TabGen_q <= "1000110100";
WHEN "111111" => memoryC4_uid155_exp2TabGen_q <= "1111100010";
WHEN OTHERS =>
memoryC4_uid155_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC4_uid154_exp2TabGen(LOOKUP,153)@9
memoryC4_uid154_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC4_uid154_exp2TabGen_0_q_to_memoryC4_uid154_exp2TabGen_a_q) IS
WHEN "000000" => memoryC4_uid154_exp2TabGen_q <= "0110100100";
WHEN "000001" => memoryC4_uid154_exp2TabGen_q <= "1110100010";
WHEN "000010" => memoryC4_uid154_exp2TabGen_q <= "0010101101";
WHEN "000011" => memoryC4_uid154_exp2TabGen_q <= "0111111001";
WHEN "000100" => memoryC4_uid154_exp2TabGen_q <= "0111000100";
WHEN "000101" => memoryC4_uid154_exp2TabGen_q <= "1101000011";
WHEN "000110" => memoryC4_uid154_exp2TabGen_q <= "1010011101";
WHEN "000111" => memoryC4_uid154_exp2TabGen_q <= "0010001100";
WHEN "001000" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "001001" => memoryC4_uid154_exp2TabGen_q <= "1001010110";
WHEN "001010" => memoryC4_uid154_exp2TabGen_q <= "1010110111";
WHEN "001011" => memoryC4_uid154_exp2TabGen_q <= "0111101001";
WHEN "001100" => memoryC4_uid154_exp2TabGen_q <= "1100111100";
WHEN "001101" => memoryC4_uid154_exp2TabGen_q <= "1110011011";
WHEN "001110" => memoryC4_uid154_exp2TabGen_q <= "1011011110";
WHEN "001111" => memoryC4_uid154_exp2TabGen_q <= "0110011011";
WHEN "010000" => memoryC4_uid154_exp2TabGen_q <= "1010110110";
WHEN "010001" => memoryC4_uid154_exp2TabGen_q <= "1111010000";
WHEN "010010" => memoryC4_uid154_exp2TabGen_q <= "1111010101";
WHEN "010011" => memoryC4_uid154_exp2TabGen_q <= "1110100000";
WHEN "010100" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "010101" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "010110" => memoryC4_uid154_exp2TabGen_q <= "0100100001";
WHEN "010111" => memoryC4_uid154_exp2TabGen_q <= "0001010111";
WHEN "011000" => memoryC4_uid154_exp2TabGen_q <= "1100101100";
WHEN "011001" => memoryC4_uid154_exp2TabGen_q <= "1000011111";
WHEN "011010" => memoryC4_uid154_exp2TabGen_q <= "1001111100";
WHEN "011011" => memoryC4_uid154_exp2TabGen_q <= "1010011100";
WHEN "011100" => memoryC4_uid154_exp2TabGen_q <= "1110110011";
WHEN "011101" => memoryC4_uid154_exp2TabGen_q <= "0011111011";
WHEN "011110" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "011111" => memoryC4_uid154_exp2TabGen_q <= "1110000111";
WHEN "100000" => memoryC4_uid154_exp2TabGen_q <= "0010101110";
WHEN "100001" => memoryC4_uid154_exp2TabGen_q <= "1111101000";
WHEN "100010" => memoryC4_uid154_exp2TabGen_q <= "1110110001";
WHEN "100011" => memoryC4_uid154_exp2TabGen_q <= "0101101110";
WHEN "100100" => memoryC4_uid154_exp2TabGen_q <= "0011111100";
WHEN "100101" => memoryC4_uid154_exp2TabGen_q <= "0110100101";
WHEN "100110" => memoryC4_uid154_exp2TabGen_q <= "0110001011";
WHEN "100111" => memoryC4_uid154_exp2TabGen_q <= "1110100100";
WHEN "101000" => memoryC4_uid154_exp2TabGen_q <= "0000101101";
WHEN "101001" => memoryC4_uid154_exp2TabGen_q <= "1011010010";
WHEN "101010" => memoryC4_uid154_exp2TabGen_q <= "0011110100";
WHEN "101011" => memoryC4_uid154_exp2TabGen_q <= "0011111000";
WHEN "101100" => memoryC4_uid154_exp2TabGen_q <= "0100100100";
WHEN "101101" => memoryC4_uid154_exp2TabGen_q <= "0010001110";
WHEN "101110" => memoryC4_uid154_exp2TabGen_q <= "1000000001";
WHEN "101111" => memoryC4_uid154_exp2TabGen_q <= "1111111110";
WHEN "110000" => memoryC4_uid154_exp2TabGen_q <= "1000001111";
WHEN "110001" => memoryC4_uid154_exp2TabGen_q <= "1111101110";
WHEN "110010" => memoryC4_uid154_exp2TabGen_q <= "0011010011";
WHEN "110011" => memoryC4_uid154_exp2TabGen_q <= "1011100101";
WHEN "110100" => memoryC4_uid154_exp2TabGen_q <= "0101111010";
WHEN "110101" => memoryC4_uid154_exp2TabGen_q <= "0000001111";
WHEN "110110" => memoryC4_uid154_exp2TabGen_q <= "0001011000";
WHEN "110111" => memoryC4_uid154_exp2TabGen_q <= "0010100100";
WHEN "111000" => memoryC4_uid154_exp2TabGen_q <= "1010100101";
WHEN "111001" => memoryC4_uid154_exp2TabGen_q <= "0101110100";
WHEN "111010" => memoryC4_uid154_exp2TabGen_q <= "1101010000";
WHEN "111011" => memoryC4_uid154_exp2TabGen_q <= "0101111101";
WHEN "111100" => memoryC4_uid154_exp2TabGen_q <= "1000001001";
WHEN "111101" => memoryC4_uid154_exp2TabGen_q <= "0100011010";
WHEN "111110" => memoryC4_uid154_exp2TabGen_q <= "0101011101";
WHEN "111111" => memoryC4_uid154_exp2TabGen_q <= "0010110101";
WHEN OTHERS =>
memoryC4_uid154_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid157_exp2TabGen(BITJOIN,156)@9
os_uid157_exp2TabGen_q <= memoryC4_uid156_exp2TabGen_q & memoryC4_uid155_exp2TabGen_q & memoryC4_uid154_exp2TabGen_q;
--sumAHighB_uid165_exp2PolyEval(ADD,164)@9
sumAHighB_uid165_exp2PolyEval_a <= STD_LOGIC_VECTOR((27 downto 27 => os_uid157_exp2TabGen_q(26)) & os_uid157_exp2TabGen_q);
sumAHighB_uid165_exp2PolyEval_b <= STD_LOGIC_VECTOR((27 downto 18 => highBBits_uid164_exp2PolyEval_b(17)) & highBBits_uid164_exp2PolyEval_b);
sumAHighB_uid165_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid165_exp2PolyEval_a) + SIGNED(sumAHighB_uid165_exp2PolyEval_b));
sumAHighB_uid165_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_o(27 downto 0);
--lowRangeB_uid163_exp2PolyEval(BITSELECT,162)@9
lowRangeB_uid163_exp2PolyEval_in <= prodXYTruncFR_uid193_pT1_uid162_exp2PolyEval_b(0 downto 0);
lowRangeB_uid163_exp2PolyEval_b <= lowRangeB_uid163_exp2PolyEval_in(0 downto 0);
--s1_uid163_uid166_exp2PolyEval(BITJOIN,165)@9
s1_uid163_uid166_exp2PolyEval_q <= sumAHighB_uid165_exp2PolyEval_q & lowRangeB_uid163_exp2PolyEval_b;
--sSM0H_uid198_pT2_uid168_exp2PolyEval(BITSELECT,197)@9
sSM0H_uid198_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q(1 downto 0);
sSM0H_uid198_pT2_uid168_exp2PolyEval_b <= sSM0H_uid198_pT2_uid168_exp2PolyEval_in(1 downto 0);
--reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0(REG,307)@9
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q <= sSM0H_uid198_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid200_pT2_uid168_exp2PolyEval(MULT,199)@10
sm0_uid200_pT2_uid168_exp2PolyEval_pr <= UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_a) * UNSIGNED(sm0_uid200_pT2_uid168_exp2PolyEval_b);
sm0_uid200_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_b <= (others => '0');
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_a <= reg_sSM0H_uid198_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_0_q;
sm0_uid200_pT2_uid168_exp2PolyEval_b <= reg_sSM0W_uid199_pT2_uid168_exp2PolyEval_0_to_sm0_uid200_pT2_uid168_exp2PolyEval_1_q;
sm0_uid200_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid200_pT2_uid168_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid200_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid200_pT2_uid168_exp2PolyEval_q <= sm0_uid200_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--yTop27Bits_uid196_pT2_uid168_exp2PolyEval(BITSELECT,195)@9
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in <= s1_uid163_uid166_exp2PolyEval_q;
yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_in(28 downto 2);
--reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1(REG,306)@9
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q <= yTop27Bits_uid196_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0(REG,305)@9
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q <= yT2_uid167_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid197_pT2_uid168_exp2PolyEval(MULT,196)@10
topProd_uid197_pT2_uid168_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_a),28)) * SIGNED(topProd_uid197_pT2_uid168_exp2PolyEval_b);
topProd_uid197_pT2_uid168_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_b <= (others => '0');
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_0_q;
topProd_uid197_pT2_uid168_exp2PolyEval_b <= reg_yTop27Bits_uid196_pT2_uid168_exp2PolyEval_0_to_topProd_uid197_pT2_uid168_exp2PolyEval_1_q;
topProd_uid197_pT2_uid168_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid197_pT2_uid168_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid197_pT2_uid168_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid197_pT2_uid168_exp2PolyEval_q <= topProd_uid197_pT2_uid168_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--highABits_uid202_pT2_uid168_exp2PolyEval(BITSELECT,201)@13
highABits_uid202_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q;
highABits_uid202_pT2_uid168_exp2PolyEval_b <= highABits_uid202_pT2_uid168_exp2PolyEval_in(53 downto 20);
--sumHighA_B_uid203_pT2_uid168_exp2PolyEval(ADD,202)@13
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a <= STD_LOGIC_VECTOR((35 downto 34 => highABits_uid202_pT2_uid168_exp2PolyEval_b(33)) & highABits_uid202_pT2_uid168_exp2PolyEval_b);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000" & sm0_uid200_pT2_uid168_exp2PolyEval_q);
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_a) + SIGNED(sumHighA_B_uid203_pT2_uid168_exp2PolyEval_b));
sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_o(34 downto 0);
--lowRangeA_uid201_pT2_uid168_exp2PolyEval(BITSELECT,200)@13
lowRangeA_uid201_pT2_uid168_exp2PolyEval_in <= topProd_uid197_pT2_uid168_exp2PolyEval_q(19 downto 0);
lowRangeA_uid201_pT2_uid168_exp2PolyEval_b <= lowRangeA_uid201_pT2_uid168_exp2PolyEval_in(19 downto 0);
--add0_uid201_uid204_pT2_uid168_exp2PolyEval(BITJOIN,203)@13
add0_uid201_uid204_pT2_uid168_exp2PolyEval_q <= sumHighA_B_uid203_pT2_uid168_exp2PolyEval_q & lowRangeA_uid201_pT2_uid168_exp2PolyEval_b;
--R_uid205_pT2_uid168_exp2PolyEval(BITSELECT,204)@13
R_uid205_pT2_uid168_exp2PolyEval_in <= add0_uid201_uid204_pT2_uid168_exp2PolyEval_q(53 downto 0);
R_uid205_pT2_uid168_exp2PolyEval_b <= R_uid205_pT2_uid168_exp2PolyEval_in(53 downto 23);
--reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1(REG,310)@13
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q <= R_uid205_pT2_uid168_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor(LOGICAL,917)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top(CONSTANT,798)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q <= "0101";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp(LOGICAL,799)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg(REG,800)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena(REG,918)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd(LOGICAL,919)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg(DELAY,868)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => addr_uid47_fpExp2Test_b, xout => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt(COUNTER,794)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i = 4 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i - 5;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg(REG,795)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux(MUX,796)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem(DUALMEM,908)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0(REG,294)@12
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid152_exp2TabGen(LOOKUP,151)@13
memoryC3_uid152_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000001" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000010" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000011" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000100" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000101" => memoryC3_uid152_exp2TabGen_q <= "001110";
WHEN "000110" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "000111" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001000" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001001" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001010" => memoryC3_uid152_exp2TabGen_q <= "001111";
WHEN "001011" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001100" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001101" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001110" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "001111" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010000" => memoryC3_uid152_exp2TabGen_q <= "010000";
WHEN "010001" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010010" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010011" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010100" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010101" => memoryC3_uid152_exp2TabGen_q <= "010001";
WHEN "010110" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "010111" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011000" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011001" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011010" => memoryC3_uid152_exp2TabGen_q <= "010010";
WHEN "011011" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011100" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011101" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011110" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "011111" => memoryC3_uid152_exp2TabGen_q <= "010011";
WHEN "100000" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100001" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100010" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100011" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100100" => memoryC3_uid152_exp2TabGen_q <= "010100";
WHEN "100101" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100110" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "100111" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101000" => memoryC3_uid152_exp2TabGen_q <= "010101";
WHEN "101001" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101010" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101011" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101100" => memoryC3_uid152_exp2TabGen_q <= "010110";
WHEN "101101" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101110" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "101111" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110000" => memoryC3_uid152_exp2TabGen_q <= "010111";
WHEN "110001" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110010" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110011" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110100" => memoryC3_uid152_exp2TabGen_q <= "011000";
WHEN "110101" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110110" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "110111" => memoryC3_uid152_exp2TabGen_q <= "011001";
WHEN "111000" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111001" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111010" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111011" => memoryC3_uid152_exp2TabGen_q <= "011010";
WHEN "111100" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111101" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111110" => memoryC3_uid152_exp2TabGen_q <= "011011";
WHEN "111111" => memoryC3_uid152_exp2TabGen_q <= "011100";
WHEN OTHERS =>
memoryC3_uid152_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid151_exp2TabGen(LOOKUP,150)@13
memoryC3_uid151_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid151_exp2TabGen_q <= "0011010110";
WHEN "000001" => memoryC3_uid151_exp2TabGen_q <= "0101110100";
WHEN "000010" => memoryC3_uid151_exp2TabGen_q <= "1000010100";
WHEN "000011" => memoryC3_uid151_exp2TabGen_q <= "1010110110";
WHEN "000100" => memoryC3_uid151_exp2TabGen_q <= "1101011010";
WHEN "000101" => memoryC3_uid151_exp2TabGen_q <= "1111111111";
WHEN "000110" => memoryC3_uid151_exp2TabGen_q <= "0010100110";
WHEN "000111" => memoryC3_uid151_exp2TabGen_q <= "0101010000";
WHEN "001000" => memoryC3_uid151_exp2TabGen_q <= "0111111010";
WHEN "001001" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "001010" => memoryC3_uid151_exp2TabGen_q <= "1101010110";
WHEN "001011" => memoryC3_uid151_exp2TabGen_q <= "0000000110";
WHEN "001100" => memoryC3_uid151_exp2TabGen_q <= "0010111001";
WHEN "001101" => memoryC3_uid151_exp2TabGen_q <= "0101101101";
WHEN "001110" => memoryC3_uid151_exp2TabGen_q <= "1000100100";
WHEN "001111" => memoryC3_uid151_exp2TabGen_q <= "1011011100";
WHEN "010000" => memoryC3_uid151_exp2TabGen_q <= "1110010111";
WHEN "010001" => memoryC3_uid151_exp2TabGen_q <= "0001010011";
WHEN "010010" => memoryC3_uid151_exp2TabGen_q <= "0100010001";
WHEN "010011" => memoryC3_uid151_exp2TabGen_q <= "0111010010";
WHEN "010100" => memoryC3_uid151_exp2TabGen_q <= "1010010101";
WHEN "010101" => memoryC3_uid151_exp2TabGen_q <= "1101011001";
WHEN "010110" => memoryC3_uid151_exp2TabGen_q <= "0000100000";
WHEN "010111" => memoryC3_uid151_exp2TabGen_q <= "0011101001";
WHEN "011000" => memoryC3_uid151_exp2TabGen_q <= "0110110101";
WHEN "011001" => memoryC3_uid151_exp2TabGen_q <= "1010000010";
WHEN "011010" => memoryC3_uid151_exp2TabGen_q <= "1101010010";
WHEN "011011" => memoryC3_uid151_exp2TabGen_q <= "0000100100";
WHEN "011100" => memoryC3_uid151_exp2TabGen_q <= "0011111000";
WHEN "011101" => memoryC3_uid151_exp2TabGen_q <= "0111001111";
WHEN "011110" => memoryC3_uid151_exp2TabGen_q <= "1010100111";
WHEN "011111" => memoryC3_uid151_exp2TabGen_q <= "1110000011";
WHEN "100000" => memoryC3_uid151_exp2TabGen_q <= "0001100000";
WHEN "100001" => memoryC3_uid151_exp2TabGen_q <= "0101000000";
WHEN "100010" => memoryC3_uid151_exp2TabGen_q <= "1000100011";
WHEN "100011" => memoryC3_uid151_exp2TabGen_q <= "1100001000";
WHEN "100100" => memoryC3_uid151_exp2TabGen_q <= "1111101111";
WHEN "100101" => memoryC3_uid151_exp2TabGen_q <= "0011011001";
WHEN "100110" => memoryC3_uid151_exp2TabGen_q <= "0111000110";
WHEN "100111" => memoryC3_uid151_exp2TabGen_q <= "1010110101";
WHEN "101000" => memoryC3_uid151_exp2TabGen_q <= "1110100111";
WHEN "101001" => memoryC3_uid151_exp2TabGen_q <= "0010011011";
WHEN "101010" => memoryC3_uid151_exp2TabGen_q <= "0110010010";
WHEN "101011" => memoryC3_uid151_exp2TabGen_q <= "1010001100";
WHEN "101100" => memoryC3_uid151_exp2TabGen_q <= "1110001000";
WHEN "101101" => memoryC3_uid151_exp2TabGen_q <= "0010000111";
WHEN "101110" => memoryC3_uid151_exp2TabGen_q <= "0110001001";
WHEN "101111" => memoryC3_uid151_exp2TabGen_q <= "1010001110";
WHEN "110000" => memoryC3_uid151_exp2TabGen_q <= "1110010110";
WHEN "110001" => memoryC3_uid151_exp2TabGen_q <= "0010100000";
WHEN "110010" => memoryC3_uid151_exp2TabGen_q <= "0110101110";
WHEN "110011" => memoryC3_uid151_exp2TabGen_q <= "1010111110";
WHEN "110100" => memoryC3_uid151_exp2TabGen_q <= "1111010001";
WHEN "110101" => memoryC3_uid151_exp2TabGen_q <= "0011100111";
WHEN "110110" => memoryC3_uid151_exp2TabGen_q <= "1000000001";
WHEN "110111" => memoryC3_uid151_exp2TabGen_q <= "1100011101";
WHEN "111000" => memoryC3_uid151_exp2TabGen_q <= "0000111100";
WHEN "111001" => memoryC3_uid151_exp2TabGen_q <= "0101011111";
WHEN "111010" => memoryC3_uid151_exp2TabGen_q <= "1010000101";
WHEN "111011" => memoryC3_uid151_exp2TabGen_q <= "1110101110";
WHEN "111100" => memoryC3_uid151_exp2TabGen_q <= "0011011010";
WHEN "111101" => memoryC3_uid151_exp2TabGen_q <= "1000001001";
WHEN "111110" => memoryC3_uid151_exp2TabGen_q <= "1100111100";
WHEN "111111" => memoryC3_uid151_exp2TabGen_q <= "0001110010";
WHEN OTHERS =>
memoryC3_uid151_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor(LOGICAL,802)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena(REG,803)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd(LOGICAL,804)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg(DELAY,740)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q, xout => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem(DUALMEM,793)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 6,
width_b => 6,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC3_uid150_exp2TabGen(LOOKUP,149)@13
memoryC3_uid150_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid150_exp2TabGen_0_q_to_memoryC3_uid150_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC3_uid150_exp2TabGen_q <= "0001000110";
WHEN "000001" => memoryC3_uid150_exp2TabGen_q <= "1000001001";
WHEN "000010" => memoryC3_uid150_exp2TabGen_q <= "1010110010";
WHEN "000011" => memoryC3_uid150_exp2TabGen_q <= "1001010101";
WHEN "000100" => memoryC3_uid150_exp2TabGen_q <= "0100000110";
WHEN "000101" => memoryC3_uid150_exp2TabGen_q <= "1011010111";
WHEN "000110" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "000111" => memoryC3_uid150_exp2TabGen_q <= "0000101101";
WHEN "001000" => memoryC3_uid150_exp2TabGen_q <= "1111011010";
WHEN "001001" => memoryC3_uid150_exp2TabGen_q <= "1011111000";
WHEN "001010" => memoryC3_uid150_exp2TabGen_q <= "0110011101";
WHEN "001011" => memoryC3_uid150_exp2TabGen_q <= "1111011110";
WHEN "001100" => memoryC3_uid150_exp2TabGen_q <= "0111010000";
WHEN "001101" => memoryC3_uid150_exp2TabGen_q <= "1110001000";
WHEN "001110" => memoryC3_uid150_exp2TabGen_q <= "0100011100";
WHEN "001111" => memoryC3_uid150_exp2TabGen_q <= "1010100001";
WHEN "010000" => memoryC3_uid150_exp2TabGen_q <= "0000101111";
WHEN "010001" => memoryC3_uid150_exp2TabGen_q <= "0111011011";
WHEN "010010" => memoryC3_uid150_exp2TabGen_q <= "1110111011";
WHEN "010011" => memoryC3_uid150_exp2TabGen_q <= "0111101000";
WHEN "010100" => memoryC3_uid150_exp2TabGen_q <= "0001110111";
WHEN "010101" => memoryC3_uid150_exp2TabGen_q <= "1110000001";
WHEN "010110" => memoryC3_uid150_exp2TabGen_q <= "1100011110";
WHEN "010111" => memoryC3_uid150_exp2TabGen_q <= "1101100011";
WHEN "011000" => memoryC3_uid150_exp2TabGen_q <= "0001101011";
WHEN "011001" => memoryC3_uid150_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC3_uid150_exp2TabGen_q <= "0100100011";
WHEN "011011" => memoryC3_uid150_exp2TabGen_q <= "0100000101";
WHEN "011100" => memoryC3_uid150_exp2TabGen_q <= "1000001100";
WHEN "011101" => memoryC3_uid150_exp2TabGen_q <= "0001010010";
WHEN "011110" => memoryC3_uid150_exp2TabGen_q <= "1111110000";
WHEN "011111" => memoryC3_uid150_exp2TabGen_q <= "0100000001";
WHEN "100000" => memoryC3_uid150_exp2TabGen_q <= "1110011111";
WHEN "100001" => memoryC3_uid150_exp2TabGen_q <= "1111100100";
WHEN "100010" => memoryC3_uid150_exp2TabGen_q <= "0111101100";
WHEN "100011" => memoryC3_uid150_exp2TabGen_q <= "0111010010";
WHEN "100100" => memoryC3_uid150_exp2TabGen_q <= "1110110000";
WHEN "100101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "100110" => memoryC3_uid150_exp2TabGen_q <= "0111001001";
WHEN "100111" => memoryC3_uid150_exp2TabGen_q <= "1000111100";
WHEN "101000" => memoryC3_uid150_exp2TabGen_q <= "0100011000";
WHEN "101001" => memoryC3_uid150_exp2TabGen_q <= "1001111101";
WHEN "101010" => memoryC3_uid150_exp2TabGen_q <= "1010000101";
WHEN "101011" => memoryC3_uid150_exp2TabGen_q <= "0101010000";
WHEN "101100" => memoryC3_uid150_exp2TabGen_q <= "1011111011";
WHEN "101101" => memoryC3_uid150_exp2TabGen_q <= "1110100101";
WHEN "101110" => memoryC3_uid150_exp2TabGen_q <= "1101101100";
WHEN "101111" => memoryC3_uid150_exp2TabGen_q <= "1001110000";
WHEN "110000" => memoryC3_uid150_exp2TabGen_q <= "0011001111";
WHEN "110001" => memoryC3_uid150_exp2TabGen_q <= "1010101001";
WHEN "110010" => memoryC3_uid150_exp2TabGen_q <= "0000011110";
WHEN "110011" => memoryC3_uid150_exp2TabGen_q <= "0101001111";
WHEN "110100" => memoryC3_uid150_exp2TabGen_q <= "1001011100";
WHEN "110101" => memoryC3_uid150_exp2TabGen_q <= "1101100111";
WHEN "110110" => memoryC3_uid150_exp2TabGen_q <= "0010010000";
WHEN "110111" => memoryC3_uid150_exp2TabGen_q <= "0111111010";
WHEN "111000" => memoryC3_uid150_exp2TabGen_q <= "1111000111";
WHEN "111001" => memoryC3_uid150_exp2TabGen_q <= "1000011001";
WHEN "111010" => memoryC3_uid150_exp2TabGen_q <= "0100010011";
WHEN "111011" => memoryC3_uid150_exp2TabGen_q <= "0011011000";
WHEN "111100" => memoryC3_uid150_exp2TabGen_q <= "0110001101";
WHEN "111101" => memoryC3_uid150_exp2TabGen_q <= "1101010101";
WHEN "111110" => memoryC3_uid150_exp2TabGen_q <= "1001010100";
WHEN "111111" => memoryC3_uid150_exp2TabGen_q <= "1010110000";
WHEN OTHERS =>
memoryC3_uid150_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC3_uid149_exp2TabGen(LOOKUP,148)@13
memoryC3_uid149_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC3_uid149_exp2TabGen_0_q) IS
WHEN "000000" => memoryC3_uid149_exp2TabGen_q <= "1111110111";
WHEN "000001" => memoryC3_uid149_exp2TabGen_q <= "1011000100";
WHEN "000010" => memoryC3_uid149_exp2TabGen_q <= "0110011000";
WHEN "000011" => memoryC3_uid149_exp2TabGen_q <= "1011011000";
WHEN "000100" => memoryC3_uid149_exp2TabGen_q <= "0001000100";
WHEN "000101" => memoryC3_uid149_exp2TabGen_q <= "1001000100";
WHEN "000110" => memoryC3_uid149_exp2TabGen_q <= "0000101011";
WHEN "000111" => memoryC3_uid149_exp2TabGen_q <= "0100011100";
WHEN "001000" => memoryC3_uid149_exp2TabGen_q <= "0011001110";
WHEN "001001" => memoryC3_uid149_exp2TabGen_q <= "1011100001";
WHEN "001010" => memoryC3_uid149_exp2TabGen_q <= "1111101000";
WHEN "001011" => memoryC3_uid149_exp2TabGen_q <= "1100000000";
WHEN "001100" => memoryC3_uid149_exp2TabGen_q <= "1000101010";
WHEN "001101" => memoryC3_uid149_exp2TabGen_q <= "0110100001";
WHEN "001110" => memoryC3_uid149_exp2TabGen_q <= "0011011110";
WHEN "001111" => memoryC3_uid149_exp2TabGen_q <= "1001011101";
WHEN "010000" => memoryC3_uid149_exp2TabGen_q <= "0100111011";
WHEN "010001" => memoryC3_uid149_exp2TabGen_q <= "0000011100";
WHEN "010010" => memoryC3_uid149_exp2TabGen_q <= "1110001001";
WHEN "010011" => memoryC3_uid149_exp2TabGen_q <= "1000100011";
WHEN "010100" => memoryC3_uid149_exp2TabGen_q <= "1101001001";
WHEN "010101" => memoryC3_uid149_exp2TabGen_q <= "1111010110";
WHEN "010110" => memoryC3_uid149_exp2TabGen_q <= "0001111011";
WHEN "010111" => memoryC3_uid149_exp2TabGen_q <= "1101111000";
WHEN "011000" => memoryC3_uid149_exp2TabGen_q <= "1111000011";
WHEN "011001" => memoryC3_uid149_exp2TabGen_q <= "1000101110";
WHEN "011010" => memoryC3_uid149_exp2TabGen_q <= "1100101000";
WHEN "011011" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "011100" => memoryC3_uid149_exp2TabGen_q <= "0100111101";
WHEN "011101" => memoryC3_uid149_exp2TabGen_q <= "0100101101";
WHEN "011110" => memoryC3_uid149_exp2TabGen_q <= "0001101111";
WHEN "011111" => memoryC3_uid149_exp2TabGen_q <= "0111110111";
WHEN "100000" => memoryC3_uid149_exp2TabGen_q <= "0101000011";
WHEN "100001" => memoryC3_uid149_exp2TabGen_q <= "0101101110";
WHEN "100010" => memoryC3_uid149_exp2TabGen_q <= "0110101000";
WHEN "100011" => memoryC3_uid149_exp2TabGen_q <= "0000101111";
WHEN "100100" => memoryC3_uid149_exp2TabGen_q <= "1101100001";
WHEN "100101" => memoryC3_uid149_exp2TabGen_q <= "0001101011";
WHEN "100110" => memoryC3_uid149_exp2TabGen_q <= "1111000110";
WHEN "100111" => memoryC3_uid149_exp2TabGen_q <= "0101010000";
WHEN "101000" => memoryC3_uid149_exp2TabGen_q <= "1111100011";
WHEN "101001" => memoryC3_uid149_exp2TabGen_q <= "0010100101";
WHEN "101010" => memoryC3_uid149_exp2TabGen_q <= "1000111101";
WHEN "101011" => memoryC3_uid149_exp2TabGen_q <= "1101001000";
WHEN "101100" => memoryC3_uid149_exp2TabGen_q <= "1101001101";
WHEN "101101" => memoryC3_uid149_exp2TabGen_q <= "0111010010";
WHEN "101110" => memoryC3_uid149_exp2TabGen_q <= "1111111100";
WHEN "101111" => memoryC3_uid149_exp2TabGen_q <= "0100110000";
WHEN "110000" => memoryC3_uid149_exp2TabGen_q <= "0000100001";
WHEN "110001" => memoryC3_uid149_exp2TabGen_q <= "0000100000";
WHEN "110010" => memoryC3_uid149_exp2TabGen_q <= "1100011000";
WHEN "110011" => memoryC3_uid149_exp2TabGen_q <= "1010011100";
WHEN "110100" => memoryC3_uid149_exp2TabGen_q <= "1101000110";
WHEN "110101" => memoryC3_uid149_exp2TabGen_q <= "1001101101";
WHEN "110110" => memoryC3_uid149_exp2TabGen_q <= "1011011101";
WHEN "110111" => memoryC3_uid149_exp2TabGen_q <= "1111000100";
WHEN "111000" => memoryC3_uid149_exp2TabGen_q <= "1000111001";
WHEN "111001" => memoryC3_uid149_exp2TabGen_q <= "1011001100";
WHEN "111010" => memoryC3_uid149_exp2TabGen_q <= "0100101100";
WHEN "111011" => memoryC3_uid149_exp2TabGen_q <= "1111111110";
WHEN "111100" => memoryC3_uid149_exp2TabGen_q <= "1001001101";
WHEN "111101" => memoryC3_uid149_exp2TabGen_q <= "0001110100";
WHEN "111110" => memoryC3_uid149_exp2TabGen_q <= "1100110001";
WHEN "111111" => memoryC3_uid149_exp2TabGen_q <= "1010111000";
WHEN OTHERS =>
memoryC3_uid149_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid153_exp2TabGen(BITJOIN,152)@13
os_uid153_exp2TabGen_q <= memoryC3_uid152_exp2TabGen_q & memoryC3_uid151_exp2TabGen_q & memoryC3_uid150_exp2TabGen_q & memoryC3_uid149_exp2TabGen_q;
--rndBit_uid169_exp2PolyEval(CONSTANT,168)
rndBit_uid169_exp2PolyEval_q <= "01";
--cIncludingRoundingBit_uid170_exp2PolyEval(BITJOIN,169)@13
cIncludingRoundingBit_uid170_exp2PolyEval_q <= os_uid153_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0(REG,309)@13
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q <= cIncludingRoundingBit_uid170_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid171_exp2PolyEval(ADD,170)@14
ts2_uid171_exp2PolyEval_a <= STD_LOGIC_VECTOR((38 downto 38 => reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q(37)) & reg_cIncludingRoundingBit_uid170_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_0_q);
ts2_uid171_exp2PolyEval_b <= STD_LOGIC_VECTOR((38 downto 31 => reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q(30)) & reg_R_uid205_pT2_uid168_exp2PolyEval_0_to_ts2_uid171_exp2PolyEval_1_q);
ts2_uid171_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid171_exp2PolyEval_a) + SIGNED(ts2_uid171_exp2PolyEval_b));
ts2_uid171_exp2PolyEval_q <= ts2_uid171_exp2PolyEval_o(38 downto 0);
--s2_uid172_exp2PolyEval(BITSELECT,171)@14
s2_uid172_exp2PolyEval_in <= ts2_uid171_exp2PolyEval_q;
s2_uid172_exp2PolyEval_b <= s2_uid172_exp2PolyEval_in(38 downto 1);
--yTop18Bits_uid212_pT3_uid174_exp2PolyEval(BITSELECT,211)@14
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_in(37 downto 20);
--reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9(REG,314)@14
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q <= yTop18Bits_uid212_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor(LOGICAL,826)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top(CONSTANT,822)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q <= "0110";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp(LOGICAL,823)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg(REG,824)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena(REG,827)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd(LOGICAL,828)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt(COUNTER,818)
-- every=1, low=0, high=6, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i = 5 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_i,3));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg(REG,819)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux(MUX,820)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem(DUALMEM,817)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 3,
numwords_a => 7,
width_b => 46,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT3_uid173_exp2PolyEval(BITSELECT,172)@14
yT3_uid173_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT3_uid173_exp2PolyEval_a_replace_mem_q;
yT3_uid173_exp2PolyEval_b <= yT3_uid173_exp2PolyEval_in(45 downto 10);
--xBottomBits_uid211_pT3_uid174_exp2PolyEval(BITSELECT,210)@14
xBottomBits_uid211_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b(8 downto 0);
xBottomBits_uid211_pT3_uid174_exp2PolyEval_b <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_in(8 downto 0);
--pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval(BITJOIN,213)@14
pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q <= xBottomBits_uid211_pT3_uid174_exp2PolyEval_b & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7(REG,313)@14
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid210_pT3_uid174_exp2PolyEval(BITSELECT,209)@14
yBottomBits_uid210_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b(10 downto 0);
yBottomBits_uid210_pT3_uid174_exp2PolyEval_b <= yBottomBits_uid210_pT3_uid174_exp2PolyEval_in(10 downto 0);
--spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval(BITJOIN,212)@14
spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q <= GND_q & yBottomBits_uid210_pT3_uid174_exp2PolyEval_b;
--pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval(BITJOIN,214)@14
pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q <= spad_yBottomBits_uid210_uid213_pT3_uid174_exp2PolyEval_q & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6(REG,312)@14
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid209_pT3_uid174_exp2PolyEval(BITSELECT,208)@14
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_in(35 downto 18);
--reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4(REG,311)@14
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q <= xTop18Bits_uid209_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma(CHAINMULTADD,259)@15
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1),19));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(0) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_l(1) * multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_p(1),38);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_w(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_x(0);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid209_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_4_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid211_uid214_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_7_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid210_uid215_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_6_q),18);
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid212_pT3_uid174_exp2PolyEval_0_to_multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0) <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval(BITSELECT,216)@18
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_cma_q;
multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_in(36 downto 6);
--highBBits_uid219_pT3_uid174_exp2PolyEval(BITSELECT,218)@18
highBBits_uid219_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b;
highBBits_uid219_pT3_uid174_exp2PolyEval_b <= highBBits_uid219_pT3_uid174_exp2PolyEval_in(30 downto 2);
--yTop27Bits_uid207_pT3_uid174_exp2PolyEval(BITSELECT,206)@14
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in <= s2_uid172_exp2PolyEval_b;
yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_in(37 downto 11);
--reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1(REG,316)@14
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q <= yTop27Bits_uid207_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid206_pT3_uid174_exp2PolyEval(BITSELECT,205)@14
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in <= yT3_uid173_exp2PolyEval_b;
xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_in(35 downto 9);
--reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0(REG,315)@14
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q <= xTop27Bits_uid206_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid208_pT3_uid174_exp2PolyEval(MULT,207)@15
topProd_uid208_pT3_uid174_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_a),28)) * SIGNED(topProd_uid208_pT3_uid174_exp2PolyEval_b);
topProd_uid208_pT3_uid174_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_b <= (others => '0');
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_a <= reg_xTop27Bits_uid206_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_0_q;
topProd_uid208_pT3_uid174_exp2PolyEval_b <= reg_yTop27Bits_uid207_pT3_uid174_exp2PolyEval_0_to_topProd_uid208_pT3_uid174_exp2PolyEval_1_q;
topProd_uid208_pT3_uid174_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid208_pT3_uid174_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid208_pT3_uid174_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid208_pT3_uid174_exp2PolyEval_q <= topProd_uid208_pT3_uid174_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid220_pT3_uid174_exp2PolyEval(ADD,219)@18
sumAHighB_uid220_pT3_uid174_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid208_pT3_uid174_exp2PolyEval_q(53)) & topProd_uid208_pT3_uid174_exp2PolyEval_q);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid219_pT3_uid174_exp2PolyEval_b(28)) & highBBits_uid219_pT3_uid174_exp2PolyEval_b);
sumAHighB_uid220_pT3_uid174_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_a) + SIGNED(sumAHighB_uid220_pT3_uid174_exp2PolyEval_b));
sumAHighB_uid220_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid218_pT3_uid174_exp2PolyEval(BITSELECT,217)@18
lowRangeB_uid218_pT3_uid174_exp2PolyEval_in <= multSumOfTwo18_uid213_pT3_uid174_exp2PolyEval_b(1 downto 0);
lowRangeB_uid218_pT3_uid174_exp2PolyEval_b <= lowRangeB_uid218_pT3_uid174_exp2PolyEval_in(1 downto 0);
--add0_uid218_uid221_pT3_uid174_exp2PolyEval(BITJOIN,220)@18
add0_uid218_uid221_pT3_uid174_exp2PolyEval_q <= sumAHighB_uid220_pT3_uid174_exp2PolyEval_q & lowRangeB_uid218_pT3_uid174_exp2PolyEval_b;
--R_uid222_pT3_uid174_exp2PolyEval(BITSELECT,221)@18
R_uid222_pT3_uid174_exp2PolyEval_in <= add0_uid218_uid221_pT3_uid174_exp2PolyEval_q(55 downto 0);
R_uid222_pT3_uid174_exp2PolyEval_b <= R_uid222_pT3_uid174_exp2PolyEval_in(55 downto 18);
--reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1(REG,318)@18
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q <= R_uid222_pT3_uid174_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor(LOGICAL,789)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q <= not (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_a or ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top(CONSTANT,772)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q <= "01010";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp(LOGICAL,773)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg(REG,774)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena(REG,790)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_nor_q = "1") THEN
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd(LOGICAL,791)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_sticky_ena_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b <= en;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_a and ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_b;
--memoryC2_uid147_exp2TabGen(LOOKUP,146)@5
memoryC2_uid147_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000001" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000010" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000011" => memoryC2_uid147_exp2TabGen_q <= "001";
WHEN "000100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "000111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "001111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "010111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "011111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100010" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100011" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100100" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100101" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100110" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "100111" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101000" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101001" => memoryC2_uid147_exp2TabGen_q <= "010";
WHEN "101010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "101111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "110111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111000" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111001" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111010" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111011" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111100" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111101" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111110" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN "111111" => memoryC2_uid147_exp2TabGen_q <= "011";
WHEN OTHERS =>
memoryC2_uid147_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg(DELAY,779)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid147_exp2TabGen_q, xout => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt(COUNTER,768)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i = 9 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i - 10;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg(REG,769)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux(MUX,770)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem(DUALMEM,780)
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_inputreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 11,
width_b => 3,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq,
address_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_aa,
data_a => ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_ia
);
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_reset0 <= areset;
ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_iq(2 downto 0);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor(LOGICAL,904)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena(REG,905)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd(LOGICAL,906)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem(DUALMEM,895)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0(REG,292)@17
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid146_exp2TabGen(LOOKUP,145)@18
memoryC2_uid146_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid146_exp2TabGen_0_q) IS
WHEN "000000" => memoryC2_uid146_exp2TabGen_q <= "1110101111";
WHEN "000001" => memoryC2_uid146_exp2TabGen_q <= "1111000101";
WHEN "000010" => memoryC2_uid146_exp2TabGen_q <= "1111011011";
WHEN "000011" => memoryC2_uid146_exp2TabGen_q <= "1111110000";
WHEN "000100" => memoryC2_uid146_exp2TabGen_q <= "0000000111";
WHEN "000101" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "000110" => memoryC2_uid146_exp2TabGen_q <= "0000110100";
WHEN "000111" => memoryC2_uid146_exp2TabGen_q <= "0001001010";
WHEN "001000" => memoryC2_uid146_exp2TabGen_q <= "0001100010";
WHEN "001001" => memoryC2_uid146_exp2TabGen_q <= "0001111001";
WHEN "001010" => memoryC2_uid146_exp2TabGen_q <= "0010010001";
WHEN "001011" => memoryC2_uid146_exp2TabGen_q <= "0010101000";
WHEN "001100" => memoryC2_uid146_exp2TabGen_q <= "0011000001";
WHEN "001101" => memoryC2_uid146_exp2TabGen_q <= "0011011001";
WHEN "001110" => memoryC2_uid146_exp2TabGen_q <= "0011110010";
WHEN "001111" => memoryC2_uid146_exp2TabGen_q <= "0100001011";
WHEN "010000" => memoryC2_uid146_exp2TabGen_q <= "0100100100";
WHEN "010001" => memoryC2_uid146_exp2TabGen_q <= "0100111101";
WHEN "010010" => memoryC2_uid146_exp2TabGen_q <= "0101010111";
WHEN "010011" => memoryC2_uid146_exp2TabGen_q <= "0101110001";
WHEN "010100" => memoryC2_uid146_exp2TabGen_q <= "0110001011";
WHEN "010101" => memoryC2_uid146_exp2TabGen_q <= "0110100110";
WHEN "010110" => memoryC2_uid146_exp2TabGen_q <= "0111000001";
WHEN "010111" => memoryC2_uid146_exp2TabGen_q <= "0111011100";
WHEN "011000" => memoryC2_uid146_exp2TabGen_q <= "0111111000";
WHEN "011001" => memoryC2_uid146_exp2TabGen_q <= "1000010011";
WHEN "011010" => memoryC2_uid146_exp2TabGen_q <= "1000101111";
WHEN "011011" => memoryC2_uid146_exp2TabGen_q <= "1001001100";
WHEN "011100" => memoryC2_uid146_exp2TabGen_q <= "1001101001";
WHEN "011101" => memoryC2_uid146_exp2TabGen_q <= "1010000110";
WHEN "011110" => memoryC2_uid146_exp2TabGen_q <= "1010100011";
WHEN "011111" => memoryC2_uid146_exp2TabGen_q <= "1011000001";
WHEN "100000" => memoryC2_uid146_exp2TabGen_q <= "1011011111";
WHEN "100001" => memoryC2_uid146_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC2_uid146_exp2TabGen_q <= "1100011100";
WHEN "100011" => memoryC2_uid146_exp2TabGen_q <= "1100111010";
WHEN "100100" => memoryC2_uid146_exp2TabGen_q <= "1101011010";
WHEN "100101" => memoryC2_uid146_exp2TabGen_q <= "1101111001";
WHEN "100110" => memoryC2_uid146_exp2TabGen_q <= "1110011001";
WHEN "100111" => memoryC2_uid146_exp2TabGen_q <= "1110111010";
WHEN "101000" => memoryC2_uid146_exp2TabGen_q <= "1111011010";
WHEN "101001" => memoryC2_uid146_exp2TabGen_q <= "1111111100";
WHEN "101010" => memoryC2_uid146_exp2TabGen_q <= "0000011101";
WHEN "101011" => memoryC2_uid146_exp2TabGen_q <= "0000111111";
WHEN "101100" => memoryC2_uid146_exp2TabGen_q <= "0001100001";
WHEN "101101" => memoryC2_uid146_exp2TabGen_q <= "0010000011";
WHEN "101110" => memoryC2_uid146_exp2TabGen_q <= "0010100110";
WHEN "101111" => memoryC2_uid146_exp2TabGen_q <= "0011001010";
WHEN "110000" => memoryC2_uid146_exp2TabGen_q <= "0011101101";
WHEN "110001" => memoryC2_uid146_exp2TabGen_q <= "0100010001";
WHEN "110010" => memoryC2_uid146_exp2TabGen_q <= "0100110110";
WHEN "110011" => memoryC2_uid146_exp2TabGen_q <= "0101011010";
WHEN "110100" => memoryC2_uid146_exp2TabGen_q <= "0110000000";
WHEN "110101" => memoryC2_uid146_exp2TabGen_q <= "0110100101";
WHEN "110110" => memoryC2_uid146_exp2TabGen_q <= "0111001011";
WHEN "110111" => memoryC2_uid146_exp2TabGen_q <= "0111110010";
WHEN "111000" => memoryC2_uid146_exp2TabGen_q <= "1000011001";
WHEN "111001" => memoryC2_uid146_exp2TabGen_q <= "1001000000";
WHEN "111010" => memoryC2_uid146_exp2TabGen_q <= "1001101000";
WHEN "111011" => memoryC2_uid146_exp2TabGen_q <= "1010010000";
WHEN "111100" => memoryC2_uid146_exp2TabGen_q <= "1010111001";
WHEN "111101" => memoryC2_uid146_exp2TabGen_q <= "1011100010";
WHEN "111110" => memoryC2_uid146_exp2TabGen_q <= "1100001011";
WHEN "111111" => memoryC2_uid146_exp2TabGen_q <= "1100110101";
WHEN OTHERS =>
memoryC2_uid146_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor(LOGICAL,776)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena(REG,777)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd(LOGICAL,778)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem(DUALMEM,767)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 4,
numwords_a => 11,
width_b => 6,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC2_uid145_exp2TabGen(LOOKUP,144)@18
memoryC2_uid145_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid145_exp2TabGen_q <= "1110111101";
WHEN "000001" => memoryC2_uid145_exp2TabGen_q <= "0101110101";
WHEN "000010" => memoryC2_uid145_exp2TabGen_q <= "0000011100";
WHEN "000011" => memoryC2_uid145_exp2TabGen_q <= "1110110100";
WHEN "000100" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000101" => memoryC2_uid145_exp2TabGen_q <= "0111000100";
WHEN "000110" => memoryC2_uid145_exp2TabGen_q <= "0001000001";
WHEN "000111" => memoryC2_uid145_exp2TabGen_q <= "1110111010";
WHEN "001000" => memoryC2_uid145_exp2TabGen_q <= "0000110010";
WHEN "001001" => memoryC2_uid145_exp2TabGen_q <= "0110101011";
WHEN "001010" => memoryC2_uid145_exp2TabGen_q <= "0000101010";
WHEN "001011" => memoryC2_uid145_exp2TabGen_q <= "1110110000";
WHEN "001100" => memoryC2_uid145_exp2TabGen_q <= "0001000000";
WHEN "001101" => memoryC2_uid145_exp2TabGen_q <= "0111011101";
WHEN "001110" => memoryC2_uid145_exp2TabGen_q <= "0010001010";
WHEN "001111" => memoryC2_uid145_exp2TabGen_q <= "0001001011";
WHEN "010000" => memoryC2_uid145_exp2TabGen_q <= "0100100001";
WHEN "010001" => memoryC2_uid145_exp2TabGen_q <= "1100010001";
WHEN "010010" => memoryC2_uid145_exp2TabGen_q <= "1000011101";
WHEN "010011" => memoryC2_uid145_exp2TabGen_q <= "1001001000";
WHEN "010100" => memoryC2_uid145_exp2TabGen_q <= "1110010101";
WHEN "010101" => memoryC2_uid145_exp2TabGen_q <= "1000001000";
WHEN "010110" => memoryC2_uid145_exp2TabGen_q <= "0110100100";
WHEN "010111" => memoryC2_uid145_exp2TabGen_q <= "1001101100";
WHEN "011000" => memoryC2_uid145_exp2TabGen_q <= "0001100010";
WHEN "011001" => memoryC2_uid145_exp2TabGen_q <= "1110001100";
WHEN "011010" => memoryC2_uid145_exp2TabGen_q <= "1111101011";
WHEN "011011" => memoryC2_uid145_exp2TabGen_q <= "0110000100";
WHEN "011100" => memoryC2_uid145_exp2TabGen_q <= "0001011001";
WHEN "011101" => memoryC2_uid145_exp2TabGen_q <= "0001101111";
WHEN "011110" => memoryC2_uid145_exp2TabGen_q <= "0111001000";
WHEN "011111" => memoryC2_uid145_exp2TabGen_q <= "0001101000";
WHEN "100000" => memoryC2_uid145_exp2TabGen_q <= "0001010011";
WHEN "100001" => memoryC2_uid145_exp2TabGen_q <= "0110001100";
WHEN "100010" => memoryC2_uid145_exp2TabGen_q <= "0000010111";
WHEN "100011" => memoryC2_uid145_exp2TabGen_q <= "1111110111";
WHEN "100100" => memoryC2_uid145_exp2TabGen_q <= "0100110001";
WHEN "100101" => memoryC2_uid145_exp2TabGen_q <= "1111001000";
WHEN "100110" => memoryC2_uid145_exp2TabGen_q <= "1111000000";
WHEN "100111" => memoryC2_uid145_exp2TabGen_q <= "0100011101";
WHEN "101000" => memoryC2_uid145_exp2TabGen_q <= "1111100010";
WHEN "101001" => memoryC2_uid145_exp2TabGen_q <= "0000010100";
WHEN "101010" => memoryC2_uid145_exp2TabGen_q <= "0110110111";
WHEN "101011" => memoryC2_uid145_exp2TabGen_q <= "0011001101";
WHEN "101100" => memoryC2_uid145_exp2TabGen_q <= "0101011101";
WHEN "101101" => memoryC2_uid145_exp2TabGen_q <= "1101101001";
WHEN "101110" => memoryC2_uid145_exp2TabGen_q <= "1011110110";
WHEN "101111" => memoryC2_uid145_exp2TabGen_q <= "0000001000";
WHEN "110000" => memoryC2_uid145_exp2TabGen_q <= "1010100011";
WHEN "110001" => memoryC2_uid145_exp2TabGen_q <= "1011001100";
WHEN "110010" => memoryC2_uid145_exp2TabGen_q <= "0010000111";
WHEN "110011" => memoryC2_uid145_exp2TabGen_q <= "1111011000";
WHEN "110100" => memoryC2_uid145_exp2TabGen_q <= "0011000011";
WHEN "110101" => memoryC2_uid145_exp2TabGen_q <= "1101001110";
WHEN "110110" => memoryC2_uid145_exp2TabGen_q <= "1101111100";
WHEN "110111" => memoryC2_uid145_exp2TabGen_q <= "0101010011";
WHEN "111000" => memoryC2_uid145_exp2TabGen_q <= "0011010110";
WHEN "111001" => memoryC2_uid145_exp2TabGen_q <= "1000001011";
WHEN "111010" => memoryC2_uid145_exp2TabGen_q <= "0011110110";
WHEN "111011" => memoryC2_uid145_exp2TabGen_q <= "0110011101";
WHEN "111100" => memoryC2_uid145_exp2TabGen_q <= "0000000011";
WHEN "111101" => memoryC2_uid145_exp2TabGen_q <= "0000101101";
WHEN "111110" => memoryC2_uid145_exp2TabGen_q <= "1000100010";
WHEN "111111" => memoryC2_uid145_exp2TabGen_q <= "0111100101";
WHEN OTHERS =>
memoryC2_uid145_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid144_exp2TabGen(LOOKUP,143)@18
memoryC2_uid144_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid144_exp2TabGen_q <= "1111111110";
WHEN "000001" => memoryC2_uid144_exp2TabGen_q <= "1011011110";
WHEN "000010" => memoryC2_uid144_exp2TabGen_q <= "0110001100";
WHEN "000011" => memoryC2_uid144_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC2_uid144_exp2TabGen_q <= "0000010011";
WHEN "000101" => memoryC2_uid144_exp2TabGen_q <= "0100010011";
WHEN "000110" => memoryC2_uid144_exp2TabGen_q <= "0000110011";
WHEN "000111" => memoryC2_uid144_exp2TabGen_q <= "0001010001";
WHEN "001000" => memoryC2_uid144_exp2TabGen_q <= "0001101001";
WHEN "001001" => memoryC2_uid144_exp2TabGen_q <= "1110011000";
WHEN "001010" => memoryC2_uid144_exp2TabGen_q <= "0100010110";
WHEN "001011" => memoryC2_uid144_exp2TabGen_q <= "0000111111";
WHEN "001100" => memoryC2_uid144_exp2TabGen_q <= "0010001010";
WHEN "001101" => memoryC2_uid144_exp2TabGen_q <= "0110010010";
WHEN "001110" => memoryC2_uid144_exp2TabGen_q <= "1100010000";
WHEN "001111" => memoryC2_uid144_exp2TabGen_q <= "0011011111";
WHEN "010000" => memoryC2_uid144_exp2TabGen_q <= "1011111000";
WHEN "010001" => memoryC2_uid144_exp2TabGen_q <= "0101111010";
WHEN "010010" => memoryC2_uid144_exp2TabGen_q <= "0010100010";
WHEN "010011" => memoryC2_uid144_exp2TabGen_q <= "0011010010";
WHEN "010100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "010101" => memoryC2_uid144_exp2TabGen_q <= "1001110110";
WHEN "010110" => memoryC2_uid144_exp2TabGen_q <= "0101011010";
WHEN "010111" => memoryC2_uid144_exp2TabGen_q <= "0000100101";
WHEN "011000" => memoryC2_uid144_exp2TabGen_q <= "1111100110";
WHEN "011001" => memoryC2_uid144_exp2TabGen_q <= "0111010101";
WHEN "011010" => memoryC2_uid144_exp2TabGen_q <= "1101001010";
WHEN "011011" => memoryC2_uid144_exp2TabGen_q <= "0111000101";
WHEN "011100" => memoryC2_uid144_exp2TabGen_q <= "1011101100";
WHEN "011101" => memoryC2_uid144_exp2TabGen_q <= "0010001001";
WHEN "011110" => memoryC2_uid144_exp2TabGen_q <= "0010001101";
WHEN "011111" => memoryC2_uid144_exp2TabGen_q <= "0100010010";
WHEN "100000" => memoryC2_uid144_exp2TabGen_q <= "0001010110";
WHEN "100001" => memoryC2_uid144_exp2TabGen_q <= "0011000010";
WHEN "100010" => memoryC2_uid144_exp2TabGen_q <= "0011100100";
WHEN "100011" => memoryC2_uid144_exp2TabGen_q <= "1101110101";
WHEN "100100" => memoryC2_uid144_exp2TabGen_q <= "1101010110";
WHEN "100101" => memoryC2_uid144_exp2TabGen_q <= "1110010001";
WHEN "100110" => memoryC2_uid144_exp2TabGen_q <= "1101011100";
WHEN "100111" => memoryC2_uid144_exp2TabGen_q <= "1000010100";
WHEN "101000" => memoryC2_uid144_exp2TabGen_q <= "1101000100";
WHEN "101001" => memoryC2_uid144_exp2TabGen_q <= "1010100001";
WHEN "101010" => memoryC2_uid144_exp2TabGen_q <= "0000001100";
WHEN "101011" => memoryC2_uid144_exp2TabGen_q <= "1110010010";
WHEN "101100" => memoryC2_uid144_exp2TabGen_q <= "0101101101";
WHEN "101101" => memoryC2_uid144_exp2TabGen_q <= "1000000100";
WHEN "101110" => memoryC2_uid144_exp2TabGen_q <= "0111101100";
WHEN "101111" => memoryC2_uid144_exp2TabGen_q <= "0111100111";
WHEN "110000" => memoryC2_uid144_exp2TabGen_q <= "1011101001";
WHEN "110001" => memoryC2_uid144_exp2TabGen_q <= "1000010001";
WHEN "110010" => memoryC2_uid144_exp2TabGen_q <= "0010110001";
WHEN "110011" => memoryC2_uid144_exp2TabGen_q <= "0001001001";
WHEN "110100" => memoryC2_uid144_exp2TabGen_q <= "1010001100";
WHEN "110101" => memoryC2_uid144_exp2TabGen_q <= "0101011101";
WHEN "110110" => memoryC2_uid144_exp2TabGen_q <= "1011010001";
WHEN "110111" => memoryC2_uid144_exp2TabGen_q <= "0100101111";
WHEN "111000" => memoryC2_uid144_exp2TabGen_q <= "1011110001";
WHEN "111001" => memoryC2_uid144_exp2TabGen_q <= "1011000110";
WHEN "111010" => memoryC2_uid144_exp2TabGen_q <= "1110010000";
WHEN "111011" => memoryC2_uid144_exp2TabGen_q <= "0001100101";
WHEN "111100" => memoryC2_uid144_exp2TabGen_q <= "0010010001";
WHEN "111101" => memoryC2_uid144_exp2TabGen_q <= "1110010101";
WHEN "111110" => memoryC2_uid144_exp2TabGen_q <= "0100101011";
WHEN "111111" => memoryC2_uid144_exp2TabGen_q <= "0101000000";
WHEN OTHERS =>
memoryC2_uid144_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC2_uid143_exp2TabGen(LOOKUP,142)@18
memoryC2_uid143_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC2_uid143_exp2TabGen_0_q_to_memoryC2_uid143_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC2_uid143_exp2TabGen_q <= "0000001110";
WHEN "000001" => memoryC2_uid143_exp2TabGen_q <= "0011010011";
WHEN "000010" => memoryC2_uid143_exp2TabGen_q <= "1100111100";
WHEN "000011" => memoryC2_uid143_exp2TabGen_q <= "0000000010";
WHEN "000100" => memoryC2_uid143_exp2TabGen_q <= "0111011111";
WHEN "000101" => memoryC2_uid143_exp2TabGen_q <= "1110101000";
WHEN "000110" => memoryC2_uid143_exp2TabGen_q <= "1100111001";
WHEN "000111" => memoryC2_uid143_exp2TabGen_q <= "1010001001";
WHEN "001000" => memoryC2_uid143_exp2TabGen_q <= "1111101011";
WHEN "001001" => memoryC2_uid143_exp2TabGen_q <= "0101001111";
WHEN "001010" => memoryC2_uid143_exp2TabGen_q <= "1110110101";
WHEN "001011" => memoryC2_uid143_exp2TabGen_q <= "0110100000";
WHEN "001100" => memoryC2_uid143_exp2TabGen_q <= "1111101001";
WHEN "001101" => memoryC2_uid143_exp2TabGen_q <= "1111010100";
WHEN "001110" => memoryC2_uid143_exp2TabGen_q <= "1101110001";
WHEN "001111" => memoryC2_uid143_exp2TabGen_q <= "0000010001";
WHEN "010000" => memoryC2_uid143_exp2TabGen_q <= "1001010010";
WHEN "010001" => memoryC2_uid143_exp2TabGen_q <= "0110011011";
WHEN "010010" => memoryC2_uid143_exp2TabGen_q <= "1101101010";
WHEN "010011" => memoryC2_uid143_exp2TabGen_q <= "1000110000";
WHEN "010100" => memoryC2_uid143_exp2TabGen_q <= "1010100100";
WHEN "010101" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "010110" => memoryC2_uid143_exp2TabGen_q <= "1101110100";
WHEN "010111" => memoryC2_uid143_exp2TabGen_q <= "0011110101";
WHEN "011000" => memoryC2_uid143_exp2TabGen_q <= "1110001101";
WHEN "011001" => memoryC2_uid143_exp2TabGen_q <= "0011000111";
WHEN "011010" => memoryC2_uid143_exp2TabGen_q <= "0110111111";
WHEN "011011" => memoryC2_uid143_exp2TabGen_q <= "1100111000";
WHEN "011100" => memoryC2_uid143_exp2TabGen_q <= "0110111001";
WHEN "011101" => memoryC2_uid143_exp2TabGen_q <= "0011010110";
WHEN "011110" => memoryC2_uid143_exp2TabGen_q <= "1110001111";
WHEN "011111" => memoryC2_uid143_exp2TabGen_q <= "0111010010";
WHEN "100000" => memoryC2_uid143_exp2TabGen_q <= "1110000011";
WHEN "100001" => memoryC2_uid143_exp2TabGen_q <= "1000000000";
WHEN "100010" => memoryC2_uid143_exp2TabGen_q <= "1010001111";
WHEN "100011" => memoryC2_uid143_exp2TabGen_q <= "1000111011";
WHEN "100100" => memoryC2_uid143_exp2TabGen_q <= "0110010001";
WHEN "100101" => memoryC2_uid143_exp2TabGen_q <= "1010010101";
WHEN "100110" => memoryC2_uid143_exp2TabGen_q <= "0001011100";
WHEN "100111" => memoryC2_uid143_exp2TabGen_q <= "1000111000";
WHEN "101000" => memoryC2_uid143_exp2TabGen_q <= "1101001101";
WHEN "101001" => memoryC2_uid143_exp2TabGen_q <= "1111001101";
WHEN "101010" => memoryC2_uid143_exp2TabGen_q <= "1111110110";
WHEN "101011" => memoryC2_uid143_exp2TabGen_q <= "1101110101";
WHEN "101100" => memoryC2_uid143_exp2TabGen_q <= "1011101101";
WHEN "101101" => memoryC2_uid143_exp2TabGen_q <= "1001100101";
WHEN "101110" => memoryC2_uid143_exp2TabGen_q <= "0011001100";
WHEN "101111" => memoryC2_uid143_exp2TabGen_q <= "1101110000";
WHEN "110000" => memoryC2_uid143_exp2TabGen_q <= "0100110111";
WHEN "110001" => memoryC2_uid143_exp2TabGen_q <= "1000111010";
WHEN "110010" => memoryC2_uid143_exp2TabGen_q <= "0101000000";
WHEN "110011" => memoryC2_uid143_exp2TabGen_q <= "1101011111";
WHEN "110100" => memoryC2_uid143_exp2TabGen_q <= "1110100011";
WHEN "110101" => memoryC2_uid143_exp2TabGen_q <= "1010100010";
WHEN "110110" => memoryC2_uid143_exp2TabGen_q <= "0100101101";
WHEN "110111" => memoryC2_uid143_exp2TabGen_q <= "0000101100";
WHEN "111000" => memoryC2_uid143_exp2TabGen_q <= "1000101100";
WHEN "111001" => memoryC2_uid143_exp2TabGen_q <= "1001001011";
WHEN "111010" => memoryC2_uid143_exp2TabGen_q <= "0101011010";
WHEN "111011" => memoryC2_uid143_exp2TabGen_q <= "0011000110";
WHEN "111100" => memoryC2_uid143_exp2TabGen_q <= "0010111100";
WHEN "111101" => memoryC2_uid143_exp2TabGen_q <= "1111000100";
WHEN "111110" => memoryC2_uid143_exp2TabGen_q <= "0101010010";
WHEN "111111" => memoryC2_uid143_exp2TabGen_q <= "1000000001";
WHEN OTHERS =>
memoryC2_uid143_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid148_exp2TabGen(BITJOIN,147)@18
os_uid148_exp2TabGen_q <= ld_memoryC2_uid147_exp2TabGen_q_to_os_uid148_exp2TabGen_e_replace_mem_q & memoryC2_uid146_exp2TabGen_q & memoryC2_uid145_exp2TabGen_q & memoryC2_uid144_exp2TabGen_q & memoryC2_uid143_exp2TabGen_q;
--cIncludingRoundingBit_uid176_exp2PolyEval(BITJOIN,175)@18
cIncludingRoundingBit_uid176_exp2PolyEval_q <= os_uid148_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0(REG,317)@18
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q <= cIncludingRoundingBit_uid176_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid177_exp2PolyEval(ADD,176)@19
ts3_uid177_exp2PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid176_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_0_q);
ts3_uid177_exp2PolyEval_b <= STD_LOGIC_VECTOR((45 downto 38 => reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q(37)) & reg_R_uid222_pT3_uid174_exp2PolyEval_0_to_ts3_uid177_exp2PolyEval_1_q);
ts3_uid177_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid177_exp2PolyEval_a) + SIGNED(ts3_uid177_exp2PolyEval_b));
ts3_uid177_exp2PolyEval_q <= ts3_uid177_exp2PolyEval_o(45 downto 0);
--s3_uid178_exp2PolyEval(BITSELECT,177)@19
s3_uid178_exp2PolyEval_in <= ts3_uid177_exp2PolyEval_q;
s3_uid178_exp2PolyEval_b <= s3_uid178_exp2PolyEval_in(45 downto 1);
--yTop27Bits_uid224_pT4_uid180_exp2PolyEval(BITSELECT,223)@19
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b;
yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9(REG,322)@19
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q <= yTop27Bits_uid224_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor(LOGICAL,839)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q <= not (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_a or ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_b);
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top(CONSTANT,835)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q <= "01011";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp(LOGICAL,836)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_mem_top_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_a = ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg(REG,837)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena(REG,840)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd(LOGICAL,841)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_a and ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt(COUNTER,831)
-- every=1, low=0, high=11, step=1, init=1
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i = 10 THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i - 11;
ELSE
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg(REG,832)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux(MUX,833)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem(DUALMEM,830)
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT2_uid167_exp2PolyEval_a_inputreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 4,
numwords_a => 12,
width_b => 46,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_iq(45 downto 0);
--yT4_uid179_exp2PolyEval(BITSELECT,178)@19
yT4_uid179_exp2PolyEval_in <= ld_yPPolyEval_uid48_fpExp2Test_b_to_yT4_uid179_exp2PolyEval_a_replace_mem_q;
yT4_uid179_exp2PolyEval_b <= yT4_uid179_exp2PolyEval_in(45 downto 3);
--xBottomBits_uid227_pT4_uid180_exp2PolyEval(BITSELECT,226)@19
xBottomBits_uid227_pT4_uid180_exp2PolyEval_in <= yT4_uid179_exp2PolyEval_b(15 downto 0);
xBottomBits_uid227_pT4_uid180_exp2PolyEval_b <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_in(15 downto 0);
--pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval(BITJOIN,228)@19
pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q <= xBottomBits_uid227_pT4_uid180_exp2PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7(REG,321)@19
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid226_pT4_uid180_exp2PolyEval(BITSELECT,225)@19
yBottomBits_uid226_pT4_uid180_exp2PolyEval_in <= s3_uid178_exp2PolyEval_b(17 downto 0);
yBottomBits_uid226_pT4_uid180_exp2PolyEval_b <= yBottomBits_uid226_pT4_uid180_exp2PolyEval_in(17 downto 0);
--ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a(DELAY,591)@19
ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid226_pT4_uid180_exp2PolyEval_b, xout => ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval(BITJOIN,227)@20
spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q <= GND_q & ld_yBottomBits_uid226_pT4_uid180_exp2PolyEval_b_to_spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_a_q;
--pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval(BITJOIN,229)@20
pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q <= spad_yBottomBits_uid226_uid228_pT4_uid180_exp2PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6(REG,320)@20
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q <= pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a(DELAY,585)@19
ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid179_exp2PolyEval_b, xout => ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid223_pT4_uid180_exp2PolyEval(BITSELECT,222)@20
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in <= ld_yT4_uid179_exp2PolyEval_b_to_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_a_q;
xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4(REG,319)@20
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q <= xTop27Bits_uid223_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma(CHAINMULTADD,260)@21
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid227_uid229_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid226_uid230_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval(BITSELECT,231)@24
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_q;
multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_in(54 downto 8);
--highBBits_uid234_pT4_uid180_exp2PolyEval(BITSELECT,233)@24
highBBits_uid234_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b;
highBBits_uid234_pT4_uid180_exp2PolyEval_b <= highBBits_uid234_pT4_uid180_exp2PolyEval_in(46 downto 18);
--ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b(DELAY,588)@20
ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid225_pT4_uid180_exp2PolyEval(MULT,224)@21
topProd_uid225_pT4_uid180_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_a),28)) * SIGNED(topProd_uid225_pT4_uid180_exp2PolyEval_b);
topProd_uid225_pT4_uid180_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_b <= (others => '0');
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_a <= reg_xTop27Bits_uid223_pT4_uid180_exp2PolyEval_0_to_multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_cma_4_q;
topProd_uid225_pT4_uid180_exp2PolyEval_b <= ld_reg_yTop27Bits_uid224_pT4_uid180_exp2PolyEval_0_to_topProd_uid225_pT4_uid180_exp2PolyEval_1_q_to_topProd_uid225_pT4_uid180_exp2PolyEval_b_q;
topProd_uid225_pT4_uid180_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid225_pT4_uid180_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid225_pT4_uid180_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid225_pT4_uid180_exp2PolyEval_q <= topProd_uid225_pT4_uid180_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid235_pT4_uid180_exp2PolyEval(ADD,234)@24
sumAHighB_uid235_pT4_uid180_exp2PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid225_pT4_uid180_exp2PolyEval_q(53)) & topProd_uid225_pT4_uid180_exp2PolyEval_q);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid234_pT4_uid180_exp2PolyEval_b(28)) & highBBits_uid234_pT4_uid180_exp2PolyEval_b);
sumAHighB_uid235_pT4_uid180_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_a) + SIGNED(sumAHighB_uid235_pT4_uid180_exp2PolyEval_b));
sumAHighB_uid235_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_o(54 downto 0);
--lowRangeB_uid233_pT4_uid180_exp2PolyEval(BITSELECT,232)@24
lowRangeB_uid233_pT4_uid180_exp2PolyEval_in <= multSumOfTwo27_uid228_pT4_uid180_exp2PolyEval_b(17 downto 0);
lowRangeB_uid233_pT4_uid180_exp2PolyEval_b <= lowRangeB_uid233_pT4_uid180_exp2PolyEval_in(17 downto 0);
--add0_uid233_uid236_pT4_uid180_exp2PolyEval(BITJOIN,235)@24
add0_uid233_uid236_pT4_uid180_exp2PolyEval_q <= sumAHighB_uid235_pT4_uid180_exp2PolyEval_q & lowRangeB_uid233_pT4_uid180_exp2PolyEval_b;
--R_uid237_pT4_uid180_exp2PolyEval(BITSELECT,236)@24
R_uid237_pT4_uid180_exp2PolyEval_in <= add0_uid233_uid236_pT4_uid180_exp2PolyEval_q(71 downto 0);
R_uid237_pT4_uid180_exp2PolyEval_b <= R_uid237_pT4_uid180_exp2PolyEval_in(71 downto 26);
--reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1(REG,326)@24
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q <= R_uid237_pT4_uid180_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor(LOGICAL,891)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top(CONSTANT,759)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q <= "010000";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp(LOGICAL,760)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg(REG,761)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena(REG,892)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd(LOGICAL,893)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt(COUNTER,755)
-- every=1, low=0, high=16, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i = 15 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i - 16;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg(REG,756)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux(MUX,757)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem(DUALMEM,882)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0(REG,284)@23
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid140_exp2TabGen(LOOKUP,139)@24
memoryC1_uid140_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid140_exp2TabGen_q <= "0101100010";
WHEN "000001" => memoryC1_uid140_exp2TabGen_q <= "0101100110";
WHEN "000010" => memoryC1_uid140_exp2TabGen_q <= "0101101010";
WHEN "000011" => memoryC1_uid140_exp2TabGen_q <= "0101101110";
WHEN "000100" => memoryC1_uid140_exp2TabGen_q <= "0101110010";
WHEN "000101" => memoryC1_uid140_exp2TabGen_q <= "0101110110";
WHEN "000110" => memoryC1_uid140_exp2TabGen_q <= "0101111010";
WHEN "000111" => memoryC1_uid140_exp2TabGen_q <= "0101111110";
WHEN "001000" => memoryC1_uid140_exp2TabGen_q <= "0110000011";
WHEN "001001" => memoryC1_uid140_exp2TabGen_q <= "0110000111";
WHEN "001010" => memoryC1_uid140_exp2TabGen_q <= "0110001011";
WHEN "001011" => memoryC1_uid140_exp2TabGen_q <= "0110001111";
WHEN "001100" => memoryC1_uid140_exp2TabGen_q <= "0110010100";
WHEN "001101" => memoryC1_uid140_exp2TabGen_q <= "0110011000";
WHEN "001110" => memoryC1_uid140_exp2TabGen_q <= "0110011100";
WHEN "001111" => memoryC1_uid140_exp2TabGen_q <= "0110100001";
WHEN "010000" => memoryC1_uid140_exp2TabGen_q <= "0110100110";
WHEN "010001" => memoryC1_uid140_exp2TabGen_q <= "0110101010";
WHEN "010010" => memoryC1_uid140_exp2TabGen_q <= "0110101111";
WHEN "010011" => memoryC1_uid140_exp2TabGen_q <= "0110110011";
WHEN "010100" => memoryC1_uid140_exp2TabGen_q <= "0110111000";
WHEN "010101" => memoryC1_uid140_exp2TabGen_q <= "0110111101";
WHEN "010110" => memoryC1_uid140_exp2TabGen_q <= "0111000010";
WHEN "010111" => memoryC1_uid140_exp2TabGen_q <= "0111000111";
WHEN "011000" => memoryC1_uid140_exp2TabGen_q <= "0111001100";
WHEN "011001" => memoryC1_uid140_exp2TabGen_q <= "0111010001";
WHEN "011010" => memoryC1_uid140_exp2TabGen_q <= "0111010110";
WHEN "011011" => memoryC1_uid140_exp2TabGen_q <= "0111011011";
WHEN "011100" => memoryC1_uid140_exp2TabGen_q <= "0111100000";
WHEN "011101" => memoryC1_uid140_exp2TabGen_q <= "0111100101";
WHEN "011110" => memoryC1_uid140_exp2TabGen_q <= "0111101011";
WHEN "011111" => memoryC1_uid140_exp2TabGen_q <= "0111110000";
WHEN "100000" => memoryC1_uid140_exp2TabGen_q <= "0111110101";
WHEN "100001" => memoryC1_uid140_exp2TabGen_q <= "0111111011";
WHEN "100010" => memoryC1_uid140_exp2TabGen_q <= "1000000000";
WHEN "100011" => memoryC1_uid140_exp2TabGen_q <= "1000000110";
WHEN "100100" => memoryC1_uid140_exp2TabGen_q <= "1000001100";
WHEN "100101" => memoryC1_uid140_exp2TabGen_q <= "1000010001";
WHEN "100110" => memoryC1_uid140_exp2TabGen_q <= "1000010111";
WHEN "100111" => memoryC1_uid140_exp2TabGen_q <= "1000011101";
WHEN "101000" => memoryC1_uid140_exp2TabGen_q <= "1000100011";
WHEN "101001" => memoryC1_uid140_exp2TabGen_q <= "1000101001";
WHEN "101010" => memoryC1_uid140_exp2TabGen_q <= "1000101111";
WHEN "101011" => memoryC1_uid140_exp2TabGen_q <= "1000110101";
WHEN "101100" => memoryC1_uid140_exp2TabGen_q <= "1000111011";
WHEN "101101" => memoryC1_uid140_exp2TabGen_q <= "1001000001";
WHEN "101110" => memoryC1_uid140_exp2TabGen_q <= "1001001000";
WHEN "101111" => memoryC1_uid140_exp2TabGen_q <= "1001001110";
WHEN "110000" => memoryC1_uid140_exp2TabGen_q <= "1001010100";
WHEN "110001" => memoryC1_uid140_exp2TabGen_q <= "1001011011";
WHEN "110010" => memoryC1_uid140_exp2TabGen_q <= "1001100001";
WHEN "110011" => memoryC1_uid140_exp2TabGen_q <= "1001101000";
WHEN "110100" => memoryC1_uid140_exp2TabGen_q <= "1001101111";
WHEN "110101" => memoryC1_uid140_exp2TabGen_q <= "1001110110";
WHEN "110110" => memoryC1_uid140_exp2TabGen_q <= "1001111100";
WHEN "110111" => memoryC1_uid140_exp2TabGen_q <= "1010000011";
WHEN "111000" => memoryC1_uid140_exp2TabGen_q <= "1010001010";
WHEN "111001" => memoryC1_uid140_exp2TabGen_q <= "1010010001";
WHEN "111010" => memoryC1_uid140_exp2TabGen_q <= "1010011001";
WHEN "111011" => memoryC1_uid140_exp2TabGen_q <= "1010100000";
WHEN "111100" => memoryC1_uid140_exp2TabGen_q <= "1010100111";
WHEN "111101" => memoryC1_uid140_exp2TabGen_q <= "1010101111";
WHEN "111110" => memoryC1_uid140_exp2TabGen_q <= "1010110110";
WHEN "111111" => memoryC1_uid140_exp2TabGen_q <= "1010111110";
WHEN OTHERS =>
memoryC1_uid140_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor(LOGICAL,763)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena(REG,764)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd(LOGICAL,765)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem(DUALMEM,754)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 17,
width_b => 6,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC1_uid139_exp2TabGen(LOOKUP,138)@24
memoryC1_uid139_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid139_exp2TabGen_q <= "1110010000";
WHEN "000001" => memoryC1_uid139_exp2TabGen_q <= "1100000110";
WHEN "000010" => memoryC1_uid139_exp2TabGen_q <= "1010100110";
WHEN "000011" => memoryC1_uid139_exp2TabGen_q <= "1001110010";
WHEN "000100" => memoryC1_uid139_exp2TabGen_q <= "1001101010";
WHEN "000101" => memoryC1_uid139_exp2TabGen_q <= "1010001110";
WHEN "000110" => memoryC1_uid139_exp2TabGen_q <= "1011100000";
WHEN "000111" => memoryC1_uid139_exp2TabGen_q <= "1101011111";
WHEN "001000" => memoryC1_uid139_exp2TabGen_q <= "0000001100";
WHEN "001001" => memoryC1_uid139_exp2TabGen_q <= "0011100111";
WHEN "001010" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "001011" => memoryC1_uid139_exp2TabGen_q <= "1100101011";
WHEN "001100" => memoryC1_uid139_exp2TabGen_q <= "0010010101";
WHEN "001101" => memoryC1_uid139_exp2TabGen_q <= "1000110000";
WHEN "001110" => memoryC1_uid139_exp2TabGen_q <= "1111111011";
WHEN "001111" => memoryC1_uid139_exp2TabGen_q <= "0111111000";
WHEN "010000" => memoryC1_uid139_exp2TabGen_q <= "0000101000";
WHEN "010001" => memoryC1_uid139_exp2TabGen_q <= "1010001010";
WHEN "010010" => memoryC1_uid139_exp2TabGen_q <= "0100011111";
WHEN "010011" => memoryC1_uid139_exp2TabGen_q <= "1111101000";
WHEN "010100" => memoryC1_uid139_exp2TabGen_q <= "1011100101";
WHEN "010101" => memoryC1_uid139_exp2TabGen_q <= "1000011000";
WHEN "010110" => memoryC1_uid139_exp2TabGen_q <= "0110000000";
WHEN "010111" => memoryC1_uid139_exp2TabGen_q <= "0100011110";
WHEN "011000" => memoryC1_uid139_exp2TabGen_q <= "0011110010";
WHEN "011001" => memoryC1_uid139_exp2TabGen_q <= "0011111110";
WHEN "011010" => memoryC1_uid139_exp2TabGen_q <= "0101000010";
WHEN "011011" => memoryC1_uid139_exp2TabGen_q <= "0110111110";
WHEN "011100" => memoryC1_uid139_exp2TabGen_q <= "1001110100";
WHEN "011101" => memoryC1_uid139_exp2TabGen_q <= "1101100011";
WHEN "011110" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN "011111" => memoryC1_uid139_exp2TabGen_q <= "0111110001";
WHEN "100000" => memoryC1_uid139_exp2TabGen_q <= "1110010001";
WHEN "100001" => memoryC1_uid139_exp2TabGen_q <= "0101101101";
WHEN "100010" => memoryC1_uid139_exp2TabGen_q <= "1110000111";
WHEN "100011" => memoryC1_uid139_exp2TabGen_q <= "0111011110";
WHEN "100100" => memoryC1_uid139_exp2TabGen_q <= "0001110011";
WHEN "100101" => memoryC1_uid139_exp2TabGen_q <= "1101000111";
WHEN "100110" => memoryC1_uid139_exp2TabGen_q <= "1001011011";
WHEN "100111" => memoryC1_uid139_exp2TabGen_q <= "0110101111";
WHEN "101000" => memoryC1_uid139_exp2TabGen_q <= "0101000100";
WHEN "101001" => memoryC1_uid139_exp2TabGen_q <= "0100011011";
WHEN "101010" => memoryC1_uid139_exp2TabGen_q <= "0100110101";
WHEN "101011" => memoryC1_uid139_exp2TabGen_q <= "0110010001";
WHEN "101100" => memoryC1_uid139_exp2TabGen_q <= "1000110010";
WHEN "101101" => memoryC1_uid139_exp2TabGen_q <= "1100010111";
WHEN "101110" => memoryC1_uid139_exp2TabGen_q <= "0001000001";
WHEN "101111" => memoryC1_uid139_exp2TabGen_q <= "0110110010";
WHEN "110000" => memoryC1_uid139_exp2TabGen_q <= "1101101010";
WHEN "110001" => memoryC1_uid139_exp2TabGen_q <= "0101101001";
WHEN "110010" => memoryC1_uid139_exp2TabGen_q <= "1110110001";
WHEN "110011" => memoryC1_uid139_exp2TabGen_q <= "1001000010";
WHEN "110100" => memoryC1_uid139_exp2TabGen_q <= "0100011101";
WHEN "110101" => memoryC1_uid139_exp2TabGen_q <= "0001000011";
WHEN "110110" => memoryC1_uid139_exp2TabGen_q <= "1110110100";
WHEN "110111" => memoryC1_uid139_exp2TabGen_q <= "1101110011";
WHEN "111000" => memoryC1_uid139_exp2TabGen_q <= "1101111110";
WHEN "111001" => memoryC1_uid139_exp2TabGen_q <= "1111011000";
WHEN "111010" => memoryC1_uid139_exp2TabGen_q <= "0010000000";
WHEN "111011" => memoryC1_uid139_exp2TabGen_q <= "0101111001";
WHEN "111100" => memoryC1_uid139_exp2TabGen_q <= "1011000010";
WHEN "111101" => memoryC1_uid139_exp2TabGen_q <= "0001011101";
WHEN "111110" => memoryC1_uid139_exp2TabGen_q <= "1001001011";
WHEN "111111" => memoryC1_uid139_exp2TabGen_q <= "0010001100";
WHEN OTHERS =>
memoryC1_uid139_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid138_exp2TabGen(LOOKUP,137)@24
memoryC1_uid138_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid138_exp2TabGen_q <= "1011111110";
WHEN "000001" => memoryC1_uid138_exp2TabGen_q <= "0000001011";
WHEN "000010" => memoryC1_uid138_exp2TabGen_q <= "0101110101";
WHEN "000011" => memoryC1_uid138_exp2TabGen_q <= "0100011101";
WHEN "000100" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "000101" => memoryC1_uid138_exp2TabGen_q <= "1011000110";
WHEN "000110" => memoryC1_uid138_exp2TabGen_q <= "0010100001";
WHEN "000111" => memoryC1_uid138_exp2TabGen_q <= "0001110010";
WHEN "001000" => memoryC1_uid138_exp2TabGen_q <= "0000110100";
WHEN "001001" => memoryC1_uid138_exp2TabGen_q <= "0111100110";
WHEN "001010" => memoryC1_uid138_exp2TabGen_q <= "1110010001";
WHEN "001011" => memoryC1_uid138_exp2TabGen_q <= "1100111111";
WHEN "001100" => memoryC1_uid138_exp2TabGen_q <= "1100000011";
WHEN "001101" => memoryC1_uid138_exp2TabGen_q <= "0011110011";
WHEN "001110" => memoryC1_uid138_exp2TabGen_q <= "1100101110";
WHEN "001111" => memoryC1_uid138_exp2TabGen_q <= "1111010110";
WHEN "010000" => memoryC1_uid138_exp2TabGen_q <= "0100010100";
WHEN "010001" => memoryC1_uid138_exp2TabGen_q <= "0100011000";
WHEN "010010" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "010011" => memoryC1_uid138_exp2TabGen_q <= "1001001100";
WHEN "010100" => memoryC1_uid138_exp2TabGen_q <= "1111111001";
WHEN "010101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "010110" => memoryC1_uid138_exp2TabGen_q <= "0011100010";
WHEN "010111" => memoryC1_uid138_exp2TabGen_q <= "0011000000";
WHEN "011000" => memoryC1_uid138_exp2TabGen_q <= "1101011100";
WHEN "011001" => memoryC1_uid138_exp2TabGen_q <= "1100011000";
WHEN "011010" => memoryC1_uid138_exp2TabGen_q <= "1001011100";
WHEN "011011" => memoryC1_uid138_exp2TabGen_q <= "1110011000";
WHEN "011100" => memoryC1_uid138_exp2TabGen_q <= "0101000001";
WHEN "011101" => memoryC1_uid138_exp2TabGen_q <= "0111010100";
WHEN "011110" => memoryC1_uid138_exp2TabGen_q <= "1111010101";
WHEN "011111" => memoryC1_uid138_exp2TabGen_q <= "0111001111";
WHEN "100000" => memoryC1_uid138_exp2TabGen_q <= "1001010011";
WHEN "100001" => memoryC1_uid138_exp2TabGen_q <= "1111111010";
WHEN "100010" => memoryC1_uid138_exp2TabGen_q <= "0101100101";
WHEN "100011" => memoryC1_uid138_exp2TabGen_q <= "0100111011";
WHEN "100100" => memoryC1_uid138_exp2TabGen_q <= "1000101011";
WHEN "100101" => memoryC1_uid138_exp2TabGen_q <= "1011101011";
WHEN "100110" => memoryC1_uid138_exp2TabGen_q <= "1000111010";
WHEN "100111" => memoryC1_uid138_exp2TabGen_q <= "1011011100";
WHEN "101000" => memoryC1_uid138_exp2TabGen_q <= "1110100000";
WHEN "101001" => memoryC1_uid138_exp2TabGen_q <= "1101011010";
WHEN "101010" => memoryC1_uid138_exp2TabGen_q <= "0011101000";
WHEN "101011" => memoryC1_uid138_exp2TabGen_q <= "1100101111";
WHEN "101100" => memoryC1_uid138_exp2TabGen_q <= "0100011011";
WHEN "101101" => memoryC1_uid138_exp2TabGen_q <= "0110100010";
WHEN "101110" => memoryC1_uid138_exp2TabGen_q <= "1111000010";
WHEN "101111" => memoryC1_uid138_exp2TabGen_q <= "1001111111";
WHEN "110000" => memoryC1_uid138_exp2TabGen_q <= "0011101010";
WHEN "110001" => memoryC1_uid138_exp2TabGen_q <= "1000010111";
WHEN "110010" => memoryC1_uid138_exp2TabGen_q <= "0100101000";
WHEN "110011" => memoryC1_uid138_exp2TabGen_q <= "0101000011";
WHEN "110100" => memoryC1_uid138_exp2TabGen_q <= "0110011010";
WHEN "110101" => memoryC1_uid138_exp2TabGen_q <= "0101100110";
WHEN "110110" => memoryC1_uid138_exp2TabGen_q <= "1111101011";
WHEN "110111" => memoryC1_uid138_exp2TabGen_q <= "0001110100";
WHEN "111000" => memoryC1_uid138_exp2TabGen_q <= "1001010110";
WHEN "111001" => memoryC1_uid138_exp2TabGen_q <= "0011110000";
WHEN "111010" => memoryC1_uid138_exp2TabGen_q <= "1110101001";
WHEN "111011" => memoryC1_uid138_exp2TabGen_q <= "0111110011";
WHEN "111100" => memoryC1_uid138_exp2TabGen_q <= "1101001000";
WHEN "111101" => memoryC1_uid138_exp2TabGen_q <= "1100101101";
WHEN "111110" => memoryC1_uid138_exp2TabGen_q <= "0100110000";
WHEN "111111" => memoryC1_uid138_exp2TabGen_q <= "0011101011";
WHEN OTHERS =>
memoryC1_uid138_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid137_exp2TabGen(LOOKUP,136)@24
memoryC1_uid137_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid137_exp2TabGen_0_q_to_memoryC1_uid137_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC1_uid137_exp2TabGen_q <= "1111101000";
WHEN "000001" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "000010" => memoryC1_uid137_exp2TabGen_q <= "0010010101";
WHEN "000011" => memoryC1_uid137_exp2TabGen_q <= "1010101011";
WHEN "000100" => memoryC1_uid137_exp2TabGen_q <= "0110000101";
WHEN "000101" => memoryC1_uid137_exp2TabGen_q <= "0100111000";
WHEN "000110" => memoryC1_uid137_exp2TabGen_q <= "1100111110";
WHEN "000111" => memoryC1_uid137_exp2TabGen_q <= "1010110000";
WHEN "001000" => memoryC1_uid137_exp2TabGen_q <= "0010000000";
WHEN "001001" => memoryC1_uid137_exp2TabGen_q <= "1110111011";
WHEN "001010" => memoryC1_uid137_exp2TabGen_q <= "0111000001";
WHEN "001011" => memoryC1_uid137_exp2TabGen_q <= "1010001000";
WHEN "001100" => memoryC1_uid137_exp2TabGen_q <= "0011010110";
WHEN "001101" => memoryC1_uid137_exp2TabGen_q <= "1010000110";
WHEN "001110" => memoryC1_uid137_exp2TabGen_q <= "0011000101";
WHEN "001111" => memoryC1_uid137_exp2TabGen_q <= "0001010100";
WHEN "010000" => memoryC1_uid137_exp2TabGen_q <= "0111001000";
WHEN "010001" => memoryC1_uid137_exp2TabGen_q <= "0111010000";
WHEN "010010" => memoryC1_uid137_exp2TabGen_q <= "0101110110";
WHEN "010011" => memoryC1_uid137_exp2TabGen_q <= "1001100000";
WHEN "010100" => memoryC1_uid137_exp2TabGen_q <= "1100011100";
WHEN "010101" => memoryC1_uid137_exp2TabGen_q <= "1101011101";
WHEN "010110" => memoryC1_uid137_exp2TabGen_q <= "0001001000";
WHEN "010111" => memoryC1_uid137_exp2TabGen_q <= "0010110111";
WHEN "011000" => memoryC1_uid137_exp2TabGen_q <= "0110000001";
WHEN "011001" => memoryC1_uid137_exp2TabGen_q <= "0111000101";
WHEN "011010" => memoryC1_uid137_exp2TabGen_q <= "1100101111";
WHEN "011011" => memoryC1_uid137_exp2TabGen_q <= "1001000111";
WHEN "011100" => memoryC1_uid137_exp2TabGen_q <= "1010111000";
WHEN "011101" => memoryC1_uid137_exp2TabGen_q <= "1110011100";
WHEN "011110" => memoryC1_uid137_exp2TabGen_q <= "1111001100";
WHEN "011111" => memoryC1_uid137_exp2TabGen_q <= "1000101000";
WHEN "100000" => memoryC1_uid137_exp2TabGen_q <= "0111101010";
WHEN "100001" => memoryC1_uid137_exp2TabGen_q <= "1011110011";
WHEN "100010" => memoryC1_uid137_exp2TabGen_q <= "1000011000";
WHEN "100011" => memoryC1_uid137_exp2TabGen_q <= "0101111001";
WHEN "100100" => memoryC1_uid137_exp2TabGen_q <= "0011001101";
WHEN "100101" => memoryC1_uid137_exp2TabGen_q <= "0110111001";
WHEN "100110" => memoryC1_uid137_exp2TabGen_q <= "0000011101";
WHEN "100111" => memoryC1_uid137_exp2TabGen_q <= "1001110010";
WHEN "101000" => memoryC1_uid137_exp2TabGen_q <= "1000010100";
WHEN "101001" => memoryC1_uid137_exp2TabGen_q <= "1110100010";
WHEN "101010" => memoryC1_uid137_exp2TabGen_q <= "1101001111";
WHEN "101011" => memoryC1_uid137_exp2TabGen_q <= "0100111100";
WHEN "101100" => memoryC1_uid137_exp2TabGen_q <= "0111010010";
WHEN "101101" => memoryC1_uid137_exp2TabGen_q <= "1000011011";
WHEN "101110" => memoryC1_uid137_exp2TabGen_q <= "0000011010";
WHEN "101111" => memoryC1_uid137_exp2TabGen_q <= "1100101101";
WHEN "110000" => memoryC1_uid137_exp2TabGen_q <= "0001100111";
WHEN "110001" => memoryC1_uid137_exp2TabGen_q <= "1011101011";
WHEN "110010" => memoryC1_uid137_exp2TabGen_q <= "0001010001";
WHEN "110011" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "110100" => memoryC1_uid137_exp2TabGen_q <= "0010010100";
WHEN "110101" => memoryC1_uid137_exp2TabGen_q <= "1000111100";
WHEN "110110" => memoryC1_uid137_exp2TabGen_q <= "0100100001";
WHEN "110111" => memoryC1_uid137_exp2TabGen_q <= "0011000111";
WHEN "111000" => memoryC1_uid137_exp2TabGen_q <= "0101110101";
WHEN "111001" => memoryC1_uid137_exp2TabGen_q <= "0010011001";
WHEN "111010" => memoryC1_uid137_exp2TabGen_q <= "0100110010";
WHEN "111011" => memoryC1_uid137_exp2TabGen_q <= "0000110110";
WHEN "111100" => memoryC1_uid137_exp2TabGen_q <= "0100000000";
WHEN "111101" => memoryC1_uid137_exp2TabGen_q <= "0110110101";
WHEN "111110" => memoryC1_uid137_exp2TabGen_q <= "1110110111";
WHEN "111111" => memoryC1_uid137_exp2TabGen_q <= "0000001100";
WHEN OTHERS =>
memoryC1_uid137_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC1_uid136_exp2TabGen(LOOKUP,135)@24
memoryC1_uid136_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC1_uid136_exp2TabGen_0_q) IS
WHEN "000000" => memoryC1_uid136_exp2TabGen_q <= "1110100001";
WHEN "000001" => memoryC1_uid136_exp2TabGen_q <= "1011101010";
WHEN "000010" => memoryC1_uid136_exp2TabGen_q <= "1001111011";
WHEN "000011" => memoryC1_uid136_exp2TabGen_q <= "1101000000";
WHEN "000100" => memoryC1_uid136_exp2TabGen_q <= "0101010110";
WHEN "000101" => memoryC1_uid136_exp2TabGen_q <= "0111110011";
WHEN "000110" => memoryC1_uid136_exp2TabGen_q <= "1100001000";
WHEN "000111" => memoryC1_uid136_exp2TabGen_q <= "0111000110";
WHEN "001000" => memoryC1_uid136_exp2TabGen_q <= "1111100101";
WHEN "001001" => memoryC1_uid136_exp2TabGen_q <= "1011111110";
WHEN "001010" => memoryC1_uid136_exp2TabGen_q <= "1100111001";
WHEN "001011" => memoryC1_uid136_exp2TabGen_q <= "0000110100";
WHEN "001100" => memoryC1_uid136_exp2TabGen_q <= "0011001010";
WHEN "001101" => memoryC1_uid136_exp2TabGen_q <= "0110000000";
WHEN "001110" => memoryC1_uid136_exp2TabGen_q <= "0111110100";
WHEN "001111" => memoryC1_uid136_exp2TabGen_q <= "0010111010";
WHEN "010000" => memoryC1_uid136_exp2TabGen_q <= "1010001000";
WHEN "010001" => memoryC1_uid136_exp2TabGen_q <= "1110011001";
WHEN "010010" => memoryC1_uid136_exp2TabGen_q <= "0010110011";
WHEN "010011" => memoryC1_uid136_exp2TabGen_q <= "1010001011";
WHEN "010100" => memoryC1_uid136_exp2TabGen_q <= "0001000101";
WHEN "010101" => memoryC1_uid136_exp2TabGen_q <= "0101000001";
WHEN "010110" => memoryC1_uid136_exp2TabGen_q <= "0101001010";
WHEN "010111" => memoryC1_uid136_exp2TabGen_q <= "0001011011";
WHEN "011000" => memoryC1_uid136_exp2TabGen_q <= "0110000010";
WHEN "011001" => memoryC1_uid136_exp2TabGen_q <= "0001011101";
WHEN "011010" => memoryC1_uid136_exp2TabGen_q <= "1000101110";
WHEN "011011" => memoryC1_uid136_exp2TabGen_q <= "1001001000";
WHEN "011100" => memoryC1_uid136_exp2TabGen_q <= "0100000001";
WHEN "011101" => memoryC1_uid136_exp2TabGen_q <= "1011001010";
WHEN "011110" => memoryC1_uid136_exp2TabGen_q <= "0110010111";
WHEN "011111" => memoryC1_uid136_exp2TabGen_q <= "1011110000";
WHEN "100000" => memoryC1_uid136_exp2TabGen_q <= "1110011101";
WHEN "100001" => memoryC1_uid136_exp2TabGen_q <= "0001110001";
WHEN "100010" => memoryC1_uid136_exp2TabGen_q <= "0110101101";
WHEN "100011" => memoryC1_uid136_exp2TabGen_q <= "0110001111";
WHEN "100100" => memoryC1_uid136_exp2TabGen_q <= "1100101111";
WHEN "100101" => memoryC1_uid136_exp2TabGen_q <= "0010000110";
WHEN "100110" => memoryC1_uid136_exp2TabGen_q <= "1110111000";
WHEN "100111" => memoryC1_uid136_exp2TabGen_q <= "0011010010";
WHEN "101000" => memoryC1_uid136_exp2TabGen_q <= "1001110001";
WHEN "101001" => memoryC1_uid136_exp2TabGen_q <= "1010000001";
WHEN "101010" => memoryC1_uid136_exp2TabGen_q <= "1001110000";
WHEN "101011" => memoryC1_uid136_exp2TabGen_q <= "1111100000";
WHEN "101100" => memoryC1_uid136_exp2TabGen_q <= "1111111100";
WHEN "101101" => memoryC1_uid136_exp2TabGen_q <= "0000001110";
WHEN "101110" => memoryC1_uid136_exp2TabGen_q <= "0100000101";
WHEN "101111" => memoryC1_uid136_exp2TabGen_q <= "1100000100";
WHEN "110000" => memoryC1_uid136_exp2TabGen_q <= "0110101011";
WHEN "110001" => memoryC1_uid136_exp2TabGen_q <= "1110100010";
WHEN "110010" => memoryC1_uid136_exp2TabGen_q <= "1010101100";
WHEN "110011" => memoryC1_uid136_exp2TabGen_q <= "1101110010";
WHEN "110100" => memoryC1_uid136_exp2TabGen_q <= "1000110011";
WHEN "110101" => memoryC1_uid136_exp2TabGen_q <= "1011111100";
WHEN "110110" => memoryC1_uid136_exp2TabGen_q <= "1001011001";
WHEN "110111" => memoryC1_uid136_exp2TabGen_q <= "1011010000";
WHEN "111000" => memoryC1_uid136_exp2TabGen_q <= "0110110011";
WHEN "111001" => memoryC1_uid136_exp2TabGen_q <= "0110100001";
WHEN "111010" => memoryC1_uid136_exp2TabGen_q <= "0001001111";
WHEN "111011" => memoryC1_uid136_exp2TabGen_q <= "0111110010";
WHEN "111100" => memoryC1_uid136_exp2TabGen_q <= "0000000000";
WHEN "111101" => memoryC1_uid136_exp2TabGen_q <= "0110101001";
WHEN "111110" => memoryC1_uid136_exp2TabGen_q <= "0001111000";
WHEN "111111" => memoryC1_uid136_exp2TabGen_q <= "0101100100";
WHEN OTHERS =>
memoryC1_uid136_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid142_exp2TabGen(BITJOIN,141)@24
os_uid142_exp2TabGen_q <= GND_q & memoryC1_uid140_exp2TabGen_q & memoryC1_uid139_exp2TabGen_q & memoryC1_uid138_exp2TabGen_q & memoryC1_uid137_exp2TabGen_q & memoryC1_uid136_exp2TabGen_q;
--cIncludingRoundingBit_uid182_exp2PolyEval(BITJOIN,181)@24
cIncludingRoundingBit_uid182_exp2PolyEval_q <= os_uid142_exp2TabGen_q & rndBit_uid169_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0(REG,325)@24
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q <= cIncludingRoundingBit_uid182_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid183_exp2PolyEval(ADD,182)@25
ts4_uid183_exp2PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid182_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_0_q);
ts4_uid183_exp2PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q(45)) & reg_R_uid237_pT4_uid180_exp2PolyEval_0_to_ts4_uid183_exp2PolyEval_1_q);
ts4_uid183_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid183_exp2PolyEval_a) + SIGNED(ts4_uid183_exp2PolyEval_b));
ts4_uid183_exp2PolyEval_q <= ts4_uid183_exp2PolyEval_o(53 downto 0);
--s4_uid184_exp2PolyEval(BITSELECT,183)@25
s4_uid184_exp2PolyEval_in <= ts4_uid183_exp2PolyEval_q;
s4_uid184_exp2PolyEval_b <= s4_uid184_exp2PolyEval_in(53 downto 1);
--yTop27Bits_uid239_pT5_uid186_exp2PolyEval(BITSELECT,238)@25
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b;
yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9(REG,330)@25
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q <= yTop27Bits_uid239_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor(LOGICAL,865)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q <= not (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_a or ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_b);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top(CONSTANT,861)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q <= "010001";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp(LOGICAL,862)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_mem_top_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_a = ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg(REG,863)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena(REG,866)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd(LOGICAL,867)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_a and ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_b;
--xBottomBits_uid242_pT5_uid186_exp2PolyEval(BITSELECT,241)@5
xBottomBits_uid242_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
xBottomBits_uid242_pT5_uid186_exp2PolyEval_b <= xBottomBits_uid242_pT5_uid186_exp2PolyEval_in(18 downto 0);
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg(DELAY,855)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => xBottomBits_uid242_pT5_uid186_exp2PolyEval_b, xout => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt(COUNTER,857)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg(REG,858)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux(MUX,859)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem(DUALMEM,856)
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_inputreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 5,
numwords_a => 18,
width_b => 19,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_iq(18 downto 0);
--pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval(BITJOIN,245)@25
pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7(REG,329)@25
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q <= pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor(LOGICAL,852)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q <= not (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_a or ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_b);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top(CONSTANT,848)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q <= "010010";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp(LOGICAL,849)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_mem_top_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_a = ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg(REG,850)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena(REG,853)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd(LOGICAL,854)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_a and ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_b;
--xTop26Bits_uid243_pT5_uid186_exp2PolyEval(BITSELECT,242)@5
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b;
xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b <= xTop26Bits_uid243_pT5_uid186_exp2PolyEval_in(45 downto 20);
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg(DELAY,842)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b, xout => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt(COUNTER,844)
-- every=1, low=0, high=18, step=1, init=1
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i = 17 THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i - 18;
ELSE
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg(REG,845)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux(MUX,846)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem(DUALMEM,843)
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_inputreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 19,
width_b => 26,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval(BITJOIN,244)@26
spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q <= GND_q & ld_xTop26Bits_uid243_pT5_uid186_exp2PolyEval_b_to_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6(REG,328)@26
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q <= spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid241_pT5_uid186_exp2PolyEval(BITSELECT,240)@25
yBottomBits_uid241_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
yBottomBits_uid241_pT5_uid186_exp2PolyEval_b <= yBottomBits_uid241_pT5_uid186_exp2PolyEval_in(25 downto 0);
--ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b(DELAY,610)@25
ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid241_pT5_uid186_exp2PolyEval_b, xout => ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval(BITJOIN,246)@26
pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q <= ld_yBottomBits_uid241_pT5_uid186_exp2PolyEval_b_to_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4(REG,327)@26
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q <= pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma(CHAINMULTADD,261)@27
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1),28));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(0) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_l(1) * multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(0),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_p(1),56);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_w(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) + multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_x(1);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid241_uid247_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_4_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_7_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid243_uid245_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_6_q),27);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(0);
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(1) <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval(BITSELECT,248)@30
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_q;
multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_in(54 downto 1);
--highBBits_uid255_pT5_uid186_exp2PolyEval(BITSELECT,254)@30
highBBits_uid255_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b;
highBBits_uid255_pT5_uid186_exp2PolyEval_b <= highBBits_uid255_pT5_uid186_exp2PolyEval_in(53 downto 19);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor(LOGICAL,943)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q <= not (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_a or ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_b);
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top(CONSTANT,939)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q <= "01101";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp(LOGICAL,940)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_mem_top_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q <= "1" when ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_a = ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_b else "0";
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg(REG,941)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena(REG,944)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd(LOGICAL,945)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_sticky_ena_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_a and ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_b;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg(DELAY,933)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yT2_uid167_exp2PolyEval_b, xout => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt(COUNTER,935)
-- every=1, low=0, high=13, step=1, init=1
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i = 12 THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_eq = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i - 13;
ELSE
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_i,4));
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg(REG,936)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux(MUX,937)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q, ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem(DUALMEM,934)
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_inputreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 4,
numwords_a => 14,
width_b => 27,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0(REG,333)@25
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q <= ld_yT2_uid167_exp2PolyEval_b_to_reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid240_pT5_uid186_exp2PolyEval(MULT,239)@26
topProd_uid240_pT5_uid186_exp2PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_a),28)) * SIGNED(topProd_uid240_pT5_uid186_exp2PolyEval_b);
topProd_uid240_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_b <= (others => '0');
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_a <= reg_yT2_uid167_exp2PolyEval_0_to_topProd_uid240_pT5_uid186_exp2PolyEval_0_q;
topProd_uid240_pT5_uid186_exp2PolyEval_b <= reg_yTop27Bits_uid239_pT5_uid186_exp2PolyEval_0_to_multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_cma_9_q;
topProd_uid240_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid240_pT5_uid186_exp2PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid240_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid240_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor(LOGICAL,930)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q <= not (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_a or ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_b);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena(REG,931)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_nor_q = "1") THEN
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd(LOGICAL,932)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_sticky_ena_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b <= en;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_a and ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_b;
--sSM0W_uid251_pT5_uid186_exp2PolyEval(BITSELECT,250)@5
sSM0W_uid251_pT5_uid186_exp2PolyEval_in <= yPPolyEval_uid48_fpExp2Test_b(18 downto 0);
sSM0W_uid251_pT5_uid186_exp2PolyEval_b <= sSM0W_uid251_pT5_uid186_exp2PolyEval_in(18 downto 16);
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg(DELAY,920)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => sSM0W_uid251_pT5_uid186_exp2PolyEval_b, xout => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem(DUALMEM,921)
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_inputreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdreg_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab <= ld_xBottomBits_uid242_pT5_uid186_exp2PolyEval_b_to_pad_xBottomBits_uid242_uid246_pT5_uid186_exp2PolyEval_b_replace_rdmux_q;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 18,
width_b => 3,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq,
address_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_aa,
data_a => ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_ia
);
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_reset0 <= areset;
ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_iq(2 downto 0);
--reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1(REG,332)@25
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q <= ld_sSM0W_uid251_pT5_uid186_exp2PolyEval_b_to_reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid250_pT5_uid186_exp2PolyEval(BITSELECT,249)@25
sSM0H_uid250_pT5_uid186_exp2PolyEval_in <= s4_uid184_exp2PolyEval_b(25 downto 0);
sSM0H_uid250_pT5_uid186_exp2PolyEval_b <= sSM0H_uid250_pT5_uid186_exp2PolyEval_in(25 downto 23);
--reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0(REG,331)@25
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q <= sSM0H_uid250_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid252_pT5_uid186_exp2PolyEval(MULT,251)@26
sm0_uid252_pT5_uid186_exp2PolyEval_pr <= UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_a) * UNSIGNED(sm0_uid252_pT5_uid186_exp2PolyEval_b);
sm0_uid252_pT5_uid186_exp2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_b <= (others => '0');
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_a <= reg_sSM0H_uid250_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_0_q;
sm0_uid252_pT5_uid186_exp2PolyEval_b <= reg_sSM0W_uid251_pT5_uid186_exp2PolyEval_0_to_sm0_uid252_pT5_uid186_exp2PolyEval_1_q;
sm0_uid252_pT5_uid186_exp2PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid252_pT5_uid186_exp2PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid252_pT5_uid186_exp2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid252_pT5_uid186_exp2PolyEval_q <= sm0_uid252_pT5_uid186_exp2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval(BITJOIN,252)@29
TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q <= topProd_uid240_pT5_uid186_exp2PolyEval_q & sm0_uid252_pT5_uid186_exp2PolyEval_q;
--ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a(DELAY,620)@29
ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q, xout => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid256_pT5_uid186_exp2PolyEval(ADD,255)@30
sumAHighB_uid256_pT5_uid186_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid253_pT5_uid186_exp2PolyEval_q_to_sumAHighB_uid256_pT5_uid186_exp2PolyEval_a_q);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid255_pT5_uid186_exp2PolyEval_b(34)) & highBBits_uid255_pT5_uid186_exp2PolyEval_b);
sumAHighB_uid256_pT5_uid186_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_a) + SIGNED(sumAHighB_uid256_pT5_uid186_exp2PolyEval_b));
sumAHighB_uid256_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_o(60 downto 0);
--lowRangeB_uid254_pT5_uid186_exp2PolyEval(BITSELECT,253)@30
lowRangeB_uid254_pT5_uid186_exp2PolyEval_in <= multSumOfTwo27_uid245_pT5_uid186_exp2PolyEval_b(18 downto 0);
lowRangeB_uid254_pT5_uid186_exp2PolyEval_b <= lowRangeB_uid254_pT5_uid186_exp2PolyEval_in(18 downto 0);
--add0_uid254_uid257_pT5_uid186_exp2PolyEval(BITJOIN,256)@30
add0_uid254_uid257_pT5_uid186_exp2PolyEval_q <= sumAHighB_uid256_pT5_uid186_exp2PolyEval_q & lowRangeB_uid254_pT5_uid186_exp2PolyEval_b;
--R_uid258_pT5_uid186_exp2PolyEval(BITSELECT,257)@30
R_uid258_pT5_uid186_exp2PolyEval_in <= add0_uid254_uid257_pT5_uid186_exp2PolyEval_q(78 downto 0);
R_uid258_pT5_uid186_exp2PolyEval_b <= R_uid258_pT5_uid186_exp2PolyEval_in(78 downto 24);
--reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1(REG,336)@30
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q <= R_uid258_pT5_uid186_exp2PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor(LOGICAL,750)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q <= not (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_a or ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_b);
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top(CONSTANT,746)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q <= "010110";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp(LOGICAL,747)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_mem_top_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q <= "1" when ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_a = ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_b else "0";
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg(REG,748)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena(REG,751)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd(LOGICAL,752)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_sticky_ena_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_a and ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_b;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt(COUNTER,742)
-- every=1, low=0, high=22, step=1, init=1
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i = 21 THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i - 22;
ELSE
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg(REG,743)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux(MUX,744)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q, ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem(DUALMEM,741)
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_inputreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_ia
);
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_iq(5 downto 0);
--memoryC0_uid134_exp2TabGen(LOOKUP,133)@30
memoryC0_uid134_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000001" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000010" => memoryC0_uid134_exp2TabGen_q <= "0100000";
WHEN "000011" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000100" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000101" => memoryC0_uid134_exp2TabGen_q <= "0100001";
WHEN "000110" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "000111" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001000" => memoryC0_uid134_exp2TabGen_q <= "0100010";
WHEN "001001" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001010" => memoryC0_uid134_exp2TabGen_q <= "0100011";
WHEN "001011" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001100" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001101" => memoryC0_uid134_exp2TabGen_q <= "0100100";
WHEN "001110" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "001111" => memoryC0_uid134_exp2TabGen_q <= "0100101";
WHEN "010000" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010001" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010010" => memoryC0_uid134_exp2TabGen_q <= "0100110";
WHEN "010011" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010100" => memoryC0_uid134_exp2TabGen_q <= "0100111";
WHEN "010101" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010110" => memoryC0_uid134_exp2TabGen_q <= "0101000";
WHEN "010111" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011000" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011001" => memoryC0_uid134_exp2TabGen_q <= "0101001";
WHEN "011010" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011011" => memoryC0_uid134_exp2TabGen_q <= "0101010";
WHEN "011100" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011101" => memoryC0_uid134_exp2TabGen_q <= "0101011";
WHEN "011110" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "011111" => memoryC0_uid134_exp2TabGen_q <= "0101100";
WHEN "100000" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100001" => memoryC0_uid134_exp2TabGen_q <= "0101101";
WHEN "100010" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100011" => memoryC0_uid134_exp2TabGen_q <= "0101110";
WHEN "100100" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100101" => memoryC0_uid134_exp2TabGen_q <= "0101111";
WHEN "100110" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "100111" => memoryC0_uid134_exp2TabGen_q <= "0110000";
WHEN "101000" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101001" => memoryC0_uid134_exp2TabGen_q <= "0110001";
WHEN "101010" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101011" => memoryC0_uid134_exp2TabGen_q <= "0110010";
WHEN "101100" => memoryC0_uid134_exp2TabGen_q <= "0110011";
WHEN "101101" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101110" => memoryC0_uid134_exp2TabGen_q <= "0110100";
WHEN "101111" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110000" => memoryC0_uid134_exp2TabGen_q <= "0110101";
WHEN "110001" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110010" => memoryC0_uid134_exp2TabGen_q <= "0110110";
WHEN "110011" => memoryC0_uid134_exp2TabGen_q <= "0110111";
WHEN "110100" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110101" => memoryC0_uid134_exp2TabGen_q <= "0111000";
WHEN "110110" => memoryC0_uid134_exp2TabGen_q <= "0111001";
WHEN "110111" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111000" => memoryC0_uid134_exp2TabGen_q <= "0111010";
WHEN "111001" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111010" => memoryC0_uid134_exp2TabGen_q <= "0111011";
WHEN "111011" => memoryC0_uid134_exp2TabGen_q <= "0111100";
WHEN "111100" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111101" => memoryC0_uid134_exp2TabGen_q <= "0111101";
WHEN "111110" => memoryC0_uid134_exp2TabGen_q <= "0111110";
WHEN "111111" => memoryC0_uid134_exp2TabGen_q <= "0111111";
WHEN OTHERS =>
memoryC0_uid134_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor(LOGICAL,878)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q <= not (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_a or ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_b);
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena(REG,879)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_nor_q = "1") THEN
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd(LOGICAL,880)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_sticky_ena_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b <= en;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_a and ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_b;
--ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem(DUALMEM,869)
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_inputreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdreg_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_rdmux_q;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 23,
width_b => 6,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_ia
);
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_iq(5 downto 0);
--reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0(REG,278)@29
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q <= ld_addr_uid47_fpExp2Test_b_to_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid133_exp2TabGen(LOOKUP,132)@30
memoryC0_uid133_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid133_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid133_exp2TabGen_q <= "0101100100";
WHEN "000010" => memoryC0_uid133_exp2TabGen_q <= "1011001101";
WHEN "000011" => memoryC0_uid133_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid133_exp2TabGen_q <= "0110101010";
WHEN "000101" => memoryC0_uid133_exp2TabGen_q <= "1100011111";
WHEN "000110" => memoryC0_uid133_exp2TabGen_q <= "0010011000";
WHEN "000111" => memoryC0_uid133_exp2TabGen_q <= "1000010100";
WHEN "001000" => memoryC0_uid133_exp2TabGen_q <= "1110010101";
WHEN "001001" => memoryC0_uid133_exp2TabGen_q <= "0100011010";
WHEN "001010" => memoryC0_uid133_exp2TabGen_q <= "1010100100";
WHEN "001011" => memoryC0_uid133_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid133_exp2TabGen_q <= "0111000011";
WHEN "001101" => memoryC0_uid133_exp2TabGen_q <= "1101011010";
WHEN "001110" => memoryC0_uid133_exp2TabGen_q <= "0011110100";
WHEN "001111" => memoryC0_uid133_exp2TabGen_q <= "1010010100";
WHEN "010000" => memoryC0_uid133_exp2TabGen_q <= "0000110111";
WHEN "010001" => memoryC0_uid133_exp2TabGen_q <= "0111100000";
WHEN "010010" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "010011" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN "010100" => memoryC0_uid133_exp2TabGen_q <= "1011110101";
WHEN "010101" => memoryC0_uid133_exp2TabGen_q <= "0010110000";
WHEN "010110" => memoryC0_uid133_exp2TabGen_q <= "1001110000";
WHEN "010111" => memoryC0_uid133_exp2TabGen_q <= "0000110101";
WHEN "011000" => memoryC0_uid133_exp2TabGen_q <= "0111111110";
WHEN "011001" => memoryC0_uid133_exp2TabGen_q <= "1111001101";
WHEN "011010" => memoryC0_uid133_exp2TabGen_q <= "0110100001";
WHEN "011011" => memoryC0_uid133_exp2TabGen_q <= "1101111010";
WHEN "011100" => memoryC0_uid133_exp2TabGen_q <= "0101011000";
WHEN "011101" => memoryC0_uid133_exp2TabGen_q <= "1100111011";
WHEN "011110" => memoryC0_uid133_exp2TabGen_q <= "0100100011";
WHEN "011111" => memoryC0_uid133_exp2TabGen_q <= "1100010001";
WHEN "100000" => memoryC0_uid133_exp2TabGen_q <= "0100000100";
WHEN "100001" => memoryC0_uid133_exp2TabGen_q <= "1011111101";
WHEN "100010" => memoryC0_uid133_exp2TabGen_q <= "0011111011";
WHEN "100011" => memoryC0_uid133_exp2TabGen_q <= "1011111111";
WHEN "100100" => memoryC0_uid133_exp2TabGen_q <= "0100001000";
WHEN "100101" => memoryC0_uid133_exp2TabGen_q <= "1100010111";
WHEN "100110" => memoryC0_uid133_exp2TabGen_q <= "0100101100";
WHEN "100111" => memoryC0_uid133_exp2TabGen_q <= "1101000110";
WHEN "101000" => memoryC0_uid133_exp2TabGen_q <= "0101100111";
WHEN "101001" => memoryC0_uid133_exp2TabGen_q <= "1110001101";
WHEN "101010" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "101011" => memoryC0_uid133_exp2TabGen_q <= "1111101100";
WHEN "101100" => memoryC0_uid133_exp2TabGen_q <= "1000100100";
WHEN "101101" => memoryC0_uid133_exp2TabGen_q <= "0001100011";
WHEN "101110" => memoryC0_uid133_exp2TabGen_q <= "1010101000";
WHEN "101111" => memoryC0_uid133_exp2TabGen_q <= "0011110011";
WHEN "110000" => memoryC0_uid133_exp2TabGen_q <= "1101000100";
WHEN "110001" => memoryC0_uid133_exp2TabGen_q <= "0110011101";
WHEN "110010" => memoryC0_uid133_exp2TabGen_q <= "1111111011";
WHEN "110011" => memoryC0_uid133_exp2TabGen_q <= "1001100000";
WHEN "110100" => memoryC0_uid133_exp2TabGen_q <= "0011001100";
WHEN "110101" => memoryC0_uid133_exp2TabGen_q <= "1100111111";
WHEN "110110" => memoryC0_uid133_exp2TabGen_q <= "0110111001";
WHEN "110111" => memoryC0_uid133_exp2TabGen_q <= "0000111001";
WHEN "111000" => memoryC0_uid133_exp2TabGen_q <= "1011000000";
WHEN "111001" => memoryC0_uid133_exp2TabGen_q <= "0101001111";
WHEN "111010" => memoryC0_uid133_exp2TabGen_q <= "1111100100";
WHEN "111011" => memoryC0_uid133_exp2TabGen_q <= "1010000001";
WHEN "111100" => memoryC0_uid133_exp2TabGen_q <= "0100100101";
WHEN "111101" => memoryC0_uid133_exp2TabGen_q <= "1111010000";
WHEN "111110" => memoryC0_uid133_exp2TabGen_q <= "1010000011";
WHEN "111111" => memoryC0_uid133_exp2TabGen_q <= "0100111110";
WHEN OTHERS =>
memoryC0_uid133_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid132_exp2TabGen(LOOKUP,131)@30
memoryC0_uid132_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid132_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid132_exp2TabGen_q <= "1101000111";
WHEN "000010" => memoryC0_uid132_exp2TabGen_q <= "1000011010";
WHEN "000011" => memoryC0_uid132_exp2TabGen_q <= "0010100011";
WHEN "000100" => memoryC0_uid132_exp2TabGen_q <= "1100001101";
WHEN "000101" => memoryC0_uid132_exp2TabGen_q <= "0110000110";
WHEN "000110" => memoryC0_uid132_exp2TabGen_q <= "0000111010";
WHEN "000111" => memoryC0_uid132_exp2TabGen_q <= "1101010101";
WHEN "001000" => memoryC0_uid132_exp2TabGen_q <= "1100000111";
WHEN "001001" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "001010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "001011" => memoryC0_uid132_exp2TabGen_q <= "1101110001";
WHEN "001100" => memoryC0_uid132_exp2TabGen_q <= "1101001101";
WHEN "001101" => memoryC0_uid132_exp2TabGen_q <= "0010101100";
WHEN "001110" => memoryC0_uid132_exp2TabGen_q <= "1110111110";
WHEN "001111" => memoryC0_uid132_exp2TabGen_q <= "0010110100";
WHEN "010000" => memoryC0_uid132_exp2TabGen_q <= "1111000001";
WHEN "010001" => memoryC0_uid132_exp2TabGen_q <= "0100010110";
WHEN "010010" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "010011" => memoryC0_uid132_exp2TabGen_q <= "1101100110";
WHEN "010100" => memoryC0_uid132_exp2TabGen_q <= "0011001001";
WHEN "010101" => memoryC0_uid132_exp2TabGen_q <= "0101000100";
WHEN "010110" => memoryC0_uid132_exp2TabGen_q <= "0100001100";
WHEN "010111" => memoryC0_uid132_exp2TabGen_q <= "0001010110";
WHEN "011000" => memoryC0_uid132_exp2TabGen_q <= "1101011010";
WHEN "011001" => memoryC0_uid132_exp2TabGen_q <= "1001001110";
WHEN "011010" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "011011" => memoryC0_uid132_exp2TabGen_q <= "0011100110";
WHEN "011100" => memoryC0_uid132_exp2TabGen_q <= "0011111011";
WHEN "011101" => memoryC0_uid132_exp2TabGen_q <= "0111100010";
WHEN "011110" => memoryC0_uid132_exp2TabGen_q <= "1111010110";
WHEN "011111" => memoryC0_uid132_exp2TabGen_q <= "1100010000";
WHEN "100000" => memoryC0_uid132_exp2TabGen_q <= "1111001100";
WHEN "100001" => memoryC0_uid132_exp2TabGen_q <= "1001000111";
WHEN "100010" => memoryC0_uid132_exp2TabGen_q <= "1010111101";
WHEN "100011" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "100100" => memoryC0_uid132_exp2TabGen_q <= "1010001110";
WHEN "100101" => memoryC0_uid132_exp2TabGen_q <= "1001100110";
WHEN "100110" => memoryC0_uid132_exp2TabGen_q <= "0100110011";
WHEN "100111" => memoryC0_uid132_exp2TabGen_q <= "1100110011";
WHEN "101000" => memoryC0_uid132_exp2TabGen_q <= "0010101000";
WHEN "101001" => memoryC0_uid132_exp2TabGen_q <= "0111010011";
WHEN "101010" => memoryC0_uid132_exp2TabGen_q <= "1011110110";
WHEN "101011" => memoryC0_uid132_exp2TabGen_q <= "0001010011";
WHEN "101100" => memoryC0_uid132_exp2TabGen_q <= "1000110000";
WHEN "101101" => memoryC0_uid132_exp2TabGen_q <= "0011001111";
WHEN "101110" => memoryC0_uid132_exp2TabGen_q <= "0001110110";
WHEN "101111" => memoryC0_uid132_exp2TabGen_q <= "0101101010";
WHEN "110000" => memoryC0_uid132_exp2TabGen_q <= "1111110011";
WHEN "110001" => memoryC0_uid132_exp2TabGen_q <= "0001010111";
WHEN "110010" => memoryC0_uid132_exp2TabGen_q <= "1011011110";
WHEN "110011" => memoryC0_uid132_exp2TabGen_q <= "1111010010";
WHEN "110100" => memoryC0_uid132_exp2TabGen_q <= "1101111011";
WHEN "110101" => memoryC0_uid132_exp2TabGen_q <= "1000100101";
WHEN "110110" => memoryC0_uid132_exp2TabGen_q <= "0000011011";
WHEN "110111" => memoryC0_uid132_exp2TabGen_q <= "0110101001";
WHEN "111000" => memoryC0_uid132_exp2TabGen_q <= "1100011011";
WHEN "111001" => memoryC0_uid132_exp2TabGen_q <= "0011000000";
WHEN "111010" => memoryC0_uid132_exp2TabGen_q <= "1011100110";
WHEN "111011" => memoryC0_uid132_exp2TabGen_q <= "0111011100";
WHEN "111100" => memoryC0_uid132_exp2TabGen_q <= "0111110100";
WHEN "111101" => memoryC0_uid132_exp2TabGen_q <= "1101111101";
WHEN "111110" => memoryC0_uid132_exp2TabGen_q <= "1011001011";
WHEN "111111" => memoryC0_uid132_exp2TabGen_q <= "0000110000";
WHEN OTHERS =>
memoryC0_uid132_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid131_exp2TabGen(LOOKUP,130)@30
memoryC0_uid131_exp2TabGen: PROCESS (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid131_exp2TabGen_0_q_to_memoryC0_uid131_exp2TabGen_a_replace_mem_q) IS
WHEN "000000" => memoryC0_uid131_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid131_exp2TabGen_q <= "1100111011";
WHEN "000010" => memoryC0_uid131_exp2TabGen_q <= "0110001010";
WHEN "000011" => memoryC0_uid131_exp2TabGen_q <= "0000111010";
WHEN "000100" => memoryC0_uid131_exp2TabGen_q <= "1001111100";
WHEN "000101" => memoryC0_uid131_exp2TabGen_q <= "0101101001";
WHEN "000110" => memoryC0_uid131_exp2TabGen_q <= "0000001001";
WHEN "000111" => memoryC0_uid131_exp2TabGen_q <= "1101010100";
WHEN "001000" => memoryC0_uid131_exp2TabGen_q <= "1000111110";
WHEN "001001" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "001010" => memoryC0_uid131_exp2TabGen_q <= "0010110100";
WHEN "001011" => memoryC0_uid131_exp2TabGen_q <= "0000110001";
WHEN "001100" => memoryC0_uid131_exp2TabGen_q <= "1100111010";
WHEN "001101" => memoryC0_uid131_exp2TabGen_q <= "1011110001";
WHEN "001110" => memoryC0_uid131_exp2TabGen_q <= "1010001111";
WHEN "001111" => memoryC0_uid131_exp2TabGen_q <= "1101110010";
WHEN "010000" => memoryC0_uid131_exp2TabGen_q <= "0100011000";
WHEN "010001" => memoryC0_uid131_exp2TabGen_q <= "0100110010";
WHEN "010010" => memoryC0_uid131_exp2TabGen_q <= "1110011101";
WHEN "010011" => memoryC0_uid131_exp2TabGen_q <= "1001110010";
WHEN "010100" => memoryC0_uid131_exp2TabGen_q <= "1000001001";
WHEN "010101" => memoryC0_uid131_exp2TabGen_q <= "0011111011";
WHEN "010110" => memoryC0_uid131_exp2TabGen_q <= "0000110000";
WHEN "010111" => memoryC0_uid131_exp2TabGen_q <= "1011100000";
WHEN "011000" => memoryC0_uid131_exp2TabGen_q <= "1010011011";
WHEN "011001" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011010" => memoryC0_uid131_exp2TabGen_q <= "1101001110";
WHEN "011011" => memoryC0_uid131_exp2TabGen_q <= "1101011010";
WHEN "011100" => memoryC0_uid131_exp2TabGen_q <= "1010100100";
WHEN "011101" => memoryC0_uid131_exp2TabGen_q <= "1011010110";
WHEN "011110" => memoryC0_uid131_exp2TabGen_q <= "0000011101";
WHEN "011111" => memoryC0_uid131_exp2TabGen_q <= "0100101010";
WHEN "100000" => memoryC0_uid131_exp2TabGen_q <= "1100111111";
WHEN "100001" => memoryC0_uid131_exp2TabGen_q <= "1000110010";
WHEN "100010" => memoryC0_uid131_exp2TabGen_q <= "0001110110";
WHEN "100011" => memoryC0_uid131_exp2TabGen_q <= "1100100001";
WHEN "100100" => memoryC0_uid131_exp2TabGen_q <= "0111110101";
WHEN "100101" => memoryC0_uid131_exp2TabGen_q <= "1101100111";
WHEN "100110" => memoryC0_uid131_exp2TabGen_q <= "0010100110";
WHEN "100111" => memoryC0_uid131_exp2TabGen_q <= "0110100010";
WHEN "101000" => memoryC0_uid131_exp2TabGen_q <= "0100010101";
WHEN "101001" => memoryC0_uid131_exp2TabGen_q <= "0010001010";
WHEN "101010" => memoryC0_uid131_exp2TabGen_q <= "0001100110";
WHEN "101011" => memoryC0_uid131_exp2TabGen_q <= "1111101111";
WHEN "101100" => memoryC0_uid131_exp2TabGen_q <= "0101010001";
WHEN "101101" => memoryC0_uid131_exp2TabGen_q <= "0110101110";
WHEN "101110" => memoryC0_uid131_exp2TabGen_q <= "0100011111";
WHEN "101111" => memoryC0_uid131_exp2TabGen_q <= "1010111100";
WHEN "110000" => memoryC0_uid131_exp2TabGen_q <= "0010101101";
WHEN "110001" => memoryC0_uid131_exp2TabGen_q <= "0000100111";
WHEN "110010" => memoryC0_uid131_exp2TabGen_q <= "0101111101";
WHEN "110011" => memoryC0_uid131_exp2TabGen_q <= "0000100101";
WHEN "110100" => memoryC0_uid131_exp2TabGen_q <= "1011000010";
WHEN "110101" => memoryC0_uid131_exp2TabGen_q <= "1100101011";
WHEN "110110" => memoryC0_uid131_exp2TabGen_q <= "1001110111";
WHEN "110111" => memoryC0_uid131_exp2TabGen_q <= "0100000011";
WHEN "111000" => memoryC0_uid131_exp2TabGen_q <= "1001111101";
WHEN "111001" => memoryC0_uid131_exp2TabGen_q <= "0111101101";
WHEN "111010" => memoryC0_uid131_exp2TabGen_q <= "0110111101";
WHEN "111011" => memoryC0_uid131_exp2TabGen_q <= "1111000101";
WHEN "111100" => memoryC0_uid131_exp2TabGen_q <= "0101010010";
WHEN "111101" => memoryC0_uid131_exp2TabGen_q <= "1100110000";
WHEN "111110" => memoryC0_uid131_exp2TabGen_q <= "0110110111";
WHEN "111111" => memoryC0_uid131_exp2TabGen_q <= "0011001111";
WHEN OTHERS =>
memoryC0_uid131_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid130_exp2TabGen(LOOKUP,129)@30
memoryC0_uid130_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid130_exp2TabGen_q <= "0000000000";
WHEN "000001" => memoryC0_uid130_exp2TabGen_q <= "1100000000";
WHEN "000010" => memoryC0_uid130_exp2TabGen_q <= "1100001010";
WHEN "000011" => memoryC0_uid130_exp2TabGen_q <= "1100110111";
WHEN "000100" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "000101" => memoryC0_uid130_exp2TabGen_q <= "1110100011";
WHEN "000110" => memoryC0_uid130_exp2TabGen_q <= "0010110110";
WHEN "000111" => memoryC0_uid130_exp2TabGen_q <= "1001011011";
WHEN "001000" => memoryC0_uid130_exp2TabGen_q <= "1010100010";
WHEN "001001" => memoryC0_uid130_exp2TabGen_q <= "1110010110";
WHEN "001010" => memoryC0_uid130_exp2TabGen_q <= "0101110011";
WHEN "001011" => memoryC0_uid130_exp2TabGen_q <= "0100011001";
WHEN "001100" => memoryC0_uid130_exp2TabGen_q <= "1011000100";
WHEN "001101" => memoryC0_uid130_exp2TabGen_q <= "0011111001";
WHEN "001110" => memoryC0_uid130_exp2TabGen_q <= "1110111101";
WHEN "001111" => memoryC0_uid130_exp2TabGen_q <= "0000000110";
WHEN "010000" => memoryC0_uid130_exp2TabGen_q <= "1101101110";
WHEN "010001" => memoryC0_uid130_exp2TabGen_q <= "0000101101";
WHEN "010010" => memoryC0_uid130_exp2TabGen_q <= "0101010011";
WHEN "010011" => memoryC0_uid130_exp2TabGen_q <= "1100111111";
WHEN "010100" => memoryC0_uid130_exp2TabGen_q <= "0001101000";
WHEN "010101" => memoryC0_uid130_exp2TabGen_q <= "1001011100";
WHEN "010110" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "010111" => memoryC0_uid130_exp2TabGen_q <= "1001111001";
WHEN "011000" => memoryC0_uid130_exp2TabGen_q <= "0001010100";
WHEN "011001" => memoryC0_uid130_exp2TabGen_q <= "1001011001";
WHEN "011010" => memoryC0_uid130_exp2TabGen_q <= "1010011111";
WHEN "011011" => memoryC0_uid130_exp2TabGen_q <= "1001001111";
WHEN "011100" => memoryC0_uid130_exp2TabGen_q <= "0010101000";
WHEN "011101" => memoryC0_uid130_exp2TabGen_q <= "1001000010";
WHEN "011110" => memoryC0_uid130_exp2TabGen_q <= "0010101011";
WHEN "011111" => memoryC0_uid130_exp2TabGen_q <= "1001000100";
WHEN "100000" => memoryC0_uid130_exp2TabGen_q <= "1001110111";
WHEN "100001" => memoryC0_uid130_exp2TabGen_q <= "1000110100";
WHEN "100010" => memoryC0_uid130_exp2TabGen_q <= "0010111110";
WHEN "100011" => memoryC0_uid130_exp2TabGen_q <= "0011001111";
WHEN "100100" => memoryC0_uid130_exp2TabGen_q <= "1000000011";
WHEN "100101" => memoryC0_uid130_exp2TabGen_q <= "1010011100";
WHEN "100110" => memoryC0_uid130_exp2TabGen_q <= "0110011100";
WHEN "100111" => memoryC0_uid130_exp2TabGen_q <= "0100100101";
WHEN "101000" => memoryC0_uid130_exp2TabGen_q <= "0101000001";
WHEN "101001" => memoryC0_uid130_exp2TabGen_q <= "1011101110";
WHEN "101010" => memoryC0_uid130_exp2TabGen_q <= "1110001011";
WHEN "101011" => memoryC0_uid130_exp2TabGen_q <= "0010011100";
WHEN "101100" => memoryC0_uid130_exp2TabGen_q <= "1111100001";
WHEN "101101" => memoryC0_uid130_exp2TabGen_q <= "1111001010";
WHEN "101110" => memoryC0_uid130_exp2TabGen_q <= "0001001010";
WHEN "101111" => memoryC0_uid130_exp2TabGen_q <= "1111111011";
WHEN "110000" => memoryC0_uid130_exp2TabGen_q <= "0110100111";
WHEN "110001" => memoryC0_uid130_exp2TabGen_q <= "1000101011";
WHEN "110010" => memoryC0_uid130_exp2TabGen_q <= "1010111100";
WHEN "110011" => memoryC0_uid130_exp2TabGen_q <= "1110000011";
WHEN "110100" => memoryC0_uid130_exp2TabGen_q <= "1010100101";
WHEN "110101" => memoryC0_uid130_exp2TabGen_q <= "1110100010";
WHEN "110110" => memoryC0_uid130_exp2TabGen_q <= "1100100000";
WHEN "110111" => memoryC0_uid130_exp2TabGen_q <= "1100010010";
WHEN "111000" => memoryC0_uid130_exp2TabGen_q <= "1101001001";
WHEN "111001" => memoryC0_uid130_exp2TabGen_q <= "1001100101";
WHEN "111010" => memoryC0_uid130_exp2TabGen_q <= "1100110110";
WHEN "111011" => memoryC0_uid130_exp2TabGen_q <= "1001111111";
WHEN "111100" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN "111101" => memoryC0_uid130_exp2TabGen_q <= "1010110100";
WHEN "111110" => memoryC0_uid130_exp2TabGen_q <= "0010001010";
WHEN "111111" => memoryC0_uid130_exp2TabGen_q <= "0100100001";
WHEN OTHERS =>
memoryC0_uid130_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--memoryC0_uid129_exp2TabGen(LOOKUP,128)@30
memoryC0_uid129_exp2TabGen: PROCESS (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_addr_uid47_fpExp2Test_0_to_memoryC0_uid129_exp2TabGen_0_q) IS
WHEN "000000" => memoryC0_uid129_exp2TabGen_q <= "0000000100";
WHEN "000001" => memoryC0_uid129_exp2TabGen_q <= "1100001011";
WHEN "000010" => memoryC0_uid129_exp2TabGen_q <= "1110100110";
WHEN "000011" => memoryC0_uid129_exp2TabGen_q <= "1001000100";
WHEN "000100" => memoryC0_uid129_exp2TabGen_q <= "0001111111";
WHEN "000101" => memoryC0_uid129_exp2TabGen_q <= "0100010100";
WHEN "000110" => memoryC0_uid129_exp2TabGen_q <= "1010001001";
WHEN "000111" => memoryC0_uid129_exp2TabGen_q <= "1100000010";
WHEN "001000" => memoryC0_uid129_exp2TabGen_q <= "1111011011";
WHEN "001001" => memoryC0_uid129_exp2TabGen_q <= "1110101110";
WHEN "001010" => memoryC0_uid129_exp2TabGen_q <= "0101011000";
WHEN "001011" => memoryC0_uid129_exp2TabGen_q <= "1010110110";
WHEN "001100" => memoryC0_uid129_exp2TabGen_q <= "0111000111";
WHEN "001101" => memoryC0_uid129_exp2TabGen_q <= "1011101101";
WHEN "001110" => memoryC0_uid129_exp2TabGen_q <= "1100001101";
WHEN "001111" => memoryC0_uid129_exp2TabGen_q <= "0001011110";
WHEN "010000" => memoryC0_uid129_exp2TabGen_q <= "0010101101";
WHEN "010001" => memoryC0_uid129_exp2TabGen_q <= "1111111110";
WHEN "010010" => memoryC0_uid129_exp2TabGen_q <= "1001011001";
WHEN "010011" => memoryC0_uid129_exp2TabGen_q <= "1110111011";
WHEN "010100" => memoryC0_uid129_exp2TabGen_q <= "0100010110";
WHEN "010101" => memoryC0_uid129_exp2TabGen_q <= "0101010100";
WHEN "010110" => memoryC0_uid129_exp2TabGen_q <= "0101101100";
WHEN "010111" => memoryC0_uid129_exp2TabGen_q <= "1010000101";
WHEN "011000" => memoryC0_uid129_exp2TabGen_q <= "0100111101";
WHEN "011001" => memoryC0_uid129_exp2TabGen_q <= "0100111001";
WHEN "011010" => memoryC0_uid129_exp2TabGen_q <= "0000010011";
WHEN "011011" => memoryC0_uid129_exp2TabGen_q <= "1011010111";
WHEN "011100" => memoryC0_uid129_exp2TabGen_q <= "0101001111";
WHEN "011101" => memoryC0_uid129_exp2TabGen_q <= "1001000111";
WHEN "011110" => memoryC0_uid129_exp2TabGen_q <= "0000101010";
WHEN "011111" => memoryC0_uid129_exp2TabGen_q <= "0100101000";
WHEN "100000" => memoryC0_uid129_exp2TabGen_q <= "1001101000";
WHEN "100001" => memoryC0_uid129_exp2TabGen_q <= "0101111100";
WHEN "100010" => memoryC0_uid129_exp2TabGen_q <= "1110100011";
WHEN "100011" => memoryC0_uid129_exp2TabGen_q <= "1001001010";
WHEN "100100" => memoryC0_uid129_exp2TabGen_q <= "0000111011";
WHEN "100101" => memoryC0_uid129_exp2TabGen_q <= "1100010100";
WHEN "100110" => memoryC0_uid129_exp2TabGen_q <= "0010011000";
WHEN "100111" => memoryC0_uid129_exp2TabGen_q <= "1101101000";
WHEN "101000" => memoryC0_uid129_exp2TabGen_q <= "1011011111";
WHEN "101001" => memoryC0_uid129_exp2TabGen_q <= "0110110101";
WHEN "101010" => memoryC0_uid129_exp2TabGen_q <= "1100101100";
WHEN "101011" => memoryC0_uid129_exp2TabGen_q <= "1010000000";
WHEN "101100" => memoryC0_uid129_exp2TabGen_q <= "0010000101";
WHEN "101101" => memoryC0_uid129_exp2TabGen_q <= "1100101010";
WHEN "101110" => memoryC0_uid129_exp2TabGen_q <= "1011101000";
WHEN "101111" => memoryC0_uid129_exp2TabGen_q <= "0111111110";
WHEN "110000" => memoryC0_uid129_exp2TabGen_q <= "0101101111";
WHEN "110001" => memoryC0_uid129_exp2TabGen_q <= "1111011100";
WHEN "110010" => memoryC0_uid129_exp2TabGen_q <= "1000111011";
WHEN "110011" => memoryC0_uid129_exp2TabGen_q <= "1010010101";
WHEN "110100" => memoryC0_uid129_exp2TabGen_q <= "0011100101";
WHEN "110101" => memoryC0_uid129_exp2TabGen_q <= "1001011110";
WHEN "110110" => memoryC0_uid129_exp2TabGen_q <= "1101001101";
WHEN "110111" => memoryC0_uid129_exp2TabGen_q <= "1111100000";
WHEN "111000" => memoryC0_uid129_exp2TabGen_q <= "0000111101";
WHEN "111001" => memoryC0_uid129_exp2TabGen_q <= "0000101111";
WHEN "111010" => memoryC0_uid129_exp2TabGen_q <= "1011111010";
WHEN "111011" => memoryC0_uid129_exp2TabGen_q <= "1110110101";
WHEN "111100" => memoryC0_uid129_exp2TabGen_q <= "1011010000";
WHEN "111101" => memoryC0_uid129_exp2TabGen_q <= "0101000000";
WHEN "111110" => memoryC0_uid129_exp2TabGen_q <= "1000000111";
WHEN "111111" => memoryC0_uid129_exp2TabGen_q <= "1011000101";
WHEN OTHERS =>
memoryC0_uid129_exp2TabGen_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--os_uid135_exp2TabGen(BITJOIN,134)@30
os_uid135_exp2TabGen_q <= memoryC0_uid134_exp2TabGen_q & memoryC0_uid133_exp2TabGen_q & memoryC0_uid132_exp2TabGen_q & memoryC0_uid131_exp2TabGen_q & memoryC0_uid130_exp2TabGen_q & memoryC0_uid129_exp2TabGen_q;
--rndBit_uid187_exp2PolyEval(CONSTANT,186)
rndBit_uid187_exp2PolyEval_q <= "001";
--cIncludingRoundingBit_uid188_exp2PolyEval(BITJOIN,187)@30
cIncludingRoundingBit_uid188_exp2PolyEval_q <= os_uid135_exp2TabGen_q & rndBit_uid187_exp2PolyEval_q;
--reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0(REG,335)@30
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q <= cIncludingRoundingBit_uid188_exp2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid189_exp2PolyEval(ADD,188)@31
ts5_uid189_exp2PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q(59)) & reg_cIncludingRoundingBit_uid188_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_0_q);
ts5_uid189_exp2PolyEval_b <= STD_LOGIC_VECTOR((60 downto 55 => reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q(54)) & reg_R_uid258_pT5_uid186_exp2PolyEval_0_to_ts5_uid189_exp2PolyEval_1_q);
ts5_uid189_exp2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid189_exp2PolyEval_a) + SIGNED(ts5_uid189_exp2PolyEval_b));
ts5_uid189_exp2PolyEval_q <= ts5_uid189_exp2PolyEval_o(60 downto 0);
--s5_uid190_exp2PolyEval(BITSELECT,189)@31
s5_uid190_exp2PolyEval_in <= ts5_uid189_exp2PolyEval_q;
s5_uid190_exp2PolyEval_b <= s5_uid190_exp2PolyEval_in(60 downto 1);
--peOR_uid50_fpExp2Test(BITSELECT,49)@31
peOR_uid50_fpExp2Test_in <= s5_uid190_exp2PolyEval_b(57 downto 0);
peOR_uid50_fpExp2Test_b <= peOR_uid50_fpExp2Test_in(57 downto 5);
--fracR_uid52_fpExp2Test(BITSELECT,51)@31
fracR_uid52_fpExp2Test_in <= peOR_uid50_fpExp2Test_b(51 downto 0);
fracR_uid52_fpExp2Test_b <= fracR_uid52_fpExp2Test_in(51 downto 0);
--reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3(REG,338)@31
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q <= fracR_uid52_fpExp2Test_b;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor(LOGICAL,724)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_notEnable_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q <= not (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_a or ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_b);
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena(REG,725)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_nor_q = "1") THEN
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd(LOGICAL,726)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_sticky_ena_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b <= en;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_a and ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_b;
--reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1(REG,337)@7
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q <= excREnc_uid70_fpExp2Test_q;
END IF;
END IF;
END PROCESS;
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg(DELAY,714)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q, xout => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem(DUALMEM,715)
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_inputreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdreg_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_rdmux_q;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 22,
width_b => 2,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq,
address_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_aa,
data_a => ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_ia
);
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_reset0 <= areset;
ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid74_fpExp2Test(MUX,73)@32
fracRPostExc_uid74_fpExp2Test_s <= ld_reg_excREnc_uid70_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_1_q_to_fracRPostExc_uid74_fpExp2Test_b_replace_mem_q;
fracRPostExc_uid74_fpExp2Test: PROCESS (fracRPostExc_uid74_fpExp2Test_s, en, cstAllZWF_uid17_fpExp2Test_q, reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q, cstAllZWF_uid17_fpExp2Test_q, oneFracRPostExc2_uid71_fpExp2Test_q)
BEGIN
CASE fracRPostExc_uid74_fpExp2Test_s IS
WHEN "00" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "01" => fracRPostExc_uid74_fpExp2Test_q <= reg_fracR_uid52_fpExp2Test_0_to_fracRPostExc_uid74_fpExp2Test_3_q;
WHEN "10" => fracRPostExc_uid74_fpExp2Test_q <= cstAllZWF_uid17_fpExp2Test_q;
WHEN "11" => fracRPostExc_uid74_fpExp2Test_q <= oneFracRPostExc2_uid71_fpExp2Test_q;
WHEN OTHERS => fracRPostExc_uid74_fpExp2Test_q <= (others => '0');
END CASE;
END PROCESS;
--RExp2_uid79_fpExp2Test(BITJOIN,78)@32
RExp2_uid79_fpExp2Test_q <= GND_q & ld_expRPostExc_uid78_fpExp2Test_q_to_RExp2_uid79_fpExp2Test_b_replace_mem_q & fracRPostExc_uid74_fpExp2Test_q;
--xOut(GPOUT,4)@32
q <= RExp2_uid79_fpExp2Test_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_mul54us_3xs.vhd | 10 | 2903 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_3XS.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 3XS: Stratix 3, 10 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. For QII8.0 LPM_MULT always creates a 10 ***
--*** 18x18 multiplier 54x54 core ***
--*** 2. Identical to HCC_MUL54US_3XS, but 72 ***
--*** outputs ***
--*** ***
--***************************************************
ENTITY fp_mul54us_3xs IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_3xs;
ARCHITECTURE syn of fp_mul54us_3xs IS
component lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (53 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
end component;
BEGIN
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "MAXIMIZE_SPEED=5",
lpm_pipeline => 4,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 54,
lpm_widthb => 54,
lpm_widthp => 72
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clken => enable,
aclr => reset,
clock => sysclk,
result => mulcc
);
END syn;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/dp_exp.vhd | 10 | 10773 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION EXPONENT(e) - TOP LEVEL ***
--*** ***
--*** DP_EXP.VHD ***
--*** ***
--*** Function: IEEE754 DP EXP() ***
--*** ***
--*** 12/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Stratix II ***
--*** Latency = 20 + 2*DoubleSpeed + ***
--*** Roundconvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 20 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 22 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 21 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 24 ***
--*** ***
--*** Stratix III ***
--*** Latency = 18 + ***
--*** Roundconvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, Roundconvert = 0 : 18 ***
--*** DoubleSpeed = 1, Roundconvert = 0 : 18 ***
--*** DoubleSpeed = 0, Roundconvert = 1 : 19 ***
--*** DoubleSpeed = 1, Roundconvert = 1 : 20 ***
--*** ***
--***************************************************
ENTITY dp_exp IS
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END dp_exp;
ARCHITECTURE rtl OF dp_exp IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
constant coredepth : positive := 19 + 2*doublespeed - device*(4 + 2*doublespeed);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal mantissanode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal rangeerror : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
--*** SII Latency = 19 + 2*doublespeed ***
--*** SIII/IV Latency = 14 ***
component dp_exp_core
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aasgn : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (54 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
rangeerror : OUT STD_LOGIC
);
end component;
component dp_expnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component dp_exprnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component dp_exprndpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--****************
--*** EXP CORE ***
--****************
expcore: dp_exp_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aasgn=>signin,aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,
rangeerror=>rangeerror);
--************************
--*** ROUND AND OUTPUT ***
--************************
gra: IF (roundconvert = 0) GENERATE
norndout: dp_expnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
END GENERATE;
grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
rndout: dp_exprnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
END GENERATE;
grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
rndoutpipe: dp_exprndpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentexp=>exponentnode,
mantissaexp=>mantissanode(53 DOWNTO 1),
nanin=>nanff(coredepth-3),
rangeerror=>rangeerror,
exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,underflowout=>underflowout);
END GENERATE;
signout <= '0';
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/hcc_lsftcomb32.vhd | 10 | 3504 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftcomb32;
ARCHITECTURE rtl OF hcc_lsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_lsftcomb32.vhd | 10 | 3504 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftcomb32;
ARCHITECTURE rtl OF hcc_lsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_ln_double_s5.vhd | 10 | 543973 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln_double_s5
-- VHDL created on Mon Apr 8 15:29:06 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (10 downto 0);
signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0);
signal oMz_uid38_fpLogETest_a : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_b : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_o : std_logic_vector (53 downto 0);
signal oMz_uid38_fpLogETest_q : std_logic_vector (53 downto 0);
signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0);
signal wideZero_uid44_fpLogETest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid45_fpLogETest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q_i : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(117 downto 0);
signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (11 downto 0);
signal expRExt_uid57_fpLogETest_a : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_b : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_o : std_logic_vector (12 downto 0);
signal expRExt_uid57_fpLogETest_q : std_logic_vector (12 downto 0);
signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (51 downto 0);
signal p1_uid92_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid130_natLogPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid142_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid147_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal mO_uid150_countZ_uid54_fpLogETest_q : std_logic_vector (8 downto 0);
signal zs_uid155_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal zs_uid161_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal zs_uid167_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal zs_uid173_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q : std_logic_vector (5 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid238_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm0_uid238_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid241_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm1_uid241_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid98_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid99_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid100_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid101_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid102_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid104_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid105_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid106_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid107_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid108_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid110_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid111_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid112_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid113_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid115_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid116_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid117_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid119_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid120_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0);
signal reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q : std_logic_vector (53 downto 0);
signal reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q : std_logic_vector (49 downto 0);
signal reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (65 downto 0);
signal reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q : std_logic_vector (51 downto 0);
signal reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q : std_logic_vector (10 downto 0);
signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q : std_logic_vector (54 downto 0);
signal ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q : std_logic_vector (116 downto 0);
signal ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q : std_logic_vector (114 downto 0);
signal ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q : std_logic_vector (112 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 : std_logic;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (52 downto 0);
signal FPOne_uid63_fpLogETest_q : std_logic_vector (63 downto 0);
signal pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (66 downto 0);
signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0);
signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogETest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogETest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogETest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0);
signal frac_uid19_fpLogETest_in : std_logic_vector (51 downto 0);
signal frac_uid19_fpLogETest_b : std_logic_vector (51 downto 0);
signal excRZero_uid64_fpLogETest_a : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_b : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0);
signal e_uid29_fpLogETest_a : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_b : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_o : std_logic_vector (11 downto 0);
signal e_uid29_fpLogETest_q : std_logic_vector (11 downto 0);
signal c_uid31_fpLogETest_a : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_b : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0);
signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0);
signal multTermOne_uid42_fpLogETest_q : std_logic_vector (53 downto 0);
signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (118 downto 0);
signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (118 downto 0);
signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (10 downto 0);
signal p0_uid93_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid94_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid94_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid132_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid132_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid138_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid138_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid144_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid144_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_a : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_b : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid41_fpLogETest_q : std_logic_vector (53 downto 0);
signal leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cIncludingRoundingBit_uid131_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid137_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal cIncludingRoundingBit_uid143_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cStage_uid152_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal os_uid103_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid109_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid114_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid121_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid118_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (117 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal RLn_uid88_fpLogETest_q : std_logic_vector (63 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q : std_logic_vector (134 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (41 downto 0);
signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (41 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid134_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT3_uid134_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid61_fpLogETest_in : std_logic_vector (52 downto 0);
signal fracR_uid61_fpLogETest_b : std_logic_vector (51 downto 0);
signal expR_uid62_fpLogETest_in : std_logic_vector (63 downto 0);
signal expR_uid62_fpLogETest_b : std_logic_vector (10 downto 0);
signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (51 downto 0);
signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (9 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0);
signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid91_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid91_constMult_b : std_logic_vector (5 downto 0);
signal addr_uid34_fpLogETest_q : std_logic_vector (10 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_b : std_logic_vector (26 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_in : std_logic_vector (118 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_b : std_logic_vector (63 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_in : std_logic_vector (54 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_b : std_logic_vector (54 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_in : std_logic_vector (86 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_b : std_logic_vector (86 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_in : std_logic_vector (22 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_b : std_logic_vector (22 downto 0);
signal sR_uid95_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid95_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid133_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid133_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid139_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid139_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid145_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid145_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in : std_logic_vector (116 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b : std_logic_vector (116 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in : std_logic_vector (114 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b : std_logic_vector (114 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in : std_logic_vector (112 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b : std_logic_vector (112 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal lowRangeB_uid124_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid124_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid125_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid125_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal FullSumAB117_uid50_fpLogETest_in : std_logic_vector (117 downto 0);
signal FullSumAB117_uid50_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b : std_logic_vector (117 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_in : std_logic_vector (63 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal yT1_uid122_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT1_uid122_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid128_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT2_uid128_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_in : std_logic_vector (14 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_b : std_logic_vector (14 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid37_fpLogETest_in : std_logic_vector (61 downto 0);
signal peOR_uid37_fpLogETest_b : std_logic_vector (54 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid126_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0);
signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0);
signal spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal r_uid188_countZ_uid54_fpLogETest_q : std_logic_vector (6 downto 0);
signal s1_uid124_uid127_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid258_uid261_pT3_uid135_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid273_uid276_pT4_uid141_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (49 downto 0);
signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (49 downto 0);
signal highBBits_uid47_fpLogETest_in : std_logic_vector (108 downto 0);
signal highBBits_uid47_fpLogETest_b : std_logic_vector (58 downto 0);
signal pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid58_fpLogETest_in : std_logic_vector (117 downto 0);
signal fracR_uid58_fpLogETest_b : std_logic_vector (52 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal expFracConc_uid59_fpLogETest_q : std_logic_vector (65 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in : std_logic_vector (110 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b : std_logic_vector (110 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in : std_logic_vector (94 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b : std_logic_vector (94 downto 0);
signal leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
begin
--xIn(GPIN,3)@0
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,902)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor(LOGICAL,914)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a or ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg(REG,912)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena(REG,915)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd(LOGICAL,916)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b;
--frac_uid19_fpLogETest(BITSELECT,18)@0
frac_uid19_fpLogETest_in <= a(51 downto 0);
frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(51 downto 0);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg(DELAY,906)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt(COUNTER,908)
-- every=1, low=0, high=1, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i,1));
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg(REG,909)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux(MUX,910)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem(DUALMEM,907)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 1,
numwords_a => 2,
width_b => 52,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq(51 downto 0);
--zPPolyEval_uid35_fpLogETest(BITSELECT,34)@4
zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q(41 downto 0);
zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(41 downto 0);
--yT2_uid128_natLogPolyEval(BITSELECT,127)@4
yT2_uid128_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT2_uid128_natLogPolyEval_b <= yT2_uid128_natLogPolyEval_in(41 downto 14);
--sSM1W_uid240_pT2_uid129_natLogPolyEval(BITSELECT,239)@4
sSM1W_uid240_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b(0 downto 0);
sSM1W_uid240_pT2_uid129_natLogPolyEval_b <= sSM1W_uid240_pT2_uid129_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1(REG,369)@4
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= sSM1W_uid240_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b(DELAY,672)@5
ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMO_uid10_fpLogETest(CONSTANT,9)
cstBiasMO_uid10_fpLogETest_q <= "01111111110";
--expX_uid6_fpLogETest(BITSELECT,5)@0
expX_uid6_fpLogETest_in <= a(62 downto 0);
expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(62 downto 52);
--c_uid31_fpLogETest(LOGICAL,30)@0
c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b;
c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q;
c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0";
--zAddrLow_uid33_fpLogETest(BITSELECT,32)@0
zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b;
zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(51 downto 42);
--addr_uid34_fpLogETest(BITJOIN,33)@0
addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b;
--reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0(REG,322)@0
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid120_natLogTabGen_lutmem(DUALMEM,316)@1
memoryC4_uid120_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid120_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid120_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid120_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid120_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid120_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid120_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid120_natLogTabGen_lutmem_ia
);
memoryC4_uid120_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid120_natLogTabGen_lutmem_q <= memoryC4_uid120_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1(REG,355)@3
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= memoryC4_uid120_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid119_natLogTabGen_lutmem(DUALMEM,315)@1
memoryC4_uid119_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid119_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid119_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid119_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid119_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid119_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid119_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid119_natLogTabGen_lutmem_ia
);
memoryC4_uid119_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid119_natLogTabGen_lutmem_q <= memoryC4_uid119_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0(REG,354)@3
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= memoryC4_uid119_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid121_natLogTabGen(BITJOIN,120)@4
os_uid121_natLogTabGen_q <= reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q & reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q;
--reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1(REG,357)@4
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= os_uid121_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid122_natLogPolyEval(BITSELECT,121)@4
yT1_uid122_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT1_uid122_natLogPolyEval_b <= yT1_uid122_natLogPolyEval_in(41 downto 25);
--reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0(REG,356)@4
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= yT1_uid122_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid230_pT1_uid123_natLogPolyEval(MULT,229)@5
prodXY_uid230_pT1_uid123_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_a),18)) * SIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_b);
prodXY_uid230_pT1_uid123_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid230_pT1_uid123_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid230_pT1_uid123_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= prodXY_uid230_pT1_uid123_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval(BITSELECT,230)@8
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in <= prodXY_uid230_pT1_uid123_natLogPolyEval_q;
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in(33 downto 15);
--highBBits_uid125_natLogPolyEval(BITSELECT,124)@8
highBBits_uid125_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b;
highBBits_uid125_natLogPolyEval_b <= highBBits_uid125_natLogPolyEval_in(18 downto 1);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor(LOGICAL,1029)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q <= not (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a or ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena(REG,1030)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd(LOGICAL,1031)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a and ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid117_natLogTabGen_lutmem(DUALMEM,314)@1
memoryC3_uid117_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid117_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid117_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid117_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid117_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid117_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid117_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid117_natLogTabGen_lutmem_ia
);
memoryC3_uid117_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid117_natLogTabGen_lutmem_q <= memoryC3_uid117_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2(REG,363)@3
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= memoryC3_uid117_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid116_natLogTabGen_lutmem(DUALMEM,313)@1
memoryC3_uid116_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid116_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid116_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid116_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid116_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid116_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid116_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid116_natLogTabGen_lutmem_ia
);
memoryC3_uid116_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid116_natLogTabGen_lutmem_q <= memoryC3_uid116_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1(REG,362)@3
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= memoryC3_uid116_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid115_natLogTabGen_lutmem(DUALMEM,312)@1
memoryC3_uid115_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid115_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid115_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid115_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid115_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid115_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid115_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid115_natLogTabGen_lutmem_ia
);
memoryC3_uid115_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid115_natLogTabGen_lutmem_q <= memoryC3_uid115_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0(REG,361)@3
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= memoryC3_uid115_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid118_natLogTabGen(BITJOIN,117)@4
os_uid118_natLogTabGen_q <= reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q & reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q & reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg(DELAY,1021)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid118_natLogTabGen_q, xout => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem(DUALMEM,1022)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid126_natLogPolyEval(ADD,125)@8
sumAHighB_uid126_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid126_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid125_natLogPolyEval_b(17)) & highBBits_uid125_natLogPolyEval_b);
sumAHighB_uid126_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid126_natLogPolyEval_a) + SIGNED(sumAHighB_uid126_natLogPolyEval_b));
sumAHighB_uid126_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid124_natLogPolyEval(BITSELECT,123)@8
lowRangeB_uid124_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b(0 downto 0);
lowRangeB_uid124_natLogPolyEval_b <= lowRangeB_uid124_natLogPolyEval_in(0 downto 0);
--s1_uid124_uid127_natLogPolyEval(BITJOIN,126)@8
s1_uid124_uid127_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_q & lowRangeB_uid124_natLogPolyEval_b;
--sSM1H_uid239_pT2_uid129_natLogPolyEval(BITSELECT,238)@8
sSM1H_uid239_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
sSM1H_uid239_pT2_uid129_natLogPolyEval_b <= sSM1H_uid239_pT2_uid129_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0(REG,368)@8
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= sSM1H_uid239_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid241_pT2_uid129_natLogPolyEval(MULT,240)@9
sm1_uid241_pT2_uid129_natLogPolyEval_pr <= SIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_b),2));
sm1_uid241_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q;
sm1_uid241_pT2_uid129_natLogPolyEval_b <= ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q;
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid241_pT2_uid129_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid241_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--GND(CONSTANT,0)
GND_q <= "0";
--pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval(BITJOIN,242)@12
pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid237_pT2_uid129_natLogPolyEval(BITSELECT,236)@4
sSM0W_uid237_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
sSM0W_uid237_pT2_uid129_natLogPolyEval_b <= sSM0W_uid237_pT2_uid129_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a(DELAY,822)@4
ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid237_pT2_uid129_natLogPolyEval_b, xout => ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1(REG,367)@8
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid236_pT2_uid129_natLogPolyEval(BITSELECT,235)@8
sSM0H_uid236_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q(2 downto 0);
sSM0H_uid236_pT2_uid129_natLogPolyEval_b <= sSM0H_uid236_pT2_uid129_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0(REG,366)@8
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= sSM0H_uid236_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid238_pT2_uid129_natLogPolyEval(MULT,237)@9
sm0_uid238_pT2_uid129_natLogPolyEval_pr <= UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_a) * UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_b);
sm0_uid238_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q;
sm0_uid238_pT2_uid129_natLogPolyEval_b <= reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q;
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid238_pT2_uid129_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid238_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval(BITJOIN,241)@12
pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid234_pT2_uid129_natLogPolyEval(BITSELECT,233)@8
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1(REG,365)@8
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor(LOGICAL,1151)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena(REG,1152)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd(LOGICAL,1153)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid233_pT2_uid129_natLogPolyEval(BITSELECT,232)@4
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b <= xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg(DELAY,1143)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b, xout => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem(DUALMEM,1144)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0(REG,364)@8
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid235_pT2_uid129_natLogPolyEval(MULT,234)@9
topProd_uid235_pT2_uid129_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_a),28)) * SIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_b);
topProd_uid235_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_b <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q;
topProd_uid235_pT2_uid129_natLogPolyEval_b <= reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q;
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid235_pT2_uid129_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid235_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= topProd_uid235_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid242_pT2_uid129_natLogPolyEval(ADDSUB3,243)@12
add0_uid242_pT2_uid129_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid235_pT2_uid129_natLogPolyEval_q(53)) & topProd_uid235_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q(26)) & pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_a) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_b) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_c));
add0_uid242_pT2_uid129_natLogPolyEval_q <= add0_uid242_pT2_uid129_natLogPolyEval_o(54 downto 0);
--R_uid245_pT2_uid129_natLogPolyEval(BITSELECT,244)@12
R_uid245_pT2_uid129_natLogPolyEval_in <= add0_uid242_pT2_uid129_natLogPolyEval_q(53 downto 0);
R_uid245_pT2_uid129_natLogPolyEval_b <= R_uid245_pT2_uid129_natLogPolyEval_in(53 downto 24);
--reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1(REG,371)@12
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= R_uid245_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor(LOGICAL,1042)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q <= not (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a or ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b);
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top(CONSTANT,1038)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp(LOGICAL,1039)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a = ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg(REG,1040)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena(REG,1043)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd(LOGICAL,1044)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a and ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid113_natLogTabGen_lutmem(DUALMEM,311)@1
memoryC2_uid113_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid113_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid113_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid113_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid113_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid113_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid113_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid113_natLogTabGen_lutmem_ia
);
memoryC2_uid113_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid113_natLogTabGen_lutmem_q <= memoryC2_uid113_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3(REG,351)@3
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= memoryC2_uid113_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid112_natLogTabGen_lutmem(DUALMEM,310)@1
memoryC2_uid112_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid112_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid112_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid112_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid112_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid112_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid112_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid112_natLogTabGen_lutmem_ia
);
memoryC2_uid112_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid112_natLogTabGen_lutmem_q <= memoryC2_uid112_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2(REG,350)@3
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= memoryC2_uid112_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid111_natLogTabGen_lutmem(DUALMEM,309)@1
memoryC2_uid111_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid111_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid111_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid111_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid111_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid111_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid111_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid111_natLogTabGen_lutmem_ia
);
memoryC2_uid111_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid111_natLogTabGen_lutmem_q <= memoryC2_uid111_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1(REG,349)@3
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= memoryC2_uid111_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid110_natLogTabGen_lutmem(DUALMEM,308)@1
memoryC2_uid110_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid110_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid110_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid110_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid110_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid110_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid110_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid110_natLogTabGen_lutmem_ia
);
memoryC2_uid110_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid110_natLogTabGen_lutmem_q <= memoryC2_uid110_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0(REG,348)@3
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= memoryC2_uid110_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid114_natLogTabGen(BITJOIN,113)@4
os_uid114_natLogTabGen_q <= reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q & reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q & reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q & reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg(DELAY,1032)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid114_natLogTabGen_q, xout => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt(COUNTER,1034)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg(REG,1035)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux(MUX,1036)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem(DUALMEM,1033)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--rndBit_uid130_natLogPolyEval(CONSTANT,129)
rndBit_uid130_natLogPolyEval_q <= "01";
--cIncludingRoundingBit_uid131_natLogPolyEval(BITJOIN,130)@12
cIncludingRoundingBit_uid131_natLogPolyEval_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0(REG,370)@12
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= cIncludingRoundingBit_uid131_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid132_natLogPolyEval(ADD,131)@13
ts2_uid132_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q);
ts2_uid132_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q(29)) & reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q);
ts2_uid132_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid132_natLogPolyEval_a) + SIGNED(ts2_uid132_natLogPolyEval_b));
ts2_uid132_natLogPolyEval_q <= ts2_uid132_natLogPolyEval_o(40 downto 0);
--s2_uid133_natLogPolyEval(BITSELECT,132)@13
s2_uid133_natLogPolyEval_in <= ts2_uid132_natLogPolyEval_q;
s2_uid133_natLogPolyEval_b <= s2_uid133_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid252_pT3_uid135_natLogPolyEval(BITSELECT,251)@13
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9(REG,375)@13
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor(LOGICAL,1055)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top(CONSTANT,1051)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q <= "0110";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp(LOGICAL,1052)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg(REG,1053)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena(REG,1056)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd(LOGICAL,1057)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg(DELAY,1045)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=6, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i = 5 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i,3));
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg(REG,1048)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux(MUX,1049)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem(DUALMEM,1046)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 3,
numwords_a => 7,
width_b => 42,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--yT3_uid134_natLogPolyEval(BITSELECT,133)@13
yT3_uid134_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q;
yT3_uid134_natLogPolyEval_b <= yT3_uid134_natLogPolyEval_in(41 downto 4);
--xBottomBits_uid251_pT3_uid135_natLogPolyEval(BITSELECT,250)@13
xBottomBits_uid251_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b(10 downto 0);
xBottomBits_uid251_pT3_uid135_natLogPolyEval_b <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval(BITJOIN,253)@13
pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7(REG,374)@13
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid250_pT3_uid135_natLogPolyEval(BITSELECT,249)@13
yBottomBits_uid250_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b(12 downto 0);
yBottomBits_uid250_pT3_uid135_natLogPolyEval_b <= yBottomBits_uid250_pT3_uid135_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval(BITJOIN,252)@13
spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q <= GND_q & yBottomBits_uid250_pT3_uid135_natLogPolyEval_b;
--pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval(BITJOIN,254)@13
pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q <= spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6(REG,373)@13
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid249_pT3_uid135_natLogPolyEval(BITSELECT,248)@13
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4(REG,372)@13
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma(CHAINMULTADD,317)@14
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval(BITSELECT,256)@17
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in(36 downto 4);
--highBBits_uid259_pT3_uid135_natLogPolyEval(BITSELECT,258)@17
highBBits_uid259_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b;
highBBits_uid259_pT3_uid135_natLogPolyEval_b <= highBBits_uid259_pT3_uid135_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid247_pT3_uid135_natLogPolyEval(BITSELECT,246)@13
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1(REG,377)@13
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid246_pT3_uid135_natLogPolyEval(BITSELECT,245)@13
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0(REG,376)@13
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid248_pT3_uid135_natLogPolyEval(MULT,247)@14
topProd_uid248_pT3_uid135_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_a),28)) * SIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_b);
topProd_uid248_pT3_uid135_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_b <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q;
topProd_uid248_pT3_uid135_natLogPolyEval_b <= reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q;
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid248_pT3_uid135_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid248_pT3_uid135_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= topProd_uid248_pT3_uid135_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid260_pT3_uid135_natLogPolyEval(ADD,259)@17
sumAHighB_uid260_pT3_uid135_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid248_pT3_uid135_natLogPolyEval_q(53)) & topProd_uid248_pT3_uid135_natLogPolyEval_q);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid259_pT3_uid135_natLogPolyEval_b(28)) & highBBits_uid259_pT3_uid135_natLogPolyEval_b);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_a) + SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_b));
sumAHighB_uid260_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid258_pT3_uid135_natLogPolyEval(BITSELECT,257)@17
lowRangeB_uid258_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b(3 downto 0);
lowRangeB_uid258_pT3_uid135_natLogPolyEval_b <= lowRangeB_uid258_pT3_uid135_natLogPolyEval_in(3 downto 0);
--add0_uid258_uid261_pT3_uid135_natLogPolyEval(BITJOIN,260)@17
add0_uid258_uid261_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_q & lowRangeB_uid258_pT3_uid135_natLogPolyEval_b;
--R_uid262_pT3_uid135_natLogPolyEval(BITSELECT,261)@17
R_uid262_pT3_uid135_natLogPolyEval_in <= add0_uid258_uid261_pT3_uid135_natLogPolyEval_q(57 downto 0);
R_uid262_pT3_uid135_natLogPolyEval_b <= R_uid262_pT3_uid135_natLogPolyEval_in(57 downto 17);
--reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1(REG,379)@17
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= R_uid262_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor(LOGICAL,1068)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q <= not (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a or ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b);
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top(CONSTANT,1064)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp(LOGICAL,1065)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a = ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg(REG,1066)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena(REG,1069)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd(LOGICAL,1070)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a and ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid108_natLogTabGen_lutmem(DUALMEM,307)@1
memoryC1_uid108_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid108_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid108_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid108_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid108_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid108_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid108_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid108_natLogTabGen_lutmem_ia
);
memoryC1_uid108_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid108_natLogTabGen_lutmem_q <= memoryC1_uid108_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4(REG,343)@3
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= memoryC1_uid108_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid107_natLogTabGen_lutmem(DUALMEM,306)@1
memoryC1_uid107_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid107_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid107_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid107_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid107_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid107_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid107_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid107_natLogTabGen_lutmem_ia
);
memoryC1_uid107_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid107_natLogTabGen_lutmem_q <= memoryC1_uid107_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3(REG,342)@3
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= memoryC1_uid107_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid106_natLogTabGen_lutmem(DUALMEM,305)@1
memoryC1_uid106_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid106_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid106_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid106_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid106_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid106_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid106_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid106_natLogTabGen_lutmem_ia
);
memoryC1_uid106_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid106_natLogTabGen_lutmem_q <= memoryC1_uid106_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2(REG,341)@3
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= memoryC1_uid106_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid105_natLogTabGen_lutmem(DUALMEM,304)@1
memoryC1_uid105_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid105_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid105_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid105_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid105_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid105_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid105_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid105_natLogTabGen_lutmem_ia
);
memoryC1_uid105_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid105_natLogTabGen_lutmem_q <= memoryC1_uid105_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1(REG,340)@3
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= memoryC1_uid105_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid104_natLogTabGen_lutmem(DUALMEM,303)@1
memoryC1_uid104_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid104_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid104_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid104_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid104_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid104_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid104_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid104_natLogTabGen_lutmem_ia
);
memoryC1_uid104_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid104_natLogTabGen_lutmem_q <= memoryC1_uid104_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0(REG,339)@3
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= memoryC1_uid104_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid109_natLogTabGen(BITJOIN,108)@4
os_uid109_natLogTabGen_q <= reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q & reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q & reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q & reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q & reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg(DELAY,1058)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid109_natLogTabGen_q, xout => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt(COUNTER,1060)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg(REG,1061)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux(MUX,1062)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem(DUALMEM,1059)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid137_natLogPolyEval(BITJOIN,136)@17
cIncludingRoundingBit_uid137_natLogPolyEval_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0(REG,378)@17
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= cIncludingRoundingBit_uid137_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid138_natLogPolyEval(ADD,137)@18
ts3_uid138_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q);
ts3_uid138_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q(40)) & reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q);
ts3_uid138_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid138_natLogPolyEval_a) + SIGNED(ts3_uid138_natLogPolyEval_b));
ts3_uid138_natLogPolyEval_q <= ts3_uid138_natLogPolyEval_o(50 downto 0);
--s3_uid139_natLogPolyEval(BITSELECT,138)@18
s3_uid139_natLogPolyEval_in <= ts3_uid138_natLogPolyEval_q;
s3_uid139_natLogPolyEval_b <= s3_uid139_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid264_pT4_uid141_natLogPolyEval(BITSELECT,263)@18
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b;
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9(REG,383)@18
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor(LOGICAL,1140)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a or ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top(CONSTANT,1136)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp(LOGICAL,1137)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg(REG,1138)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena(REG,1141)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd(LOGICAL,1142)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid267_pT4_uid141_natLogPolyEval(BITSELECT,266)@4
xBottomBits_uid267_pT4_uid141_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b(14 downto 0);
xBottomBits_uid267_pT4_uid141_natLogPolyEval_b <= xBottomBits_uid267_pT4_uid141_natLogPolyEval_in(14 downto 0);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg(DELAY,1130)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => xBottomBits_uid267_pT4_uid141_natLogPolyEval_b, xout => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt(COUNTER,1132)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg(REG,1133)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux(MUX,1134)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem(DUALMEM,1131)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 4,
numwords_a => 12,
width_b => 15,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq(14 downto 0);
--pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval(BITJOIN,268)@18
pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((10 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7(REG,382)@18
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid266_pT4_uid141_natLogPolyEval(BITSELECT,265)@18
yBottomBits_uid266_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b(22 downto 0);
yBottomBits_uid266_pT4_uid141_natLogPolyEval_b <= yBottomBits_uid266_pT4_uid141_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a(DELAY,704)@18
ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid266_pT4_uid141_natLogPolyEval_b, xout => ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval(BITJOIN,267)@19
spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q;
--pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval(BITJOIN,269)@19
pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q <= spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6(REG,381)@19
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor(LOGICAL,1127)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top(CONSTANT,1123)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp(LOGICAL,1124)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg(REG,1125)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena(REG,1128)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd(LOGICAL,1129)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt(COUNTER,1119)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg(REG,1120)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux(MUX,1121)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem(DUALMEM,1118)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 4,
numwords_a => 13,
width_b => 42,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--xTop27Bits_uid263_pT4_uid141_natLogPolyEval(BITSELECT,262)@19
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in(41 downto 15);
--reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4(REG,380)@19
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma(CHAINMULTADD,318)@20
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval(BITSELECT,271)@23
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in(54 downto 3);
--highBBits_uid274_pT4_uid141_natLogPolyEval(BITSELECT,273)@23
highBBits_uid274_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b;
highBBits_uid274_pT4_uid141_natLogPolyEval_b <= highBBits_uid274_pT4_uid141_natLogPolyEval_in(51 downto 23);
--ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b(DELAY,701)@19
ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid265_pT4_uid141_natLogPolyEval(MULT,264)@20
topProd_uid265_pT4_uid141_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_a),28)) * SIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_b);
topProd_uid265_pT4_uid141_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_b <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q;
topProd_uid265_pT4_uid141_natLogPolyEval_b <= ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q;
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid265_pT4_uid141_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid265_pT4_uid141_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= topProd_uid265_pT4_uid141_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid275_pT4_uid141_natLogPolyEval(ADD,274)@23
sumAHighB_uid275_pT4_uid141_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid265_pT4_uid141_natLogPolyEval_q(53)) & topProd_uid265_pT4_uid141_natLogPolyEval_q);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid274_pT4_uid141_natLogPolyEval_b(28)) & highBBits_uid274_pT4_uid141_natLogPolyEval_b);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_a) + SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_b));
sumAHighB_uid275_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid273_pT4_uid141_natLogPolyEval(BITSELECT,272)@23
lowRangeB_uid273_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b(22 downto 0);
lowRangeB_uid273_pT4_uid141_natLogPolyEval_b <= lowRangeB_uid273_pT4_uid141_natLogPolyEval_in(22 downto 0);
--add0_uid273_uid276_pT4_uid141_natLogPolyEval(BITJOIN,275)@23
add0_uid273_uid276_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_q & lowRangeB_uid273_pT4_uid141_natLogPolyEval_b;
--R_uid277_pT4_uid141_natLogPolyEval(BITSELECT,276)@23
R_uid277_pT4_uid141_natLogPolyEval_in <= add0_uid273_uid276_pT4_uid141_natLogPolyEval_q(76 downto 0);
R_uid277_pT4_uid141_natLogPolyEval_b <= R_uid277_pT4_uid141_natLogPolyEval_in(76 downto 25);
--reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1(REG,387)@23
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= R_uid277_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor(LOGICAL,1081)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q <= not (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a or ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b);
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top(CONSTANT,1077)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp(LOGICAL,1078)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a = ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg(REG,1079)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena(REG,1082)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd(LOGICAL,1083)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a and ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid102_natLogTabGen_lutmem(DUALMEM,302)@1
memoryC0_uid102_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid102_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid102_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid102_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid102_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid102_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid102_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid102_natLogTabGen_lutmem_ia
);
memoryC0_uid102_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid102_natLogTabGen_lutmem_q <= memoryC0_uid102_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5(REG,333)@3
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= memoryC0_uid102_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid101_natLogTabGen_lutmem(DUALMEM,301)@1
memoryC0_uid101_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid101_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid101_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid101_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid101_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid101_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid101_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid101_natLogTabGen_lutmem_ia
);
memoryC0_uid101_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid101_natLogTabGen_lutmem_q <= memoryC0_uid101_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4(REG,332)@3
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= memoryC0_uid101_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid100_natLogTabGen_lutmem(DUALMEM,300)@1
memoryC0_uid100_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid100_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid100_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid100_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid100_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid100_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid100_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid100_natLogTabGen_lutmem_ia
);
memoryC0_uid100_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid100_natLogTabGen_lutmem_q <= memoryC0_uid100_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3(REG,331)@3
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= memoryC0_uid100_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid99_natLogTabGen_lutmem(DUALMEM,299)@1
memoryC0_uid99_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid99_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid99_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid99_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid99_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid99_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid99_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid99_natLogTabGen_lutmem_ia
);
memoryC0_uid99_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid99_natLogTabGen_lutmem_q <= memoryC0_uid99_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2(REG,330)@3
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= memoryC0_uid99_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid98_natLogTabGen_lutmem(DUALMEM,298)@1
memoryC0_uid98_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid98_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid98_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid98_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid98_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid98_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid98_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid98_natLogTabGen_lutmem_ia
);
memoryC0_uid98_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid98_natLogTabGen_lutmem_q <= memoryC0_uid98_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1(REG,329)@3
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= memoryC0_uid98_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,297)@1
memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid97_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid97_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid97_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid97_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid97_natLogTabGen_lutmem_ia
);
memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0(REG,328)@3
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= memoryC0_uid97_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid103_natLogTabGen(BITJOIN,102)@4
os_uid103_natLogTabGen_q <= reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q & reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q & reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q & reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q & reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q & reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg(DELAY,1071)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid103_natLogTabGen_q, xout => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt(COUNTER,1073)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg(REG,1074)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux(MUX,1075)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem(DUALMEM,1072)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid142_natLogPolyEval(CONSTANT,141)
rndBit_uid142_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid143_natLogPolyEval(BITJOIN,142)@23
cIncludingRoundingBit_uid143_natLogPolyEval_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q & rndBit_uid142_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0(REG,386)@23
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= cIncludingRoundingBit_uid143_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid144_natLogPolyEval(ADD,143)@24
ts4_uid144_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q);
ts4_uid144_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q(51)) & reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q);
ts4_uid144_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid144_natLogPolyEval_a) + SIGNED(ts4_uid144_natLogPolyEval_b));
ts4_uid144_natLogPolyEval_q <= ts4_uid144_natLogPolyEval_o(63 downto 0);
--s4_uid145_natLogPolyEval(BITSELECT,144)@24
s4_uid145_natLogPolyEval_in <= ts4_uid144_natLogPolyEval_q;
s4_uid145_natLogPolyEval_b <= s4_uid145_natLogPolyEval_in(63 downto 1);
--peOR_uid37_fpLogETest(BITSELECT,36)@24
peOR_uid37_fpLogETest_in <= s4_uid145_natLogPolyEval_b(61 downto 0);
peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(61 downto 7);
--postPEMul_uid43_fpLogETest_b_2(BITSELECT,281)@24
postPEMul_uid43_fpLogETest_b_2_in <= STD_LOGIC_VECTOR((80 downto 55 => peOR_uid37_fpLogETest_b(54)) & peOR_uid37_fpLogETest_b);
postPEMul_uid43_fpLogETest_b_2_b <= postPEMul_uid43_fpLogETest_b_2_in(80 downto 54);
--reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1(REG,398)@24
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= postPEMul_uid43_fpLogETest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor(LOGICAL,927)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a or ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b);
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top(CONSTANT,923)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q <= "010100";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp(LOGICAL,924)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q <= "1" when ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a = ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b else "0";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg(REG,925)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena(REG,928)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd(LOGICAL,929)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt(COUNTER,919)
-- every=1, low=0, high=20, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i = 19 THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i - 20;
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i,5));
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg(REG,920)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux(MUX,921)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem(DUALMEM,918)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 21,
width_b => 52,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq(51 downto 0);
--pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@23
pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((51 downto 1 => GND_q(0)) & GND_q);
--oMz_uid38_fpLogETest(SUB,38)@23
oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q);
oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q);
oMz_uid38_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oMz_uid38_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b));
END IF;
END IF;
END PROCESS;
oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(53 downto 0);
--z2_uid40_fpLogETest(CONSTANT,39)
z2_uid40_fpLogETest_q <= "00";
--sEz_uid41_fpLogETest(BITJOIN,40)@23
sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q;
--reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2(REG,321)@23
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= sEz_uid41_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor(LOGICAL,940)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena(REG,941)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd(LOGICAL,942)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b;
--reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1(REG,320)@0
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= c_uid31_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg(DELAY,930)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q, xout => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem(DUALMEM,931)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq(0 downto 0);
--multTermOne_uid42_fpLogETest(MUX,41)@24
multTermOne_uid42_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q;
multTermOne_uid42_fpLogETest: PROCESS (multTermOne_uid42_fpLogETest_s, en, reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q, oMz_uid38_fpLogETest_q)
BEGIN
CASE multTermOne_uid42_fpLogETest_s IS
WHEN "0" => multTermOne_uid42_fpLogETest_q <= reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q;
WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q;
WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid43_fpLogETest_a_1(BITSELECT,278)@24
postPEMul_uid43_fpLogETest_a_1_in <= multTermOne_uid42_fpLogETest_q;
postPEMul_uid43_fpLogETest_a_1_b <= postPEMul_uid43_fpLogETest_a_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0(REG,390)@24
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= postPEMul_uid43_fpLogETest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b2(MULT,287)@25
postPEMul_uid43_fpLogETest_a1_b2_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b2_a) * SIGNED(postPEMul_uid43_fpLogETest_a1_b2_b);
postPEMul_uid43_fpLogETest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= postPEMul_uid43_fpLogETest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a(DELAY,739)@28
ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_a1_b2_q, xout => ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_3(BITSHIFT,293)@30
postPEMul_uid43_fpLogETest_align_3_q_int <= ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_3_q <= postPEMul_uid43_fpLogETest_align_3_q_int(134 downto 0);
--postPEMul_uid43_fpLogETest_a_0(BITSELECT,277)@24
postPEMul_uid43_fpLogETest_a_0_in <= multTermOne_uid42_fpLogETest_q(26 downto 0);
postPEMul_uid43_fpLogETest_a_0_b <= postPEMul_uid43_fpLogETest_a_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0(REG,388)@24
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= postPEMul_uid43_fpLogETest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a0_b2(MULT,286)@25
postPEMul_uid43_fpLogETest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a0_b2_a),28)) * SIGNED(postPEMul_uid43_fpLogETest_a0_b2_b);
postPEMul_uid43_fpLogETest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= postPEMul_uid43_fpLogETest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_1(BITSELECT,280)@24
postPEMul_uid43_fpLogETest_b_1_in <= peOR_uid37_fpLogETest_b(53 downto 0);
postPEMul_uid43_fpLogETest_b_1_b <= postPEMul_uid43_fpLogETest_b_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1(REG,393)@24
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= postPEMul_uid43_fpLogETest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b1(MULT,285)@25
postPEMul_uid43_fpLogETest_a1_b1_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b1_b),28));
postPEMul_uid43_fpLogETest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= postPEMul_uid43_fpLogETest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_2_add_0_0(ADD,289)@28
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a1_b1_q(53)) & postPEMul_uid43_fpLogETest_a1_b1_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a0_b2_q(53)) & postPEMul_uid43_fpLogETest_a0_b2_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a(DELAY,738)@28
ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_2(BITSHIFT,292)@29
postPEMul_uid43_fpLogETest_align_2_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_2_q <= postPEMul_uid43_fpLogETest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0(REG,401)@29
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= postPEMul_uid43_fpLogETest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_1(ADD,295)@30
postPEMul_uid43_fpLogETest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q(108)) & reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q);
postPEMul_uid43_fpLogETest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid43_fpLogETest_align_3_q(134)) & postPEMul_uid43_fpLogETest_align_3_q);
postPEMul_uid43_fpLogETest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_b));
postPEMul_uid43_fpLogETest_result_add_0_1_q <= postPEMul_uid43_fpLogETest_result_add_0_1_o(135 downto 0);
--postPEMul_uid43_fpLogETest_a0_b1(MULT,284)@25
postPEMul_uid43_fpLogETest_a0_b1_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_b);
postPEMul_uid43_fpLogETest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= postPEMul_uid43_fpLogETest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_0(BITSELECT,279)@24
postPEMul_uid43_fpLogETest_b_0_in <= peOR_uid37_fpLogETest_b(26 downto 0);
postPEMul_uid43_fpLogETest_b_0_b <= postPEMul_uid43_fpLogETest_b_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1(REG,389)@24
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= postPEMul_uid43_fpLogETest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b0(MULT,283)@25
postPEMul_uid43_fpLogETest_a1_b0_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b0_b),28));
postPEMul_uid43_fpLogETest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= postPEMul_uid43_fpLogETest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_1_add_0_0(ADD,288)@28
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid43_fpLogETest_a1_b0_q(53)) & postPEMul_uid43_fpLogETest_a1_b0_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid43_fpLogETest_a0_b1_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a(DELAY,737)@28
ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_1(BITSHIFT,291)@29
postPEMul_uid43_fpLogETest_align_1_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_1_q <= postPEMul_uid43_fpLogETest_align_1_q_int(82 downto 0);
--postPEMul_uid43_fpLogETest_a0_b0(MULT,282)@25
postPEMul_uid43_fpLogETest_a0_b0_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_b);
postPEMul_uid43_fpLogETest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= postPEMul_uid43_fpLogETest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_align_0(BITSHIFT,290)@28
postPEMul_uid43_fpLogETest_align_0_q_int <= postPEMul_uid43_fpLogETest_a0_b0_q;
postPEMul_uid43_fpLogETest_align_0_q <= postPEMul_uid43_fpLogETest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0(REG,394)@28
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= postPEMul_uid43_fpLogETest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_0(ADD,294)@29
postPEMul_uid43_fpLogETest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q);
postPEMul_uid43_fpLogETest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid43_fpLogETest_align_1_q(82)) & postPEMul_uid43_fpLogETest_align_1_q);
postPEMul_uid43_fpLogETest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_result_add_0_0_q <= postPEMul_uid43_fpLogETest_result_add_0_0_o(83 downto 0);
--postPEMul_uid43_fpLogETest_result_add_1_0(ADD,296)@30
postPEMul_uid43_fpLogETest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid43_fpLogETest_result_add_0_0_q(83)) & postPEMul_uid43_fpLogETest_result_add_0_0_q);
postPEMul_uid43_fpLogETest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid43_fpLogETest_result_add_0_1_q(135)) & postPEMul_uid43_fpLogETest_result_add_0_1_q);
postPEMul_uid43_fpLogETest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_b));
postPEMul_uid43_fpLogETest_result_add_1_0_q <= postPEMul_uid43_fpLogETest_result_add_1_0_o(136 downto 0);
--highBBits_uid47_fpLogETest(BITSELECT,46)@30
highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(108 downto 0);
highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(108 downto 50);
--reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1(REG,406)@30
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= highBBits_uid47_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid44_fpLogETest(CONSTANT,43)
wideZero_uid44_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--cstBias_uid9_fpLogETest(CONSTANT,8)
cstBias_uid9_fpLogETest_q <= "01111111111";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,903)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b);
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,899)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "011000";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,900)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,901)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,904)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,905)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg(DELAY,893)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogETest_b, xout => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,895)
-- every=1, low=0, high=24, step=1, init=1
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 23 THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 24;
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,5));
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,896)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,897)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,894)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 25,
width_b => 11,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia
);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(10 downto 0);
--e_uid29_fpLogETest(SUB,28)@27
e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q);
e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q);
e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b));
e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(11 downto 0);
--xv0_uid90_constMult(BITSELECT,89)@27
xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0);
xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0);
--ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a(DELAY,858)@27
ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv0_uid90_constMult_b, xout => ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0(REG,403)@28
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p0_uid93_constMult(LOOKUP,92)@29
p0_uid93_constMult: PROCESS (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q) IS
WHEN "000000" => p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid93_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid93_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid93_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid93_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid93_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid93_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid93_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid93_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid93_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid93_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid93_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid93_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid93_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid93_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid93_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid93_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid93_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid93_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid93_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid93_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid93_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid93_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid93_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid93_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid93_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid93_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid93_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid93_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid93_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid93_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid93_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid93_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid93_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid93_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid93_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid93_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid93_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid93_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid93_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid93_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid93_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid93_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid93_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid93_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid93_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid93_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid93_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid93_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid93_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid93_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid93_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid93_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid93_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid93_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid93_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid93_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid93_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid93_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid93_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid93_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid93_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid93_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid93_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid91_constMult(BITSELECT,90)@27
xv1_uid91_constMult_in <= e_uid29_fpLogETest_q;
xv1_uid91_constMult_b <= xv1_uid91_constMult_in(11 downto 6);
--reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0(REG,402)@27
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= xv1_uid91_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid92_constMult(LOOKUP,91)@28
p1_uid92_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q) IS
WHEN "000000" => p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid92_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid92_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid92_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid92_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid92_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid92_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid92_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid92_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid92_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid92_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid92_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid92_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid92_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid92_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid92_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid92_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid92_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid92_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid92_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid92_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid92_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid92_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid92_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid92_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid92_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid92_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid92_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid92_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid92_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid92_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid92_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid92_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid92_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid92_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid92_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid92_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid92_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid92_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid92_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid92_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid92_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid92_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid92_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid92_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid92_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid92_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid92_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid92_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid92_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid92_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid92_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid92_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid92_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid92_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid92_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid92_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid92_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid92_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid92_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid92_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid92_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid92_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid92_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid94_constMult(ADD,93)@29
lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid92_constMult_q(68)) & p1_uid92_constMult_q);
lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid93_constMult_q);
lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b));
lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(69 downto 0);
--sR_uid95_constMult(BITSELECT,94)@29
sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(68 downto 0);
sR_uid95_constMult_b <= sR_uid95_constMult_in(68 downto 2);
--reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2(REG,405)@29
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= sR_uid95_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor(LOGICAL,953)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top(CONSTANT,949)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q <= "011010";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp(LOGICAL,950)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q <= "1" when ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a = ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b else "0";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg(REG,951)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena(REG,954)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd(LOGICAL,955)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt(COUNTER,945)
-- every=1, low=0, high=26, step=1, init=1
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i = 25 THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i - 26;
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i,5));
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg(REG,946)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux(MUX,947)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux: PROCESS (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem(DUALMEM,944)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 27,
width_b => 1,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq(0 downto 0);
--addTermOne_uid45_fpLogETest(MUX,44)@30
addTermOne_uid45_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q;
addTermOne_uid45_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid45_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid45_fpLogETest_s IS
WHEN "0" => addTermOne_uid45_fpLogETest_q <= reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q;
WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q;
WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid48_fpLogETest(ADD,47)@31
sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid45_fpLogETest_q(66)) & addTermOne_uid45_fpLogETest_q);
sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q(58)) & reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q);
sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b));
sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(67 downto 0);
--lowRangeB_uid46_fpLogETest(BITSELECT,45)@30
lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(49 downto 0);
lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(49 downto 0);
--reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0(REG,407)@30
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= lowRangeB_uid46_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@31
finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q;
--FullSumAB117_uid50_fpLogETest(BITSELECT,49)@31
FullSumAB117_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q;
FullSumAB117_uid50_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_in(117 downto 117);
--notC_uid71_fpLogETest(LOGICAL,70)@31
notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a;
--signTerm2_uid72_fpLogETest(LOGICAL,71)@31
signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q;
signTerm2_uid72_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_b;
signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor(LOGICAL,966)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q <= not (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a or ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b);
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top(CONSTANT,962)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q <= "011100";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp(LOGICAL,963)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q <= "1" when ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a = ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b else "0";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg(REG,964)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena(REG,967)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd(LOGICAL,968)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a and ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg(DELAY,956)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt(COUNTER,958)
-- every=1, low=0, high=28, step=1, init=1
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i = 27 THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i - 28;
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i,5));
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg(REG,959)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux(MUX,960)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux: PROCESS (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem(DUALMEM,957)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq,
address_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa,
data_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia
);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 <= areset;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC1_uid73_fpLogETest(LOGICAL,72)@31
signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q;
signRC1_uid73_fpLogETest_q_i <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b;
signRC1_uid73_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRC1_uid73_fpLogETest_q, xin => signRC1_uid73_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor(LOGICAL,979)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q <= not (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a or ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena(REG,980)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q = "1") THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd(LOGICAL,981)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b <= en;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a and ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b;
--cstAllZWF_uid8_fpLogETest(CONSTANT,7)
cstAllZWF_uid8_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0
fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b;
fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q;
fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0";
--InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0
InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q;
InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a;
--cstAllOWE_uid12_fpLogETest(CONSTANT,11)
cstAllOWE_uid12_fpLogETest_q <= "11111111111";
--expXIsMax_uid18_fpLogETest(LOGICAL,17)@0
expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q;
expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0";
--exc_N_uid23_fpLogETest(LOGICAL,22)@0
exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q;
exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b;
--InvExc_N_uid24_fpLogETest(LOGICAL,23)@0
InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q;
InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a;
--exc_I_uid21_fpLogETest(LOGICAL,20)@0
exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q;
exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b;
--InvExc_I_uid25_fpLogETest(LOGICAL,24)@0
InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a;
--cstAllZWE_uid14_fpLogETest(CONSTANT,13)
cstAllZWE_uid14_fpLogETest_q <= "00000000000";
--expXIsZero_uid16_fpLogETest(LOGICAL,15)@0
expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0";
--InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0
InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q;
InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a;
--exc_R_uid27_fpLogETest(LOGICAL,26)@0
exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q;
exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q;
exc_R_uid27_fpLogETest_q_i <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c;
exc_R_uid27_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid27_fpLogETest_q, xin => exc_R_uid27_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg(DELAY,969)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem(DUALMEM,970)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq,
address_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa,
data_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia
);
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC11_uid74_fpLogETest(LOGICAL,73)@32
signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q;
signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q;
signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor(LOGICAL,992)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q <= not (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a or ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b);
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena(REG,993)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q = "1") THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd(LOGICAL,994)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b <= en;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a and ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b;
--reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,437)@0
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg(DELAY,982)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem(DUALMEM,983)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia
);
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq(0 downto 0);
--signR_uid75_fpLogETest(LOGICAL,74)@32
signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q;
signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q;
signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor(LOGICAL,1005)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q <= not (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a or ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b);
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena(REG,1006)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q = "1") THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd(LOGICAL,1007)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b <= en;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a and ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b;
--signX_uid7_fpLogETest(BITSELECT,6)@0
signX_uid7_fpLogETest_in <= a;
signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(63 downto 63);
--negNonZero_uid69_fpLogETest(LOGICAL,68)@0
negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b;
negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b;
--excRNaN_uid70_fpLogETest(LOGICAL,69)@0
excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q;
excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q;
excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg(DELAY,995)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem(DUALMEM,996)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq,
address_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa,
data_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia
);
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 <= areset;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq(0 downto 0);
--InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@31
InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q;
InvExcRNaN_uid76_fpLogETest_q_i <= not InvExcRNaN_uid76_fpLogETest_a;
InvExcRNaN_uid76_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => InvExcRNaN_uid76_fpLogETest_q, xin => InvExcRNaN_uid76_fpLogETest_q_i, clk => clk, aclr => areset);
--signRFull_uid77_fpLogETest(LOGICAL,76)@32
signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q;
signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q;
signRFull_uid77_fpLogETest_q_i <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b;
signRFull_uid77_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRFull_uid77_fpLogETest_q, xin => signRFull_uid77_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,522)@33
ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 8 )
PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid147_countZ_uid54_fpLogETest(CONSTANT,146)
zs_uid147_countZ_uid54_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,481)@31
ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB117_uid50_fpLogETest_b, xout => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@31
finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q;
finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((117 downto 1 => FullSumAB117_uid50_fpLogETest_b(0)) & FullSumAB117_uid50_fpLogETest_b);
finalSumOneComp_uid52_fpLogETest_q_i <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b;
finalSumOneComp_uid52_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 118, depth => 1)
PORT MAP (xout => finalSumOneComp_uid52_fpLogETest_q, xin => finalSumOneComp_uid52_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid53_fpLogETest(ADD,52)@32
finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((118 downto 118 => finalSumOneComp_uid52_fpLogETest_q(117)) & finalSumOneComp_uid52_fpLogETest_q);
finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((118 downto 1 => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q);
finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b));
finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(118 downto 0);
--rVStage_uid148_countZ_uid54_fpLogETest(BITSELECT,147)@32
rVStage_uid148_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q;
rVStage_uid148_countZ_uid54_fpLogETest_b <= rVStage_uid148_countZ_uid54_fpLogETest_in(118 downto 55);
--reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1(REG,408)@32
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= rVStage_uid148_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid149_countZ_uid54_fpLogETest(LOGICAL,148)@33
vCount_uid149_countZ_uid54_fpLogETest_a <= reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q;
vCount_uid149_countZ_uid54_fpLogETest_b <= zs_uid147_countZ_uid54_fpLogETest_q;
vCount_uid149_countZ_uid54_fpLogETest_q <= "1" when vCount_uid149_countZ_uid54_fpLogETest_a = vCount_uid149_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6(REG,422)@33
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= vCount_uid149_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g(DELAY,616)@34
ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q, xout => ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid155_countZ_uid54_fpLogETest(CONSTANT,154)
zs_uid155_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000";
--vStage_uid151_countZ_uid54_fpLogETest(BITSELECT,150)@32
vStage_uid151_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(54 downto 0);
vStage_uid151_countZ_uid54_fpLogETest_b <= vStage_uid151_countZ_uid54_fpLogETest_in(54 downto 0);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b(DELAY,574)@32
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => vStage_uid151_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid150_countZ_uid54_fpLogETest(CONSTANT,149)
mO_uid150_countZ_uid54_fpLogETest_q <= "111111111";
--cStage_uid152_countZ_uid54_fpLogETest(BITJOIN,151)@33
cStage_uid152_countZ_uid54_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q & mO_uid150_countZ_uid54_fpLogETest_q;
--ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c(DELAY,576)@32
ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid148_countZ_uid54_fpLogETest_b, xout => ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid154_countZ_uid54_fpLogETest(MUX,153)@33
vStagei_uid154_countZ_uid54_fpLogETest_s <= vCount_uid149_countZ_uid54_fpLogETest_q;
vStagei_uid154_countZ_uid54_fpLogETest: PROCESS (vStagei_uid154_countZ_uid54_fpLogETest_s, en, ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, cStage_uid152_countZ_uid54_fpLogETest_q)
BEGIN
CASE vStagei_uid154_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid154_countZ_uid54_fpLogETest_q <= ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q;
WHEN "1" => vStagei_uid154_countZ_uid54_fpLogETest_q <= cStage_uid152_countZ_uid54_fpLogETest_q;
WHEN OTHERS => vStagei_uid154_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid156_countZ_uid54_fpLogETest(BITSELECT,155)@33
rVStage_uid156_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q;
rVStage_uid156_countZ_uid54_fpLogETest_b <= rVStage_uid156_countZ_uid54_fpLogETest_in(63 downto 32);
--reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1(REG,409)@33
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= rVStage_uid156_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid157_countZ_uid54_fpLogETest(LOGICAL,156)@34
vCount_uid157_countZ_uid54_fpLogETest_a <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
vCount_uid157_countZ_uid54_fpLogETest_b <= zs_uid155_countZ_uid54_fpLogETest_q;
vCount_uid157_countZ_uid54_fpLogETest_q <= "1" when vCount_uid157_countZ_uid54_fpLogETest_a = vCount_uid157_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a(DELAY,876)@34
ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid157_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5(REG,421)@36
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid161_countZ_uid54_fpLogETest(CONSTANT,160)
zs_uid161_countZ_uid54_fpLogETest_q <= "0000000000000000";
--vStage_uid158_countZ_uid54_fpLogETest(BITSELECT,157)@33
vStage_uid158_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q(31 downto 0);
vStage_uid158_countZ_uid54_fpLogETest_b <= vStage_uid158_countZ_uid54_fpLogETest_in(31 downto 0);
--reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3(REG,411)@33
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= vStage_uid158_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid160_countZ_uid54_fpLogETest(MUX,159)@34
vStagei_uid160_countZ_uid54_fpLogETest_s <= vCount_uid157_countZ_uid54_fpLogETest_q;
vStagei_uid160_countZ_uid54_fpLogETest: PROCESS (vStagei_uid160_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q, reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid160_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid160_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid162_countZ_uid54_fpLogETest(BITSELECT,161)@34
rVStage_uid162_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q;
rVStage_uid162_countZ_uid54_fpLogETest_b <= rVStage_uid162_countZ_uid54_fpLogETest_in(31 downto 16);
--reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1(REG,412)@34
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= rVStage_uid162_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid163_countZ_uid54_fpLogETest(LOGICAL,162)@35
vCount_uid163_countZ_uid54_fpLogETest_a <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
vCount_uid163_countZ_uid54_fpLogETest_b <= zs_uid161_countZ_uid54_fpLogETest_q;
vCount_uid163_countZ_uid54_fpLogETest_q <= "1" when vCount_uid163_countZ_uid54_fpLogETest_a = vCount_uid163_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a(DELAY,875)@35
ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid163_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4(REG,420)@36
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid167_countZ_uid54_fpLogETest(CONSTANT,166)
zs_uid167_countZ_uid54_fpLogETest_q <= "00000000";
--vStage_uid164_countZ_uid54_fpLogETest(BITSELECT,163)@34
vStage_uid164_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q(15 downto 0);
vStage_uid164_countZ_uid54_fpLogETest_b <= vStage_uid164_countZ_uid54_fpLogETest_in(15 downto 0);
--reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3(REG,414)@34
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= vStage_uid164_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid166_countZ_uid54_fpLogETest(MUX,165)@35
vStagei_uid166_countZ_uid54_fpLogETest_s <= vCount_uid163_countZ_uid54_fpLogETest_q;
vStagei_uid166_countZ_uid54_fpLogETest: PROCESS (vStagei_uid166_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q, reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid166_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid166_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid168_countZ_uid54_fpLogETest(BITSELECT,167)@35
rVStage_uid168_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q;
rVStage_uid168_countZ_uid54_fpLogETest_b <= rVStage_uid168_countZ_uid54_fpLogETest_in(15 downto 8);
--vCount_uid169_countZ_uid54_fpLogETest(LOGICAL,168)@35
vCount_uid169_countZ_uid54_fpLogETest_a <= rVStage_uid168_countZ_uid54_fpLogETest_b;
vCount_uid169_countZ_uid54_fpLogETest_b <= zs_uid167_countZ_uid54_fpLogETest_q;
vCount_uid169_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid169_countZ_uid54_fpLogETest_a = vCount_uid169_countZ_uid54_fpLogETest_b else "0";
vCount_uid169_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid169_countZ_uid54_fpLogETest_q, xin => vCount_uid169_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d(DELAY,613)@36
ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid169_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid173_countZ_uid54_fpLogETest(CONSTANT,172)
zs_uid173_countZ_uid54_fpLogETest_q <= "0000";
--vStage_uid170_countZ_uid54_fpLogETest(BITSELECT,169)@35
vStage_uid170_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q(7 downto 0);
vStage_uid170_countZ_uid54_fpLogETest_b <= vStage_uid170_countZ_uid54_fpLogETest_in(7 downto 0);
--reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3(REG,416)@35
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= vStage_uid170_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2(REG,415)@35
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= rVStage_uid168_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid172_countZ_uid54_fpLogETest(MUX,171)@36
vStagei_uid172_countZ_uid54_fpLogETest_s <= vCount_uid169_countZ_uid54_fpLogETest_q;
vStagei_uid172_countZ_uid54_fpLogETest: PROCESS (vStagei_uid172_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q, reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid172_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid172_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid174_countZ_uid54_fpLogETest(BITSELECT,173)@36
rVStage_uid174_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q;
rVStage_uid174_countZ_uid54_fpLogETest_b <= rVStage_uid174_countZ_uid54_fpLogETest_in(7 downto 4);
--vCount_uid175_countZ_uid54_fpLogETest(LOGICAL,174)@36
vCount_uid175_countZ_uid54_fpLogETest_a <= rVStage_uid174_countZ_uid54_fpLogETest_b;
vCount_uid175_countZ_uid54_fpLogETest_b <= zs_uid173_countZ_uid54_fpLogETest_q;
vCount_uid175_countZ_uid54_fpLogETest_q <= "1" when vCount_uid175_countZ_uid54_fpLogETest_a = vCount_uid175_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2(REG,419)@36
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= vCount_uid175_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid176_countZ_uid54_fpLogETest(BITSELECT,175)@36
vStage_uid176_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q(3 downto 0);
vStage_uid176_countZ_uid54_fpLogETest_b <= vStage_uid176_countZ_uid54_fpLogETest_in(3 downto 0);
--vStagei_uid178_countZ_uid54_fpLogETest(MUX,177)@36
vStagei_uid178_countZ_uid54_fpLogETest_s <= vCount_uid175_countZ_uid54_fpLogETest_q;
vStagei_uid178_countZ_uid54_fpLogETest: PROCESS (vStagei_uid178_countZ_uid54_fpLogETest_s, en, rVStage_uid174_countZ_uid54_fpLogETest_b, vStage_uid176_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid178_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid178_countZ_uid54_fpLogETest_q <= rVStage_uid174_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid178_countZ_uid54_fpLogETest_q <= vStage_uid176_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid178_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid180_countZ_uid54_fpLogETest(BITSELECT,179)@36
rVStage_uid180_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q;
rVStage_uid180_countZ_uid54_fpLogETest_b <= rVStage_uid180_countZ_uid54_fpLogETest_in(3 downto 2);
--vCount_uid181_countZ_uid54_fpLogETest(LOGICAL,180)@36
vCount_uid181_countZ_uid54_fpLogETest_a <= rVStage_uid180_countZ_uid54_fpLogETest_b;
vCount_uid181_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q;
vCount_uid181_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid181_countZ_uid54_fpLogETest_a = vCount_uid181_countZ_uid54_fpLogETest_b else "0";
vCount_uid181_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid181_countZ_uid54_fpLogETest_q, xin => vCount_uid181_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid182_countZ_uid54_fpLogETest(BITSELECT,181)@36
vStage_uid182_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q(1 downto 0);
vStage_uid182_countZ_uid54_fpLogETest_b <= vStage_uid182_countZ_uid54_fpLogETest_in(1 downto 0);
--reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3(REG,418)@36
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= vStage_uid182_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2(REG,417)@36
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= rVStage_uid180_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid184_countZ_uid54_fpLogETest(MUX,183)@37
vStagei_uid184_countZ_uid54_fpLogETest_s <= vCount_uid181_countZ_uid54_fpLogETest_q;
vStagei_uid184_countZ_uid54_fpLogETest: PROCESS (vStagei_uid184_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q, reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid184_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid184_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_countZ_uid54_fpLogETest(BITSELECT,185)@37
rVStage_uid186_countZ_uid54_fpLogETest_in <= vStagei_uid184_countZ_uid54_fpLogETest_q;
rVStage_uid186_countZ_uid54_fpLogETest_b <= rVStage_uid186_countZ_uid54_fpLogETest_in(1 downto 1);
--vCount_uid187_countZ_uid54_fpLogETest(LOGICAL,186)@37
vCount_uid187_countZ_uid54_fpLogETest_a <= rVStage_uid186_countZ_uid54_fpLogETest_b;
vCount_uid187_countZ_uid54_fpLogETest_b <= GND_q;
vCount_uid187_countZ_uid54_fpLogETest_q <= "1" when vCount_uid187_countZ_uid54_fpLogETest_a = vCount_uid187_countZ_uid54_fpLogETest_b else "0";
--r_uid188_countZ_uid54_fpLogETest(BITJOIN,187)@37
r_uid188_countZ_uid54_fpLogETest_q <= ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q & reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q & reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q & ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q & reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q & vCount_uid181_countZ_uid54_fpLogETest_q & vCount_uid187_countZ_uid54_fpLogETest_q;
--ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b(DELAY,482)@37
ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => r_uid188_countZ_uid54_fpLogETest_q, xout => ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55)
cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010000001100";
--expRExt_uid57_fpLogETest(SUB,56)@38
expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q);
expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("000000" & ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q);
expRExt_uid57_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid57_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b));
END IF;
END IF;
END PROCESS;
expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(12 downto 0);
--LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest(BITSELECT,224)@39
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q(117 downto 0);
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in(117 downto 0);
--leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest(BITJOIN,225)@39
leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b & GND_q;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor(LOGICAL,1114)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a or ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena(REG,1115)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1116)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b;
--X22dto0_uid198_normVal_uid55_fpLogETest(BITSELECT,197)@32
X22dto0_uid198_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(22 downto 0);
X22dto0_uid198_normVal_uid55_fpLogETest_b <= X22dto0_uid198_normVal_uid55_fpLogETest_in(22 downto 0);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg(DELAY,1106)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => X22dto0_uid198_normVal_uid55_fpLogETest_b, xout => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1107)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq(22 downto 0);
--leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest(CONSTANT,196)
leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest(BITJOIN,198)@36
leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5(REG,426)@36
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor(LOGICAL,1103)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q <= not (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a or ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena(REG,1104)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1105)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a and ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1096)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 55,
widthad_a => 1,
numwords_a => 2,
width_b => 55,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq(54 downto 0);
--leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest(BITJOIN,195)@36
leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid147_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4(REG,425)@36
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor(LOGICAL,1092)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a or ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena(REG,1093)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1094)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b;
--X86dto0_uid192_normVal_uid55_fpLogETest(BITSELECT,191)@32
X86dto0_uid192_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(86 downto 0);
X86dto0_uid192_normVal_uid55_fpLogETest_b <= X86dto0_uid192_normVal_uid55_fpLogETest_in(86 downto 0);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg(DELAY,1084)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 87, depth => 1 )
PORT MAP ( xin => X86dto0_uid192_normVal_uid55_fpLogETest_b, xout => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1085)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 87,
widthad_a => 1,
numwords_a => 2,
width_b => 87,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq(86 downto 0);
--leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest(BITJOIN,192)@36
leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid155_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3(REG,424)@36
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor(LOGICAL,1162)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q <= not (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a or ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b);
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena(REG,1163)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q = "1") THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd(LOGICAL,1164)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b <= en;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a and ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg(DELAY,1154)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 119, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem(DUALMEM,1155)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 119,
widthad_a => 1,
numwords_a => 2,
width_b => 119,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq,
address_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa,
data_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia
);
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 <= areset;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq(118 downto 0);
--reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2(REG,423)@36
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest(BITSELECT,199)@37
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q;
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in(6 downto 5);
--leftShiftStage0_uid201_normVal_uid55_fpLogETest(MUX,200)@37
leftShiftStage0_uid201_normVal_uid55_fpLogETest_s <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b;
leftShiftStage0_uid201_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid201_normVal_uid55_fpLogETest_s, en, reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage0_uid201_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest(BITSELECT,208)@37
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(94 downto 0);
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in(94 downto 0);
--leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest(CONSTANT,207)
leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest(BITJOIN,209)@37
leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5(REG,431)@37
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest(BITSELECT,205)@37
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(102 downto 0);
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in(102 downto 0);
--leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest(BITJOIN,206)@37
leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b & zs_uid161_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4(REG,430)@37
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest(BITSELECT,202)@37
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(110 downto 0);
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in(110 downto 0);
--leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest(BITJOIN,203)@37
leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b & zs_uid167_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3(REG,429)@37
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2(REG,428)@37
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest(BITSELECT,210)@37
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(4 downto 0);
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1(REG,427)@37
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid212_normVal_uid55_fpLogETest(MUX,211)@38
leftShiftStage1_uid212_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q;
leftShiftStage1_uid212_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid212_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage1_uid212_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest(BITSELECT,219)@38
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(112 downto 0);
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b <= LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in(112 downto 0);
--ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b(DELAY,645)@38
ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 113, depth => 1 )
PORT MAP ( xin => LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest(CONSTANT,218)
leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q <= "000000";
--leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest(BITJOIN,220)@39
leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q & leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q;
--LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest(BITSELECT,216)@38
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(114 downto 0);
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b <= LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in(114 downto 0);
--ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b(DELAY,643)@38
ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 115, depth => 1 )
PORT MAP ( xin => LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest(BITJOIN,217)@39
leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q & zs_uid173_countZ_uid54_fpLogETest_q;
--LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest(BITSELECT,213)@38
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(116 downto 0);
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b <= LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in(116 downto 0);
--ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b(DELAY,641)@38
ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 117, depth => 1 )
PORT MAP ( xin => LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest(BITJOIN,214)@39
leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q & z2_uid40_fpLogETest_q;
--reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2(REG,433)@38
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest(BITSELECT,221)@37
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(2 downto 0);
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1(REG,432)@37
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b(DELAY,647)@38
ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid223_normVal_uid55_fpLogETest(MUX,222)@39
leftShiftStage2_uid223_normVal_uid55_fpLogETest_s <= ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q;
leftShiftStage2_uid223_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid223_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q, leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage2_uid223_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest(BITSELECT,226)@37
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(0 downto 0);
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b <= leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b(DELAY,655)@37
ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b, xout => ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid228_normVal_uid55_fpLogETest(MUX,227)@39
leftShiftStage3_uid228_normVal_uid55_fpLogETest_s <= ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q;
leftShiftStage3_uid228_normVal_uid55_fpLogETest: PROCESS (leftShiftStage3_uid228_normVal_uid55_fpLogETest_s, en, leftShiftStage2_uid223_normVal_uid55_fpLogETest_q, leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage3_uid228_normVal_uid55_fpLogETest_s IS
WHEN "0" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q;
WHEN "1" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid58_fpLogETest(BITSELECT,57)@39
fracR_uid58_fpLogETest_in <= leftShiftStage3_uid228_normVal_uid55_fpLogETest_q(117 downto 0);
fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(117 downto 65);
--expFracConc_uid59_fpLogETest(BITJOIN,58)@39
expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b;
--reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,434)@39
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid60_fpLogETest(ADD,59)@40
expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q);
expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b));
expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(66 downto 0);
--expR_uid62_fpLogETest(BITSELECT,61)@40
expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(63 downto 0);
expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(63 downto 53);
--reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3(REG,436)@40
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= expR_uid62_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor(LOGICAL,1018)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q <= not (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a or ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b);
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top(CONSTANT,1014)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q <= "0100100";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp(LOGICAL,1015)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q <= "1" when ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a = ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b else "0";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg(REG,1016)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena(REG,1019)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd(LOGICAL,1020)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a and ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b;
--InvSignX_uid65_fpLogETest(LOGICAL,64)@0
InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b;
InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a;
--excRInfC1_uid66_fpLogETest(LOGICAL,65)@0
excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q;
excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b;
--excRInf_uid67_fpLogETest(LOGICAL,66)@0
excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q;
excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q;
excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b;
--FPOne_uid63_fpLogETest(BITJOIN,62)@0
FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q;
--excRZero_uid64_fpLogETest(LOGICAL,63)@0
excRZero_uid64_fpLogETest_a <= a;
excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q;
excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0";
--concExc_uid78_fpLogETest(BITJOIN,77)@0
concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q;
--reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,319)@0
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= concExc_uid78_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg(DELAY,1008)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q, xout => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt(COUNTER,1010)
-- every=1, low=0, high=36, step=1, init=1
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i = 35 THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i - 36;
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i,6));
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg(REG,1011)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux(MUX,1012)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux: PROCESS (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem(DUALMEM,1009)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 37,
width_b => 3,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia
);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq(2 downto 0);
--excREnc_uid79_fpLogETest(LOOKUP,78)@40
excREnc_uid79_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid79_fpLogETest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid79_fpLogETest_q <= "01";
WHEN "001" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "010" => excREnc_uid79_fpLogETest_q <= "10";
WHEN "011" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "100" => excREnc_uid79_fpLogETest_q <= "11";
WHEN "101" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "110" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "111" => excREnc_uid79_fpLogETest_q <= "00";
WHEN OTHERS =>
excREnc_uid79_fpLogETest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid87_fpLogETest(MUX,86)@41
expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q)
BEGIN
CASE expRPostExc_uid87_fpLogETest_s IS
WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q;
WHEN "01" => expRPostExc_uid87_fpLogETest_q <= reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q;
WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79)
oneFracRPostExc2_uid80_fpLogETest_q <= "0000000000000000000000000000000000000000000000000001";
--fracR_uid61_fpLogETest(BITSELECT,60)@40
fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(52 downto 0);
fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(52 downto 1);
--reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3(REG,435)@40
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= fracR_uid61_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid83_fpLogETest(MUX,82)@41
fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q)
BEGIN
CASE fracRPostExc_uid83_fpLogETest_s IS
WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q;
WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q;
WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid88_fpLogETest(BITJOIN,87)@41
RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q;
--xOut(GPOUT,4)@41
q <= RLn_uid88_fpLogETest_q;
end normal;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/fp_ln_double_s5.vhd | 10 | 543973 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln_double_s5
-- VHDL created on Mon Apr 8 15:29:06 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (10 downto 0);
signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0);
signal oMz_uid38_fpLogETest_a : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_b : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_o : std_logic_vector (53 downto 0);
signal oMz_uid38_fpLogETest_q : std_logic_vector (53 downto 0);
signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0);
signal wideZero_uid44_fpLogETest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid45_fpLogETest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q_i : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(117 downto 0);
signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (11 downto 0);
signal expRExt_uid57_fpLogETest_a : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_b : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_o : std_logic_vector (12 downto 0);
signal expRExt_uid57_fpLogETest_q : std_logic_vector (12 downto 0);
signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (51 downto 0);
signal p1_uid92_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid130_natLogPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid142_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid147_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal mO_uid150_countZ_uid54_fpLogETest_q : std_logic_vector (8 downto 0);
signal zs_uid155_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal zs_uid161_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal zs_uid167_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal zs_uid173_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q : std_logic_vector (5 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid238_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm0_uid238_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid241_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm1_uid241_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid98_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid99_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid100_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid101_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid102_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid104_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid105_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid106_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid107_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid108_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid110_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid111_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid112_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid113_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid115_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid116_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid117_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid119_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid120_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0);
signal reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q : std_logic_vector (53 downto 0);
signal reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q : std_logic_vector (49 downto 0);
signal reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (65 downto 0);
signal reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q : std_logic_vector (51 downto 0);
signal reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q : std_logic_vector (10 downto 0);
signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q : std_logic_vector (54 downto 0);
signal ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q : std_logic_vector (116 downto 0);
signal ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q : std_logic_vector (114 downto 0);
signal ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q : std_logic_vector (112 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 : std_logic;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (52 downto 0);
signal FPOne_uid63_fpLogETest_q : std_logic_vector (63 downto 0);
signal pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (66 downto 0);
signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0);
signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogETest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogETest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogETest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0);
signal frac_uid19_fpLogETest_in : std_logic_vector (51 downto 0);
signal frac_uid19_fpLogETest_b : std_logic_vector (51 downto 0);
signal excRZero_uid64_fpLogETest_a : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_b : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0);
signal e_uid29_fpLogETest_a : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_b : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_o : std_logic_vector (11 downto 0);
signal e_uid29_fpLogETest_q : std_logic_vector (11 downto 0);
signal c_uid31_fpLogETest_a : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_b : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0);
signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0);
signal multTermOne_uid42_fpLogETest_q : std_logic_vector (53 downto 0);
signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (118 downto 0);
signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (118 downto 0);
signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (10 downto 0);
signal p0_uid93_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid94_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid94_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid132_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid132_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid138_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid138_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid144_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid144_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_a : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_b : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid41_fpLogETest_q : std_logic_vector (53 downto 0);
signal leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cIncludingRoundingBit_uid131_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid137_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal cIncludingRoundingBit_uid143_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cStage_uid152_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal os_uid103_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid109_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid114_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid121_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid118_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (117 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal RLn_uid88_fpLogETest_q : std_logic_vector (63 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q : std_logic_vector (134 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (41 downto 0);
signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (41 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid134_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT3_uid134_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid61_fpLogETest_in : std_logic_vector (52 downto 0);
signal fracR_uid61_fpLogETest_b : std_logic_vector (51 downto 0);
signal expR_uid62_fpLogETest_in : std_logic_vector (63 downto 0);
signal expR_uid62_fpLogETest_b : std_logic_vector (10 downto 0);
signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (51 downto 0);
signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (9 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0);
signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid91_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid91_constMult_b : std_logic_vector (5 downto 0);
signal addr_uid34_fpLogETest_q : std_logic_vector (10 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_b : std_logic_vector (26 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_in : std_logic_vector (118 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_b : std_logic_vector (63 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_in : std_logic_vector (54 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_b : std_logic_vector (54 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_in : std_logic_vector (86 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_b : std_logic_vector (86 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_in : std_logic_vector (22 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_b : std_logic_vector (22 downto 0);
signal sR_uid95_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid95_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid133_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid133_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid139_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid139_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid145_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid145_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in : std_logic_vector (116 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b : std_logic_vector (116 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in : std_logic_vector (114 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b : std_logic_vector (114 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in : std_logic_vector (112 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b : std_logic_vector (112 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal lowRangeB_uid124_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid124_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid125_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid125_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal FullSumAB117_uid50_fpLogETest_in : std_logic_vector (117 downto 0);
signal FullSumAB117_uid50_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b : std_logic_vector (117 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_in : std_logic_vector (63 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal yT1_uid122_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT1_uid122_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid128_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT2_uid128_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_in : std_logic_vector (14 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_b : std_logic_vector (14 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid37_fpLogETest_in : std_logic_vector (61 downto 0);
signal peOR_uid37_fpLogETest_b : std_logic_vector (54 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid126_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0);
signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0);
signal spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal r_uid188_countZ_uid54_fpLogETest_q : std_logic_vector (6 downto 0);
signal s1_uid124_uid127_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid258_uid261_pT3_uid135_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid273_uid276_pT4_uid141_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (49 downto 0);
signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (49 downto 0);
signal highBBits_uid47_fpLogETest_in : std_logic_vector (108 downto 0);
signal highBBits_uid47_fpLogETest_b : std_logic_vector (58 downto 0);
signal pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid58_fpLogETest_in : std_logic_vector (117 downto 0);
signal fracR_uid58_fpLogETest_b : std_logic_vector (52 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal expFracConc_uid59_fpLogETest_q : std_logic_vector (65 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in : std_logic_vector (110 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b : std_logic_vector (110 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in : std_logic_vector (94 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b : std_logic_vector (94 downto 0);
signal leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
begin
--xIn(GPIN,3)@0
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,902)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor(LOGICAL,914)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a or ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg(REG,912)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena(REG,915)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd(LOGICAL,916)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b;
--frac_uid19_fpLogETest(BITSELECT,18)@0
frac_uid19_fpLogETest_in <= a(51 downto 0);
frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(51 downto 0);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg(DELAY,906)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt(COUNTER,908)
-- every=1, low=0, high=1, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i,1));
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg(REG,909)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux(MUX,910)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem(DUALMEM,907)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 1,
numwords_a => 2,
width_b => 52,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq(51 downto 0);
--zPPolyEval_uid35_fpLogETest(BITSELECT,34)@4
zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q(41 downto 0);
zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(41 downto 0);
--yT2_uid128_natLogPolyEval(BITSELECT,127)@4
yT2_uid128_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT2_uid128_natLogPolyEval_b <= yT2_uid128_natLogPolyEval_in(41 downto 14);
--sSM1W_uid240_pT2_uid129_natLogPolyEval(BITSELECT,239)@4
sSM1W_uid240_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b(0 downto 0);
sSM1W_uid240_pT2_uid129_natLogPolyEval_b <= sSM1W_uid240_pT2_uid129_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1(REG,369)@4
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= sSM1W_uid240_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b(DELAY,672)@5
ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMO_uid10_fpLogETest(CONSTANT,9)
cstBiasMO_uid10_fpLogETest_q <= "01111111110";
--expX_uid6_fpLogETest(BITSELECT,5)@0
expX_uid6_fpLogETest_in <= a(62 downto 0);
expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(62 downto 52);
--c_uid31_fpLogETest(LOGICAL,30)@0
c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b;
c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q;
c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0";
--zAddrLow_uid33_fpLogETest(BITSELECT,32)@0
zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b;
zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(51 downto 42);
--addr_uid34_fpLogETest(BITJOIN,33)@0
addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b;
--reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0(REG,322)@0
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid120_natLogTabGen_lutmem(DUALMEM,316)@1
memoryC4_uid120_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid120_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid120_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid120_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid120_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid120_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid120_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid120_natLogTabGen_lutmem_ia
);
memoryC4_uid120_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid120_natLogTabGen_lutmem_q <= memoryC4_uid120_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1(REG,355)@3
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= memoryC4_uid120_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid119_natLogTabGen_lutmem(DUALMEM,315)@1
memoryC4_uid119_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid119_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid119_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid119_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid119_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid119_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid119_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid119_natLogTabGen_lutmem_ia
);
memoryC4_uid119_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid119_natLogTabGen_lutmem_q <= memoryC4_uid119_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0(REG,354)@3
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= memoryC4_uid119_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid121_natLogTabGen(BITJOIN,120)@4
os_uid121_natLogTabGen_q <= reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q & reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q;
--reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1(REG,357)@4
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= os_uid121_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid122_natLogPolyEval(BITSELECT,121)@4
yT1_uid122_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT1_uid122_natLogPolyEval_b <= yT1_uid122_natLogPolyEval_in(41 downto 25);
--reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0(REG,356)@4
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= yT1_uid122_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid230_pT1_uid123_natLogPolyEval(MULT,229)@5
prodXY_uid230_pT1_uid123_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_a),18)) * SIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_b);
prodXY_uid230_pT1_uid123_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid230_pT1_uid123_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid230_pT1_uid123_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= prodXY_uid230_pT1_uid123_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval(BITSELECT,230)@8
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in <= prodXY_uid230_pT1_uid123_natLogPolyEval_q;
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in(33 downto 15);
--highBBits_uid125_natLogPolyEval(BITSELECT,124)@8
highBBits_uid125_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b;
highBBits_uid125_natLogPolyEval_b <= highBBits_uid125_natLogPolyEval_in(18 downto 1);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor(LOGICAL,1029)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q <= not (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a or ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena(REG,1030)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd(LOGICAL,1031)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a and ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid117_natLogTabGen_lutmem(DUALMEM,314)@1
memoryC3_uid117_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid117_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid117_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid117_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid117_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid117_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid117_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid117_natLogTabGen_lutmem_ia
);
memoryC3_uid117_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid117_natLogTabGen_lutmem_q <= memoryC3_uid117_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2(REG,363)@3
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= memoryC3_uid117_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid116_natLogTabGen_lutmem(DUALMEM,313)@1
memoryC3_uid116_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid116_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid116_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid116_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid116_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid116_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid116_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid116_natLogTabGen_lutmem_ia
);
memoryC3_uid116_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid116_natLogTabGen_lutmem_q <= memoryC3_uid116_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1(REG,362)@3
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= memoryC3_uid116_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid115_natLogTabGen_lutmem(DUALMEM,312)@1
memoryC3_uid115_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid115_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid115_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid115_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid115_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid115_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid115_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid115_natLogTabGen_lutmem_ia
);
memoryC3_uid115_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid115_natLogTabGen_lutmem_q <= memoryC3_uid115_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0(REG,361)@3
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= memoryC3_uid115_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid118_natLogTabGen(BITJOIN,117)@4
os_uid118_natLogTabGen_q <= reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q & reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q & reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg(DELAY,1021)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid118_natLogTabGen_q, xout => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem(DUALMEM,1022)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid126_natLogPolyEval(ADD,125)@8
sumAHighB_uid126_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid126_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid125_natLogPolyEval_b(17)) & highBBits_uid125_natLogPolyEval_b);
sumAHighB_uid126_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid126_natLogPolyEval_a) + SIGNED(sumAHighB_uid126_natLogPolyEval_b));
sumAHighB_uid126_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid124_natLogPolyEval(BITSELECT,123)@8
lowRangeB_uid124_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b(0 downto 0);
lowRangeB_uid124_natLogPolyEval_b <= lowRangeB_uid124_natLogPolyEval_in(0 downto 0);
--s1_uid124_uid127_natLogPolyEval(BITJOIN,126)@8
s1_uid124_uid127_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_q & lowRangeB_uid124_natLogPolyEval_b;
--sSM1H_uid239_pT2_uid129_natLogPolyEval(BITSELECT,238)@8
sSM1H_uid239_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
sSM1H_uid239_pT2_uid129_natLogPolyEval_b <= sSM1H_uid239_pT2_uid129_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0(REG,368)@8
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= sSM1H_uid239_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid241_pT2_uid129_natLogPolyEval(MULT,240)@9
sm1_uid241_pT2_uid129_natLogPolyEval_pr <= SIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_b),2));
sm1_uid241_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q;
sm1_uid241_pT2_uid129_natLogPolyEval_b <= ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q;
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid241_pT2_uid129_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid241_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--GND(CONSTANT,0)
GND_q <= "0";
--pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval(BITJOIN,242)@12
pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid237_pT2_uid129_natLogPolyEval(BITSELECT,236)@4
sSM0W_uid237_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
sSM0W_uid237_pT2_uid129_natLogPolyEval_b <= sSM0W_uid237_pT2_uid129_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a(DELAY,822)@4
ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid237_pT2_uid129_natLogPolyEval_b, xout => ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1(REG,367)@8
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid236_pT2_uid129_natLogPolyEval(BITSELECT,235)@8
sSM0H_uid236_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q(2 downto 0);
sSM0H_uid236_pT2_uid129_natLogPolyEval_b <= sSM0H_uid236_pT2_uid129_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0(REG,366)@8
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= sSM0H_uid236_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid238_pT2_uid129_natLogPolyEval(MULT,237)@9
sm0_uid238_pT2_uid129_natLogPolyEval_pr <= UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_a) * UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_b);
sm0_uid238_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q;
sm0_uid238_pT2_uid129_natLogPolyEval_b <= reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q;
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid238_pT2_uid129_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid238_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval(BITJOIN,241)@12
pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid234_pT2_uid129_natLogPolyEval(BITSELECT,233)@8
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1(REG,365)@8
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor(LOGICAL,1151)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena(REG,1152)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd(LOGICAL,1153)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid233_pT2_uid129_natLogPolyEval(BITSELECT,232)@4
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b <= xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg(DELAY,1143)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b, xout => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem(DUALMEM,1144)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0(REG,364)@8
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid235_pT2_uid129_natLogPolyEval(MULT,234)@9
topProd_uid235_pT2_uid129_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_a),28)) * SIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_b);
topProd_uid235_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_b <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q;
topProd_uid235_pT2_uid129_natLogPolyEval_b <= reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q;
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid235_pT2_uid129_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid235_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= topProd_uid235_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid242_pT2_uid129_natLogPolyEval(ADDSUB3,243)@12
add0_uid242_pT2_uid129_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid235_pT2_uid129_natLogPolyEval_q(53)) & topProd_uid235_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q(26)) & pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_a) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_b) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_c));
add0_uid242_pT2_uid129_natLogPolyEval_q <= add0_uid242_pT2_uid129_natLogPolyEval_o(54 downto 0);
--R_uid245_pT2_uid129_natLogPolyEval(BITSELECT,244)@12
R_uid245_pT2_uid129_natLogPolyEval_in <= add0_uid242_pT2_uid129_natLogPolyEval_q(53 downto 0);
R_uid245_pT2_uid129_natLogPolyEval_b <= R_uid245_pT2_uid129_natLogPolyEval_in(53 downto 24);
--reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1(REG,371)@12
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= R_uid245_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor(LOGICAL,1042)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q <= not (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a or ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b);
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top(CONSTANT,1038)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp(LOGICAL,1039)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a = ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg(REG,1040)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena(REG,1043)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd(LOGICAL,1044)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a and ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid113_natLogTabGen_lutmem(DUALMEM,311)@1
memoryC2_uid113_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid113_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid113_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid113_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid113_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid113_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid113_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid113_natLogTabGen_lutmem_ia
);
memoryC2_uid113_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid113_natLogTabGen_lutmem_q <= memoryC2_uid113_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3(REG,351)@3
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= memoryC2_uid113_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid112_natLogTabGen_lutmem(DUALMEM,310)@1
memoryC2_uid112_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid112_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid112_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid112_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid112_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid112_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid112_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid112_natLogTabGen_lutmem_ia
);
memoryC2_uid112_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid112_natLogTabGen_lutmem_q <= memoryC2_uid112_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2(REG,350)@3
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= memoryC2_uid112_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid111_natLogTabGen_lutmem(DUALMEM,309)@1
memoryC2_uid111_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid111_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid111_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid111_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid111_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid111_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid111_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid111_natLogTabGen_lutmem_ia
);
memoryC2_uid111_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid111_natLogTabGen_lutmem_q <= memoryC2_uid111_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1(REG,349)@3
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= memoryC2_uid111_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid110_natLogTabGen_lutmem(DUALMEM,308)@1
memoryC2_uid110_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid110_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid110_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid110_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid110_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid110_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid110_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid110_natLogTabGen_lutmem_ia
);
memoryC2_uid110_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid110_natLogTabGen_lutmem_q <= memoryC2_uid110_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0(REG,348)@3
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= memoryC2_uid110_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid114_natLogTabGen(BITJOIN,113)@4
os_uid114_natLogTabGen_q <= reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q & reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q & reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q & reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg(DELAY,1032)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid114_natLogTabGen_q, xout => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt(COUNTER,1034)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg(REG,1035)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux(MUX,1036)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem(DUALMEM,1033)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--rndBit_uid130_natLogPolyEval(CONSTANT,129)
rndBit_uid130_natLogPolyEval_q <= "01";
--cIncludingRoundingBit_uid131_natLogPolyEval(BITJOIN,130)@12
cIncludingRoundingBit_uid131_natLogPolyEval_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0(REG,370)@12
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= cIncludingRoundingBit_uid131_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid132_natLogPolyEval(ADD,131)@13
ts2_uid132_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q);
ts2_uid132_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q(29)) & reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q);
ts2_uid132_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid132_natLogPolyEval_a) + SIGNED(ts2_uid132_natLogPolyEval_b));
ts2_uid132_natLogPolyEval_q <= ts2_uid132_natLogPolyEval_o(40 downto 0);
--s2_uid133_natLogPolyEval(BITSELECT,132)@13
s2_uid133_natLogPolyEval_in <= ts2_uid132_natLogPolyEval_q;
s2_uid133_natLogPolyEval_b <= s2_uid133_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid252_pT3_uid135_natLogPolyEval(BITSELECT,251)@13
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9(REG,375)@13
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor(LOGICAL,1055)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top(CONSTANT,1051)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q <= "0110";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp(LOGICAL,1052)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg(REG,1053)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena(REG,1056)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd(LOGICAL,1057)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg(DELAY,1045)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=6, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i = 5 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i,3));
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg(REG,1048)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux(MUX,1049)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem(DUALMEM,1046)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 3,
numwords_a => 7,
width_b => 42,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--yT3_uid134_natLogPolyEval(BITSELECT,133)@13
yT3_uid134_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q;
yT3_uid134_natLogPolyEval_b <= yT3_uid134_natLogPolyEval_in(41 downto 4);
--xBottomBits_uid251_pT3_uid135_natLogPolyEval(BITSELECT,250)@13
xBottomBits_uid251_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b(10 downto 0);
xBottomBits_uid251_pT3_uid135_natLogPolyEval_b <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval(BITJOIN,253)@13
pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7(REG,374)@13
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid250_pT3_uid135_natLogPolyEval(BITSELECT,249)@13
yBottomBits_uid250_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b(12 downto 0);
yBottomBits_uid250_pT3_uid135_natLogPolyEval_b <= yBottomBits_uid250_pT3_uid135_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval(BITJOIN,252)@13
spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q <= GND_q & yBottomBits_uid250_pT3_uid135_natLogPolyEval_b;
--pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval(BITJOIN,254)@13
pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q <= spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6(REG,373)@13
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid249_pT3_uid135_natLogPolyEval(BITSELECT,248)@13
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4(REG,372)@13
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma(CHAINMULTADD,317)@14
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval(BITSELECT,256)@17
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in(36 downto 4);
--highBBits_uid259_pT3_uid135_natLogPolyEval(BITSELECT,258)@17
highBBits_uid259_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b;
highBBits_uid259_pT3_uid135_natLogPolyEval_b <= highBBits_uid259_pT3_uid135_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid247_pT3_uid135_natLogPolyEval(BITSELECT,246)@13
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1(REG,377)@13
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid246_pT3_uid135_natLogPolyEval(BITSELECT,245)@13
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0(REG,376)@13
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid248_pT3_uid135_natLogPolyEval(MULT,247)@14
topProd_uid248_pT3_uid135_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_a),28)) * SIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_b);
topProd_uid248_pT3_uid135_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_b <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q;
topProd_uid248_pT3_uid135_natLogPolyEval_b <= reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q;
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid248_pT3_uid135_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid248_pT3_uid135_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= topProd_uid248_pT3_uid135_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid260_pT3_uid135_natLogPolyEval(ADD,259)@17
sumAHighB_uid260_pT3_uid135_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid248_pT3_uid135_natLogPolyEval_q(53)) & topProd_uid248_pT3_uid135_natLogPolyEval_q);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid259_pT3_uid135_natLogPolyEval_b(28)) & highBBits_uid259_pT3_uid135_natLogPolyEval_b);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_a) + SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_b));
sumAHighB_uid260_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid258_pT3_uid135_natLogPolyEval(BITSELECT,257)@17
lowRangeB_uid258_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b(3 downto 0);
lowRangeB_uid258_pT3_uid135_natLogPolyEval_b <= lowRangeB_uid258_pT3_uid135_natLogPolyEval_in(3 downto 0);
--add0_uid258_uid261_pT3_uid135_natLogPolyEval(BITJOIN,260)@17
add0_uid258_uid261_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_q & lowRangeB_uid258_pT3_uid135_natLogPolyEval_b;
--R_uid262_pT3_uid135_natLogPolyEval(BITSELECT,261)@17
R_uid262_pT3_uid135_natLogPolyEval_in <= add0_uid258_uid261_pT3_uid135_natLogPolyEval_q(57 downto 0);
R_uid262_pT3_uid135_natLogPolyEval_b <= R_uid262_pT3_uid135_natLogPolyEval_in(57 downto 17);
--reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1(REG,379)@17
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= R_uid262_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor(LOGICAL,1068)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q <= not (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a or ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b);
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top(CONSTANT,1064)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp(LOGICAL,1065)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a = ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg(REG,1066)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena(REG,1069)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd(LOGICAL,1070)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a and ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid108_natLogTabGen_lutmem(DUALMEM,307)@1
memoryC1_uid108_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid108_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid108_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid108_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid108_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid108_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid108_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid108_natLogTabGen_lutmem_ia
);
memoryC1_uid108_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid108_natLogTabGen_lutmem_q <= memoryC1_uid108_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4(REG,343)@3
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= memoryC1_uid108_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid107_natLogTabGen_lutmem(DUALMEM,306)@1
memoryC1_uid107_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid107_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid107_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid107_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid107_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid107_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid107_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid107_natLogTabGen_lutmem_ia
);
memoryC1_uid107_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid107_natLogTabGen_lutmem_q <= memoryC1_uid107_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3(REG,342)@3
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= memoryC1_uid107_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid106_natLogTabGen_lutmem(DUALMEM,305)@1
memoryC1_uid106_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid106_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid106_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid106_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid106_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid106_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid106_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid106_natLogTabGen_lutmem_ia
);
memoryC1_uid106_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid106_natLogTabGen_lutmem_q <= memoryC1_uid106_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2(REG,341)@3
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= memoryC1_uid106_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid105_natLogTabGen_lutmem(DUALMEM,304)@1
memoryC1_uid105_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid105_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid105_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid105_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid105_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid105_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid105_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid105_natLogTabGen_lutmem_ia
);
memoryC1_uid105_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid105_natLogTabGen_lutmem_q <= memoryC1_uid105_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1(REG,340)@3
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= memoryC1_uid105_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid104_natLogTabGen_lutmem(DUALMEM,303)@1
memoryC1_uid104_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid104_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid104_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid104_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid104_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid104_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid104_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid104_natLogTabGen_lutmem_ia
);
memoryC1_uid104_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid104_natLogTabGen_lutmem_q <= memoryC1_uid104_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0(REG,339)@3
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= memoryC1_uid104_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid109_natLogTabGen(BITJOIN,108)@4
os_uid109_natLogTabGen_q <= reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q & reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q & reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q & reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q & reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg(DELAY,1058)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid109_natLogTabGen_q, xout => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt(COUNTER,1060)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg(REG,1061)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux(MUX,1062)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem(DUALMEM,1059)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid137_natLogPolyEval(BITJOIN,136)@17
cIncludingRoundingBit_uid137_natLogPolyEval_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0(REG,378)@17
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= cIncludingRoundingBit_uid137_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid138_natLogPolyEval(ADD,137)@18
ts3_uid138_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q);
ts3_uid138_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q(40)) & reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q);
ts3_uid138_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid138_natLogPolyEval_a) + SIGNED(ts3_uid138_natLogPolyEval_b));
ts3_uid138_natLogPolyEval_q <= ts3_uid138_natLogPolyEval_o(50 downto 0);
--s3_uid139_natLogPolyEval(BITSELECT,138)@18
s3_uid139_natLogPolyEval_in <= ts3_uid138_natLogPolyEval_q;
s3_uid139_natLogPolyEval_b <= s3_uid139_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid264_pT4_uid141_natLogPolyEval(BITSELECT,263)@18
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b;
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9(REG,383)@18
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor(LOGICAL,1140)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a or ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top(CONSTANT,1136)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp(LOGICAL,1137)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg(REG,1138)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena(REG,1141)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd(LOGICAL,1142)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid267_pT4_uid141_natLogPolyEval(BITSELECT,266)@4
xBottomBits_uid267_pT4_uid141_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b(14 downto 0);
xBottomBits_uid267_pT4_uid141_natLogPolyEval_b <= xBottomBits_uid267_pT4_uid141_natLogPolyEval_in(14 downto 0);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg(DELAY,1130)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => xBottomBits_uid267_pT4_uid141_natLogPolyEval_b, xout => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt(COUNTER,1132)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg(REG,1133)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux(MUX,1134)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem(DUALMEM,1131)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 4,
numwords_a => 12,
width_b => 15,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq(14 downto 0);
--pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval(BITJOIN,268)@18
pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((10 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7(REG,382)@18
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid266_pT4_uid141_natLogPolyEval(BITSELECT,265)@18
yBottomBits_uid266_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b(22 downto 0);
yBottomBits_uid266_pT4_uid141_natLogPolyEval_b <= yBottomBits_uid266_pT4_uid141_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a(DELAY,704)@18
ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid266_pT4_uid141_natLogPolyEval_b, xout => ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval(BITJOIN,267)@19
spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q;
--pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval(BITJOIN,269)@19
pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q <= spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6(REG,381)@19
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor(LOGICAL,1127)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top(CONSTANT,1123)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp(LOGICAL,1124)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg(REG,1125)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena(REG,1128)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd(LOGICAL,1129)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt(COUNTER,1119)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg(REG,1120)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux(MUX,1121)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem(DUALMEM,1118)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 4,
numwords_a => 13,
width_b => 42,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--xTop27Bits_uid263_pT4_uid141_natLogPolyEval(BITSELECT,262)@19
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in(41 downto 15);
--reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4(REG,380)@19
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma(CHAINMULTADD,318)@20
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval(BITSELECT,271)@23
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in(54 downto 3);
--highBBits_uid274_pT4_uid141_natLogPolyEval(BITSELECT,273)@23
highBBits_uid274_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b;
highBBits_uid274_pT4_uid141_natLogPolyEval_b <= highBBits_uid274_pT4_uid141_natLogPolyEval_in(51 downto 23);
--ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b(DELAY,701)@19
ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid265_pT4_uid141_natLogPolyEval(MULT,264)@20
topProd_uid265_pT4_uid141_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_a),28)) * SIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_b);
topProd_uid265_pT4_uid141_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_b <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q;
topProd_uid265_pT4_uid141_natLogPolyEval_b <= ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q;
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid265_pT4_uid141_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid265_pT4_uid141_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= topProd_uid265_pT4_uid141_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid275_pT4_uid141_natLogPolyEval(ADD,274)@23
sumAHighB_uid275_pT4_uid141_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid265_pT4_uid141_natLogPolyEval_q(53)) & topProd_uid265_pT4_uid141_natLogPolyEval_q);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid274_pT4_uid141_natLogPolyEval_b(28)) & highBBits_uid274_pT4_uid141_natLogPolyEval_b);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_a) + SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_b));
sumAHighB_uid275_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid273_pT4_uid141_natLogPolyEval(BITSELECT,272)@23
lowRangeB_uid273_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b(22 downto 0);
lowRangeB_uid273_pT4_uid141_natLogPolyEval_b <= lowRangeB_uid273_pT4_uid141_natLogPolyEval_in(22 downto 0);
--add0_uid273_uid276_pT4_uid141_natLogPolyEval(BITJOIN,275)@23
add0_uid273_uid276_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_q & lowRangeB_uid273_pT4_uid141_natLogPolyEval_b;
--R_uid277_pT4_uid141_natLogPolyEval(BITSELECT,276)@23
R_uid277_pT4_uid141_natLogPolyEval_in <= add0_uid273_uid276_pT4_uid141_natLogPolyEval_q(76 downto 0);
R_uid277_pT4_uid141_natLogPolyEval_b <= R_uid277_pT4_uid141_natLogPolyEval_in(76 downto 25);
--reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1(REG,387)@23
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= R_uid277_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor(LOGICAL,1081)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q <= not (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a or ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b);
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top(CONSTANT,1077)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp(LOGICAL,1078)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a = ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg(REG,1079)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena(REG,1082)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd(LOGICAL,1083)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a and ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid102_natLogTabGen_lutmem(DUALMEM,302)@1
memoryC0_uid102_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid102_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid102_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid102_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid102_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid102_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid102_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid102_natLogTabGen_lutmem_ia
);
memoryC0_uid102_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid102_natLogTabGen_lutmem_q <= memoryC0_uid102_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5(REG,333)@3
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= memoryC0_uid102_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid101_natLogTabGen_lutmem(DUALMEM,301)@1
memoryC0_uid101_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid101_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid101_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid101_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid101_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid101_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid101_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid101_natLogTabGen_lutmem_ia
);
memoryC0_uid101_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid101_natLogTabGen_lutmem_q <= memoryC0_uid101_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4(REG,332)@3
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= memoryC0_uid101_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid100_natLogTabGen_lutmem(DUALMEM,300)@1
memoryC0_uid100_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid100_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid100_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid100_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid100_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid100_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid100_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid100_natLogTabGen_lutmem_ia
);
memoryC0_uid100_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid100_natLogTabGen_lutmem_q <= memoryC0_uid100_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3(REG,331)@3
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= memoryC0_uid100_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid99_natLogTabGen_lutmem(DUALMEM,299)@1
memoryC0_uid99_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid99_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid99_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid99_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid99_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid99_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid99_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid99_natLogTabGen_lutmem_ia
);
memoryC0_uid99_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid99_natLogTabGen_lutmem_q <= memoryC0_uid99_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2(REG,330)@3
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= memoryC0_uid99_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid98_natLogTabGen_lutmem(DUALMEM,298)@1
memoryC0_uid98_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid98_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid98_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid98_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid98_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid98_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid98_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid98_natLogTabGen_lutmem_ia
);
memoryC0_uid98_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid98_natLogTabGen_lutmem_q <= memoryC0_uid98_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1(REG,329)@3
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= memoryC0_uid98_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,297)@1
memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid97_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid97_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid97_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid97_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid97_natLogTabGen_lutmem_ia
);
memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0(REG,328)@3
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= memoryC0_uid97_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid103_natLogTabGen(BITJOIN,102)@4
os_uid103_natLogTabGen_q <= reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q & reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q & reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q & reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q & reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q & reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg(DELAY,1071)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid103_natLogTabGen_q, xout => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt(COUNTER,1073)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg(REG,1074)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux(MUX,1075)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem(DUALMEM,1072)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid142_natLogPolyEval(CONSTANT,141)
rndBit_uid142_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid143_natLogPolyEval(BITJOIN,142)@23
cIncludingRoundingBit_uid143_natLogPolyEval_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q & rndBit_uid142_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0(REG,386)@23
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= cIncludingRoundingBit_uid143_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid144_natLogPolyEval(ADD,143)@24
ts4_uid144_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q);
ts4_uid144_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q(51)) & reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q);
ts4_uid144_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid144_natLogPolyEval_a) + SIGNED(ts4_uid144_natLogPolyEval_b));
ts4_uid144_natLogPolyEval_q <= ts4_uid144_natLogPolyEval_o(63 downto 0);
--s4_uid145_natLogPolyEval(BITSELECT,144)@24
s4_uid145_natLogPolyEval_in <= ts4_uid144_natLogPolyEval_q;
s4_uid145_natLogPolyEval_b <= s4_uid145_natLogPolyEval_in(63 downto 1);
--peOR_uid37_fpLogETest(BITSELECT,36)@24
peOR_uid37_fpLogETest_in <= s4_uid145_natLogPolyEval_b(61 downto 0);
peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(61 downto 7);
--postPEMul_uid43_fpLogETest_b_2(BITSELECT,281)@24
postPEMul_uid43_fpLogETest_b_2_in <= STD_LOGIC_VECTOR((80 downto 55 => peOR_uid37_fpLogETest_b(54)) & peOR_uid37_fpLogETest_b);
postPEMul_uid43_fpLogETest_b_2_b <= postPEMul_uid43_fpLogETest_b_2_in(80 downto 54);
--reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1(REG,398)@24
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= postPEMul_uid43_fpLogETest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor(LOGICAL,927)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a or ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b);
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top(CONSTANT,923)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q <= "010100";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp(LOGICAL,924)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q <= "1" when ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a = ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b else "0";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg(REG,925)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena(REG,928)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd(LOGICAL,929)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt(COUNTER,919)
-- every=1, low=0, high=20, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i = 19 THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i - 20;
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i,5));
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg(REG,920)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux(MUX,921)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem(DUALMEM,918)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 21,
width_b => 52,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq(51 downto 0);
--pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@23
pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((51 downto 1 => GND_q(0)) & GND_q);
--oMz_uid38_fpLogETest(SUB,38)@23
oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q);
oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q);
oMz_uid38_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oMz_uid38_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b));
END IF;
END IF;
END PROCESS;
oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(53 downto 0);
--z2_uid40_fpLogETest(CONSTANT,39)
z2_uid40_fpLogETest_q <= "00";
--sEz_uid41_fpLogETest(BITJOIN,40)@23
sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q;
--reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2(REG,321)@23
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= sEz_uid41_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor(LOGICAL,940)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena(REG,941)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd(LOGICAL,942)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b;
--reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1(REG,320)@0
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= c_uid31_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg(DELAY,930)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q, xout => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem(DUALMEM,931)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq(0 downto 0);
--multTermOne_uid42_fpLogETest(MUX,41)@24
multTermOne_uid42_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q;
multTermOne_uid42_fpLogETest: PROCESS (multTermOne_uid42_fpLogETest_s, en, reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q, oMz_uid38_fpLogETest_q)
BEGIN
CASE multTermOne_uid42_fpLogETest_s IS
WHEN "0" => multTermOne_uid42_fpLogETest_q <= reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q;
WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q;
WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid43_fpLogETest_a_1(BITSELECT,278)@24
postPEMul_uid43_fpLogETest_a_1_in <= multTermOne_uid42_fpLogETest_q;
postPEMul_uid43_fpLogETest_a_1_b <= postPEMul_uid43_fpLogETest_a_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0(REG,390)@24
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= postPEMul_uid43_fpLogETest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b2(MULT,287)@25
postPEMul_uid43_fpLogETest_a1_b2_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b2_a) * SIGNED(postPEMul_uid43_fpLogETest_a1_b2_b);
postPEMul_uid43_fpLogETest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= postPEMul_uid43_fpLogETest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a(DELAY,739)@28
ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_a1_b2_q, xout => ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_3(BITSHIFT,293)@30
postPEMul_uid43_fpLogETest_align_3_q_int <= ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_3_q <= postPEMul_uid43_fpLogETest_align_3_q_int(134 downto 0);
--postPEMul_uid43_fpLogETest_a_0(BITSELECT,277)@24
postPEMul_uid43_fpLogETest_a_0_in <= multTermOne_uid42_fpLogETest_q(26 downto 0);
postPEMul_uid43_fpLogETest_a_0_b <= postPEMul_uid43_fpLogETest_a_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0(REG,388)@24
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= postPEMul_uid43_fpLogETest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a0_b2(MULT,286)@25
postPEMul_uid43_fpLogETest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a0_b2_a),28)) * SIGNED(postPEMul_uid43_fpLogETest_a0_b2_b);
postPEMul_uid43_fpLogETest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= postPEMul_uid43_fpLogETest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_1(BITSELECT,280)@24
postPEMul_uid43_fpLogETest_b_1_in <= peOR_uid37_fpLogETest_b(53 downto 0);
postPEMul_uid43_fpLogETest_b_1_b <= postPEMul_uid43_fpLogETest_b_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1(REG,393)@24
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= postPEMul_uid43_fpLogETest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b1(MULT,285)@25
postPEMul_uid43_fpLogETest_a1_b1_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b1_b),28));
postPEMul_uid43_fpLogETest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= postPEMul_uid43_fpLogETest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_2_add_0_0(ADD,289)@28
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a1_b1_q(53)) & postPEMul_uid43_fpLogETest_a1_b1_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a0_b2_q(53)) & postPEMul_uid43_fpLogETest_a0_b2_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a(DELAY,738)@28
ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_2(BITSHIFT,292)@29
postPEMul_uid43_fpLogETest_align_2_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_2_q <= postPEMul_uid43_fpLogETest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0(REG,401)@29
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= postPEMul_uid43_fpLogETest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_1(ADD,295)@30
postPEMul_uid43_fpLogETest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q(108)) & reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q);
postPEMul_uid43_fpLogETest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid43_fpLogETest_align_3_q(134)) & postPEMul_uid43_fpLogETest_align_3_q);
postPEMul_uid43_fpLogETest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_b));
postPEMul_uid43_fpLogETest_result_add_0_1_q <= postPEMul_uid43_fpLogETest_result_add_0_1_o(135 downto 0);
--postPEMul_uid43_fpLogETest_a0_b1(MULT,284)@25
postPEMul_uid43_fpLogETest_a0_b1_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_b);
postPEMul_uid43_fpLogETest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= postPEMul_uid43_fpLogETest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_0(BITSELECT,279)@24
postPEMul_uid43_fpLogETest_b_0_in <= peOR_uid37_fpLogETest_b(26 downto 0);
postPEMul_uid43_fpLogETest_b_0_b <= postPEMul_uid43_fpLogETest_b_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1(REG,389)@24
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= postPEMul_uid43_fpLogETest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b0(MULT,283)@25
postPEMul_uid43_fpLogETest_a1_b0_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b0_b),28));
postPEMul_uid43_fpLogETest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= postPEMul_uid43_fpLogETest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_1_add_0_0(ADD,288)@28
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid43_fpLogETest_a1_b0_q(53)) & postPEMul_uid43_fpLogETest_a1_b0_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid43_fpLogETest_a0_b1_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a(DELAY,737)@28
ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_1(BITSHIFT,291)@29
postPEMul_uid43_fpLogETest_align_1_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_1_q <= postPEMul_uid43_fpLogETest_align_1_q_int(82 downto 0);
--postPEMul_uid43_fpLogETest_a0_b0(MULT,282)@25
postPEMul_uid43_fpLogETest_a0_b0_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_b);
postPEMul_uid43_fpLogETest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= postPEMul_uid43_fpLogETest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_align_0(BITSHIFT,290)@28
postPEMul_uid43_fpLogETest_align_0_q_int <= postPEMul_uid43_fpLogETest_a0_b0_q;
postPEMul_uid43_fpLogETest_align_0_q <= postPEMul_uid43_fpLogETest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0(REG,394)@28
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= postPEMul_uid43_fpLogETest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_0(ADD,294)@29
postPEMul_uid43_fpLogETest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q);
postPEMul_uid43_fpLogETest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid43_fpLogETest_align_1_q(82)) & postPEMul_uid43_fpLogETest_align_1_q);
postPEMul_uid43_fpLogETest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_result_add_0_0_q <= postPEMul_uid43_fpLogETest_result_add_0_0_o(83 downto 0);
--postPEMul_uid43_fpLogETest_result_add_1_0(ADD,296)@30
postPEMul_uid43_fpLogETest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid43_fpLogETest_result_add_0_0_q(83)) & postPEMul_uid43_fpLogETest_result_add_0_0_q);
postPEMul_uid43_fpLogETest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid43_fpLogETest_result_add_0_1_q(135)) & postPEMul_uid43_fpLogETest_result_add_0_1_q);
postPEMul_uid43_fpLogETest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_b));
postPEMul_uid43_fpLogETest_result_add_1_0_q <= postPEMul_uid43_fpLogETest_result_add_1_0_o(136 downto 0);
--highBBits_uid47_fpLogETest(BITSELECT,46)@30
highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(108 downto 0);
highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(108 downto 50);
--reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1(REG,406)@30
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= highBBits_uid47_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid44_fpLogETest(CONSTANT,43)
wideZero_uid44_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--cstBias_uid9_fpLogETest(CONSTANT,8)
cstBias_uid9_fpLogETest_q <= "01111111111";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,903)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b);
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,899)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "011000";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,900)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,901)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,904)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,905)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg(DELAY,893)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogETest_b, xout => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,895)
-- every=1, low=0, high=24, step=1, init=1
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 23 THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 24;
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,5));
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,896)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,897)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,894)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 25,
width_b => 11,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia
);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(10 downto 0);
--e_uid29_fpLogETest(SUB,28)@27
e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q);
e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q);
e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b));
e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(11 downto 0);
--xv0_uid90_constMult(BITSELECT,89)@27
xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0);
xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0);
--ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a(DELAY,858)@27
ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv0_uid90_constMult_b, xout => ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0(REG,403)@28
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p0_uid93_constMult(LOOKUP,92)@29
p0_uid93_constMult: PROCESS (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q) IS
WHEN "000000" => p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid93_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid93_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid93_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid93_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid93_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid93_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid93_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid93_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid93_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid93_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid93_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid93_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid93_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid93_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid93_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid93_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid93_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid93_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid93_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid93_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid93_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid93_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid93_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid93_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid93_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid93_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid93_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid93_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid93_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid93_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid93_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid93_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid93_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid93_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid93_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid93_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid93_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid93_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid93_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid93_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid93_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid93_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid93_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid93_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid93_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid93_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid93_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid93_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid93_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid93_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid93_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid93_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid93_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid93_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid93_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid93_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid93_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid93_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid93_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid93_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid93_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid93_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid93_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid91_constMult(BITSELECT,90)@27
xv1_uid91_constMult_in <= e_uid29_fpLogETest_q;
xv1_uid91_constMult_b <= xv1_uid91_constMult_in(11 downto 6);
--reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0(REG,402)@27
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= xv1_uid91_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid92_constMult(LOOKUP,91)@28
p1_uid92_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q) IS
WHEN "000000" => p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid92_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid92_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid92_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid92_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid92_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid92_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid92_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid92_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid92_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid92_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid92_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid92_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid92_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid92_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid92_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid92_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid92_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid92_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid92_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid92_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid92_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid92_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid92_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid92_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid92_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid92_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid92_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid92_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid92_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid92_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid92_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid92_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid92_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid92_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid92_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid92_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid92_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid92_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid92_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid92_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid92_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid92_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid92_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid92_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid92_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid92_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid92_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid92_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid92_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid92_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid92_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid92_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid92_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid92_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid92_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid92_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid92_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid92_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid92_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid92_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid92_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid92_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid92_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid94_constMult(ADD,93)@29
lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid92_constMult_q(68)) & p1_uid92_constMult_q);
lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid93_constMult_q);
lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b));
lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(69 downto 0);
--sR_uid95_constMult(BITSELECT,94)@29
sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(68 downto 0);
sR_uid95_constMult_b <= sR_uid95_constMult_in(68 downto 2);
--reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2(REG,405)@29
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= sR_uid95_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor(LOGICAL,953)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top(CONSTANT,949)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q <= "011010";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp(LOGICAL,950)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q <= "1" when ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a = ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b else "0";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg(REG,951)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena(REG,954)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd(LOGICAL,955)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt(COUNTER,945)
-- every=1, low=0, high=26, step=1, init=1
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i = 25 THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i - 26;
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i,5));
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg(REG,946)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux(MUX,947)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux: PROCESS (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem(DUALMEM,944)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 27,
width_b => 1,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq(0 downto 0);
--addTermOne_uid45_fpLogETest(MUX,44)@30
addTermOne_uid45_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q;
addTermOne_uid45_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid45_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid45_fpLogETest_s IS
WHEN "0" => addTermOne_uid45_fpLogETest_q <= reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q;
WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q;
WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid48_fpLogETest(ADD,47)@31
sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid45_fpLogETest_q(66)) & addTermOne_uid45_fpLogETest_q);
sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q(58)) & reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q);
sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b));
sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(67 downto 0);
--lowRangeB_uid46_fpLogETest(BITSELECT,45)@30
lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(49 downto 0);
lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(49 downto 0);
--reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0(REG,407)@30
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= lowRangeB_uid46_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@31
finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q;
--FullSumAB117_uid50_fpLogETest(BITSELECT,49)@31
FullSumAB117_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q;
FullSumAB117_uid50_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_in(117 downto 117);
--notC_uid71_fpLogETest(LOGICAL,70)@31
notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a;
--signTerm2_uid72_fpLogETest(LOGICAL,71)@31
signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q;
signTerm2_uid72_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_b;
signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor(LOGICAL,966)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q <= not (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a or ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b);
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top(CONSTANT,962)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q <= "011100";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp(LOGICAL,963)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q <= "1" when ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a = ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b else "0";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg(REG,964)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena(REG,967)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd(LOGICAL,968)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a and ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg(DELAY,956)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt(COUNTER,958)
-- every=1, low=0, high=28, step=1, init=1
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i = 27 THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i - 28;
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i,5));
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg(REG,959)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux(MUX,960)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux: PROCESS (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem(DUALMEM,957)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq,
address_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa,
data_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia
);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 <= areset;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC1_uid73_fpLogETest(LOGICAL,72)@31
signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q;
signRC1_uid73_fpLogETest_q_i <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b;
signRC1_uid73_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRC1_uid73_fpLogETest_q, xin => signRC1_uid73_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor(LOGICAL,979)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q <= not (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a or ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena(REG,980)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q = "1") THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd(LOGICAL,981)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b <= en;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a and ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b;
--cstAllZWF_uid8_fpLogETest(CONSTANT,7)
cstAllZWF_uid8_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0
fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b;
fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q;
fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0";
--InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0
InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q;
InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a;
--cstAllOWE_uid12_fpLogETest(CONSTANT,11)
cstAllOWE_uid12_fpLogETest_q <= "11111111111";
--expXIsMax_uid18_fpLogETest(LOGICAL,17)@0
expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q;
expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0";
--exc_N_uid23_fpLogETest(LOGICAL,22)@0
exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q;
exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b;
--InvExc_N_uid24_fpLogETest(LOGICAL,23)@0
InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q;
InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a;
--exc_I_uid21_fpLogETest(LOGICAL,20)@0
exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q;
exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b;
--InvExc_I_uid25_fpLogETest(LOGICAL,24)@0
InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a;
--cstAllZWE_uid14_fpLogETest(CONSTANT,13)
cstAllZWE_uid14_fpLogETest_q <= "00000000000";
--expXIsZero_uid16_fpLogETest(LOGICAL,15)@0
expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0";
--InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0
InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q;
InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a;
--exc_R_uid27_fpLogETest(LOGICAL,26)@0
exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q;
exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q;
exc_R_uid27_fpLogETest_q_i <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c;
exc_R_uid27_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid27_fpLogETest_q, xin => exc_R_uid27_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg(DELAY,969)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem(DUALMEM,970)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq,
address_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa,
data_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia
);
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC11_uid74_fpLogETest(LOGICAL,73)@32
signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q;
signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q;
signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor(LOGICAL,992)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q <= not (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a or ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b);
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena(REG,993)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q = "1") THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd(LOGICAL,994)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b <= en;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a and ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b;
--reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,437)@0
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg(DELAY,982)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem(DUALMEM,983)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia
);
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq(0 downto 0);
--signR_uid75_fpLogETest(LOGICAL,74)@32
signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q;
signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q;
signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor(LOGICAL,1005)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q <= not (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a or ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b);
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena(REG,1006)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q = "1") THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd(LOGICAL,1007)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b <= en;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a and ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b;
--signX_uid7_fpLogETest(BITSELECT,6)@0
signX_uid7_fpLogETest_in <= a;
signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(63 downto 63);
--negNonZero_uid69_fpLogETest(LOGICAL,68)@0
negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b;
negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b;
--excRNaN_uid70_fpLogETest(LOGICAL,69)@0
excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q;
excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q;
excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg(DELAY,995)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem(DUALMEM,996)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq,
address_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa,
data_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia
);
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 <= areset;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq(0 downto 0);
--InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@31
InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q;
InvExcRNaN_uid76_fpLogETest_q_i <= not InvExcRNaN_uid76_fpLogETest_a;
InvExcRNaN_uid76_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => InvExcRNaN_uid76_fpLogETest_q, xin => InvExcRNaN_uid76_fpLogETest_q_i, clk => clk, aclr => areset);
--signRFull_uid77_fpLogETest(LOGICAL,76)@32
signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q;
signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q;
signRFull_uid77_fpLogETest_q_i <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b;
signRFull_uid77_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRFull_uid77_fpLogETest_q, xin => signRFull_uid77_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,522)@33
ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 8 )
PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid147_countZ_uid54_fpLogETest(CONSTANT,146)
zs_uid147_countZ_uid54_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,481)@31
ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB117_uid50_fpLogETest_b, xout => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@31
finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q;
finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((117 downto 1 => FullSumAB117_uid50_fpLogETest_b(0)) & FullSumAB117_uid50_fpLogETest_b);
finalSumOneComp_uid52_fpLogETest_q_i <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b;
finalSumOneComp_uid52_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 118, depth => 1)
PORT MAP (xout => finalSumOneComp_uid52_fpLogETest_q, xin => finalSumOneComp_uid52_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid53_fpLogETest(ADD,52)@32
finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((118 downto 118 => finalSumOneComp_uid52_fpLogETest_q(117)) & finalSumOneComp_uid52_fpLogETest_q);
finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((118 downto 1 => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q);
finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b));
finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(118 downto 0);
--rVStage_uid148_countZ_uid54_fpLogETest(BITSELECT,147)@32
rVStage_uid148_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q;
rVStage_uid148_countZ_uid54_fpLogETest_b <= rVStage_uid148_countZ_uid54_fpLogETest_in(118 downto 55);
--reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1(REG,408)@32
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= rVStage_uid148_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid149_countZ_uid54_fpLogETest(LOGICAL,148)@33
vCount_uid149_countZ_uid54_fpLogETest_a <= reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q;
vCount_uid149_countZ_uid54_fpLogETest_b <= zs_uid147_countZ_uid54_fpLogETest_q;
vCount_uid149_countZ_uid54_fpLogETest_q <= "1" when vCount_uid149_countZ_uid54_fpLogETest_a = vCount_uid149_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6(REG,422)@33
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= vCount_uid149_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g(DELAY,616)@34
ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q, xout => ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid155_countZ_uid54_fpLogETest(CONSTANT,154)
zs_uid155_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000";
--vStage_uid151_countZ_uid54_fpLogETest(BITSELECT,150)@32
vStage_uid151_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(54 downto 0);
vStage_uid151_countZ_uid54_fpLogETest_b <= vStage_uid151_countZ_uid54_fpLogETest_in(54 downto 0);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b(DELAY,574)@32
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => vStage_uid151_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid150_countZ_uid54_fpLogETest(CONSTANT,149)
mO_uid150_countZ_uid54_fpLogETest_q <= "111111111";
--cStage_uid152_countZ_uid54_fpLogETest(BITJOIN,151)@33
cStage_uid152_countZ_uid54_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q & mO_uid150_countZ_uid54_fpLogETest_q;
--ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c(DELAY,576)@32
ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid148_countZ_uid54_fpLogETest_b, xout => ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid154_countZ_uid54_fpLogETest(MUX,153)@33
vStagei_uid154_countZ_uid54_fpLogETest_s <= vCount_uid149_countZ_uid54_fpLogETest_q;
vStagei_uid154_countZ_uid54_fpLogETest: PROCESS (vStagei_uid154_countZ_uid54_fpLogETest_s, en, ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, cStage_uid152_countZ_uid54_fpLogETest_q)
BEGIN
CASE vStagei_uid154_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid154_countZ_uid54_fpLogETest_q <= ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q;
WHEN "1" => vStagei_uid154_countZ_uid54_fpLogETest_q <= cStage_uid152_countZ_uid54_fpLogETest_q;
WHEN OTHERS => vStagei_uid154_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid156_countZ_uid54_fpLogETest(BITSELECT,155)@33
rVStage_uid156_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q;
rVStage_uid156_countZ_uid54_fpLogETest_b <= rVStage_uid156_countZ_uid54_fpLogETest_in(63 downto 32);
--reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1(REG,409)@33
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= rVStage_uid156_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid157_countZ_uid54_fpLogETest(LOGICAL,156)@34
vCount_uid157_countZ_uid54_fpLogETest_a <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
vCount_uid157_countZ_uid54_fpLogETest_b <= zs_uid155_countZ_uid54_fpLogETest_q;
vCount_uid157_countZ_uid54_fpLogETest_q <= "1" when vCount_uid157_countZ_uid54_fpLogETest_a = vCount_uid157_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a(DELAY,876)@34
ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid157_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5(REG,421)@36
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid161_countZ_uid54_fpLogETest(CONSTANT,160)
zs_uid161_countZ_uid54_fpLogETest_q <= "0000000000000000";
--vStage_uid158_countZ_uid54_fpLogETest(BITSELECT,157)@33
vStage_uid158_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q(31 downto 0);
vStage_uid158_countZ_uid54_fpLogETest_b <= vStage_uid158_countZ_uid54_fpLogETest_in(31 downto 0);
--reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3(REG,411)@33
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= vStage_uid158_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid160_countZ_uid54_fpLogETest(MUX,159)@34
vStagei_uid160_countZ_uid54_fpLogETest_s <= vCount_uid157_countZ_uid54_fpLogETest_q;
vStagei_uid160_countZ_uid54_fpLogETest: PROCESS (vStagei_uid160_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q, reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid160_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid160_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid162_countZ_uid54_fpLogETest(BITSELECT,161)@34
rVStage_uid162_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q;
rVStage_uid162_countZ_uid54_fpLogETest_b <= rVStage_uid162_countZ_uid54_fpLogETest_in(31 downto 16);
--reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1(REG,412)@34
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= rVStage_uid162_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid163_countZ_uid54_fpLogETest(LOGICAL,162)@35
vCount_uid163_countZ_uid54_fpLogETest_a <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
vCount_uid163_countZ_uid54_fpLogETest_b <= zs_uid161_countZ_uid54_fpLogETest_q;
vCount_uid163_countZ_uid54_fpLogETest_q <= "1" when vCount_uid163_countZ_uid54_fpLogETest_a = vCount_uid163_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a(DELAY,875)@35
ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid163_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4(REG,420)@36
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid167_countZ_uid54_fpLogETest(CONSTANT,166)
zs_uid167_countZ_uid54_fpLogETest_q <= "00000000";
--vStage_uid164_countZ_uid54_fpLogETest(BITSELECT,163)@34
vStage_uid164_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q(15 downto 0);
vStage_uid164_countZ_uid54_fpLogETest_b <= vStage_uid164_countZ_uid54_fpLogETest_in(15 downto 0);
--reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3(REG,414)@34
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= vStage_uid164_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid166_countZ_uid54_fpLogETest(MUX,165)@35
vStagei_uid166_countZ_uid54_fpLogETest_s <= vCount_uid163_countZ_uid54_fpLogETest_q;
vStagei_uid166_countZ_uid54_fpLogETest: PROCESS (vStagei_uid166_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q, reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid166_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid166_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid168_countZ_uid54_fpLogETest(BITSELECT,167)@35
rVStage_uid168_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q;
rVStage_uid168_countZ_uid54_fpLogETest_b <= rVStage_uid168_countZ_uid54_fpLogETest_in(15 downto 8);
--vCount_uid169_countZ_uid54_fpLogETest(LOGICAL,168)@35
vCount_uid169_countZ_uid54_fpLogETest_a <= rVStage_uid168_countZ_uid54_fpLogETest_b;
vCount_uid169_countZ_uid54_fpLogETest_b <= zs_uid167_countZ_uid54_fpLogETest_q;
vCount_uid169_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid169_countZ_uid54_fpLogETest_a = vCount_uid169_countZ_uid54_fpLogETest_b else "0";
vCount_uid169_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid169_countZ_uid54_fpLogETest_q, xin => vCount_uid169_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d(DELAY,613)@36
ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid169_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid173_countZ_uid54_fpLogETest(CONSTANT,172)
zs_uid173_countZ_uid54_fpLogETest_q <= "0000";
--vStage_uid170_countZ_uid54_fpLogETest(BITSELECT,169)@35
vStage_uid170_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q(7 downto 0);
vStage_uid170_countZ_uid54_fpLogETest_b <= vStage_uid170_countZ_uid54_fpLogETest_in(7 downto 0);
--reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3(REG,416)@35
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= vStage_uid170_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2(REG,415)@35
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= rVStage_uid168_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid172_countZ_uid54_fpLogETest(MUX,171)@36
vStagei_uid172_countZ_uid54_fpLogETest_s <= vCount_uid169_countZ_uid54_fpLogETest_q;
vStagei_uid172_countZ_uid54_fpLogETest: PROCESS (vStagei_uid172_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q, reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid172_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid172_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid174_countZ_uid54_fpLogETest(BITSELECT,173)@36
rVStage_uid174_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q;
rVStage_uid174_countZ_uid54_fpLogETest_b <= rVStage_uid174_countZ_uid54_fpLogETest_in(7 downto 4);
--vCount_uid175_countZ_uid54_fpLogETest(LOGICAL,174)@36
vCount_uid175_countZ_uid54_fpLogETest_a <= rVStage_uid174_countZ_uid54_fpLogETest_b;
vCount_uid175_countZ_uid54_fpLogETest_b <= zs_uid173_countZ_uid54_fpLogETest_q;
vCount_uid175_countZ_uid54_fpLogETest_q <= "1" when vCount_uid175_countZ_uid54_fpLogETest_a = vCount_uid175_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2(REG,419)@36
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= vCount_uid175_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid176_countZ_uid54_fpLogETest(BITSELECT,175)@36
vStage_uid176_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q(3 downto 0);
vStage_uid176_countZ_uid54_fpLogETest_b <= vStage_uid176_countZ_uid54_fpLogETest_in(3 downto 0);
--vStagei_uid178_countZ_uid54_fpLogETest(MUX,177)@36
vStagei_uid178_countZ_uid54_fpLogETest_s <= vCount_uid175_countZ_uid54_fpLogETest_q;
vStagei_uid178_countZ_uid54_fpLogETest: PROCESS (vStagei_uid178_countZ_uid54_fpLogETest_s, en, rVStage_uid174_countZ_uid54_fpLogETest_b, vStage_uid176_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid178_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid178_countZ_uid54_fpLogETest_q <= rVStage_uid174_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid178_countZ_uid54_fpLogETest_q <= vStage_uid176_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid178_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid180_countZ_uid54_fpLogETest(BITSELECT,179)@36
rVStage_uid180_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q;
rVStage_uid180_countZ_uid54_fpLogETest_b <= rVStage_uid180_countZ_uid54_fpLogETest_in(3 downto 2);
--vCount_uid181_countZ_uid54_fpLogETest(LOGICAL,180)@36
vCount_uid181_countZ_uid54_fpLogETest_a <= rVStage_uid180_countZ_uid54_fpLogETest_b;
vCount_uid181_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q;
vCount_uid181_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid181_countZ_uid54_fpLogETest_a = vCount_uid181_countZ_uid54_fpLogETest_b else "0";
vCount_uid181_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid181_countZ_uid54_fpLogETest_q, xin => vCount_uid181_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid182_countZ_uid54_fpLogETest(BITSELECT,181)@36
vStage_uid182_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q(1 downto 0);
vStage_uid182_countZ_uid54_fpLogETest_b <= vStage_uid182_countZ_uid54_fpLogETest_in(1 downto 0);
--reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3(REG,418)@36
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= vStage_uid182_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2(REG,417)@36
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= rVStage_uid180_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid184_countZ_uid54_fpLogETest(MUX,183)@37
vStagei_uid184_countZ_uid54_fpLogETest_s <= vCount_uid181_countZ_uid54_fpLogETest_q;
vStagei_uid184_countZ_uid54_fpLogETest: PROCESS (vStagei_uid184_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q, reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid184_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid184_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_countZ_uid54_fpLogETest(BITSELECT,185)@37
rVStage_uid186_countZ_uid54_fpLogETest_in <= vStagei_uid184_countZ_uid54_fpLogETest_q;
rVStage_uid186_countZ_uid54_fpLogETest_b <= rVStage_uid186_countZ_uid54_fpLogETest_in(1 downto 1);
--vCount_uid187_countZ_uid54_fpLogETest(LOGICAL,186)@37
vCount_uid187_countZ_uid54_fpLogETest_a <= rVStage_uid186_countZ_uid54_fpLogETest_b;
vCount_uid187_countZ_uid54_fpLogETest_b <= GND_q;
vCount_uid187_countZ_uid54_fpLogETest_q <= "1" when vCount_uid187_countZ_uid54_fpLogETest_a = vCount_uid187_countZ_uid54_fpLogETest_b else "0";
--r_uid188_countZ_uid54_fpLogETest(BITJOIN,187)@37
r_uid188_countZ_uid54_fpLogETest_q <= ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q & reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q & reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q & ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q & reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q & vCount_uid181_countZ_uid54_fpLogETest_q & vCount_uid187_countZ_uid54_fpLogETest_q;
--ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b(DELAY,482)@37
ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => r_uid188_countZ_uid54_fpLogETest_q, xout => ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55)
cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010000001100";
--expRExt_uid57_fpLogETest(SUB,56)@38
expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q);
expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("000000" & ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q);
expRExt_uid57_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid57_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b));
END IF;
END IF;
END PROCESS;
expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(12 downto 0);
--LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest(BITSELECT,224)@39
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q(117 downto 0);
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in(117 downto 0);
--leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest(BITJOIN,225)@39
leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b & GND_q;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor(LOGICAL,1114)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a or ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena(REG,1115)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1116)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b;
--X22dto0_uid198_normVal_uid55_fpLogETest(BITSELECT,197)@32
X22dto0_uid198_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(22 downto 0);
X22dto0_uid198_normVal_uid55_fpLogETest_b <= X22dto0_uid198_normVal_uid55_fpLogETest_in(22 downto 0);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg(DELAY,1106)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => X22dto0_uid198_normVal_uid55_fpLogETest_b, xout => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1107)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq(22 downto 0);
--leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest(CONSTANT,196)
leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest(BITJOIN,198)@36
leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5(REG,426)@36
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor(LOGICAL,1103)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q <= not (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a or ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena(REG,1104)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1105)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a and ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1096)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 55,
widthad_a => 1,
numwords_a => 2,
width_b => 55,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq(54 downto 0);
--leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest(BITJOIN,195)@36
leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid147_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4(REG,425)@36
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor(LOGICAL,1092)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a or ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena(REG,1093)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1094)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b;
--X86dto0_uid192_normVal_uid55_fpLogETest(BITSELECT,191)@32
X86dto0_uid192_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(86 downto 0);
X86dto0_uid192_normVal_uid55_fpLogETest_b <= X86dto0_uid192_normVal_uid55_fpLogETest_in(86 downto 0);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg(DELAY,1084)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 87, depth => 1 )
PORT MAP ( xin => X86dto0_uid192_normVal_uid55_fpLogETest_b, xout => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1085)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 87,
widthad_a => 1,
numwords_a => 2,
width_b => 87,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq(86 downto 0);
--leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest(BITJOIN,192)@36
leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid155_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3(REG,424)@36
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor(LOGICAL,1162)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q <= not (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a or ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b);
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena(REG,1163)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q = "1") THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd(LOGICAL,1164)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b <= en;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a and ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg(DELAY,1154)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 119, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem(DUALMEM,1155)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 119,
widthad_a => 1,
numwords_a => 2,
width_b => 119,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq,
address_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa,
data_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia
);
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 <= areset;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq(118 downto 0);
--reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2(REG,423)@36
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest(BITSELECT,199)@37
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q;
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in(6 downto 5);
--leftShiftStage0_uid201_normVal_uid55_fpLogETest(MUX,200)@37
leftShiftStage0_uid201_normVal_uid55_fpLogETest_s <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b;
leftShiftStage0_uid201_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid201_normVal_uid55_fpLogETest_s, en, reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage0_uid201_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest(BITSELECT,208)@37
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(94 downto 0);
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in(94 downto 0);
--leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest(CONSTANT,207)
leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest(BITJOIN,209)@37
leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5(REG,431)@37
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest(BITSELECT,205)@37
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(102 downto 0);
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in(102 downto 0);
--leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest(BITJOIN,206)@37
leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b & zs_uid161_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4(REG,430)@37
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest(BITSELECT,202)@37
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(110 downto 0);
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in(110 downto 0);
--leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest(BITJOIN,203)@37
leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b & zs_uid167_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3(REG,429)@37
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2(REG,428)@37
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest(BITSELECT,210)@37
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(4 downto 0);
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1(REG,427)@37
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid212_normVal_uid55_fpLogETest(MUX,211)@38
leftShiftStage1_uid212_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q;
leftShiftStage1_uid212_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid212_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage1_uid212_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest(BITSELECT,219)@38
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(112 downto 0);
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b <= LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in(112 downto 0);
--ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b(DELAY,645)@38
ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 113, depth => 1 )
PORT MAP ( xin => LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest(CONSTANT,218)
leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q <= "000000";
--leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest(BITJOIN,220)@39
leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q & leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q;
--LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest(BITSELECT,216)@38
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(114 downto 0);
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b <= LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in(114 downto 0);
--ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b(DELAY,643)@38
ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 115, depth => 1 )
PORT MAP ( xin => LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest(BITJOIN,217)@39
leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q & zs_uid173_countZ_uid54_fpLogETest_q;
--LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest(BITSELECT,213)@38
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(116 downto 0);
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b <= LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in(116 downto 0);
--ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b(DELAY,641)@38
ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 117, depth => 1 )
PORT MAP ( xin => LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest(BITJOIN,214)@39
leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q & z2_uid40_fpLogETest_q;
--reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2(REG,433)@38
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest(BITSELECT,221)@37
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(2 downto 0);
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1(REG,432)@37
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b(DELAY,647)@38
ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid223_normVal_uid55_fpLogETest(MUX,222)@39
leftShiftStage2_uid223_normVal_uid55_fpLogETest_s <= ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q;
leftShiftStage2_uid223_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid223_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q, leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage2_uid223_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest(BITSELECT,226)@37
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(0 downto 0);
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b <= leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b(DELAY,655)@37
ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b, xout => ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid228_normVal_uid55_fpLogETest(MUX,227)@39
leftShiftStage3_uid228_normVal_uid55_fpLogETest_s <= ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q;
leftShiftStage3_uid228_normVal_uid55_fpLogETest: PROCESS (leftShiftStage3_uid228_normVal_uid55_fpLogETest_s, en, leftShiftStage2_uid223_normVal_uid55_fpLogETest_q, leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage3_uid228_normVal_uid55_fpLogETest_s IS
WHEN "0" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q;
WHEN "1" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid58_fpLogETest(BITSELECT,57)@39
fracR_uid58_fpLogETest_in <= leftShiftStage3_uid228_normVal_uid55_fpLogETest_q(117 downto 0);
fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(117 downto 65);
--expFracConc_uid59_fpLogETest(BITJOIN,58)@39
expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b;
--reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,434)@39
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid60_fpLogETest(ADD,59)@40
expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q);
expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b));
expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(66 downto 0);
--expR_uid62_fpLogETest(BITSELECT,61)@40
expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(63 downto 0);
expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(63 downto 53);
--reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3(REG,436)@40
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= expR_uid62_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor(LOGICAL,1018)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q <= not (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a or ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b);
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top(CONSTANT,1014)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q <= "0100100";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp(LOGICAL,1015)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q <= "1" when ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a = ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b else "0";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg(REG,1016)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena(REG,1019)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd(LOGICAL,1020)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a and ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b;
--InvSignX_uid65_fpLogETest(LOGICAL,64)@0
InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b;
InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a;
--excRInfC1_uid66_fpLogETest(LOGICAL,65)@0
excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q;
excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b;
--excRInf_uid67_fpLogETest(LOGICAL,66)@0
excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q;
excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q;
excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b;
--FPOne_uid63_fpLogETest(BITJOIN,62)@0
FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q;
--excRZero_uid64_fpLogETest(LOGICAL,63)@0
excRZero_uid64_fpLogETest_a <= a;
excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q;
excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0";
--concExc_uid78_fpLogETest(BITJOIN,77)@0
concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q;
--reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,319)@0
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= concExc_uid78_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg(DELAY,1008)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q, xout => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt(COUNTER,1010)
-- every=1, low=0, high=36, step=1, init=1
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i = 35 THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i - 36;
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i,6));
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg(REG,1011)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux(MUX,1012)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux: PROCESS (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem(DUALMEM,1009)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 37,
width_b => 3,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia
);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq(2 downto 0);
--excREnc_uid79_fpLogETest(LOOKUP,78)@40
excREnc_uid79_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid79_fpLogETest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid79_fpLogETest_q <= "01";
WHEN "001" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "010" => excREnc_uid79_fpLogETest_q <= "10";
WHEN "011" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "100" => excREnc_uid79_fpLogETest_q <= "11";
WHEN "101" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "110" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "111" => excREnc_uid79_fpLogETest_q <= "00";
WHEN OTHERS =>
excREnc_uid79_fpLogETest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid87_fpLogETest(MUX,86)@41
expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q)
BEGIN
CASE expRPostExc_uid87_fpLogETest_s IS
WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q;
WHEN "01" => expRPostExc_uid87_fpLogETest_q <= reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q;
WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79)
oneFracRPostExc2_uid80_fpLogETest_q <= "0000000000000000000000000000000000000000000000000001";
--fracR_uid61_fpLogETest(BITSELECT,60)@40
fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(52 downto 0);
fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(52 downto 1);
--reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3(REG,435)@40
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= fracR_uid61_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid83_fpLogETest(MUX,82)@41
fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q)
BEGIN
CASE fracRPostExc_uid83_fpLogETest_s IS
WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q;
WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q;
WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid88_fpLogETest(BITJOIN,87)@41
RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q;
--xOut(GPOUT,4)@41
q <= RLn_uid88_fpLogETest_q;
end normal;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/fp_sinpi_s5.vhd | 10 | 314232 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/fp_sinpi_s5.vhd | 10 | 314232 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_divrndpipe.vhd | 10 | 7102 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVRNDPIPE.VHD ***
--*** ***
--*** Function: Output Stage, Pipelined Round ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 3 ***
--***************************************************
ENTITY hcc_divrndpipe IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
END hcc_divrndpipe;
ARCHITECTURE rtl OF hcc_divrndpipe IS
signal zerovec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal satinff, zipinff, naninff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal roundmantissanode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff, exponenttwoff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal manoverflowff : STD_LOGIC;
signal infinitygen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzv: FOR k IN 1 TO 53 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= "000";
satinff <= "00";
zipinff <= "00";
naninff <= "00";
manoverflowff <= '0';
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff(1) <= signin;
signff(2) <= signff(1);
signff(3) <= signff(2);
satinff(1) <= satin;
satinff(2) <= satinff(1);
zipinff(1) <= zipin;
zipinff(2) <= zipinff(1);
naninff(1) <= nanin;
naninff(2) <= naninff(1);
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= (roundmantissanode(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(13 DOWNTO 1) <= exponentin;
exponenttwoff(13 DOWNTO 1) <= exponentoneff(13 DOWNTO 1) +
(zerovec(12 DOWNTO 1) & manoverflowff);
FOR k IN 1 TO 11 LOOP
exponentff(k) <= (exponenttwoff(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
gaa: IF (synthesize = 0) GENERATE
addb: hcc_addpipeb
GENERIC MAP (width=>52,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mantissain(53 DOWNTO 2),bb=>zerovec(52 DOWNTO 1),
carryin=>mantissain(1),
cc=>roundmantissanode);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addb: hcc_addpipes
GENERIC MAP (width=>52,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mantissain(53 DOWNTO 2),bb=>zerovec(52 DOWNTO 1),
carryin=>mantissain(1),
cc=>roundmantissanode);
END GENERATE;
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissain(1);
gmoa: FOR k IN 2 TO 53 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissain(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent >= 255
infinitygen(1) <= exponenttwoff(1);
gia: FOR k IN 2 TO 11 GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponenttwoff(k);
END GENERATE;
-- 12/05/09 - make sure exponent = -1 doesnt make infinity
infinitygen(12) <= (infinitygen(11) AND NOT(exponenttwoff(12)) AND NOT(exponenttwoff(13))) OR
satinff(2) OR (exponenttwoff(12) AND NOT(exponenttwoff(13))); -- '1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponenttwoff(1);
gza: FOR k IN 2 TO 11 GENERATE
zerogen(k) <= zerogen(k-1) OR exponenttwoff(k);
END GENERATE;
zerogen(12) <= NOT(zerogen(11)) OR zipinff(2) OR exponenttwoff(13); -- '1' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= infinitygen(12) OR zerogen(12);
setmanmax <= naninff(2);
-- set exponent to 0 when zero condition
setexpzero <= zerogen(12);
-- set exponent to "11..11" infinity
setexpmax <= infinitygen(12) OR naninff(2);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(3);
mantissaout <= mantissaff;
exponentout <= exponentff;
END rtl;
| mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/hcc_cntusgn32_sv.vhd | 20 | 4321 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
| mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/hcc_cntusgn32_sv.vhd | 20 | 4321 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
| mit |
CamelClarkson/MIPS | Register_File/sources/32x32_Mem.vhd | 2 | 10087 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Declares the entity Reg_Depth. This is the 32-bit memory/depth at each address of the register
entity Reg_Depth is
Port (
i_Clk : in std_logic; --Input clock
i_Data : in std_logic_vector(31 downto 0); --Input Data
i_Rst : in std_logic; --Input Reset (Active High)
i_w_en : in std_logic; --Read/Write enable
i_rA_sel : in std_logic; --Select bit for tri state buffer for data A
i_rB_sel : in std_logic; --Select bit for tri state buffer for Data B
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end Reg_Depth;
architecture structural of Reg_Depth is
--Declares the RFC component
component RFC is
Port (
iClk : in std_logic;
i_Rst : in std_logic;
w_sel : in std_logic;
i_data : in std_logic;
R_sel_A : in std_logic;
R_sel_B : in std_logic;
A : out std_logic;
B : out std_logic
);
end component;
begin
--Instatiates 32 RFCs that control the memory. 32 of them are instatiated because there are 32-bits at each depth
--because they are 1 bit each. 32 bit values are routed to i_data, R_sel_A, and R_sel_B to select which data is outputted,
--or written to.
Inst_RFC31: RFC
port map(
iClk => i_Clk, --Input Clock
i_Rst => i_Rst, --asynchronous reset
w_sel => i_w_en, --Read/Write enable
i_data => i_Data(31),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(31),
B => o_Data_B(31)
);
Inst_RFC30: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(30),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(30),
B => o_Data_B(30)
);
Inst_RFC29: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(29),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(29),
B => o_Data_B(29)
);
Inst_RFC28: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(28),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(28),
B => o_Data_B(28)
);
Inst_RFC27: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(27),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(27),
B => o_Data_B(27)
);
Inst_RFC26: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(26),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(26),
B => o_Data_B(26)
);
Inst_RFC25: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(25),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(25),
B => o_Data_B(25)
);
Inst_RFC24: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(24),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(24),
B => o_Data_B(24)
);
Inst_RFC23: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(23),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(23),
B => o_Data_B(23)
);
Inst_RFC22: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(22),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(22),
B => o_Data_B(22)
);
Inst_RFC21: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(21),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(21),
B => o_Data_B(21)
);
Inst_RFC20: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(20),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(20),
B => o_Data_B(20)
);
Inst_RFC19: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(19),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(19),
B => o_Data_B(19)
);
Inst_RFC18: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(18),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(18),
B => o_Data_B(18)
);
Inst_RFC17: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(17),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(17),
B => o_Data_B(17)
);
Inst_RFC16: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(16),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(16),
B => o_Data_B(16)
);
Inst_RFC15: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(15),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(15),
B => o_Data_B(15)
);
Inst_RFC14: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(14),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(14),
B => o_Data_B(14)
);
Inst_RFC13: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(13),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(13),
B => o_Data_B(13)
);
Inst_RFC12: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(12),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(12),
B => o_Data_B(12)
);
Inst_RFC11: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(11),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(11),
B => o_Data_B(11)
);
Inst_RFC10: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(10),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(10),
B => o_Data_B(10)
);
Inst_RFC9: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(9),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(9),
B => o_Data_B(9)
);
Inst_RFC8: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(8),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(8),
B => o_Data_B(8)
);
Inst_RFC7: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(7),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(7),
B => o_Data_B(7)
);
Inst_RFC6: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(6),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(6),
B => o_Data_B(6)
);
Inst_RFC5: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(5),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(5),
B => o_Data_B(5)
);
Inst_RFC4: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(4),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(4),
B => o_Data_B(4)
);
Inst_RFC3: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(3),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(3),
B => o_Data_B(3)
);
Inst_RFC2: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(2),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(2),
B => o_Data_B(2)
);
Inst_RFC1: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(1),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(1),
B => o_Data_B(1)
);
Inst_RFC0: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(0),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(0),
B => o_Data_B(0)
);
end structural;
| mit |
CamelClarkson/MIPS | ALU_Control/ALU_Control.vhd | 2 | 970 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity o_ALU_Control is
Port (
-- inputs
i_ALUOp : in STD_LOGIC_VECTOR(1 downto 0); -- From Main Control Unit
i_Inst_Funct : in STD_LOGIC_VECTOR(5 downto 0); -- From Instruction memory
-- outputs
o_ALU_Control : out STD_LOGIC_VECTOR(3 downto 0) -- Control lines to ALU
);
end o_ALU_Control;
architecture Behavioral of o_ALU_Control is
begin
o_ALU_Control(0) <= i_ALUOp(1) and ((not(i_Inst_Funct(3)) and not(i_Inst_Funct(1)) and i_Inst_Funct(2) and i_Inst_Funct(0)) or (i_Inst_Funct(3) and i_Inst_Funct(1) and not(i_Inst_Funct(2)) and not(i_Inst_Funct(0))));
o_ALU_Control(1) <= not(i_ALUOp(1)) or (not(i_Inst_Funct(2)) and not(i_Inst_Funct(0)));
o_ALU_Control(2) <= (not(i_ALUOp(1)) and i_ALUOp(0)) or (i_ALUOp(1) and not(i_Inst_Funct(2)) and i_Inst_Funct(1) and not(i_Inst_Funct(0)));
o_ALU_Control(3) <= '0';
end Behavioral;
| mit |
CamelClarkson/MIPS | MIPS_Design/Src/Register_File.vhd | 2 | 2893 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Top Level Register_File entity
entity Register_File is
Port (
i_Clk : in std_logic;
i_Rst : in std_logic;
i_regwrite : in std_logic;
i_rt : in std_logic_vector(4 downto 0);
i_rs : in std_logic_vector(4 downto 0);
i_rd : in std_logic_vector(4 downto 0);
i_rd_data : in std_logic_vector(31 downto 0);
o_rt_data : out std_logic_vector(31 downto 0);
o_rs_data : out std_logic_vector(31 downto 0)
);
end Register_File;
architecture Structural of Register_File is
--Creates signals for addresses for the Decoder/Muxiplier
signal s_rd_addr : std_logic_vector(31 downto 0);
signal s_rt_addr : std_logic_vector(31 downto 0);
signal s_rs_addr : std_logic_vector(31 downto 0);
--Declares 32 registers with a 32 bit depth
component Register32X32 is
Port(
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic_vector(31 downto 0);
i_rA_sel : in std_logic_vector(31 downto 0);
i_rB_sel : in std_logic_vector(31 downto 0);
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end component;
component Decoder is
Port (
i_w_Addr : in std_logic_vector(4 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end component;
component W_Decoder is
Port (
i_w_Addr : in std_logic_vector(5 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end component;
begin
--Decodes the 6 bit write address to a 32 bit binary value to enable writing to a register
Inst_Decoder_W: W_Decoder
port map(
i_w_Addr => i_regwrite & i_rd,
o_w_Addr => s_rd_Addr
);
--Decodes the 5 bit rt address to a 32 bit binary value used to enable the i_rA_sel input of the Register32X32 instatiation
Inst_Decoder_rt: Decoder
port map(
i_w_Addr => i_rt,
o_w_Addr => s_rt_addr
);
--Decodes the 5 bit rd address to a 32 bit binary value used to enable the i_rB_sel input of the Register32X32 instatiation
Inst_Decoder_rd: Decoder
port map(
i_w_Addr => i_rs,
o_w_Addr => s_rs_addr
);
--Instatiates the Register32X32 component, a 32 address register, 32 bit depth memory
Inst_Register32X32: Register32X32
port map(
i_Clk => i_Clk,
i_Data => i_rd_data,
i_Rst => i_Rst,
i_w_en => s_rd_Addr,
i_rA_sel => s_rt_addr,
i_rB_sel => s_rs_addr,
o_Data_A => o_rt_Data,
o_Data_B => o_rs_Data
);
end Structural;
| mit |
CamelClarkson/MIPS | MIPS_Design/Src/Zero_Flag_Gen.vhd | 2 | 1635 | ----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:10:39 PM
-- Design Name:
-- Module Name: LE - LE_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Zero_Flag_Gen is
Port ( F : in STD_LOGIC_VECTOR (31 downto 0);
ZERO : out STD_LOGIC);
end Zero_Flag_Gen;
architecture Zero_Flag_Func of Zero_Flag_Gen is
begin
ZERO <= not(F(31) or F(30) or F(29) or F(28) or F(27) or F(26) or F(25) or F(24) or F(23) or F(22) or F(21) or F(20) or F(19) or F(18) or F(17) or F(16) or F(15) or F(14) or F(13) or F(12) or F(11) or F(10) or F(9) or F(8) or F(7) or F(6) or F(5) or F(4) or F(3) or F(2) or F(1) or F(0));
end Zero_Flag_Func;
| mit |
CamelClarkson/MIPS | SLT_MUX.vhd | 2 | 3779 | ----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:25:05 PM
-- Design Name:
-- Module Name: ALU4Bit - ALU_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SLT_MUX is
Port ( F_pre : in STD_LOGIC_VECTOR (31 downto 0); -- before merge in the slt
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
Overflow : in STD_LOGIC;
SltOpVal : out STD_LOGIC;
F : out STD_LOGIC_VECTOR (31 downto 0)); --after merge in the slt
end SLT_MUX;
architecture SLTM_Func of SLT_MUX is
signal SltOpVal_wire : STD_LOGIC; -- set less than operation valid, valid is 1
signal Set : STD_LOGIC; -- set when the sign of the F_pre xor overflow is 1
--Because 0 in 32bit is 0000_0000_0000_0000_0000_0000_0000_0000, sign bit is 0.
--When A = B, result of subject is 0, will not Set.
begin
SltOpVal_wire <= (not P3) and P2 and P1 and P0;
SltOpVal <= SltOpVal_wire;
Set <= F_pre(31) xor Overflow; -- operand A less than operand B
F(31) <= (not SltOpVal_wire) and F_pre(31);
F(30) <= (not SltOpVal_wire) and F_pre(30);
F(29) <= (not SltOpVal_wire) and F_pre(29);
F(28) <= (not SltOpVal_wire) and F_pre(28);
F(27) <= (not SltOpVal_wire) and F_pre(27);
F(26) <= (not SltOpVal_wire) and F_pre(26);
F(25) <= (not SltOpVal_wire) and F_pre(25);
F(24) <= (not SltOpVal_wire) and F_pre(24);
F(23) <= (not SltOpVal_wire) and F_pre(23);
F(22) <= (not SltOpVal_wire) and F_pre(22);
F(21) <= (not SltOpVal_wire) and F_pre(21);
F(20) <= (not SltOpVal_wire) and F_pre(20);
F(19) <= (not SltOpVal_wire) and F_pre(19);
F(18) <= (not SltOpVal_wire) and F_pre(18);
F(17) <= (not SltOpVal_wire) and F_pre(17);
F(16) <= (not SltOpVal_wire) and F_pre(16);
F(15) <= (not SltOpVal_wire) and F_pre(15);
F(14) <= (not SltOpVal_wire) and F_pre(14);
F(13) <= (not SltOpVal_wire) and F_pre(13);
F(12) <= (not SltOpVal_wire) and F_pre(12);
F(11) <= (not SltOpVal_wire) and F_pre(11);
F(10) <= (not SltOpVal_wire) and F_pre(10);
F(9) <= (not SltOpVal_wire) and F_pre(9);
F(8) <= (not SltOpVal_wire) and F_pre(8);
F(7) <= (not SltOpVal_wire) and F_pre(7);
F(6) <= (not SltOpVal_wire) and F_pre(6);
F(5) <= (not SltOpVal_wire) and F_pre(5);
F(4) <= (not SltOpVal_wire) and F_pre(4);
F(3) <= (not SltOpVal_wire) and F_pre(3);
F(2) <= (not SltOpVal_wire) and F_pre(2);
F(1) <= (not SltOpVal_wire) and F_pre(1);
F(0) <= (SltOpVal_wire and Set) or ((not SltOpVal_wire) and F_pre(0));
end SLTM_Func;
| mit |
CamelClarkson/MIPS | Overflow_gen.vhd | 2 | 1595 | ----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:23:17 PM
-- Design Name:
-- Module Name: OverflowXor - OX_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Overflow_gen is
Port (
C31 : in STD_LOGIC;
C32 : in STD_LOGIC;
SltOpVal : in STD_LOGIC;
Overflow_slt : out STD_LOGIC;
Overflow : out STD_LOGIC);
end Overflow_gen;
architecture OXS_Func of Overflow_gen is
signal Temp1 : STD_LOGIC; --overflow before mask
begin
Temp1 <= C31 xor C32;
Overflow_slt <= Temp1; --in order to do the slt, no mask
Overflow <= Temp1 and (not(SltOpVal)); --Masked overflow for output
end OXS_Func;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_rst_module.vhd | 3 | 24245 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_dma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000
-- Scatter Gather clock frequency in hertz
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
----------------------------------------------------------------------- --
-- Soft Reset --
----------------------------------------------------------------------- --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_all_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_all_idle : in std_logic ; --
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_mm2s_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
mm2s_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
mm2s_cntrl_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
mm2s_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
--
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_s2mm_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
s2mm_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
s2mm_sts_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
s2mm_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out
----------------------------------------------------------------------- --
-- AXI Scatter Gather Reset Out
m_axi_sg_aresetn : out std_logic := '1' ; --
-- AXI Scatter Gather Datamover Reset Out
dm_m_axi_sg_aresetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_hrdresetn : out std_logic := '1' ; --
s_axi_lite_resetn : out std_logic := '1' --
);
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of s_axi_lite_resetn : signal is "TRUE";
Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no";
end axi_dma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
ATTRIBUTE async_reg : STRING;
signal hrd_resetn_i_cdc_tig : std_logic := '1';
signal hrd_resetn_i_d1_cdc_tig : std_logic := '1';
--ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true";
-- Soft reset support
signal mm2s_soft_reset_clr : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
signal soft_reset_clr_i : std_logic := '0';
signal mm2s_soft_reset_done : std_logic := '0';
signal s2mm_soft_reset_done : std_logic := '0';
signal mm2s_scndry_resetn_i : std_logic := '0';
signal s2mm_scndry_resetn_i : std_logic := '0';
signal dm_mm2s_scndry_resetn_i : std_logic := '0';
signal dm_s2mm_scndry_resetn_i : std_logic := '0';
signal sg_hard_reset : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register hard reset in
REG_HRD_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => sg_hard_reset,
scndry_vect_out => open
);
m_axi_sg_hrdresetn <= sg_hard_reset;
--REG_HRD_RST : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- hrd_resetn_i_cdc_tig <= axi_resetn;
-- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig;
-- end if;
-- end process REG_HRD_RST;
-- Regsiter hard reset out for axi lite interface
REG_HRD_RST_OUT : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s_axi_lite_resetn,
scndry_vect_out => open
);
--REG_HRD_RST_OUT : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig;
-- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig;
-- end if;
-- end process REG_HRD_RST_OUT;
dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i;
dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i;
-- mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface (default)
MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate
begin
-- both must be low before sg reset is asserted.
m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_BOTH;
-- Only s2mm channel included therefore map secondary resets to
-- from s2mm reset module to scatter gather interface
MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate
begin
m_axi_sg_aresetn <= s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_S2MM;
-- Only mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface
MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= mm2s_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i;
end generate MAP_SG_FOR_MM2S;
-- Invalid configuration for axi dma - simply here for completeness
MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= '1';
dm_m_axi_sg_aresetn <= '1';
end generate MAP_NO_SG;
s2mm_scndry_resetn <= s2mm_scndry_resetn_i;
mm2s_scndry_resetn <= mm2s_scndry_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
RESET_I : entity axi_dma_v7_1.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_mm2s_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
-- Secondary Reset
scndry_resetn => mm2s_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_mm2s_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_mm2s_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => mm2s_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => mm2s_cntrl_reset_out_n
);
-- Sample an hold mm2s soft reset done to use in
-- combined reset done to DMACR
MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
mm2s_soft_reset_done <= '0';
elsif(mm2s_soft_reset_clr = '1')then
mm2s_soft_reset_done <= '1';
end if;
end if;
end process MM2S_SOFT_RST_DONE;
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_reset_out_n <= '1';
mm2s_cntrl_reset_out_n <= '1';
dm_mm2s_scndry_resetn_i <= '1';
dm_mm2s_prmry_resetn <= '1';
mm2s_prmry_resetn <= '1';
mm2s_scndry_resetn_i <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
mm2s_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
RESET_I : entity axi_dma_v7_1.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_s2mm_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
-- Secondary Reset
scndry_resetn => s2mm_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_s2mm_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_s2mm_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => s2mm_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => s2mm_sts_reset_out_n
);
-- Sample an hold s2mm soft reset done to use in
-- combined reset done to DMACR
S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
s2mm_soft_reset_done <= '0';
elsif(s2mm_soft_reset_clr = '1')then
s2mm_soft_reset_done <= '1';
end if;
end if;
end process S2MM_SOFT_RST_DONE;
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_reset_out_n <= '1';
dm_s2mm_scndry_resetn_i <= '1';
dm_s2mm_prmry_resetn <= '1';
s2mm_prmry_resetn <= '1';
s2mm_scndry_resetn_i <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
s2mm_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_S2MM;
-- When both mm2s and s2mm are done then drive soft reset clear and
-- also clear s_h registers above
soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done;
soft_reset_clr <= soft_reset_clr_i;
end implementation;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg.vhd | 1 | 84392 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
dm_resetn : in std_logic ; --
sg_ctl : in std_logic_vector (7 downto 0) ;
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic;
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
ch2_update_active : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic;
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ;
bd_eq : out std_logic
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
signal m_axi_sg_awaddr_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; --
signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; --
signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awvalid_int : std_logic ; --
signal m_axi_sg_awready_int : std_logic ; --
--
-- Scatter Gather Write Data Channel --
signal m_axi_sg_wdata_int : std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
signal m_axi_sg_wstrb_int : std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
signal m_axi_sg_wlast_int : std_logic ; --
signal m_axi_sg_wvalid_int : std_logic ; --
signal m_axi_sg_wready_int : std_logic ; --
signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0);
signal m_axi_sg_bvalid_int : std_logic;
signal m_axi_sg_bready_int : std_logic;
signal m_axi_sg_bvalid_int_del : std_logic;
signal ch2_eof_detected : std_logic;
signal s_axis_ch2_updtsts_tready_i : std_logic;
signal ch2_sg_idle, tail_updt_latch : std_logic;
signal tail_updt : std_logic;
signal ch2_taildesc_wren_int : std_logic;
signal ch2_sg_idle_int : std_logic;
signal ftch_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal updt_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch1_ftch_slverr_set_i : std_logic := '0';
signal ch1_ftch_decerr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_slverr_set_i : std_logic := '0';
signal ch2_ftch_decerr_set_i : std_logic := '0';
signal ch1_updt_interr_set_i : std_logic := '0';
signal ch1_updt_slverr_set_i : std_logic := '0';
signal ch1_updt_decerr_set_i : std_logic := '0';
signal ch2_updt_interr_set_i : std_logic := '0';
signal ch2_updt_slverr_set_i : std_logic := '0';
signal ch2_updt_decerr_set_i : std_logic := '0';
signal ftch_error_capture : std_logic := '0';
signal updt_error_capture : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
ftch_error_capture <= ch1_ftch_interr_set_i or
ch1_ftch_slverr_set_i or
ch1_ftch_decerr_set_i or
ch2_ftch_interr_set_i or
ch2_ftch_slverr_set_i or
ch2_ftch_decerr_set_i;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i;
ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i;
ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i;
updt_error_capture <= ch1_updt_interr_set_i or
ch1_updt_slverr_set_i or
ch1_updt_decerr_set_i or
ch2_updt_interr_set_i or
ch2_updt_slverr_set_i or
ch2_updt_decerr_set_i or
ch2_dma_interr_set_i or
ch2_dma_slverr_set_i or
ch2_dma_decerr_set_i or
ch1_dma_interr_set_i or
ch1_dma_slverr_set_i or
ch1_dma_decerr_set_i;
ch1_updt_interr_set <= ch1_updt_interr_set_i;
ch1_updt_slverr_set <= ch1_updt_slverr_set_i;
ch1_updt_decerr_set <= ch1_updt_decerr_set_i;
ch2_updt_interr_set <= ch2_updt_interr_set_i;
ch2_updt_slverr_set <= ch2_updt_slverr_set_i;
ch2_updt_decerr_set <= ch2_updt_decerr_set_i;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (31 downto 6) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6);
elsif (updt_error_capture = '1') then
ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6);
end if;
end if;
end process;
ADDR_64 : if (C_M_AXI_SG_ADDR_WIDTH > 32) generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (63 downto 32) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (63 downto 32)<= ftch_error_addr_1(63 downto 32);
elsif (updt_error_capture = '1') then
ftch_error_addr (63 downto 32)<= updt_error_addr_1(63 downto 32);
end if;
end if;
end process;
end generate ADDR_64;
updt_error_addr <= (others => '0');
ftch_error_addr (5 downto 0) <= (others => '0');
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i;
EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate
ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26)
and s_axis_ch2_updtsts_tready_i
and s_axis_ch2_updtsts_tvalid
and s_axis_ch2_updtsts_tlast;
-- ch2_eof_detected <= '0';
ch2_sg_idle_int <= ch2_sg_idle;
-- ch2_sg_idle_int <= '0'; --ch2_sg_idle;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here
tail_updt <= '0';
elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then
tail_updt <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt;
--ch2_taildesc_wren_int <= ch2_taildesc_wren;
end generate EOF_DET;
NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate
tail_updt <= '0';
ch2_eof_detected <= '0';
ch2_taildesc_wren_int <= ch2_taildesc_wren;
ch2_sg_idle_int <= '0'; --ch2_sg_idle;
end generate NOEOF_DET;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_sg_v4_1.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set_i ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set_i ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set_i ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set_i ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set_i ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set_i ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren_int ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
ch2_eof_detected => ch2_eof_detected ,
tail_updt => tail_updt ,
tail_updt_latch => tail_updt_latch ,
ch2_sg_idle => ch2_sg_idle ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr_1 ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_sg_v4_1.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ACTUAL_ADDR => C_ACTUAL_ADDR,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => ch2_sg_idle_int ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_cyclic => ch1_cyclic ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_cyclic => ch2_cyclic ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_sg_v4_1.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set_i ,
ch1_updt_slverr_set => ch1_updt_slverr_set_i ,
ch1_updt_decerr_set => ch1_updt_decerr_set_i ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set_i ,
ch2_updt_slverr_set => ch2_updt_slverr_set_i ,
ch2_updt_decerr_set => ch2_updt_decerr_set_i ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr_1
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_sg_v4_1.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_sg_v4_1.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_sg_v4_1.axi_sg_datamover
generic map(
C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, --
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
sg_ctl => sg_ctl ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_aruser => m_axi_sg_aruser ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr_int ,
m_axi_s2mm_awlen => m_axi_sg_awlen_int ,
m_axi_s2mm_awsize => m_axi_sg_awsize_int ,
m_axi_s2mm_awburst => m_axi_sg_awburst_int ,
m_axi_s2mm_awprot => m_axi_sg_awprot_int ,
m_axi_s2mm_awcache => m_axi_sg_awcache_int ,
m_axi_s2mm_awuser => m_axi_sg_awuser_int ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid_int ,
m_axi_s2mm_awready => m_axi_sg_awready_int ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid_int ,
m_axi_s2mm_wready => m_axi_sg_wready_int ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp_int ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid_int ,
m_axi_s2mm_bready => m_axi_sg_bready_int ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
--ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate
-- begin
m_axi_sg_awaddr <= m_axi_sg_awaddr_int ;
m_axi_sg_awlen <= m_axi_sg_awlen_int ;
m_axi_sg_awsize <= m_axi_sg_awsize_int ;
m_axi_sg_awburst <= m_axi_sg_awburst_int;
m_axi_sg_awprot <= m_axi_sg_awprot_int ;
m_axi_sg_awcache <= m_axi_sg_awcache_int;
m_axi_sg_awuser <= m_axi_sg_awuser_int ;
m_axi_sg_awvalid <= m_axi_sg_awvalid_int;
m_axi_sg_awready_int <= m_axi_sg_awready;
m_axi_sg_wvalid <= m_axi_sg_wvalid_int;
m_axi_sg_wready_int <= m_axi_sg_wready;
m_axi_sg_bresp_int <= m_axi_sg_bresp;
m_axi_sg_bvalid_int <= m_axi_sg_bvalid;
m_axi_sg_bready <= m_axi_sg_bready_int;
-- end generate ENABLE_MM2S_STATUS;
--DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate
--
-- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int;
-- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int;
-- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int;
-- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int;
-- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int;
-- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int;
-- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int;
-- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int;
-- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine.
--
-- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int;
-- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine
--
-- m_axi_sg_bresp_int <= m_axi_sg_bresp;
-- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid;
-- m_axi_sg_bready <= m_axi_sg_bready_int;
--
ch2_update_active <= ch2_updt_active;
--
---- A dummy response is needed to keep things running on DMA side
-- PROC_DUMMY_RESP : process (m_axi_sg_aclk)
-- begin
-- if (dm_resetn = '0') then
-- m_axi_sg_bvalid_int_del <= '0';
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int;
-- end if;
-- end process PROC_DUMMY_RESP;
--
-- end generate DISABLE_MM2S_STATUS;
end implementation;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma.vhd | 1 | 126849 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library axi_sg_v4_1;
use axi_sg_v4_1.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
-- coverage off
max_value := "11100";
-- coverage on
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
function width_calc (value_in : integer)
return integer is
variable addr_value : integer := 32;
begin
if (value_in > 32) then
addr_value := 64;
else
addr_value := 32;
end if;
return(addr_value);
end function width_calc;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant ADDR_WIDTH : integer := width_calc (C_M_AXI_SG_ADDR_WIDTH);
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 1;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
constant CMD_WIDTH : integer := ((8*C_ENABLE_MULTI_CHANNEL)+ ADDR_WIDTH+ CMD_BASE_WIDTH) ;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
signal bd_eq : std_logic;
signal m_axi_sg_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_sg_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_mm2s_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_s2mm_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_ACTUAL_ADDR => C_M_AXI_SG_ADDR_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr_internal ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr_internal ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ,
bd_eq => bd_eq
);
m_axi_sg_awaddr <= m_axi_sg_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_araddr <= m_axi_sg_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH, --C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_CMD_WIDTH => CMD_WIDTH,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr_internal ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr_internal ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_mm2s_basic_wrap.vhd | 5 | 43235 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_reset;
use axi_sg_v4_1.axi_sg_cmd_status;
use axi_sg_v4_1.axi_sg_scc;
use axi_sg_v4_1.axi_sg_addr_cntl;
use axi_sg_v4_1.axi_sg_rddata_cntl;
use axi_sg_v4_1.axi_sg_rd_status_cntl;
use axi_sg_v4_1.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect_fdiv_32ns_32ns_32_30.vhd | 4 | 3373 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fdiv_32ns_32ns_32_30 is
generic (
ID : integer := 50;
NUM_STAGE : integer := 30;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fdiv_32ns_32ns_32_30 is
--------------------- Component ---------------------
component tri_intersect_ap_fdiv_28_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fdiv_28_no_dsp_32_u : component tri_intersect_ap_fdiv_28_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 9 | 86039 | `protect begin_protected
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| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_wr_sf.vhd | 6 | 50543 | -------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Write (S2MM) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. This module buffers write data and provides status and
-- control features such that the DataMover Write Master is only allowed
-- to post AXI WRite Requests if the associated write data needed to complete
-- the Write Data transfer is present in the Data FIFO. In addition, the Write
-- side logic is such that Write transfer requests can be pipelined to the
-- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data
-- transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
library lib_srl_fifo_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_wr_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
-- C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- -- Indicates the max burst length being used by the external
-- -- AXI4 Master for each AXI4 transfer request.
-- C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- -- Indicates if the external Master is utilizing a DRE on
-- -- the stream input to this module.
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 16;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs -----------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
-------------------------------------------------------------------------
-- Slave Stream Input ------------------------------------------------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
sin2sf_error : In std_logic; --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. --
-----------------------------------------------------------------------------------
-- DataMover Write Side Address Pipelining Control Interface ----------------------
--
ok_to_post_wr_addr : Out Std_logic; --
-- Indicates that the internal FIFO has enough data --
-- physically present to supply one more max length --
-- burst transfer or a completion burst --
-- (tlast asserted) --
--
wr_addr_posted : In std_logic; --
-- Indication that a write address has been posted to AXI4 --
--
--
wr_xfer_cmplt : In Std_logic; --
-- Indicates that the Datamover has completed a Write Data --
-- transfer on the AXI4 --
--
--
wr_ld_nxt_len : in std_logic; --
-- Active high pulse indicating a new transfer LEN qualifier --
-- has been queued to the DataMover Write Data Controller --
--
wr_len : in std_logic_vector(7 downto 0); --
-- The actual LEN qualifier value that has been queued to the --
-- DataMover Write Data Controller --
-----------------------------------------------------------------------------------
-- Write Side Stream Out to DataMover S2MM ----------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic; --
-- Write LAST output to the Stream Master --
--
sf2sout_error : Out std_logic --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
);
end entity axi_datamover_wr_sf;
architecture implementation of axi_datamover_wr_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant EOP_ERR_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
-- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
--WSTB_WIDTH +
TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
-- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
-- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
-- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
signal sig_sf2sout_eop_err_out : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
sf2sout_error <= sig_sf2sout_eop_err_out ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_good_fifo_write <= sig_good_sin_strm_dbeat;
sig_strm_sin_ready <= not(sig_data_fifo_full);
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_error &
sin2sf_tlast &
-- sin2sf_tkeep &
sin2sf_tdata;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_err_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
-- Generate the stream ready
sig_strm_sin_ready <= not(lsig_packer_full) or
lsig_good_push2fifo ;
-- Format the FIFO input data
sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit
lsig_tlast_or &
lsig_combined_data ; -- LS Bits
-- Generate a write to the Data FIFO input
sig_push_data_fifo <= lsig_packer_full;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_sin_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sin_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_sin_strm_dbeat and
(sin2sf_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_sin_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice for the packer.
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= sin2sf_tdata;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1
sin2sf_error; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or
--lsig_partial_eop_err_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register outputs into a single
-- vector for input to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Input attachments
-- sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= sin2sf_error &
-- sin2sf_tlast &
-- sin2sf_tkeep &
-- sin2sf_tdata;
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
-- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
-- TSTRB_OUT_LSB_INDEX);
-- When this Store and Forward is enabled, the Write Data Controller ignores the
-- TKEEP input so this is not sent through the FIFO.
sig_sf2sout_tkeep <= (others => '1');
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ;
-- FIFO Rd/WR Controls
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
-- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
sig_incr_uncom_wrcnt <= sig_good_fifo_write;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
-- The LEN FIFO stores the xfer lengths needed for each queued
-- write transfer in the DataMover S2MM Write Data Controller.
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_wr_demux.vhd | 18 | 75691 | -------------------------------------------------------------------------------
-- axi_datamover_wr_demux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_datamover_wr_demux;
architecture implementation of axi_datamover_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/tri_intersect_data_array.vhd | 3 | 4553 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tri_intersect_data_array_ram is
generic(
mem_type : string := "block";
dwidth : integer := 576;
awidth : integer := 5;
mem_size : integer := 20
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of tri_intersect_data_array_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1_tmp)) := d1;
end if;
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity tri_intersect_data_array is
generic (
DataWidth : INTEGER := 576;
AddressRange : INTEGER := 20;
AddressWidth : INTEGER := 5);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of tri_intersect_data_array is
component tri_intersect_data_array_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
tri_intersect_data_array_ram_U : component tri_intersect_data_array_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1,
q1 => q1);
end architecture;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd | 1 | 50345 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0';
-- KAPIL
signal ch_desc_flush : std_logic := '0';
signal m_axis_ch_ftch_tready : std_logic := '0';
signal ch_ftch_queue_empty : std_logic := '0';
signal ch_ftch_queue_full : std_logic := '0';
signal ch_ftch_pause : std_logic := '0';
signal ch_writing_curdesc : std_logic := '0';
signal ch_ftch_tready : std_logic := '0';
signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch_ftch_tvalid : std_logic := '0';
signal m_axis_ch_ftch_tlast : std_logic := '0';
signal data_concat : std_logic_vector (95 downto 0) := (others => '0');
signal data_concat_64 : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_64_cdma : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0');
signal next_bd : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_valid, tvalid_new : std_logic;
attribute mark_debug of data_concat_valid : signal is "true";
attribute mark_debug of tvalid_new : signal is "true";
signal data_concat_tlast, tlast_new : std_logic;
attribute mark_debug of data_concat_tlast : signal is "true";
attribute mark_debug of tlast_new : signal is "true";
signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0);
attribute mark_debug of counter : signal is "true";
signal sof_ftch_desc : std_logic;
signal nxtdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
attribute mark_debug of nxtdesc_int : signal is "true";
signal cyclic_enable : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else
ch2_cyclic;
nxtdesc <= nxtdesc_int;
TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate
-- TLAST is generated when 8th beat is received
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
SOF_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then
sof_ftch_desc <= '0';
elsif(counter (6) = '1'
and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tvalid = '1'
and m_axis_mm2s_tdata(27) = '1' )then
sof_ftch_desc <= '1';
end if;
end if;
end process SOF_CHECK;
end generate TLAST_GEN;
NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate
sof_ftch_desc <= '0';
CDMA : if C_ENABLE_CDMA = 1 generate
-- For CDMA TLAST is generated when 7th beat is received
-- because last one is not needed
tlast_new <= counter (6) and m_axis_mm2s_tvalid;
tvalid_new <=counter (6) and m_axis_mm2s_tvalid;
end generate CDMA;
NOCDMA : if C_ENABLE_CDMA = 0 generate
-- For DMA tlast is generated with 8th beat
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
end generate NOCDMA;
end generate NOTLAST_GEN;
-- Following shift register keeps track of number of data beats
-- of BD that is being read
DATA_BEAT_REG : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then
counter (0) <= '1';
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0');
Elsif (m_axis_mm2s_tvalid = '1') then
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0);
counter (0) <= '0';
end if;
end if;
end process DATA_BEAT_REG;
-- Registering the Buffer address from BD, 3rd beat
-- Common for DMA, CDMA
DATA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (31 downto 0) <= (others => '0');
Elsif (counter (2) = '1') then
data_concat (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1;
ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (31 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1_64;
end generate ADDR_64BIT;
ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG1_64;
data_concat_64 (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate ADDR_64BIT2;
DMA_REG2 : if C_ENABLE_CDMA = 0 generate
begin
-- For DMA, the 7th beat has the control information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (6) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
end generate DMA_REG2;
CDMA_REG2 : if C_ENABLE_CDMA = 1 generate
begin
-- For CDMA, the 5th beat has the DA information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
CDMA_ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (31 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2_64;
end generate CDMA_ADDR_64BIT;
CDMA_ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG2_64;
data_concat_64_cdma (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate CDMA_ADDR_64BIT2;
end generate CDMA_REG2;
NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate
begin
-- Last beat is directly concatenated and passed to FIFO
-- Masking the CMPLT bit with cyclic_enable
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end generate NOFLOP_FOR_QUEUE;
-- In absence of queuing option the last beat needs to be floped
FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate
begin
NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95 downto 64) <= (others => '0');
Elsif (counter (7) = '1') then
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
end if;
end if;
end process DATA_REG3;
end generate NO_FETCH_Q;
FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95) <= '0';
Elsif (counter (7) = '1') then
data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable);
end if;
end if;
end process DATA_REG3;
data_concat (94 downto 64) <= (others => '0');
end generate FETCH_Q;
DATA_CNTRL : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_valid <= '0';
data_concat_tlast <= '0';
Else
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end if;
end if;
end process DATA_CNTRL;
end generate FLOP_FOR_NOQUEUE;
-- Since the McDMA BD has two more fields to be captured
-- following procedures are needed
NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
data_concat_mcdma <= (others => '0');
end generate NOMCDMA_FTECH;
MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
DATA_MCDMA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (31 downto 0) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG1;
DATA_MCDMA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (63 downto 32) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG2;
end generate MCDMA_BD_FETCH;
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then
nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6);
-- BD addresses are always 16 word 32-bit aligned
nxtdesc_int(5 downto 0) <= (others => '0');
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (0) = '1' --etch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_ACTUAL_ADDR = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
GEN_UPPER_MSB_NXTDESC2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
nxtdesc_int (63 downto C_ACTUAL_ADDR) <= (others => '0');
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC2;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1' and (not cyclic_enable);
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_INCLUDE_MM2S => C_INCLUDE_CH1,
C_INCLUDE_S2MM => C_INCLUDE_CH2,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => '0' ,
-- Channel Control
desc1_flush => ch1_desc_flush ,
desc2_flush => ch2_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch1_active => ch1_ftch_active ,
ftch2_active => ch2_ftch_active ,
ftch1_queue_empty => ch1_ftch_queue_empty ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch1_queue_full => ch1_ftch_queue_full ,
ftch2_queue_full => ch2_ftch_queue_full ,
ftch1_pause => ch1_ftch_pause ,
ftch2_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing1_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat_64_cdma => data_concat_64_cdma,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
m_axis1_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk ,
m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch1_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch2_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0');
end generate GEN_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_CH1 => C_INCLUDE_CH1
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
desc2_flush => ch2_desc_flush ,
ftch2_active => ch2_ftch_active ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch2_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch_desc_available => m_axis_ftch1_desc_available ,
m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis2_ftch_desc_available => m_axis_ftch2_desc_available ,
m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
ch1_ftch_pause <= '0';
ch2_ftch_pause <= '0';
end generate GEN_NO_QUEUE;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
counter(0),
counter(1),
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(counter(0) = '1' or counter(1)='1')then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_afifo_autord.vhd | 6 | 16830 | -------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_Rd_clk or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect_fmul_32ns_32ns_32_5_max_dsp.vhd | 4 | 3386 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fmul_32ns_32ns_32_5_max_dsp is
generic (
ID : integer := 23;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fmul_32ns_32ns_32_5_max_dsp is
--------------------- Component ---------------------
component tri_intersect_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fmul_3_max_dsp_32_u : component tri_intersect_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/synth/tri_intersect_ap_fdiv_28_no_dsp_32.vhd | 1 | 12676 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fdiv_28_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fdiv_28_no_dsp_32;
ARCHITECTURE tri_intersect_ap_fdiv_28_no_dsp_32_arch OF tri_intersect_ap_fdiv_28_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fdiv_28_no_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=28,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fdiv_28_no_dsp_32_arch;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd | 44 | 7144 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
| mit |
hhuang25/uwaterloo_ece224 | ANT - Copy/sdram_pll.vhd | 4 | 16139 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: sdram_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sdram_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END sdram_pll;
ARCHITECTURE SYN OF sdram_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "-3000",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=sdram_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/mult_gen_v12_0/hdl/mult_gen_v12_0.vhd | 13 | 9504 | `protect begin_protected
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`protect end_protected
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd | 13 | 153715 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 112048)
`protect data_block
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`protect end_protected
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/hdl/ip/tri_intersect_ap_fdiv_28_no_dsp_32.vhd | 3 | 12682 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fdiv_28_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fdiv_28_no_dsp_32;
ARCHITECTURE tri_intersect_ap_fdiv_28_no_dsp_32_arch OF tri_intersect_ap_fdiv_28_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fdiv_28_no_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=28,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fdiv_28_no_dsp_32_arch;
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 13 | 96005 | `protect begin_protected
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`protect end_protected
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/tri_intersect.vhd | 3 | 950495 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tri_intersect is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TID : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
outs_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of tri_intersect is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"tri_intersect,hls_ip_2015_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=463,HLS_SYN_TPT=none,HLS_SYN_MEM=32,HLS_SYN_DSP=127,HLS_SYN_FF=20827,HLS_SYN_LUT=27149}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st155_fsm_154 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st156_fsm_155 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st157_fsm_156 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st158_fsm_157 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st159_fsm_158 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st160_fsm_159 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st161_fsm_160 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st162_fsm_161 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st163_fsm_162 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st164_fsm_163 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st165_fsm_164 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st166_fsm_165 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st167_fsm_166 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st168_fsm_167 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st169_fsm_168 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st170_fsm_169 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st171_fsm_170 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st172_fsm_171 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st173_fsm_172 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st174_fsm_173 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st175_fsm_174 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st176_fsm_175 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st177_fsm_176 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st178_fsm_177 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st179_fsm_178 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st180_fsm_179 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st181_fsm_180 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st182_fsm_181 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st183_fsm_182 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st184_fsm_183 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st185_fsm_184 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st186_fsm_185 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st187_fsm_186 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st188_fsm_187 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st189_fsm_188 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st190_fsm_189 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st191_fsm_190 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st192_fsm_191 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st193_fsm_192 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st194_fsm_193 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st195_fsm_194 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st196_fsm_195 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st197_fsm_196 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st198_fsm_197 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st199_fsm_198 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st200_fsm_199 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st201_fsm_200 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st202_fsm_201 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st203_fsm_202 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st204_fsm_203 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st205_fsm_204 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st206_fsm_205 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st207_fsm_206 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st208_fsm_207 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st209_fsm_208 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st210_fsm_209 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st211_fsm_210 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st212_fsm_211 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st213_fsm_212 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st214_fsm_213 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st215_fsm_214 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st216_fsm_215 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st217_fsm_216 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st218_fsm_217 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st219_fsm_218 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st220_fsm_219 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st221_fsm_220 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st222_fsm_221 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st223_fsm_222 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st224_fsm_223 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st225_fsm_224 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st226_fsm_225 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st227_fsm_226 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st228_fsm_227 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st229_fsm_228 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st230_fsm_229 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st231_fsm_230 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st232_fsm_231 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st233_fsm_232 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st234_fsm_233 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st235_fsm_234 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st236_fsm_235 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st237_fsm_236 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st238_fsm_237 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st239_fsm_238 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st240_fsm_239 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st241_fsm_240 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st242_fsm_241 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st243_fsm_242 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st244_fsm_243 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st245_fsm_244 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st246_fsm_245 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st247_fsm_246 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st248_fsm_247 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st249_fsm_248 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st250_fsm_249 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st251_fsm_250 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st252_fsm_251 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st253_fsm_252 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st254_fsm_253 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st255_fsm_254 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st256_fsm_255 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st257_fsm_256 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st258_fsm_257 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st259_fsm_258 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st260_fsm_259 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st261_fsm_260 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st262_fsm_261 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st263_fsm_262 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st264_fsm_263 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st265_fsm_264 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st266_fsm_265 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st267_fsm_266 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st268_fsm_267 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st269_fsm_268 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st270_fsm_269 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st271_fsm_270 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st272_fsm_271 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st273_fsm_272 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st274_fsm_273 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st275_fsm_274 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st276_fsm_275 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st277_fsm_276 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st278_fsm_277 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st279_fsm_278 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st280_fsm_279 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st281_fsm_280 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st282_fsm_281 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st283_fsm_282 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st284_fsm_283 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st285_fsm_284 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st286_fsm_285 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st287_fsm_286 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st288_fsm_287 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st289_fsm_288 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st290_fsm_289 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st291_fsm_290 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st292_fsm_291 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st293_fsm_292 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st294_fsm_293 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st295_fsm_294 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st296_fsm_295 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st297_fsm_296 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st298_fsm_297 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st299_fsm_298 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st300_fsm_299 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_pp0_stg0_fsm_300 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st385_fsm_301 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st386_fsm_302 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st387_fsm_303 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st388_fsm_304 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st389_fsm_305 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st390_fsm_306 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st391_fsm_307 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st392_fsm_308 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st393_fsm_309 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st394_fsm_310 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st395_fsm_311 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st396_fsm_312 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st397_fsm_313 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st398_fsm_314 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st399_fsm_315 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st400_fsm_316 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st401_fsm_317 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st402_fsm_318 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st403_fsm_319 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st404_fsm_320 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st405_fsm_321 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st406_fsm_322 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st407_fsm_323 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st408_fsm_324 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st409_fsm_325 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st410_fsm_326 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st411_fsm_327 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st412_fsm_328 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st413_fsm_329 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st414_fsm_330 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st415_fsm_331 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st416_fsm_332 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st417_fsm_333 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st418_fsm_334 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st419_fsm_335 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st420_fsm_336 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st421_fsm_337 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st422_fsm_338 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st423_fsm_339 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st424_fsm_340 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st425_fsm_341 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st426_fsm_342 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st427_fsm_343 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st428_fsm_344 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st429_fsm_345 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st430_fsm_346 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st431_fsm_347 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st432_fsm_348 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st433_fsm_349 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st434_fsm_350 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st435_fsm_351 : STD_LOGIC_VECTOR (361 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st436_fsm_352 : STD_LOGIC_VECTOR (361 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st437_fsm_353 : STD_LOGIC_VECTOR (361 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st438_fsm_354 : STD_LOGIC_VECTOR (361 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st439_fsm_355 : STD_LOGIC_VECTOR (361 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st440_fsm_356 : STD_LOGIC_VECTOR (361 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st441_fsm_357 : STD_LOGIC_VECTOR (361 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st442_fsm_358 : STD_LOGIC_VECTOR (361 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st443_fsm_359 : STD_LOGIC_VECTOR (361 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st444_fsm_360 : STD_LOGIC_VECTOR (361 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st445_fsm_361 : STD_LOGIC_VECTOR (361 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_true : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
constant ap_const_lv32_4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001011";
constant ap_const_lv32_5A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011010";
constant ap_const_lv32_69 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101001";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_87 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000111";
constant ap_const_lv32_96 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010110";
constant ap_const_lv32_A5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100101";
constant ap_const_lv32_B4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110100";
constant ap_const_lv32_C3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000011";
constant ap_const_lv32_D2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010010";
constant ap_const_lv32_E1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100001";
constant ap_const_lv32_F0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_10E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001110";
constant ap_const_lv32_11D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011101";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_49 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001001";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_6A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101010";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_88 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001000";
constant ap_const_lv32_97 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010111";
constant ap_const_lv32_A6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100110";
constant ap_const_lv32_B5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110101";
constant ap_const_lv32_C4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000100";
constant ap_const_lv32_D3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010011";
constant ap_const_lv32_E2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100010";
constant ap_const_lv32_F1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110001";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_10F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001111";
constant ap_const_lv32_11E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_6B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101011";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_89 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001001";
constant ap_const_lv32_98 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011000";
constant ap_const_lv32_A7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100111";
constant ap_const_lv32_B6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110110";
constant ap_const_lv32_C5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000101";
constant ap_const_lv32_D4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010100";
constant ap_const_lv32_E3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100011";
constant ap_const_lv32_F2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110010";
constant ap_const_lv32_101 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000001";
constant ap_const_lv32_110 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv32_6C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101100";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_8A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001010";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv32_A8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101000";
constant ap_const_lv32_B7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110111";
constant ap_const_lv32_C6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000110";
constant ap_const_lv32_D5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010101";
constant ap_const_lv32_E4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100100";
constant ap_const_lv32_F3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110011";
constant ap_const_lv32_102 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000010";
constant ap_const_lv32_111 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010001";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_5E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011110";
constant ap_const_lv32_6D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101101";
constant ap_const_lv32_7C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111100";
constant ap_const_lv32_8B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001011";
constant ap_const_lv32_9A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011010";
constant ap_const_lv32_A9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101001";
constant ap_const_lv32_B8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111000";
constant ap_const_lv32_C7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000111";
constant ap_const_lv32_D6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010110";
constant ap_const_lv32_E5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100101";
constant ap_const_lv32_F4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110100";
constant ap_const_lv32_103 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000011";
constant ap_const_lv32_112 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010010";
constant ap_const_lv32_121 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100001";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_6E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101110";
constant ap_const_lv32_7D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111101";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_9B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011011";
constant ap_const_lv32_AA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101010";
constant ap_const_lv32_B9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111001";
constant ap_const_lv32_C8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001000";
constant ap_const_lv32_D7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010111";
constant ap_const_lv32_E6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100110";
constant ap_const_lv32_F5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110101";
constant ap_const_lv32_104 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000100";
constant ap_const_lv32_113 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010011";
constant ap_const_lv32_122 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100010";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_6F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101111";
constant ap_const_lv32_7E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111110";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv32_9C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011100";
constant ap_const_lv32_AB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101011";
constant ap_const_lv32_BA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111010";
constant ap_const_lv32_C9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001001";
constant ap_const_lv32_D8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011000";
constant ap_const_lv32_E7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100111";
constant ap_const_lv32_F6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110110";
constant ap_const_lv32_105 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000101";
constant ap_const_lv32_114 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010100";
constant ap_const_lv32_123 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100011";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_9D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011101";
constant ap_const_lv32_AC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101100";
constant ap_const_lv32_BB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111011";
constant ap_const_lv32_CA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001010";
constant ap_const_lv32_D9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011001";
constant ap_const_lv32_E8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101000";
constant ap_const_lv32_F7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110111";
constant ap_const_lv32_106 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000110";
constant ap_const_lv32_115 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010101";
constant ap_const_lv32_124 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv32_71 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110001";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv32_9E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011110";
constant ap_const_lv32_AD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101101";
constant ap_const_lv32_BC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111100";
constant ap_const_lv32_CB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001011";
constant ap_const_lv32_DA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011010";
constant ap_const_lv32_E9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101001";
constant ap_const_lv32_F8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111000";
constant ap_const_lv32_107 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000111";
constant ap_const_lv32_116 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010110";
constant ap_const_lv32_125 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100101";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_54 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010100";
constant ap_const_lv32_63 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100011";
constant ap_const_lv32_72 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110010";
constant ap_const_lv32_81 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000001";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_AE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101110";
constant ap_const_lv32_BD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111101";
constant ap_const_lv32_CC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001100";
constant ap_const_lv32_DB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011011";
constant ap_const_lv32_EA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101010";
constant ap_const_lv32_F9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111001";
constant ap_const_lv32_108 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001000";
constant ap_const_lv32_117 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010111";
constant ap_const_lv32_126 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100110";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
constant ap_const_lv32_64 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100100";
constant ap_const_lv32_73 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110011";
constant ap_const_lv32_82 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000010";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_AF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101111";
constant ap_const_lv32_BE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111110";
constant ap_const_lv32_CD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001101";
constant ap_const_lv32_DC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011100";
constant ap_const_lv32_EB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101011";
constant ap_const_lv32_FA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111010";
constant ap_const_lv32_109 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001001";
constant ap_const_lv32_118 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011000";
constant ap_const_lv32_127 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_65 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100101";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv32_83 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000011";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_A1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100001";
constant ap_const_lv32_B0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_CE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001110";
constant ap_const_lv32_DD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011101";
constant ap_const_lv32_EC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101100";
constant ap_const_lv32_FB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111011";
constant ap_const_lv32_10A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001010";
constant ap_const_lv32_119 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011001";
constant ap_const_lv32_128 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101000";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_66 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100110";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv32_84 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000100";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv32_A2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100010";
constant ap_const_lv32_B1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110001";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_CF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001111";
constant ap_const_lv32_DE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011110";
constant ap_const_lv32_ED : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101101";
constant ap_const_lv32_FC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111100";
constant ap_const_lv32_10B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001011";
constant ap_const_lv32_11A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011010";
constant ap_const_lv32_129 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101001";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_67 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100111";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_85 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000101";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_A3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100011";
constant ap_const_lv32_B2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110010";
constant ap_const_lv32_C1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000001";
constant ap_const_lv32_D0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_EE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101110";
constant ap_const_lv32_FD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111101";
constant ap_const_lv32_10C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001100";
constant ap_const_lv32_11B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011011";
constant ap_const_lv32_12A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101010";
constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
constant ap_const_lv32_12C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_12E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101110";
constant ap_const_lv32_131 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110001";
constant ap_const_lv32_134 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110100";
constant ap_const_lv32_137 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110111";
constant ap_const_lv32_13A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111010";
constant ap_const_lv32_13D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111101";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_143 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000011";
constant ap_const_lv32_146 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000110";
constant ap_const_lv32_149 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001001";
constant ap_const_lv32_14C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001100";
constant ap_const_lv32_14F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001111";
constant ap_const_lv32_152 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010010";
constant ap_const_lv32_155 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010101";
constant ap_const_lv32_158 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011000";
constant ap_const_lv32_15B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011011";
constant ap_const_lv32_15E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011110";
constant ap_const_lv32_161 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100001";
constant ap_const_lv32_164 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100100";
constant ap_const_lv32_167 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100111";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_41 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000001";
constant ap_const_lv32_42 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000010";
constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011";
constant ap_const_lv32_44 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000100";
constant ap_const_lv32_45 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000101";
constant ap_const_lv32_46 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000110";
constant ap_const_lv32_4A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001010";
constant ap_const_lv32_59 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011001";
constant ap_const_lv32_68 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101000";
constant ap_const_lv32_77 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110111";
constant ap_const_lv32_86 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000110";
constant ap_const_lv32_95 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010101";
constant ap_const_lv32_A4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100100";
constant ap_const_lv32_B3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110011";
constant ap_const_lv32_C2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000010";
constant ap_const_lv32_D1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010001";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_EF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101111";
constant ap_const_lv32_12B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101011";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_const_lv64_12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv64_11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010001";
constant ap_const_lv64_13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010011";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011";
constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101";
constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110";
constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111";
constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_const_lv64_9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001001";
constant ap_const_lv64_A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001010";
constant ap_const_lv64_B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001011";
constant ap_const_lv64_C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001100";
constant ap_const_lv64_D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001101";
constant ap_const_lv64_E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001110";
constant ap_const_lv64_F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001111";
constant ap_const_lv32_FE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111110";
constant ap_const_lv32_10D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001101";
constant ap_const_lv32_11C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011100";
constant ap_const_lv32_12F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101111";
constant ap_const_lv32_130 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110000";
constant ap_const_lv32_132 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110010";
constant ap_const_lv32_133 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110011";
constant ap_const_lv32_135 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110101";
constant ap_const_lv32_136 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110110";
constant ap_const_lv32_138 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111000";
constant ap_const_lv32_139 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111001";
constant ap_const_lv32_13B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111011";
constant ap_const_lv32_13C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111100";
constant ap_const_lv32_13E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111110";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_141 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000001";
constant ap_const_lv32_142 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000010";
constant ap_const_lv32_144 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000100";
constant ap_const_lv32_145 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000101";
constant ap_const_lv32_147 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000111";
constant ap_const_lv32_148 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001000";
constant ap_const_lv32_14A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001010";
constant ap_const_lv32_14B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001011";
constant ap_const_lv32_14D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001101";
constant ap_const_lv32_14E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001110";
constant ap_const_lv32_150 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010000";
constant ap_const_lv32_151 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010001";
constant ap_const_lv32_153 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010011";
constant ap_const_lv32_154 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010100";
constant ap_const_lv32_156 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010110";
constant ap_const_lv32_157 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010111";
constant ap_const_lv32_159 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011001";
constant ap_const_lv32_15A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011010";
constant ap_const_lv32_15C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011100";
constant ap_const_lv32_15D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011101";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_162 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100010";
constant ap_const_lv32_163 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100011";
constant ap_const_lv32_165 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100101";
constant ap_const_lv32_166 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100110";
constant ap_const_lv32_168 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101101000";
constant ap_const_lv32_169 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101101001";
constant ap_const_lv32_12D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101101";
constant ap_const_lv32_3F800000 : STD_LOGIC_VECTOR (31 downto 0) := "00111111100000000000000000000000";
constant ap_const_lv32_1E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111100000";
constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111";
constant ap_const_lv32_200 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000000000";
constant ap_const_lv32_21F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000011111";
constant ap_const_lv32_220 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000100000";
constant ap_const_lv32_23F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000111111";
constant ap_const_lv576_lc_1 : STD_LOGIC_VECTOR (575 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_1DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111011111";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv32_1A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110100000";
constant ap_const_lv32_1BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110111111";
constant ap_const_lv32_1C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111000000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal i1_reg_418 : STD_LOGIC_VECTOR (4 downto 0);
signal reg_669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_399 : BOOLEAN;
signal ap_sig_cseq_ST_st73_fsm_72 : STD_LOGIC;
signal ap_sig_bdd_410 : BOOLEAN;
signal ap_sig_cseq_ST_st76_fsm_75 : STD_LOGIC;
signal ap_sig_bdd_419 : BOOLEAN;
signal ap_sig_cseq_ST_st91_fsm_90 : STD_LOGIC;
signal ap_sig_bdd_428 : BOOLEAN;
signal ap_sig_cseq_ST_st106_fsm_105 : STD_LOGIC;
signal ap_sig_bdd_437 : BOOLEAN;
signal ap_sig_cseq_ST_st121_fsm_120 : STD_LOGIC;
signal ap_sig_bdd_446 : BOOLEAN;
signal ap_sig_cseq_ST_st136_fsm_135 : STD_LOGIC;
signal ap_sig_bdd_455 : BOOLEAN;
signal ap_sig_cseq_ST_st151_fsm_150 : STD_LOGIC;
signal ap_sig_bdd_464 : BOOLEAN;
signal ap_sig_cseq_ST_st166_fsm_165 : STD_LOGIC;
signal ap_sig_bdd_473 : BOOLEAN;
signal ap_sig_cseq_ST_st181_fsm_180 : STD_LOGIC;
signal ap_sig_bdd_482 : BOOLEAN;
signal ap_sig_cseq_ST_st196_fsm_195 : STD_LOGIC;
signal ap_sig_bdd_491 : BOOLEAN;
signal ap_sig_cseq_ST_st211_fsm_210 : STD_LOGIC;
signal ap_sig_bdd_500 : BOOLEAN;
signal ap_sig_cseq_ST_st226_fsm_225 : STD_LOGIC;
signal ap_sig_bdd_509 : BOOLEAN;
signal ap_sig_cseq_ST_st241_fsm_240 : STD_LOGIC;
signal ap_sig_bdd_518 : BOOLEAN;
signal ap_sig_cseq_ST_st256_fsm_255 : STD_LOGIC;
signal ap_sig_bdd_527 : BOOLEAN;
signal ap_sig_cseq_ST_st271_fsm_270 : STD_LOGIC;
signal ap_sig_bdd_536 : BOOLEAN;
signal ap_sig_cseq_ST_st286_fsm_285 : STD_LOGIC;
signal ap_sig_bdd_545 : BOOLEAN;
signal reg_673 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_555 : BOOLEAN;
signal ap_sig_cseq_ST_st74_fsm_73 : STD_LOGIC;
signal ap_sig_bdd_563 : BOOLEAN;
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_572 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_581 : BOOLEAN;
signal ap_sig_cseq_ST_st107_fsm_106 : STD_LOGIC;
signal ap_sig_bdd_590 : BOOLEAN;
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_599 : BOOLEAN;
signal ap_sig_cseq_ST_st137_fsm_136 : STD_LOGIC;
signal ap_sig_bdd_608 : BOOLEAN;
signal ap_sig_cseq_ST_st152_fsm_151 : STD_LOGIC;
signal ap_sig_bdd_617 : BOOLEAN;
signal ap_sig_cseq_ST_st167_fsm_166 : STD_LOGIC;
signal ap_sig_bdd_626 : BOOLEAN;
signal ap_sig_cseq_ST_st182_fsm_181 : STD_LOGIC;
signal ap_sig_bdd_635 : BOOLEAN;
signal ap_sig_cseq_ST_st197_fsm_196 : STD_LOGIC;
signal ap_sig_bdd_644 : BOOLEAN;
signal ap_sig_cseq_ST_st212_fsm_211 : STD_LOGIC;
signal ap_sig_bdd_653 : BOOLEAN;
signal ap_sig_cseq_ST_st227_fsm_226 : STD_LOGIC;
signal ap_sig_bdd_662 : BOOLEAN;
signal ap_sig_cseq_ST_st242_fsm_241 : STD_LOGIC;
signal ap_sig_bdd_671 : BOOLEAN;
signal ap_sig_cseq_ST_st257_fsm_256 : STD_LOGIC;
signal ap_sig_bdd_680 : BOOLEAN;
signal ap_sig_cseq_ST_st272_fsm_271 : STD_LOGIC;
signal ap_sig_bdd_689 : BOOLEAN;
signal ap_sig_cseq_ST_st287_fsm_286 : STD_LOGIC;
signal ap_sig_bdd_698 : BOOLEAN;
signal reg_677 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_708 : BOOLEAN;
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_716 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_725 : BOOLEAN;
signal ap_sig_cseq_ST_st108_fsm_107 : STD_LOGIC;
signal ap_sig_bdd_734 : BOOLEAN;
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_743 : BOOLEAN;
signal ap_sig_cseq_ST_st138_fsm_137 : STD_LOGIC;
signal ap_sig_bdd_752 : BOOLEAN;
signal ap_sig_cseq_ST_st153_fsm_152 : STD_LOGIC;
signal ap_sig_bdd_761 : BOOLEAN;
signal ap_sig_cseq_ST_st168_fsm_167 : STD_LOGIC;
signal ap_sig_bdd_770 : BOOLEAN;
signal ap_sig_cseq_ST_st183_fsm_182 : STD_LOGIC;
signal ap_sig_bdd_779 : BOOLEAN;
signal ap_sig_cseq_ST_st198_fsm_197 : STD_LOGIC;
signal ap_sig_bdd_788 : BOOLEAN;
signal ap_sig_cseq_ST_st213_fsm_212 : STD_LOGIC;
signal ap_sig_bdd_797 : BOOLEAN;
signal ap_sig_cseq_ST_st228_fsm_227 : STD_LOGIC;
signal ap_sig_bdd_806 : BOOLEAN;
signal ap_sig_cseq_ST_st243_fsm_242 : STD_LOGIC;
signal ap_sig_bdd_815 : BOOLEAN;
signal ap_sig_cseq_ST_st258_fsm_257 : STD_LOGIC;
signal ap_sig_bdd_824 : BOOLEAN;
signal ap_sig_cseq_ST_st273_fsm_272 : STD_LOGIC;
signal ap_sig_bdd_833 : BOOLEAN;
signal ap_sig_cseq_ST_st288_fsm_287 : STD_LOGIC;
signal ap_sig_bdd_842 : BOOLEAN;
signal reg_681 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_852 : BOOLEAN;
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_860 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_869 : BOOLEAN;
signal ap_sig_cseq_ST_st109_fsm_108 : STD_LOGIC;
signal ap_sig_bdd_878 : BOOLEAN;
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_887 : BOOLEAN;
signal ap_sig_cseq_ST_st139_fsm_138 : STD_LOGIC;
signal ap_sig_bdd_896 : BOOLEAN;
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_905 : BOOLEAN;
signal ap_sig_cseq_ST_st169_fsm_168 : STD_LOGIC;
signal ap_sig_bdd_914 : BOOLEAN;
signal ap_sig_cseq_ST_st184_fsm_183 : STD_LOGIC;
signal ap_sig_bdd_923 : BOOLEAN;
signal ap_sig_cseq_ST_st199_fsm_198 : STD_LOGIC;
signal ap_sig_bdd_932 : BOOLEAN;
signal ap_sig_cseq_ST_st214_fsm_213 : STD_LOGIC;
signal ap_sig_bdd_941 : BOOLEAN;
signal ap_sig_cseq_ST_st229_fsm_228 : STD_LOGIC;
signal ap_sig_bdd_950 : BOOLEAN;
signal ap_sig_cseq_ST_st244_fsm_243 : STD_LOGIC;
signal ap_sig_bdd_959 : BOOLEAN;
signal ap_sig_cseq_ST_st259_fsm_258 : STD_LOGIC;
signal ap_sig_bdd_968 : BOOLEAN;
signal ap_sig_cseq_ST_st274_fsm_273 : STD_LOGIC;
signal ap_sig_bdd_977 : BOOLEAN;
signal ap_sig_cseq_ST_st289_fsm_288 : STD_LOGIC;
signal ap_sig_bdd_986 : BOOLEAN;
signal reg_685 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_996 : BOOLEAN;
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_1004 : BOOLEAN;
signal ap_sig_cseq_ST_st95_fsm_94 : STD_LOGIC;
signal ap_sig_bdd_1013 : BOOLEAN;
signal ap_sig_cseq_ST_st110_fsm_109 : STD_LOGIC;
signal ap_sig_bdd_1022 : BOOLEAN;
signal ap_sig_cseq_ST_st125_fsm_124 : STD_LOGIC;
signal ap_sig_bdd_1031 : BOOLEAN;
signal ap_sig_cseq_ST_st140_fsm_139 : STD_LOGIC;
signal ap_sig_bdd_1040 : BOOLEAN;
signal ap_sig_cseq_ST_st155_fsm_154 : STD_LOGIC;
signal ap_sig_bdd_1049 : BOOLEAN;
signal ap_sig_cseq_ST_st170_fsm_169 : STD_LOGIC;
signal ap_sig_bdd_1058 : BOOLEAN;
signal ap_sig_cseq_ST_st185_fsm_184 : STD_LOGIC;
signal ap_sig_bdd_1067 : BOOLEAN;
signal ap_sig_cseq_ST_st200_fsm_199 : STD_LOGIC;
signal ap_sig_bdd_1076 : BOOLEAN;
signal ap_sig_cseq_ST_st215_fsm_214 : STD_LOGIC;
signal ap_sig_bdd_1085 : BOOLEAN;
signal ap_sig_cseq_ST_st230_fsm_229 : STD_LOGIC;
signal ap_sig_bdd_1094 : BOOLEAN;
signal ap_sig_cseq_ST_st245_fsm_244 : STD_LOGIC;
signal ap_sig_bdd_1103 : BOOLEAN;
signal ap_sig_cseq_ST_st260_fsm_259 : STD_LOGIC;
signal ap_sig_bdd_1112 : BOOLEAN;
signal ap_sig_cseq_ST_st275_fsm_274 : STD_LOGIC;
signal ap_sig_bdd_1121 : BOOLEAN;
signal ap_sig_cseq_ST_st290_fsm_289 : STD_LOGIC;
signal ap_sig_bdd_1130 : BOOLEAN;
signal reg_689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_1140 : BOOLEAN;
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_1148 : BOOLEAN;
signal ap_sig_cseq_ST_st96_fsm_95 : STD_LOGIC;
signal ap_sig_bdd_1157 : BOOLEAN;
signal ap_sig_cseq_ST_st111_fsm_110 : STD_LOGIC;
signal ap_sig_bdd_1166 : BOOLEAN;
signal ap_sig_cseq_ST_st126_fsm_125 : STD_LOGIC;
signal ap_sig_bdd_1175 : BOOLEAN;
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_1184 : BOOLEAN;
signal ap_sig_cseq_ST_st156_fsm_155 : STD_LOGIC;
signal ap_sig_bdd_1193 : BOOLEAN;
signal ap_sig_cseq_ST_st171_fsm_170 : STD_LOGIC;
signal ap_sig_bdd_1202 : BOOLEAN;
signal ap_sig_cseq_ST_st186_fsm_185 : STD_LOGIC;
signal ap_sig_bdd_1211 : BOOLEAN;
signal ap_sig_cseq_ST_st201_fsm_200 : STD_LOGIC;
signal ap_sig_bdd_1220 : BOOLEAN;
signal ap_sig_cseq_ST_st216_fsm_215 : STD_LOGIC;
signal ap_sig_bdd_1229 : BOOLEAN;
signal ap_sig_cseq_ST_st231_fsm_230 : STD_LOGIC;
signal ap_sig_bdd_1238 : BOOLEAN;
signal ap_sig_cseq_ST_st246_fsm_245 : STD_LOGIC;
signal ap_sig_bdd_1247 : BOOLEAN;
signal ap_sig_cseq_ST_st261_fsm_260 : STD_LOGIC;
signal ap_sig_bdd_1256 : BOOLEAN;
signal ap_sig_cseq_ST_st276_fsm_275 : STD_LOGIC;
signal ap_sig_bdd_1265 : BOOLEAN;
signal ap_sig_cseq_ST_st291_fsm_290 : STD_LOGIC;
signal ap_sig_bdd_1274 : BOOLEAN;
signal reg_693 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_1284 : BOOLEAN;
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_1292 : BOOLEAN;
signal ap_sig_cseq_ST_st97_fsm_96 : STD_LOGIC;
signal ap_sig_bdd_1301 : BOOLEAN;
signal ap_sig_cseq_ST_st112_fsm_111 : STD_LOGIC;
signal ap_sig_bdd_1310 : BOOLEAN;
signal ap_sig_cseq_ST_st127_fsm_126 : STD_LOGIC;
signal ap_sig_bdd_1319 : BOOLEAN;
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_1328 : BOOLEAN;
signal ap_sig_cseq_ST_st157_fsm_156 : STD_LOGIC;
signal ap_sig_bdd_1337 : BOOLEAN;
signal ap_sig_cseq_ST_st172_fsm_171 : STD_LOGIC;
signal ap_sig_bdd_1346 : BOOLEAN;
signal ap_sig_cseq_ST_st187_fsm_186 : STD_LOGIC;
signal ap_sig_bdd_1355 : BOOLEAN;
signal ap_sig_cseq_ST_st202_fsm_201 : STD_LOGIC;
signal ap_sig_bdd_1364 : BOOLEAN;
signal ap_sig_cseq_ST_st217_fsm_216 : STD_LOGIC;
signal ap_sig_bdd_1373 : BOOLEAN;
signal ap_sig_cseq_ST_st232_fsm_231 : STD_LOGIC;
signal ap_sig_bdd_1382 : BOOLEAN;
signal ap_sig_cseq_ST_st247_fsm_246 : STD_LOGIC;
signal ap_sig_bdd_1391 : BOOLEAN;
signal ap_sig_cseq_ST_st262_fsm_261 : STD_LOGIC;
signal ap_sig_bdd_1400 : BOOLEAN;
signal ap_sig_cseq_ST_st277_fsm_276 : STD_LOGIC;
signal ap_sig_bdd_1409 : BOOLEAN;
signal ap_sig_cseq_ST_st292_fsm_291 : STD_LOGIC;
signal ap_sig_bdd_1418 : BOOLEAN;
signal reg_697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_1428 : BOOLEAN;
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_1436 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_1445 : BOOLEAN;
signal ap_sig_cseq_ST_st113_fsm_112 : STD_LOGIC;
signal ap_sig_bdd_1454 : BOOLEAN;
signal ap_sig_cseq_ST_st128_fsm_127 : STD_LOGIC;
signal ap_sig_bdd_1463 : BOOLEAN;
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_1472 : BOOLEAN;
signal ap_sig_cseq_ST_st158_fsm_157 : STD_LOGIC;
signal ap_sig_bdd_1481 : BOOLEAN;
signal ap_sig_cseq_ST_st173_fsm_172 : STD_LOGIC;
signal ap_sig_bdd_1490 : BOOLEAN;
signal ap_sig_cseq_ST_st188_fsm_187 : STD_LOGIC;
signal ap_sig_bdd_1499 : BOOLEAN;
signal ap_sig_cseq_ST_st203_fsm_202 : STD_LOGIC;
signal ap_sig_bdd_1508 : BOOLEAN;
signal ap_sig_cseq_ST_st218_fsm_217 : STD_LOGIC;
signal ap_sig_bdd_1517 : BOOLEAN;
signal ap_sig_cseq_ST_st233_fsm_232 : STD_LOGIC;
signal ap_sig_bdd_1526 : BOOLEAN;
signal ap_sig_cseq_ST_st248_fsm_247 : STD_LOGIC;
signal ap_sig_bdd_1535 : BOOLEAN;
signal ap_sig_cseq_ST_st263_fsm_262 : STD_LOGIC;
signal ap_sig_bdd_1544 : BOOLEAN;
signal ap_sig_cseq_ST_st278_fsm_277 : STD_LOGIC;
signal ap_sig_bdd_1553 : BOOLEAN;
signal ap_sig_cseq_ST_st293_fsm_292 : STD_LOGIC;
signal ap_sig_bdd_1562 : BOOLEAN;
signal reg_701 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_1572 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_1580 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_1589 : BOOLEAN;
signal ap_sig_cseq_ST_st114_fsm_113 : STD_LOGIC;
signal ap_sig_bdd_1598 : BOOLEAN;
signal ap_sig_cseq_ST_st129_fsm_128 : STD_LOGIC;
signal ap_sig_bdd_1607 : BOOLEAN;
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_1616 : BOOLEAN;
signal ap_sig_cseq_ST_st159_fsm_158 : STD_LOGIC;
signal ap_sig_bdd_1625 : BOOLEAN;
signal ap_sig_cseq_ST_st174_fsm_173 : STD_LOGIC;
signal ap_sig_bdd_1634 : BOOLEAN;
signal ap_sig_cseq_ST_st189_fsm_188 : STD_LOGIC;
signal ap_sig_bdd_1643 : BOOLEAN;
signal ap_sig_cseq_ST_st204_fsm_203 : STD_LOGIC;
signal ap_sig_bdd_1652 : BOOLEAN;
signal ap_sig_cseq_ST_st219_fsm_218 : STD_LOGIC;
signal ap_sig_bdd_1661 : BOOLEAN;
signal ap_sig_cseq_ST_st234_fsm_233 : STD_LOGIC;
signal ap_sig_bdd_1670 : BOOLEAN;
signal ap_sig_cseq_ST_st249_fsm_248 : STD_LOGIC;
signal ap_sig_bdd_1679 : BOOLEAN;
signal ap_sig_cseq_ST_st264_fsm_263 : STD_LOGIC;
signal ap_sig_bdd_1688 : BOOLEAN;
signal ap_sig_cseq_ST_st279_fsm_278 : STD_LOGIC;
signal ap_sig_bdd_1697 : BOOLEAN;
signal ap_sig_cseq_ST_st294_fsm_293 : STD_LOGIC;
signal ap_sig_bdd_1706 : BOOLEAN;
signal reg_705 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_1716 : BOOLEAN;
signal ap_sig_cseq_ST_st85_fsm_84 : STD_LOGIC;
signal ap_sig_bdd_1724 : BOOLEAN;
signal ap_sig_cseq_ST_st100_fsm_99 : STD_LOGIC;
signal ap_sig_bdd_1733 : BOOLEAN;
signal ap_sig_cseq_ST_st115_fsm_114 : STD_LOGIC;
signal ap_sig_bdd_1742 : BOOLEAN;
signal ap_sig_cseq_ST_st130_fsm_129 : STD_LOGIC;
signal ap_sig_bdd_1751 : BOOLEAN;
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_1760 : BOOLEAN;
signal ap_sig_cseq_ST_st160_fsm_159 : STD_LOGIC;
signal ap_sig_bdd_1769 : BOOLEAN;
signal ap_sig_cseq_ST_st175_fsm_174 : STD_LOGIC;
signal ap_sig_bdd_1778 : BOOLEAN;
signal ap_sig_cseq_ST_st190_fsm_189 : STD_LOGIC;
signal ap_sig_bdd_1787 : BOOLEAN;
signal ap_sig_cseq_ST_st205_fsm_204 : STD_LOGIC;
signal ap_sig_bdd_1796 : BOOLEAN;
signal ap_sig_cseq_ST_st220_fsm_219 : STD_LOGIC;
signal ap_sig_bdd_1805 : BOOLEAN;
signal ap_sig_cseq_ST_st235_fsm_234 : STD_LOGIC;
signal ap_sig_bdd_1814 : BOOLEAN;
signal ap_sig_cseq_ST_st250_fsm_249 : STD_LOGIC;
signal ap_sig_bdd_1823 : BOOLEAN;
signal ap_sig_cseq_ST_st265_fsm_264 : STD_LOGIC;
signal ap_sig_bdd_1832 : BOOLEAN;
signal ap_sig_cseq_ST_st280_fsm_279 : STD_LOGIC;
signal ap_sig_bdd_1841 : BOOLEAN;
signal ap_sig_cseq_ST_st295_fsm_294 : STD_LOGIC;
signal ap_sig_bdd_1850 : BOOLEAN;
signal reg_709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_1860 : BOOLEAN;
signal ap_sig_cseq_ST_st86_fsm_85 : STD_LOGIC;
signal ap_sig_bdd_1868 : BOOLEAN;
signal ap_sig_cseq_ST_st101_fsm_100 : STD_LOGIC;
signal ap_sig_bdd_1877 : BOOLEAN;
signal ap_sig_cseq_ST_st116_fsm_115 : STD_LOGIC;
signal ap_sig_bdd_1886 : BOOLEAN;
signal ap_sig_cseq_ST_st131_fsm_130 : STD_LOGIC;
signal ap_sig_bdd_1895 : BOOLEAN;
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_1904 : BOOLEAN;
signal ap_sig_cseq_ST_st161_fsm_160 : STD_LOGIC;
signal ap_sig_bdd_1913 : BOOLEAN;
signal ap_sig_cseq_ST_st176_fsm_175 : STD_LOGIC;
signal ap_sig_bdd_1922 : BOOLEAN;
signal ap_sig_cseq_ST_st191_fsm_190 : STD_LOGIC;
signal ap_sig_bdd_1931 : BOOLEAN;
signal ap_sig_cseq_ST_st206_fsm_205 : STD_LOGIC;
signal ap_sig_bdd_1940 : BOOLEAN;
signal ap_sig_cseq_ST_st221_fsm_220 : STD_LOGIC;
signal ap_sig_bdd_1949 : BOOLEAN;
signal ap_sig_cseq_ST_st236_fsm_235 : STD_LOGIC;
signal ap_sig_bdd_1958 : BOOLEAN;
signal ap_sig_cseq_ST_st251_fsm_250 : STD_LOGIC;
signal ap_sig_bdd_1967 : BOOLEAN;
signal ap_sig_cseq_ST_st266_fsm_265 : STD_LOGIC;
signal ap_sig_bdd_1976 : BOOLEAN;
signal ap_sig_cseq_ST_st281_fsm_280 : STD_LOGIC;
signal ap_sig_bdd_1985 : BOOLEAN;
signal ap_sig_cseq_ST_st296_fsm_295 : STD_LOGIC;
signal ap_sig_bdd_1994 : BOOLEAN;
signal reg_713 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_2004 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_2012 : BOOLEAN;
signal ap_sig_cseq_ST_st102_fsm_101 : STD_LOGIC;
signal ap_sig_bdd_2021 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_2030 : BOOLEAN;
signal ap_sig_cseq_ST_st132_fsm_131 : STD_LOGIC;
signal ap_sig_bdd_2039 : BOOLEAN;
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_2048 : BOOLEAN;
signal ap_sig_cseq_ST_st162_fsm_161 : STD_LOGIC;
signal ap_sig_bdd_2057 : BOOLEAN;
signal ap_sig_cseq_ST_st177_fsm_176 : STD_LOGIC;
signal ap_sig_bdd_2066 : BOOLEAN;
signal ap_sig_cseq_ST_st192_fsm_191 : STD_LOGIC;
signal ap_sig_bdd_2075 : BOOLEAN;
signal ap_sig_cseq_ST_st207_fsm_206 : STD_LOGIC;
signal ap_sig_bdd_2084 : BOOLEAN;
signal ap_sig_cseq_ST_st222_fsm_221 : STD_LOGIC;
signal ap_sig_bdd_2093 : BOOLEAN;
signal ap_sig_cseq_ST_st237_fsm_236 : STD_LOGIC;
signal ap_sig_bdd_2102 : BOOLEAN;
signal ap_sig_cseq_ST_st252_fsm_251 : STD_LOGIC;
signal ap_sig_bdd_2111 : BOOLEAN;
signal ap_sig_cseq_ST_st267_fsm_266 : STD_LOGIC;
signal ap_sig_bdd_2120 : BOOLEAN;
signal ap_sig_cseq_ST_st282_fsm_281 : STD_LOGIC;
signal ap_sig_bdd_2129 : BOOLEAN;
signal ap_sig_cseq_ST_st297_fsm_296 : STD_LOGIC;
signal ap_sig_bdd_2138 : BOOLEAN;
signal reg_717 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_2148 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_2156 : BOOLEAN;
signal ap_sig_cseq_ST_st103_fsm_102 : STD_LOGIC;
signal ap_sig_bdd_2165 : BOOLEAN;
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_2174 : BOOLEAN;
signal ap_sig_cseq_ST_st133_fsm_132 : STD_LOGIC;
signal ap_sig_bdd_2183 : BOOLEAN;
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_2192 : BOOLEAN;
signal ap_sig_cseq_ST_st163_fsm_162 : STD_LOGIC;
signal ap_sig_bdd_2201 : BOOLEAN;
signal ap_sig_cseq_ST_st178_fsm_177 : STD_LOGIC;
signal ap_sig_bdd_2210 : BOOLEAN;
signal ap_sig_cseq_ST_st193_fsm_192 : STD_LOGIC;
signal ap_sig_bdd_2219 : BOOLEAN;
signal ap_sig_cseq_ST_st208_fsm_207 : STD_LOGIC;
signal ap_sig_bdd_2228 : BOOLEAN;
signal ap_sig_cseq_ST_st223_fsm_222 : STD_LOGIC;
signal ap_sig_bdd_2237 : BOOLEAN;
signal ap_sig_cseq_ST_st238_fsm_237 : STD_LOGIC;
signal ap_sig_bdd_2246 : BOOLEAN;
signal ap_sig_cseq_ST_st253_fsm_252 : STD_LOGIC;
signal ap_sig_bdd_2255 : BOOLEAN;
signal ap_sig_cseq_ST_st268_fsm_267 : STD_LOGIC;
signal ap_sig_bdd_2264 : BOOLEAN;
signal ap_sig_cseq_ST_st283_fsm_282 : STD_LOGIC;
signal ap_sig_bdd_2273 : BOOLEAN;
signal ap_sig_cseq_ST_st298_fsm_297 : STD_LOGIC;
signal ap_sig_bdd_2282 : BOOLEAN;
signal reg_721 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_2292 : BOOLEAN;
signal ap_sig_cseq_ST_st89_fsm_88 : STD_LOGIC;
signal ap_sig_bdd_2300 : BOOLEAN;
signal ap_sig_cseq_ST_st104_fsm_103 : STD_LOGIC;
signal ap_sig_bdd_2309 : BOOLEAN;
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_2318 : BOOLEAN;
signal ap_sig_cseq_ST_st134_fsm_133 : STD_LOGIC;
signal ap_sig_bdd_2327 : BOOLEAN;
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_2336 : BOOLEAN;
signal ap_sig_cseq_ST_st164_fsm_163 : STD_LOGIC;
signal ap_sig_bdd_2345 : BOOLEAN;
signal ap_sig_cseq_ST_st179_fsm_178 : STD_LOGIC;
signal ap_sig_bdd_2354 : BOOLEAN;
signal ap_sig_cseq_ST_st194_fsm_193 : STD_LOGIC;
signal ap_sig_bdd_2363 : BOOLEAN;
signal ap_sig_cseq_ST_st209_fsm_208 : STD_LOGIC;
signal ap_sig_bdd_2372 : BOOLEAN;
signal ap_sig_cseq_ST_st224_fsm_223 : STD_LOGIC;
signal ap_sig_bdd_2381 : BOOLEAN;
signal ap_sig_cseq_ST_st239_fsm_238 : STD_LOGIC;
signal ap_sig_bdd_2390 : BOOLEAN;
signal ap_sig_cseq_ST_st254_fsm_253 : STD_LOGIC;
signal ap_sig_bdd_2399 : BOOLEAN;
signal ap_sig_cseq_ST_st269_fsm_268 : STD_LOGIC;
signal ap_sig_bdd_2408 : BOOLEAN;
signal ap_sig_cseq_ST_st284_fsm_283 : STD_LOGIC;
signal ap_sig_bdd_2417 : BOOLEAN;
signal ap_sig_cseq_ST_st299_fsm_298 : STD_LOGIC;
signal ap_sig_bdd_2426 : BOOLEAN;
signal data_array_q0 : STD_LOGIC_VECTOR (575 downto 0);
signal reg_725 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_st72_fsm_71 : STD_LOGIC;
signal ap_sig_bdd_2437 : BOOLEAN;
signal ap_reg_ppstg_reg_725_pp0_it2 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it27 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it28 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it29 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it30 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it31 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it32 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it33 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it34 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it35 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it36 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it37 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it38 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it39 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it40 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it41 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it42 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it43 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it44 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it45 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it46 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it47 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it48 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it49 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it50 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it51 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it52 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it53 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it54 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it55 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it56 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it57 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it58 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it59 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it60 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it61 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it62 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it63 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it64 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it65 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it66 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it67 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it68 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it69 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it70 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it71 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it72 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it73 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it74 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it75 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it76 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it77 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it78 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it79 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it80 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it81 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it82 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it83 : STD_LOGIC := '0';
signal ap_reg_ppstg_reg_725_pp0_it3 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it4 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it6 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it7 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it8 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it9 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it10 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it11 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it12 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it13 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it14 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it15 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it16 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it17 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it18 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it19 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it20 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it21 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it22 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it23 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it24 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it25 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it26 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it27 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it28 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it29 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it30 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it31 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it32 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it33 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it34 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it35 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it36 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it37 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it38 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it39 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it40 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it41 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it42 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it43 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it44 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it45 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it46 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it47 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it48 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it49 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it50 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it51 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it52 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it53 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it54 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it55 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it56 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it57 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it58 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it59 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it60 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it61 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it62 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it63 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it64 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it65 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it66 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it67 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it68 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it69 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it70 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it71 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it72 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it73 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it74 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it75 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it76 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it77 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it78 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it79 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it80 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it81 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_300 : STD_LOGIC;
signal ap_sig_bdd_2694 : BOOLEAN;
signal exitcond2_reg_3854 : STD_LOGIC_VECTOR (0 downto 0);
signal reg_729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st386_fsm_302 : STD_LOGIC;
signal ap_sig_bdd_2708 : BOOLEAN;
signal ap_sig_ioackin_outs_TREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st389_fsm_305 : STD_LOGIC;
signal ap_sig_bdd_2719 : BOOLEAN;
signal ap_sig_cseq_ST_st392_fsm_308 : STD_LOGIC;
signal ap_sig_bdd_2728 : BOOLEAN;
signal ap_sig_cseq_ST_st395_fsm_311 : STD_LOGIC;
signal ap_sig_bdd_2737 : BOOLEAN;
signal ap_sig_cseq_ST_st398_fsm_314 : STD_LOGIC;
signal ap_sig_bdd_2746 : BOOLEAN;
signal ap_sig_cseq_ST_st401_fsm_317 : STD_LOGIC;
signal ap_sig_bdd_2755 : BOOLEAN;
signal ap_sig_cseq_ST_st404_fsm_320 : STD_LOGIC;
signal ap_sig_bdd_2764 : BOOLEAN;
signal ap_sig_cseq_ST_st407_fsm_323 : STD_LOGIC;
signal ap_sig_bdd_2773 : BOOLEAN;
signal ap_sig_cseq_ST_st410_fsm_326 : STD_LOGIC;
signal ap_sig_bdd_2782 : BOOLEAN;
signal ap_sig_cseq_ST_st413_fsm_329 : STD_LOGIC;
signal ap_sig_bdd_2791 : BOOLEAN;
signal ap_sig_cseq_ST_st416_fsm_332 : STD_LOGIC;
signal ap_sig_bdd_2800 : BOOLEAN;
signal ap_sig_cseq_ST_st419_fsm_335 : STD_LOGIC;
signal ap_sig_bdd_2809 : BOOLEAN;
signal ap_sig_cseq_ST_st422_fsm_338 : STD_LOGIC;
signal ap_sig_bdd_2818 : BOOLEAN;
signal ap_sig_cseq_ST_st425_fsm_341 : STD_LOGIC;
signal ap_sig_bdd_2827 : BOOLEAN;
signal ap_sig_cseq_ST_st428_fsm_344 : STD_LOGIC;
signal ap_sig_bdd_2836 : BOOLEAN;
signal ap_sig_cseq_ST_st431_fsm_347 : STD_LOGIC;
signal ap_sig_bdd_2845 : BOOLEAN;
signal ap_sig_cseq_ST_st434_fsm_350 : STD_LOGIC;
signal ap_sig_bdd_2854 : BOOLEAN;
signal ap_sig_cseq_ST_st437_fsm_353 : STD_LOGIC;
signal ap_sig_bdd_2863 : BOOLEAN;
signal ap_sig_cseq_ST_st440_fsm_356 : STD_LOGIC;
signal ap_sig_bdd_2872 : BOOLEAN;
signal ap_sig_cseq_ST_st443_fsm_359 : STD_LOGIC;
signal ap_sig_bdd_2881 : BOOLEAN;
signal reg_733 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_val14_reg_3415 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_2893 : BOOLEAN;
signal ins_data_val15_reg_3420 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_2902 : BOOLEAN;
signal ins_data_val16_reg_3425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_2911 : BOOLEAN;
signal ins_data_val17_reg_3430 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_2920 : BOOLEAN;
signal ins_data_val18_reg_3435 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_2929 : BOOLEAN;
signal ins_data_val19_reg_3440 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_2938 : BOOLEAN;
signal ins_data_val20_reg_3445 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_2947 : BOOLEAN;
signal ins_data_val21_reg_3450 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_2956 : BOOLEAN;
signal ins_data_val22_reg_3455 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_2965 : BOOLEAN;
signal ins_data_val23_reg_3460 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_2974 : BOOLEAN;
signal ins_data_val24_reg_3465 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_2983 : BOOLEAN;
signal ins_data_val25_reg_3470 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st26_fsm_25 : STD_LOGIC;
signal ap_sig_bdd_2992 : BOOLEAN;
signal ins_data_val26_reg_3475 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st27_fsm_26 : STD_LOGIC;
signal ap_sig_bdd_3001 : BOOLEAN;
signal ins_data_val27_reg_3480 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st28_fsm_27 : STD_LOGIC;
signal ap_sig_bdd_3010 : BOOLEAN;
signal ins_data_val28_reg_3485 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_3019 : BOOLEAN;
signal ins_data_val29_reg_3490 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_3028 : BOOLEAN;
signal ins_data_val30_reg_3495 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st31_fsm_30 : STD_LOGIC;
signal ap_sig_bdd_3037 : BOOLEAN;
signal ins_data_val31_reg_3500 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st32_fsm_31 : STD_LOGIC;
signal ap_sig_bdd_3046 : BOOLEAN;
signal ins_data_val32_reg_3505 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st33_fsm_32 : STD_LOGIC;
signal ap_sig_bdd_3055 : BOOLEAN;
signal ins_data_val33_reg_3510 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st34_fsm_33 : STD_LOGIC;
signal ap_sig_bdd_3064 : BOOLEAN;
signal ins_data_val34_reg_3515 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st35_fsm_34 : STD_LOGIC;
signal ap_sig_bdd_3073 : BOOLEAN;
signal ins_data_val35_reg_3520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st36_fsm_35 : STD_LOGIC;
signal ap_sig_bdd_3082 : BOOLEAN;
signal ins_data_val36_reg_3525 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st37_fsm_36 : STD_LOGIC;
signal ap_sig_bdd_3091 : BOOLEAN;
signal ins_data_val37_reg_3530 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st38_fsm_37 : STD_LOGIC;
signal ap_sig_bdd_3100 : BOOLEAN;
signal ins_data_val38_reg_3535 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st39_fsm_38 : STD_LOGIC;
signal ap_sig_bdd_3109 : BOOLEAN;
signal ins_data_val39_reg_3540 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st40_fsm_39 : STD_LOGIC;
signal ap_sig_bdd_3118 : BOOLEAN;
signal ins_data_val40_reg_3545 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_3127 : BOOLEAN;
signal ins_data_val41_reg_3550 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st42_fsm_41 : STD_LOGIC;
signal ap_sig_bdd_3136 : BOOLEAN;
signal ins_data_val42_reg_3555 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st43_fsm_42 : STD_LOGIC;
signal ap_sig_bdd_3145 : BOOLEAN;
signal ins_data_val43_reg_3560 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st44_fsm_43 : STD_LOGIC;
signal ap_sig_bdd_3154 : BOOLEAN;
signal ins_data_val44_reg_3565 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st45_fsm_44 : STD_LOGIC;
signal ap_sig_bdd_3163 : BOOLEAN;
signal ins_data_val45_reg_3570 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_3172 : BOOLEAN;
signal ins_data_val46_reg_3575 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st47_fsm_46 : STD_LOGIC;
signal ap_sig_bdd_3181 : BOOLEAN;
signal ins_data_val47_reg_3580 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st48_fsm_47 : STD_LOGIC;
signal ap_sig_bdd_3190 : BOOLEAN;
signal ins_data_val48_reg_3585 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st49_fsm_48 : STD_LOGIC;
signal ap_sig_bdd_3199 : BOOLEAN;
signal ins_data_val49_reg_3590 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st50_fsm_49 : STD_LOGIC;
signal ap_sig_bdd_3208 : BOOLEAN;
signal ins_data_val50_reg_3595 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st51_fsm_50 : STD_LOGIC;
signal ap_sig_bdd_3217 : BOOLEAN;
signal ins_data_val51_reg_3600 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st52_fsm_51 : STD_LOGIC;
signal ap_sig_bdd_3226 : BOOLEAN;
signal ins_data_val52_reg_3605 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st53_fsm_52 : STD_LOGIC;
signal ap_sig_bdd_3235 : BOOLEAN;
signal ins_data_val53_reg_3610 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st54_fsm_53 : STD_LOGIC;
signal ap_sig_bdd_3244 : BOOLEAN;
signal ins_data_val54_reg_3615 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st55_fsm_54 : STD_LOGIC;
signal ap_sig_bdd_3253 : BOOLEAN;
signal ins_data_val55_reg_3620 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st56_fsm_55 : STD_LOGIC;
signal ap_sig_bdd_3262 : BOOLEAN;
signal ins_data_val56_reg_3625 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st57_fsm_56 : STD_LOGIC;
signal ap_sig_bdd_3271 : BOOLEAN;
signal ins_data_val57_reg_3630 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st58_fsm_57 : STD_LOGIC;
signal ap_sig_bdd_3280 : BOOLEAN;
signal ins_data_val58_reg_3635 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st59_fsm_58 : STD_LOGIC;
signal ap_sig_bdd_3289 : BOOLEAN;
signal ins_data_val59_reg_3640 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st60_fsm_59 : STD_LOGIC;
signal ap_sig_bdd_3298 : BOOLEAN;
signal ins_data_val60_reg_3645 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st61_fsm_60 : STD_LOGIC;
signal ap_sig_bdd_3307 : BOOLEAN;
signal ins_data_val61_reg_3650 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st62_fsm_61 : STD_LOGIC;
signal ap_sig_bdd_3316 : BOOLEAN;
signal ins_data_val62_reg_3655 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st63_fsm_62 : STD_LOGIC;
signal ap_sig_bdd_3325 : BOOLEAN;
signal ins_data_val63_reg_3660 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st64_fsm_63 : STD_LOGIC;
signal ap_sig_bdd_3334 : BOOLEAN;
signal ins_data_val64_reg_3665 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st65_fsm_64 : STD_LOGIC;
signal ap_sig_bdd_3343 : BOOLEAN;
signal ins_data_val65_reg_3670 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st66_fsm_65 : STD_LOGIC;
signal ap_sig_bdd_3352 : BOOLEAN;
signal ins_data_val66_reg_3675 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st67_fsm_66 : STD_LOGIC;
signal ap_sig_bdd_3361 : BOOLEAN;
signal ins_data_val67_reg_3680 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st68_fsm_67 : STD_LOGIC;
signal ap_sig_bdd_3370 : BOOLEAN;
signal ins_data_val68_reg_3685 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st69_fsm_68 : STD_LOGIC;
signal ap_sig_bdd_3379 : BOOLEAN;
signal ins_data_val69_reg_3690 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st70_fsm_69 : STD_LOGIC;
signal ap_sig_bdd_3388 : BOOLEAN;
signal ins_data_val70_reg_3695 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st71_fsm_70 : STD_LOGIC;
signal ap_sig_bdd_3397 : BOOLEAN;
signal data_array_addr_16_gep_fu_244_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_16_reg_3700 : STD_LOGIC_VECTOR (4 downto 0);
signal ins_data_val71_reg_3706 : STD_LOGIC_VECTOR (31 downto 0);
signal data_array_addr_18_gep_fu_256_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_18_reg_3711 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_gep_fu_264_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_reg_3717 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_load_2_reg_3722 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_addr_2_gep_fu_272_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_2_reg_3727 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_4_gep_fu_280_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_4_reg_3732 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st75_fsm_74 : STD_LOGIC;
signal ap_sig_bdd_3417 : BOOLEAN;
signal data_array_addr_17_gep_fu_288_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_17_reg_3737 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_load_1_reg_3743 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_addr_19_gep_fu_296_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_19_reg_3748 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_1_gep_fu_304_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_1_reg_3754 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_load_3_reg_3759 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_addr_3_gep_fu_312_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_3_reg_3764 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_5_gep_fu_320_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_5_reg_3769 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st90_fsm_89 : STD_LOGIC;
signal ap_sig_bdd_3437 : BOOLEAN;
signal data_array_addr_6_gep_fu_328_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_6_reg_3774 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st105_fsm_104 : STD_LOGIC;
signal ap_sig_bdd_3447 : BOOLEAN;
signal data_array_addr_7_gep_fu_336_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_7_reg_3779 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st120_fsm_119 : STD_LOGIC;
signal ap_sig_bdd_3457 : BOOLEAN;
signal data_array_addr_8_gep_fu_344_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_8_reg_3784 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st135_fsm_134 : STD_LOGIC;
signal ap_sig_bdd_3467 : BOOLEAN;
signal data_array_addr_9_gep_fu_352_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_9_reg_3789 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st150_fsm_149 : STD_LOGIC;
signal ap_sig_bdd_3477 : BOOLEAN;
signal data_array_addr_10_gep_fu_360_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_10_reg_3794 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st165_fsm_164 : STD_LOGIC;
signal ap_sig_bdd_3487 : BOOLEAN;
signal data_array_addr_11_gep_fu_368_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_11_reg_3799 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st180_fsm_179 : STD_LOGIC;
signal ap_sig_bdd_3497 : BOOLEAN;
signal data_array_addr_12_gep_fu_376_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_12_reg_3804 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st195_fsm_194 : STD_LOGIC;
signal ap_sig_bdd_3507 : BOOLEAN;
signal data_array_addr_13_gep_fu_384_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_13_reg_3809 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st210_fsm_209 : STD_LOGIC;
signal ap_sig_bdd_3517 : BOOLEAN;
signal data_array_addr_14_gep_fu_392_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_14_reg_3814 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st225_fsm_224 : STD_LOGIC;
signal ap_sig_bdd_3527 : BOOLEAN;
signal data_array_addr_15_gep_fu_400_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_15_reg_3819 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st240_fsm_239 : STD_LOGIC;
signal ap_sig_bdd_3537 : BOOLEAN;
signal ins_keep_V_val_reg_3824 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st300_fsm_299 : STD_LOGIC;
signal ap_sig_bdd_3547 : BOOLEAN;
signal ins_strb_V_val_reg_3829 : STD_LOGIC_VECTOR (3 downto 0);
signal ins_user_V_val_reg_3834 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_last_V_val_reg_3839 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_id_V_val_reg_3844 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_dest_V_val_reg_3849 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_fu_2840_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it35 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it36 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it37 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it38 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it39 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it40 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it41 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it42 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it43 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it44 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it45 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it46 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it47 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it48 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it49 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it50 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it51 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it52 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it53 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it54 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it55 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it56 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it57 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it58 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it59 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it60 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it61 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it62 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it63 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it64 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it65 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it66 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it67 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it68 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it69 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it70 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it71 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it72 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it73 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it74 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it75 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it76 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it77 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it78 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it79 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it80 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it81 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it82 : STD_LOGIC_VECTOR (0 downto 0);
signal i_fu_2846_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_20_reg_3863 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_22_fu_2857_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_3869 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_new_reg_3874 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_new_reg_3879 : STD_LOGIC_VECTOR (31 downto 0);
signal v1x_assign_new_reg_3884 : STD_LOGIC_VECTOR (31 downto 0);
signal v1y_assign_new_reg_3889 : STD_LOGIC_VECTOR (31 downto 0);
signal v1z_assign_new_reg_3894 : STD_LOGIC_VECTOR (31 downto 0);
signal v2x_assign_new_reg_3899 : STD_LOGIC_VECTOR (31 downto 0);
signal v2y_assign_new_reg_3904 : STD_LOGIC_VECTOR (31 downto 0);
signal v2z_assign_new_reg_3909 : STD_LOGIC_VECTOR (31 downto 0);
signal rdx_assign_new_reg_3914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdy_assign_new_reg_3919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdz_assign_new_reg_3924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rex_assign_new_reg_3929 : STD_LOGIC_VECTOR (31 downto 0);
signal rey_assign_new_reg_3934 : STD_LOGIC_VECTOR (31 downto 0);
signal rez_assign_new_reg_3939 : STD_LOGIC_VECTOR (31 downto 0);
signal v0x_assign4_fu_3001_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_fu_3007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_fu_3013_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal a_reg_4010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal b_reg_4017 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_reg_4024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal d_reg_4031 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal e_reg_4038 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal f_reg_4045 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_454_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_reg_4052 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_4059 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_462_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal l_reg_4066 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal g_fu_3055_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal g_reg_4073 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal h_fu_3059_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal h_reg_4080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_fu_3063_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_4087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_522_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_reg_4094 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_526_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_311_reg_4099 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_530_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_i_reg_4104 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_534_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_i_reg_4109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_538_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_i_reg_4114 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_542_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_i_reg_4119 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_546_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_i_reg_4124 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_550_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_i_reg_4129 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_466_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_i_reg_4134 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_470_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_i_reg_4140 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_554_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_i_reg_4146 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_558_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_i_reg_4151 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_i_reg_4156 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_478_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_i_reg_4162 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_562_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_i_reg_4168 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_566_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_i_reg_4173 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_570_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_i_reg_4178 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_574_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_i_reg_4183 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_578_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_i_reg_4188 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_582_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_i_reg_4193 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_586_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_i_reg_4198 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_590_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_i_reg_4203 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_594_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_i_reg_4208 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_598_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_i_reg_4213 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_482_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_i_reg_4218 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_486_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_i_reg_4224 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_490_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_i_reg_4230 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_602_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_i_reg_4235 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_494_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_i_reg_4240 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_606_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_i_reg_4245 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_498_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_i_reg_4250 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_610_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_i_reg_4255 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_502_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_i_reg_4260 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_614_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_i_reg_4265 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal m_reg_4270 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_510_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_i_reg_4275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_514_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_i_reg_4280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_518_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_i_reg_4285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_630_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal im_reg_4290 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_fu_3071_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_reg_4297 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_addr_111281129_part_set_fu_3103_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal beta_addr_111281129_part_set_reg_4307 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address0 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_ce0 : STD_LOGIC;
signal data_array_we0 : STD_LOGIC;
signal data_array_d0 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address1 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_ce1 : STD_LOGIC;
signal data_array_we1 : STD_LOGIC;
signal data_array_d1 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_q1 : STD_LOGIC_VECTOR (575 downto 0);
signal tmp_1_fu_2852_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st255_fsm_254 : STD_LOGIC;
signal ap_sig_bdd_5023 : BOOLEAN;
signal ap_sig_cseq_ST_st270_fsm_269 : STD_LOGIC;
signal ap_sig_bdd_5046 : BOOLEAN;
signal ap_sig_cseq_ST_st285_fsm_284 : STD_LOGIC;
signal ap_sig_bdd_5069 : BOOLEAN;
signal t_load_fu_3115_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_fu_3120_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st387_fsm_303 : STD_LOGIC;
signal ap_sig_bdd_5096 : BOOLEAN;
signal beta_load_fu_3125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st388_fsm_304 : STD_LOGIC;
signal ap_sig_bdd_5104 : BOOLEAN;
signal t_load_s_fu_3130_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_s_fu_3135_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st390_fsm_306 : STD_LOGIC;
signal ap_sig_bdd_5113 : BOOLEAN;
signal beta_load_s_fu_3140_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st391_fsm_307 : STD_LOGIC;
signal ap_sig_bdd_5121 : BOOLEAN;
signal t_load_1_fu_3145_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_1_fu_3150_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st393_fsm_309 : STD_LOGIC;
signal ap_sig_bdd_5130 : BOOLEAN;
signal beta_load_1_fu_3155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st394_fsm_310 : STD_LOGIC;
signal ap_sig_bdd_5138 : BOOLEAN;
signal t_load_2_fu_3160_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_2_fu_3165_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st396_fsm_312 : STD_LOGIC;
signal ap_sig_bdd_5147 : BOOLEAN;
signal beta_load_2_fu_3170_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st397_fsm_313 : STD_LOGIC;
signal ap_sig_bdd_5155 : BOOLEAN;
signal t_load_3_fu_3175_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_3_fu_3180_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st399_fsm_315 : STD_LOGIC;
signal ap_sig_bdd_5164 : BOOLEAN;
signal beta_load_3_fu_3185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st400_fsm_316 : STD_LOGIC;
signal ap_sig_bdd_5172 : BOOLEAN;
signal t_load_4_fu_3190_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_4_fu_3195_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st402_fsm_318 : STD_LOGIC;
signal ap_sig_bdd_5181 : BOOLEAN;
signal beta_load_4_fu_3200_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st403_fsm_319 : STD_LOGIC;
signal ap_sig_bdd_5189 : BOOLEAN;
signal t_load_5_fu_3205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_5_fu_3210_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st405_fsm_321 : STD_LOGIC;
signal ap_sig_bdd_5198 : BOOLEAN;
signal beta_load_5_fu_3215_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st406_fsm_322 : STD_LOGIC;
signal ap_sig_bdd_5206 : BOOLEAN;
signal t_load_6_fu_3220_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_6_fu_3225_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st408_fsm_324 : STD_LOGIC;
signal ap_sig_bdd_5215 : BOOLEAN;
signal beta_load_6_fu_3230_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st409_fsm_325 : STD_LOGIC;
signal ap_sig_bdd_5223 : BOOLEAN;
signal t_load_7_fu_3235_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_7_fu_3240_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st411_fsm_327 : STD_LOGIC;
signal ap_sig_bdd_5232 : BOOLEAN;
signal beta_load_7_fu_3245_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st412_fsm_328 : STD_LOGIC;
signal ap_sig_bdd_5240 : BOOLEAN;
signal t_load_8_fu_3250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_8_fu_3255_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st414_fsm_330 : STD_LOGIC;
signal ap_sig_bdd_5249 : BOOLEAN;
signal beta_load_8_fu_3260_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st415_fsm_331 : STD_LOGIC;
signal ap_sig_bdd_5257 : BOOLEAN;
signal t_load_9_fu_3265_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_9_fu_3270_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st417_fsm_333 : STD_LOGIC;
signal ap_sig_bdd_5266 : BOOLEAN;
signal beta_load_9_fu_3275_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st418_fsm_334 : STD_LOGIC;
signal ap_sig_bdd_5274 : BOOLEAN;
signal t_load_10_fu_3280_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_10_fu_3285_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st420_fsm_336 : STD_LOGIC;
signal ap_sig_bdd_5283 : BOOLEAN;
signal beta_load_10_fu_3290_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st421_fsm_337 : STD_LOGIC;
signal ap_sig_bdd_5291 : BOOLEAN;
signal t_load_11_fu_3295_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_11_fu_3300_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st423_fsm_339 : STD_LOGIC;
signal ap_sig_bdd_5300 : BOOLEAN;
signal beta_load_11_fu_3305_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st424_fsm_340 : STD_LOGIC;
signal ap_sig_bdd_5308 : BOOLEAN;
signal t_load_12_fu_3310_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_12_fu_3315_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st426_fsm_342 : STD_LOGIC;
signal ap_sig_bdd_5317 : BOOLEAN;
signal beta_load_12_fu_3320_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st427_fsm_343 : STD_LOGIC;
signal ap_sig_bdd_5325 : BOOLEAN;
signal t_load_13_fu_3325_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_13_fu_3330_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st429_fsm_345 : STD_LOGIC;
signal ap_sig_bdd_5334 : BOOLEAN;
signal beta_load_13_fu_3335_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st430_fsm_346 : STD_LOGIC;
signal ap_sig_bdd_5342 : BOOLEAN;
signal t_load_14_fu_3340_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_14_fu_3345_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st432_fsm_348 : STD_LOGIC;
signal ap_sig_bdd_5351 : BOOLEAN;
signal beta_load_14_fu_3350_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st433_fsm_349 : STD_LOGIC;
signal ap_sig_bdd_5359 : BOOLEAN;
signal t_load_15_fu_3355_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_15_fu_3360_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st435_fsm_351 : STD_LOGIC;
signal ap_sig_bdd_5368 : BOOLEAN;
signal beta_load_15_fu_3365_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st436_fsm_352 : STD_LOGIC;
signal ap_sig_bdd_5376 : BOOLEAN;
signal t_load_16_fu_3370_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_16_fu_3375_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st438_fsm_354 : STD_LOGIC;
signal ap_sig_bdd_5385 : BOOLEAN;
signal beta_load_16_fu_3380_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st439_fsm_355 : STD_LOGIC;
signal ap_sig_bdd_5393 : BOOLEAN;
signal t_load_17_fu_3385_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_17_fu_3390_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st441_fsm_357 : STD_LOGIC;
signal ap_sig_bdd_5402 : BOOLEAN;
signal beta_load_17_fu_3395_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st442_fsm_358 : STD_LOGIC;
signal ap_sig_bdd_5410 : BOOLEAN;
signal t_load_18_fu_3400_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_18_fu_3405_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st444_fsm_360 : STD_LOGIC;
signal ap_sig_bdd_5419 : BOOLEAN;
signal beta_load_18_fu_3410_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st445_fsm_361 : STD_LOGIC;
signal ap_sig_bdd_5427 : BOOLEAN;
signal ap_reg_ioackin_outs_TREADY : STD_LOGIC := '0';
signal rez_addr959960_part_set_fu_830_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_3953954_part_set_fu_922_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_5947948_part_set_fu_1017_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_1956957_part_set_fu_1109_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_4950951_part_set_fu_1201_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_6944945_part_set_fu_1308_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_7941942_part_set_fu_1415_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_8938939_part_set_fu_1522_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_9935936_part_set_fu_1629_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_10932933_part_set_fu_1736_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_11929930_part_set_fu_1843_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_12926927_part_set_fu_1950_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_13923924_part_set_fu_2057_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_14920921_part_set_fu_2164_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_15917918_part_set_fu_2271_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_16914915_part_set_fu_2378_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_17911912_part_set_fu_2485_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_18908909_part_set_fu_2592_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_19905906_part_set_fu_2698_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_20902903_part_set_fu_2828_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_st385_fsm_301 : STD_LOGIC;
signal ap_sig_bdd_5902 : BOOLEAN;
signal grp_fu_430_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_454_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_454_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_462_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_462_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_466_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_466_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_470_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_470_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_474_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_474_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_478_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_478_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_482_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_482_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_486_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_486_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_490_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_490_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_494_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_494_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_498_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_498_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_502_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_502_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_510_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_510_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_514_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_514_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_518_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_518_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_522_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_522_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_526_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_526_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_530_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_530_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_534_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_534_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_538_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_538_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_542_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_542_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_546_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_546_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_550_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_550_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_554_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_554_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_558_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_558_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_562_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_562_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_566_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_566_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_570_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_570_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_574_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_574_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_578_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_578_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_582_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_582_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_586_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_586_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_590_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_590_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_594_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_594_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_598_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_598_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_602_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_602_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_606_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_606_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_610_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_610_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_614_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_614_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_618_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_618_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_622_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_622_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_626_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_626_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_630_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_630_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_14_toint_fu_793_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_13_toint_fu_789_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_12_toint_fu_785_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_11_toint_fu_781_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_10_toint_fu_777_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_9_toint_fu_773_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_8_toint_fu_769_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_7_toint_fu_765_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_6_toint_fu_761_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_5_toint_fu_757_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_4_toint_fu_753_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_3_toint_fu_749_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_2_toint_fu_745_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_1_toint_fu_741_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_toint_fu_737_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_796_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_44_toint_fu_885_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_43_toint_fu_882_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_42_toint_fu_879_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_41_toint_fu_876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_40_toint_fu_873_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_39_toint_fu_870_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_38_toint_fu_867_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_37_toint_fu_864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_36_toint_fu_861_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_35_toint_fu_858_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_34_toint_fu_855_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_33_toint_fu_852_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_32_toint_fu_849_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_31_toint_fu_846_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_30_toint_fu_843_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_888_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_74_toint_fu_979_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_73_toint_fu_975_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_72_toint_fu_971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_71_toint_fu_968_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_70_toint_fu_965_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_69_toint_fu_962_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_68_toint_fu_959_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_67_toint_fu_956_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_66_toint_fu_953_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_65_toint_fu_950_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_64_toint_fu_947_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_63_toint_fu_944_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_62_toint_fu_941_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_61_toint_fu_938_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_60_toint_fu_935_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_983_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_29_toint_fu_1072_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_28_toint_fu_1069_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_27_toint_fu_1066_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_26_toint_fu_1063_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_25_toint_fu_1060_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_24_toint_fu_1057_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_23_toint_fu_1054_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_22_toint_fu_1051_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_21_toint_fu_1048_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_20_toint_fu_1045_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_19_toint_fu_1042_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_18_toint_fu_1039_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_17_toint_fu_1036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_16_toint_fu_1033_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_15_toint_fu_1030_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_1075_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_59_toint_fu_1164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_58_toint_fu_1161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_57_toint_fu_1158_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_56_toint_fu_1155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_55_toint_fu_1152_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_54_toint_fu_1149_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_53_toint_fu_1146_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_52_toint_fu_1143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_51_toint_fu_1140_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_50_toint_fu_1137_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_49_toint_fu_1134_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_48_toint_fu_1131_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_47_toint_fu_1128_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_46_toint_fu_1125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_45_toint_fu_1122_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_1167_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_89_toint_fu_1270_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_88_toint_fu_1266_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_87_toint_fu_1262_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_86_toint_fu_1258_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_85_toint_fu_1254_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_84_toint_fu_1250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_83_toint_fu_1246_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_82_toint_fu_1242_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_81_toint_fu_1238_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_80_toint_fu_1234_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_79_toint_fu_1230_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_78_toint_fu_1226_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_77_toint_fu_1222_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_76_toint_fu_1218_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_75_toint_fu_1214_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_1274_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_104_toint_fu_1377_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_103_toint_fu_1373_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_102_toint_fu_1369_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_101_toint_fu_1365_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_100_toint_fu_1361_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_99_toint_fu_1357_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_98_toint_fu_1353_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_97_toint_fu_1349_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_96_toint_fu_1345_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_95_toint_fu_1341_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_94_toint_fu_1337_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_93_toint_fu_1333_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_92_toint_fu_1329_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_91_toint_fu_1325_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_90_toint_fu_1321_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_1381_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_119_toint_fu_1484_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_118_toint_fu_1480_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_117_toint_fu_1476_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_116_toint_fu_1472_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_115_toint_fu_1468_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_114_toint_fu_1464_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_113_toint_fu_1460_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_112_toint_fu_1456_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_111_toint_fu_1452_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_110_toint_fu_1448_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_109_toint_fu_1444_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_108_toint_fu_1440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_107_toint_fu_1436_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_106_toint_fu_1432_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_105_toint_fu_1428_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_1488_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_134_toint_fu_1591_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_133_toint_fu_1587_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_132_toint_fu_1583_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_131_toint_fu_1579_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_130_toint_fu_1575_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_129_toint_fu_1571_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_128_toint_fu_1567_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_127_toint_fu_1563_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_126_toint_fu_1559_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_125_toint_fu_1555_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_124_toint_fu_1551_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_123_toint_fu_1547_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_122_toint_fu_1543_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_121_toint_fu_1539_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_120_toint_fu_1535_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_fu_1595_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_149_toint_fu_1698_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_148_toint_fu_1694_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_147_toint_fu_1690_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_146_toint_fu_1686_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_145_toint_fu_1682_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_144_toint_fu_1678_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_143_toint_fu_1674_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_142_toint_fu_1670_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_141_toint_fu_1666_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_140_toint_fu_1662_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_139_toint_fu_1658_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_138_toint_fu_1654_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_137_toint_fu_1650_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_136_toint_fu_1646_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_135_toint_fu_1642_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_fu_1702_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_164_toint_fu_1805_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_163_toint_fu_1801_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_162_toint_fu_1797_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_161_toint_fu_1793_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_160_toint_fu_1789_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_159_toint_fu_1785_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_158_toint_fu_1781_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_157_toint_fu_1777_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_156_toint_fu_1773_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_155_toint_fu_1769_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_154_toint_fu_1765_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_153_toint_fu_1761_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_152_toint_fu_1757_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_151_toint_fu_1753_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_150_toint_fu_1749_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_fu_1809_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_179_toint_fu_1912_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_178_toint_fu_1908_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_177_toint_fu_1904_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_176_toint_fu_1900_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_175_toint_fu_1896_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_174_toint_fu_1892_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_173_toint_fu_1888_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_172_toint_fu_1884_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_171_toint_fu_1880_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_170_toint_fu_1876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_169_toint_fu_1872_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_168_toint_fu_1868_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_167_toint_fu_1864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_166_toint_fu_1860_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_165_toint_fu_1856_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_fu_1916_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_194_toint_fu_2019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_193_toint_fu_2015_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_192_toint_fu_2011_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_191_toint_fu_2007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_190_toint_fu_2003_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_189_toint_fu_1999_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_188_toint_fu_1995_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_187_toint_fu_1991_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_186_toint_fu_1987_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_185_toint_fu_1983_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_184_toint_fu_1979_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_183_toint_fu_1975_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_182_toint_fu_1971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_181_toint_fu_1967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_180_toint_fu_1963_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_fu_2023_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_209_toint_fu_2126_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_208_toint_fu_2122_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_207_toint_fu_2118_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_206_toint_fu_2114_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_205_toint_fu_2110_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_204_toint_fu_2106_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_203_toint_fu_2102_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_202_toint_fu_2098_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_201_toint_fu_2094_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_200_toint_fu_2090_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_199_toint_fu_2086_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_198_toint_fu_2082_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_197_toint_fu_2078_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_196_toint_fu_2074_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_195_toint_fu_2070_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_fu_2130_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_224_toint_fu_2233_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_223_toint_fu_2229_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_222_toint_fu_2225_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_221_toint_fu_2221_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_220_toint_fu_2217_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_219_toint_fu_2213_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_218_toint_fu_2209_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_217_toint_fu_2205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_216_toint_fu_2201_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_215_toint_fu_2197_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_214_toint_fu_2193_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_213_toint_fu_2189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_212_toint_fu_2185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_211_toint_fu_2181_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_210_toint_fu_2177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_2237_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_239_toint_fu_2340_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_238_toint_fu_2336_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_237_toint_fu_2332_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_236_toint_fu_2328_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_235_toint_fu_2324_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_234_toint_fu_2320_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_233_toint_fu_2316_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_232_toint_fu_2312_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_231_toint_fu_2308_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_230_toint_fu_2304_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_229_toint_fu_2300_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_228_toint_fu_2296_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_227_toint_fu_2292_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_226_toint_fu_2288_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_225_toint_fu_2284_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_2344_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_254_toint_fu_2447_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_253_toint_fu_2443_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_252_toint_fu_2439_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_251_toint_fu_2435_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_250_toint_fu_2431_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_249_toint_fu_2427_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_248_toint_fu_2423_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_247_toint_fu_2419_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_246_toint_fu_2415_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_245_toint_fu_2411_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_244_toint_fu_2407_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_243_toint_fu_2403_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_242_toint_fu_2399_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_241_toint_fu_2395_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_240_toint_fu_2391_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_2451_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_269_toint_fu_2554_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_268_toint_fu_2550_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_267_toint_fu_2546_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_266_toint_fu_2542_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_265_toint_fu_2538_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_264_toint_fu_2534_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_263_toint_fu_2530_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_262_toint_fu_2526_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_261_toint_fu_2522_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_260_toint_fu_2518_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_259_toint_fu_2514_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_258_toint_fu_2510_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_257_toint_fu_2506_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_256_toint_fu_2502_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_255_toint_fu_2498_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_2558_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_284_toint_fu_2660_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_283_toint_fu_2656_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_282_toint_fu_2652_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_281_toint_fu_2648_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_280_toint_fu_2644_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_279_toint_fu_2640_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_278_toint_fu_2636_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_277_toint_fu_2632_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_276_toint_fu_2628_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_275_toint_fu_2624_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_274_toint_fu_2620_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_273_toint_fu_2616_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_272_toint_fu_2612_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_271_toint_fu_2608_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_270_toint_fu_2604_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_fu_2664_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_299_toint_fu_2790_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_298_toint_fu_2762_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_297_toint_fu_2758_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_296_toint_fu_2754_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_295_toint_fu_2750_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_294_toint_fu_2746_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_293_toint_fu_2742_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_292_toint_fu_2738_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_291_toint_fu_2734_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_290_toint_fu_2730_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_289_toint_fu_2726_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_288_toint_fu_2722_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_287_toint_fu_2718_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_286_toint_fu_2714_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_285_toint_fu_2710_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_2794_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal tmp_61_to_int_i_fu_3068_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_618_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_622_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_626_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_write_assign_toint_fu_3089_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_write_assign_toint_fu_3085_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal t_write_assign_toint_fu_3081_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_3093_p4 : STD_LOGIC_VECTOR (95 downto 0);
signal grp_fu_639_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_ce : STD_LOGIC;
signal grp_fu_434_ce : STD_LOGIC;
signal grp_fu_438_ce : STD_LOGIC;
signal grp_fu_442_ce : STD_LOGIC;
signal grp_fu_446_ce : STD_LOGIC;
signal grp_fu_450_ce : STD_LOGIC;
signal grp_fu_454_ce : STD_LOGIC;
signal grp_fu_458_ce : STD_LOGIC;
signal grp_fu_462_ce : STD_LOGIC;
signal grp_fu_466_ce : STD_LOGIC;
signal grp_fu_470_ce : STD_LOGIC;
signal grp_fu_474_ce : STD_LOGIC;
signal grp_fu_478_ce : STD_LOGIC;
signal grp_fu_482_ce : STD_LOGIC;
signal grp_fu_486_ce : STD_LOGIC;
signal grp_fu_490_ce : STD_LOGIC;
signal grp_fu_494_ce : STD_LOGIC;
signal grp_fu_498_ce : STD_LOGIC;
signal grp_fu_502_ce : STD_LOGIC;
signal grp_fu_506_ce : STD_LOGIC;
signal grp_fu_510_ce : STD_LOGIC;
signal grp_fu_514_ce : STD_LOGIC;
signal grp_fu_518_ce : STD_LOGIC;
signal grp_fu_522_ce : STD_LOGIC;
signal grp_fu_526_ce : STD_LOGIC;
signal grp_fu_530_ce : STD_LOGIC;
signal grp_fu_534_ce : STD_LOGIC;
signal grp_fu_538_ce : STD_LOGIC;
signal grp_fu_542_ce : STD_LOGIC;
signal grp_fu_546_ce : STD_LOGIC;
signal grp_fu_550_ce : STD_LOGIC;
signal grp_fu_554_ce : STD_LOGIC;
signal grp_fu_558_ce : STD_LOGIC;
signal grp_fu_562_ce : STD_LOGIC;
signal grp_fu_566_ce : STD_LOGIC;
signal grp_fu_570_ce : STD_LOGIC;
signal grp_fu_574_ce : STD_LOGIC;
signal grp_fu_578_ce : STD_LOGIC;
signal grp_fu_582_ce : STD_LOGIC;
signal grp_fu_586_ce : STD_LOGIC;
signal grp_fu_590_ce : STD_LOGIC;
signal grp_fu_594_ce : STD_LOGIC;
signal grp_fu_598_ce : STD_LOGIC;
signal grp_fu_602_ce : STD_LOGIC;
signal grp_fu_606_ce : STD_LOGIC;
signal grp_fu_610_ce : STD_LOGIC;
signal grp_fu_614_ce : STD_LOGIC;
signal grp_fu_618_ce : STD_LOGIC;
signal grp_fu_622_ce : STD_LOGIC;
signal grp_fu_626_ce : STD_LOGIC;
signal grp_fu_630_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (361 downto 0);
component tri_intersect_fsub_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fadd_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fmul_32ns_32ns_32_5_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fdiv_32ns_32ns_32_30 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_data_array IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (4 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (575 downto 0);
q0 : OUT STD_LOGIC_VECTOR (575 downto 0);
address1 : IN STD_LOGIC_VECTOR (4 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (575 downto 0);
q1 : OUT STD_LOGIC_VECTOR (575 downto 0) );
end component;
begin
data_array_U : component tri_intersect_data_array
generic map (
DataWidth => 576,
AddressRange => 20,
AddressWidth => 5)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => data_array_address0,
ce0 => data_array_ce0,
we0 => data_array_we0,
d0 => data_array_d0,
q0 => data_array_q0,
address1 => data_array_address1,
ce1 => data_array_ce1,
we1 => data_array_we1,
d1 => data_array_d1,
q1 => data_array_q1);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U0 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_430_p0,
din1 => grp_fu_430_p1,
ce => grp_fu_430_ce,
dout => grp_fu_430_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U1 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_434_p0,
din1 => grp_fu_434_p1,
ce => grp_fu_434_ce,
dout => grp_fu_434_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U2 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_438_p0,
din1 => grp_fu_438_p1,
ce => grp_fu_438_ce,
dout => grp_fu_438_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U3 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_442_p0,
din1 => grp_fu_442_p1,
ce => grp_fu_442_ce,
dout => grp_fu_442_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U4 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_446_p0,
din1 => grp_fu_446_p1,
ce => grp_fu_446_ce,
dout => grp_fu_446_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U5 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_450_p0,
din1 => grp_fu_450_p1,
ce => grp_fu_450_ce,
dout => grp_fu_450_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U6 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_454_p0,
din1 => grp_fu_454_p1,
ce => grp_fu_454_ce,
dout => grp_fu_454_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U7 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_458_p0,
din1 => grp_fu_458_p1,
ce => grp_fu_458_ce,
dout => grp_fu_458_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U8 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_462_p0,
din1 => grp_fu_462_p1,
ce => grp_fu_462_ce,
dout => grp_fu_462_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U9 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_466_p0,
din1 => grp_fu_466_p1,
ce => grp_fu_466_ce,
dout => grp_fu_466_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U10 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_470_p0,
din1 => grp_fu_470_p1,
ce => grp_fu_470_ce,
dout => grp_fu_470_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U11 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_474_p0,
din1 => grp_fu_474_p1,
ce => grp_fu_474_ce,
dout => grp_fu_474_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U12 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_478_p0,
din1 => grp_fu_478_p1,
ce => grp_fu_478_ce,
dout => grp_fu_478_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U13 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_482_p0,
din1 => grp_fu_482_p1,
ce => grp_fu_482_ce,
dout => grp_fu_482_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U14 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_486_p0,
din1 => grp_fu_486_p1,
ce => grp_fu_486_ce,
dout => grp_fu_486_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U15 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_490_p0,
din1 => grp_fu_490_p1,
ce => grp_fu_490_ce,
dout => grp_fu_490_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U16 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_494_p0,
din1 => grp_fu_494_p1,
ce => grp_fu_494_ce,
dout => grp_fu_494_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U17 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_498_p0,
din1 => grp_fu_498_p1,
ce => grp_fu_498_ce,
dout => grp_fu_498_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U18 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_502_p0,
din1 => grp_fu_502_p1,
ce => grp_fu_502_ce,
dout => grp_fu_502_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U19 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_506_p0,
din1 => grp_fu_506_p1,
ce => grp_fu_506_ce,
dout => grp_fu_506_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U20 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_510_p0,
din1 => grp_fu_510_p1,
ce => grp_fu_510_ce,
dout => grp_fu_510_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U21 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_514_p0,
din1 => grp_fu_514_p1,
ce => grp_fu_514_ce,
dout => grp_fu_514_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U22 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_518_p0,
din1 => grp_fu_518_p1,
ce => grp_fu_518_ce,
dout => grp_fu_518_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U23 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_522_p0,
din1 => grp_fu_522_p1,
ce => grp_fu_522_ce,
dout => grp_fu_522_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U24 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_526_p0,
din1 => grp_fu_526_p1,
ce => grp_fu_526_ce,
dout => grp_fu_526_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U25 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_530_p0,
din1 => grp_fu_530_p1,
ce => grp_fu_530_ce,
dout => grp_fu_530_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U26 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_534_p0,
din1 => grp_fu_534_p1,
ce => grp_fu_534_ce,
dout => grp_fu_534_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U27 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_538_p0,
din1 => grp_fu_538_p1,
ce => grp_fu_538_ce,
dout => grp_fu_538_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U28 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_542_p0,
din1 => grp_fu_542_p1,
ce => grp_fu_542_ce,
dout => grp_fu_542_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U29 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_546_p0,
din1 => grp_fu_546_p1,
ce => grp_fu_546_ce,
dout => grp_fu_546_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U30 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_550_p0,
din1 => grp_fu_550_p1,
ce => grp_fu_550_ce,
dout => grp_fu_550_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U31 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_554_p0,
din1 => grp_fu_554_p1,
ce => grp_fu_554_ce,
dout => grp_fu_554_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U32 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_558_p0,
din1 => grp_fu_558_p1,
ce => grp_fu_558_ce,
dout => grp_fu_558_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U33 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_562_p0,
din1 => grp_fu_562_p1,
ce => grp_fu_562_ce,
dout => grp_fu_562_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U34 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_566_p0,
din1 => grp_fu_566_p1,
ce => grp_fu_566_ce,
dout => grp_fu_566_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U35 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_570_p0,
din1 => grp_fu_570_p1,
ce => grp_fu_570_ce,
dout => grp_fu_570_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U36 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_574_p0,
din1 => grp_fu_574_p1,
ce => grp_fu_574_ce,
dout => grp_fu_574_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U37 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_578_p0,
din1 => grp_fu_578_p1,
ce => grp_fu_578_ce,
dout => grp_fu_578_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U38 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_582_p0,
din1 => grp_fu_582_p1,
ce => grp_fu_582_ce,
dout => grp_fu_582_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U39 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_586_p0,
din1 => grp_fu_586_p1,
ce => grp_fu_586_ce,
dout => grp_fu_586_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U40 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_590_p0,
din1 => grp_fu_590_p1,
ce => grp_fu_590_ce,
dout => grp_fu_590_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U41 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_594_p0,
din1 => grp_fu_594_p1,
ce => grp_fu_594_ce,
dout => grp_fu_594_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U42 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_598_p0,
din1 => grp_fu_598_p1,
ce => grp_fu_598_ce,
dout => grp_fu_598_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U43 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_602_p0,
din1 => grp_fu_602_p1,
ce => grp_fu_602_ce,
dout => grp_fu_602_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U44 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_606_p0,
din1 => grp_fu_606_p1,
ce => grp_fu_606_ce,
dout => grp_fu_606_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U45 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_610_p0,
din1 => grp_fu_610_p1,
ce => grp_fu_610_ce,
dout => grp_fu_610_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U46 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_614_p0,
din1 => grp_fu_614_p1,
ce => grp_fu_614_ce,
dout => grp_fu_614_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U47 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_618_p0,
din1 => grp_fu_618_p1,
ce => grp_fu_618_ce,
dout => grp_fu_618_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U48 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_622_p0,
din1 => grp_fu_622_p1,
ce => grp_fu_622_ce,
dout => grp_fu_622_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U49 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_626_p0,
din1 => grp_fu_626_p1,
ce => grp_fu_626_ce,
dout => grp_fu_626_p2);
tri_intersect_fdiv_32ns_32ns_32_30_U50 : component tri_intersect_fdiv_32ns_32ns_32_30
generic map (
ID => 1,
NUM_STAGE => 30,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_630_p0,
din1 => grp_fu_630_p1,
ce => grp_fu_630_ce,
dout => grp_fu_630_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_outs_TREADY assign process. --
ap_reg_ioackin_outs_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361) and (ap_const_logic_1 = outs_TREADY)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (ap_const_lv1_0 = exitcond2_fu_2840_p2))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it23 assign process. --
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it24 assign process. --
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it25 assign process. --
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it26 assign process. --
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it27 assign process. --
ap_reg_ppiten_pp0_it27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it28 assign process. --
ap_reg_ppiten_pp0_it28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it29 assign process. --
ap_reg_ppiten_pp0_it29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it30 assign process. --
ap_reg_ppiten_pp0_it30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it31 assign process. --
ap_reg_ppiten_pp0_it31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it32 assign process. --
ap_reg_ppiten_pp0_it32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it33 assign process. --
ap_reg_ppiten_pp0_it33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it34 assign process. --
ap_reg_ppiten_pp0_it34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it35 assign process. --
ap_reg_ppiten_pp0_it35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it36 assign process. --
ap_reg_ppiten_pp0_it36_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it36 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it36 <= ap_reg_ppiten_pp0_it35;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it37 assign process. --
ap_reg_ppiten_pp0_it37_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it37 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it37 <= ap_reg_ppiten_pp0_it36;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it38 assign process. --
ap_reg_ppiten_pp0_it38_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it38 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it38 <= ap_reg_ppiten_pp0_it37;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it39 assign process. --
ap_reg_ppiten_pp0_it39_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it39 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it39 <= ap_reg_ppiten_pp0_it38;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it40 assign process. --
ap_reg_ppiten_pp0_it40_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it40 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it40 <= ap_reg_ppiten_pp0_it39;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it41 assign process. --
ap_reg_ppiten_pp0_it41_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it41 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it41 <= ap_reg_ppiten_pp0_it40;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it42 assign process. --
ap_reg_ppiten_pp0_it42_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it42 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it42 <= ap_reg_ppiten_pp0_it41;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it43 assign process. --
ap_reg_ppiten_pp0_it43_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it43 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it43 <= ap_reg_ppiten_pp0_it42;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it44 assign process. --
ap_reg_ppiten_pp0_it44_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it44 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it44 <= ap_reg_ppiten_pp0_it43;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it45 assign process. --
ap_reg_ppiten_pp0_it45_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it45 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it45 <= ap_reg_ppiten_pp0_it44;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it46 assign process. --
ap_reg_ppiten_pp0_it46_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it46 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it46 <= ap_reg_ppiten_pp0_it45;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it47 assign process. --
ap_reg_ppiten_pp0_it47_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it47 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it47 <= ap_reg_ppiten_pp0_it46;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it48 assign process. --
ap_reg_ppiten_pp0_it48_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it48 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it48 <= ap_reg_ppiten_pp0_it47;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it49 assign process. --
ap_reg_ppiten_pp0_it49_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it49 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it49 <= ap_reg_ppiten_pp0_it48;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it50 assign process. --
ap_reg_ppiten_pp0_it50_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it50 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it50 <= ap_reg_ppiten_pp0_it49;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it51 assign process. --
ap_reg_ppiten_pp0_it51_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it51 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it51 <= ap_reg_ppiten_pp0_it50;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it52 assign process. --
ap_reg_ppiten_pp0_it52_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it52 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it52 <= ap_reg_ppiten_pp0_it51;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it53 assign process. --
ap_reg_ppiten_pp0_it53_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it53 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it53 <= ap_reg_ppiten_pp0_it52;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it54 assign process. --
ap_reg_ppiten_pp0_it54_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it54 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it54 <= ap_reg_ppiten_pp0_it53;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it55 assign process. --
ap_reg_ppiten_pp0_it55_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it55 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it55 <= ap_reg_ppiten_pp0_it54;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it56 assign process. --
ap_reg_ppiten_pp0_it56_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it56 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it56 <= ap_reg_ppiten_pp0_it55;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it57 assign process. --
ap_reg_ppiten_pp0_it57_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it57 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it57 <= ap_reg_ppiten_pp0_it56;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it58 assign process. --
ap_reg_ppiten_pp0_it58_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it58 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it58 <= ap_reg_ppiten_pp0_it57;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it59 assign process. --
ap_reg_ppiten_pp0_it59_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it59 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it59 <= ap_reg_ppiten_pp0_it58;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it60 assign process. --
ap_reg_ppiten_pp0_it60_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it60 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it60 <= ap_reg_ppiten_pp0_it59;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it61 assign process. --
ap_reg_ppiten_pp0_it61_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it61 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it61 <= ap_reg_ppiten_pp0_it60;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it62 assign process. --
ap_reg_ppiten_pp0_it62_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it62 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it62 <= ap_reg_ppiten_pp0_it61;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it63 assign process. --
ap_reg_ppiten_pp0_it63_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it63 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it63 <= ap_reg_ppiten_pp0_it62;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it64 assign process. --
ap_reg_ppiten_pp0_it64_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it64 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it64 <= ap_reg_ppiten_pp0_it63;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it65 assign process. --
ap_reg_ppiten_pp0_it65_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it65 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it65 <= ap_reg_ppiten_pp0_it64;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it66 assign process. --
ap_reg_ppiten_pp0_it66_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it66 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it66 <= ap_reg_ppiten_pp0_it65;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it67 assign process. --
ap_reg_ppiten_pp0_it67_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it67 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it67 <= ap_reg_ppiten_pp0_it66;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it68 assign process. --
ap_reg_ppiten_pp0_it68_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it68 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it68 <= ap_reg_ppiten_pp0_it67;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it69 assign process. --
ap_reg_ppiten_pp0_it69_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it69 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it69 <= ap_reg_ppiten_pp0_it68;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it70 assign process. --
ap_reg_ppiten_pp0_it70_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it70 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it70 <= ap_reg_ppiten_pp0_it69;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it71 assign process. --
ap_reg_ppiten_pp0_it71_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it71 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it71 <= ap_reg_ppiten_pp0_it70;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it72 assign process. --
ap_reg_ppiten_pp0_it72_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it72 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it72 <= ap_reg_ppiten_pp0_it71;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it73 assign process. --
ap_reg_ppiten_pp0_it73_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it73 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it73 <= ap_reg_ppiten_pp0_it72;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it74 assign process. --
ap_reg_ppiten_pp0_it74_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it74 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it74 <= ap_reg_ppiten_pp0_it73;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it75 assign process. --
ap_reg_ppiten_pp0_it75_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it75 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it75 <= ap_reg_ppiten_pp0_it74;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it76 assign process. --
ap_reg_ppiten_pp0_it76_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it76 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it76 <= ap_reg_ppiten_pp0_it75;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it77 assign process. --
ap_reg_ppiten_pp0_it77_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it77 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it77 <= ap_reg_ppiten_pp0_it76;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it78 assign process. --
ap_reg_ppiten_pp0_it78_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it78 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it78 <= ap_reg_ppiten_pp0_it77;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it79 assign process. --
ap_reg_ppiten_pp0_it79_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it79 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it79 <= ap_reg_ppiten_pp0_it78;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it80 assign process. --
ap_reg_ppiten_pp0_it80_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it80 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it80 <= ap_reg_ppiten_pp0_it79;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it81 assign process. --
ap_reg_ppiten_pp0_it81_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it81 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it81 <= ap_reg_ppiten_pp0_it80;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it82 assign process. --
ap_reg_ppiten_pp0_it82_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it82 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it82 <= ap_reg_ppiten_pp0_it81;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it83 assign process. --
ap_reg_ppiten_pp0_it83_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it83 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it83 <= ap_reg_ppiten_pp0_it82;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end process;
-- i1_reg_418 assign process. --
i1_reg_418_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299))) then
i1_reg_418 <= ap_const_lv5_0;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (ap_const_lv1_0 = exitcond2_fu_2840_p2))) then
i1_reg_418 <= i_fu_2846_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it9)) then
a_reg_4010 <= grp_fu_430_p2;
b_reg_4017 <= grp_fu_434_p2;
c_reg_4024 <= grp_fu_438_p2;
d_reg_4031 <= grp_fu_442_p2;
e_reg_4038 <= grp_fu_446_p2;
f_reg_4045 <= grp_fu_450_p2;
j_reg_4052 <= grp_fu_454_p2;
k_reg_4059 <= grp_fu_458_p2;
l_reg_4066 <= grp_fu_462_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_true = ap_true)) then
ap_reg_ppstg_a_reg_4010_pp0_it11 <= a_reg_4010;
ap_reg_ppstg_a_reg_4010_pp0_it12 <= ap_reg_ppstg_a_reg_4010_pp0_it11;
ap_reg_ppstg_a_reg_4010_pp0_it13 <= ap_reg_ppstg_a_reg_4010_pp0_it12;
ap_reg_ppstg_a_reg_4010_pp0_it14 <= ap_reg_ppstg_a_reg_4010_pp0_it13;
ap_reg_ppstg_a_reg_4010_pp0_it15 <= ap_reg_ppstg_a_reg_4010_pp0_it14;
ap_reg_ppstg_a_reg_4010_pp0_it16 <= ap_reg_ppstg_a_reg_4010_pp0_it15;
ap_reg_ppstg_a_reg_4010_pp0_it17 <= ap_reg_ppstg_a_reg_4010_pp0_it16;
ap_reg_ppstg_a_reg_4010_pp0_it18 <= ap_reg_ppstg_a_reg_4010_pp0_it17;
ap_reg_ppstg_a_reg_4010_pp0_it19 <= ap_reg_ppstg_a_reg_4010_pp0_it18;
ap_reg_ppstg_a_reg_4010_pp0_it20 <= ap_reg_ppstg_a_reg_4010_pp0_it19;
ap_reg_ppstg_a_reg_4010_pp0_it21 <= ap_reg_ppstg_a_reg_4010_pp0_it20;
ap_reg_ppstg_a_reg_4010_pp0_it22 <= ap_reg_ppstg_a_reg_4010_pp0_it21;
ap_reg_ppstg_a_reg_4010_pp0_it23 <= ap_reg_ppstg_a_reg_4010_pp0_it22;
ap_reg_ppstg_a_reg_4010_pp0_it24 <= ap_reg_ppstg_a_reg_4010_pp0_it23;
ap_reg_ppstg_b_reg_4017_pp0_it11 <= b_reg_4017;
ap_reg_ppstg_b_reg_4017_pp0_it12 <= ap_reg_ppstg_b_reg_4017_pp0_it11;
ap_reg_ppstg_b_reg_4017_pp0_it13 <= ap_reg_ppstg_b_reg_4017_pp0_it12;
ap_reg_ppstg_b_reg_4017_pp0_it14 <= ap_reg_ppstg_b_reg_4017_pp0_it13;
ap_reg_ppstg_b_reg_4017_pp0_it15 <= ap_reg_ppstg_b_reg_4017_pp0_it14;
ap_reg_ppstg_b_reg_4017_pp0_it16 <= ap_reg_ppstg_b_reg_4017_pp0_it15;
ap_reg_ppstg_b_reg_4017_pp0_it17 <= ap_reg_ppstg_b_reg_4017_pp0_it16;
ap_reg_ppstg_b_reg_4017_pp0_it18 <= ap_reg_ppstg_b_reg_4017_pp0_it17;
ap_reg_ppstg_b_reg_4017_pp0_it19 <= ap_reg_ppstg_b_reg_4017_pp0_it18;
ap_reg_ppstg_b_reg_4017_pp0_it20 <= ap_reg_ppstg_b_reg_4017_pp0_it19;
ap_reg_ppstg_b_reg_4017_pp0_it21 <= ap_reg_ppstg_b_reg_4017_pp0_it20;
ap_reg_ppstg_b_reg_4017_pp0_it22 <= ap_reg_ppstg_b_reg_4017_pp0_it21;
ap_reg_ppstg_b_reg_4017_pp0_it23 <= ap_reg_ppstg_b_reg_4017_pp0_it22;
ap_reg_ppstg_b_reg_4017_pp0_it24 <= ap_reg_ppstg_b_reg_4017_pp0_it23;
ap_reg_ppstg_c_reg_4024_pp0_it11 <= c_reg_4024;
ap_reg_ppstg_c_reg_4024_pp0_it12 <= ap_reg_ppstg_c_reg_4024_pp0_it11;
ap_reg_ppstg_c_reg_4024_pp0_it13 <= ap_reg_ppstg_c_reg_4024_pp0_it12;
ap_reg_ppstg_c_reg_4024_pp0_it14 <= ap_reg_ppstg_c_reg_4024_pp0_it13;
ap_reg_ppstg_c_reg_4024_pp0_it15 <= ap_reg_ppstg_c_reg_4024_pp0_it14;
ap_reg_ppstg_c_reg_4024_pp0_it16 <= ap_reg_ppstg_c_reg_4024_pp0_it15;
ap_reg_ppstg_c_reg_4024_pp0_it17 <= ap_reg_ppstg_c_reg_4024_pp0_it16;
ap_reg_ppstg_c_reg_4024_pp0_it18 <= ap_reg_ppstg_c_reg_4024_pp0_it17;
ap_reg_ppstg_c_reg_4024_pp0_it19 <= ap_reg_ppstg_c_reg_4024_pp0_it18;
ap_reg_ppstg_c_reg_4024_pp0_it20 <= ap_reg_ppstg_c_reg_4024_pp0_it19;
ap_reg_ppstg_c_reg_4024_pp0_it21 <= ap_reg_ppstg_c_reg_4024_pp0_it20;
ap_reg_ppstg_c_reg_4024_pp0_it22 <= ap_reg_ppstg_c_reg_4024_pp0_it21;
ap_reg_ppstg_c_reg_4024_pp0_it23 <= ap_reg_ppstg_c_reg_4024_pp0_it22;
ap_reg_ppstg_c_reg_4024_pp0_it24 <= ap_reg_ppstg_c_reg_4024_pp0_it23;
ap_reg_ppstg_c_reg_4024_pp0_it25 <= ap_reg_ppstg_c_reg_4024_pp0_it24;
ap_reg_ppstg_c_reg_4024_pp0_it26 <= ap_reg_ppstg_c_reg_4024_pp0_it25;
ap_reg_ppstg_c_reg_4024_pp0_it27 <= ap_reg_ppstg_c_reg_4024_pp0_it26;
ap_reg_ppstg_c_reg_4024_pp0_it28 <= ap_reg_ppstg_c_reg_4024_pp0_it27;
ap_reg_ppstg_c_reg_4024_pp0_it29 <= ap_reg_ppstg_c_reg_4024_pp0_it28;
ap_reg_ppstg_c_reg_4024_pp0_it30 <= ap_reg_ppstg_c_reg_4024_pp0_it29;
ap_reg_ppstg_c_reg_4024_pp0_it31 <= ap_reg_ppstg_c_reg_4024_pp0_it30;
ap_reg_ppstg_c_reg_4024_pp0_it32 <= ap_reg_ppstg_c_reg_4024_pp0_it31;
ap_reg_ppstg_c_reg_4024_pp0_it33 <= ap_reg_ppstg_c_reg_4024_pp0_it32;
ap_reg_ppstg_d_reg_4031_pp0_it11 <= d_reg_4031;
ap_reg_ppstg_d_reg_4031_pp0_it12 <= ap_reg_ppstg_d_reg_4031_pp0_it11;
ap_reg_ppstg_d_reg_4031_pp0_it13 <= ap_reg_ppstg_d_reg_4031_pp0_it12;
ap_reg_ppstg_d_reg_4031_pp0_it14 <= ap_reg_ppstg_d_reg_4031_pp0_it13;
ap_reg_ppstg_d_reg_4031_pp0_it15 <= ap_reg_ppstg_d_reg_4031_pp0_it14;
ap_reg_ppstg_d_reg_4031_pp0_it16 <= ap_reg_ppstg_d_reg_4031_pp0_it15;
ap_reg_ppstg_d_reg_4031_pp0_it17 <= ap_reg_ppstg_d_reg_4031_pp0_it16;
ap_reg_ppstg_d_reg_4031_pp0_it18 <= ap_reg_ppstg_d_reg_4031_pp0_it17;
ap_reg_ppstg_d_reg_4031_pp0_it19 <= ap_reg_ppstg_d_reg_4031_pp0_it18;
ap_reg_ppstg_d_reg_4031_pp0_it20 <= ap_reg_ppstg_d_reg_4031_pp0_it19;
ap_reg_ppstg_d_reg_4031_pp0_it21 <= ap_reg_ppstg_d_reg_4031_pp0_it20;
ap_reg_ppstg_d_reg_4031_pp0_it22 <= ap_reg_ppstg_d_reg_4031_pp0_it21;
ap_reg_ppstg_d_reg_4031_pp0_it23 <= ap_reg_ppstg_d_reg_4031_pp0_it22;
ap_reg_ppstg_d_reg_4031_pp0_it24 <= ap_reg_ppstg_d_reg_4031_pp0_it23;
ap_reg_ppstg_d_reg_4031_pp0_it25 <= ap_reg_ppstg_d_reg_4031_pp0_it24;
ap_reg_ppstg_d_reg_4031_pp0_it26 <= ap_reg_ppstg_d_reg_4031_pp0_it25;
ap_reg_ppstg_d_reg_4031_pp0_it27 <= ap_reg_ppstg_d_reg_4031_pp0_it26;
ap_reg_ppstg_d_reg_4031_pp0_it28 <= ap_reg_ppstg_d_reg_4031_pp0_it27;
ap_reg_ppstg_d_reg_4031_pp0_it29 <= ap_reg_ppstg_d_reg_4031_pp0_it28;
ap_reg_ppstg_d_reg_4031_pp0_it30 <= ap_reg_ppstg_d_reg_4031_pp0_it29;
ap_reg_ppstg_d_reg_4031_pp0_it31 <= ap_reg_ppstg_d_reg_4031_pp0_it30;
ap_reg_ppstg_d_reg_4031_pp0_it32 <= ap_reg_ppstg_d_reg_4031_pp0_it31;
ap_reg_ppstg_d_reg_4031_pp0_it33 <= ap_reg_ppstg_d_reg_4031_pp0_it32;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8;
ap_reg_ppstg_e_reg_4038_pp0_it11 <= e_reg_4038;
ap_reg_ppstg_e_reg_4038_pp0_it12 <= ap_reg_ppstg_e_reg_4038_pp0_it11;
ap_reg_ppstg_e_reg_4038_pp0_it13 <= ap_reg_ppstg_e_reg_4038_pp0_it12;
ap_reg_ppstg_e_reg_4038_pp0_it14 <= ap_reg_ppstg_e_reg_4038_pp0_it13;
ap_reg_ppstg_e_reg_4038_pp0_it15 <= ap_reg_ppstg_e_reg_4038_pp0_it14;
ap_reg_ppstg_e_reg_4038_pp0_it16 <= ap_reg_ppstg_e_reg_4038_pp0_it15;
ap_reg_ppstg_e_reg_4038_pp0_it17 <= ap_reg_ppstg_e_reg_4038_pp0_it16;
ap_reg_ppstg_e_reg_4038_pp0_it18 <= ap_reg_ppstg_e_reg_4038_pp0_it17;
ap_reg_ppstg_e_reg_4038_pp0_it19 <= ap_reg_ppstg_e_reg_4038_pp0_it18;
ap_reg_ppstg_e_reg_4038_pp0_it20 <= ap_reg_ppstg_e_reg_4038_pp0_it19;
ap_reg_ppstg_e_reg_4038_pp0_it21 <= ap_reg_ppstg_e_reg_4038_pp0_it20;
ap_reg_ppstg_e_reg_4038_pp0_it22 <= ap_reg_ppstg_e_reg_4038_pp0_it21;
ap_reg_ppstg_e_reg_4038_pp0_it23 <= ap_reg_ppstg_e_reg_4038_pp0_it22;
ap_reg_ppstg_e_reg_4038_pp0_it24 <= ap_reg_ppstg_e_reg_4038_pp0_it23;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it10 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it9;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it11 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it10;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it12 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it11;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it13 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it12;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it14 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it13;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it15 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it14;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it16 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it15;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it17 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it16;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it18 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it17;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it19 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it18;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it2 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it1;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it20 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it19;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it21 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it20;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it22 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it21;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it23 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it22;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it24 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it23;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it25 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it24;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it26 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it25;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it27 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it26;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it28 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it27;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it29 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it28;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it3 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it2;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it30 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it29;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it31 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it30;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it32 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it31;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it33 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it32;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it34 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it33;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it35 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it34;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it36 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it35;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it37 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it36;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it38 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it37;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it39 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it38;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it4 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it3;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it40 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it39;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it41 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it40;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it42 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it41;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it43 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it42;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it44 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it43;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it45 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it44;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it46 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it45;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it47 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it46;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it48 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it47;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it49 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it48;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it5 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it4;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it50 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it49;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it51 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it50;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it52 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it51;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it53 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it52;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it54 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it53;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it55 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it54;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it56 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it55;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it57 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it56;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it58 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it57;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it59 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it58;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it6 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it5;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it60 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it59;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it61 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it60;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it62 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it61;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it63 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it62;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it64 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it63;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it65 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it64;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it66 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it65;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it67 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it66;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it68 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it67;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it69 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it68;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it7 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it6;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it70 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it69;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it71 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it70;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it72 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it71;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it73 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it72;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it74 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it73;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it75 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it74;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it76 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it75;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it77 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it76;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it78 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it77;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it79 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it78;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it8 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it7;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it80 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it79;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it81 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it80;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it82 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it81;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it9 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it8;
ap_reg_ppstg_f_reg_4045_pp0_it11 <= f_reg_4045;
ap_reg_ppstg_f_reg_4045_pp0_it12 <= ap_reg_ppstg_f_reg_4045_pp0_it11;
ap_reg_ppstg_f_reg_4045_pp0_it13 <= ap_reg_ppstg_f_reg_4045_pp0_it12;
ap_reg_ppstg_f_reg_4045_pp0_it14 <= ap_reg_ppstg_f_reg_4045_pp0_it13;
ap_reg_ppstg_f_reg_4045_pp0_it15 <= ap_reg_ppstg_f_reg_4045_pp0_it14;
ap_reg_ppstg_f_reg_4045_pp0_it16 <= ap_reg_ppstg_f_reg_4045_pp0_it15;
ap_reg_ppstg_f_reg_4045_pp0_it17 <= ap_reg_ppstg_f_reg_4045_pp0_it16;
ap_reg_ppstg_f_reg_4045_pp0_it18 <= ap_reg_ppstg_f_reg_4045_pp0_it17;
ap_reg_ppstg_f_reg_4045_pp0_it19 <= ap_reg_ppstg_f_reg_4045_pp0_it18;
ap_reg_ppstg_f_reg_4045_pp0_it20 <= ap_reg_ppstg_f_reg_4045_pp0_it19;
ap_reg_ppstg_f_reg_4045_pp0_it21 <= ap_reg_ppstg_f_reg_4045_pp0_it20;
ap_reg_ppstg_f_reg_4045_pp0_it22 <= ap_reg_ppstg_f_reg_4045_pp0_it21;
ap_reg_ppstg_f_reg_4045_pp0_it23 <= ap_reg_ppstg_f_reg_4045_pp0_it22;
ap_reg_ppstg_f_reg_4045_pp0_it24 <= ap_reg_ppstg_f_reg_4045_pp0_it23;
ap_reg_ppstg_g_reg_4073_pp0_it12 <= g_reg_4073;
ap_reg_ppstg_g_reg_4073_pp0_it13 <= ap_reg_ppstg_g_reg_4073_pp0_it12;
ap_reg_ppstg_g_reg_4073_pp0_it14 <= ap_reg_ppstg_g_reg_4073_pp0_it13;
ap_reg_ppstg_g_reg_4073_pp0_it15 <= ap_reg_ppstg_g_reg_4073_pp0_it14;
ap_reg_ppstg_g_reg_4073_pp0_it16 <= ap_reg_ppstg_g_reg_4073_pp0_it15;
ap_reg_ppstg_g_reg_4073_pp0_it17 <= ap_reg_ppstg_g_reg_4073_pp0_it16;
ap_reg_ppstg_g_reg_4073_pp0_it18 <= ap_reg_ppstg_g_reg_4073_pp0_it17;
ap_reg_ppstg_g_reg_4073_pp0_it19 <= ap_reg_ppstg_g_reg_4073_pp0_it18;
ap_reg_ppstg_g_reg_4073_pp0_it20 <= ap_reg_ppstg_g_reg_4073_pp0_it19;
ap_reg_ppstg_g_reg_4073_pp0_it21 <= ap_reg_ppstg_g_reg_4073_pp0_it20;
ap_reg_ppstg_g_reg_4073_pp0_it22 <= ap_reg_ppstg_g_reg_4073_pp0_it21;
ap_reg_ppstg_g_reg_4073_pp0_it23 <= ap_reg_ppstg_g_reg_4073_pp0_it22;
ap_reg_ppstg_g_reg_4073_pp0_it24 <= ap_reg_ppstg_g_reg_4073_pp0_it23;
ap_reg_ppstg_g_reg_4073_pp0_it25 <= ap_reg_ppstg_g_reg_4073_pp0_it24;
ap_reg_ppstg_g_reg_4073_pp0_it26 <= ap_reg_ppstg_g_reg_4073_pp0_it25;
ap_reg_ppstg_g_reg_4073_pp0_it27 <= ap_reg_ppstg_g_reg_4073_pp0_it26;
ap_reg_ppstg_g_reg_4073_pp0_it28 <= ap_reg_ppstg_g_reg_4073_pp0_it27;
ap_reg_ppstg_g_reg_4073_pp0_it29 <= ap_reg_ppstg_g_reg_4073_pp0_it28;
ap_reg_ppstg_g_reg_4073_pp0_it30 <= ap_reg_ppstg_g_reg_4073_pp0_it29;
ap_reg_ppstg_g_reg_4073_pp0_it31 <= ap_reg_ppstg_g_reg_4073_pp0_it30;
ap_reg_ppstg_g_reg_4073_pp0_it32 <= ap_reg_ppstg_g_reg_4073_pp0_it31;
ap_reg_ppstg_g_reg_4073_pp0_it33 <= ap_reg_ppstg_g_reg_4073_pp0_it32;
ap_reg_ppstg_h_reg_4080_pp0_it12 <= h_reg_4080;
ap_reg_ppstg_h_reg_4080_pp0_it13 <= ap_reg_ppstg_h_reg_4080_pp0_it12;
ap_reg_ppstg_h_reg_4080_pp0_it14 <= ap_reg_ppstg_h_reg_4080_pp0_it13;
ap_reg_ppstg_h_reg_4080_pp0_it15 <= ap_reg_ppstg_h_reg_4080_pp0_it14;
ap_reg_ppstg_h_reg_4080_pp0_it16 <= ap_reg_ppstg_h_reg_4080_pp0_it15;
ap_reg_ppstg_h_reg_4080_pp0_it17 <= ap_reg_ppstg_h_reg_4080_pp0_it16;
ap_reg_ppstg_h_reg_4080_pp0_it18 <= ap_reg_ppstg_h_reg_4080_pp0_it17;
ap_reg_ppstg_h_reg_4080_pp0_it19 <= ap_reg_ppstg_h_reg_4080_pp0_it18;
ap_reg_ppstg_h_reg_4080_pp0_it20 <= ap_reg_ppstg_h_reg_4080_pp0_it19;
ap_reg_ppstg_h_reg_4080_pp0_it21 <= ap_reg_ppstg_h_reg_4080_pp0_it20;
ap_reg_ppstg_h_reg_4080_pp0_it22 <= ap_reg_ppstg_h_reg_4080_pp0_it21;
ap_reg_ppstg_h_reg_4080_pp0_it23 <= ap_reg_ppstg_h_reg_4080_pp0_it22;
ap_reg_ppstg_h_reg_4080_pp0_it24 <= ap_reg_ppstg_h_reg_4080_pp0_it23;
ap_reg_ppstg_i_1_reg_4087_pp0_it12 <= i_1_reg_4087;
ap_reg_ppstg_i_1_reg_4087_pp0_it13 <= ap_reg_ppstg_i_1_reg_4087_pp0_it12;
ap_reg_ppstg_i_1_reg_4087_pp0_it14 <= ap_reg_ppstg_i_1_reg_4087_pp0_it13;
ap_reg_ppstg_i_1_reg_4087_pp0_it15 <= ap_reg_ppstg_i_1_reg_4087_pp0_it14;
ap_reg_ppstg_i_1_reg_4087_pp0_it16 <= ap_reg_ppstg_i_1_reg_4087_pp0_it15;
ap_reg_ppstg_i_1_reg_4087_pp0_it17 <= ap_reg_ppstg_i_1_reg_4087_pp0_it16;
ap_reg_ppstg_i_1_reg_4087_pp0_it18 <= ap_reg_ppstg_i_1_reg_4087_pp0_it17;
ap_reg_ppstg_i_1_reg_4087_pp0_it19 <= ap_reg_ppstg_i_1_reg_4087_pp0_it18;
ap_reg_ppstg_i_1_reg_4087_pp0_it20 <= ap_reg_ppstg_i_1_reg_4087_pp0_it19;
ap_reg_ppstg_i_1_reg_4087_pp0_it21 <= ap_reg_ppstg_i_1_reg_4087_pp0_it20;
ap_reg_ppstg_i_1_reg_4087_pp0_it22 <= ap_reg_ppstg_i_1_reg_4087_pp0_it21;
ap_reg_ppstg_i_1_reg_4087_pp0_it23 <= ap_reg_ppstg_i_1_reg_4087_pp0_it22;
ap_reg_ppstg_i_1_reg_4087_pp0_it24 <= ap_reg_ppstg_i_1_reg_4087_pp0_it23;
ap_reg_ppstg_j_reg_4052_pp0_it11 <= j_reg_4052;
ap_reg_ppstg_j_reg_4052_pp0_it12 <= ap_reg_ppstg_j_reg_4052_pp0_it11;
ap_reg_ppstg_j_reg_4052_pp0_it13 <= ap_reg_ppstg_j_reg_4052_pp0_it12;
ap_reg_ppstg_j_reg_4052_pp0_it14 <= ap_reg_ppstg_j_reg_4052_pp0_it13;
ap_reg_ppstg_j_reg_4052_pp0_it15 <= ap_reg_ppstg_j_reg_4052_pp0_it14;
ap_reg_ppstg_j_reg_4052_pp0_it16 <= ap_reg_ppstg_j_reg_4052_pp0_it15;
ap_reg_ppstg_j_reg_4052_pp0_it17 <= ap_reg_ppstg_j_reg_4052_pp0_it16;
ap_reg_ppstg_j_reg_4052_pp0_it18 <= ap_reg_ppstg_j_reg_4052_pp0_it17;
ap_reg_ppstg_j_reg_4052_pp0_it19 <= ap_reg_ppstg_j_reg_4052_pp0_it18;
ap_reg_ppstg_j_reg_4052_pp0_it20 <= ap_reg_ppstg_j_reg_4052_pp0_it19;
ap_reg_ppstg_j_reg_4052_pp0_it21 <= ap_reg_ppstg_j_reg_4052_pp0_it20;
ap_reg_ppstg_j_reg_4052_pp0_it22 <= ap_reg_ppstg_j_reg_4052_pp0_it21;
ap_reg_ppstg_j_reg_4052_pp0_it23 <= ap_reg_ppstg_j_reg_4052_pp0_it22;
ap_reg_ppstg_j_reg_4052_pp0_it24 <= ap_reg_ppstg_j_reg_4052_pp0_it23;
ap_reg_ppstg_k_reg_4059_pp0_it11 <= k_reg_4059;
ap_reg_ppstg_k_reg_4059_pp0_it12 <= ap_reg_ppstg_k_reg_4059_pp0_it11;
ap_reg_ppstg_k_reg_4059_pp0_it13 <= ap_reg_ppstg_k_reg_4059_pp0_it12;
ap_reg_ppstg_k_reg_4059_pp0_it14 <= ap_reg_ppstg_k_reg_4059_pp0_it13;
ap_reg_ppstg_k_reg_4059_pp0_it15 <= ap_reg_ppstg_k_reg_4059_pp0_it14;
ap_reg_ppstg_k_reg_4059_pp0_it16 <= ap_reg_ppstg_k_reg_4059_pp0_it15;
ap_reg_ppstg_k_reg_4059_pp0_it17 <= ap_reg_ppstg_k_reg_4059_pp0_it16;
ap_reg_ppstg_k_reg_4059_pp0_it18 <= ap_reg_ppstg_k_reg_4059_pp0_it17;
ap_reg_ppstg_k_reg_4059_pp0_it19 <= ap_reg_ppstg_k_reg_4059_pp0_it18;
ap_reg_ppstg_k_reg_4059_pp0_it20 <= ap_reg_ppstg_k_reg_4059_pp0_it19;
ap_reg_ppstg_k_reg_4059_pp0_it21 <= ap_reg_ppstg_k_reg_4059_pp0_it20;
ap_reg_ppstg_k_reg_4059_pp0_it22 <= ap_reg_ppstg_k_reg_4059_pp0_it21;
ap_reg_ppstg_k_reg_4059_pp0_it23 <= ap_reg_ppstg_k_reg_4059_pp0_it22;
ap_reg_ppstg_k_reg_4059_pp0_it24 <= ap_reg_ppstg_k_reg_4059_pp0_it23;
ap_reg_ppstg_l_reg_4066_pp0_it11 <= l_reg_4066;
ap_reg_ppstg_l_reg_4066_pp0_it12 <= ap_reg_ppstg_l_reg_4066_pp0_it11;
ap_reg_ppstg_l_reg_4066_pp0_it13 <= ap_reg_ppstg_l_reg_4066_pp0_it12;
ap_reg_ppstg_l_reg_4066_pp0_it14 <= ap_reg_ppstg_l_reg_4066_pp0_it13;
ap_reg_ppstg_l_reg_4066_pp0_it15 <= ap_reg_ppstg_l_reg_4066_pp0_it14;
ap_reg_ppstg_l_reg_4066_pp0_it16 <= ap_reg_ppstg_l_reg_4066_pp0_it15;
ap_reg_ppstg_l_reg_4066_pp0_it17 <= ap_reg_ppstg_l_reg_4066_pp0_it16;
ap_reg_ppstg_l_reg_4066_pp0_it18 <= ap_reg_ppstg_l_reg_4066_pp0_it17;
ap_reg_ppstg_l_reg_4066_pp0_it19 <= ap_reg_ppstg_l_reg_4066_pp0_it18;
ap_reg_ppstg_l_reg_4066_pp0_it20 <= ap_reg_ppstg_l_reg_4066_pp0_it19;
ap_reg_ppstg_l_reg_4066_pp0_it21 <= ap_reg_ppstg_l_reg_4066_pp0_it20;
ap_reg_ppstg_l_reg_4066_pp0_it22 <= ap_reg_ppstg_l_reg_4066_pp0_it21;
ap_reg_ppstg_l_reg_4066_pp0_it23 <= ap_reg_ppstg_l_reg_4066_pp0_it22;
ap_reg_ppstg_l_reg_4066_pp0_it24 <= ap_reg_ppstg_l_reg_4066_pp0_it23;
ap_reg_ppstg_l_reg_4066_pp0_it25 <= ap_reg_ppstg_l_reg_4066_pp0_it24;
ap_reg_ppstg_l_reg_4066_pp0_it26 <= ap_reg_ppstg_l_reg_4066_pp0_it25;
ap_reg_ppstg_l_reg_4066_pp0_it27 <= ap_reg_ppstg_l_reg_4066_pp0_it26;
ap_reg_ppstg_l_reg_4066_pp0_it28 <= ap_reg_ppstg_l_reg_4066_pp0_it27;
ap_reg_ppstg_l_reg_4066_pp0_it29 <= ap_reg_ppstg_l_reg_4066_pp0_it28;
ap_reg_ppstg_l_reg_4066_pp0_it30 <= ap_reg_ppstg_l_reg_4066_pp0_it29;
ap_reg_ppstg_l_reg_4066_pp0_it31 <= ap_reg_ppstg_l_reg_4066_pp0_it30;
ap_reg_ppstg_l_reg_4066_pp0_it32 <= ap_reg_ppstg_l_reg_4066_pp0_it31;
ap_reg_ppstg_l_reg_4066_pp0_it33 <= ap_reg_ppstg_l_reg_4066_pp0_it32;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2 <= rdx_assign_new_reg_3914;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2 <= rdy_assign_new_reg_3919;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2 <= rdz_assign_new_reg_3924;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8;
ap_reg_ppstg_reg_725_pp0_it10 <= ap_reg_ppstg_reg_725_pp0_it9;
ap_reg_ppstg_reg_725_pp0_it11 <= ap_reg_ppstg_reg_725_pp0_it10;
ap_reg_ppstg_reg_725_pp0_it12 <= ap_reg_ppstg_reg_725_pp0_it11;
ap_reg_ppstg_reg_725_pp0_it13 <= ap_reg_ppstg_reg_725_pp0_it12;
ap_reg_ppstg_reg_725_pp0_it14 <= ap_reg_ppstg_reg_725_pp0_it13;
ap_reg_ppstg_reg_725_pp0_it15 <= ap_reg_ppstg_reg_725_pp0_it14;
ap_reg_ppstg_reg_725_pp0_it16 <= ap_reg_ppstg_reg_725_pp0_it15;
ap_reg_ppstg_reg_725_pp0_it17 <= ap_reg_ppstg_reg_725_pp0_it16;
ap_reg_ppstg_reg_725_pp0_it18 <= ap_reg_ppstg_reg_725_pp0_it17;
ap_reg_ppstg_reg_725_pp0_it19 <= ap_reg_ppstg_reg_725_pp0_it18;
ap_reg_ppstg_reg_725_pp0_it2 <= reg_725;
ap_reg_ppstg_reg_725_pp0_it20 <= ap_reg_ppstg_reg_725_pp0_it19;
ap_reg_ppstg_reg_725_pp0_it21 <= ap_reg_ppstg_reg_725_pp0_it20;
ap_reg_ppstg_reg_725_pp0_it22 <= ap_reg_ppstg_reg_725_pp0_it21;
ap_reg_ppstg_reg_725_pp0_it23 <= ap_reg_ppstg_reg_725_pp0_it22;
ap_reg_ppstg_reg_725_pp0_it24 <= ap_reg_ppstg_reg_725_pp0_it23;
ap_reg_ppstg_reg_725_pp0_it25 <= ap_reg_ppstg_reg_725_pp0_it24;
ap_reg_ppstg_reg_725_pp0_it26 <= ap_reg_ppstg_reg_725_pp0_it25;
ap_reg_ppstg_reg_725_pp0_it27 <= ap_reg_ppstg_reg_725_pp0_it26;
ap_reg_ppstg_reg_725_pp0_it28 <= ap_reg_ppstg_reg_725_pp0_it27;
ap_reg_ppstg_reg_725_pp0_it29 <= ap_reg_ppstg_reg_725_pp0_it28;
ap_reg_ppstg_reg_725_pp0_it3 <= ap_reg_ppstg_reg_725_pp0_it2;
ap_reg_ppstg_reg_725_pp0_it30 <= ap_reg_ppstg_reg_725_pp0_it29;
ap_reg_ppstg_reg_725_pp0_it31 <= ap_reg_ppstg_reg_725_pp0_it30;
ap_reg_ppstg_reg_725_pp0_it32 <= ap_reg_ppstg_reg_725_pp0_it31;
ap_reg_ppstg_reg_725_pp0_it33 <= ap_reg_ppstg_reg_725_pp0_it32;
ap_reg_ppstg_reg_725_pp0_it34 <= ap_reg_ppstg_reg_725_pp0_it33;
ap_reg_ppstg_reg_725_pp0_it35 <= ap_reg_ppstg_reg_725_pp0_it34;
ap_reg_ppstg_reg_725_pp0_it36 <= ap_reg_ppstg_reg_725_pp0_it35;
ap_reg_ppstg_reg_725_pp0_it37 <= ap_reg_ppstg_reg_725_pp0_it36;
ap_reg_ppstg_reg_725_pp0_it38 <= ap_reg_ppstg_reg_725_pp0_it37;
ap_reg_ppstg_reg_725_pp0_it39 <= ap_reg_ppstg_reg_725_pp0_it38;
ap_reg_ppstg_reg_725_pp0_it4 <= ap_reg_ppstg_reg_725_pp0_it3;
ap_reg_ppstg_reg_725_pp0_it40 <= ap_reg_ppstg_reg_725_pp0_it39;
ap_reg_ppstg_reg_725_pp0_it41 <= ap_reg_ppstg_reg_725_pp0_it40;
ap_reg_ppstg_reg_725_pp0_it42 <= ap_reg_ppstg_reg_725_pp0_it41;
ap_reg_ppstg_reg_725_pp0_it43 <= ap_reg_ppstg_reg_725_pp0_it42;
ap_reg_ppstg_reg_725_pp0_it44 <= ap_reg_ppstg_reg_725_pp0_it43;
ap_reg_ppstg_reg_725_pp0_it45 <= ap_reg_ppstg_reg_725_pp0_it44;
ap_reg_ppstg_reg_725_pp0_it46 <= ap_reg_ppstg_reg_725_pp0_it45;
ap_reg_ppstg_reg_725_pp0_it47 <= ap_reg_ppstg_reg_725_pp0_it46;
ap_reg_ppstg_reg_725_pp0_it48 <= ap_reg_ppstg_reg_725_pp0_it47;
ap_reg_ppstg_reg_725_pp0_it49 <= ap_reg_ppstg_reg_725_pp0_it48;
ap_reg_ppstg_reg_725_pp0_it5 <= ap_reg_ppstg_reg_725_pp0_it4;
ap_reg_ppstg_reg_725_pp0_it50 <= ap_reg_ppstg_reg_725_pp0_it49;
ap_reg_ppstg_reg_725_pp0_it51 <= ap_reg_ppstg_reg_725_pp0_it50;
ap_reg_ppstg_reg_725_pp0_it52 <= ap_reg_ppstg_reg_725_pp0_it51;
ap_reg_ppstg_reg_725_pp0_it53 <= ap_reg_ppstg_reg_725_pp0_it52;
ap_reg_ppstg_reg_725_pp0_it54 <= ap_reg_ppstg_reg_725_pp0_it53;
ap_reg_ppstg_reg_725_pp0_it55 <= ap_reg_ppstg_reg_725_pp0_it54;
ap_reg_ppstg_reg_725_pp0_it56 <= ap_reg_ppstg_reg_725_pp0_it55;
ap_reg_ppstg_reg_725_pp0_it57 <= ap_reg_ppstg_reg_725_pp0_it56;
ap_reg_ppstg_reg_725_pp0_it58 <= ap_reg_ppstg_reg_725_pp0_it57;
ap_reg_ppstg_reg_725_pp0_it59 <= ap_reg_ppstg_reg_725_pp0_it58;
ap_reg_ppstg_reg_725_pp0_it6 <= ap_reg_ppstg_reg_725_pp0_it5;
ap_reg_ppstg_reg_725_pp0_it60 <= ap_reg_ppstg_reg_725_pp0_it59;
ap_reg_ppstg_reg_725_pp0_it61 <= ap_reg_ppstg_reg_725_pp0_it60;
ap_reg_ppstg_reg_725_pp0_it62 <= ap_reg_ppstg_reg_725_pp0_it61;
ap_reg_ppstg_reg_725_pp0_it63 <= ap_reg_ppstg_reg_725_pp0_it62;
ap_reg_ppstg_reg_725_pp0_it64 <= ap_reg_ppstg_reg_725_pp0_it63;
ap_reg_ppstg_reg_725_pp0_it65 <= ap_reg_ppstg_reg_725_pp0_it64;
ap_reg_ppstg_reg_725_pp0_it66 <= ap_reg_ppstg_reg_725_pp0_it65;
ap_reg_ppstg_reg_725_pp0_it67 <= ap_reg_ppstg_reg_725_pp0_it66;
ap_reg_ppstg_reg_725_pp0_it68 <= ap_reg_ppstg_reg_725_pp0_it67;
ap_reg_ppstg_reg_725_pp0_it69 <= ap_reg_ppstg_reg_725_pp0_it68;
ap_reg_ppstg_reg_725_pp0_it7 <= ap_reg_ppstg_reg_725_pp0_it6;
ap_reg_ppstg_reg_725_pp0_it70 <= ap_reg_ppstg_reg_725_pp0_it69;
ap_reg_ppstg_reg_725_pp0_it71 <= ap_reg_ppstg_reg_725_pp0_it70;
ap_reg_ppstg_reg_725_pp0_it72 <= ap_reg_ppstg_reg_725_pp0_it71;
ap_reg_ppstg_reg_725_pp0_it73 <= ap_reg_ppstg_reg_725_pp0_it72;
ap_reg_ppstg_reg_725_pp0_it74 <= ap_reg_ppstg_reg_725_pp0_it73;
ap_reg_ppstg_reg_725_pp0_it75 <= ap_reg_ppstg_reg_725_pp0_it74;
ap_reg_ppstg_reg_725_pp0_it76 <= ap_reg_ppstg_reg_725_pp0_it75;
ap_reg_ppstg_reg_725_pp0_it77 <= ap_reg_ppstg_reg_725_pp0_it76;
ap_reg_ppstg_reg_725_pp0_it78 <= ap_reg_ppstg_reg_725_pp0_it77;
ap_reg_ppstg_reg_725_pp0_it79 <= ap_reg_ppstg_reg_725_pp0_it78;
ap_reg_ppstg_reg_725_pp0_it8 <= ap_reg_ppstg_reg_725_pp0_it7;
ap_reg_ppstg_reg_725_pp0_it80 <= ap_reg_ppstg_reg_725_pp0_it79;
ap_reg_ppstg_reg_725_pp0_it81 <= ap_reg_ppstg_reg_725_pp0_it80;
ap_reg_ppstg_reg_725_pp0_it9 <= ap_reg_ppstg_reg_725_pp0_it8;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48 <= tmp_25_i_reg_4275;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48 <= tmp_31_i_reg_4280;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48 <= tmp_36_i_reg_4285;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300)) then
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1 <= data_array_addr_20_reg_3863;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it1 <= exitcond2_reg_3854;
exitcond2_reg_3854 <= exitcond2_fu_2840_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it81)) then
beta_addr_111281129_part_set_reg_4307 <= beta_addr_111281129_part_set_fu_3103_p5;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (ap_const_lv1_0 = exitcond2_fu_2840_p2))) then
data_array_addr_20_reg_3863 <= tmp_1_fu_2852_p1(5 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
data_array_load_1_reg_3743 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72))) then
data_array_load_2_reg_3722 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
data_array_load_3_reg_3759 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it10)) then
g_reg_4073 <= g_fu_3055_p1;
h_reg_4080 <= h_fu_3059_p1;
i_1_reg_4087 <= i_1_fu_3063_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it76)) then
im_reg_4290 <= grp_fu_630_p2;
tmp_61_neg_i_reg_4297 <= tmp_61_neg_i_fu_3071_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then
ins_data_val14_reg_3415 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then
ins_data_val15_reg_3420 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16))) then
ins_data_val16_reg_3425 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
ins_data_val17_reg_3430 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18))) then
ins_data_val18_reg_3435 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19))) then
ins_data_val19_reg_3440 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20))) then
ins_data_val20_reg_3445 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21))) then
ins_data_val21_reg_3450 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22))) then
ins_data_val22_reg_3455 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23))) then
ins_data_val23_reg_3460 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
ins_data_val24_reg_3465 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25))) then
ins_data_val25_reg_3470 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26))) then
ins_data_val26_reg_3475 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
ins_data_val27_reg_3480 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
ins_data_val28_reg_3485 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
ins_data_val29_reg_3490 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30))) then
ins_data_val30_reg_3495 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31))) then
ins_data_val31_reg_3500 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32))) then
ins_data_val32_reg_3505 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33))) then
ins_data_val33_reg_3510 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34))) then
ins_data_val34_reg_3515 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st36_fsm_35))) then
ins_data_val35_reg_3520 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st37_fsm_36))) then
ins_data_val36_reg_3525 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st38_fsm_37))) then
ins_data_val37_reg_3530 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38))) then
ins_data_val38_reg_3535 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39))) then
ins_data_val39_reg_3540 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40))) then
ins_data_val40_reg_3545 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41))) then
ins_data_val41_reg_3550 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42))) then
ins_data_val42_reg_3555 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43))) then
ins_data_val43_reg_3560 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st45_fsm_44))) then
ins_data_val44_reg_3565 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45))) then
ins_data_val45_reg_3570 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46))) then
ins_data_val46_reg_3575 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47))) then
ins_data_val47_reg_3580 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48))) then
ins_data_val48_reg_3585 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st50_fsm_49))) then
ins_data_val49_reg_3590 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st51_fsm_50))) then
ins_data_val50_reg_3595 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st52_fsm_51))) then
ins_data_val51_reg_3600 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52))) then
ins_data_val52_reg_3605 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st54_fsm_53))) then
ins_data_val53_reg_3610 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st55_fsm_54))) then
ins_data_val54_reg_3615 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st56_fsm_55))) then
ins_data_val55_reg_3620 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st57_fsm_56))) then
ins_data_val56_reg_3625 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st58_fsm_57))) then
ins_data_val57_reg_3630 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st59_fsm_58))) then
ins_data_val58_reg_3635 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st60_fsm_59))) then
ins_data_val59_reg_3640 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st61_fsm_60))) then
ins_data_val60_reg_3645 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st62_fsm_61))) then
ins_data_val61_reg_3650 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st63_fsm_62))) then
ins_data_val62_reg_3655 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st64_fsm_63))) then
ins_data_val63_reg_3660 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st65_fsm_64))) then
ins_data_val64_reg_3665 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st66_fsm_65))) then
ins_data_val65_reg_3670 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st67_fsm_66))) then
ins_data_val66_reg_3675 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st68_fsm_67))) then
ins_data_val67_reg_3680 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st69_fsm_68))) then
ins_data_val68_reg_3685 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st70_fsm_69))) then
ins_data_val69_reg_3690 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70))) then
ins_data_val70_reg_3695 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71))) then
ins_data_val71_reg_3706 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299))) then
ins_dest_V_val_reg_3849 <= ins_TDEST;
ins_id_V_val_reg_3844 <= ins_TID;
ins_keep_V_val_reg_3824 <= ins_TKEEP;
ins_last_V_val_reg_3839 <= ins_TLAST;
ins_strb_V_val_reg_3829 <= ins_TSTRB;
ins_user_V_val_reg_3834 <= ins_TUSER;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it46)) then
m_reg_4270 <= grp_fu_506_p2;
tmp_25_i_reg_4275 <= grp_fu_510_p2;
tmp_31_i_reg_4280 <= grp_fu_514_p2;
tmp_36_i_reg_4285 <= grp_fu_518_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (exitcond2_reg_3854 = ap_const_lv1_0))) then
rdx_assign_new_reg_3914 <= data_array_q0(319 downto 288);
rdy_assign_new_reg_3919 <= data_array_q0(351 downto 320);
rdz_assign_new_reg_3924 <= data_array_q0(383 downto 352);
rex_assign_new_reg_3929 <= data_array_q0(415 downto 384);
rey_assign_new_reg_3934 <= data_array_q0(447 downto 416);
rez_assign_new_reg_3939 <= data_array_q0(479 downto 448);
tmp_22_reg_3869 <= tmp_22_fu_2857_p1;
v0y_assign_new_reg_3874 <= data_array_q0(63 downto 32);
v0z_assign_new_reg_3879 <= data_array_q0(95 downto 64);
v1x_assign_new_reg_3884 <= data_array_q0(127 downto 96);
v1y_assign_new_reg_3889 <= data_array_q0(159 downto 128);
v1z_assign_new_reg_3894 <= data_array_q0(191 downto 160);
v2x_assign_new_reg_3899 <= data_array_q0(223 downto 192);
v2y_assign_new_reg_3904 <= data_array_q0(255 downto 224);
v2z_assign_new_reg_3909 <= data_array_q0(287 downto 256);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st106_fsm_105)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st136_fsm_135)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st181_fsm_180)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st196_fsm_195)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st211_fsm_210)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st226_fsm_225)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st241_fsm_240)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st256_fsm_255)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st271_fsm_270)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st286_fsm_285)))) then
reg_669 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st107_fsm_106)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st137_fsm_136)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st167_fsm_166)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st182_fsm_181)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st197_fsm_196)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st212_fsm_211)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st227_fsm_226)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st242_fsm_241)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st257_fsm_256)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st272_fsm_271)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st287_fsm_286)))) then
reg_673 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st108_fsm_107)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st168_fsm_167)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st183_fsm_182)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st198_fsm_197)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st213_fsm_212)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st228_fsm_227)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st243_fsm_242)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st258_fsm_257)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st273_fsm_272)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st288_fsm_287)))) then
reg_677 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st109_fsm_108)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st169_fsm_168)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st184_fsm_183)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st199_fsm_198)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st214_fsm_213)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st229_fsm_228)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st244_fsm_243)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st259_fsm_258)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st274_fsm_273)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st289_fsm_288)))) then
reg_681 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st110_fsm_109)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st170_fsm_169)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st185_fsm_184)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st200_fsm_199)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st215_fsm_214)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st230_fsm_229)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st245_fsm_244)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st260_fsm_259)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st275_fsm_274)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st290_fsm_289)))) then
reg_685 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st96_fsm_95)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st111_fsm_110)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st126_fsm_125)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st171_fsm_170)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st186_fsm_185)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st201_fsm_200)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st216_fsm_215)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st231_fsm_230)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st246_fsm_245)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st261_fsm_260)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st276_fsm_275)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st291_fsm_290)))) then
reg_689 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st112_fsm_111)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st127_fsm_126)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st172_fsm_171)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st187_fsm_186)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st202_fsm_201)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st217_fsm_216)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st232_fsm_231)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st247_fsm_246)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st262_fsm_261)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st277_fsm_276)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st292_fsm_291)))) then
reg_693 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st113_fsm_112)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st158_fsm_157)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st173_fsm_172)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st188_fsm_187)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st203_fsm_202)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st218_fsm_217)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st233_fsm_232)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st248_fsm_247)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st263_fsm_262)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st278_fsm_277)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st293_fsm_292)))) then
reg_697 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st174_fsm_173)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st189_fsm_188)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st204_fsm_203)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st219_fsm_218)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st234_fsm_233)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st249_fsm_248)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st264_fsm_263)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st279_fsm_278)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st294_fsm_293)))) then
reg_701 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st100_fsm_99)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st130_fsm_129)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st175_fsm_174)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st190_fsm_189)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st205_fsm_204)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st220_fsm_219)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st235_fsm_234)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st250_fsm_249)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st265_fsm_264)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st280_fsm_279)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st295_fsm_294)))) then
reg_705 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st101_fsm_100)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st131_fsm_130)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st176_fsm_175)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st191_fsm_190)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st206_fsm_205)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st221_fsm_220)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st236_fsm_235)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st251_fsm_250)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st266_fsm_265)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st281_fsm_280)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st296_fsm_295)))) then
reg_709 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st102_fsm_101)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st132_fsm_131)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st177_fsm_176)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st192_fsm_191)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st207_fsm_206)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st222_fsm_221)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st237_fsm_236)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st252_fsm_251)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st267_fsm_266)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st282_fsm_281)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st297_fsm_296)))) then
reg_713 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st103_fsm_102)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st133_fsm_132)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st178_fsm_177)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st193_fsm_192)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st208_fsm_207)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st223_fsm_222)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st238_fsm_237)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st253_fsm_252)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st268_fsm_267)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st283_fsm_282)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st298_fsm_297)))) then
reg_717 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st134_fsm_133)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st179_fsm_178)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st194_fsm_193)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st209_fsm_208)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st224_fsm_223)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st239_fsm_238)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st254_fsm_253)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st269_fsm_268)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st284_fsm_283)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st299_fsm_298)))) then
reg_721 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (exitcond2_reg_3854 = ap_const_lv1_0)))) then
reg_725 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359)))) then
reg_729 <= data_array_q1(543 downto 512);
reg_733 <= data_array_q1(575 downto 544);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it32)) then
tmp_10_i_reg_4218 <= grp_fu_482_p2;
tmp_23_i_reg_4224 <= grp_fu_486_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it37)) then
tmp_11_i_reg_4235 <= grp_fu_602_p2;
tmp_20_i_reg_4240 <= grp_fu_494_p2;
tmp_24_i_reg_4245 <= grp_fu_606_p2;
tmp_29_i_reg_4250 <= grp_fu_498_p2;
tmp_30_i_reg_4255 <= grp_fu_610_p2;
tmp_34_i_reg_4260 <= grp_fu_502_p2;
tmp_35_i_reg_4265 <= grp_fu_614_p2;
tmp_7_i_reg_4230 <= grp_fu_490_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it14)) then
tmp_12_i_reg_4114 <= grp_fu_538_p2;
tmp_13_i_reg_4119 <= grp_fu_542_p2;
tmp_16_i_reg_4124 <= grp_fu_546_p2;
tmp_17_i_reg_4129 <= grp_fu_550_p2;
tmp_3_i_reg_4104 <= grp_fu_530_p2;
tmp_4_i_reg_4109 <= grp_fu_534_p2;
tmp_i_311_reg_4099 <= grp_fu_526_p2;
tmp_i_reg_4094 <= grp_fu_522_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it23)) then
tmp_14_i_reg_4156 <= grp_fu_474_p2;
tmp_18_i_reg_4162 <= grp_fu_478_p2;
tmp_1_i_reg_4134 <= grp_fu_466_p2;
tmp_21_i_reg_4168 <= grp_fu_562_p2;
tmp_22_i_reg_4173 <= grp_fu_566_p2;
tmp_5_i_reg_4140 <= grp_fu_470_p2;
tmp_8_i_reg_4146 <= grp_fu_554_p2;
tmp_9_i_reg_4151 <= grp_fu_558_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it28)) then
tmp_15_i_reg_4188 <= grp_fu_578_p2;
tmp_19_i_reg_4193 <= grp_fu_582_p2;
tmp_27_i_reg_4198 <= grp_fu_586_p2;
tmp_28_i_reg_4203 <= grp_fu_590_p2;
tmp_2_i_reg_4178 <= grp_fu_570_p2;
tmp_32_i_reg_4208 <= grp_fu_594_p2;
tmp_33_i_reg_4213 <= grp_fu_598_p2;
tmp_6_i_reg_4183 <= grp_fu_574_p2;
end if;
end if;
end process;
data_array_addr_16_reg_3700(4 downto 0) <= "10000";
data_array_addr_18_reg_3711(4 downto 0) <= "10010";
data_array_addr_reg_3717(4 downto 0) <= "00000";
data_array_addr_2_reg_3727(4 downto 0) <= "00010";
data_array_addr_4_reg_3732(4 downto 0) <= "00100";
data_array_addr_17_reg_3737(4 downto 0) <= "10001";
data_array_addr_19_reg_3748(4 downto 0) <= "10011";
data_array_addr_1_reg_3754(4 downto 0) <= "00001";
data_array_addr_3_reg_3764(4 downto 0) <= "00011";
data_array_addr_5_reg_3769(4 downto 0) <= "00101";
data_array_addr_6_reg_3774(4 downto 0) <= "00110";
data_array_addr_7_reg_3779(4 downto 0) <= "00111";
data_array_addr_8_reg_3784(4 downto 0) <= "01000";
data_array_addr_9_reg_3789(4 downto 0) <= "01001";
data_array_addr_10_reg_3794(4 downto 0) <= "01010";
data_array_addr_11_reg_3799(4 downto 0) <= "01011";
data_array_addr_12_reg_3804(4 downto 0) <= "01100";
data_array_addr_13_reg_3809(4 downto 0) <= "01101";
data_array_addr_14_reg_3814(4 downto 0) <= "01110";
data_array_addr_15_reg_3819(4 downto 0) <= "01111";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ins_TVALID, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it82, ap_reg_ppiten_pp0_it83, ap_sig_ioackin_outs_TREADY, exitcond2_fu_2840_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st7_fsm_6 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st8_fsm_7 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st10_fsm_9 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st11_fsm_10;
else
ap_NS_fsm <= ap_ST_st10_fsm_9;
end if;
when ap_ST_st11_fsm_10 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
else
ap_NS_fsm <= ap_ST_st11_fsm_10;
end if;
when ap_ST_st12_fsm_11 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st13_fsm_12;
else
ap_NS_fsm <= ap_ST_st12_fsm_11;
end if;
when ap_ST_st13_fsm_12 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st14_fsm_13 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
else
ap_NS_fsm <= ap_ST_st14_fsm_13;
end if;
when ap_ST_st15_fsm_14 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st16_fsm_15;
else
ap_NS_fsm <= ap_ST_st15_fsm_14;
end if;
when ap_ST_st16_fsm_15 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st16_fsm_15;
end if;
when ap_ST_st17_fsm_16 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st17_fsm_16;
end if;
when ap_ST_st18_fsm_17 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st19_fsm_18 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st19_fsm_18;
end if;
when ap_ST_st20_fsm_19 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
else
ap_NS_fsm <= ap_ST_st20_fsm_19;
end if;
when ap_ST_st21_fsm_20 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st22_fsm_21;
else
ap_NS_fsm <= ap_ST_st21_fsm_20;
end if;
when ap_ST_st22_fsm_21 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st23_fsm_22;
else
ap_NS_fsm <= ap_ST_st22_fsm_21;
end if;
when ap_ST_st23_fsm_22 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st23_fsm_22;
end if;
when ap_ST_st24_fsm_23 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st25_fsm_24;
else
ap_NS_fsm <= ap_ST_st24_fsm_23;
end if;
when ap_ST_st25_fsm_24 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st26_fsm_25;
else
ap_NS_fsm <= ap_ST_st25_fsm_24;
end if;
when ap_ST_st26_fsm_25 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st27_fsm_26;
else
ap_NS_fsm <= ap_ST_st26_fsm_25;
end if;
when ap_ST_st27_fsm_26 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st28_fsm_27;
else
ap_NS_fsm <= ap_ST_st27_fsm_26;
end if;
when ap_ST_st28_fsm_27 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st29_fsm_28;
else
ap_NS_fsm <= ap_ST_st28_fsm_27;
end if;
when ap_ST_st29_fsm_28 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
else
ap_NS_fsm <= ap_ST_st29_fsm_28;
end if;
when ap_ST_st30_fsm_29 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st31_fsm_30;
else
ap_NS_fsm <= ap_ST_st30_fsm_29;
end if;
when ap_ST_st31_fsm_30 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st32_fsm_31;
else
ap_NS_fsm <= ap_ST_st31_fsm_30;
end if;
when ap_ST_st32_fsm_31 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st33_fsm_32;
else
ap_NS_fsm <= ap_ST_st32_fsm_31;
end if;
when ap_ST_st33_fsm_32 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st34_fsm_33;
else
ap_NS_fsm <= ap_ST_st33_fsm_32;
end if;
when ap_ST_st34_fsm_33 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st35_fsm_34;
else
ap_NS_fsm <= ap_ST_st34_fsm_33;
end if;
when ap_ST_st35_fsm_34 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st36_fsm_35;
else
ap_NS_fsm <= ap_ST_st35_fsm_34;
end if;
when ap_ST_st36_fsm_35 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st37_fsm_36;
else
ap_NS_fsm <= ap_ST_st36_fsm_35;
end if;
when ap_ST_st37_fsm_36 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st38_fsm_37;
else
ap_NS_fsm <= ap_ST_st37_fsm_36;
end if;
when ap_ST_st38_fsm_37 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st39_fsm_38;
else
ap_NS_fsm <= ap_ST_st38_fsm_37;
end if;
when ap_ST_st39_fsm_38 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st39_fsm_38;
end if;
when ap_ST_st40_fsm_39 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st41_fsm_40;
else
ap_NS_fsm <= ap_ST_st40_fsm_39;
end if;
when ap_ST_st41_fsm_40 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st42_fsm_41;
else
ap_NS_fsm <= ap_ST_st41_fsm_40;
end if;
when ap_ST_st42_fsm_41 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st43_fsm_42;
else
ap_NS_fsm <= ap_ST_st42_fsm_41;
end if;
when ap_ST_st43_fsm_42 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st44_fsm_43;
else
ap_NS_fsm <= ap_ST_st43_fsm_42;
end if;
when ap_ST_st44_fsm_43 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st45_fsm_44;
else
ap_NS_fsm <= ap_ST_st44_fsm_43;
end if;
when ap_ST_st45_fsm_44 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st46_fsm_45;
else
ap_NS_fsm <= ap_ST_st45_fsm_44;
end if;
when ap_ST_st46_fsm_45 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st47_fsm_46;
else
ap_NS_fsm <= ap_ST_st46_fsm_45;
end if;
when ap_ST_st47_fsm_46 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st48_fsm_47;
else
ap_NS_fsm <= ap_ST_st47_fsm_46;
end if;
when ap_ST_st48_fsm_47 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st49_fsm_48;
else
ap_NS_fsm <= ap_ST_st48_fsm_47;
end if;
when ap_ST_st49_fsm_48 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st50_fsm_49;
else
ap_NS_fsm <= ap_ST_st49_fsm_48;
end if;
when ap_ST_st50_fsm_49 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st51_fsm_50;
else
ap_NS_fsm <= ap_ST_st50_fsm_49;
end if;
when ap_ST_st51_fsm_50 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st52_fsm_51;
else
ap_NS_fsm <= ap_ST_st51_fsm_50;
end if;
when ap_ST_st52_fsm_51 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st53_fsm_52;
else
ap_NS_fsm <= ap_ST_st52_fsm_51;
end if;
when ap_ST_st53_fsm_52 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st54_fsm_53;
else
ap_NS_fsm <= ap_ST_st53_fsm_52;
end if;
when ap_ST_st54_fsm_53 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st55_fsm_54;
else
ap_NS_fsm <= ap_ST_st54_fsm_53;
end if;
when ap_ST_st55_fsm_54 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st56_fsm_55;
else
ap_NS_fsm <= ap_ST_st55_fsm_54;
end if;
when ap_ST_st56_fsm_55 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st57_fsm_56;
else
ap_NS_fsm <= ap_ST_st56_fsm_55;
end if;
when ap_ST_st57_fsm_56 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st58_fsm_57;
else
ap_NS_fsm <= ap_ST_st57_fsm_56;
end if;
when ap_ST_st58_fsm_57 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st59_fsm_58;
else
ap_NS_fsm <= ap_ST_st58_fsm_57;
end if;
when ap_ST_st59_fsm_58 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st60_fsm_59;
else
ap_NS_fsm <= ap_ST_st59_fsm_58;
end if;
when ap_ST_st60_fsm_59 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st61_fsm_60;
else
ap_NS_fsm <= ap_ST_st60_fsm_59;
end if;
when ap_ST_st61_fsm_60 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st62_fsm_61;
else
ap_NS_fsm <= ap_ST_st61_fsm_60;
end if;
when ap_ST_st62_fsm_61 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st63_fsm_62;
else
ap_NS_fsm <= ap_ST_st62_fsm_61;
end if;
when ap_ST_st63_fsm_62 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st64_fsm_63;
else
ap_NS_fsm <= ap_ST_st63_fsm_62;
end if;
when ap_ST_st64_fsm_63 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st65_fsm_64;
else
ap_NS_fsm <= ap_ST_st64_fsm_63;
end if;
when ap_ST_st65_fsm_64 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st66_fsm_65;
else
ap_NS_fsm <= ap_ST_st65_fsm_64;
end if;
when ap_ST_st66_fsm_65 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st67_fsm_66;
else
ap_NS_fsm <= ap_ST_st66_fsm_65;
end if;
when ap_ST_st67_fsm_66 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st68_fsm_67;
else
ap_NS_fsm <= ap_ST_st67_fsm_66;
end if;
when ap_ST_st68_fsm_67 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st69_fsm_68;
else
ap_NS_fsm <= ap_ST_st68_fsm_67;
end if;
when ap_ST_st69_fsm_68 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st70_fsm_69;
else
ap_NS_fsm <= ap_ST_st69_fsm_68;
end if;
when ap_ST_st70_fsm_69 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st71_fsm_70;
else
ap_NS_fsm <= ap_ST_st70_fsm_69;
end if;
when ap_ST_st71_fsm_70 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st72_fsm_71;
else
ap_NS_fsm <= ap_ST_st71_fsm_70;
end if;
when ap_ST_st72_fsm_71 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st73_fsm_72;
else
ap_NS_fsm <= ap_ST_st72_fsm_71;
end if;
when ap_ST_st73_fsm_72 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st74_fsm_73;
else
ap_NS_fsm <= ap_ST_st73_fsm_72;
end if;
when ap_ST_st74_fsm_73 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st75_fsm_74;
else
ap_NS_fsm <= ap_ST_st74_fsm_73;
end if;
when ap_ST_st75_fsm_74 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st76_fsm_75;
else
ap_NS_fsm <= ap_ST_st75_fsm_74;
end if;
when ap_ST_st76_fsm_75 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st77_fsm_76;
else
ap_NS_fsm <= ap_ST_st76_fsm_75;
end if;
when ap_ST_st77_fsm_76 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st78_fsm_77;
else
ap_NS_fsm <= ap_ST_st77_fsm_76;
end if;
when ap_ST_st78_fsm_77 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st79_fsm_78;
else
ap_NS_fsm <= ap_ST_st78_fsm_77;
end if;
when ap_ST_st79_fsm_78 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st79_fsm_78;
end if;
when ap_ST_st80_fsm_79 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st81_fsm_80;
else
ap_NS_fsm <= ap_ST_st80_fsm_79;
end if;
when ap_ST_st81_fsm_80 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st82_fsm_81;
else
ap_NS_fsm <= ap_ST_st81_fsm_80;
end if;
when ap_ST_st82_fsm_81 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st83_fsm_82;
else
ap_NS_fsm <= ap_ST_st82_fsm_81;
end if;
when ap_ST_st83_fsm_82 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st84_fsm_83;
else
ap_NS_fsm <= ap_ST_st83_fsm_82;
end if;
when ap_ST_st84_fsm_83 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st85_fsm_84;
else
ap_NS_fsm <= ap_ST_st84_fsm_83;
end if;
when ap_ST_st85_fsm_84 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st86_fsm_85;
else
ap_NS_fsm <= ap_ST_st85_fsm_84;
end if;
when ap_ST_st86_fsm_85 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st87_fsm_86;
else
ap_NS_fsm <= ap_ST_st86_fsm_85;
end if;
when ap_ST_st87_fsm_86 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st88_fsm_87;
else
ap_NS_fsm <= ap_ST_st87_fsm_86;
end if;
when ap_ST_st88_fsm_87 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st89_fsm_88;
else
ap_NS_fsm <= ap_ST_st88_fsm_87;
end if;
when ap_ST_st89_fsm_88 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st90_fsm_89;
else
ap_NS_fsm <= ap_ST_st89_fsm_88;
end if;
when ap_ST_st90_fsm_89 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st91_fsm_90;
else
ap_NS_fsm <= ap_ST_st90_fsm_89;
end if;
when ap_ST_st91_fsm_90 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st92_fsm_91;
else
ap_NS_fsm <= ap_ST_st91_fsm_90;
end if;
when ap_ST_st92_fsm_91 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st92_fsm_91;
end if;
when ap_ST_st93_fsm_92 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st94_fsm_93;
else
ap_NS_fsm <= ap_ST_st93_fsm_92;
end if;
when ap_ST_st94_fsm_93 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st95_fsm_94;
else
ap_NS_fsm <= ap_ST_st94_fsm_93;
end if;
when ap_ST_st95_fsm_94 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st96_fsm_95;
else
ap_NS_fsm <= ap_ST_st95_fsm_94;
end if;
when ap_ST_st96_fsm_95 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st97_fsm_96;
else
ap_NS_fsm <= ap_ST_st96_fsm_95;
end if;
when ap_ST_st97_fsm_96 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st98_fsm_97;
else
ap_NS_fsm <= ap_ST_st97_fsm_96;
end if;
when ap_ST_st98_fsm_97 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st99_fsm_98;
else
ap_NS_fsm <= ap_ST_st98_fsm_97;
end if;
when ap_ST_st99_fsm_98 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st100_fsm_99;
else
ap_NS_fsm <= ap_ST_st99_fsm_98;
end if;
when ap_ST_st100_fsm_99 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st101_fsm_100;
else
ap_NS_fsm <= ap_ST_st100_fsm_99;
end if;
when ap_ST_st101_fsm_100 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st102_fsm_101;
else
ap_NS_fsm <= ap_ST_st101_fsm_100;
end if;
when ap_ST_st102_fsm_101 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st103_fsm_102;
else
ap_NS_fsm <= ap_ST_st102_fsm_101;
end if;
when ap_ST_st103_fsm_102 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st104_fsm_103;
else
ap_NS_fsm <= ap_ST_st103_fsm_102;
end if;
when ap_ST_st104_fsm_103 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st105_fsm_104;
else
ap_NS_fsm <= ap_ST_st104_fsm_103;
end if;
when ap_ST_st105_fsm_104 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st106_fsm_105;
else
ap_NS_fsm <= ap_ST_st105_fsm_104;
end if;
when ap_ST_st106_fsm_105 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st107_fsm_106;
else
ap_NS_fsm <= ap_ST_st106_fsm_105;
end if;
when ap_ST_st107_fsm_106 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st108_fsm_107;
else
ap_NS_fsm <= ap_ST_st107_fsm_106;
end if;
when ap_ST_st108_fsm_107 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st109_fsm_108;
else
ap_NS_fsm <= ap_ST_st108_fsm_107;
end if;
when ap_ST_st109_fsm_108 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st110_fsm_109;
else
ap_NS_fsm <= ap_ST_st109_fsm_108;
end if;
when ap_ST_st110_fsm_109 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st111_fsm_110;
else
ap_NS_fsm <= ap_ST_st110_fsm_109;
end if;
when ap_ST_st111_fsm_110 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st112_fsm_111;
else
ap_NS_fsm <= ap_ST_st111_fsm_110;
end if;
when ap_ST_st112_fsm_111 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st113_fsm_112;
else
ap_NS_fsm <= ap_ST_st112_fsm_111;
end if;
when ap_ST_st113_fsm_112 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st114_fsm_113;
else
ap_NS_fsm <= ap_ST_st113_fsm_112;
end if;
when ap_ST_st114_fsm_113 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st115_fsm_114;
else
ap_NS_fsm <= ap_ST_st114_fsm_113;
end if;
when ap_ST_st115_fsm_114 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st116_fsm_115;
else
ap_NS_fsm <= ap_ST_st115_fsm_114;
end if;
when ap_ST_st116_fsm_115 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st117_fsm_116;
else
ap_NS_fsm <= ap_ST_st116_fsm_115;
end if;
when ap_ST_st117_fsm_116 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st118_fsm_117;
else
ap_NS_fsm <= ap_ST_st117_fsm_116;
end if;
when ap_ST_st118_fsm_117 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st119_fsm_118;
else
ap_NS_fsm <= ap_ST_st118_fsm_117;
end if;
when ap_ST_st119_fsm_118 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st120_fsm_119;
else
ap_NS_fsm <= ap_ST_st119_fsm_118;
end if;
when ap_ST_st120_fsm_119 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st121_fsm_120;
else
ap_NS_fsm <= ap_ST_st120_fsm_119;
end if;
when ap_ST_st121_fsm_120 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st122_fsm_121;
else
ap_NS_fsm <= ap_ST_st121_fsm_120;
end if;
when ap_ST_st122_fsm_121 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st123_fsm_122;
else
ap_NS_fsm <= ap_ST_st122_fsm_121;
end if;
when ap_ST_st123_fsm_122 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st124_fsm_123;
else
ap_NS_fsm <= ap_ST_st123_fsm_122;
end if;
when ap_ST_st124_fsm_123 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st125_fsm_124;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st125_fsm_124 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st126_fsm_125;
else
ap_NS_fsm <= ap_ST_st125_fsm_124;
end if;
when ap_ST_st126_fsm_125 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st127_fsm_126;
else
ap_NS_fsm <= ap_ST_st126_fsm_125;
end if;
when ap_ST_st127_fsm_126 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st128_fsm_127;
else
ap_NS_fsm <= ap_ST_st127_fsm_126;
end if;
when ap_ST_st128_fsm_127 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st129_fsm_128;
else
ap_NS_fsm <= ap_ST_st128_fsm_127;
end if;
when ap_ST_st129_fsm_128 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st130_fsm_129;
else
ap_NS_fsm <= ap_ST_st129_fsm_128;
end if;
when ap_ST_st130_fsm_129 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st131_fsm_130;
else
ap_NS_fsm <= ap_ST_st130_fsm_129;
end if;
when ap_ST_st131_fsm_130 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st132_fsm_131;
else
ap_NS_fsm <= ap_ST_st131_fsm_130;
end if;
when ap_ST_st132_fsm_131 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st133_fsm_132;
else
ap_NS_fsm <= ap_ST_st132_fsm_131;
end if;
when ap_ST_st133_fsm_132 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st134_fsm_133;
else
ap_NS_fsm <= ap_ST_st133_fsm_132;
end if;
when ap_ST_st134_fsm_133 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st135_fsm_134;
else
ap_NS_fsm <= ap_ST_st134_fsm_133;
end if;
when ap_ST_st135_fsm_134 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st136_fsm_135;
else
ap_NS_fsm <= ap_ST_st135_fsm_134;
end if;
when ap_ST_st136_fsm_135 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st137_fsm_136;
else
ap_NS_fsm <= ap_ST_st136_fsm_135;
end if;
when ap_ST_st137_fsm_136 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st138_fsm_137;
else
ap_NS_fsm <= ap_ST_st137_fsm_136;
end if;
when ap_ST_st138_fsm_137 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st139_fsm_138;
else
ap_NS_fsm <= ap_ST_st138_fsm_137;
end if;
when ap_ST_st139_fsm_138 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st140_fsm_139;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st140_fsm_139 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st141_fsm_140;
else
ap_NS_fsm <= ap_ST_st140_fsm_139;
end if;
when ap_ST_st141_fsm_140 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st142_fsm_141;
else
ap_NS_fsm <= ap_ST_st141_fsm_140;
end if;
when ap_ST_st142_fsm_141 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st142_fsm_141;
end if;
when ap_ST_st143_fsm_142 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st144_fsm_143 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st145_fsm_144;
else
ap_NS_fsm <= ap_ST_st144_fsm_143;
end if;
when ap_ST_st145_fsm_144 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st146_fsm_145;
else
ap_NS_fsm <= ap_ST_st145_fsm_144;
end if;
when ap_ST_st146_fsm_145 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
else
ap_NS_fsm <= ap_ST_st146_fsm_145;
end if;
when ap_ST_st147_fsm_146 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st147_fsm_146;
end if;
when ap_ST_st148_fsm_147 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st149_fsm_148;
end if;
when ap_ST_st150_fsm_149 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st151_fsm_150;
else
ap_NS_fsm <= ap_ST_st150_fsm_149;
end if;
when ap_ST_st151_fsm_150 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st152_fsm_151;
else
ap_NS_fsm <= ap_ST_st151_fsm_150;
end if;
when ap_ST_st152_fsm_151 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st153_fsm_152;
else
ap_NS_fsm <= ap_ST_st152_fsm_151;
end if;
when ap_ST_st153_fsm_152 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st154_fsm_153 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st155_fsm_154;
else
ap_NS_fsm <= ap_ST_st154_fsm_153;
end if;
when ap_ST_st155_fsm_154 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st156_fsm_155;
else
ap_NS_fsm <= ap_ST_st155_fsm_154;
end if;
when ap_ST_st156_fsm_155 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st157_fsm_156;
else
ap_NS_fsm <= ap_ST_st156_fsm_155;
end if;
when ap_ST_st157_fsm_156 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st158_fsm_157;
else
ap_NS_fsm <= ap_ST_st157_fsm_156;
end if;
when ap_ST_st158_fsm_157 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st159_fsm_158;
else
ap_NS_fsm <= ap_ST_st158_fsm_157;
end if;
when ap_ST_st159_fsm_158 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st160_fsm_159;
else
ap_NS_fsm <= ap_ST_st159_fsm_158;
end if;
when ap_ST_st160_fsm_159 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st161_fsm_160;
else
ap_NS_fsm <= ap_ST_st160_fsm_159;
end if;
when ap_ST_st161_fsm_160 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st162_fsm_161;
else
ap_NS_fsm <= ap_ST_st161_fsm_160;
end if;
when ap_ST_st162_fsm_161 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st163_fsm_162;
else
ap_NS_fsm <= ap_ST_st162_fsm_161;
end if;
when ap_ST_st163_fsm_162 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st164_fsm_163;
else
ap_NS_fsm <= ap_ST_st163_fsm_162;
end if;
when ap_ST_st164_fsm_163 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st165_fsm_164;
else
ap_NS_fsm <= ap_ST_st164_fsm_163;
end if;
when ap_ST_st165_fsm_164 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st166_fsm_165;
else
ap_NS_fsm <= ap_ST_st165_fsm_164;
end if;
when ap_ST_st166_fsm_165 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st167_fsm_166;
else
ap_NS_fsm <= ap_ST_st166_fsm_165;
end if;
when ap_ST_st167_fsm_166 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st168_fsm_167;
else
ap_NS_fsm <= ap_ST_st167_fsm_166;
end if;
when ap_ST_st168_fsm_167 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st169_fsm_168;
else
ap_NS_fsm <= ap_ST_st168_fsm_167;
end if;
when ap_ST_st169_fsm_168 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st170_fsm_169;
else
ap_NS_fsm <= ap_ST_st169_fsm_168;
end if;
when ap_ST_st170_fsm_169 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st171_fsm_170;
else
ap_NS_fsm <= ap_ST_st170_fsm_169;
end if;
when ap_ST_st171_fsm_170 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st172_fsm_171;
else
ap_NS_fsm <= ap_ST_st171_fsm_170;
end if;
when ap_ST_st172_fsm_171 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st173_fsm_172;
else
ap_NS_fsm <= ap_ST_st172_fsm_171;
end if;
when ap_ST_st173_fsm_172 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st174_fsm_173;
else
ap_NS_fsm <= ap_ST_st173_fsm_172;
end if;
when ap_ST_st174_fsm_173 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st175_fsm_174;
else
ap_NS_fsm <= ap_ST_st174_fsm_173;
end if;
when ap_ST_st175_fsm_174 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st176_fsm_175;
else
ap_NS_fsm <= ap_ST_st175_fsm_174;
end if;
when ap_ST_st176_fsm_175 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st177_fsm_176;
else
ap_NS_fsm <= ap_ST_st176_fsm_175;
end if;
when ap_ST_st177_fsm_176 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st178_fsm_177;
else
ap_NS_fsm <= ap_ST_st177_fsm_176;
end if;
when ap_ST_st178_fsm_177 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st179_fsm_178;
else
ap_NS_fsm <= ap_ST_st178_fsm_177;
end if;
when ap_ST_st179_fsm_178 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st180_fsm_179;
else
ap_NS_fsm <= ap_ST_st179_fsm_178;
end if;
when ap_ST_st180_fsm_179 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st181_fsm_180;
else
ap_NS_fsm <= ap_ST_st180_fsm_179;
end if;
when ap_ST_st181_fsm_180 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st182_fsm_181;
else
ap_NS_fsm <= ap_ST_st181_fsm_180;
end if;
when ap_ST_st182_fsm_181 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st183_fsm_182;
else
ap_NS_fsm <= ap_ST_st182_fsm_181;
end if;
when ap_ST_st183_fsm_182 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st184_fsm_183;
else
ap_NS_fsm <= ap_ST_st183_fsm_182;
end if;
when ap_ST_st184_fsm_183 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st185_fsm_184;
else
ap_NS_fsm <= ap_ST_st184_fsm_183;
end if;
when ap_ST_st185_fsm_184 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st186_fsm_185;
else
ap_NS_fsm <= ap_ST_st185_fsm_184;
end if;
when ap_ST_st186_fsm_185 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st187_fsm_186;
else
ap_NS_fsm <= ap_ST_st186_fsm_185;
end if;
when ap_ST_st187_fsm_186 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st188_fsm_187;
else
ap_NS_fsm <= ap_ST_st187_fsm_186;
end if;
when ap_ST_st188_fsm_187 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st189_fsm_188;
else
ap_NS_fsm <= ap_ST_st188_fsm_187;
end if;
when ap_ST_st189_fsm_188 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st190_fsm_189;
else
ap_NS_fsm <= ap_ST_st189_fsm_188;
end if;
when ap_ST_st190_fsm_189 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st191_fsm_190;
else
ap_NS_fsm <= ap_ST_st190_fsm_189;
end if;
when ap_ST_st191_fsm_190 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st192_fsm_191;
else
ap_NS_fsm <= ap_ST_st191_fsm_190;
end if;
when ap_ST_st192_fsm_191 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st193_fsm_192;
else
ap_NS_fsm <= ap_ST_st192_fsm_191;
end if;
when ap_ST_st193_fsm_192 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st194_fsm_193;
else
ap_NS_fsm <= ap_ST_st193_fsm_192;
end if;
when ap_ST_st194_fsm_193 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st195_fsm_194;
else
ap_NS_fsm <= ap_ST_st194_fsm_193;
end if;
when ap_ST_st195_fsm_194 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st196_fsm_195;
else
ap_NS_fsm <= ap_ST_st195_fsm_194;
end if;
when ap_ST_st196_fsm_195 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st197_fsm_196;
else
ap_NS_fsm <= ap_ST_st196_fsm_195;
end if;
when ap_ST_st197_fsm_196 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st198_fsm_197;
else
ap_NS_fsm <= ap_ST_st197_fsm_196;
end if;
when ap_ST_st198_fsm_197 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st199_fsm_198;
else
ap_NS_fsm <= ap_ST_st198_fsm_197;
end if;
when ap_ST_st199_fsm_198 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st200_fsm_199;
else
ap_NS_fsm <= ap_ST_st199_fsm_198;
end if;
when ap_ST_st200_fsm_199 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st201_fsm_200;
else
ap_NS_fsm <= ap_ST_st200_fsm_199;
end if;
when ap_ST_st201_fsm_200 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st202_fsm_201;
else
ap_NS_fsm <= ap_ST_st201_fsm_200;
end if;
when ap_ST_st202_fsm_201 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st203_fsm_202;
else
ap_NS_fsm <= ap_ST_st202_fsm_201;
end if;
when ap_ST_st203_fsm_202 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st204_fsm_203;
else
ap_NS_fsm <= ap_ST_st203_fsm_202;
end if;
when ap_ST_st204_fsm_203 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st205_fsm_204;
else
ap_NS_fsm <= ap_ST_st204_fsm_203;
end if;
when ap_ST_st205_fsm_204 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st206_fsm_205;
else
ap_NS_fsm <= ap_ST_st205_fsm_204;
end if;
when ap_ST_st206_fsm_205 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st207_fsm_206;
else
ap_NS_fsm <= ap_ST_st206_fsm_205;
end if;
when ap_ST_st207_fsm_206 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st208_fsm_207;
else
ap_NS_fsm <= ap_ST_st207_fsm_206;
end if;
when ap_ST_st208_fsm_207 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st209_fsm_208;
else
ap_NS_fsm <= ap_ST_st208_fsm_207;
end if;
when ap_ST_st209_fsm_208 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st210_fsm_209;
else
ap_NS_fsm <= ap_ST_st209_fsm_208;
end if;
when ap_ST_st210_fsm_209 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st211_fsm_210;
else
ap_NS_fsm <= ap_ST_st210_fsm_209;
end if;
when ap_ST_st211_fsm_210 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st212_fsm_211;
else
ap_NS_fsm <= ap_ST_st211_fsm_210;
end if;
when ap_ST_st212_fsm_211 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st213_fsm_212;
else
ap_NS_fsm <= ap_ST_st212_fsm_211;
end if;
when ap_ST_st213_fsm_212 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st214_fsm_213;
else
ap_NS_fsm <= ap_ST_st213_fsm_212;
end if;
when ap_ST_st214_fsm_213 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st215_fsm_214;
else
ap_NS_fsm <= ap_ST_st214_fsm_213;
end if;
when ap_ST_st215_fsm_214 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st216_fsm_215;
else
ap_NS_fsm <= ap_ST_st215_fsm_214;
end if;
when ap_ST_st216_fsm_215 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st217_fsm_216;
else
ap_NS_fsm <= ap_ST_st216_fsm_215;
end if;
when ap_ST_st217_fsm_216 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st218_fsm_217;
else
ap_NS_fsm <= ap_ST_st217_fsm_216;
end if;
when ap_ST_st218_fsm_217 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st219_fsm_218;
else
ap_NS_fsm <= ap_ST_st218_fsm_217;
end if;
when ap_ST_st219_fsm_218 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st220_fsm_219;
else
ap_NS_fsm <= ap_ST_st219_fsm_218;
end if;
when ap_ST_st220_fsm_219 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st221_fsm_220;
else
ap_NS_fsm <= ap_ST_st220_fsm_219;
end if;
when ap_ST_st221_fsm_220 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st222_fsm_221;
else
ap_NS_fsm <= ap_ST_st221_fsm_220;
end if;
when ap_ST_st222_fsm_221 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st223_fsm_222;
else
ap_NS_fsm <= ap_ST_st222_fsm_221;
end if;
when ap_ST_st223_fsm_222 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st224_fsm_223;
else
ap_NS_fsm <= ap_ST_st223_fsm_222;
end if;
when ap_ST_st224_fsm_223 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st225_fsm_224;
else
ap_NS_fsm <= ap_ST_st224_fsm_223;
end if;
when ap_ST_st225_fsm_224 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st226_fsm_225;
else
ap_NS_fsm <= ap_ST_st225_fsm_224;
end if;
when ap_ST_st226_fsm_225 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st227_fsm_226;
else
ap_NS_fsm <= ap_ST_st226_fsm_225;
end if;
when ap_ST_st227_fsm_226 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st228_fsm_227;
else
ap_NS_fsm <= ap_ST_st227_fsm_226;
end if;
when ap_ST_st228_fsm_227 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st229_fsm_228;
else
ap_NS_fsm <= ap_ST_st228_fsm_227;
end if;
when ap_ST_st229_fsm_228 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st230_fsm_229;
else
ap_NS_fsm <= ap_ST_st229_fsm_228;
end if;
when ap_ST_st230_fsm_229 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st231_fsm_230;
else
ap_NS_fsm <= ap_ST_st230_fsm_229;
end if;
when ap_ST_st231_fsm_230 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st232_fsm_231;
else
ap_NS_fsm <= ap_ST_st231_fsm_230;
end if;
when ap_ST_st232_fsm_231 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st233_fsm_232;
else
ap_NS_fsm <= ap_ST_st232_fsm_231;
end if;
when ap_ST_st233_fsm_232 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st234_fsm_233;
else
ap_NS_fsm <= ap_ST_st233_fsm_232;
end if;
when ap_ST_st234_fsm_233 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st235_fsm_234;
else
ap_NS_fsm <= ap_ST_st234_fsm_233;
end if;
when ap_ST_st235_fsm_234 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st236_fsm_235;
else
ap_NS_fsm <= ap_ST_st235_fsm_234;
end if;
when ap_ST_st236_fsm_235 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st237_fsm_236;
else
ap_NS_fsm <= ap_ST_st236_fsm_235;
end if;
when ap_ST_st237_fsm_236 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st238_fsm_237;
else
ap_NS_fsm <= ap_ST_st237_fsm_236;
end if;
when ap_ST_st238_fsm_237 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st239_fsm_238;
else
ap_NS_fsm <= ap_ST_st238_fsm_237;
end if;
when ap_ST_st239_fsm_238 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st240_fsm_239;
else
ap_NS_fsm <= ap_ST_st239_fsm_238;
end if;
when ap_ST_st240_fsm_239 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st241_fsm_240;
else
ap_NS_fsm <= ap_ST_st240_fsm_239;
end if;
when ap_ST_st241_fsm_240 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st242_fsm_241;
else
ap_NS_fsm <= ap_ST_st241_fsm_240;
end if;
when ap_ST_st242_fsm_241 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st243_fsm_242;
else
ap_NS_fsm <= ap_ST_st242_fsm_241;
end if;
when ap_ST_st243_fsm_242 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st244_fsm_243;
else
ap_NS_fsm <= ap_ST_st243_fsm_242;
end if;
when ap_ST_st244_fsm_243 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st245_fsm_244;
else
ap_NS_fsm <= ap_ST_st244_fsm_243;
end if;
when ap_ST_st245_fsm_244 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st246_fsm_245;
else
ap_NS_fsm <= ap_ST_st245_fsm_244;
end if;
when ap_ST_st246_fsm_245 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st247_fsm_246;
else
ap_NS_fsm <= ap_ST_st246_fsm_245;
end if;
when ap_ST_st247_fsm_246 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st248_fsm_247;
else
ap_NS_fsm <= ap_ST_st247_fsm_246;
end if;
when ap_ST_st248_fsm_247 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st249_fsm_248;
else
ap_NS_fsm <= ap_ST_st248_fsm_247;
end if;
when ap_ST_st249_fsm_248 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st250_fsm_249;
else
ap_NS_fsm <= ap_ST_st249_fsm_248;
end if;
when ap_ST_st250_fsm_249 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st251_fsm_250;
else
ap_NS_fsm <= ap_ST_st250_fsm_249;
end if;
when ap_ST_st251_fsm_250 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st252_fsm_251;
else
ap_NS_fsm <= ap_ST_st251_fsm_250;
end if;
when ap_ST_st252_fsm_251 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st253_fsm_252;
else
ap_NS_fsm <= ap_ST_st252_fsm_251;
end if;
when ap_ST_st253_fsm_252 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st254_fsm_253;
else
ap_NS_fsm <= ap_ST_st253_fsm_252;
end if;
when ap_ST_st254_fsm_253 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st255_fsm_254;
else
ap_NS_fsm <= ap_ST_st254_fsm_253;
end if;
when ap_ST_st255_fsm_254 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st256_fsm_255;
else
ap_NS_fsm <= ap_ST_st255_fsm_254;
end if;
when ap_ST_st256_fsm_255 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st257_fsm_256;
else
ap_NS_fsm <= ap_ST_st256_fsm_255;
end if;
when ap_ST_st257_fsm_256 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st258_fsm_257;
else
ap_NS_fsm <= ap_ST_st257_fsm_256;
end if;
when ap_ST_st258_fsm_257 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st259_fsm_258;
else
ap_NS_fsm <= ap_ST_st258_fsm_257;
end if;
when ap_ST_st259_fsm_258 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st260_fsm_259;
else
ap_NS_fsm <= ap_ST_st259_fsm_258;
end if;
when ap_ST_st260_fsm_259 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st261_fsm_260;
else
ap_NS_fsm <= ap_ST_st260_fsm_259;
end if;
when ap_ST_st261_fsm_260 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st262_fsm_261;
else
ap_NS_fsm <= ap_ST_st261_fsm_260;
end if;
when ap_ST_st262_fsm_261 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st263_fsm_262;
else
ap_NS_fsm <= ap_ST_st262_fsm_261;
end if;
when ap_ST_st263_fsm_262 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st264_fsm_263;
else
ap_NS_fsm <= ap_ST_st263_fsm_262;
end if;
when ap_ST_st264_fsm_263 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st265_fsm_264;
else
ap_NS_fsm <= ap_ST_st264_fsm_263;
end if;
when ap_ST_st265_fsm_264 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st266_fsm_265;
else
ap_NS_fsm <= ap_ST_st265_fsm_264;
end if;
when ap_ST_st266_fsm_265 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st267_fsm_266;
else
ap_NS_fsm <= ap_ST_st266_fsm_265;
end if;
when ap_ST_st267_fsm_266 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st268_fsm_267;
else
ap_NS_fsm <= ap_ST_st267_fsm_266;
end if;
when ap_ST_st268_fsm_267 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st269_fsm_268;
else
ap_NS_fsm <= ap_ST_st268_fsm_267;
end if;
when ap_ST_st269_fsm_268 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st270_fsm_269;
else
ap_NS_fsm <= ap_ST_st269_fsm_268;
end if;
when ap_ST_st270_fsm_269 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st271_fsm_270;
else
ap_NS_fsm <= ap_ST_st270_fsm_269;
end if;
when ap_ST_st271_fsm_270 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st272_fsm_271;
else
ap_NS_fsm <= ap_ST_st271_fsm_270;
end if;
when ap_ST_st272_fsm_271 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st273_fsm_272;
else
ap_NS_fsm <= ap_ST_st272_fsm_271;
end if;
when ap_ST_st273_fsm_272 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st274_fsm_273;
else
ap_NS_fsm <= ap_ST_st273_fsm_272;
end if;
when ap_ST_st274_fsm_273 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st275_fsm_274;
else
ap_NS_fsm <= ap_ST_st274_fsm_273;
end if;
when ap_ST_st275_fsm_274 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st276_fsm_275;
else
ap_NS_fsm <= ap_ST_st275_fsm_274;
end if;
when ap_ST_st276_fsm_275 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st277_fsm_276;
else
ap_NS_fsm <= ap_ST_st276_fsm_275;
end if;
when ap_ST_st277_fsm_276 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st278_fsm_277;
else
ap_NS_fsm <= ap_ST_st277_fsm_276;
end if;
when ap_ST_st278_fsm_277 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st279_fsm_278;
else
ap_NS_fsm <= ap_ST_st278_fsm_277;
end if;
when ap_ST_st279_fsm_278 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st280_fsm_279;
else
ap_NS_fsm <= ap_ST_st279_fsm_278;
end if;
when ap_ST_st280_fsm_279 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st281_fsm_280;
else
ap_NS_fsm <= ap_ST_st280_fsm_279;
end if;
when ap_ST_st281_fsm_280 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st282_fsm_281;
else
ap_NS_fsm <= ap_ST_st281_fsm_280;
end if;
when ap_ST_st282_fsm_281 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st283_fsm_282;
else
ap_NS_fsm <= ap_ST_st282_fsm_281;
end if;
when ap_ST_st283_fsm_282 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st284_fsm_283;
else
ap_NS_fsm <= ap_ST_st283_fsm_282;
end if;
when ap_ST_st284_fsm_283 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st285_fsm_284;
else
ap_NS_fsm <= ap_ST_st284_fsm_283;
end if;
when ap_ST_st285_fsm_284 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st286_fsm_285;
else
ap_NS_fsm <= ap_ST_st285_fsm_284;
end if;
when ap_ST_st286_fsm_285 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st287_fsm_286;
else
ap_NS_fsm <= ap_ST_st286_fsm_285;
end if;
when ap_ST_st287_fsm_286 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st288_fsm_287;
else
ap_NS_fsm <= ap_ST_st287_fsm_286;
end if;
when ap_ST_st288_fsm_287 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st289_fsm_288;
else
ap_NS_fsm <= ap_ST_st288_fsm_287;
end if;
when ap_ST_st289_fsm_288 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st290_fsm_289;
else
ap_NS_fsm <= ap_ST_st289_fsm_288;
end if;
when ap_ST_st290_fsm_289 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st291_fsm_290;
else
ap_NS_fsm <= ap_ST_st290_fsm_289;
end if;
when ap_ST_st291_fsm_290 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st292_fsm_291;
else
ap_NS_fsm <= ap_ST_st291_fsm_290;
end if;
when ap_ST_st292_fsm_291 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st293_fsm_292;
else
ap_NS_fsm <= ap_ST_st292_fsm_291;
end if;
when ap_ST_st293_fsm_292 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st294_fsm_293;
else
ap_NS_fsm <= ap_ST_st293_fsm_292;
end if;
when ap_ST_st294_fsm_293 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st295_fsm_294;
else
ap_NS_fsm <= ap_ST_st294_fsm_293;
end if;
when ap_ST_st295_fsm_294 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st296_fsm_295;
else
ap_NS_fsm <= ap_ST_st295_fsm_294;
end if;
when ap_ST_st296_fsm_295 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st297_fsm_296;
else
ap_NS_fsm <= ap_ST_st296_fsm_295;
end if;
when ap_ST_st297_fsm_296 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st298_fsm_297;
else
ap_NS_fsm <= ap_ST_st297_fsm_296;
end if;
when ap_ST_st298_fsm_297 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st299_fsm_298;
else
ap_NS_fsm <= ap_ST_st298_fsm_297;
end if;
when ap_ST_st299_fsm_298 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st300_fsm_299;
else
ap_NS_fsm <= ap_ST_st299_fsm_298;
end if;
when ap_ST_st300_fsm_299 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_300;
else
ap_NS_fsm <= ap_ST_st300_fsm_299;
end if;
when ap_ST_pp0_stg0_fsm_300 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it82)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_300;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) then
ap_NS_fsm <= ap_ST_st385_fsm_301;
else
ap_NS_fsm <= ap_ST_st385_fsm_301;
end if;
when ap_ST_st385_fsm_301 =>
ap_NS_fsm <= ap_ST_st386_fsm_302;
when ap_ST_st386_fsm_302 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st387_fsm_303;
else
ap_NS_fsm <= ap_ST_st386_fsm_302;
end if;
when ap_ST_st387_fsm_303 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st388_fsm_304;
else
ap_NS_fsm <= ap_ST_st387_fsm_303;
end if;
when ap_ST_st388_fsm_304 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st389_fsm_305;
else
ap_NS_fsm <= ap_ST_st388_fsm_304;
end if;
when ap_ST_st389_fsm_305 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st390_fsm_306;
else
ap_NS_fsm <= ap_ST_st389_fsm_305;
end if;
when ap_ST_st390_fsm_306 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st391_fsm_307;
else
ap_NS_fsm <= ap_ST_st390_fsm_306;
end if;
when ap_ST_st391_fsm_307 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st392_fsm_308;
else
ap_NS_fsm <= ap_ST_st391_fsm_307;
end if;
when ap_ST_st392_fsm_308 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st393_fsm_309;
else
ap_NS_fsm <= ap_ST_st392_fsm_308;
end if;
when ap_ST_st393_fsm_309 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st394_fsm_310;
else
ap_NS_fsm <= ap_ST_st393_fsm_309;
end if;
when ap_ST_st394_fsm_310 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st395_fsm_311;
else
ap_NS_fsm <= ap_ST_st394_fsm_310;
end if;
when ap_ST_st395_fsm_311 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st396_fsm_312;
else
ap_NS_fsm <= ap_ST_st395_fsm_311;
end if;
when ap_ST_st396_fsm_312 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st397_fsm_313;
else
ap_NS_fsm <= ap_ST_st396_fsm_312;
end if;
when ap_ST_st397_fsm_313 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st398_fsm_314;
else
ap_NS_fsm <= ap_ST_st397_fsm_313;
end if;
when ap_ST_st398_fsm_314 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st399_fsm_315;
else
ap_NS_fsm <= ap_ST_st398_fsm_314;
end if;
when ap_ST_st399_fsm_315 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st400_fsm_316;
else
ap_NS_fsm <= ap_ST_st399_fsm_315;
end if;
when ap_ST_st400_fsm_316 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st401_fsm_317;
else
ap_NS_fsm <= ap_ST_st400_fsm_316;
end if;
when ap_ST_st401_fsm_317 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st402_fsm_318;
else
ap_NS_fsm <= ap_ST_st401_fsm_317;
end if;
when ap_ST_st402_fsm_318 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st403_fsm_319;
else
ap_NS_fsm <= ap_ST_st402_fsm_318;
end if;
when ap_ST_st403_fsm_319 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st404_fsm_320;
else
ap_NS_fsm <= ap_ST_st403_fsm_319;
end if;
when ap_ST_st404_fsm_320 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st405_fsm_321;
else
ap_NS_fsm <= ap_ST_st404_fsm_320;
end if;
when ap_ST_st405_fsm_321 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st406_fsm_322;
else
ap_NS_fsm <= ap_ST_st405_fsm_321;
end if;
when ap_ST_st406_fsm_322 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st407_fsm_323;
else
ap_NS_fsm <= ap_ST_st406_fsm_322;
end if;
when ap_ST_st407_fsm_323 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st408_fsm_324;
else
ap_NS_fsm <= ap_ST_st407_fsm_323;
end if;
when ap_ST_st408_fsm_324 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st409_fsm_325;
else
ap_NS_fsm <= ap_ST_st408_fsm_324;
end if;
when ap_ST_st409_fsm_325 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st410_fsm_326;
else
ap_NS_fsm <= ap_ST_st409_fsm_325;
end if;
when ap_ST_st410_fsm_326 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st411_fsm_327;
else
ap_NS_fsm <= ap_ST_st410_fsm_326;
end if;
when ap_ST_st411_fsm_327 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st412_fsm_328;
else
ap_NS_fsm <= ap_ST_st411_fsm_327;
end if;
when ap_ST_st412_fsm_328 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st413_fsm_329;
else
ap_NS_fsm <= ap_ST_st412_fsm_328;
end if;
when ap_ST_st413_fsm_329 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st414_fsm_330;
else
ap_NS_fsm <= ap_ST_st413_fsm_329;
end if;
when ap_ST_st414_fsm_330 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st415_fsm_331;
else
ap_NS_fsm <= ap_ST_st414_fsm_330;
end if;
when ap_ST_st415_fsm_331 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st416_fsm_332;
else
ap_NS_fsm <= ap_ST_st415_fsm_331;
end if;
when ap_ST_st416_fsm_332 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st417_fsm_333;
else
ap_NS_fsm <= ap_ST_st416_fsm_332;
end if;
when ap_ST_st417_fsm_333 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st418_fsm_334;
else
ap_NS_fsm <= ap_ST_st417_fsm_333;
end if;
when ap_ST_st418_fsm_334 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st419_fsm_335;
else
ap_NS_fsm <= ap_ST_st418_fsm_334;
end if;
when ap_ST_st419_fsm_335 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st420_fsm_336;
else
ap_NS_fsm <= ap_ST_st419_fsm_335;
end if;
when ap_ST_st420_fsm_336 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st421_fsm_337;
else
ap_NS_fsm <= ap_ST_st420_fsm_336;
end if;
when ap_ST_st421_fsm_337 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st422_fsm_338;
else
ap_NS_fsm <= ap_ST_st421_fsm_337;
end if;
when ap_ST_st422_fsm_338 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st423_fsm_339;
else
ap_NS_fsm <= ap_ST_st422_fsm_338;
end if;
when ap_ST_st423_fsm_339 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st424_fsm_340;
else
ap_NS_fsm <= ap_ST_st423_fsm_339;
end if;
when ap_ST_st424_fsm_340 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st425_fsm_341;
else
ap_NS_fsm <= ap_ST_st424_fsm_340;
end if;
when ap_ST_st425_fsm_341 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st426_fsm_342;
else
ap_NS_fsm <= ap_ST_st425_fsm_341;
end if;
when ap_ST_st426_fsm_342 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st427_fsm_343;
else
ap_NS_fsm <= ap_ST_st426_fsm_342;
end if;
when ap_ST_st427_fsm_343 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st428_fsm_344;
else
ap_NS_fsm <= ap_ST_st427_fsm_343;
end if;
when ap_ST_st428_fsm_344 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st429_fsm_345;
else
ap_NS_fsm <= ap_ST_st428_fsm_344;
end if;
when ap_ST_st429_fsm_345 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st430_fsm_346;
else
ap_NS_fsm <= ap_ST_st429_fsm_345;
end if;
when ap_ST_st430_fsm_346 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st431_fsm_347;
else
ap_NS_fsm <= ap_ST_st430_fsm_346;
end if;
when ap_ST_st431_fsm_347 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st432_fsm_348;
else
ap_NS_fsm <= ap_ST_st431_fsm_347;
end if;
when ap_ST_st432_fsm_348 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st433_fsm_349;
else
ap_NS_fsm <= ap_ST_st432_fsm_348;
end if;
when ap_ST_st433_fsm_349 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st434_fsm_350;
else
ap_NS_fsm <= ap_ST_st433_fsm_349;
end if;
when ap_ST_st434_fsm_350 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st435_fsm_351;
else
ap_NS_fsm <= ap_ST_st434_fsm_350;
end if;
when ap_ST_st435_fsm_351 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st436_fsm_352;
else
ap_NS_fsm <= ap_ST_st435_fsm_351;
end if;
when ap_ST_st436_fsm_352 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st437_fsm_353;
else
ap_NS_fsm <= ap_ST_st436_fsm_352;
end if;
when ap_ST_st437_fsm_353 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st438_fsm_354;
else
ap_NS_fsm <= ap_ST_st437_fsm_353;
end if;
when ap_ST_st438_fsm_354 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st439_fsm_355;
else
ap_NS_fsm <= ap_ST_st438_fsm_354;
end if;
when ap_ST_st439_fsm_355 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st440_fsm_356;
else
ap_NS_fsm <= ap_ST_st439_fsm_355;
end if;
when ap_ST_st440_fsm_356 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st441_fsm_357;
else
ap_NS_fsm <= ap_ST_st440_fsm_356;
end if;
when ap_ST_st441_fsm_357 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st442_fsm_358;
else
ap_NS_fsm <= ap_ST_st441_fsm_357;
end if;
when ap_ST_st442_fsm_358 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st443_fsm_359;
else
ap_NS_fsm <= ap_ST_st442_fsm_358;
end if;
when ap_ST_st443_fsm_359 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st444_fsm_360;
else
ap_NS_fsm <= ap_ST_st443_fsm_359;
end if;
when ap_ST_st444_fsm_360 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st445_fsm_361;
else
ap_NS_fsm <= ap_ST_st444_fsm_360;
end if;
when ap_ST_st445_fsm_361 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st445_fsm_361;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1004 assign process. --
ap_sig_bdd_1004_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1004 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_1013 assign process. --
ap_sig_bdd_1013_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1013 <= (ap_const_lv1_1 = ap_CS_fsm(94 downto 94));
end process;
-- ap_sig_bdd_1022 assign process. --
ap_sig_bdd_1022_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1022 <= (ap_const_lv1_1 = ap_CS_fsm(109 downto 109));
end process;
-- ap_sig_bdd_1031 assign process. --
ap_sig_bdd_1031_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1031 <= (ap_const_lv1_1 = ap_CS_fsm(124 downto 124));
end process;
-- ap_sig_bdd_1040 assign process. --
ap_sig_bdd_1040_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1040 <= (ap_const_lv1_1 = ap_CS_fsm(139 downto 139));
end process;
-- ap_sig_bdd_1049 assign process. --
ap_sig_bdd_1049_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1049 <= (ap_const_lv1_1 = ap_CS_fsm(154 downto 154));
end process;
-- ap_sig_bdd_1058 assign process. --
ap_sig_bdd_1058_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1058 <= (ap_const_lv1_1 = ap_CS_fsm(169 downto 169));
end process;
-- ap_sig_bdd_1067 assign process. --
ap_sig_bdd_1067_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1067 <= (ap_const_lv1_1 = ap_CS_fsm(184 downto 184));
end process;
-- ap_sig_bdd_1076 assign process. --
ap_sig_bdd_1076_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1076 <= (ap_const_lv1_1 = ap_CS_fsm(199 downto 199));
end process;
-- ap_sig_bdd_1085 assign process. --
ap_sig_bdd_1085_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1085 <= (ap_const_lv1_1 = ap_CS_fsm(214 downto 214));
end process;
-- ap_sig_bdd_1094 assign process. --
ap_sig_bdd_1094_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1094 <= (ap_const_lv1_1 = ap_CS_fsm(229 downto 229));
end process;
-- ap_sig_bdd_1103 assign process. --
ap_sig_bdd_1103_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1103 <= (ap_const_lv1_1 = ap_CS_fsm(244 downto 244));
end process;
-- ap_sig_bdd_1112 assign process. --
ap_sig_bdd_1112_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1112 <= (ap_const_lv1_1 = ap_CS_fsm(259 downto 259));
end process;
-- ap_sig_bdd_1121 assign process. --
ap_sig_bdd_1121_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1121 <= (ap_const_lv1_1 = ap_CS_fsm(274 downto 274));
end process;
-- ap_sig_bdd_1130 assign process. --
ap_sig_bdd_1130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1130 <= (ap_const_lv1_1 = ap_CS_fsm(289 downto 289));
end process;
-- ap_sig_bdd_1140 assign process. --
ap_sig_bdd_1140_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1140 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_1148 assign process. --
ap_sig_bdd_1148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1148 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_1157 assign process. --
ap_sig_bdd_1157_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1157 <= (ap_const_lv1_1 = ap_CS_fsm(95 downto 95));
end process;
-- ap_sig_bdd_1166 assign process. --
ap_sig_bdd_1166_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1166 <= (ap_const_lv1_1 = ap_CS_fsm(110 downto 110));
end process;
-- ap_sig_bdd_1175 assign process. --
ap_sig_bdd_1175_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1175 <= (ap_const_lv1_1 = ap_CS_fsm(125 downto 125));
end process;
-- ap_sig_bdd_1184 assign process. --
ap_sig_bdd_1184_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1184 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_1193 assign process. --
ap_sig_bdd_1193_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1193 <= (ap_const_lv1_1 = ap_CS_fsm(155 downto 155));
end process;
-- ap_sig_bdd_1202 assign process. --
ap_sig_bdd_1202_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1202 <= (ap_const_lv1_1 = ap_CS_fsm(170 downto 170));
end process;
-- ap_sig_bdd_1211 assign process. --
ap_sig_bdd_1211_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1211 <= (ap_const_lv1_1 = ap_CS_fsm(185 downto 185));
end process;
-- ap_sig_bdd_1220 assign process. --
ap_sig_bdd_1220_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1220 <= (ap_const_lv1_1 = ap_CS_fsm(200 downto 200));
end process;
-- ap_sig_bdd_1229 assign process. --
ap_sig_bdd_1229_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1229 <= (ap_const_lv1_1 = ap_CS_fsm(215 downto 215));
end process;
-- ap_sig_bdd_1238 assign process. --
ap_sig_bdd_1238_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1238 <= (ap_const_lv1_1 = ap_CS_fsm(230 downto 230));
end process;
-- ap_sig_bdd_1247 assign process. --
ap_sig_bdd_1247_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1247 <= (ap_const_lv1_1 = ap_CS_fsm(245 downto 245));
end process;
-- ap_sig_bdd_1256 assign process. --
ap_sig_bdd_1256_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1256 <= (ap_const_lv1_1 = ap_CS_fsm(260 downto 260));
end process;
-- ap_sig_bdd_1265 assign process. --
ap_sig_bdd_1265_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1265 <= (ap_const_lv1_1 = ap_CS_fsm(275 downto 275));
end process;
-- ap_sig_bdd_1274 assign process. --
ap_sig_bdd_1274_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1274 <= (ap_const_lv1_1 = ap_CS_fsm(290 downto 290));
end process;
-- ap_sig_bdd_1284 assign process. --
ap_sig_bdd_1284_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1284 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_1292 assign process. --
ap_sig_bdd_1292_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1292 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_1301 assign process. --
ap_sig_bdd_1301_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1301 <= (ap_const_lv1_1 = ap_CS_fsm(96 downto 96));
end process;
-- ap_sig_bdd_1310 assign process. --
ap_sig_bdd_1310_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1310 <= (ap_const_lv1_1 = ap_CS_fsm(111 downto 111));
end process;
-- ap_sig_bdd_1319 assign process. --
ap_sig_bdd_1319_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1319 <= (ap_const_lv1_1 = ap_CS_fsm(126 downto 126));
end process;
-- ap_sig_bdd_1328 assign process. --
ap_sig_bdd_1328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1328 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_1337 assign process. --
ap_sig_bdd_1337_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1337 <= (ap_const_lv1_1 = ap_CS_fsm(156 downto 156));
end process;
-- ap_sig_bdd_1346 assign process. --
ap_sig_bdd_1346_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1346 <= (ap_const_lv1_1 = ap_CS_fsm(171 downto 171));
end process;
-- ap_sig_bdd_1355 assign process. --
ap_sig_bdd_1355_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1355 <= (ap_const_lv1_1 = ap_CS_fsm(186 downto 186));
end process;
-- ap_sig_bdd_1364 assign process. --
ap_sig_bdd_1364_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1364 <= (ap_const_lv1_1 = ap_CS_fsm(201 downto 201));
end process;
-- ap_sig_bdd_1373 assign process. --
ap_sig_bdd_1373_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1373 <= (ap_const_lv1_1 = ap_CS_fsm(216 downto 216));
end process;
-- ap_sig_bdd_1382 assign process. --
ap_sig_bdd_1382_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1382 <= (ap_const_lv1_1 = ap_CS_fsm(231 downto 231));
end process;
-- ap_sig_bdd_1391 assign process. --
ap_sig_bdd_1391_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1391 <= (ap_const_lv1_1 = ap_CS_fsm(246 downto 246));
end process;
-- ap_sig_bdd_1400 assign process. --
ap_sig_bdd_1400_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1400 <= (ap_const_lv1_1 = ap_CS_fsm(261 downto 261));
end process;
-- ap_sig_bdd_1409 assign process. --
ap_sig_bdd_1409_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1409 <= (ap_const_lv1_1 = ap_CS_fsm(276 downto 276));
end process;
-- ap_sig_bdd_1418 assign process. --
ap_sig_bdd_1418_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1418 <= (ap_const_lv1_1 = ap_CS_fsm(291 downto 291));
end process;
-- ap_sig_bdd_1428 assign process. --
ap_sig_bdd_1428_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1428 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_1436 assign process. --
ap_sig_bdd_1436_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1436 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_1445 assign process. --
ap_sig_bdd_1445_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1445 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_1454 assign process. --
ap_sig_bdd_1454_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1454 <= (ap_const_lv1_1 = ap_CS_fsm(112 downto 112));
end process;
-- ap_sig_bdd_1463 assign process. --
ap_sig_bdd_1463_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1463 <= (ap_const_lv1_1 = ap_CS_fsm(127 downto 127));
end process;
-- ap_sig_bdd_1472 assign process. --
ap_sig_bdd_1472_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1472 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_1481 assign process. --
ap_sig_bdd_1481_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1481 <= (ap_const_lv1_1 = ap_CS_fsm(157 downto 157));
end process;
-- ap_sig_bdd_1490 assign process. --
ap_sig_bdd_1490_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1490 <= (ap_const_lv1_1 = ap_CS_fsm(172 downto 172));
end process;
-- ap_sig_bdd_1499 assign process. --
ap_sig_bdd_1499_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1499 <= (ap_const_lv1_1 = ap_CS_fsm(187 downto 187));
end process;
-- ap_sig_bdd_1508 assign process. --
ap_sig_bdd_1508_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1508 <= (ap_const_lv1_1 = ap_CS_fsm(202 downto 202));
end process;
-- ap_sig_bdd_1517 assign process. --
ap_sig_bdd_1517_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1517 <= (ap_const_lv1_1 = ap_CS_fsm(217 downto 217));
end process;
-- ap_sig_bdd_1526 assign process. --
ap_sig_bdd_1526_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1526 <= (ap_const_lv1_1 = ap_CS_fsm(232 downto 232));
end process;
-- ap_sig_bdd_1535 assign process. --
ap_sig_bdd_1535_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1535 <= (ap_const_lv1_1 = ap_CS_fsm(247 downto 247));
end process;
-- ap_sig_bdd_1544 assign process. --
ap_sig_bdd_1544_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1544 <= (ap_const_lv1_1 = ap_CS_fsm(262 downto 262));
end process;
-- ap_sig_bdd_1553 assign process. --
ap_sig_bdd_1553_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1553 <= (ap_const_lv1_1 = ap_CS_fsm(277 downto 277));
end process;
-- ap_sig_bdd_1562 assign process. --
ap_sig_bdd_1562_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1562 <= (ap_const_lv1_1 = ap_CS_fsm(292 downto 292));
end process;
-- ap_sig_bdd_1572 assign process. --
ap_sig_bdd_1572_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1572 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_1580 assign process. --
ap_sig_bdd_1580_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1580 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_1589 assign process. --
ap_sig_bdd_1589_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1589 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_1598 assign process. --
ap_sig_bdd_1598_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1598 <= (ap_const_lv1_1 = ap_CS_fsm(113 downto 113));
end process;
-- ap_sig_bdd_1607 assign process. --
ap_sig_bdd_1607_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1607 <= (ap_const_lv1_1 = ap_CS_fsm(128 downto 128));
end process;
-- ap_sig_bdd_1616 assign process. --
ap_sig_bdd_1616_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1616 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_1625 assign process. --
ap_sig_bdd_1625_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1625 <= (ap_const_lv1_1 = ap_CS_fsm(158 downto 158));
end process;
-- ap_sig_bdd_1634 assign process. --
ap_sig_bdd_1634_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1634 <= (ap_const_lv1_1 = ap_CS_fsm(173 downto 173));
end process;
-- ap_sig_bdd_1643 assign process. --
ap_sig_bdd_1643_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1643 <= (ap_const_lv1_1 = ap_CS_fsm(188 downto 188));
end process;
-- ap_sig_bdd_1652 assign process. --
ap_sig_bdd_1652_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1652 <= (ap_const_lv1_1 = ap_CS_fsm(203 downto 203));
end process;
-- ap_sig_bdd_1661 assign process. --
ap_sig_bdd_1661_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1661 <= (ap_const_lv1_1 = ap_CS_fsm(218 downto 218));
end process;
-- ap_sig_bdd_1670 assign process. --
ap_sig_bdd_1670_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1670 <= (ap_const_lv1_1 = ap_CS_fsm(233 downto 233));
end process;
-- ap_sig_bdd_1679 assign process. --
ap_sig_bdd_1679_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1679 <= (ap_const_lv1_1 = ap_CS_fsm(248 downto 248));
end process;
-- ap_sig_bdd_1688 assign process. --
ap_sig_bdd_1688_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1688 <= (ap_const_lv1_1 = ap_CS_fsm(263 downto 263));
end process;
-- ap_sig_bdd_1697 assign process. --
ap_sig_bdd_1697_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1697 <= (ap_const_lv1_1 = ap_CS_fsm(278 downto 278));
end process;
-- ap_sig_bdd_1706 assign process. --
ap_sig_bdd_1706_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1706 <= (ap_const_lv1_1 = ap_CS_fsm(293 downto 293));
end process;
-- ap_sig_bdd_1716 assign process. --
ap_sig_bdd_1716_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1716 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_1724 assign process. --
ap_sig_bdd_1724_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1724 <= (ap_const_lv1_1 = ap_CS_fsm(84 downto 84));
end process;
-- ap_sig_bdd_1733 assign process. --
ap_sig_bdd_1733_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1733 <= (ap_const_lv1_1 = ap_CS_fsm(99 downto 99));
end process;
-- ap_sig_bdd_1742 assign process. --
ap_sig_bdd_1742_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1742 <= (ap_const_lv1_1 = ap_CS_fsm(114 downto 114));
end process;
-- ap_sig_bdd_1751 assign process. --
ap_sig_bdd_1751_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1751 <= (ap_const_lv1_1 = ap_CS_fsm(129 downto 129));
end process;
-- ap_sig_bdd_1760 assign process. --
ap_sig_bdd_1760_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1760 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_1769 assign process. --
ap_sig_bdd_1769_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1769 <= (ap_const_lv1_1 = ap_CS_fsm(159 downto 159));
end process;
-- ap_sig_bdd_1778 assign process. --
ap_sig_bdd_1778_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1778 <= (ap_const_lv1_1 = ap_CS_fsm(174 downto 174));
end process;
-- ap_sig_bdd_1787 assign process. --
ap_sig_bdd_1787_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1787 <= (ap_const_lv1_1 = ap_CS_fsm(189 downto 189));
end process;
-- ap_sig_bdd_1796 assign process. --
ap_sig_bdd_1796_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1796 <= (ap_const_lv1_1 = ap_CS_fsm(204 downto 204));
end process;
-- ap_sig_bdd_1805 assign process. --
ap_sig_bdd_1805_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1805 <= (ap_const_lv1_1 = ap_CS_fsm(219 downto 219));
end process;
-- ap_sig_bdd_1814 assign process. --
ap_sig_bdd_1814_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1814 <= (ap_const_lv1_1 = ap_CS_fsm(234 downto 234));
end process;
-- ap_sig_bdd_1823 assign process. --
ap_sig_bdd_1823_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1823 <= (ap_const_lv1_1 = ap_CS_fsm(249 downto 249));
end process;
-- ap_sig_bdd_1832 assign process. --
ap_sig_bdd_1832_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1832 <= (ap_const_lv1_1 = ap_CS_fsm(264 downto 264));
end process;
-- ap_sig_bdd_1841 assign process. --
ap_sig_bdd_1841_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1841 <= (ap_const_lv1_1 = ap_CS_fsm(279 downto 279));
end process;
-- ap_sig_bdd_1850 assign process. --
ap_sig_bdd_1850_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1850 <= (ap_const_lv1_1 = ap_CS_fsm(294 downto 294));
end process;
-- ap_sig_bdd_1860 assign process. --
ap_sig_bdd_1860_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1860 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_1868 assign process. --
ap_sig_bdd_1868_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1868 <= (ap_const_lv1_1 = ap_CS_fsm(85 downto 85));
end process;
-- ap_sig_bdd_1877 assign process. --
ap_sig_bdd_1877_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1877 <= (ap_const_lv1_1 = ap_CS_fsm(100 downto 100));
end process;
-- ap_sig_bdd_1886 assign process. --
ap_sig_bdd_1886_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1886 <= (ap_const_lv1_1 = ap_CS_fsm(115 downto 115));
end process;
-- ap_sig_bdd_1895 assign process. --
ap_sig_bdd_1895_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1895 <= (ap_const_lv1_1 = ap_CS_fsm(130 downto 130));
end process;
-- ap_sig_bdd_1904 assign process. --
ap_sig_bdd_1904_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1904 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_1913 assign process. --
ap_sig_bdd_1913_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1913 <= (ap_const_lv1_1 = ap_CS_fsm(160 downto 160));
end process;
-- ap_sig_bdd_1922 assign process. --
ap_sig_bdd_1922_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1922 <= (ap_const_lv1_1 = ap_CS_fsm(175 downto 175));
end process;
-- ap_sig_bdd_1931 assign process. --
ap_sig_bdd_1931_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1931 <= (ap_const_lv1_1 = ap_CS_fsm(190 downto 190));
end process;
-- ap_sig_bdd_1940 assign process. --
ap_sig_bdd_1940_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1940 <= (ap_const_lv1_1 = ap_CS_fsm(205 downto 205));
end process;
-- ap_sig_bdd_1949 assign process. --
ap_sig_bdd_1949_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1949 <= (ap_const_lv1_1 = ap_CS_fsm(220 downto 220));
end process;
-- ap_sig_bdd_1958 assign process. --
ap_sig_bdd_1958_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1958 <= (ap_const_lv1_1 = ap_CS_fsm(235 downto 235));
end process;
-- ap_sig_bdd_1967 assign process. --
ap_sig_bdd_1967_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1967 <= (ap_const_lv1_1 = ap_CS_fsm(250 downto 250));
end process;
-- ap_sig_bdd_1976 assign process. --
ap_sig_bdd_1976_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1976 <= (ap_const_lv1_1 = ap_CS_fsm(265 downto 265));
end process;
-- ap_sig_bdd_1985 assign process. --
ap_sig_bdd_1985_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1985 <= (ap_const_lv1_1 = ap_CS_fsm(280 downto 280));
end process;
-- ap_sig_bdd_1994 assign process. --
ap_sig_bdd_1994_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1994 <= (ap_const_lv1_1 = ap_CS_fsm(295 downto 295));
end process;
-- ap_sig_bdd_2004 assign process. --
ap_sig_bdd_2004_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2004 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_2012 assign process. --
ap_sig_bdd_2012_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2012 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_2021 assign process. --
ap_sig_bdd_2021_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2021 <= (ap_const_lv1_1 = ap_CS_fsm(101 downto 101));
end process;
-- ap_sig_bdd_2030 assign process. --
ap_sig_bdd_2030_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2030 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_2039 assign process. --
ap_sig_bdd_2039_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2039 <= (ap_const_lv1_1 = ap_CS_fsm(131 downto 131));
end process;
-- ap_sig_bdd_2048 assign process. --
ap_sig_bdd_2048_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2048 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_2057 assign process. --
ap_sig_bdd_2057_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2057 <= (ap_const_lv1_1 = ap_CS_fsm(161 downto 161));
end process;
-- ap_sig_bdd_2066 assign process. --
ap_sig_bdd_2066_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2066 <= (ap_const_lv1_1 = ap_CS_fsm(176 downto 176));
end process;
-- ap_sig_bdd_2075 assign process. --
ap_sig_bdd_2075_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2075 <= (ap_const_lv1_1 = ap_CS_fsm(191 downto 191));
end process;
-- ap_sig_bdd_2084 assign process. --
ap_sig_bdd_2084_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2084 <= (ap_const_lv1_1 = ap_CS_fsm(206 downto 206));
end process;
-- ap_sig_bdd_2093 assign process. --
ap_sig_bdd_2093_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2093 <= (ap_const_lv1_1 = ap_CS_fsm(221 downto 221));
end process;
-- ap_sig_bdd_2102 assign process. --
ap_sig_bdd_2102_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2102 <= (ap_const_lv1_1 = ap_CS_fsm(236 downto 236));
end process;
-- ap_sig_bdd_2111 assign process. --
ap_sig_bdd_2111_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2111 <= (ap_const_lv1_1 = ap_CS_fsm(251 downto 251));
end process;
-- ap_sig_bdd_2120 assign process. --
ap_sig_bdd_2120_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2120 <= (ap_const_lv1_1 = ap_CS_fsm(266 downto 266));
end process;
-- ap_sig_bdd_2129 assign process. --
ap_sig_bdd_2129_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2129 <= (ap_const_lv1_1 = ap_CS_fsm(281 downto 281));
end process;
-- ap_sig_bdd_2138 assign process. --
ap_sig_bdd_2138_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2138 <= (ap_const_lv1_1 = ap_CS_fsm(296 downto 296));
end process;
-- ap_sig_bdd_2148 assign process. --
ap_sig_bdd_2148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2148 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_2156 assign process. --
ap_sig_bdd_2156_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2156 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_2165 assign process. --
ap_sig_bdd_2165_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2165 <= (ap_const_lv1_1 = ap_CS_fsm(102 downto 102));
end process;
-- ap_sig_bdd_2174 assign process. --
ap_sig_bdd_2174_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2174 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_2183 assign process. --
ap_sig_bdd_2183_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2183 <= (ap_const_lv1_1 = ap_CS_fsm(132 downto 132));
end process;
-- ap_sig_bdd_2192 assign process. --
ap_sig_bdd_2192_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2192 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_2201 assign process. --
ap_sig_bdd_2201_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2201 <= (ap_const_lv1_1 = ap_CS_fsm(162 downto 162));
end process;
-- ap_sig_bdd_2210 assign process. --
ap_sig_bdd_2210_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2210 <= (ap_const_lv1_1 = ap_CS_fsm(177 downto 177));
end process;
-- ap_sig_bdd_2219 assign process. --
ap_sig_bdd_2219_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2219 <= (ap_const_lv1_1 = ap_CS_fsm(192 downto 192));
end process;
-- ap_sig_bdd_2228 assign process. --
ap_sig_bdd_2228_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2228 <= (ap_const_lv1_1 = ap_CS_fsm(207 downto 207));
end process;
-- ap_sig_bdd_2237 assign process. --
ap_sig_bdd_2237_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2237 <= (ap_const_lv1_1 = ap_CS_fsm(222 downto 222));
end process;
-- ap_sig_bdd_2246 assign process. --
ap_sig_bdd_2246_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2246 <= (ap_const_lv1_1 = ap_CS_fsm(237 downto 237));
end process;
-- ap_sig_bdd_2255 assign process. --
ap_sig_bdd_2255_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2255 <= (ap_const_lv1_1 = ap_CS_fsm(252 downto 252));
end process;
-- ap_sig_bdd_2264 assign process. --
ap_sig_bdd_2264_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2264 <= (ap_const_lv1_1 = ap_CS_fsm(267 downto 267));
end process;
-- ap_sig_bdd_2273 assign process. --
ap_sig_bdd_2273_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2273 <= (ap_const_lv1_1 = ap_CS_fsm(282 downto 282));
end process;
-- ap_sig_bdd_2282 assign process. --
ap_sig_bdd_2282_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2282 <= (ap_const_lv1_1 = ap_CS_fsm(297 downto 297));
end process;
-- ap_sig_bdd_2292 assign process. --
ap_sig_bdd_2292_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2292 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_2300 assign process. --
ap_sig_bdd_2300_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2300 <= (ap_const_lv1_1 = ap_CS_fsm(88 downto 88));
end process;
-- ap_sig_bdd_2309 assign process. --
ap_sig_bdd_2309_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2309 <= (ap_const_lv1_1 = ap_CS_fsm(103 downto 103));
end process;
-- ap_sig_bdd_2318 assign process. --
ap_sig_bdd_2318_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2318 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_bdd_2327 assign process. --
ap_sig_bdd_2327_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2327 <= (ap_const_lv1_1 = ap_CS_fsm(133 downto 133));
end process;
-- ap_sig_bdd_2336 assign process. --
ap_sig_bdd_2336_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2336 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_2345 assign process. --
ap_sig_bdd_2345_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2345 <= (ap_const_lv1_1 = ap_CS_fsm(163 downto 163));
end process;
-- ap_sig_bdd_2354 assign process. --
ap_sig_bdd_2354_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2354 <= (ap_const_lv1_1 = ap_CS_fsm(178 downto 178));
end process;
-- ap_sig_bdd_2363 assign process. --
ap_sig_bdd_2363_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2363 <= (ap_const_lv1_1 = ap_CS_fsm(193 downto 193));
end process;
-- ap_sig_bdd_2372 assign process. --
ap_sig_bdd_2372_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2372 <= (ap_const_lv1_1 = ap_CS_fsm(208 downto 208));
end process;
-- ap_sig_bdd_2381 assign process. --
ap_sig_bdd_2381_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2381 <= (ap_const_lv1_1 = ap_CS_fsm(223 downto 223));
end process;
-- ap_sig_bdd_2390 assign process. --
ap_sig_bdd_2390_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2390 <= (ap_const_lv1_1 = ap_CS_fsm(238 downto 238));
end process;
-- ap_sig_bdd_2399 assign process. --
ap_sig_bdd_2399_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2399 <= (ap_const_lv1_1 = ap_CS_fsm(253 downto 253));
end process;
-- ap_sig_bdd_2408 assign process. --
ap_sig_bdd_2408_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2408 <= (ap_const_lv1_1 = ap_CS_fsm(268 downto 268));
end process;
-- ap_sig_bdd_2417 assign process. --
ap_sig_bdd_2417_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2417 <= (ap_const_lv1_1 = ap_CS_fsm(283 downto 283));
end process;
-- ap_sig_bdd_2426 assign process. --
ap_sig_bdd_2426_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2426 <= (ap_const_lv1_1 = ap_CS_fsm(298 downto 298));
end process;
-- ap_sig_bdd_2437 assign process. --
ap_sig_bdd_2437_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2437 <= (ap_const_lv1_1 = ap_CS_fsm(71 downto 71));
end process;
-- ap_sig_bdd_2694 assign process. --
ap_sig_bdd_2694_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2694 <= (ap_const_lv1_1 = ap_CS_fsm(300 downto 300));
end process;
-- ap_sig_bdd_2708 assign process. --
ap_sig_bdd_2708_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2708 <= (ap_const_lv1_1 = ap_CS_fsm(302 downto 302));
end process;
-- ap_sig_bdd_2719 assign process. --
ap_sig_bdd_2719_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2719 <= (ap_const_lv1_1 = ap_CS_fsm(305 downto 305));
end process;
-- ap_sig_bdd_2728 assign process. --
ap_sig_bdd_2728_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2728 <= (ap_const_lv1_1 = ap_CS_fsm(308 downto 308));
end process;
-- ap_sig_bdd_2737 assign process. --
ap_sig_bdd_2737_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2737 <= (ap_const_lv1_1 = ap_CS_fsm(311 downto 311));
end process;
-- ap_sig_bdd_2746 assign process. --
ap_sig_bdd_2746_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2746 <= (ap_const_lv1_1 = ap_CS_fsm(314 downto 314));
end process;
-- ap_sig_bdd_2755 assign process. --
ap_sig_bdd_2755_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2755 <= (ap_const_lv1_1 = ap_CS_fsm(317 downto 317));
end process;
-- ap_sig_bdd_2764 assign process. --
ap_sig_bdd_2764_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2764 <= (ap_const_lv1_1 = ap_CS_fsm(320 downto 320));
end process;
-- ap_sig_bdd_2773 assign process. --
ap_sig_bdd_2773_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2773 <= (ap_const_lv1_1 = ap_CS_fsm(323 downto 323));
end process;
-- ap_sig_bdd_2782 assign process. --
ap_sig_bdd_2782_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2782 <= (ap_const_lv1_1 = ap_CS_fsm(326 downto 326));
end process;
-- ap_sig_bdd_2791 assign process. --
ap_sig_bdd_2791_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2791 <= (ap_const_lv1_1 = ap_CS_fsm(329 downto 329));
end process;
-- ap_sig_bdd_2800 assign process. --
ap_sig_bdd_2800_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2800 <= (ap_const_lv1_1 = ap_CS_fsm(332 downto 332));
end process;
-- ap_sig_bdd_2809 assign process. --
ap_sig_bdd_2809_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2809 <= (ap_const_lv1_1 = ap_CS_fsm(335 downto 335));
end process;
-- ap_sig_bdd_2818 assign process. --
ap_sig_bdd_2818_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2818 <= (ap_const_lv1_1 = ap_CS_fsm(338 downto 338));
end process;
-- ap_sig_bdd_2827 assign process. --
ap_sig_bdd_2827_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2827 <= (ap_const_lv1_1 = ap_CS_fsm(341 downto 341));
end process;
-- ap_sig_bdd_2836 assign process. --
ap_sig_bdd_2836_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2836 <= (ap_const_lv1_1 = ap_CS_fsm(344 downto 344));
end process;
-- ap_sig_bdd_2845 assign process. --
ap_sig_bdd_2845_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2845 <= (ap_const_lv1_1 = ap_CS_fsm(347 downto 347));
end process;
-- ap_sig_bdd_2854 assign process. --
ap_sig_bdd_2854_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2854 <= (ap_const_lv1_1 = ap_CS_fsm(350 downto 350));
end process;
-- ap_sig_bdd_2863 assign process. --
ap_sig_bdd_2863_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2863 <= (ap_const_lv1_1 = ap_CS_fsm(353 downto 353));
end process;
-- ap_sig_bdd_2872 assign process. --
ap_sig_bdd_2872_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2872 <= (ap_const_lv1_1 = ap_CS_fsm(356 downto 356));
end process;
-- ap_sig_bdd_2881 assign process. --
ap_sig_bdd_2881_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2881 <= (ap_const_lv1_1 = ap_CS_fsm(359 downto 359));
end process;
-- ap_sig_bdd_2893 assign process. --
ap_sig_bdd_2893_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2893 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_2902 assign process. --
ap_sig_bdd_2902_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2902 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_2911 assign process. --
ap_sig_bdd_2911_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2911 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_2920 assign process. --
ap_sig_bdd_2920_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2920 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_2929 assign process. --
ap_sig_bdd_2929_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2929 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_2938 assign process. --
ap_sig_bdd_2938_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2938 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_2947 assign process. --
ap_sig_bdd_2947_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2947 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_2956 assign process. --
ap_sig_bdd_2956_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2956 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_2965 assign process. --
ap_sig_bdd_2965_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2965 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_2974 assign process. --
ap_sig_bdd_2974_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2974 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_2983 assign process. --
ap_sig_bdd_2983_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2983 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_2992 assign process. --
ap_sig_bdd_2992_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2992 <= (ap_const_lv1_1 = ap_CS_fsm(25 downto 25));
end process;
-- ap_sig_bdd_3001 assign process. --
ap_sig_bdd_3001_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3001 <= (ap_const_lv1_1 = ap_CS_fsm(26 downto 26));
end process;
-- ap_sig_bdd_3010 assign process. --
ap_sig_bdd_3010_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3010 <= (ap_const_lv1_1 = ap_CS_fsm(27 downto 27));
end process;
-- ap_sig_bdd_3019 assign process. --
ap_sig_bdd_3019_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3019 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_3028 assign process. --
ap_sig_bdd_3028_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3028 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_3037 assign process. --
ap_sig_bdd_3037_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3037 <= (ap_const_lv1_1 = ap_CS_fsm(30 downto 30));
end process;
-- ap_sig_bdd_3046 assign process. --
ap_sig_bdd_3046_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3046 <= (ap_const_lv1_1 = ap_CS_fsm(31 downto 31));
end process;
-- ap_sig_bdd_3055 assign process. --
ap_sig_bdd_3055_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3055 <= (ap_const_lv1_1 = ap_CS_fsm(32 downto 32));
end process;
-- ap_sig_bdd_3064 assign process. --
ap_sig_bdd_3064_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3064 <= (ap_const_lv1_1 = ap_CS_fsm(33 downto 33));
end process;
-- ap_sig_bdd_3073 assign process. --
ap_sig_bdd_3073_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3073 <= (ap_const_lv1_1 = ap_CS_fsm(34 downto 34));
end process;
-- ap_sig_bdd_3082 assign process. --
ap_sig_bdd_3082_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3082 <= (ap_const_lv1_1 = ap_CS_fsm(35 downto 35));
end process;
-- ap_sig_bdd_3091 assign process. --
ap_sig_bdd_3091_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3091 <= (ap_const_lv1_1 = ap_CS_fsm(36 downto 36));
end process;
-- ap_sig_bdd_3100 assign process. --
ap_sig_bdd_3100_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3100 <= (ap_const_lv1_1 = ap_CS_fsm(37 downto 37));
end process;
-- ap_sig_bdd_3109 assign process. --
ap_sig_bdd_3109_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3109 <= (ap_const_lv1_1 = ap_CS_fsm(38 downto 38));
end process;
-- ap_sig_bdd_3118 assign process. --
ap_sig_bdd_3118_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3118 <= (ap_const_lv1_1 = ap_CS_fsm(39 downto 39));
end process;
-- ap_sig_bdd_3127 assign process. --
ap_sig_bdd_3127_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3127 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_3136 assign process. --
ap_sig_bdd_3136_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3136 <= (ap_const_lv1_1 = ap_CS_fsm(41 downto 41));
end process;
-- ap_sig_bdd_3145 assign process. --
ap_sig_bdd_3145_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3145 <= (ap_const_lv1_1 = ap_CS_fsm(42 downto 42));
end process;
-- ap_sig_bdd_3154 assign process. --
ap_sig_bdd_3154_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3154 <= (ap_const_lv1_1 = ap_CS_fsm(43 downto 43));
end process;
-- ap_sig_bdd_3163 assign process. --
ap_sig_bdd_3163_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3163 <= (ap_const_lv1_1 = ap_CS_fsm(44 downto 44));
end process;
-- ap_sig_bdd_3172 assign process. --
ap_sig_bdd_3172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3172 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_3181 assign process. --
ap_sig_bdd_3181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3181 <= (ap_const_lv1_1 = ap_CS_fsm(46 downto 46));
end process;
-- ap_sig_bdd_3190 assign process. --
ap_sig_bdd_3190_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3190 <= (ap_const_lv1_1 = ap_CS_fsm(47 downto 47));
end process;
-- ap_sig_bdd_3199 assign process. --
ap_sig_bdd_3199_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3199 <= (ap_const_lv1_1 = ap_CS_fsm(48 downto 48));
end process;
-- ap_sig_bdd_3208 assign process. --
ap_sig_bdd_3208_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3208 <= (ap_const_lv1_1 = ap_CS_fsm(49 downto 49));
end process;
-- ap_sig_bdd_3217 assign process. --
ap_sig_bdd_3217_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3217 <= (ap_const_lv1_1 = ap_CS_fsm(50 downto 50));
end process;
-- ap_sig_bdd_3226 assign process. --
ap_sig_bdd_3226_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3226 <= (ap_const_lv1_1 = ap_CS_fsm(51 downto 51));
end process;
-- ap_sig_bdd_3235 assign process. --
ap_sig_bdd_3235_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3235 <= (ap_const_lv1_1 = ap_CS_fsm(52 downto 52));
end process;
-- ap_sig_bdd_3244 assign process. --
ap_sig_bdd_3244_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3244 <= (ap_const_lv1_1 = ap_CS_fsm(53 downto 53));
end process;
-- ap_sig_bdd_3253 assign process. --
ap_sig_bdd_3253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3253 <= (ap_const_lv1_1 = ap_CS_fsm(54 downto 54));
end process;
-- ap_sig_bdd_3262 assign process. --
ap_sig_bdd_3262_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3262 <= (ap_const_lv1_1 = ap_CS_fsm(55 downto 55));
end process;
-- ap_sig_bdd_3271 assign process. --
ap_sig_bdd_3271_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3271 <= (ap_const_lv1_1 = ap_CS_fsm(56 downto 56));
end process;
-- ap_sig_bdd_3280 assign process. --
ap_sig_bdd_3280_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3280 <= (ap_const_lv1_1 = ap_CS_fsm(57 downto 57));
end process;
-- ap_sig_bdd_3289 assign process. --
ap_sig_bdd_3289_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3289 <= (ap_const_lv1_1 = ap_CS_fsm(58 downto 58));
end process;
-- ap_sig_bdd_3298 assign process. --
ap_sig_bdd_3298_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3298 <= (ap_const_lv1_1 = ap_CS_fsm(59 downto 59));
end process;
-- ap_sig_bdd_3307 assign process. --
ap_sig_bdd_3307_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3307 <= (ap_const_lv1_1 = ap_CS_fsm(60 downto 60));
end process;
-- ap_sig_bdd_3316 assign process. --
ap_sig_bdd_3316_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3316 <= (ap_const_lv1_1 = ap_CS_fsm(61 downto 61));
end process;
-- ap_sig_bdd_3325 assign process. --
ap_sig_bdd_3325_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3325 <= (ap_const_lv1_1 = ap_CS_fsm(62 downto 62));
end process;
-- ap_sig_bdd_3334 assign process. --
ap_sig_bdd_3334_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3334 <= (ap_const_lv1_1 = ap_CS_fsm(63 downto 63));
end process;
-- ap_sig_bdd_3343 assign process. --
ap_sig_bdd_3343_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3343 <= (ap_const_lv1_1 = ap_CS_fsm(64 downto 64));
end process;
-- ap_sig_bdd_3352 assign process. --
ap_sig_bdd_3352_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3352 <= (ap_const_lv1_1 = ap_CS_fsm(65 downto 65));
end process;
-- ap_sig_bdd_3361 assign process. --
ap_sig_bdd_3361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3361 <= (ap_const_lv1_1 = ap_CS_fsm(66 downto 66));
end process;
-- ap_sig_bdd_3370 assign process. --
ap_sig_bdd_3370_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3370 <= (ap_const_lv1_1 = ap_CS_fsm(67 downto 67));
end process;
-- ap_sig_bdd_3379 assign process. --
ap_sig_bdd_3379_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3379 <= (ap_const_lv1_1 = ap_CS_fsm(68 downto 68));
end process;
-- ap_sig_bdd_3388 assign process. --
ap_sig_bdd_3388_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3388 <= (ap_const_lv1_1 = ap_CS_fsm(69 downto 69));
end process;
-- ap_sig_bdd_3397 assign process. --
ap_sig_bdd_3397_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3397 <= (ap_const_lv1_1 = ap_CS_fsm(70 downto 70));
end process;
-- ap_sig_bdd_3417 assign process. --
ap_sig_bdd_3417_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3417 <= (ap_const_lv1_1 = ap_CS_fsm(74 downto 74));
end process;
-- ap_sig_bdd_3437 assign process. --
ap_sig_bdd_3437_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3437 <= (ap_const_lv1_1 = ap_CS_fsm(89 downto 89));
end process;
-- ap_sig_bdd_3447 assign process. --
ap_sig_bdd_3447_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3447 <= (ap_const_lv1_1 = ap_CS_fsm(104 downto 104));
end process;
-- ap_sig_bdd_3457 assign process. --
ap_sig_bdd_3457_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3457 <= (ap_const_lv1_1 = ap_CS_fsm(119 downto 119));
end process;
-- ap_sig_bdd_3467 assign process. --
ap_sig_bdd_3467_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3467 <= (ap_const_lv1_1 = ap_CS_fsm(134 downto 134));
end process;
-- ap_sig_bdd_3477 assign process. --
ap_sig_bdd_3477_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3477 <= (ap_const_lv1_1 = ap_CS_fsm(149 downto 149));
end process;
-- ap_sig_bdd_3487 assign process. --
ap_sig_bdd_3487_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3487 <= (ap_const_lv1_1 = ap_CS_fsm(164 downto 164));
end process;
-- ap_sig_bdd_3497 assign process. --
ap_sig_bdd_3497_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3497 <= (ap_const_lv1_1 = ap_CS_fsm(179 downto 179));
end process;
-- ap_sig_bdd_3507 assign process. --
ap_sig_bdd_3507_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3507 <= (ap_const_lv1_1 = ap_CS_fsm(194 downto 194));
end process;
-- ap_sig_bdd_3517 assign process. --
ap_sig_bdd_3517_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3517 <= (ap_const_lv1_1 = ap_CS_fsm(209 downto 209));
end process;
-- ap_sig_bdd_3527 assign process. --
ap_sig_bdd_3527_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3527 <= (ap_const_lv1_1 = ap_CS_fsm(224 downto 224));
end process;
-- ap_sig_bdd_3537 assign process. --
ap_sig_bdd_3537_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3537 <= (ap_const_lv1_1 = ap_CS_fsm(239 downto 239));
end process;
-- ap_sig_bdd_3547 assign process. --
ap_sig_bdd_3547_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3547 <= (ap_const_lv1_1 = ap_CS_fsm(299 downto 299));
end process;
-- ap_sig_bdd_399 assign process. --
ap_sig_bdd_399_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_399 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_410 assign process. --
ap_sig_bdd_410_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_410 <= (ap_const_lv1_1 = ap_CS_fsm(72 downto 72));
end process;
-- ap_sig_bdd_419 assign process. --
ap_sig_bdd_419_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_419 <= (ap_const_lv1_1 = ap_CS_fsm(75 downto 75));
end process;
-- ap_sig_bdd_428 assign process. --
ap_sig_bdd_428_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_428 <= (ap_const_lv1_1 = ap_CS_fsm(90 downto 90));
end process;
-- ap_sig_bdd_437 assign process. --
ap_sig_bdd_437_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_437 <= (ap_const_lv1_1 = ap_CS_fsm(105 downto 105));
end process;
-- ap_sig_bdd_446 assign process. --
ap_sig_bdd_446_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_446 <= (ap_const_lv1_1 = ap_CS_fsm(120 downto 120));
end process;
-- ap_sig_bdd_455 assign process. --
ap_sig_bdd_455_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_455 <= (ap_const_lv1_1 = ap_CS_fsm(135 downto 135));
end process;
-- ap_sig_bdd_464 assign process. --
ap_sig_bdd_464_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_464 <= (ap_const_lv1_1 = ap_CS_fsm(150 downto 150));
end process;
-- ap_sig_bdd_473 assign process. --
ap_sig_bdd_473_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_473 <= (ap_const_lv1_1 = ap_CS_fsm(165 downto 165));
end process;
-- ap_sig_bdd_482 assign process. --
ap_sig_bdd_482_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_482 <= (ap_const_lv1_1 = ap_CS_fsm(180 downto 180));
end process;
-- ap_sig_bdd_491 assign process. --
ap_sig_bdd_491_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_491 <= (ap_const_lv1_1 = ap_CS_fsm(195 downto 195));
end process;
-- ap_sig_bdd_500 assign process. --
ap_sig_bdd_500_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_500 <= (ap_const_lv1_1 = ap_CS_fsm(210 downto 210));
end process;
-- ap_sig_bdd_5023 assign process. --
ap_sig_bdd_5023_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5023 <= (ap_const_lv1_1 = ap_CS_fsm(254 downto 254));
end process;
-- ap_sig_bdd_5046 assign process. --
ap_sig_bdd_5046_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5046 <= (ap_const_lv1_1 = ap_CS_fsm(269 downto 269));
end process;
-- ap_sig_bdd_5069 assign process. --
ap_sig_bdd_5069_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5069 <= (ap_const_lv1_1 = ap_CS_fsm(284 downto 284));
end process;
-- ap_sig_bdd_509 assign process. --
ap_sig_bdd_509_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_509 <= (ap_const_lv1_1 = ap_CS_fsm(225 downto 225));
end process;
-- ap_sig_bdd_5096 assign process. --
ap_sig_bdd_5096_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5096 <= (ap_const_lv1_1 = ap_CS_fsm(303 downto 303));
end process;
-- ap_sig_bdd_5104 assign process. --
ap_sig_bdd_5104_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5104 <= (ap_const_lv1_1 = ap_CS_fsm(304 downto 304));
end process;
-- ap_sig_bdd_5113 assign process. --
ap_sig_bdd_5113_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5113 <= (ap_const_lv1_1 = ap_CS_fsm(306 downto 306));
end process;
-- ap_sig_bdd_5121 assign process. --
ap_sig_bdd_5121_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5121 <= (ap_const_lv1_1 = ap_CS_fsm(307 downto 307));
end process;
-- ap_sig_bdd_5130 assign process. --
ap_sig_bdd_5130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5130 <= (ap_const_lv1_1 = ap_CS_fsm(309 downto 309));
end process;
-- ap_sig_bdd_5138 assign process. --
ap_sig_bdd_5138_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5138 <= (ap_const_lv1_1 = ap_CS_fsm(310 downto 310));
end process;
-- ap_sig_bdd_5147 assign process. --
ap_sig_bdd_5147_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5147 <= (ap_const_lv1_1 = ap_CS_fsm(312 downto 312));
end process;
-- ap_sig_bdd_5155 assign process. --
ap_sig_bdd_5155_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5155 <= (ap_const_lv1_1 = ap_CS_fsm(313 downto 313));
end process;
-- ap_sig_bdd_5164 assign process. --
ap_sig_bdd_5164_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5164 <= (ap_const_lv1_1 = ap_CS_fsm(315 downto 315));
end process;
-- ap_sig_bdd_5172 assign process. --
ap_sig_bdd_5172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5172 <= (ap_const_lv1_1 = ap_CS_fsm(316 downto 316));
end process;
-- ap_sig_bdd_518 assign process. --
ap_sig_bdd_518_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_518 <= (ap_const_lv1_1 = ap_CS_fsm(240 downto 240));
end process;
-- ap_sig_bdd_5181 assign process. --
ap_sig_bdd_5181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5181 <= (ap_const_lv1_1 = ap_CS_fsm(318 downto 318));
end process;
-- ap_sig_bdd_5189 assign process. --
ap_sig_bdd_5189_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5189 <= (ap_const_lv1_1 = ap_CS_fsm(319 downto 319));
end process;
-- ap_sig_bdd_5198 assign process. --
ap_sig_bdd_5198_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5198 <= (ap_const_lv1_1 = ap_CS_fsm(321 downto 321));
end process;
-- ap_sig_bdd_5206 assign process. --
ap_sig_bdd_5206_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5206 <= (ap_const_lv1_1 = ap_CS_fsm(322 downto 322));
end process;
-- ap_sig_bdd_5215 assign process. --
ap_sig_bdd_5215_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5215 <= (ap_const_lv1_1 = ap_CS_fsm(324 downto 324));
end process;
-- ap_sig_bdd_5223 assign process. --
ap_sig_bdd_5223_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5223 <= (ap_const_lv1_1 = ap_CS_fsm(325 downto 325));
end process;
-- ap_sig_bdd_5232 assign process. --
ap_sig_bdd_5232_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5232 <= (ap_const_lv1_1 = ap_CS_fsm(327 downto 327));
end process;
-- ap_sig_bdd_5240 assign process. --
ap_sig_bdd_5240_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5240 <= (ap_const_lv1_1 = ap_CS_fsm(328 downto 328));
end process;
-- ap_sig_bdd_5249 assign process. --
ap_sig_bdd_5249_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5249 <= (ap_const_lv1_1 = ap_CS_fsm(330 downto 330));
end process;
-- ap_sig_bdd_5257 assign process. --
ap_sig_bdd_5257_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5257 <= (ap_const_lv1_1 = ap_CS_fsm(331 downto 331));
end process;
-- ap_sig_bdd_5266 assign process. --
ap_sig_bdd_5266_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5266 <= (ap_const_lv1_1 = ap_CS_fsm(333 downto 333));
end process;
-- ap_sig_bdd_527 assign process. --
ap_sig_bdd_527_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_527 <= (ap_const_lv1_1 = ap_CS_fsm(255 downto 255));
end process;
-- ap_sig_bdd_5274 assign process. --
ap_sig_bdd_5274_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5274 <= (ap_const_lv1_1 = ap_CS_fsm(334 downto 334));
end process;
-- ap_sig_bdd_5283 assign process. --
ap_sig_bdd_5283_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5283 <= (ap_const_lv1_1 = ap_CS_fsm(336 downto 336));
end process;
-- ap_sig_bdd_5291 assign process. --
ap_sig_bdd_5291_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5291 <= (ap_const_lv1_1 = ap_CS_fsm(337 downto 337));
end process;
-- ap_sig_bdd_5300 assign process. --
ap_sig_bdd_5300_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5300 <= (ap_const_lv1_1 = ap_CS_fsm(339 downto 339));
end process;
-- ap_sig_bdd_5308 assign process. --
ap_sig_bdd_5308_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5308 <= (ap_const_lv1_1 = ap_CS_fsm(340 downto 340));
end process;
-- ap_sig_bdd_5317 assign process. --
ap_sig_bdd_5317_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5317 <= (ap_const_lv1_1 = ap_CS_fsm(342 downto 342));
end process;
-- ap_sig_bdd_5325 assign process. --
ap_sig_bdd_5325_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5325 <= (ap_const_lv1_1 = ap_CS_fsm(343 downto 343));
end process;
-- ap_sig_bdd_5334 assign process. --
ap_sig_bdd_5334_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5334 <= (ap_const_lv1_1 = ap_CS_fsm(345 downto 345));
end process;
-- ap_sig_bdd_5342 assign process. --
ap_sig_bdd_5342_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5342 <= (ap_const_lv1_1 = ap_CS_fsm(346 downto 346));
end process;
-- ap_sig_bdd_5351 assign process. --
ap_sig_bdd_5351_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5351 <= (ap_const_lv1_1 = ap_CS_fsm(348 downto 348));
end process;
-- ap_sig_bdd_5359 assign process. --
ap_sig_bdd_5359_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5359 <= (ap_const_lv1_1 = ap_CS_fsm(349 downto 349));
end process;
-- ap_sig_bdd_536 assign process. --
ap_sig_bdd_536_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_536 <= (ap_const_lv1_1 = ap_CS_fsm(270 downto 270));
end process;
-- ap_sig_bdd_5368 assign process. --
ap_sig_bdd_5368_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5368 <= (ap_const_lv1_1 = ap_CS_fsm(351 downto 351));
end process;
-- ap_sig_bdd_5376 assign process. --
ap_sig_bdd_5376_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5376 <= (ap_const_lv1_1 = ap_CS_fsm(352 downto 352));
end process;
-- ap_sig_bdd_5385 assign process. --
ap_sig_bdd_5385_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5385 <= (ap_const_lv1_1 = ap_CS_fsm(354 downto 354));
end process;
-- ap_sig_bdd_5393 assign process. --
ap_sig_bdd_5393_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5393 <= (ap_const_lv1_1 = ap_CS_fsm(355 downto 355));
end process;
-- ap_sig_bdd_5402 assign process. --
ap_sig_bdd_5402_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5402 <= (ap_const_lv1_1 = ap_CS_fsm(357 downto 357));
end process;
-- ap_sig_bdd_5410 assign process. --
ap_sig_bdd_5410_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5410 <= (ap_const_lv1_1 = ap_CS_fsm(358 downto 358));
end process;
-- ap_sig_bdd_5419 assign process. --
ap_sig_bdd_5419_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5419 <= (ap_const_lv1_1 = ap_CS_fsm(360 downto 360));
end process;
-- ap_sig_bdd_5427 assign process. --
ap_sig_bdd_5427_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5427 <= (ap_const_lv1_1 = ap_CS_fsm(361 downto 361));
end process;
-- ap_sig_bdd_545 assign process. --
ap_sig_bdd_545_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_545 <= (ap_const_lv1_1 = ap_CS_fsm(285 downto 285));
end process;
-- ap_sig_bdd_555 assign process. --
ap_sig_bdd_555_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_555 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_563 assign process. --
ap_sig_bdd_563_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_563 <= (ap_const_lv1_1 = ap_CS_fsm(73 downto 73));
end process;
-- ap_sig_bdd_572 assign process. --
ap_sig_bdd_572_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_572 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_581 assign process. --
ap_sig_bdd_581_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_581 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_590 assign process. --
ap_sig_bdd_590_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_590 <= (ap_const_lv1_1 = ap_CS_fsm(106 downto 106));
end process;
-- ap_sig_bdd_5902 assign process. --
ap_sig_bdd_5902_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5902 <= (ap_const_lv1_1 = ap_CS_fsm(301 downto 301));
end process;
-- ap_sig_bdd_599 assign process. --
ap_sig_bdd_599_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_599 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_608 assign process. --
ap_sig_bdd_608_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_608 <= (ap_const_lv1_1 = ap_CS_fsm(136 downto 136));
end process;
-- ap_sig_bdd_617 assign process. --
ap_sig_bdd_617_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_617 <= (ap_const_lv1_1 = ap_CS_fsm(151 downto 151));
end process;
-- ap_sig_bdd_626 assign process. --
ap_sig_bdd_626_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_626 <= (ap_const_lv1_1 = ap_CS_fsm(166 downto 166));
end process;
-- ap_sig_bdd_635 assign process. --
ap_sig_bdd_635_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_635 <= (ap_const_lv1_1 = ap_CS_fsm(181 downto 181));
end process;
-- ap_sig_bdd_644 assign process. --
ap_sig_bdd_644_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_644 <= (ap_const_lv1_1 = ap_CS_fsm(196 downto 196));
end process;
-- ap_sig_bdd_653 assign process. --
ap_sig_bdd_653_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_653 <= (ap_const_lv1_1 = ap_CS_fsm(211 downto 211));
end process;
-- ap_sig_bdd_662 assign process. --
ap_sig_bdd_662_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_662 <= (ap_const_lv1_1 = ap_CS_fsm(226 downto 226));
end process;
-- ap_sig_bdd_671 assign process. --
ap_sig_bdd_671_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_671 <= (ap_const_lv1_1 = ap_CS_fsm(241 downto 241));
end process;
-- ap_sig_bdd_680 assign process. --
ap_sig_bdd_680_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_680 <= (ap_const_lv1_1 = ap_CS_fsm(256 downto 256));
end process;
-- ap_sig_bdd_689 assign process. --
ap_sig_bdd_689_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_689 <= (ap_const_lv1_1 = ap_CS_fsm(271 downto 271));
end process;
-- ap_sig_bdd_698 assign process. --
ap_sig_bdd_698_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_698 <= (ap_const_lv1_1 = ap_CS_fsm(286 downto 286));
end process;
-- ap_sig_bdd_708 assign process. --
ap_sig_bdd_708_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_708 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_716 assign process. --
ap_sig_bdd_716_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_716 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_725 assign process. --
ap_sig_bdd_725_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_725 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_734 assign process. --
ap_sig_bdd_734_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_734 <= (ap_const_lv1_1 = ap_CS_fsm(107 downto 107));
end process;
-- ap_sig_bdd_743 assign process. --
ap_sig_bdd_743_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_743 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_752 assign process. --
ap_sig_bdd_752_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_752 <= (ap_const_lv1_1 = ap_CS_fsm(137 downto 137));
end process;
-- ap_sig_bdd_761 assign process. --
ap_sig_bdd_761_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_761 <= (ap_const_lv1_1 = ap_CS_fsm(152 downto 152));
end process;
-- ap_sig_bdd_770 assign process. --
ap_sig_bdd_770_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_770 <= (ap_const_lv1_1 = ap_CS_fsm(167 downto 167));
end process;
-- ap_sig_bdd_779 assign process. --
ap_sig_bdd_779_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_779 <= (ap_const_lv1_1 = ap_CS_fsm(182 downto 182));
end process;
-- ap_sig_bdd_788 assign process. --
ap_sig_bdd_788_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_788 <= (ap_const_lv1_1 = ap_CS_fsm(197 downto 197));
end process;
-- ap_sig_bdd_797 assign process. --
ap_sig_bdd_797_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_797 <= (ap_const_lv1_1 = ap_CS_fsm(212 downto 212));
end process;
-- ap_sig_bdd_806 assign process. --
ap_sig_bdd_806_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_806 <= (ap_const_lv1_1 = ap_CS_fsm(227 downto 227));
end process;
-- ap_sig_bdd_815 assign process. --
ap_sig_bdd_815_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_815 <= (ap_const_lv1_1 = ap_CS_fsm(242 downto 242));
end process;
-- ap_sig_bdd_824 assign process. --
ap_sig_bdd_824_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_824 <= (ap_const_lv1_1 = ap_CS_fsm(257 downto 257));
end process;
-- ap_sig_bdd_833 assign process. --
ap_sig_bdd_833_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_833 <= (ap_const_lv1_1 = ap_CS_fsm(272 downto 272));
end process;
-- ap_sig_bdd_842 assign process. --
ap_sig_bdd_842_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_842 <= (ap_const_lv1_1 = ap_CS_fsm(287 downto 287));
end process;
-- ap_sig_bdd_852 assign process. --
ap_sig_bdd_852_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_852 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_860 assign process. --
ap_sig_bdd_860_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_860 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_869 assign process. --
ap_sig_bdd_869_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_869 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_878 assign process. --
ap_sig_bdd_878_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_878 <= (ap_const_lv1_1 = ap_CS_fsm(108 downto 108));
end process;
-- ap_sig_bdd_887 assign process. --
ap_sig_bdd_887_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_887 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_896 assign process. --
ap_sig_bdd_896_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_896 <= (ap_const_lv1_1 = ap_CS_fsm(138 downto 138));
end process;
-- ap_sig_bdd_905 assign process. --
ap_sig_bdd_905_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_905 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_914 assign process. --
ap_sig_bdd_914_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_914 <= (ap_const_lv1_1 = ap_CS_fsm(168 downto 168));
end process;
-- ap_sig_bdd_923 assign process. --
ap_sig_bdd_923_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_923 <= (ap_const_lv1_1 = ap_CS_fsm(183 downto 183));
end process;
-- ap_sig_bdd_932 assign process. --
ap_sig_bdd_932_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_932 <= (ap_const_lv1_1 = ap_CS_fsm(198 downto 198));
end process;
-- ap_sig_bdd_941 assign process. --
ap_sig_bdd_941_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_941 <= (ap_const_lv1_1 = ap_CS_fsm(213 downto 213));
end process;
-- ap_sig_bdd_950 assign process. --
ap_sig_bdd_950_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_950 <= (ap_const_lv1_1 = ap_CS_fsm(228 downto 228));
end process;
-- ap_sig_bdd_959 assign process. --
ap_sig_bdd_959_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_959 <= (ap_const_lv1_1 = ap_CS_fsm(243 downto 243));
end process;
-- ap_sig_bdd_968 assign process. --
ap_sig_bdd_968_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_968 <= (ap_const_lv1_1 = ap_CS_fsm(258 downto 258));
end process;
-- ap_sig_bdd_977 assign process. --
ap_sig_bdd_977_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_977 <= (ap_const_lv1_1 = ap_CS_fsm(273 downto 273));
end process;
-- ap_sig_bdd_986 assign process. --
ap_sig_bdd_986_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_986 <= (ap_const_lv1_1 = ap_CS_fsm(288 downto 288));
end process;
-- ap_sig_bdd_996 assign process. --
ap_sig_bdd_996_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_996 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_300 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_300_assign_proc : process(ap_sig_bdd_2694)
begin
if (ap_sig_bdd_2694) then
ap_sig_cseq_ST_pp0_stg0_fsm_300 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_300 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st100_fsm_99 assign process. --
ap_sig_cseq_ST_st100_fsm_99_assign_proc : process(ap_sig_bdd_1733)
begin
if (ap_sig_bdd_1733) then
ap_sig_cseq_ST_st100_fsm_99 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st100_fsm_99 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st101_fsm_100 assign process. --
ap_sig_cseq_ST_st101_fsm_100_assign_proc : process(ap_sig_bdd_1877)
begin
if (ap_sig_bdd_1877) then
ap_sig_cseq_ST_st101_fsm_100 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st101_fsm_100 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st102_fsm_101 assign process. --
ap_sig_cseq_ST_st102_fsm_101_assign_proc : process(ap_sig_bdd_2021)
begin
if (ap_sig_bdd_2021) then
ap_sig_cseq_ST_st102_fsm_101 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st102_fsm_101 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st103_fsm_102 assign process. --
ap_sig_cseq_ST_st103_fsm_102_assign_proc : process(ap_sig_bdd_2165)
begin
if (ap_sig_bdd_2165) then
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st104_fsm_103 assign process. --
ap_sig_cseq_ST_st104_fsm_103_assign_proc : process(ap_sig_bdd_2309)
begin
if (ap_sig_bdd_2309) then
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st105_fsm_104 assign process. --
ap_sig_cseq_ST_st105_fsm_104_assign_proc : process(ap_sig_bdd_3447)
begin
if (ap_sig_bdd_3447) then
ap_sig_cseq_ST_st105_fsm_104 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st105_fsm_104 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st106_fsm_105 assign process. --
ap_sig_cseq_ST_st106_fsm_105_assign_proc : process(ap_sig_bdd_437)
begin
if (ap_sig_bdd_437) then
ap_sig_cseq_ST_st106_fsm_105 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st106_fsm_105 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st107_fsm_106 assign process. --
ap_sig_cseq_ST_st107_fsm_106_assign_proc : process(ap_sig_bdd_590)
begin
if (ap_sig_bdd_590) then
ap_sig_cseq_ST_st107_fsm_106 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st107_fsm_106 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st108_fsm_107 assign process. --
ap_sig_cseq_ST_st108_fsm_107_assign_proc : process(ap_sig_bdd_734)
begin
if (ap_sig_bdd_734) then
ap_sig_cseq_ST_st108_fsm_107 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st108_fsm_107 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st109_fsm_108 assign process. --
ap_sig_cseq_ST_st109_fsm_108_assign_proc : process(ap_sig_bdd_878)
begin
if (ap_sig_bdd_878) then
ap_sig_cseq_ST_st109_fsm_108 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st109_fsm_108 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_1716)
begin
if (ap_sig_bdd_1716) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st110_fsm_109 assign process. --
ap_sig_cseq_ST_st110_fsm_109_assign_proc : process(ap_sig_bdd_1022)
begin
if (ap_sig_bdd_1022) then
ap_sig_cseq_ST_st110_fsm_109 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st110_fsm_109 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st111_fsm_110 assign process. --
ap_sig_cseq_ST_st111_fsm_110_assign_proc : process(ap_sig_bdd_1166)
begin
if (ap_sig_bdd_1166) then
ap_sig_cseq_ST_st111_fsm_110 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st111_fsm_110 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st112_fsm_111 assign process. --
ap_sig_cseq_ST_st112_fsm_111_assign_proc : process(ap_sig_bdd_1310)
begin
if (ap_sig_bdd_1310) then
ap_sig_cseq_ST_st112_fsm_111 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st112_fsm_111 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st113_fsm_112 assign process. --
ap_sig_cseq_ST_st113_fsm_112_assign_proc : process(ap_sig_bdd_1454)
begin
if (ap_sig_bdd_1454) then
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st114_fsm_113 assign process. --
ap_sig_cseq_ST_st114_fsm_113_assign_proc : process(ap_sig_bdd_1598)
begin
if (ap_sig_bdd_1598) then
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st115_fsm_114 assign process. --
ap_sig_cseq_ST_st115_fsm_114_assign_proc : process(ap_sig_bdd_1742)
begin
if (ap_sig_bdd_1742) then
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st116_fsm_115 assign process. --
ap_sig_cseq_ST_st116_fsm_115_assign_proc : process(ap_sig_bdd_1886)
begin
if (ap_sig_bdd_1886) then
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_2030)
begin
if (ap_sig_bdd_2030) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_2174)
begin
if (ap_sig_bdd_2174) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_2318)
begin
if (ap_sig_bdd_2318) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_1860)
begin
if (ap_sig_bdd_1860) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st120_fsm_119 assign process. --
ap_sig_cseq_ST_st120_fsm_119_assign_proc : process(ap_sig_bdd_3457)
begin
if (ap_sig_bdd_3457) then
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_120 assign process. --
ap_sig_cseq_ST_st121_fsm_120_assign_proc : process(ap_sig_bdd_446)
begin
if (ap_sig_bdd_446) then
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_599)
begin
if (ap_sig_bdd_599) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_743)
begin
if (ap_sig_bdd_743) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_887)
begin
if (ap_sig_bdd_887) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st125_fsm_124 assign process. --
ap_sig_cseq_ST_st125_fsm_124_assign_proc : process(ap_sig_bdd_1031)
begin
if (ap_sig_bdd_1031) then
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st126_fsm_125 assign process. --
ap_sig_cseq_ST_st126_fsm_125_assign_proc : process(ap_sig_bdd_1175)
begin
if (ap_sig_bdd_1175) then
ap_sig_cseq_ST_st126_fsm_125 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st126_fsm_125 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st127_fsm_126 assign process. --
ap_sig_cseq_ST_st127_fsm_126_assign_proc : process(ap_sig_bdd_1319)
begin
if (ap_sig_bdd_1319) then
ap_sig_cseq_ST_st127_fsm_126 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st127_fsm_126 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st128_fsm_127 assign process. --
ap_sig_cseq_ST_st128_fsm_127_assign_proc : process(ap_sig_bdd_1463)
begin
if (ap_sig_bdd_1463) then
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st129_fsm_128 assign process. --
ap_sig_cseq_ST_st129_fsm_128_assign_proc : process(ap_sig_bdd_1607)
begin
if (ap_sig_bdd_1607) then
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_2004)
begin
if (ap_sig_bdd_2004) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st130_fsm_129 assign process. --
ap_sig_cseq_ST_st130_fsm_129_assign_proc : process(ap_sig_bdd_1751)
begin
if (ap_sig_bdd_1751) then
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st131_fsm_130 assign process. --
ap_sig_cseq_ST_st131_fsm_130_assign_proc : process(ap_sig_bdd_1895)
begin
if (ap_sig_bdd_1895) then
ap_sig_cseq_ST_st131_fsm_130 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st131_fsm_130 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st132_fsm_131 assign process. --
ap_sig_cseq_ST_st132_fsm_131_assign_proc : process(ap_sig_bdd_2039)
begin
if (ap_sig_bdd_2039) then
ap_sig_cseq_ST_st132_fsm_131 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st132_fsm_131 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st133_fsm_132 assign process. --
ap_sig_cseq_ST_st133_fsm_132_assign_proc : process(ap_sig_bdd_2183)
begin
if (ap_sig_bdd_2183) then
ap_sig_cseq_ST_st133_fsm_132 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st133_fsm_132 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st134_fsm_133 assign process. --
ap_sig_cseq_ST_st134_fsm_133_assign_proc : process(ap_sig_bdd_2327)
begin
if (ap_sig_bdd_2327) then
ap_sig_cseq_ST_st134_fsm_133 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st134_fsm_133 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st135_fsm_134 assign process. --
ap_sig_cseq_ST_st135_fsm_134_assign_proc : process(ap_sig_bdd_3467)
begin
if (ap_sig_bdd_3467) then
ap_sig_cseq_ST_st135_fsm_134 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st135_fsm_134 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st136_fsm_135 assign process. --
ap_sig_cseq_ST_st136_fsm_135_assign_proc : process(ap_sig_bdd_455)
begin
if (ap_sig_bdd_455) then
ap_sig_cseq_ST_st136_fsm_135 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st136_fsm_135 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st137_fsm_136 assign process. --
ap_sig_cseq_ST_st137_fsm_136_assign_proc : process(ap_sig_bdd_608)
begin
if (ap_sig_bdd_608) then
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st138_fsm_137 assign process. --
ap_sig_cseq_ST_st138_fsm_137_assign_proc : process(ap_sig_bdd_752)
begin
if (ap_sig_bdd_752) then
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st139_fsm_138 assign process. --
ap_sig_cseq_ST_st139_fsm_138_assign_proc : process(ap_sig_bdd_896)
begin
if (ap_sig_bdd_896) then
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_2148)
begin
if (ap_sig_bdd_2148) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st140_fsm_139 assign process. --
ap_sig_cseq_ST_st140_fsm_139_assign_proc : process(ap_sig_bdd_1040)
begin
if (ap_sig_bdd_1040) then
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_1184)
begin
if (ap_sig_bdd_1184) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_1328)
begin
if (ap_sig_bdd_1328) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_1472)
begin
if (ap_sig_bdd_1472) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_1616)
begin
if (ap_sig_bdd_1616) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_1760)
begin
if (ap_sig_bdd_1760) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_1904)
begin
if (ap_sig_bdd_1904) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_2048)
begin
if (ap_sig_bdd_2048) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_2192)
begin
if (ap_sig_bdd_2192) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_2336)
begin
if (ap_sig_bdd_2336) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_2292)
begin
if (ap_sig_bdd_2292) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st150_fsm_149 assign process. --
ap_sig_cseq_ST_st150_fsm_149_assign_proc : process(ap_sig_bdd_3477)
begin
if (ap_sig_bdd_3477) then
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st151_fsm_150 assign process. --
ap_sig_cseq_ST_st151_fsm_150_assign_proc : process(ap_sig_bdd_464)
begin
if (ap_sig_bdd_464) then
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st152_fsm_151 assign process. --
ap_sig_cseq_ST_st152_fsm_151_assign_proc : process(ap_sig_bdd_617)
begin
if (ap_sig_bdd_617) then
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st153_fsm_152 assign process. --
ap_sig_cseq_ST_st153_fsm_152_assign_proc : process(ap_sig_bdd_761)
begin
if (ap_sig_bdd_761) then
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_905)
begin
if (ap_sig_bdd_905) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st155_fsm_154 assign process. --
ap_sig_cseq_ST_st155_fsm_154_assign_proc : process(ap_sig_bdd_1049)
begin
if (ap_sig_bdd_1049) then
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st156_fsm_155 assign process. --
ap_sig_cseq_ST_st156_fsm_155_assign_proc : process(ap_sig_bdd_1193)
begin
if (ap_sig_bdd_1193) then
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st157_fsm_156 assign process. --
ap_sig_cseq_ST_st157_fsm_156_assign_proc : process(ap_sig_bdd_1337)
begin
if (ap_sig_bdd_1337) then
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st158_fsm_157 assign process. --
ap_sig_cseq_ST_st158_fsm_157_assign_proc : process(ap_sig_bdd_1481)
begin
if (ap_sig_bdd_1481) then
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st159_fsm_158 assign process. --
ap_sig_cseq_ST_st159_fsm_158_assign_proc : process(ap_sig_bdd_1625)
begin
if (ap_sig_bdd_1625) then
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_2893)
begin
if (ap_sig_bdd_2893) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st160_fsm_159 assign process. --
ap_sig_cseq_ST_st160_fsm_159_assign_proc : process(ap_sig_bdd_1769)
begin
if (ap_sig_bdd_1769) then
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st161_fsm_160 assign process. --
ap_sig_cseq_ST_st161_fsm_160_assign_proc : process(ap_sig_bdd_1913)
begin
if (ap_sig_bdd_1913) then
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st162_fsm_161 assign process. --
ap_sig_cseq_ST_st162_fsm_161_assign_proc : process(ap_sig_bdd_2057)
begin
if (ap_sig_bdd_2057) then
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st163_fsm_162 assign process. --
ap_sig_cseq_ST_st163_fsm_162_assign_proc : process(ap_sig_bdd_2201)
begin
if (ap_sig_bdd_2201) then
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st164_fsm_163 assign process. --
ap_sig_cseq_ST_st164_fsm_163_assign_proc : process(ap_sig_bdd_2345)
begin
if (ap_sig_bdd_2345) then
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st165_fsm_164 assign process. --
ap_sig_cseq_ST_st165_fsm_164_assign_proc : process(ap_sig_bdd_3487)
begin
if (ap_sig_bdd_3487) then
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st166_fsm_165 assign process. --
ap_sig_cseq_ST_st166_fsm_165_assign_proc : process(ap_sig_bdd_473)
begin
if (ap_sig_bdd_473) then
ap_sig_cseq_ST_st166_fsm_165 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st166_fsm_165 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st167_fsm_166 assign process. --
ap_sig_cseq_ST_st167_fsm_166_assign_proc : process(ap_sig_bdd_626)
begin
if (ap_sig_bdd_626) then
ap_sig_cseq_ST_st167_fsm_166 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st167_fsm_166 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st168_fsm_167 assign process. --
ap_sig_cseq_ST_st168_fsm_167_assign_proc : process(ap_sig_bdd_770)
begin
if (ap_sig_bdd_770) then
ap_sig_cseq_ST_st168_fsm_167 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st168_fsm_167 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st169_fsm_168 assign process. --
ap_sig_cseq_ST_st169_fsm_168_assign_proc : process(ap_sig_bdd_914)
begin
if (ap_sig_bdd_914) then
ap_sig_cseq_ST_st169_fsm_168 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st169_fsm_168 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_2902)
begin
if (ap_sig_bdd_2902) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st170_fsm_169 assign process. --
ap_sig_cseq_ST_st170_fsm_169_assign_proc : process(ap_sig_bdd_1058)
begin
if (ap_sig_bdd_1058) then
ap_sig_cseq_ST_st170_fsm_169 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st170_fsm_169 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st171_fsm_170 assign process. --
ap_sig_cseq_ST_st171_fsm_170_assign_proc : process(ap_sig_bdd_1202)
begin
if (ap_sig_bdd_1202) then
ap_sig_cseq_ST_st171_fsm_170 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st171_fsm_170 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st172_fsm_171 assign process. --
ap_sig_cseq_ST_st172_fsm_171_assign_proc : process(ap_sig_bdd_1346)
begin
if (ap_sig_bdd_1346) then
ap_sig_cseq_ST_st172_fsm_171 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st172_fsm_171 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st173_fsm_172 assign process. --
ap_sig_cseq_ST_st173_fsm_172_assign_proc : process(ap_sig_bdd_1490)
begin
if (ap_sig_bdd_1490) then
ap_sig_cseq_ST_st173_fsm_172 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st173_fsm_172 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st174_fsm_173 assign process. --
ap_sig_cseq_ST_st174_fsm_173_assign_proc : process(ap_sig_bdd_1634)
begin
if (ap_sig_bdd_1634) then
ap_sig_cseq_ST_st174_fsm_173 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st174_fsm_173 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st175_fsm_174 assign process. --
ap_sig_cseq_ST_st175_fsm_174_assign_proc : process(ap_sig_bdd_1778)
begin
if (ap_sig_bdd_1778) then
ap_sig_cseq_ST_st175_fsm_174 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st175_fsm_174 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st176_fsm_175 assign process. --
ap_sig_cseq_ST_st176_fsm_175_assign_proc : process(ap_sig_bdd_1922)
begin
if (ap_sig_bdd_1922) then
ap_sig_cseq_ST_st176_fsm_175 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st176_fsm_175 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st177_fsm_176 assign process. --
ap_sig_cseq_ST_st177_fsm_176_assign_proc : process(ap_sig_bdd_2066)
begin
if (ap_sig_bdd_2066) then
ap_sig_cseq_ST_st177_fsm_176 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st177_fsm_176 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st178_fsm_177 assign process. --
ap_sig_cseq_ST_st178_fsm_177_assign_proc : process(ap_sig_bdd_2210)
begin
if (ap_sig_bdd_2210) then
ap_sig_cseq_ST_st178_fsm_177 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st178_fsm_177 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st179_fsm_178 assign process. --
ap_sig_cseq_ST_st179_fsm_178_assign_proc : process(ap_sig_bdd_2354)
begin
if (ap_sig_bdd_2354) then
ap_sig_cseq_ST_st179_fsm_178 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st179_fsm_178 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_2911)
begin
if (ap_sig_bdd_2911) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st180_fsm_179 assign process. --
ap_sig_cseq_ST_st180_fsm_179_assign_proc : process(ap_sig_bdd_3497)
begin
if (ap_sig_bdd_3497) then
ap_sig_cseq_ST_st180_fsm_179 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st180_fsm_179 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st181_fsm_180 assign process. --
ap_sig_cseq_ST_st181_fsm_180_assign_proc : process(ap_sig_bdd_482)
begin
if (ap_sig_bdd_482) then
ap_sig_cseq_ST_st181_fsm_180 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st181_fsm_180 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st182_fsm_181 assign process. --
ap_sig_cseq_ST_st182_fsm_181_assign_proc : process(ap_sig_bdd_635)
begin
if (ap_sig_bdd_635) then
ap_sig_cseq_ST_st182_fsm_181 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st182_fsm_181 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st183_fsm_182 assign process. --
ap_sig_cseq_ST_st183_fsm_182_assign_proc : process(ap_sig_bdd_779)
begin
if (ap_sig_bdd_779) then
ap_sig_cseq_ST_st183_fsm_182 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st183_fsm_182 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st184_fsm_183 assign process. --
ap_sig_cseq_ST_st184_fsm_183_assign_proc : process(ap_sig_bdd_923)
begin
if (ap_sig_bdd_923) then
ap_sig_cseq_ST_st184_fsm_183 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st184_fsm_183 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st185_fsm_184 assign process. --
ap_sig_cseq_ST_st185_fsm_184_assign_proc : process(ap_sig_bdd_1067)
begin
if (ap_sig_bdd_1067) then
ap_sig_cseq_ST_st185_fsm_184 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st185_fsm_184 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st186_fsm_185 assign process. --
ap_sig_cseq_ST_st186_fsm_185_assign_proc : process(ap_sig_bdd_1211)
begin
if (ap_sig_bdd_1211) then
ap_sig_cseq_ST_st186_fsm_185 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st186_fsm_185 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st187_fsm_186 assign process. --
ap_sig_cseq_ST_st187_fsm_186_assign_proc : process(ap_sig_bdd_1355)
begin
if (ap_sig_bdd_1355) then
ap_sig_cseq_ST_st187_fsm_186 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st187_fsm_186 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st188_fsm_187 assign process. --
ap_sig_cseq_ST_st188_fsm_187_assign_proc : process(ap_sig_bdd_1499)
begin
if (ap_sig_bdd_1499) then
ap_sig_cseq_ST_st188_fsm_187 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st188_fsm_187 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st189_fsm_188 assign process. --
ap_sig_cseq_ST_st189_fsm_188_assign_proc : process(ap_sig_bdd_1643)
begin
if (ap_sig_bdd_1643) then
ap_sig_cseq_ST_st189_fsm_188 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st189_fsm_188 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_2920)
begin
if (ap_sig_bdd_2920) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st190_fsm_189 assign process. --
ap_sig_cseq_ST_st190_fsm_189_assign_proc : process(ap_sig_bdd_1787)
begin
if (ap_sig_bdd_1787) then
ap_sig_cseq_ST_st190_fsm_189 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st190_fsm_189 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st191_fsm_190 assign process. --
ap_sig_cseq_ST_st191_fsm_190_assign_proc : process(ap_sig_bdd_1931)
begin
if (ap_sig_bdd_1931) then
ap_sig_cseq_ST_st191_fsm_190 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st191_fsm_190 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st192_fsm_191 assign process. --
ap_sig_cseq_ST_st192_fsm_191_assign_proc : process(ap_sig_bdd_2075)
begin
if (ap_sig_bdd_2075) then
ap_sig_cseq_ST_st192_fsm_191 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st192_fsm_191 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st193_fsm_192 assign process. --
ap_sig_cseq_ST_st193_fsm_192_assign_proc : process(ap_sig_bdd_2219)
begin
if (ap_sig_bdd_2219) then
ap_sig_cseq_ST_st193_fsm_192 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st193_fsm_192 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st194_fsm_193 assign process. --
ap_sig_cseq_ST_st194_fsm_193_assign_proc : process(ap_sig_bdd_2363)
begin
if (ap_sig_bdd_2363) then
ap_sig_cseq_ST_st194_fsm_193 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st194_fsm_193 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st195_fsm_194 assign process. --
ap_sig_cseq_ST_st195_fsm_194_assign_proc : process(ap_sig_bdd_3507)
begin
if (ap_sig_bdd_3507) then
ap_sig_cseq_ST_st195_fsm_194 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st195_fsm_194 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st196_fsm_195 assign process. --
ap_sig_cseq_ST_st196_fsm_195_assign_proc : process(ap_sig_bdd_491)
begin
if (ap_sig_bdd_491) then
ap_sig_cseq_ST_st196_fsm_195 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st196_fsm_195 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st197_fsm_196 assign process. --
ap_sig_cseq_ST_st197_fsm_196_assign_proc : process(ap_sig_bdd_644)
begin
if (ap_sig_bdd_644) then
ap_sig_cseq_ST_st197_fsm_196 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st197_fsm_196 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st198_fsm_197 assign process. --
ap_sig_cseq_ST_st198_fsm_197_assign_proc : process(ap_sig_bdd_788)
begin
if (ap_sig_bdd_788) then
ap_sig_cseq_ST_st198_fsm_197 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st198_fsm_197 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st199_fsm_198 assign process. --
ap_sig_cseq_ST_st199_fsm_198_assign_proc : process(ap_sig_bdd_932)
begin
if (ap_sig_bdd_932) then
ap_sig_cseq_ST_st199_fsm_198 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st199_fsm_198 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_2929)
begin
if (ap_sig_bdd_2929) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_399)
begin
if (ap_sig_bdd_399) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st200_fsm_199 assign process. --
ap_sig_cseq_ST_st200_fsm_199_assign_proc : process(ap_sig_bdd_1076)
begin
if (ap_sig_bdd_1076) then
ap_sig_cseq_ST_st200_fsm_199 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st200_fsm_199 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st201_fsm_200 assign process. --
ap_sig_cseq_ST_st201_fsm_200_assign_proc : process(ap_sig_bdd_1220)
begin
if (ap_sig_bdd_1220) then
ap_sig_cseq_ST_st201_fsm_200 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st201_fsm_200 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st202_fsm_201 assign process. --
ap_sig_cseq_ST_st202_fsm_201_assign_proc : process(ap_sig_bdd_1364)
begin
if (ap_sig_bdd_1364) then
ap_sig_cseq_ST_st202_fsm_201 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st202_fsm_201 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st203_fsm_202 assign process. --
ap_sig_cseq_ST_st203_fsm_202_assign_proc : process(ap_sig_bdd_1508)
begin
if (ap_sig_bdd_1508) then
ap_sig_cseq_ST_st203_fsm_202 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st203_fsm_202 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st204_fsm_203 assign process. --
ap_sig_cseq_ST_st204_fsm_203_assign_proc : process(ap_sig_bdd_1652)
begin
if (ap_sig_bdd_1652) then
ap_sig_cseq_ST_st204_fsm_203 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st204_fsm_203 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st205_fsm_204 assign process. --
ap_sig_cseq_ST_st205_fsm_204_assign_proc : process(ap_sig_bdd_1796)
begin
if (ap_sig_bdd_1796) then
ap_sig_cseq_ST_st205_fsm_204 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st205_fsm_204 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st206_fsm_205 assign process. --
ap_sig_cseq_ST_st206_fsm_205_assign_proc : process(ap_sig_bdd_1940)
begin
if (ap_sig_bdd_1940) then
ap_sig_cseq_ST_st206_fsm_205 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st206_fsm_205 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st207_fsm_206 assign process. --
ap_sig_cseq_ST_st207_fsm_206_assign_proc : process(ap_sig_bdd_2084)
begin
if (ap_sig_bdd_2084) then
ap_sig_cseq_ST_st207_fsm_206 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st207_fsm_206 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st208_fsm_207 assign process. --
ap_sig_cseq_ST_st208_fsm_207_assign_proc : process(ap_sig_bdd_2228)
begin
if (ap_sig_bdd_2228) then
ap_sig_cseq_ST_st208_fsm_207 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st208_fsm_207 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st209_fsm_208 assign process. --
ap_sig_cseq_ST_st209_fsm_208_assign_proc : process(ap_sig_bdd_2372)
begin
if (ap_sig_bdd_2372) then
ap_sig_cseq_ST_st209_fsm_208 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st209_fsm_208 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_2938)
begin
if (ap_sig_bdd_2938) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st210_fsm_209 assign process. --
ap_sig_cseq_ST_st210_fsm_209_assign_proc : process(ap_sig_bdd_3517)
begin
if (ap_sig_bdd_3517) then
ap_sig_cseq_ST_st210_fsm_209 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st210_fsm_209 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st211_fsm_210 assign process. --
ap_sig_cseq_ST_st211_fsm_210_assign_proc : process(ap_sig_bdd_500)
begin
if (ap_sig_bdd_500) then
ap_sig_cseq_ST_st211_fsm_210 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st211_fsm_210 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st212_fsm_211 assign process. --
ap_sig_cseq_ST_st212_fsm_211_assign_proc : process(ap_sig_bdd_653)
begin
if (ap_sig_bdd_653) then
ap_sig_cseq_ST_st212_fsm_211 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st212_fsm_211 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st213_fsm_212 assign process. --
ap_sig_cseq_ST_st213_fsm_212_assign_proc : process(ap_sig_bdd_797)
begin
if (ap_sig_bdd_797) then
ap_sig_cseq_ST_st213_fsm_212 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st213_fsm_212 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st214_fsm_213 assign process. --
ap_sig_cseq_ST_st214_fsm_213_assign_proc : process(ap_sig_bdd_941)
begin
if (ap_sig_bdd_941) then
ap_sig_cseq_ST_st214_fsm_213 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st214_fsm_213 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st215_fsm_214 assign process. --
ap_sig_cseq_ST_st215_fsm_214_assign_proc : process(ap_sig_bdd_1085)
begin
if (ap_sig_bdd_1085) then
ap_sig_cseq_ST_st215_fsm_214 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st215_fsm_214 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st216_fsm_215 assign process. --
ap_sig_cseq_ST_st216_fsm_215_assign_proc : process(ap_sig_bdd_1229)
begin
if (ap_sig_bdd_1229) then
ap_sig_cseq_ST_st216_fsm_215 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st216_fsm_215 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st217_fsm_216 assign process. --
ap_sig_cseq_ST_st217_fsm_216_assign_proc : process(ap_sig_bdd_1373)
begin
if (ap_sig_bdd_1373) then
ap_sig_cseq_ST_st217_fsm_216 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st217_fsm_216 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st218_fsm_217 assign process. --
ap_sig_cseq_ST_st218_fsm_217_assign_proc : process(ap_sig_bdd_1517)
begin
if (ap_sig_bdd_1517) then
ap_sig_cseq_ST_st218_fsm_217 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st218_fsm_217 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st219_fsm_218 assign process. --
ap_sig_cseq_ST_st219_fsm_218_assign_proc : process(ap_sig_bdd_1661)
begin
if (ap_sig_bdd_1661) then
ap_sig_cseq_ST_st219_fsm_218 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st219_fsm_218 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_2947)
begin
if (ap_sig_bdd_2947) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st220_fsm_219 assign process. --
ap_sig_cseq_ST_st220_fsm_219_assign_proc : process(ap_sig_bdd_1805)
begin
if (ap_sig_bdd_1805) then
ap_sig_cseq_ST_st220_fsm_219 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st220_fsm_219 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st221_fsm_220 assign process. --
ap_sig_cseq_ST_st221_fsm_220_assign_proc : process(ap_sig_bdd_1949)
begin
if (ap_sig_bdd_1949) then
ap_sig_cseq_ST_st221_fsm_220 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st221_fsm_220 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st222_fsm_221 assign process. --
ap_sig_cseq_ST_st222_fsm_221_assign_proc : process(ap_sig_bdd_2093)
begin
if (ap_sig_bdd_2093) then
ap_sig_cseq_ST_st222_fsm_221 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st222_fsm_221 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st223_fsm_222 assign process. --
ap_sig_cseq_ST_st223_fsm_222_assign_proc : process(ap_sig_bdd_2237)
begin
if (ap_sig_bdd_2237) then
ap_sig_cseq_ST_st223_fsm_222 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st223_fsm_222 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st224_fsm_223 assign process. --
ap_sig_cseq_ST_st224_fsm_223_assign_proc : process(ap_sig_bdd_2381)
begin
if (ap_sig_bdd_2381) then
ap_sig_cseq_ST_st224_fsm_223 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st224_fsm_223 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st225_fsm_224 assign process. --
ap_sig_cseq_ST_st225_fsm_224_assign_proc : process(ap_sig_bdd_3527)
begin
if (ap_sig_bdd_3527) then
ap_sig_cseq_ST_st225_fsm_224 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st225_fsm_224 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st226_fsm_225 assign process. --
ap_sig_cseq_ST_st226_fsm_225_assign_proc : process(ap_sig_bdd_509)
begin
if (ap_sig_bdd_509) then
ap_sig_cseq_ST_st226_fsm_225 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st226_fsm_225 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st227_fsm_226 assign process. --
ap_sig_cseq_ST_st227_fsm_226_assign_proc : process(ap_sig_bdd_662)
begin
if (ap_sig_bdd_662) then
ap_sig_cseq_ST_st227_fsm_226 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st227_fsm_226 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st228_fsm_227 assign process. --
ap_sig_cseq_ST_st228_fsm_227_assign_proc : process(ap_sig_bdd_806)
begin
if (ap_sig_bdd_806) then
ap_sig_cseq_ST_st228_fsm_227 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st228_fsm_227 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st229_fsm_228 assign process. --
ap_sig_cseq_ST_st229_fsm_228_assign_proc : process(ap_sig_bdd_950)
begin
if (ap_sig_bdd_950) then
ap_sig_cseq_ST_st229_fsm_228 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st229_fsm_228 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_2956)
begin
if (ap_sig_bdd_2956) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st230_fsm_229 assign process. --
ap_sig_cseq_ST_st230_fsm_229_assign_proc : process(ap_sig_bdd_1094)
begin
if (ap_sig_bdd_1094) then
ap_sig_cseq_ST_st230_fsm_229 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st230_fsm_229 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st231_fsm_230 assign process. --
ap_sig_cseq_ST_st231_fsm_230_assign_proc : process(ap_sig_bdd_1238)
begin
if (ap_sig_bdd_1238) then
ap_sig_cseq_ST_st231_fsm_230 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st231_fsm_230 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st232_fsm_231 assign process. --
ap_sig_cseq_ST_st232_fsm_231_assign_proc : process(ap_sig_bdd_1382)
begin
if (ap_sig_bdd_1382) then
ap_sig_cseq_ST_st232_fsm_231 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st232_fsm_231 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st233_fsm_232 assign process. --
ap_sig_cseq_ST_st233_fsm_232_assign_proc : process(ap_sig_bdd_1526)
begin
if (ap_sig_bdd_1526) then
ap_sig_cseq_ST_st233_fsm_232 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st233_fsm_232 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st234_fsm_233 assign process. --
ap_sig_cseq_ST_st234_fsm_233_assign_proc : process(ap_sig_bdd_1670)
begin
if (ap_sig_bdd_1670) then
ap_sig_cseq_ST_st234_fsm_233 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st234_fsm_233 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st235_fsm_234 assign process. --
ap_sig_cseq_ST_st235_fsm_234_assign_proc : process(ap_sig_bdd_1814)
begin
if (ap_sig_bdd_1814) then
ap_sig_cseq_ST_st235_fsm_234 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st235_fsm_234 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st236_fsm_235 assign process. --
ap_sig_cseq_ST_st236_fsm_235_assign_proc : process(ap_sig_bdd_1958)
begin
if (ap_sig_bdd_1958) then
ap_sig_cseq_ST_st236_fsm_235 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st236_fsm_235 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st237_fsm_236 assign process. --
ap_sig_cseq_ST_st237_fsm_236_assign_proc : process(ap_sig_bdd_2102)
begin
if (ap_sig_bdd_2102) then
ap_sig_cseq_ST_st237_fsm_236 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st237_fsm_236 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st238_fsm_237 assign process. --
ap_sig_cseq_ST_st238_fsm_237_assign_proc : process(ap_sig_bdd_2246)
begin
if (ap_sig_bdd_2246) then
ap_sig_cseq_ST_st238_fsm_237 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st238_fsm_237 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st239_fsm_238 assign process. --
ap_sig_cseq_ST_st239_fsm_238_assign_proc : process(ap_sig_bdd_2390)
begin
if (ap_sig_bdd_2390) then
ap_sig_cseq_ST_st239_fsm_238 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st239_fsm_238 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_2965)
begin
if (ap_sig_bdd_2965) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st240_fsm_239 assign process. --
ap_sig_cseq_ST_st240_fsm_239_assign_proc : process(ap_sig_bdd_3537)
begin
if (ap_sig_bdd_3537) then
ap_sig_cseq_ST_st240_fsm_239 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st240_fsm_239 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st241_fsm_240 assign process. --
ap_sig_cseq_ST_st241_fsm_240_assign_proc : process(ap_sig_bdd_518)
begin
if (ap_sig_bdd_518) then
ap_sig_cseq_ST_st241_fsm_240 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st241_fsm_240 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st242_fsm_241 assign process. --
ap_sig_cseq_ST_st242_fsm_241_assign_proc : process(ap_sig_bdd_671)
begin
if (ap_sig_bdd_671) then
ap_sig_cseq_ST_st242_fsm_241 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st242_fsm_241 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st243_fsm_242 assign process. --
ap_sig_cseq_ST_st243_fsm_242_assign_proc : process(ap_sig_bdd_815)
begin
if (ap_sig_bdd_815) then
ap_sig_cseq_ST_st243_fsm_242 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st243_fsm_242 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st244_fsm_243 assign process. --
ap_sig_cseq_ST_st244_fsm_243_assign_proc : process(ap_sig_bdd_959)
begin
if (ap_sig_bdd_959) then
ap_sig_cseq_ST_st244_fsm_243 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st244_fsm_243 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st245_fsm_244 assign process. --
ap_sig_cseq_ST_st245_fsm_244_assign_proc : process(ap_sig_bdd_1103)
begin
if (ap_sig_bdd_1103) then
ap_sig_cseq_ST_st245_fsm_244 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st245_fsm_244 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st246_fsm_245 assign process. --
ap_sig_cseq_ST_st246_fsm_245_assign_proc : process(ap_sig_bdd_1247)
begin
if (ap_sig_bdd_1247) then
ap_sig_cseq_ST_st246_fsm_245 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st246_fsm_245 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st247_fsm_246 assign process. --
ap_sig_cseq_ST_st247_fsm_246_assign_proc : process(ap_sig_bdd_1391)
begin
if (ap_sig_bdd_1391) then
ap_sig_cseq_ST_st247_fsm_246 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st247_fsm_246 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st248_fsm_247 assign process. --
ap_sig_cseq_ST_st248_fsm_247_assign_proc : process(ap_sig_bdd_1535)
begin
if (ap_sig_bdd_1535) then
ap_sig_cseq_ST_st248_fsm_247 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st248_fsm_247 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st249_fsm_248 assign process. --
ap_sig_cseq_ST_st249_fsm_248_assign_proc : process(ap_sig_bdd_1679)
begin
if (ap_sig_bdd_1679) then
ap_sig_cseq_ST_st249_fsm_248 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st249_fsm_248 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_2974)
begin
if (ap_sig_bdd_2974) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st250_fsm_249 assign process. --
ap_sig_cseq_ST_st250_fsm_249_assign_proc : process(ap_sig_bdd_1823)
begin
if (ap_sig_bdd_1823) then
ap_sig_cseq_ST_st250_fsm_249 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st250_fsm_249 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st251_fsm_250 assign process. --
ap_sig_cseq_ST_st251_fsm_250_assign_proc : process(ap_sig_bdd_1967)
begin
if (ap_sig_bdd_1967) then
ap_sig_cseq_ST_st251_fsm_250 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st251_fsm_250 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st252_fsm_251 assign process. --
ap_sig_cseq_ST_st252_fsm_251_assign_proc : process(ap_sig_bdd_2111)
begin
if (ap_sig_bdd_2111) then
ap_sig_cseq_ST_st252_fsm_251 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st252_fsm_251 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st253_fsm_252 assign process. --
ap_sig_cseq_ST_st253_fsm_252_assign_proc : process(ap_sig_bdd_2255)
begin
if (ap_sig_bdd_2255) then
ap_sig_cseq_ST_st253_fsm_252 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st253_fsm_252 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st254_fsm_253 assign process. --
ap_sig_cseq_ST_st254_fsm_253_assign_proc : process(ap_sig_bdd_2399)
begin
if (ap_sig_bdd_2399) then
ap_sig_cseq_ST_st254_fsm_253 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st254_fsm_253 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st255_fsm_254 assign process. --
ap_sig_cseq_ST_st255_fsm_254_assign_proc : process(ap_sig_bdd_5023)
begin
if (ap_sig_bdd_5023) then
ap_sig_cseq_ST_st255_fsm_254 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st255_fsm_254 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st256_fsm_255 assign process. --
ap_sig_cseq_ST_st256_fsm_255_assign_proc : process(ap_sig_bdd_527)
begin
if (ap_sig_bdd_527) then
ap_sig_cseq_ST_st256_fsm_255 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st256_fsm_255 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st257_fsm_256 assign process. --
ap_sig_cseq_ST_st257_fsm_256_assign_proc : process(ap_sig_bdd_680)
begin
if (ap_sig_bdd_680) then
ap_sig_cseq_ST_st257_fsm_256 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st257_fsm_256 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st258_fsm_257 assign process. --
ap_sig_cseq_ST_st258_fsm_257_assign_proc : process(ap_sig_bdd_824)
begin
if (ap_sig_bdd_824) then
ap_sig_cseq_ST_st258_fsm_257 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st258_fsm_257 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st259_fsm_258 assign process. --
ap_sig_cseq_ST_st259_fsm_258_assign_proc : process(ap_sig_bdd_968)
begin
if (ap_sig_bdd_968) then
ap_sig_cseq_ST_st259_fsm_258 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st259_fsm_258 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_2983)
begin
if (ap_sig_bdd_2983) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st260_fsm_259 assign process. --
ap_sig_cseq_ST_st260_fsm_259_assign_proc : process(ap_sig_bdd_1112)
begin
if (ap_sig_bdd_1112) then
ap_sig_cseq_ST_st260_fsm_259 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st260_fsm_259 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st261_fsm_260 assign process. --
ap_sig_cseq_ST_st261_fsm_260_assign_proc : process(ap_sig_bdd_1256)
begin
if (ap_sig_bdd_1256) then
ap_sig_cseq_ST_st261_fsm_260 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st261_fsm_260 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st262_fsm_261 assign process. --
ap_sig_cseq_ST_st262_fsm_261_assign_proc : process(ap_sig_bdd_1400)
begin
if (ap_sig_bdd_1400) then
ap_sig_cseq_ST_st262_fsm_261 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st262_fsm_261 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st263_fsm_262 assign process. --
ap_sig_cseq_ST_st263_fsm_262_assign_proc : process(ap_sig_bdd_1544)
begin
if (ap_sig_bdd_1544) then
ap_sig_cseq_ST_st263_fsm_262 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st263_fsm_262 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st264_fsm_263 assign process. --
ap_sig_cseq_ST_st264_fsm_263_assign_proc : process(ap_sig_bdd_1688)
begin
if (ap_sig_bdd_1688) then
ap_sig_cseq_ST_st264_fsm_263 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st264_fsm_263 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st265_fsm_264 assign process. --
ap_sig_cseq_ST_st265_fsm_264_assign_proc : process(ap_sig_bdd_1832)
begin
if (ap_sig_bdd_1832) then
ap_sig_cseq_ST_st265_fsm_264 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st265_fsm_264 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st266_fsm_265 assign process. --
ap_sig_cseq_ST_st266_fsm_265_assign_proc : process(ap_sig_bdd_1976)
begin
if (ap_sig_bdd_1976) then
ap_sig_cseq_ST_st266_fsm_265 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st266_fsm_265 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st267_fsm_266 assign process. --
ap_sig_cseq_ST_st267_fsm_266_assign_proc : process(ap_sig_bdd_2120)
begin
if (ap_sig_bdd_2120) then
ap_sig_cseq_ST_st267_fsm_266 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st267_fsm_266 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st268_fsm_267 assign process. --
ap_sig_cseq_ST_st268_fsm_267_assign_proc : process(ap_sig_bdd_2264)
begin
if (ap_sig_bdd_2264) then
ap_sig_cseq_ST_st268_fsm_267 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st268_fsm_267 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st269_fsm_268 assign process. --
ap_sig_cseq_ST_st269_fsm_268_assign_proc : process(ap_sig_bdd_2408)
begin
if (ap_sig_bdd_2408) then
ap_sig_cseq_ST_st269_fsm_268 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st269_fsm_268 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st26_fsm_25 assign process. --
ap_sig_cseq_ST_st26_fsm_25_assign_proc : process(ap_sig_bdd_2992)
begin
if (ap_sig_bdd_2992) then
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st270_fsm_269 assign process. --
ap_sig_cseq_ST_st270_fsm_269_assign_proc : process(ap_sig_bdd_5046)
begin
if (ap_sig_bdd_5046) then
ap_sig_cseq_ST_st270_fsm_269 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st270_fsm_269 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st271_fsm_270 assign process. --
ap_sig_cseq_ST_st271_fsm_270_assign_proc : process(ap_sig_bdd_536)
begin
if (ap_sig_bdd_536) then
ap_sig_cseq_ST_st271_fsm_270 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st271_fsm_270 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st272_fsm_271 assign process. --
ap_sig_cseq_ST_st272_fsm_271_assign_proc : process(ap_sig_bdd_689)
begin
if (ap_sig_bdd_689) then
ap_sig_cseq_ST_st272_fsm_271 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st272_fsm_271 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st273_fsm_272 assign process. --
ap_sig_cseq_ST_st273_fsm_272_assign_proc : process(ap_sig_bdd_833)
begin
if (ap_sig_bdd_833) then
ap_sig_cseq_ST_st273_fsm_272 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st273_fsm_272 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st274_fsm_273 assign process. --
ap_sig_cseq_ST_st274_fsm_273_assign_proc : process(ap_sig_bdd_977)
begin
if (ap_sig_bdd_977) then
ap_sig_cseq_ST_st274_fsm_273 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st274_fsm_273 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st275_fsm_274 assign process. --
ap_sig_cseq_ST_st275_fsm_274_assign_proc : process(ap_sig_bdd_1121)
begin
if (ap_sig_bdd_1121) then
ap_sig_cseq_ST_st275_fsm_274 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st275_fsm_274 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st276_fsm_275 assign process. --
ap_sig_cseq_ST_st276_fsm_275_assign_proc : process(ap_sig_bdd_1265)
begin
if (ap_sig_bdd_1265) then
ap_sig_cseq_ST_st276_fsm_275 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st276_fsm_275 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st277_fsm_276 assign process. --
ap_sig_cseq_ST_st277_fsm_276_assign_proc : process(ap_sig_bdd_1409)
begin
if (ap_sig_bdd_1409) then
ap_sig_cseq_ST_st277_fsm_276 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st277_fsm_276 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st278_fsm_277 assign process. --
ap_sig_cseq_ST_st278_fsm_277_assign_proc : process(ap_sig_bdd_1553)
begin
if (ap_sig_bdd_1553) then
ap_sig_cseq_ST_st278_fsm_277 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st278_fsm_277 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st279_fsm_278 assign process. --
ap_sig_cseq_ST_st279_fsm_278_assign_proc : process(ap_sig_bdd_1697)
begin
if (ap_sig_bdd_1697) then
ap_sig_cseq_ST_st279_fsm_278 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st279_fsm_278 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st27_fsm_26 assign process. --
ap_sig_cseq_ST_st27_fsm_26_assign_proc : process(ap_sig_bdd_3001)
begin
if (ap_sig_bdd_3001) then
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st280_fsm_279 assign process. --
ap_sig_cseq_ST_st280_fsm_279_assign_proc : process(ap_sig_bdd_1841)
begin
if (ap_sig_bdd_1841) then
ap_sig_cseq_ST_st280_fsm_279 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st280_fsm_279 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st281_fsm_280 assign process. --
ap_sig_cseq_ST_st281_fsm_280_assign_proc : process(ap_sig_bdd_1985)
begin
if (ap_sig_bdd_1985) then
ap_sig_cseq_ST_st281_fsm_280 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st281_fsm_280 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st282_fsm_281 assign process. --
ap_sig_cseq_ST_st282_fsm_281_assign_proc : process(ap_sig_bdd_2129)
begin
if (ap_sig_bdd_2129) then
ap_sig_cseq_ST_st282_fsm_281 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st282_fsm_281 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st283_fsm_282 assign process. --
ap_sig_cseq_ST_st283_fsm_282_assign_proc : process(ap_sig_bdd_2273)
begin
if (ap_sig_bdd_2273) then
ap_sig_cseq_ST_st283_fsm_282 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st283_fsm_282 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st284_fsm_283 assign process. --
ap_sig_cseq_ST_st284_fsm_283_assign_proc : process(ap_sig_bdd_2417)
begin
if (ap_sig_bdd_2417) then
ap_sig_cseq_ST_st284_fsm_283 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st284_fsm_283 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st285_fsm_284 assign process. --
ap_sig_cseq_ST_st285_fsm_284_assign_proc : process(ap_sig_bdd_5069)
begin
if (ap_sig_bdd_5069) then
ap_sig_cseq_ST_st285_fsm_284 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st285_fsm_284 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st286_fsm_285 assign process. --
ap_sig_cseq_ST_st286_fsm_285_assign_proc : process(ap_sig_bdd_545)
begin
if (ap_sig_bdd_545) then
ap_sig_cseq_ST_st286_fsm_285 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st286_fsm_285 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st287_fsm_286 assign process. --
ap_sig_cseq_ST_st287_fsm_286_assign_proc : process(ap_sig_bdd_698)
begin
if (ap_sig_bdd_698) then
ap_sig_cseq_ST_st287_fsm_286 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st287_fsm_286 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st288_fsm_287 assign process. --
ap_sig_cseq_ST_st288_fsm_287_assign_proc : process(ap_sig_bdd_842)
begin
if (ap_sig_bdd_842) then
ap_sig_cseq_ST_st288_fsm_287 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st288_fsm_287 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st289_fsm_288 assign process. --
ap_sig_cseq_ST_st289_fsm_288_assign_proc : process(ap_sig_bdd_986)
begin
if (ap_sig_bdd_986) then
ap_sig_cseq_ST_st289_fsm_288 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st289_fsm_288 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st28_fsm_27 assign process. --
ap_sig_cseq_ST_st28_fsm_27_assign_proc : process(ap_sig_bdd_3010)
begin
if (ap_sig_bdd_3010) then
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st290_fsm_289 assign process. --
ap_sig_cseq_ST_st290_fsm_289_assign_proc : process(ap_sig_bdd_1130)
begin
if (ap_sig_bdd_1130) then
ap_sig_cseq_ST_st290_fsm_289 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st290_fsm_289 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st291_fsm_290 assign process. --
ap_sig_cseq_ST_st291_fsm_290_assign_proc : process(ap_sig_bdd_1274)
begin
if (ap_sig_bdd_1274) then
ap_sig_cseq_ST_st291_fsm_290 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st291_fsm_290 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st292_fsm_291 assign process. --
ap_sig_cseq_ST_st292_fsm_291_assign_proc : process(ap_sig_bdd_1418)
begin
if (ap_sig_bdd_1418) then
ap_sig_cseq_ST_st292_fsm_291 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st292_fsm_291 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st293_fsm_292 assign process. --
ap_sig_cseq_ST_st293_fsm_292_assign_proc : process(ap_sig_bdd_1562)
begin
if (ap_sig_bdd_1562) then
ap_sig_cseq_ST_st293_fsm_292 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st293_fsm_292 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st294_fsm_293 assign process. --
ap_sig_cseq_ST_st294_fsm_293_assign_proc : process(ap_sig_bdd_1706)
begin
if (ap_sig_bdd_1706) then
ap_sig_cseq_ST_st294_fsm_293 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st294_fsm_293 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st295_fsm_294 assign process. --
ap_sig_cseq_ST_st295_fsm_294_assign_proc : process(ap_sig_bdd_1850)
begin
if (ap_sig_bdd_1850) then
ap_sig_cseq_ST_st295_fsm_294 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st295_fsm_294 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st296_fsm_295 assign process. --
ap_sig_cseq_ST_st296_fsm_295_assign_proc : process(ap_sig_bdd_1994)
begin
if (ap_sig_bdd_1994) then
ap_sig_cseq_ST_st296_fsm_295 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st296_fsm_295 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st297_fsm_296 assign process. --
ap_sig_cseq_ST_st297_fsm_296_assign_proc : process(ap_sig_bdd_2138)
begin
if (ap_sig_bdd_2138) then
ap_sig_cseq_ST_st297_fsm_296 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st297_fsm_296 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st298_fsm_297 assign process. --
ap_sig_cseq_ST_st298_fsm_297_assign_proc : process(ap_sig_bdd_2282)
begin
if (ap_sig_bdd_2282) then
ap_sig_cseq_ST_st298_fsm_297 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st298_fsm_297 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st299_fsm_298 assign process. --
ap_sig_cseq_ST_st299_fsm_298_assign_proc : process(ap_sig_bdd_2426)
begin
if (ap_sig_bdd_2426) then
ap_sig_cseq_ST_st299_fsm_298 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st299_fsm_298 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_3019)
begin
if (ap_sig_bdd_3019) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_555)
begin
if (ap_sig_bdd_555) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st300_fsm_299 assign process. --
ap_sig_cseq_ST_st300_fsm_299_assign_proc : process(ap_sig_bdd_3547)
begin
if (ap_sig_bdd_3547) then
ap_sig_cseq_ST_st300_fsm_299 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st300_fsm_299 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_3028)
begin
if (ap_sig_bdd_3028) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st31_fsm_30 assign process. --
ap_sig_cseq_ST_st31_fsm_30_assign_proc : process(ap_sig_bdd_3037)
begin
if (ap_sig_bdd_3037) then
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st32_fsm_31 assign process. --
ap_sig_cseq_ST_st32_fsm_31_assign_proc : process(ap_sig_bdd_3046)
begin
if (ap_sig_bdd_3046) then
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st33_fsm_32 assign process. --
ap_sig_cseq_ST_st33_fsm_32_assign_proc : process(ap_sig_bdd_3055)
begin
if (ap_sig_bdd_3055) then
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st34_fsm_33 assign process. --
ap_sig_cseq_ST_st34_fsm_33_assign_proc : process(ap_sig_bdd_3064)
begin
if (ap_sig_bdd_3064) then
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st35_fsm_34 assign process. --
ap_sig_cseq_ST_st35_fsm_34_assign_proc : process(ap_sig_bdd_3073)
begin
if (ap_sig_bdd_3073) then
ap_sig_cseq_ST_st35_fsm_34 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st35_fsm_34 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st36_fsm_35 assign process. --
ap_sig_cseq_ST_st36_fsm_35_assign_proc : process(ap_sig_bdd_3082)
begin
if (ap_sig_bdd_3082) then
ap_sig_cseq_ST_st36_fsm_35 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st36_fsm_35 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st37_fsm_36 assign process. --
ap_sig_cseq_ST_st37_fsm_36_assign_proc : process(ap_sig_bdd_3091)
begin
if (ap_sig_bdd_3091) then
ap_sig_cseq_ST_st37_fsm_36 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st37_fsm_36 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st385_fsm_301 assign process. --
ap_sig_cseq_ST_st385_fsm_301_assign_proc : process(ap_sig_bdd_5902)
begin
if (ap_sig_bdd_5902) then
ap_sig_cseq_ST_st385_fsm_301 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st385_fsm_301 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st386_fsm_302 assign process. --
ap_sig_cseq_ST_st386_fsm_302_assign_proc : process(ap_sig_bdd_2708)
begin
if (ap_sig_bdd_2708) then
ap_sig_cseq_ST_st386_fsm_302 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st386_fsm_302 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st387_fsm_303 assign process. --
ap_sig_cseq_ST_st387_fsm_303_assign_proc : process(ap_sig_bdd_5096)
begin
if (ap_sig_bdd_5096) then
ap_sig_cseq_ST_st387_fsm_303 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st387_fsm_303 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st388_fsm_304 assign process. --
ap_sig_cseq_ST_st388_fsm_304_assign_proc : process(ap_sig_bdd_5104)
begin
if (ap_sig_bdd_5104) then
ap_sig_cseq_ST_st388_fsm_304 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st388_fsm_304 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st389_fsm_305 assign process. --
ap_sig_cseq_ST_st389_fsm_305_assign_proc : process(ap_sig_bdd_2719)
begin
if (ap_sig_bdd_2719) then
ap_sig_cseq_ST_st389_fsm_305 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st389_fsm_305 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st38_fsm_37 assign process. --
ap_sig_cseq_ST_st38_fsm_37_assign_proc : process(ap_sig_bdd_3100)
begin
if (ap_sig_bdd_3100) then
ap_sig_cseq_ST_st38_fsm_37 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st38_fsm_37 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st390_fsm_306 assign process. --
ap_sig_cseq_ST_st390_fsm_306_assign_proc : process(ap_sig_bdd_5113)
begin
if (ap_sig_bdd_5113) then
ap_sig_cseq_ST_st390_fsm_306 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st390_fsm_306 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st391_fsm_307 assign process. --
ap_sig_cseq_ST_st391_fsm_307_assign_proc : process(ap_sig_bdd_5121)
begin
if (ap_sig_bdd_5121) then
ap_sig_cseq_ST_st391_fsm_307 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st391_fsm_307 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st392_fsm_308 assign process. --
ap_sig_cseq_ST_st392_fsm_308_assign_proc : process(ap_sig_bdd_2728)
begin
if (ap_sig_bdd_2728) then
ap_sig_cseq_ST_st392_fsm_308 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st392_fsm_308 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st393_fsm_309 assign process. --
ap_sig_cseq_ST_st393_fsm_309_assign_proc : process(ap_sig_bdd_5130)
begin
if (ap_sig_bdd_5130) then
ap_sig_cseq_ST_st393_fsm_309 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st393_fsm_309 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st394_fsm_310 assign process. --
ap_sig_cseq_ST_st394_fsm_310_assign_proc : process(ap_sig_bdd_5138)
begin
if (ap_sig_bdd_5138) then
ap_sig_cseq_ST_st394_fsm_310 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st394_fsm_310 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st395_fsm_311 assign process. --
ap_sig_cseq_ST_st395_fsm_311_assign_proc : process(ap_sig_bdd_2737)
begin
if (ap_sig_bdd_2737) then
ap_sig_cseq_ST_st395_fsm_311 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st395_fsm_311 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st396_fsm_312 assign process. --
ap_sig_cseq_ST_st396_fsm_312_assign_proc : process(ap_sig_bdd_5147)
begin
if (ap_sig_bdd_5147) then
ap_sig_cseq_ST_st396_fsm_312 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st396_fsm_312 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st397_fsm_313 assign process. --
ap_sig_cseq_ST_st397_fsm_313_assign_proc : process(ap_sig_bdd_5155)
begin
if (ap_sig_bdd_5155) then
ap_sig_cseq_ST_st397_fsm_313 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st397_fsm_313 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st398_fsm_314 assign process. --
ap_sig_cseq_ST_st398_fsm_314_assign_proc : process(ap_sig_bdd_2746)
begin
if (ap_sig_bdd_2746) then
ap_sig_cseq_ST_st398_fsm_314 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st398_fsm_314 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st399_fsm_315 assign process. --
ap_sig_cseq_ST_st399_fsm_315_assign_proc : process(ap_sig_bdd_5164)
begin
if (ap_sig_bdd_5164) then
ap_sig_cseq_ST_st399_fsm_315 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st399_fsm_315 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_38 assign process. --
ap_sig_cseq_ST_st39_fsm_38_assign_proc : process(ap_sig_bdd_3109)
begin
if (ap_sig_bdd_3109) then
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_708)
begin
if (ap_sig_bdd_708) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st400_fsm_316 assign process. --
ap_sig_cseq_ST_st400_fsm_316_assign_proc : process(ap_sig_bdd_5172)
begin
if (ap_sig_bdd_5172) then
ap_sig_cseq_ST_st400_fsm_316 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st400_fsm_316 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st401_fsm_317 assign process. --
ap_sig_cseq_ST_st401_fsm_317_assign_proc : process(ap_sig_bdd_2755)
begin
if (ap_sig_bdd_2755) then
ap_sig_cseq_ST_st401_fsm_317 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st401_fsm_317 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st402_fsm_318 assign process. --
ap_sig_cseq_ST_st402_fsm_318_assign_proc : process(ap_sig_bdd_5181)
begin
if (ap_sig_bdd_5181) then
ap_sig_cseq_ST_st402_fsm_318 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st402_fsm_318 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st403_fsm_319 assign process. --
ap_sig_cseq_ST_st403_fsm_319_assign_proc : process(ap_sig_bdd_5189)
begin
if (ap_sig_bdd_5189) then
ap_sig_cseq_ST_st403_fsm_319 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st403_fsm_319 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st404_fsm_320 assign process. --
ap_sig_cseq_ST_st404_fsm_320_assign_proc : process(ap_sig_bdd_2764)
begin
if (ap_sig_bdd_2764) then
ap_sig_cseq_ST_st404_fsm_320 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st404_fsm_320 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st405_fsm_321 assign process. --
ap_sig_cseq_ST_st405_fsm_321_assign_proc : process(ap_sig_bdd_5198)
begin
if (ap_sig_bdd_5198) then
ap_sig_cseq_ST_st405_fsm_321 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st405_fsm_321 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st406_fsm_322 assign process. --
ap_sig_cseq_ST_st406_fsm_322_assign_proc : process(ap_sig_bdd_5206)
begin
if (ap_sig_bdd_5206) then
ap_sig_cseq_ST_st406_fsm_322 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st406_fsm_322 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st407_fsm_323 assign process. --
ap_sig_cseq_ST_st407_fsm_323_assign_proc : process(ap_sig_bdd_2773)
begin
if (ap_sig_bdd_2773) then
ap_sig_cseq_ST_st407_fsm_323 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st407_fsm_323 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st408_fsm_324 assign process. --
ap_sig_cseq_ST_st408_fsm_324_assign_proc : process(ap_sig_bdd_5215)
begin
if (ap_sig_bdd_5215) then
ap_sig_cseq_ST_st408_fsm_324 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st408_fsm_324 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st409_fsm_325 assign process. --
ap_sig_cseq_ST_st409_fsm_325_assign_proc : process(ap_sig_bdd_5223)
begin
if (ap_sig_bdd_5223) then
ap_sig_cseq_ST_st409_fsm_325 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st409_fsm_325 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st40_fsm_39 assign process. --
ap_sig_cseq_ST_st40_fsm_39_assign_proc : process(ap_sig_bdd_3118)
begin
if (ap_sig_bdd_3118) then
ap_sig_cseq_ST_st40_fsm_39 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st40_fsm_39 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st410_fsm_326 assign process. --
ap_sig_cseq_ST_st410_fsm_326_assign_proc : process(ap_sig_bdd_2782)
begin
if (ap_sig_bdd_2782) then
ap_sig_cseq_ST_st410_fsm_326 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st410_fsm_326 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st411_fsm_327 assign process. --
ap_sig_cseq_ST_st411_fsm_327_assign_proc : process(ap_sig_bdd_5232)
begin
if (ap_sig_bdd_5232) then
ap_sig_cseq_ST_st411_fsm_327 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st411_fsm_327 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st412_fsm_328 assign process. --
ap_sig_cseq_ST_st412_fsm_328_assign_proc : process(ap_sig_bdd_5240)
begin
if (ap_sig_bdd_5240) then
ap_sig_cseq_ST_st412_fsm_328 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st412_fsm_328 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st413_fsm_329 assign process. --
ap_sig_cseq_ST_st413_fsm_329_assign_proc : process(ap_sig_bdd_2791)
begin
if (ap_sig_bdd_2791) then
ap_sig_cseq_ST_st413_fsm_329 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st413_fsm_329 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st414_fsm_330 assign process. --
ap_sig_cseq_ST_st414_fsm_330_assign_proc : process(ap_sig_bdd_5249)
begin
if (ap_sig_bdd_5249) then
ap_sig_cseq_ST_st414_fsm_330 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st414_fsm_330 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st415_fsm_331 assign process. --
ap_sig_cseq_ST_st415_fsm_331_assign_proc : process(ap_sig_bdd_5257)
begin
if (ap_sig_bdd_5257) then
ap_sig_cseq_ST_st415_fsm_331 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st415_fsm_331 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st416_fsm_332 assign process. --
ap_sig_cseq_ST_st416_fsm_332_assign_proc : process(ap_sig_bdd_2800)
begin
if (ap_sig_bdd_2800) then
ap_sig_cseq_ST_st416_fsm_332 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st416_fsm_332 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st417_fsm_333 assign process. --
ap_sig_cseq_ST_st417_fsm_333_assign_proc : process(ap_sig_bdd_5266)
begin
if (ap_sig_bdd_5266) then
ap_sig_cseq_ST_st417_fsm_333 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st417_fsm_333 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st418_fsm_334 assign process. --
ap_sig_cseq_ST_st418_fsm_334_assign_proc : process(ap_sig_bdd_5274)
begin
if (ap_sig_bdd_5274) then
ap_sig_cseq_ST_st418_fsm_334 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st418_fsm_334 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st419_fsm_335 assign process. --
ap_sig_cseq_ST_st419_fsm_335_assign_proc : process(ap_sig_bdd_2809)
begin
if (ap_sig_bdd_2809) then
ap_sig_cseq_ST_st419_fsm_335 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st419_fsm_335 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_3127)
begin
if (ap_sig_bdd_3127) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st420_fsm_336 assign process. --
ap_sig_cseq_ST_st420_fsm_336_assign_proc : process(ap_sig_bdd_5283)
begin
if (ap_sig_bdd_5283) then
ap_sig_cseq_ST_st420_fsm_336 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st420_fsm_336 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st421_fsm_337 assign process. --
ap_sig_cseq_ST_st421_fsm_337_assign_proc : process(ap_sig_bdd_5291)
begin
if (ap_sig_bdd_5291) then
ap_sig_cseq_ST_st421_fsm_337 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st421_fsm_337 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st422_fsm_338 assign process. --
ap_sig_cseq_ST_st422_fsm_338_assign_proc : process(ap_sig_bdd_2818)
begin
if (ap_sig_bdd_2818) then
ap_sig_cseq_ST_st422_fsm_338 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st422_fsm_338 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st423_fsm_339 assign process. --
ap_sig_cseq_ST_st423_fsm_339_assign_proc : process(ap_sig_bdd_5300)
begin
if (ap_sig_bdd_5300) then
ap_sig_cseq_ST_st423_fsm_339 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st423_fsm_339 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st424_fsm_340 assign process. --
ap_sig_cseq_ST_st424_fsm_340_assign_proc : process(ap_sig_bdd_5308)
begin
if (ap_sig_bdd_5308) then
ap_sig_cseq_ST_st424_fsm_340 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st424_fsm_340 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st425_fsm_341 assign process. --
ap_sig_cseq_ST_st425_fsm_341_assign_proc : process(ap_sig_bdd_2827)
begin
if (ap_sig_bdd_2827) then
ap_sig_cseq_ST_st425_fsm_341 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st425_fsm_341 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st426_fsm_342 assign process. --
ap_sig_cseq_ST_st426_fsm_342_assign_proc : process(ap_sig_bdd_5317)
begin
if (ap_sig_bdd_5317) then
ap_sig_cseq_ST_st426_fsm_342 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st426_fsm_342 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st427_fsm_343 assign process. --
ap_sig_cseq_ST_st427_fsm_343_assign_proc : process(ap_sig_bdd_5325)
begin
if (ap_sig_bdd_5325) then
ap_sig_cseq_ST_st427_fsm_343 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st427_fsm_343 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st428_fsm_344 assign process. --
ap_sig_cseq_ST_st428_fsm_344_assign_proc : process(ap_sig_bdd_2836)
begin
if (ap_sig_bdd_2836) then
ap_sig_cseq_ST_st428_fsm_344 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st428_fsm_344 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st429_fsm_345 assign process. --
ap_sig_cseq_ST_st429_fsm_345_assign_proc : process(ap_sig_bdd_5334)
begin
if (ap_sig_bdd_5334) then
ap_sig_cseq_ST_st429_fsm_345 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st429_fsm_345 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st42_fsm_41 assign process. --
ap_sig_cseq_ST_st42_fsm_41_assign_proc : process(ap_sig_bdd_3136)
begin
if (ap_sig_bdd_3136) then
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st430_fsm_346 assign process. --
ap_sig_cseq_ST_st430_fsm_346_assign_proc : process(ap_sig_bdd_5342)
begin
if (ap_sig_bdd_5342) then
ap_sig_cseq_ST_st430_fsm_346 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st430_fsm_346 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st431_fsm_347 assign process. --
ap_sig_cseq_ST_st431_fsm_347_assign_proc : process(ap_sig_bdd_2845)
begin
if (ap_sig_bdd_2845) then
ap_sig_cseq_ST_st431_fsm_347 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st431_fsm_347 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st432_fsm_348 assign process. --
ap_sig_cseq_ST_st432_fsm_348_assign_proc : process(ap_sig_bdd_5351)
begin
if (ap_sig_bdd_5351) then
ap_sig_cseq_ST_st432_fsm_348 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st432_fsm_348 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st433_fsm_349 assign process. --
ap_sig_cseq_ST_st433_fsm_349_assign_proc : process(ap_sig_bdd_5359)
begin
if (ap_sig_bdd_5359) then
ap_sig_cseq_ST_st433_fsm_349 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st433_fsm_349 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st434_fsm_350 assign process. --
ap_sig_cseq_ST_st434_fsm_350_assign_proc : process(ap_sig_bdd_2854)
begin
if (ap_sig_bdd_2854) then
ap_sig_cseq_ST_st434_fsm_350 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st434_fsm_350 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st435_fsm_351 assign process. --
ap_sig_cseq_ST_st435_fsm_351_assign_proc : process(ap_sig_bdd_5368)
begin
if (ap_sig_bdd_5368) then
ap_sig_cseq_ST_st435_fsm_351 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st435_fsm_351 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st436_fsm_352 assign process. --
ap_sig_cseq_ST_st436_fsm_352_assign_proc : process(ap_sig_bdd_5376)
begin
if (ap_sig_bdd_5376) then
ap_sig_cseq_ST_st436_fsm_352 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st436_fsm_352 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st437_fsm_353 assign process. --
ap_sig_cseq_ST_st437_fsm_353_assign_proc : process(ap_sig_bdd_2863)
begin
if (ap_sig_bdd_2863) then
ap_sig_cseq_ST_st437_fsm_353 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st437_fsm_353 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st438_fsm_354 assign process. --
ap_sig_cseq_ST_st438_fsm_354_assign_proc : process(ap_sig_bdd_5385)
begin
if (ap_sig_bdd_5385) then
ap_sig_cseq_ST_st438_fsm_354 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st438_fsm_354 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st439_fsm_355 assign process. --
ap_sig_cseq_ST_st439_fsm_355_assign_proc : process(ap_sig_bdd_5393)
begin
if (ap_sig_bdd_5393) then
ap_sig_cseq_ST_st439_fsm_355 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st439_fsm_355 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st43_fsm_42 assign process. --
ap_sig_cseq_ST_st43_fsm_42_assign_proc : process(ap_sig_bdd_3145)
begin
if (ap_sig_bdd_3145) then
ap_sig_cseq_ST_st43_fsm_42 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st43_fsm_42 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st440_fsm_356 assign process. --
ap_sig_cseq_ST_st440_fsm_356_assign_proc : process(ap_sig_bdd_2872)
begin
if (ap_sig_bdd_2872) then
ap_sig_cseq_ST_st440_fsm_356 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st440_fsm_356 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st441_fsm_357 assign process. --
ap_sig_cseq_ST_st441_fsm_357_assign_proc : process(ap_sig_bdd_5402)
begin
if (ap_sig_bdd_5402) then
ap_sig_cseq_ST_st441_fsm_357 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st441_fsm_357 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st442_fsm_358 assign process. --
ap_sig_cseq_ST_st442_fsm_358_assign_proc : process(ap_sig_bdd_5410)
begin
if (ap_sig_bdd_5410) then
ap_sig_cseq_ST_st442_fsm_358 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st442_fsm_358 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st443_fsm_359 assign process. --
ap_sig_cseq_ST_st443_fsm_359_assign_proc : process(ap_sig_bdd_2881)
begin
if (ap_sig_bdd_2881) then
ap_sig_cseq_ST_st443_fsm_359 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st443_fsm_359 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st444_fsm_360 assign process. --
ap_sig_cseq_ST_st444_fsm_360_assign_proc : process(ap_sig_bdd_5419)
begin
if (ap_sig_bdd_5419) then
ap_sig_cseq_ST_st444_fsm_360 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st444_fsm_360 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st445_fsm_361 assign process. --
ap_sig_cseq_ST_st445_fsm_361_assign_proc : process(ap_sig_bdd_5427)
begin
if (ap_sig_bdd_5427) then
ap_sig_cseq_ST_st445_fsm_361 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st445_fsm_361 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st44_fsm_43 assign process. --
ap_sig_cseq_ST_st44_fsm_43_assign_proc : process(ap_sig_bdd_3154)
begin
if (ap_sig_bdd_3154) then
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st45_fsm_44 assign process. --
ap_sig_cseq_ST_st45_fsm_44_assign_proc : process(ap_sig_bdd_3163)
begin
if (ap_sig_bdd_3163) then
ap_sig_cseq_ST_st45_fsm_44 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st45_fsm_44 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_3172)
begin
if (ap_sig_bdd_3172) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st47_fsm_46 assign process. --
ap_sig_cseq_ST_st47_fsm_46_assign_proc : process(ap_sig_bdd_3181)
begin
if (ap_sig_bdd_3181) then
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st48_fsm_47 assign process. --
ap_sig_cseq_ST_st48_fsm_47_assign_proc : process(ap_sig_bdd_3190)
begin
if (ap_sig_bdd_3190) then
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st49_fsm_48 assign process. --
ap_sig_cseq_ST_st49_fsm_48_assign_proc : process(ap_sig_bdd_3199)
begin
if (ap_sig_bdd_3199) then
ap_sig_cseq_ST_st49_fsm_48 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st49_fsm_48 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_852)
begin
if (ap_sig_bdd_852) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st50_fsm_49 assign process. --
ap_sig_cseq_ST_st50_fsm_49_assign_proc : process(ap_sig_bdd_3208)
begin
if (ap_sig_bdd_3208) then
ap_sig_cseq_ST_st50_fsm_49 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st50_fsm_49 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st51_fsm_50 assign process. --
ap_sig_cseq_ST_st51_fsm_50_assign_proc : process(ap_sig_bdd_3217)
begin
if (ap_sig_bdd_3217) then
ap_sig_cseq_ST_st51_fsm_50 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st51_fsm_50 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st52_fsm_51 assign process. --
ap_sig_cseq_ST_st52_fsm_51_assign_proc : process(ap_sig_bdd_3226)
begin
if (ap_sig_bdd_3226) then
ap_sig_cseq_ST_st52_fsm_51 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st52_fsm_51 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st53_fsm_52 assign process. --
ap_sig_cseq_ST_st53_fsm_52_assign_proc : process(ap_sig_bdd_3235)
begin
if (ap_sig_bdd_3235) then
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st54_fsm_53 assign process. --
ap_sig_cseq_ST_st54_fsm_53_assign_proc : process(ap_sig_bdd_3244)
begin
if (ap_sig_bdd_3244) then
ap_sig_cseq_ST_st54_fsm_53 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st54_fsm_53 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st55_fsm_54 assign process. --
ap_sig_cseq_ST_st55_fsm_54_assign_proc : process(ap_sig_bdd_3253)
begin
if (ap_sig_bdd_3253) then
ap_sig_cseq_ST_st55_fsm_54 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st55_fsm_54 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st56_fsm_55 assign process. --
ap_sig_cseq_ST_st56_fsm_55_assign_proc : process(ap_sig_bdd_3262)
begin
if (ap_sig_bdd_3262) then
ap_sig_cseq_ST_st56_fsm_55 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st56_fsm_55 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st57_fsm_56 assign process. --
ap_sig_cseq_ST_st57_fsm_56_assign_proc : process(ap_sig_bdd_3271)
begin
if (ap_sig_bdd_3271) then
ap_sig_cseq_ST_st57_fsm_56 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st57_fsm_56 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st58_fsm_57 assign process. --
ap_sig_cseq_ST_st58_fsm_57_assign_proc : process(ap_sig_bdd_3280)
begin
if (ap_sig_bdd_3280) then
ap_sig_cseq_ST_st58_fsm_57 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st58_fsm_57 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st59_fsm_58 assign process. --
ap_sig_cseq_ST_st59_fsm_58_assign_proc : process(ap_sig_bdd_3289)
begin
if (ap_sig_bdd_3289) then
ap_sig_cseq_ST_st59_fsm_58 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st59_fsm_58 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_996)
begin
if (ap_sig_bdd_996) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st60_fsm_59 assign process. --
ap_sig_cseq_ST_st60_fsm_59_assign_proc : process(ap_sig_bdd_3298)
begin
if (ap_sig_bdd_3298) then
ap_sig_cseq_ST_st60_fsm_59 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st60_fsm_59 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st61_fsm_60 assign process. --
ap_sig_cseq_ST_st61_fsm_60_assign_proc : process(ap_sig_bdd_3307)
begin
if (ap_sig_bdd_3307) then
ap_sig_cseq_ST_st61_fsm_60 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st61_fsm_60 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st62_fsm_61 assign process. --
ap_sig_cseq_ST_st62_fsm_61_assign_proc : process(ap_sig_bdd_3316)
begin
if (ap_sig_bdd_3316) then
ap_sig_cseq_ST_st62_fsm_61 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st62_fsm_61 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st63_fsm_62 assign process. --
ap_sig_cseq_ST_st63_fsm_62_assign_proc : process(ap_sig_bdd_3325)
begin
if (ap_sig_bdd_3325) then
ap_sig_cseq_ST_st63_fsm_62 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st63_fsm_62 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st64_fsm_63 assign process. --
ap_sig_cseq_ST_st64_fsm_63_assign_proc : process(ap_sig_bdd_3334)
begin
if (ap_sig_bdd_3334) then
ap_sig_cseq_ST_st64_fsm_63 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st64_fsm_63 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st65_fsm_64 assign process. --
ap_sig_cseq_ST_st65_fsm_64_assign_proc : process(ap_sig_bdd_3343)
begin
if (ap_sig_bdd_3343) then
ap_sig_cseq_ST_st65_fsm_64 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st65_fsm_64 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st66_fsm_65 assign process. --
ap_sig_cseq_ST_st66_fsm_65_assign_proc : process(ap_sig_bdd_3352)
begin
if (ap_sig_bdd_3352) then
ap_sig_cseq_ST_st66_fsm_65 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st66_fsm_65 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st67_fsm_66 assign process. --
ap_sig_cseq_ST_st67_fsm_66_assign_proc : process(ap_sig_bdd_3361)
begin
if (ap_sig_bdd_3361) then
ap_sig_cseq_ST_st67_fsm_66 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st67_fsm_66 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st68_fsm_67 assign process. --
ap_sig_cseq_ST_st68_fsm_67_assign_proc : process(ap_sig_bdd_3370)
begin
if (ap_sig_bdd_3370) then
ap_sig_cseq_ST_st68_fsm_67 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st68_fsm_67 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st69_fsm_68 assign process. --
ap_sig_cseq_ST_st69_fsm_68_assign_proc : process(ap_sig_bdd_3379)
begin
if (ap_sig_bdd_3379) then
ap_sig_cseq_ST_st69_fsm_68 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st69_fsm_68 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_1140)
begin
if (ap_sig_bdd_1140) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st70_fsm_69 assign process. --
ap_sig_cseq_ST_st70_fsm_69_assign_proc : process(ap_sig_bdd_3388)
begin
if (ap_sig_bdd_3388) then
ap_sig_cseq_ST_st70_fsm_69 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st70_fsm_69 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st71_fsm_70 assign process. --
ap_sig_cseq_ST_st71_fsm_70_assign_proc : process(ap_sig_bdd_3397)
begin
if (ap_sig_bdd_3397) then
ap_sig_cseq_ST_st71_fsm_70 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st71_fsm_70 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st72_fsm_71 assign process. --
ap_sig_cseq_ST_st72_fsm_71_assign_proc : process(ap_sig_bdd_2437)
begin
if (ap_sig_bdd_2437) then
ap_sig_cseq_ST_st72_fsm_71 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st72_fsm_71 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st73_fsm_72 assign process. --
ap_sig_cseq_ST_st73_fsm_72_assign_proc : process(ap_sig_bdd_410)
begin
if (ap_sig_bdd_410) then
ap_sig_cseq_ST_st73_fsm_72 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st73_fsm_72 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st74_fsm_73 assign process. --
ap_sig_cseq_ST_st74_fsm_73_assign_proc : process(ap_sig_bdd_563)
begin
if (ap_sig_bdd_563) then
ap_sig_cseq_ST_st74_fsm_73 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st74_fsm_73 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st75_fsm_74 assign process. --
ap_sig_cseq_ST_st75_fsm_74_assign_proc : process(ap_sig_bdd_3417)
begin
if (ap_sig_bdd_3417) then
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st76_fsm_75 assign process. --
ap_sig_cseq_ST_st76_fsm_75_assign_proc : process(ap_sig_bdd_419)
begin
if (ap_sig_bdd_419) then
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_572)
begin
if (ap_sig_bdd_572) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_716)
begin
if (ap_sig_bdd_716) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_860)
begin
if (ap_sig_bdd_860) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_1284)
begin
if (ap_sig_bdd_1284) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_1004)
begin
if (ap_sig_bdd_1004) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_1148)
begin
if (ap_sig_bdd_1148) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_1292)
begin
if (ap_sig_bdd_1292) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_1436)
begin
if (ap_sig_bdd_1436) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_1580)
begin
if (ap_sig_bdd_1580) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st85_fsm_84 assign process. --
ap_sig_cseq_ST_st85_fsm_84_assign_proc : process(ap_sig_bdd_1724)
begin
if (ap_sig_bdd_1724) then
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st86_fsm_85 assign process. --
ap_sig_cseq_ST_st86_fsm_85_assign_proc : process(ap_sig_bdd_1868)
begin
if (ap_sig_bdd_1868) then
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_2012)
begin
if (ap_sig_bdd_2012) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_2156)
begin
if (ap_sig_bdd_2156) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st89_fsm_88 assign process. --
ap_sig_cseq_ST_st89_fsm_88_assign_proc : process(ap_sig_bdd_2300)
begin
if (ap_sig_bdd_2300) then
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_1428)
begin
if (ap_sig_bdd_1428) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st90_fsm_89 assign process. --
ap_sig_cseq_ST_st90_fsm_89_assign_proc : process(ap_sig_bdd_3437)
begin
if (ap_sig_bdd_3437) then
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st91_fsm_90 assign process. --
ap_sig_cseq_ST_st91_fsm_90_assign_proc : process(ap_sig_bdd_428)
begin
if (ap_sig_bdd_428) then
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_581)
begin
if (ap_sig_bdd_581) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_725)
begin
if (ap_sig_bdd_725) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_869)
begin
if (ap_sig_bdd_869) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st95_fsm_94 assign process. --
ap_sig_cseq_ST_st95_fsm_94_assign_proc : process(ap_sig_bdd_1013)
begin
if (ap_sig_bdd_1013) then
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st96_fsm_95 assign process. --
ap_sig_cseq_ST_st96_fsm_95_assign_proc : process(ap_sig_bdd_1157)
begin
if (ap_sig_bdd_1157) then
ap_sig_cseq_ST_st96_fsm_95 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st96_fsm_95 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st97_fsm_96 assign process. --
ap_sig_cseq_ST_st97_fsm_96_assign_proc : process(ap_sig_bdd_1301)
begin
if (ap_sig_bdd_1301) then
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_1445)
begin
if (ap_sig_bdd_1445) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_1589)
begin
if (ap_sig_bdd_1589) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_1572)
begin
if (ap_sig_bdd_1572) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_outs_TREADY assign process. --
ap_sig_ioackin_outs_TREADY_assign_proc : process(outs_TREADY, ap_reg_ioackin_outs_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) then
ap_sig_ioackin_outs_TREADY <= outs_TREADY;
else
ap_sig_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end process;
beta_addr_111281129_part_set_fu_3103_p5 <= (tmp_21_fu_3093_p4 & ap_reg_ppstg_reg_725_pp0_it81(479 downto 0));
beta_load_10_fu_3290_p1 <= reg_733;
beta_load_11_fu_3305_p1 <= reg_733;
beta_load_12_fu_3320_p1 <= reg_733;
beta_load_13_fu_3335_p1 <= reg_733;
beta_load_14_fu_3350_p1 <= reg_733;
beta_load_15_fu_3365_p1 <= reg_733;
beta_load_16_fu_3380_p1 <= reg_733;
beta_load_17_fu_3395_p1 <= reg_733;
beta_load_18_fu_3410_p1 <= reg_733;
beta_load_1_fu_3155_p1 <= reg_733;
beta_load_2_fu_3170_p1 <= reg_733;
beta_load_3_fu_3185_p1 <= reg_733;
beta_load_4_fu_3200_p1 <= reg_733;
beta_load_5_fu_3215_p1 <= reg_733;
beta_load_6_fu_3230_p1 <= reg_733;
beta_load_7_fu_3245_p1 <= reg_733;
beta_load_8_fu_3260_p1 <= reg_733;
beta_load_9_fu_3275_p1 <= reg_733;
beta_load_fu_3125_p1 <= reg_733;
beta_load_s_fu_3140_p1 <= reg_733;
beta_write_assign_toint_fu_3089_p1 <= grp_fu_626_p2;
data_array_addr_10_gep_fu_360_p3 <= ap_const_lv64_A(5 - 1 downto 0);
data_array_addr_11_gep_fu_368_p3 <= ap_const_lv64_B(5 - 1 downto 0);
data_array_addr_12_gep_fu_376_p3 <= ap_const_lv64_C(5 - 1 downto 0);
data_array_addr_13_gep_fu_384_p3 <= ap_const_lv64_D(5 - 1 downto 0);
data_array_addr_14_gep_fu_392_p3 <= ap_const_lv64_E(5 - 1 downto 0);
data_array_addr_15_gep_fu_400_p3 <= ap_const_lv64_F(5 - 1 downto 0);
data_array_addr_16_gep_fu_244_p3 <= ap_const_lv64_10(5 - 1 downto 0);
data_array_addr_17_gep_fu_288_p3 <= ap_const_lv64_11(5 - 1 downto 0);
data_array_addr_18_gep_fu_256_p3 <= ap_const_lv64_12(5 - 1 downto 0);
data_array_addr_19_gep_fu_296_p3 <= ap_const_lv64_13(5 - 1 downto 0);
data_array_addr_1_gep_fu_304_p3 <= ap_const_lv64_1(5 - 1 downto 0);
data_array_addr_2_gep_fu_272_p3 <= ap_const_lv64_2(5 - 1 downto 0);
data_array_addr_3_gep_fu_312_p3 <= ap_const_lv64_3(5 - 1 downto 0);
data_array_addr_4_gep_fu_280_p3 <= ap_const_lv64_4(5 - 1 downto 0);
data_array_addr_5_gep_fu_320_p3 <= ap_const_lv64_5(5 - 1 downto 0);
data_array_addr_6_gep_fu_328_p3 <= ap_const_lv64_6(5 - 1 downto 0);
data_array_addr_7_gep_fu_336_p3 <= ap_const_lv64_7(5 - 1 downto 0);
data_array_addr_8_gep_fu_344_p3 <= ap_const_lv64_8(5 - 1 downto 0);
data_array_addr_9_gep_fu_352_p3 <= ap_const_lv64_9(5 - 1 downto 0);
data_array_addr_gep_fu_264_p3 <= ap_const_lv64_0(5 - 1 downto 0);
-- data_array_address0 assign process. --
data_array_address0_assign_proc : process(ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st72_fsm_71, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg0_fsm_300, ap_sig_cseq_ST_st71_fsm_70, data_array_addr_16_reg_3700, data_array_addr_18_reg_3711, ap_sig_cseq_ST_st75_fsm_74, data_array_addr_17_reg_3737, data_array_addr_19_reg_3748, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, tmp_1_fu_2852_p1, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) then
data_array_address0 <= data_array_addr_19_reg_3748;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)) then
data_array_address0 <= data_array_addr_18_reg_3711;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) then
data_array_address0 <= data_array_addr_17_reg_3737;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) then
data_array_address0 <= data_array_addr_16_reg_3700;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) then
data_array_address0 <= ap_const_lv64_F(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) then
data_array_address0 <= ap_const_lv64_E(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) then
data_array_address0 <= ap_const_lv64_D(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) then
data_array_address0 <= ap_const_lv64_C(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) then
data_array_address0 <= ap_const_lv64_B(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) then
data_array_address0 <= ap_const_lv64_A(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
data_array_address0 <= ap_const_lv64_9(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) then
data_array_address0 <= ap_const_lv64_8(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
data_array_address0 <= ap_const_lv64_7(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) then
data_array_address0 <= ap_const_lv64_6(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) then
data_array_address0 <= ap_const_lv64_5(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) then
data_array_address0 <= ap_const_lv64_3(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
data_array_address0 <= ap_const_lv64_1(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) then
data_array_address0 <= ap_const_lv64_4(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) then
data_array_address0 <= ap_const_lv64_2(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) then
data_array_address0 <= ap_const_lv64_0(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300))) then
data_array_address0 <= tmp_1_fu_2852_p1(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) then
data_array_address0 <= ap_const_lv64_13(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) then
data_array_address0 <= ap_const_lv64_11(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) then
data_array_address0 <= ap_const_lv64_12(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70)) then
data_array_address0 <= ap_const_lv64_10(5 - 1 downto 0);
else
data_array_address0 <= "XXXXX";
end if;
end process;
-- data_array_address1 assign process. --
data_array_address1_assign_proc : process(ap_reg_ppiten_pp0_it83, data_array_addr_16_reg_3700, data_array_addr_18_reg_3711, data_array_addr_reg_3717, data_array_addr_2_reg_3727, data_array_addr_4_reg_3732, data_array_addr_17_reg_3737, data_array_addr_19_reg_3748, data_array_addr_1_reg_3754, data_array_addr_3_reg_3764, data_array_addr_5_reg_3769, data_array_addr_6_reg_3774, data_array_addr_7_reg_3779, data_array_addr_8_reg_3784, data_array_addr_9_reg_3789, data_array_addr_10_reg_3794, data_array_addr_11_reg_3799, data_array_addr_12_reg_3804, data_array_addr_13_reg_3809, data_array_addr_14_reg_3814, data_array_addr_15_reg_3819, ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st385_fsm_301)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it83)) then
data_array_address1 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) then
data_array_address1 <= data_array_addr_19_reg_3748;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) then
data_array_address1 <= data_array_addr_18_reg_3711;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) then
data_array_address1 <= data_array_addr_17_reg_3737;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) then
data_array_address1 <= data_array_addr_16_reg_3700;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) then
data_array_address1 <= data_array_addr_15_reg_3819;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) then
data_array_address1 <= data_array_addr_14_reg_3814;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) then
data_array_address1 <= data_array_addr_13_reg_3809;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) then
data_array_address1 <= data_array_addr_12_reg_3804;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) then
data_array_address1 <= data_array_addr_11_reg_3799;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) then
data_array_address1 <= data_array_addr_10_reg_3794;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) then
data_array_address1 <= data_array_addr_9_reg_3789;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) then
data_array_address1 <= data_array_addr_8_reg_3784;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) then
data_array_address1 <= data_array_addr_7_reg_3779;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) then
data_array_address1 <= data_array_addr_6_reg_3774;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) then
data_array_address1 <= data_array_addr_5_reg_3769;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) then
data_array_address1 <= data_array_addr_4_reg_3732;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) then
data_array_address1 <= data_array_addr_3_reg_3764;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) then
data_array_address1 <= data_array_addr_2_reg_3727;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) then
data_array_address1 <= data_array_addr_1_reg_3754;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st385_fsm_301)) then
data_array_address1 <= data_array_addr_reg_3717;
else
data_array_address1 <= "XXXXX";
end if;
end process;
-- data_array_ce0 assign process. --
data_array_ce0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st72_fsm_71, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg0_fsm_300, ap_sig_cseq_ST_st71_fsm_70, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)))) then
data_array_ce0 <= ap_const_logic_1;
else
data_array_ce0 <= ap_const_logic_0;
end if;
end process;
-- data_array_ce1 assign process. --
data_array_ce1_assign_proc : process(ap_reg_ppiten_pp0_it83, ap_sig_ioackin_outs_TREADY, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st385_fsm_301)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) or (ap_const_logic_1 = ap_sig_cseq_ST_st385_fsm_301))) then
data_array_ce1 <= ap_const_logic_1;
else
data_array_ce1 <= ap_const_logic_0;
end if;
end process;
-- data_array_d0 assign process. --
data_array_d0_assign_proc : process(ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284, rez_addr959960_part_set_fu_830_p5, rez_addr_3953954_part_set_fu_922_p5, rez_addr_5947948_part_set_fu_1017_p5, rez_addr_1956957_part_set_fu_1109_p5, rez_addr_4950951_part_set_fu_1201_p5, rez_addr_6944945_part_set_fu_1308_p5, rez_addr_7941942_part_set_fu_1415_p5, rez_addr_8938939_part_set_fu_1522_p5, rez_addr_9935936_part_set_fu_1629_p5, rez_addr_10932933_part_set_fu_1736_p5, rez_addr_11929930_part_set_fu_1843_p5, rez_addr_12926927_part_set_fu_1950_p5, rez_addr_13923924_part_set_fu_2057_p5, rez_addr_14920921_part_set_fu_2164_p5, rez_addr_15917918_part_set_fu_2271_p5, rez_addr_16914915_part_set_fu_2378_p5, rez_addr_17911912_part_set_fu_2485_p5, rez_addr_18908909_part_set_fu_2592_p5, rez_addr_19905906_part_set_fu_2698_p5, rez_addr_20902903_part_set_fu_2828_p5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) then
data_array_d0 <= rez_addr_20902903_part_set_fu_2828_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)) then
data_array_d0 <= rez_addr_19905906_part_set_fu_2698_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) then
data_array_d0 <= rez_addr_18908909_part_set_fu_2592_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) then
data_array_d0 <= rez_addr_17911912_part_set_fu_2485_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) then
data_array_d0 <= rez_addr_16914915_part_set_fu_2378_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) then
data_array_d0 <= rez_addr_15917918_part_set_fu_2271_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) then
data_array_d0 <= rez_addr_14920921_part_set_fu_2164_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) then
data_array_d0 <= rez_addr_13923924_part_set_fu_2057_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) then
data_array_d0 <= rez_addr_12926927_part_set_fu_1950_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) then
data_array_d0 <= rez_addr_11929930_part_set_fu_1843_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
data_array_d0 <= rez_addr_10932933_part_set_fu_1736_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) then
data_array_d0 <= rez_addr_9935936_part_set_fu_1629_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
data_array_d0 <= rez_addr_8938939_part_set_fu_1522_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) then
data_array_d0 <= rez_addr_7941942_part_set_fu_1415_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) then
data_array_d0 <= rez_addr_6944945_part_set_fu_1308_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) then
data_array_d0 <= rez_addr_4950951_part_set_fu_1201_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
data_array_d0 <= rez_addr_1956957_part_set_fu_1109_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) then
data_array_d0 <= rez_addr_5947948_part_set_fu_1017_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) then
data_array_d0 <= rez_addr_3953954_part_set_fu_922_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) then
data_array_d0 <= rez_addr959960_part_set_fu_830_p5;
else
data_array_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
data_array_d1 <= beta_addr_111281129_part_set_reg_4307;
-- data_array_we0 assign process. --
data_array_we0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)))) then
data_array_we0 <= ap_const_logic_1;
else
data_array_we0 <= ap_const_logic_0;
end if;
end process;
-- data_array_we1 assign process. --
data_array_we1_assign_proc : process(ap_reg_ppiten_pp0_it83, ap_reg_ppstg_exitcond2_reg_3854_pp0_it82)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it82)))) then
data_array_we1 <= ap_const_logic_1;
else
data_array_we1 <= ap_const_logic_0;
end if;
end process;
exitcond2_fu_2840_p2 <= "1" when (i1_reg_418 = ap_const_lv5_14) else "0";
g_fu_3055_p1 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10;
gamma_load_10_fu_3285_p1 <= reg_729;
gamma_load_11_fu_3300_p1 <= reg_729;
gamma_load_12_fu_3315_p1 <= reg_729;
gamma_load_13_fu_3330_p1 <= reg_729;
gamma_load_14_fu_3345_p1 <= reg_729;
gamma_load_15_fu_3360_p1 <= reg_729;
gamma_load_16_fu_3375_p1 <= reg_729;
gamma_load_17_fu_3390_p1 <= reg_729;
gamma_load_18_fu_3405_p1 <= reg_729;
gamma_load_1_fu_3150_p1 <= reg_729;
gamma_load_2_fu_3165_p1 <= reg_729;
gamma_load_3_fu_3180_p1 <= reg_729;
gamma_load_4_fu_3195_p1 <= reg_729;
gamma_load_5_fu_3210_p1 <= reg_729;
gamma_load_6_fu_3225_p1 <= reg_729;
gamma_load_7_fu_3240_p1 <= reg_729;
gamma_load_8_fu_3255_p1 <= reg_729;
gamma_load_9_fu_3270_p1 <= reg_729;
gamma_load_fu_3120_p1 <= reg_729;
gamma_load_s_fu_3135_p1 <= reg_729;
gamma_write_assign_toint_fu_3085_p1 <= grp_fu_622_p2;
grp_fu_430_ce <= ap_const_logic_1;
grp_fu_430_p0 <= v0x_assign4_fu_3001_p1;
grp_fu_430_p1 <= v1x_assign_new_reg_3884;
grp_fu_434_ce <= ap_const_logic_1;
grp_fu_434_p0 <= v0y_assign_fu_3007_p1;
grp_fu_434_p1 <= v1y_assign_new_reg_3889;
grp_fu_438_ce <= ap_const_logic_1;
grp_fu_438_p0 <= v0z_assign_fu_3013_p1;
grp_fu_438_p1 <= v1z_assign_new_reg_3894;
grp_fu_442_ce <= ap_const_logic_1;
grp_fu_442_p0 <= v0x_assign4_fu_3001_p1;
grp_fu_442_p1 <= v2x_assign_new_reg_3899;
grp_fu_446_ce <= ap_const_logic_1;
grp_fu_446_p0 <= v0y_assign_fu_3007_p1;
grp_fu_446_p1 <= v2y_assign_new_reg_3904;
grp_fu_450_ce <= ap_const_logic_1;
grp_fu_450_p0 <= v0z_assign_fu_3013_p1;
grp_fu_450_p1 <= v2z_assign_new_reg_3909;
grp_fu_454_ce <= ap_const_logic_1;
grp_fu_454_p0 <= v0x_assign4_fu_3001_p1;
grp_fu_454_p1 <= rex_assign_new_reg_3929;
grp_fu_458_ce <= ap_const_logic_1;
grp_fu_458_p0 <= v0y_assign_fu_3007_p1;
grp_fu_458_p1 <= rey_assign_new_reg_3934;
grp_fu_462_ce <= ap_const_logic_1;
grp_fu_462_p0 <= v0z_assign_fu_3013_p1;
grp_fu_462_p1 <= rez_assign_new_reg_3939;
grp_fu_466_ce <= ap_const_logic_1;
grp_fu_466_p0 <= tmp_i_reg_4094;
grp_fu_466_p1 <= tmp_i_311_reg_4099;
grp_fu_470_ce <= ap_const_logic_1;
grp_fu_470_p0 <= tmp_3_i_reg_4104;
grp_fu_470_p1 <= tmp_4_i_reg_4109;
grp_fu_474_ce <= ap_const_logic_1;
grp_fu_474_p0 <= tmp_12_i_reg_4114;
grp_fu_474_p1 <= tmp_13_i_reg_4119;
grp_fu_478_ce <= ap_const_logic_1;
grp_fu_478_p0 <= tmp_16_i_reg_4124;
grp_fu_478_p1 <= tmp_17_i_reg_4129;
grp_fu_482_ce <= ap_const_logic_1;
grp_fu_482_p0 <= tmp_8_i_reg_4146;
grp_fu_482_p1 <= tmp_9_i_reg_4151;
grp_fu_486_ce <= ap_const_logic_1;
grp_fu_486_p0 <= tmp_21_i_reg_4168;
grp_fu_486_p1 <= tmp_22_i_reg_4173;
grp_fu_490_ce <= ap_const_logic_1;
grp_fu_490_p0 <= tmp_2_i_reg_4178;
grp_fu_490_p1 <= tmp_6_i_reg_4183;
grp_fu_494_ce <= ap_const_logic_1;
grp_fu_494_p0 <= tmp_15_i_reg_4188;
grp_fu_494_p1 <= tmp_19_i_reg_4193;
grp_fu_498_ce <= ap_const_logic_1;
grp_fu_498_p0 <= tmp_27_i_reg_4198;
grp_fu_498_p1 <= tmp_28_i_reg_4203;
grp_fu_502_ce <= ap_const_logic_1;
grp_fu_502_p0 <= tmp_32_i_reg_4208;
grp_fu_502_p1 <= tmp_33_i_reg_4213;
grp_fu_506_ce <= ap_const_logic_1;
grp_fu_506_p0 <= tmp_7_i_reg_4230;
grp_fu_506_p1 <= tmp_11_i_reg_4235;
grp_fu_510_ce <= ap_const_logic_1;
grp_fu_510_p0 <= tmp_20_i_reg_4240;
grp_fu_510_p1 <= tmp_24_i_reg_4245;
grp_fu_514_ce <= ap_const_logic_1;
grp_fu_514_p0 <= tmp_29_i_reg_4250;
grp_fu_514_p1 <= tmp_30_i_reg_4255;
grp_fu_518_ce <= ap_const_logic_1;
grp_fu_518_p0 <= tmp_34_i_reg_4260;
grp_fu_518_p1 <= tmp_35_i_reg_4265;
grp_fu_522_ce <= ap_const_logic_1;
grp_fu_522_p0 <= e_reg_4038;
grp_fu_522_p1 <= i_1_fu_3063_p1;
grp_fu_526_ce <= ap_const_logic_1;
grp_fu_526_p0 <= f_reg_4045;
grp_fu_526_p1 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10;
grp_fu_530_ce <= ap_const_logic_1;
grp_fu_530_p0 <= f_reg_4045;
grp_fu_530_p1 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10;
grp_fu_534_ce <= ap_const_logic_1;
grp_fu_534_p0 <= d_reg_4031;
grp_fu_534_p1 <= i_1_fu_3063_p1;
grp_fu_538_ce <= ap_const_logic_1;
grp_fu_538_p0 <= a_reg_4010;
grp_fu_538_p1 <= k_reg_4059;
grp_fu_542_ce <= ap_const_logic_1;
grp_fu_542_p0 <= j_reg_4052;
grp_fu_542_p1 <= b_reg_4017;
grp_fu_546_ce <= ap_const_logic_1;
grp_fu_546_p0 <= j_reg_4052;
grp_fu_546_p1 <= c_reg_4024;
grp_fu_550_ce <= ap_const_logic_1;
grp_fu_550_p0 <= a_reg_4010;
grp_fu_550_p1 <= l_reg_4066;
grp_fu_554_ce <= ap_const_logic_1;
grp_fu_554_p0 <= ap_reg_ppstg_d_reg_4031_pp0_it19;
grp_fu_554_p1 <= ap_reg_ppstg_h_reg_4080_pp0_it19;
grp_fu_558_ce <= ap_const_logic_1;
grp_fu_558_p0 <= ap_reg_ppstg_e_reg_4038_pp0_it19;
grp_fu_558_p1 <= ap_reg_ppstg_g_reg_4073_pp0_it19;
grp_fu_562_ce <= ap_const_logic_1;
grp_fu_562_p0 <= ap_reg_ppstg_b_reg_4017_pp0_it19;
grp_fu_562_p1 <= ap_reg_ppstg_l_reg_4066_pp0_it19;
grp_fu_566_ce <= ap_const_logic_1;
grp_fu_566_p0 <= ap_reg_ppstg_k_reg_4059_pp0_it19;
grp_fu_566_p1 <= ap_reg_ppstg_c_reg_4024_pp0_it19;
grp_fu_570_ce <= ap_const_logic_1;
grp_fu_570_p0 <= ap_reg_ppstg_a_reg_4010_pp0_it24;
grp_fu_570_p1 <= tmp_1_i_reg_4134;
grp_fu_574_ce <= ap_const_logic_1;
grp_fu_574_p0 <= ap_reg_ppstg_b_reg_4017_pp0_it24;
grp_fu_574_p1 <= tmp_5_i_reg_4140;
grp_fu_578_ce <= ap_const_logic_1;
grp_fu_578_p0 <= ap_reg_ppstg_f_reg_4045_pp0_it24;
grp_fu_578_p1 <= tmp_14_i_reg_4156;
grp_fu_582_ce <= ap_const_logic_1;
grp_fu_582_p0 <= ap_reg_ppstg_e_reg_4038_pp0_it24;
grp_fu_582_p1 <= tmp_18_i_reg_4162;
grp_fu_586_ce <= ap_const_logic_1;
grp_fu_586_p0 <= tmp_14_i_reg_4156;
grp_fu_586_p1 <= ap_reg_ppstg_i_1_reg_4087_pp0_it24;
grp_fu_590_ce <= ap_const_logic_1;
grp_fu_590_p0 <= tmp_18_i_reg_4162;
grp_fu_590_p1 <= ap_reg_ppstg_h_reg_4080_pp0_it24;
grp_fu_594_ce <= ap_const_logic_1;
grp_fu_594_p0 <= ap_reg_ppstg_j_reg_4052_pp0_it24;
grp_fu_594_p1 <= tmp_1_i_reg_4134;
grp_fu_598_ce <= ap_const_logic_1;
grp_fu_598_p0 <= ap_reg_ppstg_k_reg_4059_pp0_it24;
grp_fu_598_p1 <= tmp_5_i_reg_4140;
grp_fu_602_ce <= ap_const_logic_1;
grp_fu_602_p0 <= ap_reg_ppstg_c_reg_4024_pp0_it33;
grp_fu_602_p1 <= tmp_10_i_reg_4218;
grp_fu_606_ce <= ap_const_logic_1;
grp_fu_606_p0 <= ap_reg_ppstg_d_reg_4031_pp0_it33;
grp_fu_606_p1 <= tmp_23_i_reg_4224;
grp_fu_610_ce <= ap_const_logic_1;
grp_fu_610_p0 <= tmp_23_i_reg_4224;
grp_fu_610_p1 <= ap_reg_ppstg_g_reg_4073_pp0_it33;
grp_fu_614_ce <= ap_const_logic_1;
grp_fu_614_p0 <= ap_reg_ppstg_l_reg_4066_pp0_it33;
grp_fu_614_p1 <= tmp_10_i_reg_4218;
grp_fu_618_ce <= ap_const_logic_1;
grp_fu_618_p0 <= tmp_61_neg_i_reg_4297;
grp_fu_618_p1 <= im_reg_4290;
grp_fu_622_ce <= ap_const_logic_1;
grp_fu_622_p0 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77;
grp_fu_622_p1 <= im_reg_4290;
grp_fu_626_ce <= ap_const_logic_1;
grp_fu_626_p0 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77;
grp_fu_626_p1 <= im_reg_4290;
grp_fu_630_ce <= ap_const_logic_1;
grp_fu_630_p0 <= ap_const_lv32_3F800000;
grp_fu_630_p1 <= m_reg_4270;
grp_fu_639_p4 <= data_array_q1(511 downto 480);
h_fu_3059_p1 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10;
i_1_fu_3063_p1 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10;
i_fu_2846_p2 <= std_logic_vector(unsigned(i1_reg_418) + unsigned(ap_const_lv5_1));
-- ins_TREADY assign process. --
ins_TREADY_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st76_fsm_75, ap_sig_cseq_ST_st91_fsm_90, ap_sig_cseq_ST_st106_fsm_105, ap_sig_cseq_ST_st121_fsm_120, ap_sig_cseq_ST_st136_fsm_135, ap_sig_cseq_ST_st151_fsm_150, ap_sig_cseq_ST_st166_fsm_165, ap_sig_cseq_ST_st181_fsm_180, ap_sig_cseq_ST_st196_fsm_195, ap_sig_cseq_ST_st211_fsm_210, ap_sig_cseq_ST_st226_fsm_225, ap_sig_cseq_ST_st241_fsm_240, ap_sig_cseq_ST_st256_fsm_255, ap_sig_cseq_ST_st271_fsm_270, ap_sig_cseq_ST_st286_fsm_285, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st92_fsm_91, ap_sig_cseq_ST_st107_fsm_106, ap_sig_cseq_ST_st122_fsm_121, ap_sig_cseq_ST_st137_fsm_136, ap_sig_cseq_ST_st152_fsm_151, ap_sig_cseq_ST_st167_fsm_166, ap_sig_cseq_ST_st182_fsm_181, ap_sig_cseq_ST_st197_fsm_196, ap_sig_cseq_ST_st212_fsm_211, ap_sig_cseq_ST_st227_fsm_226, ap_sig_cseq_ST_st242_fsm_241, ap_sig_cseq_ST_st257_fsm_256, ap_sig_cseq_ST_st272_fsm_271, ap_sig_cseq_ST_st287_fsm_286, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st93_fsm_92, ap_sig_cseq_ST_st108_fsm_107, ap_sig_cseq_ST_st123_fsm_122, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st153_fsm_152, ap_sig_cseq_ST_st168_fsm_167, ap_sig_cseq_ST_st183_fsm_182, ap_sig_cseq_ST_st198_fsm_197, ap_sig_cseq_ST_st213_fsm_212, ap_sig_cseq_ST_st228_fsm_227, ap_sig_cseq_ST_st243_fsm_242, ap_sig_cseq_ST_st258_fsm_257, ap_sig_cseq_ST_st273_fsm_272, ap_sig_cseq_ST_st288_fsm_287, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st94_fsm_93, ap_sig_cseq_ST_st109_fsm_108, ap_sig_cseq_ST_st124_fsm_123, ap_sig_cseq_ST_st139_fsm_138, ap_sig_cseq_ST_st154_fsm_153, ap_sig_cseq_ST_st169_fsm_168, ap_sig_cseq_ST_st184_fsm_183, ap_sig_cseq_ST_st199_fsm_198, ap_sig_cseq_ST_st214_fsm_213, ap_sig_cseq_ST_st229_fsm_228, ap_sig_cseq_ST_st244_fsm_243, ap_sig_cseq_ST_st259_fsm_258, ap_sig_cseq_ST_st274_fsm_273, ap_sig_cseq_ST_st289_fsm_288, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st95_fsm_94, ap_sig_cseq_ST_st110_fsm_109, ap_sig_cseq_ST_st125_fsm_124, ap_sig_cseq_ST_st140_fsm_139, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st170_fsm_169, ap_sig_cseq_ST_st185_fsm_184, ap_sig_cseq_ST_st200_fsm_199, ap_sig_cseq_ST_st215_fsm_214, ap_sig_cseq_ST_st230_fsm_229, ap_sig_cseq_ST_st245_fsm_244, ap_sig_cseq_ST_st260_fsm_259, ap_sig_cseq_ST_st275_fsm_274, ap_sig_cseq_ST_st290_fsm_289, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st81_fsm_80, ap_sig_cseq_ST_st96_fsm_95, ap_sig_cseq_ST_st111_fsm_110, ap_sig_cseq_ST_st126_fsm_125, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st156_fsm_155, ap_sig_cseq_ST_st171_fsm_170, ap_sig_cseq_ST_st186_fsm_185, ap_sig_cseq_ST_st201_fsm_200, ap_sig_cseq_ST_st216_fsm_215, ap_sig_cseq_ST_st231_fsm_230, ap_sig_cseq_ST_st246_fsm_245, ap_sig_cseq_ST_st261_fsm_260, ap_sig_cseq_ST_st276_fsm_275, ap_sig_cseq_ST_st291_fsm_290, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st82_fsm_81, ap_sig_cseq_ST_st97_fsm_96, ap_sig_cseq_ST_st112_fsm_111, ap_sig_cseq_ST_st127_fsm_126, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st157_fsm_156, ap_sig_cseq_ST_st172_fsm_171, ap_sig_cseq_ST_st187_fsm_186, ap_sig_cseq_ST_st202_fsm_201, ap_sig_cseq_ST_st217_fsm_216, ap_sig_cseq_ST_st232_fsm_231, ap_sig_cseq_ST_st247_fsm_246, ap_sig_cseq_ST_st262_fsm_261, ap_sig_cseq_ST_st277_fsm_276, ap_sig_cseq_ST_st292_fsm_291, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st98_fsm_97, ap_sig_cseq_ST_st113_fsm_112, ap_sig_cseq_ST_st128_fsm_127, ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st158_fsm_157, ap_sig_cseq_ST_st173_fsm_172, ap_sig_cseq_ST_st188_fsm_187, ap_sig_cseq_ST_st203_fsm_202, ap_sig_cseq_ST_st218_fsm_217, ap_sig_cseq_ST_st233_fsm_232, ap_sig_cseq_ST_st248_fsm_247, ap_sig_cseq_ST_st263_fsm_262, ap_sig_cseq_ST_st278_fsm_277, ap_sig_cseq_ST_st293_fsm_292, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st84_fsm_83, ap_sig_cseq_ST_st99_fsm_98, ap_sig_cseq_ST_st114_fsm_113, ap_sig_cseq_ST_st129_fsm_128, ap_sig_cseq_ST_st144_fsm_143, ap_sig_cseq_ST_st159_fsm_158, ap_sig_cseq_ST_st174_fsm_173, ap_sig_cseq_ST_st189_fsm_188, ap_sig_cseq_ST_st204_fsm_203, ap_sig_cseq_ST_st219_fsm_218, ap_sig_cseq_ST_st234_fsm_233, ap_sig_cseq_ST_st249_fsm_248, ap_sig_cseq_ST_st264_fsm_263, ap_sig_cseq_ST_st279_fsm_278, ap_sig_cseq_ST_st294_fsm_293, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st85_fsm_84, ap_sig_cseq_ST_st100_fsm_99, ap_sig_cseq_ST_st115_fsm_114, ap_sig_cseq_ST_st130_fsm_129, ap_sig_cseq_ST_st145_fsm_144, ap_sig_cseq_ST_st160_fsm_159, ap_sig_cseq_ST_st175_fsm_174, ap_sig_cseq_ST_st190_fsm_189, ap_sig_cseq_ST_st205_fsm_204, ap_sig_cseq_ST_st220_fsm_219, ap_sig_cseq_ST_st235_fsm_234, ap_sig_cseq_ST_st250_fsm_249, ap_sig_cseq_ST_st265_fsm_264, ap_sig_cseq_ST_st280_fsm_279, ap_sig_cseq_ST_st295_fsm_294, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st101_fsm_100, ap_sig_cseq_ST_st116_fsm_115, ap_sig_cseq_ST_st131_fsm_130, ap_sig_cseq_ST_st146_fsm_145, ap_sig_cseq_ST_st161_fsm_160, ap_sig_cseq_ST_st176_fsm_175, ap_sig_cseq_ST_st191_fsm_190, ap_sig_cseq_ST_st206_fsm_205, ap_sig_cseq_ST_st221_fsm_220, ap_sig_cseq_ST_st236_fsm_235, ap_sig_cseq_ST_st251_fsm_250, ap_sig_cseq_ST_st266_fsm_265, ap_sig_cseq_ST_st281_fsm_280, ap_sig_cseq_ST_st296_fsm_295, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st102_fsm_101, ap_sig_cseq_ST_st117_fsm_116, ap_sig_cseq_ST_st132_fsm_131, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st162_fsm_161, ap_sig_cseq_ST_st177_fsm_176, ap_sig_cseq_ST_st192_fsm_191, ap_sig_cseq_ST_st207_fsm_206, ap_sig_cseq_ST_st222_fsm_221, ap_sig_cseq_ST_st237_fsm_236, ap_sig_cseq_ST_st252_fsm_251, ap_sig_cseq_ST_st267_fsm_266, ap_sig_cseq_ST_st282_fsm_281, ap_sig_cseq_ST_st297_fsm_296, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st103_fsm_102, ap_sig_cseq_ST_st118_fsm_117, ap_sig_cseq_ST_st133_fsm_132, ap_sig_cseq_ST_st148_fsm_147, ap_sig_cseq_ST_st163_fsm_162, ap_sig_cseq_ST_st178_fsm_177, ap_sig_cseq_ST_st193_fsm_192, ap_sig_cseq_ST_st208_fsm_207, ap_sig_cseq_ST_st223_fsm_222, ap_sig_cseq_ST_st238_fsm_237, ap_sig_cseq_ST_st253_fsm_252, ap_sig_cseq_ST_st268_fsm_267, ap_sig_cseq_ST_st283_fsm_282, ap_sig_cseq_ST_st298_fsm_297, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st104_fsm_103, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st134_fsm_133, ap_sig_cseq_ST_st149_fsm_148, ap_sig_cseq_ST_st164_fsm_163, ap_sig_cseq_ST_st179_fsm_178, ap_sig_cseq_ST_st194_fsm_193, ap_sig_cseq_ST_st209_fsm_208, ap_sig_cseq_ST_st224_fsm_223, ap_sig_cseq_ST_st239_fsm_238, ap_sig_cseq_ST_st254_fsm_253, ap_sig_cseq_ST_st269_fsm_268, ap_sig_cseq_ST_st284_fsm_283, ap_sig_cseq_ST_st299_fsm_298, ap_sig_cseq_ST_st72_fsm_71, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st33_fsm_32, ap_sig_cseq_ST_st34_fsm_33, ap_sig_cseq_ST_st35_fsm_34, ap_sig_cseq_ST_st36_fsm_35, ap_sig_cseq_ST_st37_fsm_36, ap_sig_cseq_ST_st38_fsm_37, ap_sig_cseq_ST_st39_fsm_38, ap_sig_cseq_ST_st40_fsm_39, ap_sig_cseq_ST_st41_fsm_40, ap_sig_cseq_ST_st42_fsm_41, ap_sig_cseq_ST_st43_fsm_42, ap_sig_cseq_ST_st44_fsm_43, ap_sig_cseq_ST_st45_fsm_44, ap_sig_cseq_ST_st46_fsm_45, ap_sig_cseq_ST_st47_fsm_46, ap_sig_cseq_ST_st48_fsm_47, ap_sig_cseq_ST_st49_fsm_48, ap_sig_cseq_ST_st50_fsm_49, ap_sig_cseq_ST_st51_fsm_50, ap_sig_cseq_ST_st52_fsm_51, ap_sig_cseq_ST_st53_fsm_52, ap_sig_cseq_ST_st54_fsm_53, ap_sig_cseq_ST_st55_fsm_54, ap_sig_cseq_ST_st56_fsm_55, ap_sig_cseq_ST_st57_fsm_56, ap_sig_cseq_ST_st58_fsm_57, ap_sig_cseq_ST_st59_fsm_58, ap_sig_cseq_ST_st60_fsm_59, ap_sig_cseq_ST_st61_fsm_60, ap_sig_cseq_ST_st62_fsm_61, ap_sig_cseq_ST_st63_fsm_62, ap_sig_cseq_ST_st64_fsm_63, ap_sig_cseq_ST_st65_fsm_64, ap_sig_cseq_ST_st66_fsm_65, ap_sig_cseq_ST_st67_fsm_66, ap_sig_cseq_ST_st68_fsm_67, ap_sig_cseq_ST_st69_fsm_68, ap_sig_cseq_ST_st70_fsm_69, ap_sig_cseq_ST_st71_fsm_70, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st106_fsm_105)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st136_fsm_135)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st181_fsm_180)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st196_fsm_195)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st211_fsm_210)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st226_fsm_225)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st241_fsm_240)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st256_fsm_255)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st271_fsm_270)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st286_fsm_285)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st107_fsm_106)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st137_fsm_136)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st167_fsm_166)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st182_fsm_181)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st197_fsm_196)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st212_fsm_211)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st227_fsm_226)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st242_fsm_241)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st257_fsm_256)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st272_fsm_271)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st287_fsm_286)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st108_fsm_107)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st168_fsm_167)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st183_fsm_182)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st198_fsm_197)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st213_fsm_212)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st228_fsm_227)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st243_fsm_242)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st258_fsm_257)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st273_fsm_272)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st288_fsm_287)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st109_fsm_108)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st169_fsm_168)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st184_fsm_183)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st199_fsm_198)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st214_fsm_213)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st229_fsm_228)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st244_fsm_243)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st259_fsm_258)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st274_fsm_273)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st289_fsm_288)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st110_fsm_109)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st170_fsm_169)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st185_fsm_184)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st200_fsm_199)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st215_fsm_214)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st230_fsm_229)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st245_fsm_244)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st260_fsm_259)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st275_fsm_274)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st290_fsm_289)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st96_fsm_95)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st111_fsm_110)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st126_fsm_125)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st171_fsm_170)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st186_fsm_185)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st201_fsm_200)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st216_fsm_215)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st231_fsm_230)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st246_fsm_245)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st261_fsm_260)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st276_fsm_275)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st291_fsm_290)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st112_fsm_111)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st127_fsm_126)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st172_fsm_171)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st187_fsm_186)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st202_fsm_201)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st217_fsm_216)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st232_fsm_231)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st247_fsm_246)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st262_fsm_261)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st277_fsm_276)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st292_fsm_291)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st113_fsm_112)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st158_fsm_157)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st173_fsm_172)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st188_fsm_187)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st203_fsm_202)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st218_fsm_217)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st233_fsm_232)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st248_fsm_247)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st263_fsm_262)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st278_fsm_277)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st293_fsm_292)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st174_fsm_173)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st189_fsm_188)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st204_fsm_203)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st219_fsm_218)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st234_fsm_233)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st249_fsm_248)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st264_fsm_263)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st279_fsm_278)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st294_fsm_293)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st100_fsm_99)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st130_fsm_129)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st175_fsm_174)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st190_fsm_189)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st205_fsm_204)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st220_fsm_219)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st235_fsm_234)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st250_fsm_249)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st265_fsm_264)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st280_fsm_279)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st295_fsm_294)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st101_fsm_100)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st131_fsm_130)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st176_fsm_175)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st191_fsm_190)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st206_fsm_205)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st221_fsm_220)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st236_fsm_235)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st251_fsm_250)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st266_fsm_265)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st281_fsm_280)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st296_fsm_295)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st102_fsm_101)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st132_fsm_131)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st177_fsm_176)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st192_fsm_191)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st207_fsm_206)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st222_fsm_221)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st237_fsm_236)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st252_fsm_251)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st267_fsm_266)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st282_fsm_281)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st297_fsm_296)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st103_fsm_102)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st133_fsm_132)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st178_fsm_177)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st193_fsm_192)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st208_fsm_207)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st223_fsm_222)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st238_fsm_237)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st253_fsm_252)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st268_fsm_267)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st283_fsm_282)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st298_fsm_297)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st134_fsm_133)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st179_fsm_178)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st194_fsm_193)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st209_fsm_208)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st224_fsm_223)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st239_fsm_238)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st254_fsm_253)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st269_fsm_268)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st284_fsm_283)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st299_fsm_298)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st36_fsm_35)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st37_fsm_36)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st38_fsm_37)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st45_fsm_44)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st50_fsm_49)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st51_fsm_50)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st52_fsm_51)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st54_fsm_53)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st55_fsm_54)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st56_fsm_55)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st57_fsm_56)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st58_fsm_57)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st59_fsm_58)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st60_fsm_59)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st61_fsm_60)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st62_fsm_61)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st63_fsm_62)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st64_fsm_63)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st65_fsm_64)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st66_fsm_65)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st67_fsm_66)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st68_fsm_67)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st69_fsm_68)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st70_fsm_69)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)))) then
ins_TREADY <= ap_const_logic_1;
else
ins_TREADY <= ap_const_logic_0;
end if;
end process;
ins_data_tmp_load_100_toint_fu_1361_p1 <= reg_709;
ins_data_tmp_load_101_toint_fu_1365_p1 <= reg_713;
ins_data_tmp_load_102_toint_fu_1369_p1 <= reg_717;
ins_data_tmp_load_103_toint_fu_1373_p1 <= reg_721;
ins_data_tmp_load_104_toint_fu_1377_p1 <= ins_TDATA;
ins_data_tmp_load_105_toint_fu_1428_p1 <= reg_669;
ins_data_tmp_load_106_toint_fu_1432_p1 <= reg_673;
ins_data_tmp_load_107_toint_fu_1436_p1 <= reg_677;
ins_data_tmp_load_108_toint_fu_1440_p1 <= reg_681;
ins_data_tmp_load_109_toint_fu_1444_p1 <= reg_685;
ins_data_tmp_load_10_toint_fu_777_p1 <= reg_709;
ins_data_tmp_load_110_toint_fu_1448_p1 <= reg_689;
ins_data_tmp_load_111_toint_fu_1452_p1 <= reg_693;
ins_data_tmp_load_112_toint_fu_1456_p1 <= reg_697;
ins_data_tmp_load_113_toint_fu_1460_p1 <= reg_701;
ins_data_tmp_load_114_toint_fu_1464_p1 <= reg_705;
ins_data_tmp_load_115_toint_fu_1468_p1 <= reg_709;
ins_data_tmp_load_116_toint_fu_1472_p1 <= reg_713;
ins_data_tmp_load_117_toint_fu_1476_p1 <= reg_717;
ins_data_tmp_load_118_toint_fu_1480_p1 <= reg_721;
ins_data_tmp_load_119_toint_fu_1484_p1 <= ins_TDATA;
ins_data_tmp_load_11_toint_fu_781_p1 <= reg_713;
ins_data_tmp_load_120_toint_fu_1535_p1 <= reg_669;
ins_data_tmp_load_121_toint_fu_1539_p1 <= reg_673;
ins_data_tmp_load_122_toint_fu_1543_p1 <= reg_677;
ins_data_tmp_load_123_toint_fu_1547_p1 <= reg_681;
ins_data_tmp_load_124_toint_fu_1551_p1 <= reg_685;
ins_data_tmp_load_125_toint_fu_1555_p1 <= reg_689;
ins_data_tmp_load_126_toint_fu_1559_p1 <= reg_693;
ins_data_tmp_load_127_toint_fu_1563_p1 <= reg_697;
ins_data_tmp_load_128_toint_fu_1567_p1 <= reg_701;
ins_data_tmp_load_129_toint_fu_1571_p1 <= reg_705;
ins_data_tmp_load_12_toint_fu_785_p1 <= reg_717;
ins_data_tmp_load_130_toint_fu_1575_p1 <= reg_709;
ins_data_tmp_load_131_toint_fu_1579_p1 <= reg_713;
ins_data_tmp_load_132_toint_fu_1583_p1 <= reg_717;
ins_data_tmp_load_133_toint_fu_1587_p1 <= reg_721;
ins_data_tmp_load_134_toint_fu_1591_p1 <= ins_TDATA;
ins_data_tmp_load_135_toint_fu_1642_p1 <= reg_669;
ins_data_tmp_load_136_toint_fu_1646_p1 <= reg_673;
ins_data_tmp_load_137_toint_fu_1650_p1 <= reg_677;
ins_data_tmp_load_138_toint_fu_1654_p1 <= reg_681;
ins_data_tmp_load_139_toint_fu_1658_p1 <= reg_685;
ins_data_tmp_load_13_toint_fu_789_p1 <= reg_721;
ins_data_tmp_load_140_toint_fu_1662_p1 <= reg_689;
ins_data_tmp_load_141_toint_fu_1666_p1 <= reg_693;
ins_data_tmp_load_142_toint_fu_1670_p1 <= reg_697;
ins_data_tmp_load_143_toint_fu_1674_p1 <= reg_701;
ins_data_tmp_load_144_toint_fu_1678_p1 <= reg_705;
ins_data_tmp_load_145_toint_fu_1682_p1 <= reg_709;
ins_data_tmp_load_146_toint_fu_1686_p1 <= reg_713;
ins_data_tmp_load_147_toint_fu_1690_p1 <= reg_717;
ins_data_tmp_load_148_toint_fu_1694_p1 <= reg_721;
ins_data_tmp_load_149_toint_fu_1698_p1 <= ins_TDATA;
ins_data_tmp_load_14_toint_fu_793_p1 <= ins_data_val14_reg_3415;
ins_data_tmp_load_150_toint_fu_1749_p1 <= reg_669;
ins_data_tmp_load_151_toint_fu_1753_p1 <= reg_673;
ins_data_tmp_load_152_toint_fu_1757_p1 <= reg_677;
ins_data_tmp_load_153_toint_fu_1761_p1 <= reg_681;
ins_data_tmp_load_154_toint_fu_1765_p1 <= reg_685;
ins_data_tmp_load_155_toint_fu_1769_p1 <= reg_689;
ins_data_tmp_load_156_toint_fu_1773_p1 <= reg_693;
ins_data_tmp_load_157_toint_fu_1777_p1 <= reg_697;
ins_data_tmp_load_158_toint_fu_1781_p1 <= reg_701;
ins_data_tmp_load_159_toint_fu_1785_p1 <= reg_705;
ins_data_tmp_load_15_toint_fu_1030_p1 <= ins_data_val15_reg_3420;
ins_data_tmp_load_160_toint_fu_1789_p1 <= reg_709;
ins_data_tmp_load_161_toint_fu_1793_p1 <= reg_713;
ins_data_tmp_load_162_toint_fu_1797_p1 <= reg_717;
ins_data_tmp_load_163_toint_fu_1801_p1 <= reg_721;
ins_data_tmp_load_164_toint_fu_1805_p1 <= ins_TDATA;
ins_data_tmp_load_165_toint_fu_1856_p1 <= reg_669;
ins_data_tmp_load_166_toint_fu_1860_p1 <= reg_673;
ins_data_tmp_load_167_toint_fu_1864_p1 <= reg_677;
ins_data_tmp_load_168_toint_fu_1868_p1 <= reg_681;
ins_data_tmp_load_169_toint_fu_1872_p1 <= reg_685;
ins_data_tmp_load_16_toint_fu_1033_p1 <= ins_data_val16_reg_3425;
ins_data_tmp_load_170_toint_fu_1876_p1 <= reg_689;
ins_data_tmp_load_171_toint_fu_1880_p1 <= reg_693;
ins_data_tmp_load_172_toint_fu_1884_p1 <= reg_697;
ins_data_tmp_load_173_toint_fu_1888_p1 <= reg_701;
ins_data_tmp_load_174_toint_fu_1892_p1 <= reg_705;
ins_data_tmp_load_175_toint_fu_1896_p1 <= reg_709;
ins_data_tmp_load_176_toint_fu_1900_p1 <= reg_713;
ins_data_tmp_load_177_toint_fu_1904_p1 <= reg_717;
ins_data_tmp_load_178_toint_fu_1908_p1 <= reg_721;
ins_data_tmp_load_179_toint_fu_1912_p1 <= ins_TDATA;
ins_data_tmp_load_17_toint_fu_1036_p1 <= ins_data_val17_reg_3430;
ins_data_tmp_load_180_toint_fu_1963_p1 <= reg_669;
ins_data_tmp_load_181_toint_fu_1967_p1 <= reg_673;
ins_data_tmp_load_182_toint_fu_1971_p1 <= reg_677;
ins_data_tmp_load_183_toint_fu_1975_p1 <= reg_681;
ins_data_tmp_load_184_toint_fu_1979_p1 <= reg_685;
ins_data_tmp_load_185_toint_fu_1983_p1 <= reg_689;
ins_data_tmp_load_186_toint_fu_1987_p1 <= reg_693;
ins_data_tmp_load_187_toint_fu_1991_p1 <= reg_697;
ins_data_tmp_load_188_toint_fu_1995_p1 <= reg_701;
ins_data_tmp_load_189_toint_fu_1999_p1 <= reg_705;
ins_data_tmp_load_18_toint_fu_1039_p1 <= ins_data_val18_reg_3435;
ins_data_tmp_load_190_toint_fu_2003_p1 <= reg_709;
ins_data_tmp_load_191_toint_fu_2007_p1 <= reg_713;
ins_data_tmp_load_192_toint_fu_2011_p1 <= reg_717;
ins_data_tmp_load_193_toint_fu_2015_p1 <= reg_721;
ins_data_tmp_load_194_toint_fu_2019_p1 <= ins_TDATA;
ins_data_tmp_load_195_toint_fu_2070_p1 <= reg_669;
ins_data_tmp_load_196_toint_fu_2074_p1 <= reg_673;
ins_data_tmp_load_197_toint_fu_2078_p1 <= reg_677;
ins_data_tmp_load_198_toint_fu_2082_p1 <= reg_681;
ins_data_tmp_load_199_toint_fu_2086_p1 <= reg_685;
ins_data_tmp_load_19_toint_fu_1042_p1 <= ins_data_val19_reg_3440;
ins_data_tmp_load_1_toint_fu_741_p1 <= reg_673;
ins_data_tmp_load_200_toint_fu_2090_p1 <= reg_689;
ins_data_tmp_load_201_toint_fu_2094_p1 <= reg_693;
ins_data_tmp_load_202_toint_fu_2098_p1 <= reg_697;
ins_data_tmp_load_203_toint_fu_2102_p1 <= reg_701;
ins_data_tmp_load_204_toint_fu_2106_p1 <= reg_705;
ins_data_tmp_load_205_toint_fu_2110_p1 <= reg_709;
ins_data_tmp_load_206_toint_fu_2114_p1 <= reg_713;
ins_data_tmp_load_207_toint_fu_2118_p1 <= reg_717;
ins_data_tmp_load_208_toint_fu_2122_p1 <= reg_721;
ins_data_tmp_load_209_toint_fu_2126_p1 <= ins_TDATA;
ins_data_tmp_load_20_toint_fu_1045_p1 <= ins_data_val20_reg_3445;
ins_data_tmp_load_210_toint_fu_2177_p1 <= reg_669;
ins_data_tmp_load_211_toint_fu_2181_p1 <= reg_673;
ins_data_tmp_load_212_toint_fu_2185_p1 <= reg_677;
ins_data_tmp_load_213_toint_fu_2189_p1 <= reg_681;
ins_data_tmp_load_214_toint_fu_2193_p1 <= reg_685;
ins_data_tmp_load_215_toint_fu_2197_p1 <= reg_689;
ins_data_tmp_load_216_toint_fu_2201_p1 <= reg_693;
ins_data_tmp_load_217_toint_fu_2205_p1 <= reg_697;
ins_data_tmp_load_218_toint_fu_2209_p1 <= reg_701;
ins_data_tmp_load_219_toint_fu_2213_p1 <= reg_705;
ins_data_tmp_load_21_toint_fu_1048_p1 <= ins_data_val21_reg_3450;
ins_data_tmp_load_220_toint_fu_2217_p1 <= reg_709;
ins_data_tmp_load_221_toint_fu_2221_p1 <= reg_713;
ins_data_tmp_load_222_toint_fu_2225_p1 <= reg_717;
ins_data_tmp_load_223_toint_fu_2229_p1 <= reg_721;
ins_data_tmp_load_224_toint_fu_2233_p1 <= ins_TDATA;
ins_data_tmp_load_225_toint_fu_2284_p1 <= reg_669;
ins_data_tmp_load_226_toint_fu_2288_p1 <= reg_673;
ins_data_tmp_load_227_toint_fu_2292_p1 <= reg_677;
ins_data_tmp_load_228_toint_fu_2296_p1 <= reg_681;
ins_data_tmp_load_229_toint_fu_2300_p1 <= reg_685;
ins_data_tmp_load_22_toint_fu_1051_p1 <= ins_data_val22_reg_3455;
ins_data_tmp_load_230_toint_fu_2304_p1 <= reg_689;
ins_data_tmp_load_231_toint_fu_2308_p1 <= reg_693;
ins_data_tmp_load_232_toint_fu_2312_p1 <= reg_697;
ins_data_tmp_load_233_toint_fu_2316_p1 <= reg_701;
ins_data_tmp_load_234_toint_fu_2320_p1 <= reg_705;
ins_data_tmp_load_235_toint_fu_2324_p1 <= reg_709;
ins_data_tmp_load_236_toint_fu_2328_p1 <= reg_713;
ins_data_tmp_load_237_toint_fu_2332_p1 <= reg_717;
ins_data_tmp_load_238_toint_fu_2336_p1 <= reg_721;
ins_data_tmp_load_239_toint_fu_2340_p1 <= ins_TDATA;
ins_data_tmp_load_23_toint_fu_1054_p1 <= ins_data_val23_reg_3460;
ins_data_tmp_load_240_toint_fu_2391_p1 <= reg_669;
ins_data_tmp_load_241_toint_fu_2395_p1 <= reg_673;
ins_data_tmp_load_242_toint_fu_2399_p1 <= reg_677;
ins_data_tmp_load_243_toint_fu_2403_p1 <= reg_681;
ins_data_tmp_load_244_toint_fu_2407_p1 <= reg_685;
ins_data_tmp_load_245_toint_fu_2411_p1 <= reg_689;
ins_data_tmp_load_246_toint_fu_2415_p1 <= reg_693;
ins_data_tmp_load_247_toint_fu_2419_p1 <= reg_697;
ins_data_tmp_load_248_toint_fu_2423_p1 <= reg_701;
ins_data_tmp_load_249_toint_fu_2427_p1 <= reg_705;
ins_data_tmp_load_24_toint_fu_1057_p1 <= ins_data_val24_reg_3465;
ins_data_tmp_load_250_toint_fu_2431_p1 <= reg_709;
ins_data_tmp_load_251_toint_fu_2435_p1 <= reg_713;
ins_data_tmp_load_252_toint_fu_2439_p1 <= reg_717;
ins_data_tmp_load_253_toint_fu_2443_p1 <= reg_721;
ins_data_tmp_load_254_toint_fu_2447_p1 <= ins_TDATA;
ins_data_tmp_load_255_toint_fu_2498_p1 <= reg_669;
ins_data_tmp_load_256_toint_fu_2502_p1 <= reg_673;
ins_data_tmp_load_257_toint_fu_2506_p1 <= reg_677;
ins_data_tmp_load_258_toint_fu_2510_p1 <= reg_681;
ins_data_tmp_load_259_toint_fu_2514_p1 <= reg_685;
ins_data_tmp_load_25_toint_fu_1060_p1 <= ins_data_val25_reg_3470;
ins_data_tmp_load_260_toint_fu_2518_p1 <= reg_689;
ins_data_tmp_load_261_toint_fu_2522_p1 <= reg_693;
ins_data_tmp_load_262_toint_fu_2526_p1 <= reg_697;
ins_data_tmp_load_263_toint_fu_2530_p1 <= reg_701;
ins_data_tmp_load_264_toint_fu_2534_p1 <= reg_705;
ins_data_tmp_load_265_toint_fu_2538_p1 <= reg_709;
ins_data_tmp_load_266_toint_fu_2542_p1 <= reg_713;
ins_data_tmp_load_267_toint_fu_2546_p1 <= reg_717;
ins_data_tmp_load_268_toint_fu_2550_p1 <= reg_721;
ins_data_tmp_load_269_toint_fu_2554_p1 <= ins_TDATA;
ins_data_tmp_load_26_toint_fu_1063_p1 <= ins_data_val26_reg_3475;
ins_data_tmp_load_270_toint_fu_2604_p1 <= reg_669;
ins_data_tmp_load_271_toint_fu_2608_p1 <= reg_673;
ins_data_tmp_load_272_toint_fu_2612_p1 <= reg_677;
ins_data_tmp_load_273_toint_fu_2616_p1 <= reg_681;
ins_data_tmp_load_274_toint_fu_2620_p1 <= reg_685;
ins_data_tmp_load_275_toint_fu_2624_p1 <= reg_689;
ins_data_tmp_load_276_toint_fu_2628_p1 <= reg_693;
ins_data_tmp_load_277_toint_fu_2632_p1 <= reg_697;
ins_data_tmp_load_278_toint_fu_2636_p1 <= reg_701;
ins_data_tmp_load_279_toint_fu_2640_p1 <= reg_705;
ins_data_tmp_load_27_toint_fu_1066_p1 <= ins_data_val27_reg_3480;
ins_data_tmp_load_280_toint_fu_2644_p1 <= reg_709;
ins_data_tmp_load_281_toint_fu_2648_p1 <= reg_713;
ins_data_tmp_load_282_toint_fu_2652_p1 <= reg_717;
ins_data_tmp_load_283_toint_fu_2656_p1 <= reg_721;
ins_data_tmp_load_284_toint_fu_2660_p1 <= ins_TDATA;
ins_data_tmp_load_285_toint_fu_2710_p1 <= reg_669;
ins_data_tmp_load_286_toint_fu_2714_p1 <= reg_673;
ins_data_tmp_load_287_toint_fu_2718_p1 <= reg_677;
ins_data_tmp_load_288_toint_fu_2722_p1 <= reg_681;
ins_data_tmp_load_289_toint_fu_2726_p1 <= reg_685;
ins_data_tmp_load_28_toint_fu_1069_p1 <= ins_data_val28_reg_3485;
ins_data_tmp_load_290_toint_fu_2730_p1 <= reg_689;
ins_data_tmp_load_291_toint_fu_2734_p1 <= reg_693;
ins_data_tmp_load_292_toint_fu_2738_p1 <= reg_697;
ins_data_tmp_load_293_toint_fu_2742_p1 <= reg_701;
ins_data_tmp_load_294_toint_fu_2746_p1 <= reg_705;
ins_data_tmp_load_295_toint_fu_2750_p1 <= reg_709;
ins_data_tmp_load_296_toint_fu_2754_p1 <= reg_713;
ins_data_tmp_load_297_toint_fu_2758_p1 <= reg_717;
ins_data_tmp_load_298_toint_fu_2762_p1 <= reg_721;
ins_data_tmp_load_299_toint_fu_2790_p1 <= ins_TDATA;
ins_data_tmp_load_29_toint_fu_1072_p1 <= ins_data_val29_reg_3490;
ins_data_tmp_load_2_toint_fu_745_p1 <= reg_677;
ins_data_tmp_load_30_toint_fu_843_p1 <= ins_data_val30_reg_3495;
ins_data_tmp_load_31_toint_fu_846_p1 <= ins_data_val31_reg_3500;
ins_data_tmp_load_32_toint_fu_849_p1 <= ins_data_val32_reg_3505;
ins_data_tmp_load_33_toint_fu_852_p1 <= ins_data_val33_reg_3510;
ins_data_tmp_load_34_toint_fu_855_p1 <= ins_data_val34_reg_3515;
ins_data_tmp_load_35_toint_fu_858_p1 <= ins_data_val35_reg_3520;
ins_data_tmp_load_36_toint_fu_861_p1 <= ins_data_val36_reg_3525;
ins_data_tmp_load_37_toint_fu_864_p1 <= ins_data_val37_reg_3530;
ins_data_tmp_load_38_toint_fu_867_p1 <= ins_data_val38_reg_3535;
ins_data_tmp_load_39_toint_fu_870_p1 <= ins_data_val39_reg_3540;
ins_data_tmp_load_3_toint_fu_749_p1 <= reg_681;
ins_data_tmp_load_40_toint_fu_873_p1 <= ins_data_val40_reg_3545;
ins_data_tmp_load_41_toint_fu_876_p1 <= ins_data_val41_reg_3550;
ins_data_tmp_load_42_toint_fu_879_p1 <= ins_data_val42_reg_3555;
ins_data_tmp_load_43_toint_fu_882_p1 <= ins_data_val43_reg_3560;
ins_data_tmp_load_44_toint_fu_885_p1 <= ins_data_val44_reg_3565;
ins_data_tmp_load_45_toint_fu_1122_p1 <= ins_data_val45_reg_3570;
ins_data_tmp_load_46_toint_fu_1125_p1 <= ins_data_val46_reg_3575;
ins_data_tmp_load_47_toint_fu_1128_p1 <= ins_data_val47_reg_3580;
ins_data_tmp_load_48_toint_fu_1131_p1 <= ins_data_val48_reg_3585;
ins_data_tmp_load_49_toint_fu_1134_p1 <= ins_data_val49_reg_3590;
ins_data_tmp_load_4_toint_fu_753_p1 <= reg_685;
ins_data_tmp_load_50_toint_fu_1137_p1 <= ins_data_val50_reg_3595;
ins_data_tmp_load_51_toint_fu_1140_p1 <= ins_data_val51_reg_3600;
ins_data_tmp_load_52_toint_fu_1143_p1 <= ins_data_val52_reg_3605;
ins_data_tmp_load_53_toint_fu_1146_p1 <= ins_data_val53_reg_3610;
ins_data_tmp_load_54_toint_fu_1149_p1 <= ins_data_val54_reg_3615;
ins_data_tmp_load_55_toint_fu_1152_p1 <= ins_data_val55_reg_3620;
ins_data_tmp_load_56_toint_fu_1155_p1 <= ins_data_val56_reg_3625;
ins_data_tmp_load_57_toint_fu_1158_p1 <= ins_data_val57_reg_3630;
ins_data_tmp_load_58_toint_fu_1161_p1 <= ins_data_val58_reg_3635;
ins_data_tmp_load_59_toint_fu_1164_p1 <= ins_data_val59_reg_3640;
ins_data_tmp_load_5_toint_fu_757_p1 <= reg_689;
ins_data_tmp_load_60_toint_fu_935_p1 <= ins_data_val60_reg_3645;
ins_data_tmp_load_61_toint_fu_938_p1 <= ins_data_val61_reg_3650;
ins_data_tmp_load_62_toint_fu_941_p1 <= ins_data_val62_reg_3655;
ins_data_tmp_load_63_toint_fu_944_p1 <= ins_data_val63_reg_3660;
ins_data_tmp_load_64_toint_fu_947_p1 <= ins_data_val64_reg_3665;
ins_data_tmp_load_65_toint_fu_950_p1 <= ins_data_val65_reg_3670;
ins_data_tmp_load_66_toint_fu_953_p1 <= ins_data_val66_reg_3675;
ins_data_tmp_load_67_toint_fu_956_p1 <= ins_data_val67_reg_3680;
ins_data_tmp_load_68_toint_fu_959_p1 <= ins_data_val68_reg_3685;
ins_data_tmp_load_69_toint_fu_962_p1 <= ins_data_val69_reg_3690;
ins_data_tmp_load_6_toint_fu_761_p1 <= reg_693;
ins_data_tmp_load_70_toint_fu_965_p1 <= ins_data_val70_reg_3695;
ins_data_tmp_load_71_toint_fu_968_p1 <= ins_data_val71_reg_3706;
ins_data_tmp_load_72_toint_fu_971_p1 <= reg_669;
ins_data_tmp_load_73_toint_fu_975_p1 <= reg_673;
ins_data_tmp_load_74_toint_fu_979_p1 <= ins_TDATA;
ins_data_tmp_load_75_toint_fu_1214_p1 <= reg_669;
ins_data_tmp_load_76_toint_fu_1218_p1 <= reg_673;
ins_data_tmp_load_77_toint_fu_1222_p1 <= reg_677;
ins_data_tmp_load_78_toint_fu_1226_p1 <= reg_681;
ins_data_tmp_load_79_toint_fu_1230_p1 <= reg_685;
ins_data_tmp_load_7_toint_fu_765_p1 <= reg_697;
ins_data_tmp_load_80_toint_fu_1234_p1 <= reg_689;
ins_data_tmp_load_81_toint_fu_1238_p1 <= reg_693;
ins_data_tmp_load_82_toint_fu_1242_p1 <= reg_697;
ins_data_tmp_load_83_toint_fu_1246_p1 <= reg_701;
ins_data_tmp_load_84_toint_fu_1250_p1 <= reg_705;
ins_data_tmp_load_85_toint_fu_1254_p1 <= reg_709;
ins_data_tmp_load_86_toint_fu_1258_p1 <= reg_713;
ins_data_tmp_load_87_toint_fu_1262_p1 <= reg_717;
ins_data_tmp_load_88_toint_fu_1266_p1 <= reg_721;
ins_data_tmp_load_89_toint_fu_1270_p1 <= ins_TDATA;
ins_data_tmp_load_8_toint_fu_769_p1 <= reg_701;
ins_data_tmp_load_90_toint_fu_1321_p1 <= reg_669;
ins_data_tmp_load_91_toint_fu_1325_p1 <= reg_673;
ins_data_tmp_load_92_toint_fu_1329_p1 <= reg_677;
ins_data_tmp_load_93_toint_fu_1333_p1 <= reg_681;
ins_data_tmp_load_94_toint_fu_1337_p1 <= reg_685;
ins_data_tmp_load_95_toint_fu_1341_p1 <= reg_689;
ins_data_tmp_load_96_toint_fu_1345_p1 <= reg_693;
ins_data_tmp_load_97_toint_fu_1349_p1 <= reg_697;
ins_data_tmp_load_98_toint_fu_1353_p1 <= reg_701;
ins_data_tmp_load_99_toint_fu_1357_p1 <= reg_705;
ins_data_tmp_load_9_toint_fu_773_p1 <= reg_705;
ins_data_tmp_load_toint_fu_737_p1 <= reg_669;
-- outs_TDATA assign process. --
outs_TDATA_assign_proc : process(ap_sig_cseq_ST_st386_fsm_302, ap_sig_cseq_ST_st389_fsm_305, ap_sig_cseq_ST_st392_fsm_308, ap_sig_cseq_ST_st395_fsm_311, ap_sig_cseq_ST_st398_fsm_314, ap_sig_cseq_ST_st401_fsm_317, ap_sig_cseq_ST_st404_fsm_320, ap_sig_cseq_ST_st407_fsm_323, ap_sig_cseq_ST_st410_fsm_326, ap_sig_cseq_ST_st413_fsm_329, ap_sig_cseq_ST_st416_fsm_332, ap_sig_cseq_ST_st419_fsm_335, ap_sig_cseq_ST_st422_fsm_338, ap_sig_cseq_ST_st425_fsm_341, ap_sig_cseq_ST_st428_fsm_344, ap_sig_cseq_ST_st431_fsm_347, ap_sig_cseq_ST_st434_fsm_350, ap_sig_cseq_ST_st437_fsm_353, ap_sig_cseq_ST_st440_fsm_356, ap_sig_cseq_ST_st443_fsm_359, t_load_fu_3115_p1, gamma_load_fu_3120_p1, ap_sig_cseq_ST_st387_fsm_303, beta_load_fu_3125_p1, ap_sig_cseq_ST_st388_fsm_304, t_load_s_fu_3130_p1, gamma_load_s_fu_3135_p1, ap_sig_cseq_ST_st390_fsm_306, beta_load_s_fu_3140_p1, ap_sig_cseq_ST_st391_fsm_307, t_load_1_fu_3145_p1, gamma_load_1_fu_3150_p1, ap_sig_cseq_ST_st393_fsm_309, beta_load_1_fu_3155_p1, ap_sig_cseq_ST_st394_fsm_310, t_load_2_fu_3160_p1, gamma_load_2_fu_3165_p1, ap_sig_cseq_ST_st396_fsm_312, beta_load_2_fu_3170_p1, ap_sig_cseq_ST_st397_fsm_313, t_load_3_fu_3175_p1, gamma_load_3_fu_3180_p1, ap_sig_cseq_ST_st399_fsm_315, beta_load_3_fu_3185_p1, ap_sig_cseq_ST_st400_fsm_316, t_load_4_fu_3190_p1, gamma_load_4_fu_3195_p1, ap_sig_cseq_ST_st402_fsm_318, beta_load_4_fu_3200_p1, ap_sig_cseq_ST_st403_fsm_319, t_load_5_fu_3205_p1, gamma_load_5_fu_3210_p1, ap_sig_cseq_ST_st405_fsm_321, beta_load_5_fu_3215_p1, ap_sig_cseq_ST_st406_fsm_322, t_load_6_fu_3220_p1, gamma_load_6_fu_3225_p1, ap_sig_cseq_ST_st408_fsm_324, beta_load_6_fu_3230_p1, ap_sig_cseq_ST_st409_fsm_325, t_load_7_fu_3235_p1, gamma_load_7_fu_3240_p1, ap_sig_cseq_ST_st411_fsm_327, beta_load_7_fu_3245_p1, ap_sig_cseq_ST_st412_fsm_328, t_load_8_fu_3250_p1, gamma_load_8_fu_3255_p1, ap_sig_cseq_ST_st414_fsm_330, beta_load_8_fu_3260_p1, ap_sig_cseq_ST_st415_fsm_331, t_load_9_fu_3265_p1, gamma_load_9_fu_3270_p1, ap_sig_cseq_ST_st417_fsm_333, beta_load_9_fu_3275_p1, ap_sig_cseq_ST_st418_fsm_334, t_load_10_fu_3280_p1, gamma_load_10_fu_3285_p1, ap_sig_cseq_ST_st420_fsm_336, beta_load_10_fu_3290_p1, ap_sig_cseq_ST_st421_fsm_337, t_load_11_fu_3295_p1, gamma_load_11_fu_3300_p1, ap_sig_cseq_ST_st423_fsm_339, beta_load_11_fu_3305_p1, ap_sig_cseq_ST_st424_fsm_340, t_load_12_fu_3310_p1, gamma_load_12_fu_3315_p1, ap_sig_cseq_ST_st426_fsm_342, beta_load_12_fu_3320_p1, ap_sig_cseq_ST_st427_fsm_343, t_load_13_fu_3325_p1, gamma_load_13_fu_3330_p1, ap_sig_cseq_ST_st429_fsm_345, beta_load_13_fu_3335_p1, ap_sig_cseq_ST_st430_fsm_346, t_load_14_fu_3340_p1, gamma_load_14_fu_3345_p1, ap_sig_cseq_ST_st432_fsm_348, beta_load_14_fu_3350_p1, ap_sig_cseq_ST_st433_fsm_349, t_load_15_fu_3355_p1, gamma_load_15_fu_3360_p1, ap_sig_cseq_ST_st435_fsm_351, beta_load_15_fu_3365_p1, ap_sig_cseq_ST_st436_fsm_352, t_load_16_fu_3370_p1, gamma_load_16_fu_3375_p1, ap_sig_cseq_ST_st438_fsm_354, beta_load_16_fu_3380_p1, ap_sig_cseq_ST_st439_fsm_355, t_load_17_fu_3385_p1, gamma_load_17_fu_3390_p1, ap_sig_cseq_ST_st441_fsm_357, beta_load_17_fu_3395_p1, ap_sig_cseq_ST_st442_fsm_358, t_load_18_fu_3400_p1, gamma_load_18_fu_3405_p1, ap_sig_cseq_ST_st444_fsm_360, beta_load_18_fu_3410_p1, ap_sig_cseq_ST_st445_fsm_361)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361)) then
outs_TDATA <= beta_load_18_fu_3410_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360)) then
outs_TDATA <= gamma_load_18_fu_3405_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359)) then
outs_TDATA <= t_load_18_fu_3400_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) then
outs_TDATA <= beta_load_17_fu_3395_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357)) then
outs_TDATA <= gamma_load_17_fu_3390_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356)) then
outs_TDATA <= t_load_17_fu_3385_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) then
outs_TDATA <= beta_load_16_fu_3380_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354)) then
outs_TDATA <= gamma_load_16_fu_3375_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353)) then
outs_TDATA <= t_load_16_fu_3370_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) then
outs_TDATA <= beta_load_15_fu_3365_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351)) then
outs_TDATA <= gamma_load_15_fu_3360_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350)) then
outs_TDATA <= t_load_15_fu_3355_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) then
outs_TDATA <= beta_load_14_fu_3350_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348)) then
outs_TDATA <= gamma_load_14_fu_3345_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347)) then
outs_TDATA <= t_load_14_fu_3340_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) then
outs_TDATA <= beta_load_13_fu_3335_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345)) then
outs_TDATA <= gamma_load_13_fu_3330_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344)) then
outs_TDATA <= t_load_13_fu_3325_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) then
outs_TDATA <= beta_load_12_fu_3320_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342)) then
outs_TDATA <= gamma_load_12_fu_3315_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341)) then
outs_TDATA <= t_load_12_fu_3310_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) then
outs_TDATA <= beta_load_11_fu_3305_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339)) then
outs_TDATA <= gamma_load_11_fu_3300_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338)) then
outs_TDATA <= t_load_11_fu_3295_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) then
outs_TDATA <= beta_load_10_fu_3290_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336)) then
outs_TDATA <= gamma_load_10_fu_3285_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335)) then
outs_TDATA <= t_load_10_fu_3280_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) then
outs_TDATA <= beta_load_9_fu_3275_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333)) then
outs_TDATA <= gamma_load_9_fu_3270_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332)) then
outs_TDATA <= t_load_9_fu_3265_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) then
outs_TDATA <= beta_load_8_fu_3260_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330)) then
outs_TDATA <= gamma_load_8_fu_3255_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329)) then
outs_TDATA <= t_load_8_fu_3250_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) then
outs_TDATA <= beta_load_7_fu_3245_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327)) then
outs_TDATA <= gamma_load_7_fu_3240_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326)) then
outs_TDATA <= t_load_7_fu_3235_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) then
outs_TDATA <= beta_load_6_fu_3230_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324)) then
outs_TDATA <= gamma_load_6_fu_3225_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323)) then
outs_TDATA <= t_load_6_fu_3220_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) then
outs_TDATA <= beta_load_5_fu_3215_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321)) then
outs_TDATA <= gamma_load_5_fu_3210_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320)) then
outs_TDATA <= t_load_5_fu_3205_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) then
outs_TDATA <= beta_load_4_fu_3200_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318)) then
outs_TDATA <= gamma_load_4_fu_3195_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317)) then
outs_TDATA <= t_load_4_fu_3190_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) then
outs_TDATA <= beta_load_3_fu_3185_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315)) then
outs_TDATA <= gamma_load_3_fu_3180_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314)) then
outs_TDATA <= t_load_3_fu_3175_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) then
outs_TDATA <= beta_load_2_fu_3170_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312)) then
outs_TDATA <= gamma_load_2_fu_3165_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311)) then
outs_TDATA <= t_load_2_fu_3160_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) then
outs_TDATA <= beta_load_1_fu_3155_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309)) then
outs_TDATA <= gamma_load_1_fu_3150_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308)) then
outs_TDATA <= t_load_1_fu_3145_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) then
outs_TDATA <= beta_load_s_fu_3140_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306)) then
outs_TDATA <= gamma_load_s_fu_3135_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305)) then
outs_TDATA <= t_load_s_fu_3130_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) then
outs_TDATA <= beta_load_fu_3125_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303)) then
outs_TDATA <= gamma_load_fu_3120_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302)) then
outs_TDATA <= t_load_fu_3115_p1;
else
outs_TDATA <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
outs_TDEST <= ins_dest_V_val_reg_3849;
outs_TID <= ins_id_V_val_reg_3844;
outs_TKEEP <= ins_keep_V_val_reg_3824;
-- outs_TLAST assign process. --
outs_TLAST_assign_proc : process(ap_sig_cseq_ST_st386_fsm_302, ap_sig_cseq_ST_st389_fsm_305, ap_sig_cseq_ST_st392_fsm_308, ap_sig_cseq_ST_st395_fsm_311, ap_sig_cseq_ST_st398_fsm_314, ap_sig_cseq_ST_st401_fsm_317, ap_sig_cseq_ST_st404_fsm_320, ap_sig_cseq_ST_st407_fsm_323, ap_sig_cseq_ST_st410_fsm_326, ap_sig_cseq_ST_st413_fsm_329, ap_sig_cseq_ST_st416_fsm_332, ap_sig_cseq_ST_st419_fsm_335, ap_sig_cseq_ST_st422_fsm_338, ap_sig_cseq_ST_st425_fsm_341, ap_sig_cseq_ST_st428_fsm_344, ap_sig_cseq_ST_st431_fsm_347, ap_sig_cseq_ST_st434_fsm_350, ap_sig_cseq_ST_st437_fsm_353, ap_sig_cseq_ST_st440_fsm_356, ap_sig_cseq_ST_st443_fsm_359, ins_last_V_val_reg_3839, ap_sig_cseq_ST_st387_fsm_303, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st390_fsm_306, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st393_fsm_309, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st396_fsm_312, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st399_fsm_315, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st402_fsm_318, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st405_fsm_321, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st408_fsm_324, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st411_fsm_327, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st414_fsm_330, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st417_fsm_333, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st420_fsm_336, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st423_fsm_339, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st426_fsm_342, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st429_fsm_345, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st432_fsm_348, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st435_fsm_351, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st438_fsm_354, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st441_fsm_357, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st444_fsm_360, ap_sig_cseq_ST_st445_fsm_361)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361)) then
outs_TLAST <= ins_last_V_val_reg_3839;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) or (ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305) or (ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308) or (ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311) or (ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314) or (ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317) or (ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320) or (ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323) or (ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326) or (ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329) or (ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332) or (ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335) or (ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338) or (ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341) or (ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344) or (ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347) or (ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350) or (ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353) or (ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356) or (ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359) or (ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303) or (ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304) or (ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306) or (ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307) or (ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309) or (ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310) or (ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312) or (ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313) or (ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315) or (ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316) or (ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318) or (ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319) or (ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321) or (ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322) or (ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324) or (ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325) or (ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327) or (ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328) or (ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330) or (ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331) or (ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333) or (ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334) or (ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336) or (ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337) or (ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339) or (ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340) or (ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342) or (ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343) or (ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345) or (ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346) or (ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348) or (ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349) or (ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351) or (ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352) or (ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354) or (ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355) or (ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357) or (ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358) or (ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360))) then
outs_TLAST <= ap_const_lv1_0;
else
outs_TLAST <= "X";
end if;
end process;
outs_TSTRB <= ins_strb_V_val_reg_3829;
outs_TUSER <= ins_user_V_val_reg_3834;
-- outs_TVALID assign process. --
outs_TVALID_assign_proc : process(ap_sig_cseq_ST_st386_fsm_302, ap_sig_cseq_ST_st389_fsm_305, ap_sig_cseq_ST_st392_fsm_308, ap_sig_cseq_ST_st395_fsm_311, ap_sig_cseq_ST_st398_fsm_314, ap_sig_cseq_ST_st401_fsm_317, ap_sig_cseq_ST_st404_fsm_320, ap_sig_cseq_ST_st407_fsm_323, ap_sig_cseq_ST_st410_fsm_326, ap_sig_cseq_ST_st413_fsm_329, ap_sig_cseq_ST_st416_fsm_332, ap_sig_cseq_ST_st419_fsm_335, ap_sig_cseq_ST_st422_fsm_338, ap_sig_cseq_ST_st425_fsm_341, ap_sig_cseq_ST_st428_fsm_344, ap_sig_cseq_ST_st431_fsm_347, ap_sig_cseq_ST_st434_fsm_350, ap_sig_cseq_ST_st437_fsm_353, ap_sig_cseq_ST_st440_fsm_356, ap_sig_cseq_ST_st443_fsm_359, ap_sig_cseq_ST_st387_fsm_303, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st390_fsm_306, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st393_fsm_309, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st396_fsm_312, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st399_fsm_315, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st402_fsm_318, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st405_fsm_321, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st408_fsm_324, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st411_fsm_327, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st414_fsm_330, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st417_fsm_333, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st420_fsm_336, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st423_fsm_339, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st426_fsm_342, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st429_fsm_345, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st432_fsm_348, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st435_fsm_351, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st438_fsm_354, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st441_fsm_357, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st444_fsm_360, ap_sig_cseq_ST_st445_fsm_361, ap_reg_ioackin_outs_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)))) then
outs_TVALID <= ap_const_logic_1;
else
outs_TVALID <= ap_const_logic_0;
end if;
end process;
rez_addr959960_part_set_fu_830_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_fu_796_p16);
rez_addr_10932933_part_set_fu_1736_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_10_fu_1702_p16);
rez_addr_11929930_part_set_fu_1843_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_11_fu_1809_p16);
rez_addr_12926927_part_set_fu_1950_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_12_fu_1916_p16);
rez_addr_13923924_part_set_fu_2057_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_13_fu_2023_p16);
rez_addr_14920921_part_set_fu_2164_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_14_fu_2130_p16);
rez_addr_15917918_part_set_fu_2271_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_15_fu_2237_p16);
rez_addr_16914915_part_set_fu_2378_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_16_fu_2344_p16);
rez_addr_17911912_part_set_fu_2485_p5 <= (reg_725(575 downto 480) & tmp_17_fu_2451_p16);
rez_addr_18908909_part_set_fu_2592_p5 <= (data_array_load_1_reg_3743(575 downto 480) & tmp_18_fu_2558_p16);
rez_addr_1956957_part_set_fu_1109_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_2_fu_1075_p16);
rez_addr_19905906_part_set_fu_2698_p5 <= (data_array_load_2_reg_3722(575 downto 480) & tmp_19_fu_2664_p16);
rez_addr_20902903_part_set_fu_2828_p5 <= (data_array_load_3_reg_3759(575 downto 480) & tmp_20_fu_2794_p16);
rez_addr_3953954_part_set_fu_922_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_3_fu_888_p16);
rez_addr_4950951_part_set_fu_1201_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_4_fu_1167_p16);
rez_addr_5947948_part_set_fu_1017_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_5_fu_983_p16);
rez_addr_6944945_part_set_fu_1308_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_6_fu_1274_p16);
rez_addr_7941942_part_set_fu_1415_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_7_fu_1381_p16);
rez_addr_8938939_part_set_fu_1522_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_8_fu_1488_p16);
rez_addr_9935936_part_set_fu_1629_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_9_fu_1595_p16);
t_load_10_fu_3280_p1 <= grp_fu_639_p4;
t_load_11_fu_3295_p1 <= grp_fu_639_p4;
t_load_12_fu_3310_p1 <= grp_fu_639_p4;
t_load_13_fu_3325_p1 <= grp_fu_639_p4;
t_load_14_fu_3340_p1 <= grp_fu_639_p4;
t_load_15_fu_3355_p1 <= grp_fu_639_p4;
t_load_16_fu_3370_p1 <= grp_fu_639_p4;
t_load_17_fu_3385_p1 <= grp_fu_639_p4;
t_load_18_fu_3400_p1 <= grp_fu_639_p4;
t_load_1_fu_3145_p1 <= grp_fu_639_p4;
t_load_2_fu_3160_p1 <= grp_fu_639_p4;
t_load_3_fu_3175_p1 <= grp_fu_639_p4;
t_load_4_fu_3190_p1 <= grp_fu_639_p4;
t_load_5_fu_3205_p1 <= grp_fu_639_p4;
t_load_6_fu_3220_p1 <= grp_fu_639_p4;
t_load_7_fu_3235_p1 <= grp_fu_639_p4;
t_load_8_fu_3250_p1 <= grp_fu_639_p4;
t_load_9_fu_3265_p1 <= grp_fu_639_p4;
t_load_fu_3115_p1 <= grp_fu_639_p4;
t_load_s_fu_3130_p1 <= grp_fu_639_p4;
t_write_assign_toint_fu_3081_p1 <= grp_fu_618_p2;
tmp_10_fu_1702_p16 <= ((((((((((((((ins_data_tmp_load_149_toint_fu_1698_p1 & ins_data_tmp_load_148_toint_fu_1694_p1) & ins_data_tmp_load_147_toint_fu_1690_p1) & ins_data_tmp_load_146_toint_fu_1686_p1) & ins_data_tmp_load_145_toint_fu_1682_p1) & ins_data_tmp_load_144_toint_fu_1678_p1) & ins_data_tmp_load_143_toint_fu_1674_p1) & ins_data_tmp_load_142_toint_fu_1670_p1) & ins_data_tmp_load_141_toint_fu_1666_p1) & ins_data_tmp_load_140_toint_fu_1662_p1) & ins_data_tmp_load_139_toint_fu_1658_p1) & ins_data_tmp_load_138_toint_fu_1654_p1) & ins_data_tmp_load_137_toint_fu_1650_p1) & ins_data_tmp_load_136_toint_fu_1646_p1) & ins_data_tmp_load_135_toint_fu_1642_p1);
tmp_11_fu_1809_p16 <= ((((((((((((((ins_data_tmp_load_164_toint_fu_1805_p1 & ins_data_tmp_load_163_toint_fu_1801_p1) & ins_data_tmp_load_162_toint_fu_1797_p1) & ins_data_tmp_load_161_toint_fu_1793_p1) & ins_data_tmp_load_160_toint_fu_1789_p1) & ins_data_tmp_load_159_toint_fu_1785_p1) & ins_data_tmp_load_158_toint_fu_1781_p1) & ins_data_tmp_load_157_toint_fu_1777_p1) & ins_data_tmp_load_156_toint_fu_1773_p1) & ins_data_tmp_load_155_toint_fu_1769_p1) & ins_data_tmp_load_154_toint_fu_1765_p1) & ins_data_tmp_load_153_toint_fu_1761_p1) & ins_data_tmp_load_152_toint_fu_1757_p1) & ins_data_tmp_load_151_toint_fu_1753_p1) & ins_data_tmp_load_150_toint_fu_1749_p1);
tmp_12_fu_1916_p16 <= ((((((((((((((ins_data_tmp_load_179_toint_fu_1912_p1 & ins_data_tmp_load_178_toint_fu_1908_p1) & ins_data_tmp_load_177_toint_fu_1904_p1) & ins_data_tmp_load_176_toint_fu_1900_p1) & ins_data_tmp_load_175_toint_fu_1896_p1) & ins_data_tmp_load_174_toint_fu_1892_p1) & ins_data_tmp_load_173_toint_fu_1888_p1) & ins_data_tmp_load_172_toint_fu_1884_p1) & ins_data_tmp_load_171_toint_fu_1880_p1) & ins_data_tmp_load_170_toint_fu_1876_p1) & ins_data_tmp_load_169_toint_fu_1872_p1) & ins_data_tmp_load_168_toint_fu_1868_p1) & ins_data_tmp_load_167_toint_fu_1864_p1) & ins_data_tmp_load_166_toint_fu_1860_p1) & ins_data_tmp_load_165_toint_fu_1856_p1);
tmp_13_fu_2023_p16 <= ((((((((((((((ins_data_tmp_load_194_toint_fu_2019_p1 & ins_data_tmp_load_193_toint_fu_2015_p1) & ins_data_tmp_load_192_toint_fu_2011_p1) & ins_data_tmp_load_191_toint_fu_2007_p1) & ins_data_tmp_load_190_toint_fu_2003_p1) & ins_data_tmp_load_189_toint_fu_1999_p1) & ins_data_tmp_load_188_toint_fu_1995_p1) & ins_data_tmp_load_187_toint_fu_1991_p1) & ins_data_tmp_load_186_toint_fu_1987_p1) & ins_data_tmp_load_185_toint_fu_1983_p1) & ins_data_tmp_load_184_toint_fu_1979_p1) & ins_data_tmp_load_183_toint_fu_1975_p1) & ins_data_tmp_load_182_toint_fu_1971_p1) & ins_data_tmp_load_181_toint_fu_1967_p1) & ins_data_tmp_load_180_toint_fu_1963_p1);
tmp_14_fu_2130_p16 <= ((((((((((((((ins_data_tmp_load_209_toint_fu_2126_p1 & ins_data_tmp_load_208_toint_fu_2122_p1) & ins_data_tmp_load_207_toint_fu_2118_p1) & ins_data_tmp_load_206_toint_fu_2114_p1) & ins_data_tmp_load_205_toint_fu_2110_p1) & ins_data_tmp_load_204_toint_fu_2106_p1) & ins_data_tmp_load_203_toint_fu_2102_p1) & ins_data_tmp_load_202_toint_fu_2098_p1) & ins_data_tmp_load_201_toint_fu_2094_p1) & ins_data_tmp_load_200_toint_fu_2090_p1) & ins_data_tmp_load_199_toint_fu_2086_p1) & ins_data_tmp_load_198_toint_fu_2082_p1) & ins_data_tmp_load_197_toint_fu_2078_p1) & ins_data_tmp_load_196_toint_fu_2074_p1) & ins_data_tmp_load_195_toint_fu_2070_p1);
tmp_15_fu_2237_p16 <= ((((((((((((((ins_data_tmp_load_224_toint_fu_2233_p1 & ins_data_tmp_load_223_toint_fu_2229_p1) & ins_data_tmp_load_222_toint_fu_2225_p1) & ins_data_tmp_load_221_toint_fu_2221_p1) & ins_data_tmp_load_220_toint_fu_2217_p1) & ins_data_tmp_load_219_toint_fu_2213_p1) & ins_data_tmp_load_218_toint_fu_2209_p1) & ins_data_tmp_load_217_toint_fu_2205_p1) & ins_data_tmp_load_216_toint_fu_2201_p1) & ins_data_tmp_load_215_toint_fu_2197_p1) & ins_data_tmp_load_214_toint_fu_2193_p1) & ins_data_tmp_load_213_toint_fu_2189_p1) & ins_data_tmp_load_212_toint_fu_2185_p1) & ins_data_tmp_load_211_toint_fu_2181_p1) & ins_data_tmp_load_210_toint_fu_2177_p1);
tmp_16_fu_2344_p16 <= ((((((((((((((ins_data_tmp_load_239_toint_fu_2340_p1 & ins_data_tmp_load_238_toint_fu_2336_p1) & ins_data_tmp_load_237_toint_fu_2332_p1) & ins_data_tmp_load_236_toint_fu_2328_p1) & ins_data_tmp_load_235_toint_fu_2324_p1) & ins_data_tmp_load_234_toint_fu_2320_p1) & ins_data_tmp_load_233_toint_fu_2316_p1) & ins_data_tmp_load_232_toint_fu_2312_p1) & ins_data_tmp_load_231_toint_fu_2308_p1) & ins_data_tmp_load_230_toint_fu_2304_p1) & ins_data_tmp_load_229_toint_fu_2300_p1) & ins_data_tmp_load_228_toint_fu_2296_p1) & ins_data_tmp_load_227_toint_fu_2292_p1) & ins_data_tmp_load_226_toint_fu_2288_p1) & ins_data_tmp_load_225_toint_fu_2284_p1);
tmp_17_fu_2451_p16 <= ((((((((((((((ins_data_tmp_load_254_toint_fu_2447_p1 & ins_data_tmp_load_253_toint_fu_2443_p1) & ins_data_tmp_load_252_toint_fu_2439_p1) & ins_data_tmp_load_251_toint_fu_2435_p1) & ins_data_tmp_load_250_toint_fu_2431_p1) & ins_data_tmp_load_249_toint_fu_2427_p1) & ins_data_tmp_load_248_toint_fu_2423_p1) & ins_data_tmp_load_247_toint_fu_2419_p1) & ins_data_tmp_load_246_toint_fu_2415_p1) & ins_data_tmp_load_245_toint_fu_2411_p1) & ins_data_tmp_load_244_toint_fu_2407_p1) & ins_data_tmp_load_243_toint_fu_2403_p1) & ins_data_tmp_load_242_toint_fu_2399_p1) & ins_data_tmp_load_241_toint_fu_2395_p1) & ins_data_tmp_load_240_toint_fu_2391_p1);
tmp_18_fu_2558_p16 <= ((((((((((((((ins_data_tmp_load_269_toint_fu_2554_p1 & ins_data_tmp_load_268_toint_fu_2550_p1) & ins_data_tmp_load_267_toint_fu_2546_p1) & ins_data_tmp_load_266_toint_fu_2542_p1) & ins_data_tmp_load_265_toint_fu_2538_p1) & ins_data_tmp_load_264_toint_fu_2534_p1) & ins_data_tmp_load_263_toint_fu_2530_p1) & ins_data_tmp_load_262_toint_fu_2526_p1) & ins_data_tmp_load_261_toint_fu_2522_p1) & ins_data_tmp_load_260_toint_fu_2518_p1) & ins_data_tmp_load_259_toint_fu_2514_p1) & ins_data_tmp_load_258_toint_fu_2510_p1) & ins_data_tmp_load_257_toint_fu_2506_p1) & ins_data_tmp_load_256_toint_fu_2502_p1) & ins_data_tmp_load_255_toint_fu_2498_p1);
tmp_19_fu_2664_p16 <= ((((((((((((((ins_data_tmp_load_284_toint_fu_2660_p1 & ins_data_tmp_load_283_toint_fu_2656_p1) & ins_data_tmp_load_282_toint_fu_2652_p1) & ins_data_tmp_load_281_toint_fu_2648_p1) & ins_data_tmp_load_280_toint_fu_2644_p1) & ins_data_tmp_load_279_toint_fu_2640_p1) & ins_data_tmp_load_278_toint_fu_2636_p1) & ins_data_tmp_load_277_toint_fu_2632_p1) & ins_data_tmp_load_276_toint_fu_2628_p1) & ins_data_tmp_load_275_toint_fu_2624_p1) & ins_data_tmp_load_274_toint_fu_2620_p1) & ins_data_tmp_load_273_toint_fu_2616_p1) & ins_data_tmp_load_272_toint_fu_2612_p1) & ins_data_tmp_load_271_toint_fu_2608_p1) & ins_data_tmp_load_270_toint_fu_2604_p1);
tmp_1_fu_2852_p1 <= std_logic_vector(resize(unsigned(i1_reg_418),64));
tmp_20_fu_2794_p16 <= ((((((((((((((ins_data_tmp_load_299_toint_fu_2790_p1 & ins_data_tmp_load_298_toint_fu_2762_p1) & ins_data_tmp_load_297_toint_fu_2758_p1) & ins_data_tmp_load_296_toint_fu_2754_p1) & ins_data_tmp_load_295_toint_fu_2750_p1) & ins_data_tmp_load_294_toint_fu_2746_p1) & ins_data_tmp_load_293_toint_fu_2742_p1) & ins_data_tmp_load_292_toint_fu_2738_p1) & ins_data_tmp_load_291_toint_fu_2734_p1) & ins_data_tmp_load_290_toint_fu_2730_p1) & ins_data_tmp_load_289_toint_fu_2726_p1) & ins_data_tmp_load_288_toint_fu_2722_p1) & ins_data_tmp_load_287_toint_fu_2718_p1) & ins_data_tmp_load_286_toint_fu_2714_p1) & ins_data_tmp_load_285_toint_fu_2710_p1);
tmp_21_fu_3093_p4 <= ((beta_write_assign_toint_fu_3089_p1 & gamma_write_assign_toint_fu_3085_p1) & t_write_assign_toint_fu_3081_p1);
tmp_22_fu_2857_p1 <= data_array_q0(32 - 1 downto 0);
tmp_2_fu_1075_p16 <= ((((((((((((((ins_data_tmp_load_29_toint_fu_1072_p1 & ins_data_tmp_load_28_toint_fu_1069_p1) & ins_data_tmp_load_27_toint_fu_1066_p1) & ins_data_tmp_load_26_toint_fu_1063_p1) & ins_data_tmp_load_25_toint_fu_1060_p1) & ins_data_tmp_load_24_toint_fu_1057_p1) & ins_data_tmp_load_23_toint_fu_1054_p1) & ins_data_tmp_load_22_toint_fu_1051_p1) & ins_data_tmp_load_21_toint_fu_1048_p1) & ins_data_tmp_load_20_toint_fu_1045_p1) & ins_data_tmp_load_19_toint_fu_1042_p1) & ins_data_tmp_load_18_toint_fu_1039_p1) & ins_data_tmp_load_17_toint_fu_1036_p1) & ins_data_tmp_load_16_toint_fu_1033_p1) & ins_data_tmp_load_15_toint_fu_1030_p1);
tmp_3_fu_888_p16 <= ((((((((((((((ins_data_tmp_load_44_toint_fu_885_p1 & ins_data_tmp_load_43_toint_fu_882_p1) & ins_data_tmp_load_42_toint_fu_879_p1) & ins_data_tmp_load_41_toint_fu_876_p1) & ins_data_tmp_load_40_toint_fu_873_p1) & ins_data_tmp_load_39_toint_fu_870_p1) & ins_data_tmp_load_38_toint_fu_867_p1) & ins_data_tmp_load_37_toint_fu_864_p1) & ins_data_tmp_load_36_toint_fu_861_p1) & ins_data_tmp_load_35_toint_fu_858_p1) & ins_data_tmp_load_34_toint_fu_855_p1) & ins_data_tmp_load_33_toint_fu_852_p1) & ins_data_tmp_load_32_toint_fu_849_p1) & ins_data_tmp_load_31_toint_fu_846_p1) & ins_data_tmp_load_30_toint_fu_843_p1);
tmp_4_fu_1167_p16 <= ((((((((((((((ins_data_tmp_load_59_toint_fu_1164_p1 & ins_data_tmp_load_58_toint_fu_1161_p1) & ins_data_tmp_load_57_toint_fu_1158_p1) & ins_data_tmp_load_56_toint_fu_1155_p1) & ins_data_tmp_load_55_toint_fu_1152_p1) & ins_data_tmp_load_54_toint_fu_1149_p1) & ins_data_tmp_load_53_toint_fu_1146_p1) & ins_data_tmp_load_52_toint_fu_1143_p1) & ins_data_tmp_load_51_toint_fu_1140_p1) & ins_data_tmp_load_50_toint_fu_1137_p1) & ins_data_tmp_load_49_toint_fu_1134_p1) & ins_data_tmp_load_48_toint_fu_1131_p1) & ins_data_tmp_load_47_toint_fu_1128_p1) & ins_data_tmp_load_46_toint_fu_1125_p1) & ins_data_tmp_load_45_toint_fu_1122_p1);
tmp_5_fu_983_p16 <= ((((((((((((((ins_data_tmp_load_74_toint_fu_979_p1 & ins_data_tmp_load_73_toint_fu_975_p1) & ins_data_tmp_load_72_toint_fu_971_p1) & ins_data_tmp_load_71_toint_fu_968_p1) & ins_data_tmp_load_70_toint_fu_965_p1) & ins_data_tmp_load_69_toint_fu_962_p1) & ins_data_tmp_load_68_toint_fu_959_p1) & ins_data_tmp_load_67_toint_fu_956_p1) & ins_data_tmp_load_66_toint_fu_953_p1) & ins_data_tmp_load_65_toint_fu_950_p1) & ins_data_tmp_load_64_toint_fu_947_p1) & ins_data_tmp_load_63_toint_fu_944_p1) & ins_data_tmp_load_62_toint_fu_941_p1) & ins_data_tmp_load_61_toint_fu_938_p1) & ins_data_tmp_load_60_toint_fu_935_p1);
tmp_61_neg_i_fu_3071_p2 <= (tmp_61_to_int_i_fu_3068_p1 xor ap_const_lv32_80000000);
tmp_61_to_int_i_fu_3068_p1 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76;
tmp_6_fu_1274_p16 <= ((((((((((((((ins_data_tmp_load_89_toint_fu_1270_p1 & ins_data_tmp_load_88_toint_fu_1266_p1) & ins_data_tmp_load_87_toint_fu_1262_p1) & ins_data_tmp_load_86_toint_fu_1258_p1) & ins_data_tmp_load_85_toint_fu_1254_p1) & ins_data_tmp_load_84_toint_fu_1250_p1) & ins_data_tmp_load_83_toint_fu_1246_p1) & ins_data_tmp_load_82_toint_fu_1242_p1) & ins_data_tmp_load_81_toint_fu_1238_p1) & ins_data_tmp_load_80_toint_fu_1234_p1) & ins_data_tmp_load_79_toint_fu_1230_p1) & ins_data_tmp_load_78_toint_fu_1226_p1) & ins_data_tmp_load_77_toint_fu_1222_p1) & ins_data_tmp_load_76_toint_fu_1218_p1) & ins_data_tmp_load_75_toint_fu_1214_p1);
tmp_7_fu_1381_p16 <= ((((((((((((((ins_data_tmp_load_104_toint_fu_1377_p1 & ins_data_tmp_load_103_toint_fu_1373_p1) & ins_data_tmp_load_102_toint_fu_1369_p1) & ins_data_tmp_load_101_toint_fu_1365_p1) & ins_data_tmp_load_100_toint_fu_1361_p1) & ins_data_tmp_load_99_toint_fu_1357_p1) & ins_data_tmp_load_98_toint_fu_1353_p1) & ins_data_tmp_load_97_toint_fu_1349_p1) & ins_data_tmp_load_96_toint_fu_1345_p1) & ins_data_tmp_load_95_toint_fu_1341_p1) & ins_data_tmp_load_94_toint_fu_1337_p1) & ins_data_tmp_load_93_toint_fu_1333_p1) & ins_data_tmp_load_92_toint_fu_1329_p1) & ins_data_tmp_load_91_toint_fu_1325_p1) & ins_data_tmp_load_90_toint_fu_1321_p1);
tmp_8_fu_1488_p16 <= ((((((((((((((ins_data_tmp_load_119_toint_fu_1484_p1 & ins_data_tmp_load_118_toint_fu_1480_p1) & ins_data_tmp_load_117_toint_fu_1476_p1) & ins_data_tmp_load_116_toint_fu_1472_p1) & ins_data_tmp_load_115_toint_fu_1468_p1) & ins_data_tmp_load_114_toint_fu_1464_p1) & ins_data_tmp_load_113_toint_fu_1460_p1) & ins_data_tmp_load_112_toint_fu_1456_p1) & ins_data_tmp_load_111_toint_fu_1452_p1) & ins_data_tmp_load_110_toint_fu_1448_p1) & ins_data_tmp_load_109_toint_fu_1444_p1) & ins_data_tmp_load_108_toint_fu_1440_p1) & ins_data_tmp_load_107_toint_fu_1436_p1) & ins_data_tmp_load_106_toint_fu_1432_p1) & ins_data_tmp_load_105_toint_fu_1428_p1);
tmp_9_fu_1595_p16 <= ((((((((((((((ins_data_tmp_load_134_toint_fu_1591_p1 & ins_data_tmp_load_133_toint_fu_1587_p1) & ins_data_tmp_load_132_toint_fu_1583_p1) & ins_data_tmp_load_131_toint_fu_1579_p1) & ins_data_tmp_load_130_toint_fu_1575_p1) & ins_data_tmp_load_129_toint_fu_1571_p1) & ins_data_tmp_load_128_toint_fu_1567_p1) & ins_data_tmp_load_127_toint_fu_1563_p1) & ins_data_tmp_load_126_toint_fu_1559_p1) & ins_data_tmp_load_125_toint_fu_1555_p1) & ins_data_tmp_load_124_toint_fu_1551_p1) & ins_data_tmp_load_123_toint_fu_1547_p1) & ins_data_tmp_load_122_toint_fu_1543_p1) & ins_data_tmp_load_121_toint_fu_1539_p1) & ins_data_tmp_load_120_toint_fu_1535_p1);
tmp_fu_796_p16 <= ((((((((((((((ins_data_tmp_load_14_toint_fu_793_p1 & ins_data_tmp_load_13_toint_fu_789_p1) & ins_data_tmp_load_12_toint_fu_785_p1) & ins_data_tmp_load_11_toint_fu_781_p1) & ins_data_tmp_load_10_toint_fu_777_p1) & ins_data_tmp_load_9_toint_fu_773_p1) & ins_data_tmp_load_8_toint_fu_769_p1) & ins_data_tmp_load_7_toint_fu_765_p1) & ins_data_tmp_load_6_toint_fu_761_p1) & ins_data_tmp_load_5_toint_fu_757_p1) & ins_data_tmp_load_4_toint_fu_753_p1) & ins_data_tmp_load_3_toint_fu_749_p1) & ins_data_tmp_load_2_toint_fu_745_p1) & ins_data_tmp_load_1_toint_fu_741_p1) & ins_data_tmp_load_toint_fu_737_p1);
v0x_assign4_fu_3001_p1 <= tmp_22_reg_3869;
v0y_assign_fu_3007_p1 <= v0y_assign_new_reg_3874;
v0z_assign_fu_3013_p1 <= v0z_assign_new_reg_3879;
end behav;
| mit |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fmul_3_max_dsp_32/sim/tri_intersect_ap_fmul_3_max_dsp_32.vhd | 1 | 10719 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fmul_3_max_dsp_32;
ARCHITECTURE tri_intersect_ap_fmul_3_max_dsp_32_arch OF tri_intersect_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fmul_3_max_dsp_32_arch;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_s2mm_cmdsts_if.vhd | 1 | 22870 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_cmdsts_if is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_ENABLE_QUEUE : integer range 0 to 1 := 1
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : out std_logic ; --
--
s2mm_packet_eof : out std_logic ; --
--
s2mm_sts_received_clr : in std_logic ; --
s2mm_sts_received : out std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8)-1 downto 0); --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
s2mm_brcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_done : out std_logic ; --
s2mm_error : out std_logic ; --
s2mm_interr : out std_logic ; --
s2mm_slverr : out std_logic ; --
s2mm_decerr : out std_logic ; --
s2mm_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_s2mm_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal s2mm_slverr_i : std_logic := '0';
signal s2mm_decerr_i : std_logic := '0';
signal s2mm_interr_i : std_logic := '0';
signal s2mm_error_or : std_logic := '0';
signal s2mm_packet_eof_i : std_logic := '0';
signal smpl_dma_overflow : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s2mm_slverr <= s2mm_slverr_i;
s2mm_decerr <= s2mm_decerr_i;
s2mm_interr <= s2mm_interr_i or smpl_dma_overflow;
s2mm_packet_eof <= s2mm_packet_eof_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when s2mm_desc_cmplt = '1' and s2mm_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_HOLD_NO_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
-- s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
end generate GEN_HOLD_NO_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
elsif(sts_tready = '1' and m_axis_s2mm_sts_tvalid = '1')then
sts_tready <= '0';
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_s2mm_sts_tready <= sts_tready;
log_status <= '1' when m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0'
else '0';
-- Status stream is included, and using the rxlength from the status stream and in Scatter Gather Mode
DETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_SG_USE_STSAPP_LENGTH = 1
and C_INCLUDE_SG = 1) or (C_MICRO_DMA = 1) generate
begin
-- Bytes received not available in determinate byte mode
s2mm_brcvd <= (others => '0');
-- Simple DMA overflow not used in Scatter Gather Mode
smpl_dma_overflow <= '0';
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on status received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGEOF_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
end generate DETERMINATE_BTT_MODE;
-- No Status Stream or not using rxlength from status stream or in Simple DMA Mode
INDETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_SG_USE_STSAPP_LENGTH = 0
or C_INCLUDE_SG = 0) and (C_MICRO_DMA = 0) generate
-- Bytes received MSB index bit
constant BRCVD_MSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - C_SG_LENGTH_WIDTH);
-- Bytes received LSB index bit
constant BRCVD_LSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - 1);
begin
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_brcvd <= m_axis_s2mm_sts_tdata(BRCVD_MSB_BIT downto BRCVD_LSB_BIT);
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on statis received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
-- If in Simple DMA mode then generate overflow flag
GEN_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 0 generate
REG_OVERFLOW : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_dma_overflow <= '0';
-- If status received and TLAST bit is NOT set then packet is bigger than
-- BTT value commanded which is an invalid command
elsif(log_status = '1' and m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT) = '0')then
smpl_dma_overflow <= '1';
end if;
end if;
end process REG_OVERFLOW;
end generate GEN_OVERFLOW_SMPL_DMA;
-- If in Scatter Gather Mode then do NOT generate simple dma mode overflow flag
GEN_NO_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 1 generate
begin
smpl_dma_overflow <= '0';
end generate GEN_NO_OVERFLOW_SMPL_DMA;
end generate INDETERMINATE_BTT_MODE;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
s2mm_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error_or <= s2mm_slverr_i or s2mm_decerr_i or s2mm_interr_i or smpl_dma_overflow;
-- Log errors into a global error output
S2MM_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((s2mm_error_or = '1')
or (stale_desc = '1' and s2mm_cmnd_wr='1'))then
s2mm_error <= '1';
end if;
end if;
end process S2MM_ERROR_PROCESS;
end implementation;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_rst_processing_system7_0_100M_0/synth/triangle_intersect_rst_processing_system7_0_100M_0.vhd | 1 | 6938 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY triangle_intersect_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END triangle_intersect_rst_processing_system7_0_100M_0;
ARCHITECTURE triangle_intersect_rst_processing_system7_0_100M_0_arch OF triangle_intersect_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF triangle_intersect_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "triangle_intersect_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "triangle_intersect_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END triangle_intersect_rst_processing_system7_0_100M_0_arch;
| mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/lib_fifo_v1_0/259791c0/hdl/src/vhdl/sync_fifo_fg.vhd | 7 | 69796 | -- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
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-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
| mit |
herenvarno/dlx | dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.core/a.b.a.a-Adder.core/a.b.a.a.a-P4Adder.vhd | 1 | 2069 | --------------------------------------------------------------------------------
-- FILE: P4Adder
-- DESC: The Adder used in P4 micro-processor
--
-- Author:
-- Create: 2015-05-27
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity P4Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE;
SPARSITY : integer := C_ADD_SPARSITY
);
port(
cin : in std_logic;
a, b : in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout : out std_logic
);
end P4Adder;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture p4_adder_arch of P4Adder is
component P4CarryGenerator is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE;
SPARSITY: integer := C_ADD_SPARSITY
);
port(
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
cin: in std_logic;
cout: out std_logic_vector(DATA_SIZE/SPARSITY-1 downto 0)
);
end component;
component AdderSumGenerator is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
SPARSITY : integer := C_ADD_SPARSITY
);
port (
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
cin: in std_logic_vector(DATA_SIZE/SPARSITY-1 downto 0);
sum: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
signal carry : std_logic_vector(DATA_SIZE/SPARSITY downto 0);
begin
carry(0) <= cin;
CG0: P4CarryGenerator
generic map (DATA_SIZE, SPARSITY)
port map(a, b, cin, carry(DATA_SIZE/SPARSITY downto 1));
SG0: AdderSumGenerator
generic map (DATA_SIZE, SPARSITY)
port map(a, b, carry(DATA_SIZE/SPARSITY-1 downto 0), s);
cout <= carry(DATA_SIZE/SPARSITY);
end p4_adder_arch;
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/Mibench/firmware/outputs/ram_image.vhd | 1 | 181522 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafaf2708000c4034241400ac373c343c343c373c00100010",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f000cafafafafafafafafafafafafafafafaf",
INIT_02 => X"afafafaf03af270003278f0303af2740034034278f8f8f8f8f8f8f8f8f8f8f8f",
INIT_03 => X"8faf0030008faf008c343caf0014248faf00008faf008c343c0014248c3cac3c",
INIT_04 => X"afafaf00008f8faf00008faf00008faf008c343caf30008faf008c343c001000",
INIT_05 => X"af240014008f0000008faf00008c0024003c8faf30008c0024003c8fafaf0008",
INIT_06 => X"0014008f001428008faf24008f0008ac008f3caf00008f8faf008c3caf00008f",
INIT_07 => X"008f0000008faf00343c8faf008c343caf24008fac008f3caf003c8faf008c3c",
INIT_08 => X"3caf24008f0008af24008f001400348faf00008faf008c343cac008f343caf00",
INIT_09 => X"0000000000000008ac243cac008f343caf00008f0000008faf30008faf008c34",
INIT_0A => X"0801010101010101010000000000000000000000000000000000000000000000",
INIT_0B => X"3a3938080706050403022a29280d0c0b0a0908071a19180302010f0e0d0c0ac0",
INIT_0C => X"0d0c6a6968080706050403025a59580d0c0b0a0908074a49480302010f0e0d0c",
INIT_0D => X"000000000b0a09080706050403028a89880d0c0b0a0908077a79780302010f0e",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"aaa9a8a7a6a5a4a3a2a1bd000000880884608580bd1da50584049c1c00000000",
INIT_01 => X"aeadacabaaa9a8a7a6a5a4a3a2a10000bfb9b8b7b6b5b4b3b2b1b0afaeadacab",
INIT_02 => X"c0c0c5c4a0bebd00e0bdbec0a0bebd9a601b1abdbfb9b8b7b6b5b4b3b2b1b0af",
INIT_03 => X"c2c2024200828200424202c0006202c3c2020082820042420200620243024002",
INIT_04 => X"c0c0c26200c2c3c20200c2c20200828200424202c24200828200424202004000",
INIT_05 => X"c202006200c2400200c2c202004282620203c2c242004282620203c2c0c00000",
INIT_06 => X"004000c200404200c2c24200c200006200c203c24300c2c3c2004202c20200c2",
INIT_07 => X"0082400200c282624202838200424202c24200c26200c203c26202c3c2004202",
INIT_08 => X"02c24200c20000c24200c200406202c3c2020082820042420262008243028262",
INIT_09 => X"0000000000000000620203620082430282620082400200c28242008282004242",
INIT_0A => X"0101010101010101010000000000000000000000000000000000000000000000",
INIT_0B => X"010101282726252423220101011d1c1b1a1918170101011312110f0e0d0c01a8",
INIT_0C => X"4d4c010101484746454443420101013d3c3b3a3938370101013332312f2e2d2c",
INIT_0D => X"000000006b6a69686766656463620101015d5c5b5a5958570101015352514f4e",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000ff000000600000ff18001f0018001800180000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00000000f000ff00000000e8f000ff6000700000000000000000000000000000",
INIT_03 => X"000012ff00000000000010000000080000140000000000001000ff00001f0018",
INIT_04 => X"000000100000000014000000140000000000001000ff00000000000010000000",
INIT_05 => X"0000000000001812000000120000100520000000000000100520000000000000",
INIT_06 => X"0000000000ff0000000000000000000000001000100000000000001000140000",
INIT_07 => X"000018120000001000ff00000000001000ff0000000000100010000000000010",
INIT_08 => X"1000010000000100010000000010fe0000140000000000001000000000100010",
INIT_09 => X"00000000000000000000180000000010001000001814000000ff000000000000",
INIT_0A => X"0101010101010101010000000000000000000000000000000000000000000000",
INIT_0B => X"010101282726252423220101011d1c1b1a1918170101011312110f0e0d0c0101",
INIT_0C => X"4d4c010101484746454443420101013d3c3b3a3938370101013332312f2e2d2c",
INIT_0D => X"000000006b6a69686766656463620101015d5c5b5a5958570101015352514f4e",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"2c2824201c181410040090140059000104fd2a00f80004000000000000120003",
INIT_01 => X"3c3a34302c2824201c181410040000516c6864605c5854504c4844403c3a3430",
INIT_02 => X"04103c382134c800080804212104f800080001706c6864605c5854504c484440",
INIT_03 => X"0000020000000000001c000000c2001414020000000000140000fc0100000000",
INIT_04 => X"10241821001c202000002c1c02000000000028002cff0000000000240000b300",
INIT_05 => X"24010016000c210200180c020000215c80001008ff0000215c800010080c00d7",
INIT_06 => X"000d002400c76500101001001000dc0000280028250028082800000008000008",
INIT_07 => X"0000210000000024ffff000000001c0000ff0000000028002825042828000000",
INIT_08 => X"0004000004001f0401000400072aff040402000000000020000000001c000025",
INIT_09 => X"00000000000000600001000000002000002500002100000400ff000000000020",
INIT_0A => X"1004040404040404040000000000000000000000000000000000000000000000",
INIT_0B => X"0401100110040110040104011010040110040104040110100401100401100401",
INIT_0C => X"0401040110041004011004010401101004011004011004011004011004011004",
INIT_0D => X"0000000010040110040110040110040110040110040110040401100110040110",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/mb_lite/config_Pkg.vhd | 3 | 3338 | ----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE config_Pkg IS
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
CONSTANT CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
CONSTANT CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
CONSTANT CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
CONSTANT CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
CONSTANT CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
CONSTANT CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
CONSTANT CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
CONSTANT CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
CONSTANT CFG_REG_FWD_WB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
CONSTANT CFG_MEM_FWD_WB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
CONSTANT CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
CONSTANT CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
CONSTANT CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
END config_Pkg;
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/mb_lite/config_Pkg.vhd | 3 | 3338 | ----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE config_Pkg IS
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
CONSTANT CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
CONSTANT CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
CONSTANT CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
CONSTANT CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
CONSTANT CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
CONSTANT CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
CONSTANT CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
CONSTANT CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
CONSTANT CFG_REG_FWD_WB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
CONSTANT CFG_MEM_FWD_WB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
CONSTANT CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
CONSTANT CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
CONSTANT CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
END config_Pkg;
| mit |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA | Multiplier/Project/VHDL/toplevel.vhd | 3 | 3468 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
port (clk : in std_logic;
reset : in std_logic;
addrA : in std_logic_vector(2 downto 0);
addrB : in std_logic_vector(2 downto 0);
showAB: in std_logic;
start: in std_logic;
result: out std_logic_vector(31 downto 0);
outAB : out std_logic_vector(31 downto 0);
ready : out std_logic_vector(7 downto 0)
);
end multiplier;
architecture synt of multiplier is
signal romAOut : std_logic_vector (31 downto 0);
signal romBOut : std_logic_vector (31 downto 0);
component graph_driver
port (in_graph : in std_logic_vector(31 downto 0);
out_graph : out std_logic_vector(31 downto 0)
);
end component;
signal outAB_graph_s: std_logic_vector(31 downto 0);
signal result_graph_s: std_logic_vector(31 downto 0);
component romMemOpA
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component romMemOpB
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component device
port (a,b: in std_logic_vector(31 downto 0);
clk,en,rst: in std_logic;
c: out std_logic_vector(31 downto 0);
done: out std_logic
);
end component;
signal en_mul:std_logic;
signal rst_mul:std_logic;
signal result_graph_ss: std_logic_vector(31 downto 0);
signal done_mult: std_logic;
signal graph: std_logic_vector(31 downto 0);
type state is (initial, multiply, view_result);
signal CurrentState, NextState : state;
begin
process(CurrentState,start) begin
NextState<=initial;
result_graph_s<=(others=>'0');
case CurrentState is
when initial =>
en_mul<='0';
rst_mul<='0';
-----result<="11110000010000000010010011110001";
if(start='0') then
NextState<=multiply;
else
NextState<=initial;
end if;
when multiply =>
en_mul<='1';
rst_mul<='1';
if(done_mult='1') then
NextState<=view_result;
else
NextState<=multiply;
end if;
when view_result =>
if(start='0') then
NextState<=initial;
else
NextState<=view_result;
end if;
end case;
end process;
transitions:process (clk, reset) begin
if reset='0'then
CurrentState <= initial;
elsif (clk'event and clk='1')then
CurrentState <= NextState;
end if;
end process;
uOpA: romMemOpA
port map (
addr => addrA,
dataOut => romAOut
);
uOpB: romMemOpB
port map (
addr => addrB,
dataOut => romBOut
);
uMult: device
port map (
a => romAOut,
b => romBOut,
clk=>clk ,
en=> en_mul,
rst=> rst_mul,
c => result_graph_ss,
done=>done_mult
);
outtAB_graph: graph_driver port map(in_graph=>outAB_graph_s,out_graph=>outAB);
result_graph: graph_driver port map(in_graph=>result_graph_ss,out_graph=>result);
-- When the button assoiciated to outAB is pushed romAOut is displayed
outAB_graph_s<= romAOut when showAB = '0'
else romBOut;
ready(7 downto 0) <= (others => done_mult);
end synt;
| mit |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA | Multiplier/Project/VHDL/toplevel - copia (2).vhd | 3 | 3468 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
port (clk : in std_logic;
reset : in std_logic;
addrA : in std_logic_vector(2 downto 0);
addrB : in std_logic_vector(2 downto 0);
showAB: in std_logic;
start: in std_logic;
result: out std_logic_vector(31 downto 0);
outAB : out std_logic_vector(31 downto 0);
ready : out std_logic_vector(7 downto 0)
);
end multiplier;
architecture synt of multiplier is
signal romAOut : std_logic_vector (31 downto 0);
signal romBOut : std_logic_vector (31 downto 0);
component graph_driver
port (in_graph : in std_logic_vector(31 downto 0);
out_graph : out std_logic_vector(31 downto 0)
);
end component;
signal outAB_graph_s: std_logic_vector(31 downto 0);
signal result_graph_s: std_logic_vector(31 downto 0);
component romMemOpA
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component romMemOpB
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component device
port (a,b: in std_logic_vector(31 downto 0);
clk,en,rst: in std_logic;
c: out std_logic_vector(31 downto 0);
done: out std_logic
);
end component;
signal en_mul:std_logic;
signal rst_mul:std_logic;
signal result_graph_ss: std_logic_vector(31 downto 0);
signal done_mult: std_logic;
signal graph: std_logic_vector(31 downto 0);
type state is (initial, multiply, view_result);
signal CurrentState, NextState : state;
begin
process(CurrentState,start) begin
NextState<=initial;
result_graph_s<=(others=>'0');
case CurrentState is
when initial =>
en_mul<='0';
rst_mul<='0';
-----result<="11110000010000000010010011110001";
if(start='0') then
NextState<=multiply;
else
NextState<=initial;
end if;
when multiply =>
en_mul<='1';
rst_mul<='1';
if(done_mult='1') then
NextState<=view_result;
else
NextState<=multiply;
end if;
when view_result =>
if(start='0') then
NextState<=initial;
else
NextState<=view_result;
end if;
end case;
end process;
transitions:process (clk, reset) begin
if reset='0'then
CurrentState <= initial;
elsif (clk'event and clk='1')then
CurrentState <= NextState;
end if;
end process;
uOpA: romMemOpA
port map (
addr => addrA,
dataOut => romAOut
);
uOpB: romMemOpB
port map (
addr => addrB,
dataOut => romBOut
);
uMult: device
port map (
a => romAOut,
b => romBOut,
clk=>clk ,
en=> en_mul,
rst=> rst_mul,
c => result_graph_ss,
done=>done_mult
);
outtAB_graph: graph_driver port map(in_graph=>outAB_graph_s,out_graph=>outAB);
result_graph: graph_driver port map(in_graph=>result_graph_ss,out_graph=>result);
-- When the button assoiciated to outAB is pushed romAOut is displayed
outAB_graph_s<= romAOut when showAB = '0'
else romBOut;
ready(7 downto 0) <= (others => done_mult);
end synt;
| mit |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA | Multiplier/Project/VHDL/datapath.vhd | 1 | 2346 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity datapath is
port (a,b: in std_logic_vector(31 downto 0);
clk,rst: in std_logic;
en: in std_logic_vector(1 downto 0);
c: out std_logic_vector(31 downto 0);
done,m47: out std_logic
);
end datapath;
architecture arch_datapath_1 of datapath is
component reg is
port (clk,en,rst: in std_logic;
a:in std_logic_vector((31) downto 0);
r: out std_logic_vector((31) downto 0)
);
end component;
component mul_int1 is
port (in1: in std_logic_vector(23 downto 0);
in2: in std_logic_vector(23 downto 0);
clk,rst: in std_logic;
done:out std_logic;
res: out std_logic_vector(47 downto 0):=(others=>'0')
);
end component;
component extractor is
port (
ext_in:in std_logic_vector(47 downto 0 );
ext_out:out std_logic_vector(22 downto 0 )
);
end component;
signal rra,rrb: std_logic_vector(31 downto 0);
alias signa: std_logic is rra(31);
alias signb: std_logic is rrb(31);
alias expa: std_logic_vector(7 downto 0) is rra(30 downto 23);
alias expb: std_logic_vector(7 downto 0) is rrb(30 downto 23);
alias manta: std_logic_vector(22 downto 0) is rra(22 downto 0);
alias mantb: std_logic_vector(22 downto 0) is rrb(22 downto 0);
signal mana,manb: std_logic_vector(23 downto 0);
signal done_mul: std_logic;
signal mul_out: std_logic_vector(47 downto 0);
signal ext_out: std_logic_vector(22 downto 0);
signal signf: std_logic;
signal expf:std_logic_vector(7 downto 0):=(others=>'0');
signal expg:std_logic_vector(7 downto 0):=(others=>'0');
signal exph:std_logic_vector(7 downto 0):=(others=>'0');
signal ric: std_logic_vector(31 downto 0);
begin
mana<='1' & manta;
manb<='1' & mantb;
rega: reg port map(clk=>clk,en=>en(0),rst=>rst,a=>a,r=>rra);
regb: reg port map(clk=>clk,en=>en(0),rst=>rst,a=>b,r=>rrb);
mult: mul_int1 port map(in1=>mana,in2=>manb,clk=>clk,rst=>rst,done=>done_mul,res=>mul_out);
ext: extractor port map(ext_in=>mul_out,ext_out=>ext_out);
signf<=signa xor signb;
expg<=std_logic_vector(expa+expb);
exph<=std_logic_vector(expg)-"01111111";
expf<=exph+("0000000" & mul_out(47));
ric<=signf & expf & ext_out;
regc: reg port map(clk=>clk,en=>en(1),rst=>rst,a=>ric,r=>c);
done<=done_mul;
m47<=mul_out(47);
end arch_datapath_1;
| mit |
jakubcabal/pipemania-fpga-game | source/comp/control/kb_code.vhd | 1 | 1751 | -- kb_code.vhd - Modul pro dekodovani kodu klavesy
-- Autori: Jakub Cabal
-- Posledni zmena: 14.10.2014
-- Popis: Tato komponenta generuje kod prave zmackle klavesy
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity KB_CODE is
Port (
CLK : in STD_LOGIC; -- Vychozi hodinovy signal
RST : in STD_LOGIC; -- Vychozi synchronni reset
PS2RX_DATA : in STD_LOGIC_VECTOR(7 downto 0); -- Vstupní data z PS2_RX
PS2RX_VALID : in STD_LOGIC; -- Data z PS2_RX jsou pripravena na vycteni
KEY_CODE : out STD_LOGIC_VECTOR(7 downto 0) -- Kod klavesy
);
end KB_CODE;
architecture FULL of KB_CODE is
signal ps2_code : STD_LOGIC_VECTOR(7 downto 0);
signal ps2_code_last : STD_LOGIC_VECTOR(7 downto 0);
begin
----------------------------------------------------------------
-- ZPRACOVANI DAT
----------------------------------------------------------------
-- Vycteni dat z PS2_RX
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
ps2_code <= (others => '0');
ps2_code_last <= (others => '0');
elsif (PS2RX_VALID = '1') then
ps2_code <= PS2RX_DATA;
ps2_code_last <= ps2_code;
end if;
end if;
end process;
-- Propagace kodu klavesy na vystup, pri uvolneni klavesy
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
KEY_CODE <= (others => '0');
elsif (ps2_code_last /= X"F0") then
KEY_CODE <= ps2_code;
end if;
end if;
end process;
end FULL; | mit |
dicearr/neuron-vhdl | src/adder_tree.vhd | 1 | 4835 | -- ----------------------------------------------------------------
-- adder_tree.vhd
--
-- 4/28/2011 D. W. Hawkins ([email protected])
--
-- Adder tree.
--
-- This component calculates the pipelined sum of parallel input
-- arguments and generates a single output. The sums are
-- implemented in pairs. The width of the sums increases 1-bit
-- per layer. The number of sum layers is ceil(log2(NINPUTS)),
-- where NINPUTS is the number of inputs.
--
-- The sum pipeline pads the number of sums at the input to the
-- next power of two; synthesis removes unused logic. The sum
-- indexing for an 8 input example is;
--
-- sum(0) --|\ sum(8)
-- |+|--------|\
-- sum(1) --|/ | | sum(12)
-- |+|---------|\
-- sum(2) --|\ sum(9) | | | |
-- |+|--------|/ | |
-- sum(3) --|/ | | sum(14)
-- |+|---------
-- sum(4) --|\ sum(10) | |
-- |+|--------|\ | |
-- sum(5) --|/ | | sum(13) | |
-- |+|---------|/
-- sum(6) --|\ sum(11)| |
-- |+|--------|/
-- sum(7) --|/
--
-- The width of the full-precision output can be reduce by
-- rounding using the unbiased 'convergent' rounding component.
--
-- The parallel inputs are signed values packed into a wide
-- std_logic_vector.
--
-- ----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- ----------------------------------------------------------------
entity adder_tree is
generic (
-- Number of inputs
NINPUTS : integer;
-- Input data width
IWIDTH : integer;
-- Output data width
-- * full-precision requires that
-- OWIDTH = IWIDTH + ceil(log2(NINPUTS))
OWIDTH : integer
);
port (
-- Reset and clock
rstN : in std_logic;
clk : in std_logic;
-- Input data
-- * NINPUTS x signed(IWIDTH-1 downto 0)
d : in std_logic_vector(NINPUTS*IWIDTH-1 downto 0);
-- Output data
q : out signed(OWIDTH-1 downto 0)
);
end entity;
-- ----------------------------------------------------------------
architecture mixed of adder_tree is
-- ------------------------------------------------------------
-- Local functions
-- ------------------------------------------------------------
--
-- Input lookup and signed conversion
impure function din(i : integer) return signed is
begin
return signed(d((i+1)*IWIDTH-1 downto i*IWIDTH));
end function;
-- ------------------------------------------------------------
-- Constants
-- ------------------------------------------------------------
--
-- Number of stages required to sum the inputs
constant NSTAGES : integer :=
integer(ceil(log2(real(NINPUTS))));
-- Number of inputs padded to next power-of-2
-- * the width of the first stage of sums
constant PWIDTH : integer := 2**NSTAGES;
-- The total number of sums in the pipeline
constant NSUMS : integer := PWIDTH-1;
-- The width of the last sum (used for all sums)
constant SWIDTH : integer :=
IWIDTH + NSTAGES;
-- ------------------------------------------------------------
-- Signals
-- ------------------------------------------------------------
--
-- Sum pipeline
type sum_t is array (0 to NSUMS-1) of
signed(SWIDTH-1 downto 0);
signal sum : sum_t;
begin
-- ------------------------------------------------------------
-- Pipelined adders
-- ------------------------------------------------------------
--
process(clk,rstN)
variable prev_index : integer;
variable curr_index : integer;
variable num_sums : integer;
begin
if (rstN = '0') then
sum <= (others => (others => '0'));
elsif rising_edge(clk) then
-- First stage; pairs of input sums
-- * unused power-of-2 padding is left at the
-- reset value of zero.
num_sums := PWIDTH/2;
for j in 0 to num_sums-1 loop
if (2*j+1 < NINPUTS) then
-- Resize and then sum (to avoid overflow)
sum(j) <=
resize(din(2*j), SWIDTH) +
resize(din(2*j+1), SWIDTH);
elsif (2*j < NINPUTS) then
sum(j) <= resize(din(2*j), SWIDTH);
end if;
end loop;
-- Subsequent stages; sums of previous sums
prev_index := 0;
curr_index := num_sums;
num_sums := num_sums/2;
for i in 1 to NSTAGES-1 loop
for j in 0 to num_sums-1 loop
sum(curr_index + j) <=
sum(prev_index + 2*j) +
sum(prev_index + 2*j + 1);
end loop;
prev_index := curr_index;
curr_index := curr_index + num_sums;
num_sums := num_sums/2;
end loop;
end if;
end process;
-- ------------------------------------------------------------
-- Full-precision output sum
-- ------------------------------------------------------------
--
q <= sum(NSUMS-1)(OWIDTH-1 downto 0);
end architecture; | mit |
nczempin/NICNAC16 | ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd | 1 | 12646 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
DATA_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0):= hex_to_std_logic_vector("0",16);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(15 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
16,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
ENA <= DO_READ ;
END ARCHITECTURE;
| mit |
jakubcabal/pipemania-fpga-game | source/comp/video/vga_sync.vhd | 1 | 3859 | --------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: VGA_SYNC
-- AUTHORS: Vojtěch Jeřábek <[email protected]>
-- Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity VGA_SYNC is
Port (
CLK : in std_logic; -- clock, must be 50 MHz
RST : in std_logic; -- reset
PIXEL_X : out std_logic_vector(9 downto 0); -- cislo pixelu na radku
PIXEL_Y : out std_logic_vector(9 downto 0); -- cislo pixelu ve sloupci
HSYNC : out std_logic; -- synchronizacni pulzy pro VGA vystup
VSYNC : out std_logic
);
end VGA_SYNC;
architecture Behavioral of VGA_SYNC is
signal pixel_tick : std_logic; -- doba vykreslovani pixelu - 25 MHz
signal position_x : unsigned(9 downto 0); -- udava cislo pixelu na radku
signal position_y : unsigned(9 downto 0); -- udava cislo pixelu ve sloupci
begin
----------------------------------------------------------------------------
-- pixel_tick o potrebne frekvenci 25MHz, vyzaduje CLK o frekvenci 50MHZ
pixel_tick_p : process (CLK, RST)
begin
if (RST = '1') then
pixel_tick <= '0';
elsif (rising_edge(CLK)) then
pixel_tick <= not pixel_tick;
end if;
end process;
----------------------------------------------------------------------------
-- pocitani na jakem pixelu na radku se nachazime
position_x_p : process (CLK, RST)
begin
if (RST = '1') then
position_x <= (others => '0');
elsif (rising_edge(CLK)) then
if (pixel_tick = '1') then
if (position_x = 799) then
position_x <= (others => '0');
else
position_x <= position_x + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- pocitani na jakem pixelu ve sloupci se nachazime
position_y_p : process (CLK, RST)
begin
if (RST = '1') then
position_y <= (others => '0');
elsif (rising_edge(CLK)) then
if (pixel_tick = '1' and position_x = 799) then
if (position_y = 524) then
position_y <= (others => '0');
else
position_y <= position_y + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- synchronizacni pulzy pro VGA
hsync_reg_p : process (CLK, RST)
begin
if (RST = '1') then
HSYNC <= '0';
elsif (rising_edge(CLK)) then
if (position_x > 655 and position_x < 752) then
HSYNC <= '0';
else
HSYNC <= '1';
end if;
end if;
end process;
vsync_reg_p : process (CLK, RST)
begin
if (RST = '1') then
VSYNC <= '0';
elsif (rising_edge(CLK)) then
if (position_y > 489 and position_y < 492) then
VSYNC <= '0';
else
VSYNC <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- prirazeni vystupnich signalu
PIXEL_X <= std_logic_vector(position_x);
PIXEL_Y <= std_logic_vector(position_y);
end Behavioral;
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/plasma/reg_bank.vhd | 2 | 10179 | ---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
entity reg_bank is
generic(memory_type : string := "DUAL_PORT_");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0);
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
-- tri_port_mem:
-- if memory_type = "TRI_PORT_X" generate
-- ram_proc: process(clk, addr_read1, addr_read2,
-- addr_write, reg_dest_new, write_enable)
-- variable tri_port_ram : ram_type;
-- begin
-- data_out1 <= tri_port_ram(conv_integer(addr_read1));
-- data_out2 <= tri_port_ram(conv_integer(addr_read2));
-- if rising_edge(clk) then
-- if write_enable = '1' then
-- tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
-- end if;
-- end if;
-- end process;
-- end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
dual_port_mem:
if memory_type = "DUAL_PORT_" generate
ram_proc2: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable dual_port_ram1 : ram_type;
variable dual_port_ram2 : ram_type;
begin
data_out1 <= dual_port_ram1(conv_integer(addr_read1));
data_out2 <= dual_port_ram2(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --dual_port_mem
-- Option #3
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
-- From library UNISIM; use UNISIM.vcomponents.all;
xilinx_16x1d:
if memory_type = "XILINX_16X" generate
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
signal weA, weB : std_logic;
begin
weA <= write_enable and not addr_write(4); --lower 16 registers
weB <= write_enable and addr_write(4); --upper 16 registers
reg_loop: for i in 0 to 31 generate
begin
--Read port 1 lower 16 registers
reg_bit1a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 1 upper 16 registers
reg_bit1b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 lower 16 registers
reg_bit2a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 upper 16 registers
reg_bit2b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
end generate; --reg_loop
data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
end generate; --xilinx_16x1d
end; --architecture ram_block
| mit |
jakubcabal/pipemania-fpga-game | source/comp/memory/mem_hub.vhd | 1 | 2948 | --------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: MEM_HUB
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MEM_HUB is
Port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
-- Port A
EN_A : in std_logic; -- Povoleni prace s portem A
WE_A : in std_logic; -- Povoleni zapisu
ADDR_A : in std_logic_vector(7 downto 0); -- Adresa
DIN_A : in std_logic_vector(31 downto 0); -- Vstupni data
DOUT_A : out std_logic_vector(31 downto 0); -- Vystupni data
ACK_A : out std_logic; -- Potvrzeni prace s portem A
-- Port B
EN_B : in std_logic; -- Povoleni prace s portem B
WE_B : in std_logic; -- Povoleni zapisu
ADDR_B : in std_logic_vector(7 downto 0); -- Adresa
DIN_B : in std_logic_vector(31 downto 0); -- Vstupni data
DOUT_B : out std_logic_vector(31 downto 0); -- Vystupni data
ACK_B : out std_logic; -- Potvrzeni prace s portem B
-- Output port
WE : out std_logic; -- Povoleni zapisu
ADDR : out std_logic_vector(7 downto 0); -- Adresa
DIN : out std_logic_vector(31 downto 0); -- Vstupni data
DOUT : in std_logic_vector(31 downto 0) -- Vystupni data
);
end MEM_HUB;
architecture FULL of MEM_HUB is
signal sig_ack_a : std_logic;
signal sig_ack_b : std_logic;
signal last_ack_a : std_logic;
signal last_ack_b : std_logic;
begin
ctrl_mux_p : process (WE_A, WE_B, EN_A, EN_B, ADDR_A, ADDR_B, DIN_A, DIN_B)
begin
if (EN_A = '1') then
WE <= WE_A;
ADDR <= ADDR_A;
DIN <= DIN_A;
sig_ack_a <= '1';
sig_ack_b <= '0';
elsif (EN_B = '1') then
WE <= WE_B;
ADDR <= ADDR_B;
DIN <= DIN_B;
sig_ack_a <= '0';
sig_ack_b <= '1';
else
WE <= '0';
ADDR <= (others => '0');
DIN <= (others => '0');
sig_ack_a <= '0';
sig_ack_b <= '0';
end if;
end process;
ACK_A <= sig_ack_a;
ACK_B <= sig_ack_b;
DOUT_A <= DOUT;
DOUT_B <= DOUT;
ack_reg : process (CLK, RST)
begin
if (RST = '1') then
last_ack_a <= '0';
last_ack_b <= '0';
elsif (rising_edge(CLK)) then
last_ack_a <= sig_ack_a;
last_ack_b <= sig_ack_b;
end if;
end process;
end FULL;
| mit |
dicearr/neuron-vhdl | src/data_types.vhd | 1 | 1609 | ----------------------------------------------------------------------------------
-- Engineer: Diego Ceresuela, Oscar Clemente.
--
-- Create Date: 18.04.2016 11:33:46
-- Module Name: data_types - Package
-- Description:
--
-- Dependencies:
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package data_types is
type vector is array (natural range <>) of STD_LOGIC_VECTOR (31 downto 0);
function to_vec (slv: std_logic_vector) return vector;
function to_slv (v: vector) return std_logic_vector;
end data_types;
package body data_types is
function to_vec (slv: std_logic_vector) return vector is
variable c : vector (0 to (slv'length/32)-1);
begin
for I in c'range loop
c(I) := slv((I*32)+31 downto (I*32));
end loop;
return c;
end function to_vec;
function to_slv (v: vector) return std_logic_vector is
variable slv : std_logic_vector ((v'length*32)-1 downto 0);
begin
for I in v'range loop
slv((I*32)+31 downto (I*32)) := v(I);
end loop;
return slv;
end function to_slv;
end data_types;
| mit |
jakubcabal/pipemania-fpga-game | source/comp/control/ps2_rx.vhd | 1 | 5740 | --------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: PS2_RX
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PS2_RX is
Port (
CLK : in std_logic; -- Vychozi hodinovy signal
RST : in std_logic; -- Vychozi reset
PS2C : in std_logic; -- Hodinovy signal z PS2 portu
PS2D : in std_logic; -- Seriova vstupni data z PS2 portu
PS2RX_DATA : out std_logic_vector(7 downto 0); -- Vystupni data
PS2RX_VALID : out std_logic -- Data jsou pripravena na vycteni
);
end PS2_RX;
architecture FULL of PS2_RX is
signal ps2_valid : std_logic;
signal parity_valid : std_logic;
signal parity_ctrl : std_logic;
signal parity_ps2 : std_logic;
signal ps2_bit_count : unsigned(3 downto 0);
signal sig_ps2rx_data : std_logic_vector(7 downto 0);
signal sig_ps2rx_data2 : std_logic_vector(7 downto 0);
type state is (idle, dps, load);
signal present_st : state;
signal next_st : state;
begin
----------------------------------------------------------------------------
-- FALLING EDGE DETECTOR OF PS/2 CLOCK
----------------------------------------------------------------------------
falling_edge_detector_i : entity work.FALLING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => PS2C,
VYSTUP => ps2_valid -- Pri sestupne hrane jsou validni data
);
----------------------------------------------------------------------------
-- PS2 RX FSM
----------------------------------------------------------------------------
fsm_reg : process (CLK, RST)
begin
if (RST = '1') then
present_st <= idle;
elsif (rising_edge(CLK)) then
present_st <= next_st;
end if;
end process;
-- Rozhodovaci cast stavoveho automatu
process (present_st, PS2D, ps2_valid, ps2_bit_count)
begin
case present_st is
when idle =>
if (ps2_valid = '1' AND PS2D = '0') then
next_st <= dps;
else
next_st <= idle;
end if;
when dps =>
if (to_integer(ps2_bit_count) = 11) then
next_st <= load;
else
next_st <= dps;
end if;
when load =>
next_st <= idle;
end case;
end process;
-- Vystupni cast stavoveho automatu
process (present_st, parity_valid)
begin
case present_st is
when idle =>
PS2RX_VALID <= '0';
when dps =>
PS2RX_VALID <= '0';
when load =>
PS2RX_VALID <= parity_valid;
end case;
end process;
----------------------------------------------------------------------------
-- BIT COUNTER
----------------------------------------------------------------------------
bit_cnt_p : process (CLK, RST)
begin
if (RST = '1') then
ps2_bit_count <= (others => '0');
elsif (rising_edge(CLK)) then
if (to_integer(ps2_bit_count) = 11) then
ps2_bit_count <= (others => '0');
elsif (ps2_valid = '1') then
ps2_bit_count <= ps2_bit_count + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PS/2 DATA
----------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
if (ps2_valid = '1') then
if (to_integer(ps2_bit_count) > 0 AND to_integer(ps2_bit_count) < 9) then
sig_ps2rx_data(7 downto 0) <= PS2D & sig_ps2rx_data(7 downto 1);
end if;
end if;
end if;
end process;
process (CLK)
begin
if (rising_edge(CLK)) then
if (ps2_valid = '1') then
if (to_integer(ps2_bit_count) = 9) then
parity_ps2 <= PS2D;
end if;
end if;
end if;
end process;
-- Propagace PS2 dat na vystup
process (CLK)
begin
if (rising_edge(CLK)) then
if (to_integer(ps2_bit_count) = 10) then
sig_ps2rx_data2 <= sig_ps2rx_data;
end if;
end if;
end process;
PS2RX_DATA <= sig_ps2rx_data2;
----------------------------------------------------------------------------
-- DATA PARITY CHECK
----------------------------------------------------------------------------
parity_ctrl <= sig_ps2rx_data2(7) xor sig_ps2rx_data2(6) xor
sig_ps2rx_data2(5) xor sig_ps2rx_data2(4) xor
sig_ps2rx_data2(3) xor sig_ps2rx_data2(2) xor
sig_ps2rx_data2(1) xor sig_ps2rx_data2(0) xor '1';
-- Kontrola parity
process (CLK, RST)
begin
if (RST = '1') then
parity_valid <= '0';
elsif (rising_edge(CLK)) then
if (parity_ctrl = parity_ps2) then
parity_valid <= '1';
else
parity_valid <= '0';
end if;
end if;
end process;
end FULL;
| mit |
dicearr/neuron-vhdl | src/sigmoid.vhd | 1 | 30205 | ----------------------------------------------------------------------------------
-- Engineer: Diego Ceresuela, Oscar Clemente.
--
-- Create Date: 13.04.2016 08:23:25
-- Module Name: sigmoid - Behavioral
-- Description: Implements a ROM containing the aproximation of the sigmoid function.
--
-- Dependencies:
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sigmoid is
Port ( Y : in STD_LOGIC_VECTOR (31 downto 0);
O : out STD_LOGIC_VECTOR (31 downto 0);
clk: in STD_LOGIC );
end sigmoid;
architecture Behavioral of sigmoid is
type rom is array (0 to 3410) of STD_LOGIC_VECTOR (15 downto 0);
signal sigmoid_val : rom := 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signal ind, dec, decimal_32, ent_32 : integer := 0;
begin
process (clk) begin
if rising_edge(clk) then
decimal_32 <= conv_integer(x"0000" & Y(15 downto 0));
ent_32 <= conv_integer(Y(31 downto 16));
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if ( Y(31 downto 16) < -10 ) then
dec <= decimal_32/9855;
elsif ( Y(31 downto 16) < -9 ) then
dec <= decimal_32/2815;
elsif ( Y(31 downto 16) < 9 ) then
dec <= decimal_32/351;
elsif ( Y(31 downto 16) < 10 ) then
dec <= decimal_32/2815;
else
dec <= decimal_32/9855;
end if;
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if ( Y(31 downto 16) < -10 ) then
ind <= dec;
elsif ( Y(31 downto 16) < -9 ) then
ind <= 7 + dec;
elsif ( Y(31 downto 16) < 9 ) then
ind <= 1704+(ent_32*186)+dec;
elsif ( Y(31 downto 16) < 10 ) then
ind <= 1705+(ent_32*186)+dec;
else
ind <= 1728+(ent_32*186)+dec;
end if;
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if (Y(31 downto 16) < -11) then O <= x"00000000";
elsif (Y(31 downto 16) > 11) then O <= x"0000FFFF";
else
O <= x"0000" & sigmoid_val(ind);
end if;
end if;
end process;
end Behavioral;
| mit |
velentr/foundry.vhdl | adder.vhd | 1 | 3923 | --------------------------------------------------------------------------------
-- adder.vhd
--
-- This file contains a simple N-bit full adder/subtractor using a carry chain.
-- The carry out of each bit is used to calculate that sum of the next bit.
-- This will slow the operation down slightly, but will reduce the amount of
-- logic required.
--
-- When 'Sub' is inactive, the operation 'OpA + OpB' is performed. If 'Sub' is
-- inactive, then 'OpA - OpB' is performed.
--
-- Note that the generic parameter N determines the number of bits of the input
-- and output, as well as the indices of the carry outputs. It should generally
-- be an even number for the half-carry to work properly.
--
-- The size of this cell is O(N). The speed of this cell is O(N).
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 27 Jan 2015 Brian Kubisiak Initial revision.
-- 18 Jul 2015 Brian Kubisiak Small tweaks, updated documentation.
--
--------------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
-- Adder
--
-- parameters:
-- N (integer) Number of bits in the operands/result.
-- inputs:
-- Cin (std_logic) Carry/borrow for the adder.
-- OpA (std_logic_vector) First operand to the adder/subtractor.
-- OpB (std_logic_vector) Second operand to the adder/subtractor.
-- Sub (std_logic) Perform 'a - b' instead of 'a + b'. Active
-- high.
--
-- outputs:
-- Res (std_logic_vector) Result of the addition
-- Cout (std_logic) Carry out of bit N-1
-- Coutv (std_logic) Carry out of bit N-2, used for finding oflow
-- HCout (std_logic) Carry out of bit (N/2)-1 (half carry)
--
entity Adder is
-- N determines the size of the adder. Should be an even number.
generic (N : integer);
port (
-- Carry input.
Cin : in std_logic;
-- Indicates subtraction should be performed, active high.
Sub : in std_logic;
-- Operands on which to perform addition/subtraction.
OpA : in std_logic_vector(N-1 downto 0);
OpB : in std_logic_vector(N-1 downto 0);
-- Carry output of bit N-1.
Cout : out std_logic;
-- Carry out of bit N-2, used for finding overflow.
Coutv : out std_logic;
-- Carry out of bit (N/2)-1.
HCout : out std_logic;
-- Result of the addition/subtraction
Res : out std_logic_vector(N-1 downto 0)
);
end Adder;
--
-- This adder/subtractor uses a for-generate loop to create a carry chain of
-- full adders/subtractors. It saves the carry bits, so these can easily be
-- output.
--
architecture carry_chain of Adder is
-- This signal holds the carries into each bit
signal carry : std_logic_vector(N downto 0);
-- This is the second operand, inverted if subtracting
signal OpBmod: std_logic_vector(N-1 downto 0);
begin
-- Invert the carry input if subtracting
carry(0) <= Cin xor Sub;
-- Invert operand B if subtracting
InvB: for I in 0 to N-1 generate
OpBmod(I) <= OpB(I) xor Sub;
end generate InvB;
-- Chain together all the carry bits
FullAdder: for I in 0 to N-1 generate
-- Calculate each result bit based on the inputs and the carry in
Res(I) <= OpA(I) xor OpBmod(I) xor carry(I);
-- Base the next carry on the result
carry(I+1) <= ((OpA(I) xor OpBmod(I)) and carry(I))
or (OpA(I) and OpBmod(I));
end generate FullAdder;
-- Now we can just output the carry bits, inverted if we were subtracting
Cout <= carry(N) xor sub;
Coutv <= carry(N-1) xor sub;
HCout <= carry(N/2) xor sub;
end carry_chain;
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/plasma/control.vhd | 2 | 15689 | ---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --FTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH;
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/dsram.vhd | 3 | 1654 | ----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.std_Pkg.ALL;
ENTITY dsram IS GENERIC
(
WIDTH : positive := 32;
SIZE : positive := 8
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END dsram;
ARCHITECTURE arch OF dsram IS
TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type;
BEGIN
PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF ena_i = '1' THEN
IF wre_i = '1' THEN
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
END IF;
dat_o <= ram(my_conv_integer(adr_i));
END IF;
END IF;
END PROCESS;
END arch;
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/mb_lite/dsram.vhd | 3 | 1654 | ----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.std_Pkg.ALL;
ENTITY dsram IS GENERIC
(
WIDTH : positive := 32;
SIZE : positive := 8
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END dsram;
ARCHITECTURE arch OF dsram IS
TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type;
BEGIN
PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF ena_i = '1' THEN
IF wre_i = '1' THEN
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
END IF;
dat_o <= ram(my_conv_integer(adr_i));
END IF;
END IF;
END PROCESS;
END arch;
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/mlite_pack.vhd | 2 | 21630 | ---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
lpm_width : NATURAL;
lpm_widthad : NATURAL;
rden_used : STRING;
intended_device_family : STRING;
lpm_indata : STRING;
lpm_wraddress_control : STRING;
lpm_rdaddress_control : STRING;
lpm_outdata : STRING;
use_eab : STRING;
lpm_type : STRING);
PORT (
wren : IN STD_LOGIC ;
wrclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"16");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "ALTERA_LPM");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "ALTERA_LPM"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
opcode_test_out : out std_logic_vector(31 downto 0);
pc_future_test_out : out std_logic_vector(31 downto 2);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "ALTERA_LPM"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
| mit |
herenvarno/dlx | dlx_vhd/src/a.b-DataPath.core/a.b.f-Mul.core/a.b.f.0-BoothGenerator.vhd | 1 | 1329 | --------------------------------------------------------------------------------
-- FILE: BoothGenerator
-- DESC: Generator of Booth's Multiplier
--
-- Author:
-- Create: 2015-08-14
-- Update: 2015-08-14
-- Status: TESED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity BoothGenerator is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port(
a: in std_logic_vector(DATA_SIZE*2-1 downto 0);
ya, y2a: out std_logic_vector(DATA_SIZE*2-1 downto 0)
);
end BoothGenerator;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture booth_generator_arch of BoothGenerator is
begin
-- a
ya(DATA_SIZE*2-1 downto STAGE*2) <= a(DATA_SIZE*2-STAGE*2-1 downto 0);
ya(STAGE*2-1 downto 0) <= (others=>'0');
-- 2a
y2a(DATA_SIZE*2-1 downto STAGE*2+1) <= a(DATA_SIZE*2-STAGE*2-2 downto 0);
y2a(STAGE*2 downto 0) <= (others=>'0');
end booth_generator_arch;
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/plasma/ram_image.vhd | 2 | 181522 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafaf2708000c4034241400ac373c343c343c373c00100010",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f000cafafafafafafafafafafafafafafafaf",
INIT_02 => X"008faf03afaf270003278f0303af2740034034278f8f8f8f8f8f8f8f8f8f8f8f",
INIT_03 => X"08000caf24008faf240008af2400080010008f240010008f24af008f000caf24",
INIT_04 => X"008f8f0008af00008f8f00080010008f240010008f24af008faf24af03af2700",
INIT_05 => X"00000000000000000000000000000000000000000000000003278f0324af0000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"aaa9a8a7a6a5a4a3a2a1bd000000880884608580bd1da50584049c1c00000000",
INIT_01 => X"aeadacabaaa9a8a7a6a5a4a3a2a10000bfb9b8b7b6b5b4b3b2b1b0afaeadacab",
INIT_02 => X"00c2c0a0bebfbd00e0bdbec0a0bebd9a601b1abdbfb9b8b7b6b5b4b3b2b1b0af",
INIT_03 => X"000000824200828202000082020000006200c302006200c302c2008200008242",
INIT_04 => X"00c3c20000824300c3820000006200c302006200c302c200c2c202c4a0bebd00",
INIT_05 => X"000000000000000000000000000000000000000000000000e0bdbec002820043",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000ff000000600000ff18001f0018001800180000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"000000f00000ff00000000e8f000ff6000700000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"00000000000010000000000000000000000000000000000000000000f000ff00",
INIT_05 => X"000000000000000000000000000000000000000000000000000000e8ff001000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"2c2824201c181410040090140059000104fd2a00f80004000000000000120003",
INIT_01 => X"3c3a34302c2824201c181410040000516c6864605c5854504c4844403c3a3430",
INIT_02 => X"001010212024d80008100c21210cf000080001706c6864605c5854504c484440",
INIT_03 => X"7f00810002000000050079000100790007001803000800180218000000810001",
INIT_04 => X"00180000a3002100000000a3000a00080200080008010800180001182114e800",
INIT_05 => X"00000000000000000000000000000000000000000000000008181421ff001218",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/plasma/uart.vhd | 2 | 6948 | ---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(7 downto 0);
signal uart_read2 : std_logic;
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2,
busy_write_sig, uart_read)
constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
"0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
read_value_reg <= ONES(7 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
-- synthesis_on
end; --architecture logic
| mit |
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