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jakubcabal/pipemania-fpga-game | source/comp/video/cell_ctrl.vhd | 1 | 15927 | --------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: CELL_CTRL
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CELL_CTRL is
Port (
CLK : in std_logic;
PIXEL_X : in std_logic_vector(9 downto 0);
PIXEL_Y : in std_logic_vector(9 downto 0);
KURZOR_ADDR : in std_logic_vector(7 downto 0);
KURZOR : out std_logic;
PIXEL_SET_X : out std_logic;
PIXEL_SET_Y : out std_logic;
KOMP_SET_X : out std_logic;
KOMP_SET_Y : out std_logic;
KOMP_ON : out std_logic;
KOMP4_IS : out std_logic;
ADDR : out std_logic_vector(7 downto 0);
KOMP0 : in std_logic_vector(5 downto 0);
KOMP1 : in std_logic_vector(5 downto 0);
KOMP2 : in std_logic_vector(5 downto 0);
KOMP3 : in std_logic_vector(5 downto 0);
KOMP4 : in std_logic_vector(5 downto 0);
KOMP_OUT : out std_logic_vector(5 downto 0);
SCREEN_CODE : in std_logic_vector(2 downto 0) -- game screen code
);
end CELL_CTRL;
architecture FULL of CELL_CTRL is
signal pix_x : std_logic_vector(9 downto 0);
signal pix_y : std_logic_vector(9 downto 0);
signal addr_x : std_logic_vector(3 downto 0);
signal addr_y : std_logic_vector(3 downto 0);
signal addr_x2 : std_logic_vector(3 downto 0);
signal addr_y2 : std_logic_vector(3 downto 0);
signal obj_addr_x : std_logic_vector(4 downto 0);
signal obj_addr_x2 : std_logic_vector(4 downto 0);
signal obj_addr_y : std_logic_vector(3 downto 0);
signal obj_addr_y2 : std_logic_vector(3 downto 0);
signal pix_set_x : std_logic;
signal pix_set_y : std_logic;
signal sig_kurzor_x : std_logic_vector(3 downto 0);
signal sig_kurzor_y : std_logic_vector(3 downto 0);
signal kurzor_set_x : std_logic;
signal kurzor_set_y : std_logic;
signal k_set_x : std_logic;
signal k_set_y : std_logic;
signal sig_kset_x : std_logic;
signal sig_kset_y : std_logic;
signal sig_komp_on : std_logic;
signal pre_komp_out : std_logic_vector(5 downto 0);
signal rom_addr : std_logic_vector(11 downto 0);
signal rom_data : std_logic_vector(8 downto 0);
signal game_screens : std_logic_vector(2 downto 0);
begin
pix_x <= PIXEL_X;
pix_y <= PIXEL_Y;
----------------------------------------------------------------------------
-- ZOBRAZOVANI HERNIHO POLE
----------------------------------------------------------------------------
process (CLK)
begin
if rising_edge(CLK) then
case pix_x is
when "0000000000" => -- 0
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(0, 5));
when "0000100000" => -- 32
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(1, 5));
when "0001000000" => -- 64
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(2, 5));
when "0001100000" => -- 96
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(0, 4));
obj_addr_x <= std_logic_vector(to_unsigned(3, 5));
when "0010000000" => -- 128
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(1, 4));
obj_addr_x <= std_logic_vector(to_unsigned(4, 5));
when "0010100000" => -- 160
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(2, 4));
obj_addr_x <= std_logic_vector(to_unsigned(5, 5));
when "0011000000" => -- 192
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(3, 4));
obj_addr_x <= std_logic_vector(to_unsigned(6, 5));
when "0011100000" => -- 224
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(4, 4));
obj_addr_x <= std_logic_vector(to_unsigned(7, 5));
when "0100000000" => -- 256
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(5, 4));
obj_addr_x <= std_logic_vector(to_unsigned(8, 5));
when "0100100000" => -- 288
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(6, 4));
obj_addr_x <= std_logic_vector(to_unsigned(9, 5));
when "0101000000" => -- 320
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(7, 4));
obj_addr_x <= std_logic_vector(to_unsigned(10, 5));
when "0101100000" => -- 352
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(8, 4));
obj_addr_x <= std_logic_vector(to_unsigned(11, 5));
when "0110000000" => -- 384
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(9, 4));
obj_addr_x <= std_logic_vector(to_unsigned(12, 5));
when "0110100000" => -- 416
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(10, 4));
obj_addr_x <= std_logic_vector(to_unsigned(13, 5));
when "0111000000" => -- 448
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(11, 4));
obj_addr_x <= std_logic_vector(to_unsigned(14, 5));
when "0111100000" => -- 480
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(12, 4));
obj_addr_x <= std_logic_vector(to_unsigned(15, 5));
when "1000000000" => -- 512
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(13, 4));
obj_addr_x <= std_logic_vector(to_unsigned(16, 5));
when "1000100000" => -- 544
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(17, 5));
when "1001000000" => -- 576
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(18, 5));
when "1001100000" => -- 608
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(19, 5));
when others =>
pix_set_x <= '0';
k_set_x <= '0';
addr_x <= (others => '0');
obj_addr_x <= (others => '0');
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case pix_y is
when "0000000000" => -- 0
pix_set_y <= '0';
k_set_y <= '1';
addr_y <= (others => '0');
obj_addr_y <= std_logic_vector(to_unsigned(0, 4));
when "0000100000" => -- 32
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(0, 4));
obj_addr_y <= std_logic_vector(to_unsigned(1, 4));
when "0001000000" => -- 64
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(1, 4));
obj_addr_y <= std_logic_vector(to_unsigned(2, 4));
when "0001100000" => -- 96
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(2, 4));
obj_addr_y <= std_logic_vector(to_unsigned(3, 4));
when "0010000000" => -- 128
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(3, 4));
obj_addr_y <= std_logic_vector(to_unsigned(4, 4));
when "0010100000" => -- 160
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(4, 4));
obj_addr_y <= std_logic_vector(to_unsigned(5, 4));
when "0011000000" => -- 192
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(5, 4));
obj_addr_y <= std_logic_vector(to_unsigned(6, 4));
when "0011100000" => -- 224
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(6, 4));
obj_addr_y <= std_logic_vector(to_unsigned(7, 4));
when "0100000000" => -- 256
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(7, 4));
obj_addr_y <= std_logic_vector(to_unsigned(8, 4));
when "0100100000" => -- 288
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(8, 4));
obj_addr_y <= std_logic_vector(to_unsigned(9, 4));
when "0101000000" => -- 320
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(9, 4));
obj_addr_y <= std_logic_vector(to_unsigned(10, 4));
when "0101100000" => -- 352
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(10, 4));
obj_addr_y <= std_logic_vector(to_unsigned(11, 4));
when "0110000000" => -- 384
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(11, 4));
obj_addr_y <= std_logic_vector(to_unsigned(12, 4));
when "0110100000" => -- 416
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(12, 4));
obj_addr_y <= std_logic_vector(to_unsigned(13, 4));
when "0111000000" => -- 448
pix_set_y <= '0';
k_set_y <= '1';
addr_y <= (others => '0');
obj_addr_y <= std_logic_vector(to_unsigned(14, 4));
when others =>
pix_set_y <= '0';
k_set_y <= '0';
addr_y <= (others => '0');
obj_addr_y <= (others => '0');
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1') then
addr_x2 <= addr_x;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1' AND pix_set_y = '1') then
addr_y2 <= addr_y;
end if;
end if;
end process;
ADDR <= addr_y2 & addr_x2;
process (CLK)
begin
if rising_edge(CLK) then
if (k_set_x = '1') then
obj_addr_x2 <= obj_addr_x;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (k_set_x = '1' AND k_set_y = '1') then
obj_addr_y2 <= obj_addr_y;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
PIXEL_SET_X <= pix_set_x;
PIXEL_SET_Y <= pix_set_x AND pix_set_y;
sig_kset_x <= k_set_x;
sig_kset_y <= k_set_x AND k_set_y;
KOMP_SET_X <= sig_kset_x;
KOMP_SET_Y <= sig_kset_y;
end if;
end process;
sig_kurzor_x <= KURZOR_ADDR(3 downto 0);
sig_kurzor_y <= KURZOR_ADDR(7 downto 4);
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1') then
if (sig_kurzor_x = addr_x) then
kurzor_set_x <= '1';
else
kurzor_set_x <= '0';
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1' AND pix_set_y = '1') then
if (sig_kurzor_y = addr_y) then
kurzor_set_y <= '1';
else
kurzor_set_y <= '0';
end if;
end if;
end if;
end process;
KURZOR <= kurzor_set_x AND kurzor_set_y;
----------------------------------------------------------------------------
-- ZOBRAZOVANI OBJEKTU MIMO HERNI POLE VCETNE MEZI HERNICH OBRAZOVEK
----------------------------------------------------------------------------
-- Nastaveni cteci pameti
rom_addr <= SCREEN_CODE & obj_addr_y2 & obj_addr_x2;
rom_screen_i : entity work.BRAM_ROM_SCREEN
port map (
CLK => CLK,
ROM_ADDR => rom_addr,
ROM_DOUT => rom_data
);
pre_komp_out <= rom_data(8 downto 3);
with rom_data(2 downto 0) select
KOMP_OUT <= pre_komp_out when "100",
KOMP0 when "101",
KOMP1 when "110",
KOMP2 when "111",
KOMP3 when "001",
KOMP4 when "010",
"000000" when others;
-- aktivní, když se vykreslují roury mimo herní plochu
with rom_data(2 downto 0) select
sig_komp_on <= '1' when "100",
'1' when "101",
'1' when "110",
'1' when "111",
'1' when "001",
'1' when "010",
'0' when others;
KOMP_ON <= sig_komp_on;
KOMP4_IS <= '1' when (rom_data(2 downto 0) = "010") else '0';
end FULL;
| mit |
jeffmagina/ECE368 | Lab1/ALU/alu_arithmetic_unit.vhd | 1 | 1599 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
| mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/DEBUG_CONTROLLER.vhd | 2 | 2079 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:26:35 02/25/2015
-- Design Name:
-- Module Name: DEBUG_CONTROLLER - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEBUG_CONTROLLER is
Port( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0));
end DEBUG_CONTROLLER;
architecture Structural of DEBUG_CONTROLLER is
signal RD : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal KEY_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal TO_SEG : STD_LOGIC_VECTOR(15 downto 0);
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
U1: entity work.KEYBOARD_CONTROLLER
Port MAP ( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE);
U2: entity work.ASCII_BUFFER
port MAP(
ASCII_DATA => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => TO_SEG);
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => TO_SEG(15 downto 12),
SEG_1 => TO_SEG(11 downto 8),
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
end Structural;
| mit |
gustavogarciautp/Procesador | Entrega 1/OMUXT.vhd | 3 | 434 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OMUXT is
Port ( Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
SEUimm: in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
oper2 : out STD_LOGIC_VECTOR (31 downto 0));
end OMUXT;
architecture Behavioral of OMUXT is
begin
process(Crs2,SEUimm,i)
begin
if i='0' then
Oper2<=Crs2;
else
Oper2<=SEUimm;
end if;
end process;
end Behavioral; | mit |
KPU-RISC/KPU | VHDL/InstructionDecoder.vhd | 1 | 69353 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/23/2015 03:41:27 PM
-- Design Name:
-- Module Name: InstructionDecoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionDecoder is
port
(
TimingSignals : in BIT_VECTOR(7 downto 0); -- The 8 different timing states
Instruction : in BIT_VECTOR(7 downto 0); -- The instruction to execute
Flags : in BIT_VECTOR(7 downto 0); -- Content of the FLAGS register - needed for conditional jumps
-- ==============================================================
-- The various control lines of the CPU which go low/high
-- depending on the timing state and the instruction to execute:
-- ==============================================================
Load_PC : out BIT;
Select_PC : out BIT;
Load_SRAM: out BIT;
Select_SRAM: out BIT;
Return_SRAM: out BIT;
Load_INC: out BIT;
Select_INC: out BIT;
Load_INSTR: out BIT;
Select_INSTR_To_DataBus: out BIT;
Select_INSTR_To_ALU: out BIT;
Load_A_From_DataBus: out BIT;
Select_A_To_ALU: out BIT;
Load_B_From_DataBus: out BIT;
Select_B_To_ALU: out BIT;
Load_C_From_DataBus: out BIT;
Load_InternalA_From_DataBus: out BIT;
Select_InternalA_To_DataBus: out BIT;
Load_Flags: out BIT;
Select_A_To_DataBus: out BIT;
Select_B_To_DataBus: out BIT;
Select_C_To_DataBus: out BIT;
Load_D_From_DataBus: out BIT;
Select_D_To_DataBus: out BIT;
Load_E_From_DataBus: out BIT;
Select_E_To_DataBus: out BIT;
Load_F_From_DataBus: out BIT;
Select_F_To_DataBus: out BIT;
Load_G_From_DataBus: out BIT;
Select_G_To_DataBus: out BIT;
Load_H_From_DataBus: out BIT;
Select_H_To_DataBus: out BIT;
load_M_From_AddressBus: out BIT;
select_M_To_AddressBus: out BIT;
load_XL_From_DataBus: out BIT;
load_XH_From_DataBus: out BIT;
load_X_From_AddressBus: out BIT;
select_XL_To_DataBus: out BIT;
select_XH_To_DataBus: out BIT;
select_X_To_AddressBus: out BIT;
Load_J_From_AddressBus: out BIT;
Select_J_To_AddressBus: out BIT;
Load_SP_From_AddressBus: out BIT;
Select_SP_To_AddressBus: out BIT;
Load_BP_From_AddressBus: out BIT;
Select_BP_To_AddressBus: out BIT;
Load_Y_From_AddressBus: out BIT;
Select_Y_To_AddressBus: out BIT;
Load_Z_From_AddressBus: out BIT;
Select_Z_To_AddressBus: out BIT;
Load_Adder16Bit_InputA: out BIT;
Select_Adder16Bit_InputA: out BIT;
Load_Adder16Bit_InputB: out BIT;
Select_Adder16Bit_InputB: out BIT;
Load_Adder16Bit_OutputC: out BIT;
Select_Adder16Bit_OutputC: out BIT;
load_FlagsSaved_From_FlagsRegister: out BIT;
load_FlagsSaved_To_FlagsRegister: out BIT;
Load_FlagsFromDataBus: out BIT;
Select_FlagsToFlagsBus: out BIT;
Load_FlagsFromFlagsBus: out BIT;
Select_FlagsToDataBus: out BIT;
Select_Flags: out BIT;
Select_PortA_To_DataBus: out BIT;
Select_PortB_To_DataBus: out BIT;
Load_PortC_From_DataBus: out BIT;
Load_PortD_From_DataBus: out BIT;
StopCPU: out BIT
);
end InstructionDecoder;
architecture Behavioral of InstructionDecoder is
component Decoder3to8 is
Port
(
F : in BIT_VECTOR(2 downto 0); -- 3-Bit Function Code (Input)
X : out BIT_VECTOR(7 downto 0); -- 8-Bit State (Output)
Started: in BIT -- Is the CPU already running?
);
end component Decoder3to8;
signal NegatedInstruction : BIT_VECTOR(7 downto 0);
signal NegatedFlags : BIT_VECTOR(7 downto 0);
signal instruction_SETAB: BIT;
signal instruction_ALU: BIT;
signal instruction_MOV: BIT;
signal instruction_MOV16: BIT;
signal instruction_LOAD: BIT;
signal instruction_STORE: BIT;
signal instruction_JMP: BIT;
signal instruction_HLT: BIT;
signal instruction_JZ: BIT;
signal instruction_JNZ: BIT;
signal instruction_JNS: BIT;
signal instruction_JNC: BIT;
signal instruction_SAVE_FLAGS: BIT;
signal instruction_RESTORE_FLAGS: BIT;
signal instruction_NOP: BIT;
signal instruction_FLAGS_TO_OUTBUFFER: BIT;
signal instruction_INBUFFER_TO_FLAGS: BIT;
signal instruction_ADDER_16BIT: BIT;
signal instruction_STORE_FLAGS: BIT;
signal instruction_LOAD_FLAGS: BIT;
signal instruction_IN: BIT;
signal instruction_OUT: BIT;
-- Internal ALU instructions
signal instruction_MOV_ALU_IN: BIT;
signal instruction_MOV_ALU_OUT: BIT;
signal instruction_MOV_ALU_C_TO_AB: BIT;
signal MOV_DestinationRegister: BIT_VECTOR(7 downto 0);
signal MOV_SourceRegister: BIT_VECTOR(7 downto 0);
signal MOV16_DestinationRegister: BIT_VECTOR(7 downto 0);
signal MOV16_SourceRegister: BIT_VECTOR(7 downto 0);
-- Used by the Fetch/Increment cycle
signal Select_SRAM_FETCH: BIT;
signal Load_PC_FETCH: BIT;
signal Select_PC_FETCH: BIT;
signal Return_SRAM_FETCH: BIT;
-- Used by the SETAB opcode
signal Load_A_From_DataBus_SETAB: BIT;
signal Load_B_From_DataBus_SETAB: BIT;
-- Used by the ALU opcode
signal Load_C_From_DataBus_ALU: BIT;
signal Load_Flags_From_ALU: BIT;
-- Used by the MOV opcode
signal Select_D_To_DataBus_MOV: BIT;
signal Select_E_To_DataBus_MOV: BIT;
signal Select_F_To_DataBus_MOV: BIT;
signal Select_G_To_DataBus_MOV: BIT;
signal Select_H_To_DataBus_MOV: BIT;
signal Select_SP_To_DataBus_MOV: BIT;
signal Select_XL_To_DataBus_MOV: BIT;
signal Select_XH_To_DataBus_MOV: BIT;
signal Load_D_From_DataBus_MOV: BIT;
signal Load_E_From_DataBus_MOV: BIT;
signal Load_F_From_DataBus_MOV: BIT;
signal Load_G_From_DataBus_MOV: BIT;
signal Load_H_From_DataBus_MOV: BIT;
signal Load_SP_From_DataBus_MOV: BIT;
signal Load_XL_From_DataBus_MOV: BIT;
signal Load_XH_From_DataBus_MOV: BIT;
signal Load_J_From_DataBus_MOV: BIT;
-- Used by the MOV16 opcode
signal Select_M_To_AddressBus_MOV16: BIT;
signal Select_X_To_AddressBus_MOV16: BIT;
signal Load_M_From_AddressBus_MOV16: BIT;
signal Load_X_From_AddressBus_MOV16: BIT;
signal Select_J_To_AddressBus_MOV16: BIT;
signal Load_J_From_AddressBus_MOV16: BIT;
signal Select_SP_To_AddressBus_MOV16: BIT;
signal Load_SP_From_AddressBus_MOV16: BIT;
signal Select_PC_To_AddressBus_MOV16: BIT;
signal Load_PC_From_AddressBus_MOV16: BIT;
signal Select_BP_To_AddressBus_MOV16: BIT;
signal Load_BP_From_AddressBus_MOV16: BIT;
signal Select_Y_To_AddressBus_MOV16: BIT;
signal Load_Y_From_AddressBus_MOV16: BIT;
signal Select_Z_To_AddressBus_MOV16: BIT;
signal Load_Z_From_AddressBus_MOV16: BIT;
-- Used by the LOAD opcode
signal Select_SRAM_LOAD: BIT;
signal Return_SRAM_LOAD: BIT;
signal Load_D_From_DataBus_LOAD: BIT;
signal Load_E_From_DataBus_LOAD: BIT;
signal Load_F_From_DataBus_LOAD: BIT;
signal Load_G_From_DataBus_LOAD: BIT;
signal Load_H_From_DataBus_LOAD: BIT;
signal Load_XL_From_DataBus_LOAD: BIT;
signal Load_XH_From_DataBus_LOAD: BIT;
signal Select_M_To_AddressBus_LOAD: BIT;
-- Used by the STORE opcode
signal Load_SRAM_LOAD: BIT;
signal Select_D_To_DataBus_STORE: BIT;
signal Select_E_To_DataBus_STORE: BIT;
signal Select_F_To_DataBus_STORE: BIT;
signal Select_G_To_DataBus_STORE: BIT;
signal Select_H_To_DataBus_STORE: BIT;
signal Select_XL_To_DataBus_STORE: BIT;
signal Select_XH_To_DataBus_STORE: BIT;
signal Select_M_To_AddressBus_STORE: BIT;
signal Load_SRAM_STORE: BIT;
-- Used by the LOAD_FLAGS opcode
signal Load_SRAM_STORE_FLAGS: BIT;
signal Select_M_To_AddressBus_STORE_FLAGS: BIT;
-- Used by the STORE_FLAGS opcode
signal Select_SRAM_LOAD_FLAGS: BIT;
signal Select_M_To_AddressBus_LOAD_FLAGS: BIT;
signal Return_SRAM_LOAD_FLAGS: BIT;
-- Used by the JMP opcode
signal Load_PC_JMP: BIT;
signal Select_J_To_AddressBus_JMP: BIT;
-- Used by the JZ opcode
signal Load_PC_JZ: BIT;
signal Select_J_To_AddressBus_JZ: BIT;
signal Select_Flags_JZ: BIT;
-- Used by the JNS opcode
signal Load_PC_JNS: BIT;
signal Select_J_To_AddressBus_JNS: BIT;
signal Select_Flags_JNS: BIT;
-- Used by the JNC opcode
signal Load_PC_JNC: BIT;
signal Select_J_To_AddressBus_JNC: BIT;
signal Select_Flags_JNC: BIT;
-- Used by the JNZ opcode
signal Load_PC_JNZ: BIT;
signal Select_J_To_AddressBus_JNZ: BIT;
signal Select_Flags_JNZ: BIT;
-- Used by the SAVE_FLAGS opcode
signal Select_Flags_SAVE_FLAGS: BIT;
-- Used by the RESTORE_FLAGS opcode
signal Load_Flags_SAVE_FLAGS: BIT;
-- Used by the INBUFFER_TO_FLAGS opcode
signal Load_Flags_INBUFFER_TO_FLAGS: BIT;
-- Used by the FLAGS_TO_DATABUS opcode
signal Select_Flags_FLAGS_TO_OUTBUFFER: BIT;
-- Used by the MOV_ALU_IN opcode
signal Select_D_To_DataBus_MOV_ALU_IN: BIT;
signal Select_E_To_DataBus_MOV_ALU_IN: BIT;
signal Select_F_To_DataBus_MOV_ALU_IN: BIT;
signal Select_G_To_DataBus_MOV_ALU_IN: BIT;
signal Select_H_To_DataBus_MOV_ALU_IN: BIT;
signal Select_XL_To_DataBus_MOV_ALU_IN: BIT;
signal Select_XH_To_DataBus_MOV_ALU_IN: BIT;
signal Select_SP_To_DataBus_MOV_ALU_IN: BIT;
signal Load_A_From_DataBus_MOV_ALU_IN: BIT;
signal Load_B_From_DataBus_MOV_ALU_IN: BIT;
signal MOV_ALU_IN_SourceRegister: BIT_VECTOR(7 downto 0);
-- Used by the MOV_ALU_OUT opcode
signal Load_D_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_E_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_F_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_G_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_H_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_XL_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_XH_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_SP_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_J_From_DataBus_MOV_ALU_OUT: BIT;
signal Select_C_To_DataBus_MOV_ALU_OUT: BIT;
signal MOV_ALU_OUT_DestinationRegister: BIT_VECTOR(7 downto 0);
-- Used by the MOV_ALU_C_TO_AB opcode
signal Load_A_From_DataBus_MOV_ALU_C_TO_AB: BIT;
signal Load_B_From_DataBus_MOV_ALU_C_TO_AB: BIT;
signal Select_C_To_DataBus_MOV_ALU_C_TO_AB: BIT;
-- Used by the ADDER_16BIT opcode
signal Select_D_To_DataBus_ADDER_16BIT: BIT;
signal Select_X_To_AddressBus_ADDER_16BIT: BIT;
signal Load_X_From_AddressBus_ADDER_16BIT: BIT;
signal Select_J_To_AddressBus_ADDER_16BIT: BIT;
-- Used by the IN opcode
signal Load_XL_From_DataBus_IN: BIT;
-- Used by the OUT opcode
signal Select_XL_To_DataBus_OUT: BIT;
begin
-- Negate the instruction, so that we can afterwards probe
-- for a specific instruction
NegatedInstruction <= not(Instruction);
-- Negate the FLAGS
NegatedFlags <= not(Flags);
-- ================================================================
-- The following section implements the Fetch/Increment operations
-- ================================================================
Load_PC_FETCH <= TimingSignals(2); -- State #3
Select_PC_FETCH <= TimingSignals(0) or -- State #1
TimingSignals(1); -- State #2
-- We request the data from the RAM in the states #1 and #2
Select_SRAM_FETCH <= TimingSignals(0) or -- State #1
TimingSignals(1); -- State #2
-- Because the RAM has a latency of 1 clock cycle, we only return the
-- requested data from the RAM in state #2 (data in state #1 is still unstable!!!)
Return_SRAM_FETCH <= TimingSignals(1); -- State #2
Load_INC <= TimingSignals(0); -- State #1
Select_INC <= TimingSignals(2); -- State #3
Load_INSTR <= TimingSignals(1); -- State #2
-- ============================================================
-- Now we have to decode the instruction to enable the correct
-- Control Lines based on the provided timing signal
-- ============================================================
-- ---------------------------------------
-- Instruction "SETAB" - Format: 111DVVVV
-- ---------------------------------------
-- 111: OpCode
-- D: Destination ('0' = Register A, '1' = Register B)
-- VVVV: 4-bit value
-- Check if we execute the "SETAB" instruction - OpCode "111"
instruction_SETAB <= Instruction(7) and Instruction(6) and Instruction(5);
-- The "Select_INSTR" control line goes high, when we execute the
-- instruction "SETAB" and the time state is #4
-- This gates the instruction from the instruction register onto the data bus
Select_INSTR_To_DataBus <= instruction_SETAB and TimingSignals(3);
-- The instruction from the data bus is loaded into the register "Internal A"
Load_InternalA_From_DataBus <= instruction_SETAB and TimingSignals(3);
-- The first 4 bits from the register "Internal A" are gated back to the data bus
Select_InternalA_To_DataBus <= instruction_SETAB and TimingSignals(4);
-- The "Load_A" control line goes high, when we execute the
-- instruction "SETAB" and the time state is #4
-- This loads the data currently stored on the data bus into the Register "A"
Load_A_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and NegatedInstruction(4);
-- The "Load_B" control line goes high, when we execute the
-- instruction "SETAB" and the time state is #4
-- This loads the data currently stored on the data bus into the Register "B"
Load_B_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and Instruction(4);
-- ---------------------------------------
-- Instruction "ALU" - Format: 1000FFFF
-- ---------------------------------------
-- 1000: OpCode
-- FFFF: 4-bit function code
-- Check if we execute the "ALU" instruction - OpoCode "1000"
instruction_ALU <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and NegatedInstruction(4);
instruction_NOP <= NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0);
-- The "Select_A_To_ALU" and "Select_B_To_ALU" control lines are going high, when we execute
-- the instruction "ALU" and the time state is #4 or #5.
-- This transfers the content of the Register A and Register B into the ALU
-- for execution.
Select_A_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4));
Select_B_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4));
-- The "SELECT_INSTR" control line goes high, when we execute the instruction "ALU"
-- and the time state is #4 or #5.
-- This transfers the 4-bit function code of the Instruction Register into the ALU
-- for execution.
Select_INSTR_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4));
-- The "Select C" control line goes high, when we execute the instruction
-- "ALU" and the time state is #5.
-- This transfers the result of the ALU into the Register C.
Load_C_From_DataBus_ALU <= instruction_ALU and TimingSignals(4);
-- This transfers the result of the ALU Flags into the register FLAGS
Load_Flags_From_ALU <= instruction_ALU and TimingSignals(4) and not(instruction_NOP);
-- -------------------------------------------------
-- Instruction "MOV_ALU_C_TO_AB" - Format: 1010111D
-- -------------------------------------------------
-- 1010111: OpCode
-- D: Destination Register
-- => "0": Register A
-- => "1": Register B
-- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "1010111"
instruction_MOV_ALU_C_TO_AB <= Instruction(7) and
NegatedInstruction(6) and
Instruction(5) and
NegatedInstruction(4) and
Instruction(3) and
Instruction(2) and
Instruction(1);
Load_A_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5));
Load_B_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and Instruction(0) and (TimingSignals(4) or TimingSignals(5));
-- Select the register C of the ALU to the data bus
Select_C_To_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and (TimingSignals(4) or TimingSignals(5));
-- --------------------------------------------
-- Instruction "MOV_ALU_OUT" - Format: 11011DDD
-- --------------------------------------------
-- 11011: OpCode
-- DDD: Destination Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "11011"
instruction_MOV_ALU_OUT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
Instruction(4) and
Instruction(3);
-- Decode the destination and source register from the provided instruction
DestinationRegisterDecoder_MOV_ALU_OUT: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_OUT_DestinationRegister, '1');
-- Load the specified register from the data bus
Load_D_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(0) and (TimingSignals(4) or TimingSignals(5));
Load_E_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(1) and (TimingSignals(4) or TimingSignals(5));
Load_F_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(2) and (TimingSignals(4) or TimingSignals(5));
Load_G_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(3) and (TimingSignals(4) or TimingSignals(5));
Load_H_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(4) and (TimingSignals(4) or TimingSignals(5));
Load_XL_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(6) and (TimingSignals(4) or TimingSignals(5));
Load_XH_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Select the register C of the ALU to the data bus
Select_C_To_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and (TimingSignals(4) or TimingSignals(5));
-- --------------------------------------------
-- Instruction "MOV_ALU_IN" - Format: 1011DSSS
-- --------------------------------------------
-- 1011: OpCode
-- D: Destination Register
-- => "0": Register A
-- => "1": Register B
-- SSS: Source Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "MOV_ALU_IN" instruction - OpCode "1011"
instruction_MOV_ALU_IN <= Instruction(7) and
NegatedInstruction(6) and
Instruction(5) and
Instruction(4);
-- Decode the destination and source register from the provided instruction
SourceRegisterDecoder_MOV_ALU_IN: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_IN_SourceRegister, '1');
-- Latch the specified register onto the data bus
Select_D_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5));
Select_E_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5));
Select_F_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5));
Select_G_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5));
Select_H_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5));
Select_XL_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5));
Select_XH_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Load the specified register from the data bus
Load_A_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and NegatedInstruction(3) and TimingSignals(4);
Load_B_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and Instruction(3) and TimingSignals(4);
-- ---------------------------------------
-- Instruction "MOV" - Format: 00DDDSSS
-- ---------------------------------------
-- 00: OpCode
-- DDD: Destination Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- SSS: Source Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "MOV" instruction - OpCode "00"
instruction_MOV <= NegatedInstruction(7) and NegatedInstruction(6);
-- Decode the destination and source register from the provided instruction
DestinationRegisterDecoder: Decoder3to8 port map(Instruction(5 downto 3), MOV_DestinationRegister, '1');
SourceRegisterDecoder: Decoder3to8 port map(Instruction(2 downto 0), MOV_SourceRegister, '1');
-- Gate the specified register onto the data bus
Select_D_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5));
Select_E_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5));
Select_F_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5));
Select_G_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5));
Select_H_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5));
Select_XL_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5));
Select_XH_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Load the specified register from the data bus
Load_D_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(0) and TimingSignals(4);
Load_E_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(1) and TimingSignals(4);
Load_F_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(2) and TimingSignals(4);
Load_G_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(3) and TimingSignals(4);
Load_H_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(4) and TimingSignals(4);
Load_XL_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(6) and TimingSignals(4);
Load_XH_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(7) and TimingSignals(4);
-- ---------------------------------------
-- Instruction "MOV16" - Format: 01DDDSSS
-- ---------------------------------------
-- 01: OpCode
-- DDD: Destination Register
-- => "000": Register M
-- => "001": Register X
-- => "010": Register J
-- => "011": Register SP
-- => "100": Register PC
-- => "101": Register BP
-- => "110": Register Y
-- => "111": Register Z
-- SSS: Source Register
-- => "000": Register M
-- => "001": Register X
-- => "010": Register J
-- => "011": Register SP
-- => "100": Register PC
-- => "101": Register BP
-- => "110": Register Y
-- => "111": Register Z
-- Check if we execute the "MOV16" instruction - OpCode "01"
instruction_MOV16 <= NegatedInstruction(7) and Instruction(6);
-- Decode the destination and source register from the provided instruction
DestinationRegisterDecoderMOV16: Decoder3to8 port map(Instruction(5 downto 3), MOV16_DestinationRegister, '1');
SourceRegisterDecoderMOV16: Decoder3to8 port map(Instruction(2 downto 0), MOV16_SourceRegister, '1');
-- Gate the specified register onto the data bus
Select_M_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5));
Select_X_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5));
Select_J_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5));
Select_SP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5));
Select_PC_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5));
Select_BP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(5) and (TimingSignals(4) or TimingSignals(5));
Select_Y_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5));
Select_Z_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Load the specified register from the data bus
Load_M_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(0) and TimingSignals(4);
Load_X_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(1) and TimingSignals(4);
Load_J_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(2) and TimingSignals(4);
Load_SP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(3) and TimingSignals(4);
Load_PC_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(4) and TimingSignals(4);
Load_BP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(5) and TimingSignals(4);
Load_Y_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(6) and TimingSignals(4);
Load_Z_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(7) and TimingSignals(4);
-- -------------------------------------
-- Instruction "HLT" - Format: 11000011
-- -------------------------------------
-- Stops the execution of the CPU.
-- 11010011: OpCode
-- Check if we execute the "HLT" instruction - OpCode "11010011"
instruction_HLT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0);
-- Stops the CPU execution
StopCPU <= instruction_HLT;
-- ---------------------------------------
-- Instruction "LOAD" - Format: 10010DDD
-- ---------------------------------------
-- Loads a 8-bit value from SRAM memory into the specified register.
-- The SRAM memory address is stored in the register "M".
-- The transfer of the data to the register from the SRAM memory is done through the data bus.
-- 10010: OpCode
-- DDD: Destination Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not used...>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "LOAD" instruction - OpCode "10010"
instruction_LOAD <= Instruction(7) and
NegatedInstruction(6) and
NegatedInstruction(5) and
Instruction(4) and
NegatedInstruction(3);
-- Latch the SRAM memory address from register M onto the address bus
Select_M_To_AddressBus_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5));
-- Request the 8-bit from the RAM memory in the states #5, #6, and #7
Select_SRAM_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5) or TimingSignals(6));
-- Because the RAM has a latency of 1 clock cycle, we only return the
-- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!)
-- This finally places the requested RAM data onto the data bus
Return_SRAM_LOAD <= TimingSignals(6); -- State #7
-- Load the Register D from the data bus
Load_D_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Load the Register E from the data bus
Load_E_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
-- Load the Register F from the data bus
Load_F_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Load the Register G from the data bus
Load_G_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0);
-- Load the Register H from the data bus
Load_H_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
Instruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Load the Register XL from the data bus
Load_XL_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
Instruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Load the Register XL from the data bus
Load_XH_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
Instruction(2) and
Instruction(1) and
Instruction(0);
-- ---------------------------------------
-- Instruction "STORE" - Format: 10011SSS
-- ---------------------------------------
-- Save a 8-bit value to SRAM memory from the specified register.
-- The SRAM memory address is stored in the register "M".
-- The transfer of the data from the register into the SRAM memory is done through the data bus.
-- 10011: OpCode
-- SSS: Source Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not used...>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "STORE" instruction - OpCode "10011"
instruction_STORE <= Instruction(7) and
NegatedInstruction(6) and
NegatedInstruction(5) and
Instruction(4) and
Instruction(3);
-- Selects the content of the register "M" onto the address bus
Select_M_To_AddressBus_STORE <= instruction_STORE and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register D to the data bus
Select_D_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register E to the data bus
Select_E_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register F to the data bus
Select_F_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register G to the data bus
Select_G_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register H to the data bus
Select_H_To_DataBus_STORE <= instruction_STORE and
Instruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register XL to the data bus
Select_XL_To_DataBus_STORE <= instruction_STORE and
Instruction(2) and
Instruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register XH to the data bus
Select_XH_To_DataBus_STORE <= instruction_STORE and
Instruction(2) and
Instruction(1) and
Instruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Enables the Load Line of the RAM memory and transfers the data from the data bus into
-- the memory address provided in register M
Load_SRAM_STORE <= instruction_STORE and
TimingSignals(5);
-- ---------------------------------------------
-- Instruction "STORE_FLAGS" - Format: 11001001
-- ---------------------------------------------
-- Selects the flags from the "FlagsOutBuffer" register onto the data bus
-- and stores it in the RAM.
-- 11001001: OpCode
-- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001001"
instruction_STORE_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
-- Selects the content of the register "M" onto the address bus
Select_M_To_AddressBus_STORE_FLAGS <= instruction_STORE_FLAGS and
(TimingSignals(4) or TimingSignals(5));
-- Selects the flags from the "FlagsOutBuffer" onto the data bus
Select_FlagsToDataBus <= instruction_STORE_FLAGS and
(TimingSignals(4) or TimingSignals(5));
-- Enables the Load Line of the RAM memory and transfers the data from the data bus into
-- the memory address provided in register M
Load_SRAM_STORE_FLAGS <= instruction_STORE_FLAGS and
TimingSignals(5);
-- ---------------------------------------------
-- Instruction "LOAD_FLAGS" - Format: 11001010
-- ---------------------------------------------
-- Loads the flags from the RAM and writes them into the "FlagsInBuffer" register.
-- and stores it onto the stack
-- 11001010: OpCode
-- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001010"
instruction_LOAD_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Latch the SRAM memory address from register M onto the address bus
Select_M_To_AddressBus_LOAD_FLAGS <= instruction_LOAD_FLAGS and
(TimingSignals(4) or TimingSignals(5));
-- Request the 8-bit from the RAM memory in the states #5, #6, and #7
Select_SRAM_LOAD_FLAGS <= instruction_LOAD_FLAGS and
(TimingSignals(4) or TimingSignals(5) or TimingSignals(6));
-- Because the RAM has a latency of 1 clock cycle, we only return the
-- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!)
-- This finally places the requested RAM data onto the data bus
Return_SRAM_LOAD_FLAGS <= TimingSignals(6); -- State #7
-- Selects the flags from the "FlagsOutBuffer" onto the data bus
Load_FlagsFromDataBus <= instruction_LOAD_FLAGS and
TimingSignals(6);
-- ---------------------------------------
-- Instruction "JMP" - Format: 11000010
-- ---------------------------------------
-- Unconditional jump to the address in the program code that is stored in the register "J".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11000010: OpCode
-- Check if we execute the "JMP" instruction - OpCode "11000010"
instruction_JMP <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JMP <= instruction_JMP and
(TimingSignals(4) or TimingSignals(5));
-- Load the Program Counter from the address bus
Load_PC_JMP <= instruction_JMP and
TimingSignals(5);
-- --------------------------------------------
-- Instruction "SAVE_FLAGS" - Format: 11000100
-- --------------------------------------------
-- Saves the current content of the flags register into the "SavedFlags" register
-- 11000100: OpCode
-- Check if we execute the "SAVE_FLAGS" instruction - OpCode "11000100"
instruction_SAVE_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Enables the Select Line of the flags register to load the flags into the "SavedFlags" register
Select_Flags_SAVE_FLAGS <= instruction_SAVE_FLAGS and
TimingSignals(4);
-- Enables the Load Line of the "SavedFlags" register to load the flags into the "SavedFlags" register
Load_FlagsSaved_From_FlagsRegister <= instruction_SAVE_FLAGS and
TimingSignals(4);
-- -----------------------------------------------
-- Instruction "RESTORE_FLAGS" - Format: 11000101
-- -----------------------------------------------
-- Saves the current content of the flags register into the "SavedFlags" register
-- 11000101: OpCode
-- Check if we execute the "RESTORE_FLAGS" instruction - OpCode "11000101"
instruction_RESTORE_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
NegatedInstruction(1) and
Instruction(0);
-- Enables the Load Line of the flags register to load the "SavedFlags" register into the flags register
Load_Flags_SAVE_FLAGS <= instruction_RESTORE_FLAGS and
TimingSignals(4);
-- Enables the Select Line of the "SavedFlags" register to load the "SavedFlags" register into the flags register
Load_FlagsSaved_To_FlagsRegister <= instruction_RESTORE_FLAGS and
TimingSignals(4);
-- ----------------------------------------------------
-- Instruction "FLAGS_TO_OUTBUFFER" - Format: 11000110
-- ----------------------------------------------------
-- Writes the current content of the flags register onto the data bus
-- 11000110: OpCode
-- Check if we execute the "FLAGS_TO_OUTBUFFER" instruction - OpCode "11000110"
instruction_FLAGS_TO_OUTBUFFER <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Selects the content from the Flags register onto the Flags Bus
Select_Flags_FLAGS_TO_OUTBUFFER <= instruction_FLAGS_TO_OUTBUFFER and
TimingSignals(4);
-- Loads the content from the Flags Bus into the "FlagsOutBuffer" register
Load_FlagsFromFlagsBus <= instruction_FLAGS_TO_OUTBUFFER and
TimingSignals(4);
-- ---------------------------------------------------
-- Instruction "INBUFFER_TO_FLAGS" - Format: 11000111
-- ---------------------------------------------------
-- Writes the current content of the flags register onto the data bus
-- 11000111: OpCode
-- Check if we execute the "FLAGS_TO_INBUFFER" instruction - OpCode "11000111"
instruction_INBUFFER_TO_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
Instruction(1) and
Instruction(0);
-- Selects the content from the "FlagsInBuffer" register to the Flags Bus
Select_FlagsToFlagsBus <= instruction_INBUFFER_TO_FLAGS and
TimingSignals(4);
-- Loads the content from the Flags Bus into the Flags register
Load_Flags_INBUFFER_TO_FLAGS <= instruction_INBUFFER_TO_FLAGS and
TimingSignals(4);
-- ---------------------------------------
-- Instruction "JZ" - Format: 11000000
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Zero-Flag in the FLAGS register is set to "1".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11000000: OpCode
-- Check if we execute the "JZ" instruction - OpCode "11000000"
instruction_JZ <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
Select_Flags_JZ <= instruction_JZ and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JZ <= instruction_JZ and
Flags(1) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JZ <= instruction_JZ and
Flags(1) and
TimingSignals(7);
-- ---------------------------------------
-- Instruction "JNS" - Format: 11001011
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Sign-Flag in the FLAGS register is set to "0".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11001011: OpCode
-- Check if we execute the "JNS" instruction - OpCode "11001011"
instruction_JNS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0);
Select_Flags_JNS <= instruction_JNS and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JNS <= instruction_JNS and
(not Flags(0)) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JNS <= instruction_JNS and
(not Flags(0)) and
TimingSignals(7);
-- ---------------------------------------
-- Instruction "JNC" - Format: 11010001
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Carry-Flag in the FLAGS register is set to "0".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11001011: OpCode
-- Check if we execute the "JNC" instruction - OpCode "11010001"
instruction_JNC <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
Instruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
Select_Flags_JNC <= instruction_JNC and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JNC <= instruction_JNC and
(not Flags(2)) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JNC <= instruction_JNC and
(not Flags(2)) and
TimingSignals(7);
-- ---------------------------------------
-- Instruction "JNZ" - Format: 11000001
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Zero-Flag in the FLAGS register is set to "0".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11000001: OpCode
-- Check if we execute the "JNZ" instruction - OpCode "11000001"
instruction_JNZ <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
Select_Flags_JNZ <= instruction_JNZ and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JNZ <= instruction_JNZ and
NegatedFlags(1) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JNZ <= instruction_JNZ and
NegatedFlags(1) and
TimingSignals(7);
-- ---------------------------------------------
-- Instruction "16BIT_ADDER" - Format: 11001000
-- ---------------------------------------------
-- Performs a 16-bit addition between the 16-bit value in register "X" and the
-- 8-bit value in register "D".
-- The result of the addition is put back into register "X".
-- 11001000: OpCode
-- Check if we execute the "16BIT_ADDER" instruction - OpCode "11001000"
instruction_ADDER_16BIT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Select the content of register "X" to the address bus
Select_X_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and
TimingSignals(3);
-- Load the A input of the 16-bit Adder from the address bus
Load_Adder16Bit_InputA <= instruction_ADDER_16BIT and
TimingSignals(3);
-- Select the content of register "J" to the address bus
Select_J_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and
TimingSignals(4);
-- Load the B input of the 16-bit Adder from the address bus
Load_Adder16Bit_InputB <= instruction_ADDER_16BIT and
TimingSignals(4);
-- Select the A input into the 16-bit Adder
Select_Adder16Bit_InputA <= instruction_ADDER_16BIT and
(TimingSignals(5) or TimingSignals(6));
-- Select the B input into the 16-bit Adder
Select_Adder16Bit_InputB <= instruction_ADDER_16BIT and
(TimingSignals(5) or TimingSignals(6));
-- Load the output from the 16-bit adder into the C output
Load_Adder16Bit_OutputC <= instruction_ADDER_16BIT and
TimingSignals(6);
-- Select the output from the C output onto the address bus
Select_Adder16Bit_OutputC <= instruction_ADDER_16BIT and
TimingSignals(7);
-- Load the content from the address bus into the register "X"
Load_X_From_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and
TimingSignals(7);
-- ---------------------------------------------
-- Instruction "IN" - Format: 1100110P
-- ---------------------------------------------
-- Reads from the specified input port and places the read value into the specified register.
-- 1100110P: OpCode
-- P: Port - "0" -> Input Port A, "1" -> Input Port B
-- Check if we execute the "IN" instruction - OpCode "1101"
instruction_IN <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
Instruction(2) and
NegatedInstruction(1);
-- Select the input value from Input Port A to the data bus
Select_PortA_To_DataBus <= instruction_IN and
NegatedInstruction(0) and
(TimingSignals(3) or TimingSignals(4));
-- Select the input value from Input Port B to the data bus
Select_PortB_To_DataBus <= instruction_IN and
Instruction(0) and
(TimingSignals(3) or TimingSignals(4));
-- Load the Register XL from the data bus
Load_XL_From_DataBus_IN <= instruction_IN and
TimingSignals(4);
-- ---------------------------------------------
-- Instruction "OUT" - Format: 1100111P
-- ---------------------------------------------
-- Reads from the specified input port and places the read value into the specified register.
-- 1100111P: OpCode
-- P: Port - "0" -> Output Port C, "1" -> Output Port D
-- Check if we execute the "IN" instruction - OpCode "1100111"
instruction_OUT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
Instruction(2) and
Instruction(1);
-- Select the register XL to the data bus
Select_XL_To_DataBus_OUT <= instruction_OUT and
(TimingSignals(3) or TimingSignals(4));
-- Select the output value from the data bus into the Output Port C
Load_PortC_From_DataBus <= instruction_OUT and
NegatedInstruction(0) and
TimingSignals(4);
-- Select the output value from the data bus into the Output Port D
Load_PortD_From_DataBus <= instruction_OUT and
Instruction(0) and
TimingSignals(4);
-- ================================================================
-- The following section enables the final CPU control lines
-- ================================================================
-- Enable/Disable Load Line of register A
Load_A_From_DataBus <= Load_A_From_DataBus_SETAB or
Load_A_From_DataBus_MOV_ALU_IN or
Load_A_From_DataBus_MOV_ALU_C_TO_AB;
-- Enable/Disable Load Line of register B
Load_B_From_DataBus <= Load_B_From_DataBus_SETAB or
Load_B_From_DataBus_MOV_ALU_IN or
Load_B_From_DataBus_MOV_ALU_C_TO_AB;
-- Enable/Disable Load Line of register C
Load_C_From_DataBus <= Load_C_From_DataBus_ALU;
-- Enable/Disable Load Line of register D
Load_D_From_DataBus <= Load_D_From_DataBus_MOV_ALU_OUT or
Load_D_From_DataBus_MOV or
Load_D_From_DataBus_LOAD;
-- Enable/Disable Load Line of register E
Load_E_From_DataBus <= Load_E_From_DataBus_MOV_ALU_OUT or
Load_E_From_DataBus_MOV or
Load_E_From_DataBus_LOAD;
-- Enable/Disable Load Line of register F
Load_F_From_DataBus <= Load_F_From_DataBus_MOV_ALU_OUT or
Load_F_From_DataBus_MOV or
Load_F_From_DataBus_LOAD;
-- Enable/Disable Load Line of register G
Load_G_From_DataBus <= Load_G_From_DataBus_MOV_ALU_OUT or
Load_G_From_DataBus_MOV or
Load_G_From_DataBus_LOAD;
-- Enable/Disable Load Line of register H
Load_H_From_DataBus <= Load_H_From_DataBus_MOV_ALU_OUT or
Load_H_From_DataBus_MOV or
Load_H_From_DataBus_LOAD;
-- Enable/Disable Load Line of register XL
Load_XL_From_DataBus <= Load_XL_From_DataBus_MOV_ALU_OUT or
Load_XL_From_DataBus_MOV or
Load_XL_From_DataBus_LOAD or
Load_XL_From_DataBus_IN;
-- Enable/Disable Load Line of register XH
Load_XH_From_DataBus <= Load_XH_From_DataBus_MOV_ALU_OUT or
Load_XH_From_DataBus_MOV or
Load_XH_From_DataBus_LOAD;
-- Enable/Disable the Load Line of register M
Load_M_From_AddressBus <= Load_M_From_AddressBus_MOV16;
-- Enable/Disable the Load Line of register X
Load_X_From_AddressBus <= Load_X_From_AddressBus_MOV16 or
Load_X_From_AddressBus_ADDER_16BIT;
-- Enable/Disable Load Line of register J
Load_J_From_AddressBus <= Load_J_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register SP
Load_SP_From_AddressBus <= Load_SP_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register BP
Load_BP_From_AddressBus <= Load_BP_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register Y
Load_Y_From_AddressBus <= Load_Y_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register Z
Load_Z_From_AddressBus <= Load_Z_From_AddressBus_MOV16;
-- Enable/Disable Select Line of register C
Select_C_To_DataBus <= Select_C_To_DataBus_MOV_ALU_OUT or
Select_C_To_DataBus_MOV_ALU_C_TO_AB;
-- Enable/Disable Select Line of register D
Select_D_To_DataBus <= Select_D_To_DataBus_MOV_ALU_IN or
Select_D_To_DataBus_MOV or
Select_D_To_DataBus_STORE or
Select_D_To_DataBus_ADDER_16BIT;
-- Enable/Disable Select Line of register E
Select_E_To_DataBus <= Select_E_To_DataBus_MOV_ALU_IN or
Select_E_To_DataBus_MOV or
Select_E_To_DataBus_STORE;
-- Enable/Disable Select Line of register F
Select_F_To_DataBus <= Select_F_To_DataBus_MOV_ALU_IN or
Select_F_To_DataBus_MOV or
Select_F_To_DataBus_STORE;
-- Enable/Disable Select Line of register G
Select_G_To_DataBus <= Select_G_To_DataBus_MOV_ALU_IN or
Select_G_To_DataBus_MOV or
Select_G_To_DataBus_STORE;
-- Enable/Disable Select Line of register H
Select_H_To_DataBus <= Select_H_To_DataBus_MOV_ALU_IN or
Select_H_To_DataBus_MOV or
Select_H_To_DataBus_STORE;
-- Enable/Disable Select Line of register XL
Select_XL_To_DataBus <= Select_XL_To_DataBus_MOV_ALU_IN or
Select_XL_To_DataBus_MOV or
Select_XL_To_DataBus_STORE or
Select_XL_To_DataBus_OUT;
-- Enable/Disable Select Line of register XH
Select_XH_To_DataBus <= Select_XH_To_DataBus_MOV_ALU_IN or
Select_XH_To_DataBus_MOV or
Select_XH_To_DataBus_STORE;
-- Enable/Disable the Select Line of register M
Select_M_To_AddressBus <= Select_M_To_AddressBus_MOV16 or
Select_M_To_AddressBus_LOAD or
Select_M_To_AddressBus_LOAD_FLAGS or
Select_M_To_AddressBus_STORE or
Select_M_To_AddressBus_STORE_FLAGS;
-- Enable/Disable the Select Line of register X
Select_X_To_AddressBus <= Select_X_To_AddressBus_MOV16 or
Select_X_To_AddressBus_ADDER_16BIT or
Select_X_To_AddressBus_ADDER_16BIT;
-- Enable/Disable Select Line of register SP
Select_SP_To_AddressBus <= Select_SP_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register BP
Select_BP_To_AddressBus <= Select_BP_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register Y
Select_Y_To_AddressBus <= Select_Y_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register Z
Select_Z_To_AddressBus <= Select_Z_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register J
Select_J_To_AddressBus <= Select_J_To_AddressBus_MOV16 or
Select_J_To_AddressBus_JMP or
Select_J_To_AddressBus_JZ or
Select_J_To_AddressBus_JNS or
Select_J_To_AddressBus_JNZ or
Select_J_To_AddressBus_JNC or
Select_J_To_AddressBus_ADDER_16BIT;
-- Enables the Select Line of the flags register
Select_Flags <= Select_Flags_JZ or
Select_Flags_SAVE_FLAGS or
Select_Flags_JNZ or
Select_Flags_JNS or
Select_Flags_JNC or
Select_Flags_FLAGS_TO_OUTBUFFER;
-- Enables the Load Line of the flags register
Load_Flags <= Load_Flags_From_ALU or
Load_Flags_SAVE_FLAGS or
Load_Flags_INBUFFER_TO_FLAGS;
-- Requests the data from the RAM to the data bus
Select_SRAM <= Select_SRAM_FETCH or
Select_SRAM_LOAD or
Select_SRAM_LOAD_FLAGS;
-- Loads the data from the data bus into the RAM
Load_SRAM <= Load_SRAM_STORE or
Load_SRAM_STORE_FLAGS;
-- Returns the requested data from the RAM onto the data bus
Return_SRAM <= Return_SRAM_FETCH or
Return_SRAM_LOAD or
Return_SRAM_LOAD_FLAGS;
-- Enable/Disable the Load Line of the Program Counter
Load_PC <= Load_PC_FETCH or
Load_PC_JMP or
Load_PC_JZ or
Load_PC_JNS or
Load_PC_JNZ or
Load_PC_JNC or
Load_PC_From_AddressBus_MOV16;
-- Enable/Disable the Load Line of the Program Counter
Select_PC <= Select_PC_FETCH or
Select_PC_To_AddressBus_MOV16;
end Behavioral;
| mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG_for lab/alu_shift_unit.vhd | 3 | 1193 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Shift Unit
-- Operations - Shift Left, Shift Right
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Shift_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
COUNT : in STD_LOGIC_VECTOR (2 downto 0);
OP : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU_Shift_Unit;
architecture Combinational of ALU_Shift_Unit is
signal shift_left, shift_right : std_logic_vector (7 downto 0) := (OTHERS => '0');
begin
shift_left <= to_stdlogicvector(to_bitvector(A) sll conv_integer(COUNT));
shift_right <= to_stdlogicvector(to_bitvector(A) srl conv_integer(COUNT));
RESULT <= shift_left when OP='0' else shift_right;
end Combinational;
| mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG_for lab/keyboard_controller.vhd | 8 | 2793 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keyboard Controller
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity KEYBOARD_CONTROLLER is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
ASCII_OUT: out STD_LOGIC_VECTOR (7 downto 0); -- Include Basic Ascii (no extension codes)
ASCII_RD : out STD_LOGIC; -- Indicate Ascii value is available to read
ASCII_WE : out STD_LOGIC); -- Can the Character write(none special character)
end KEYBOARD_CONTROLLER;
architecture Structural of KEYBOARD_CONTROLLER is
signal TX_DATA : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal RX_DATA : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal WR : STD_LOGIC := '0';
signal RD : STD_LOGIC := '0';
signal BS : STD_LOGIC := '0';
signal ER : STD_LOGIC := '0';
signal ASCII : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
-- signal A_RD : STD_LOGIC := '0';
-- signal A_SP : STD_LOGIC := '0';
begin
ASCII_OUT <= ASCII;
U1: entity work.PS2_DRIVER
port map( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
TX_DATA => TX_DATA,
WR => WR,
RX_DATA => RX_DATA,
RD => RD,
BS => BS,
ER => ER);
U2: entity work.KEYCODE_TO_ASCII
port map( CLK => CLK,
RST => RST,
KEYCODE => RX_DATA,
VALID_SIGNAL => RD,
COMPLETE => ASCII_RD,
ASCII => ASCII);
U3: entity work.WE_ASCII
port map( ASCII_IN => ASCII,
ASCII_WE => ASCII_WE);
-- ASCII Generator: Buggy, use at ones risk
-- PS2_ASCII_GEN: entity work.PS2_ASCII_GEN
-- port map( CLK => CLK,
-- RST => RST,
-- PS2_RX => RX_DATA,
-- PS2_RD => RD,
-- PS2_BS => BS,
-- PS2_ER => ER,
-- PS2_TX => TX_DATA,
-- PS2_WR => WR,
-- ASCII => ASCII,
-- ASCII_RD => ASCII_RD,
-- ASCII_SP => ASCII_SP);
end Structural;
| mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/keyboard_controller.vhd | 8 | 2793 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keyboard Controller
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity KEYBOARD_CONTROLLER is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
ASCII_OUT: out STD_LOGIC_VECTOR (7 downto 0); -- Include Basic Ascii (no extension codes)
ASCII_RD : out STD_LOGIC; -- Indicate Ascii value is available to read
ASCII_WE : out STD_LOGIC); -- Can the Character write(none special character)
end KEYBOARD_CONTROLLER;
architecture Structural of KEYBOARD_CONTROLLER is
signal TX_DATA : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal RX_DATA : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal WR : STD_LOGIC := '0';
signal RD : STD_LOGIC := '0';
signal BS : STD_LOGIC := '0';
signal ER : STD_LOGIC := '0';
signal ASCII : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
-- signal A_RD : STD_LOGIC := '0';
-- signal A_SP : STD_LOGIC := '0';
begin
ASCII_OUT <= ASCII;
U1: entity work.PS2_DRIVER
port map( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
TX_DATA => TX_DATA,
WR => WR,
RX_DATA => RX_DATA,
RD => RD,
BS => BS,
ER => ER);
U2: entity work.KEYCODE_TO_ASCII
port map( CLK => CLK,
RST => RST,
KEYCODE => RX_DATA,
VALID_SIGNAL => RD,
COMPLETE => ASCII_RD,
ASCII => ASCII);
U3: entity work.WE_ASCII
port map( ASCII_IN => ASCII,
ASCII_WE => ASCII_WE);
-- ASCII Generator: Buggy, use at ones risk
-- PS2_ASCII_GEN: entity work.PS2_ASCII_GEN
-- port map( CLK => CLK,
-- RST => RST,
-- PS2_RX => RX_DATA,
-- PS2_RD => RD,
-- PS2_BS => BS,
-- PS2_ER => ER,
-- PS2_TX => TX_DATA,
-- PS2_WR => WR,
-- ASCII => ASCII,
-- ASCII_RD => ASCII_RD,
-- ASCII_SP => ASCII_SP);
end Structural;
| mit |
gustavogarciautp/Procesador | Entrega 2/OMUXT_tb.vhd | 2 | 1427 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OMUXT_tb IS
END OMUXT_tb;
ARCHITECTURE behavior OF OMUXT_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal oper2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OMUXT PORT MAP (
Crs2 => Crs2,
SEUimm => SEUimm,
i => i,
oper2 => oper2
);
-- Stimulus process
stim_proc: process
begin
i<='0';
Crs2<="01000010111001000110011101010111";
SEUimm<="00000000000000000000000100110101";
wait for 20 ns;
Crs2<="00000000000010000000001000000000";
SEUimm<="11111111111111111111001000000000";
wait for 20 ns;
i<='1';
Crs2<="00001111111000000011111111100000";
SEUimm<="00000000000000000000001111111111";
wait for 20 ns;
Crs2<="00000000000000000011101001010100";
SEUimm<="00000000000000000000001111000011";
wait;
end process;
END;
| mit |
KPU-RISC/KPU | VHDL/EnableCircuit.vhd | 1 | 1457 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 06:01:15 PM
-- Design Name:
-- Module Name: EnableCircuit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EnableCircuit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Enable : in BIT; -- Should be input value returned?
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end EnableCircuit;
architecture Behavioral of EnableCircuit is
begin
Output(0) <= Input(0) and Enable;
Output(1) <= Input(1) and Enable;
Output(2) <= Input(2) and Enable;
Output(3) <= Input(3) and Enable;
Output(4) <= Input(4) and Enable;
Output(5) <= Input(5) and Enable;
Output(6) <= Input(6) and Enable;
Output(7) <= Input(7) and Enable;
end Behavioral;
| mit |
jeffmagina/ECE368 | Project1/EXECUTE/ALU/alu_toplevel.vhd | 1 | 2586 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (15 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(3 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
| mit |
gustavogarciautp/Procesador | Entrega 2/SEU.vhd | 3 | 389 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEU is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
SEUimm : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture Behavioral of SEU is
begin
process(imm13)
begin
if imm13(12)='1' then
SEUimm<="1111111111111111111"&imm13;
else
SEUimm<="0000000000000000000"&imm13;
end if;
end process;
end Behavioral; | mit |
gustavogarciautp/Procesador | Entrega 3/SEU_tb.vhd | 2 | 914 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SEU_tb IS
END SEU_tb;
ARCHITECTURE behavior OF SEU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal imm13 : std_logic_vector(12 downto 0) := (others => '0');
--Outputs
signal SEUimm : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SEU PORT MAP (
imm13 => imm13,
SEUimm => SEUimm
);
-- Stimulus process
stim_proc: process
begin
imm13<="0100101001110";
wait for 20 ns;
imm13<="1011000101011";
wait for 20 ns;
imm13<="0000000000001";
wait for 20 ns;
imm13<="1000000000000";
wait;
end process;
END;
| mit |
jeffmagina/ECE368 | Lab2/VGA Part 1/clk_tb.vhd | 1 | 2570 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: VGA_COLOR Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY VGA_COLOR_tb_vhd IS
END VGA_COLOR_tb_vhd;
ARCHITECTURE behavior OF VGA_COLOR_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT VGA_COLOR
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
SW : in STD_LOGIC_VECTOR (7 downto 0);
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL HSYNC : STD_LOGIC := '0';
SIGNAL VSYNC : STD_LOGIC := '0';
SIGNAL VGARED : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGAGRN : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGABLU : STD_LOGIC_VECTOR(1 downto 0) := (others=>'0');
SIGNAL SW : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: VGA_COLOR PORT MAP( CLK => CLK,
RST => RST,
SW => SW,
HSYNC => HSYNC,
VSYNC => VSYNC,
VGARED => VGARED,
VGAGRN => VGAGRN,
VGABLU => VGABLU);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start VGA_COLOR Test Bench" severity NOTE;
wait; -- will wait forever
END PROCESS;
END;
| mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/alu_toplevel.vhd | 3 | 2604 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
| mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG_for lab/alu_toplevel.vhd | 3 | 2604 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
| mit |
jeffmagina/ECE368 | Lab1/CounterTest/clk4Hz.vhd | 1 | 1421 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock Divider
-- Lower the Clock frequency from
-- 50 Mhz to 4 hz
-- 50Mhz = 50,000,000/12,500,000 = 2 Hz
-- 4Hz ~= 1/2 second
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port ( CLK_IN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal clkdv: STD_LOGIC:='0';
signal counter : integer range 0 to 12500000 := 0;
begin
frequency_divider: process (RST, CLK_IN) begin
if (RST = '1') then
clkdv <= '0';
counter <= 0;
elsif rising_edge(CLK_IN) then
if (counter = 12500000) then
if(clkdv='0') then
clkdv <= '1';
else
clkdv <= '0';
end if;
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_OUT <= clkdv;
end Behavioral;
| mit |
gustavogarciautp/Procesador | Entrega 2/ALU_tb.vhd | 1 | 7455 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C: IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal C : std_logic:='0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
ALUOP => ALUOP,
C => C,
ALURESULT => ALURESULT
);
-- Stimulus process
stim_proc: process
begin
C<='1';
------------------SUB-------------------------------
ALUOP<="000111";
-- 5 - 28
Oper1<="00000000000000000000000000000101"; -- +5
Oper2<="00000000000000000000000000011100"; -- +28
wait for 20 ns;
-- 32 - 20
Oper1<="00000000000000000000000000100000";-- +32
Oper2<="00000000000000000000000000010100";-- +20
wait for 20 ns;
-- -45 - (+33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000100001";-- +33
wait for 20 ns;
-- -45 - (+63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000111111";-- +63
wait for 20 ns;
-- -45 - (-33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
-- -45 - (-63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-63)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-33)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
----------------SUMA----------------
ALUOP<="000110";-- 75 + 25
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- 75 + (-25)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- 75 + (-100)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-- -75 + 25
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- -75 + 100
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000001100100";-- +100
wait for 20 ns;
-- -75 + (-25)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- -75 + (-100)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-------------------OR--------------------
ALUOP<="000010";
Oper1<="11111111111111111100011110110101";
Oper2<="00000011101010001001010000001100";
wait for 20 ns;
-----------------orn---------------------
ALUOP<="000011";
wait for 20 ns;
-----------------xor-------------------
ALUOP<="000100";
wait for 20 ns;
-----------------xnor-------------------
ALUOP<="000101";
wait for 20 ns;
-----------------and-------------------
ALUOP<="000000";
wait for 20 ns;
-----------------andn-------------------
ALUOP<="000001";
wait for 20 ns;
-----------------SLL------------------
ALUOP<="001000";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRL-------------------
ALUOP<="001001";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRA----------------------
ALUOP<="001010";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------ANDcc---------------------
ALUOP<="001011";
Oper1<="00000111111000000010010000000111";
Oper2<="00000111111111000000000000000011";
wait for 20 ns;
-----------------ANDNcc--------------------
ALUOP<="001100";
Oper1<="00000000111111111000000010100000";
Oper2<="00001111111100000000000000000011";
wait for 20 ns;
-----------------ORcc----------------------
ALUOP<="001101";
Oper1<="00000001111111111100000000000000";
Oper2<="11111000000000111111110000000000";
wait for 20 ns;
-----------------ORNcc---------------------
ALUOP<="001110";
Oper1<="00000011111111100000011111000000";
Oper2<="00000000001111111111111100000000";
wait for 20 ns;
-----------------XORcc---------------------
ALUOP<="001111";
Oper1<="00001000100000000111111111100000";
Oper2<="00000001111110000110000011000000";
wait for 20 ns;
-----------------XNORcc--------------------
ALUOP<="010000";
Oper1<="00000001111111111100000000000111";
Oper2<="11110000001111100000110001000000";
wait for 20 ns;
-----------------ADDcc---------------------
ALUOP<="010001";
Oper1<="00000000000000000000000001101000";
Oper2<="00000000000000000000000000000101";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------ADDX----------------------
ALUOP<="010010";
Oper1<="00000000000000100101010000000000";
Oper2<="00000000000000000000000100000011";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------ADDXcc--------------------
ALUOP<="010011";
Oper1<="00000000000000000000000000101010";
Oper2<="00000000000000000000000000001101";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------SUBcc---------------------
ALUOP<="010100";
Oper1<="00000000000000000000000100000000";
Oper2<="00000000000000000000000000010000";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------SUBX----------------------
ALUOP<="010101";
Oper1<="00000000000000000000000000001111";
Oper2<="00000000000000000000000000001011";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------SUBXcc--------------------
ALUOP<="010110";
Oper1<="00000000000000000000000100011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------SAVE----------------------
ALUOP<="010111";
Oper1<="00000000000000000000000000011011";
Oper2<="00000000000000000000000000001100";
wait for 20 ns;
-----------------RESTORE-------------------
ALUOP<="011000";
Oper1<="00000000000000000000000000010000";
Oper2<="00000000000000000000000000000111";
wait for 20 ns;
---------------Instrucciones no definidas--------------------------
ALUOP<="111111";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000011111111";
wait;
end process;
END;
| mit |
gustavogarciautp/Procesador | Entrega 1/OMUXT_tb.vhd | 1 | 1440 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OMUXT_tb IS
END OMUXT_tb;
ARCHITECTURE behavior OF OMUXT_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal oper2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OMUXT PORT MAP (
Crs2 => Crs2,
SEUimm => SEUimm,
i => i,
oper2 => oper2
);
-- Stimulus process
stim_proc: process
begin
i<='0';
Crs2<="01000010111001000110011101010111";
SEUimm<="00000000000000000000000100110101";
wait for 20 ns;
Crs2<="00000000000010000000001000000000";
SEUimm<="11111111111111111111001000000000";
wait for 20 ns;
i<='1';
Crs2<="00001111111000000011111111100000";
SEUimm<="00000000000000000000001111111111";
wait for 20 ns;
Crs2<="00000000000000000011101001010100";
SEUimm<="00000000000000000000001111000011";
wait;
end process;
END;
| mit |
jeffmagina/ECE368 | Project1/RISC_MACHINE/RISC_MACHINE_tbd.vhd | 1 | 2471 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:46:18 04/07/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/RISC_MACHINE/RISC_MACHINE_tbd.vhd
-- Project Name: RISC_MACHINE
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RISC_MACHINE
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY RISC_MACHINE_tbd IS
END RISC_MACHINE_tbd;
ARCHITECTURE behavior OF RISC_MACHINE_tbd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RISC_MACHINE
PORT(
CLK : IN std_logic;
PC_RESET : IN std_logic;
RISC_INST_ENB : IN STD_LOGIC;
CCR_OUT : OUT std_logic_vector(3 downto 0);
DATA_OUT : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal PC_RESET : std_logic := '0';
signal RISC_INST_ENB : std_logic := '0';
--Outputs
signal CCR_OUT : std_logic_vector(3 downto 0);
signal DATA_OUT : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RISC_MACHINE PORT MAP (
CLK => CLK,
PC_RESET => PC_RESET,
RISC_INST_ENB => RISC_INST_ENB,
CCR_OUT => CCR_OUT,
DATA_OUT => DATA_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
tb: process
begin
-- hold reset state for 100 ns.
RISC_INST_ENB <= '1';
wait for 100 ns;
wait;
end process;
END;
| mit |
gustavogarciautp/Procesador | Entrega 2/PSRModifier.vhd | 1 | 1710 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSRModifier is
Port ( ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
NZVC : out STD_LOGIC_VECTOR (3 downto 0));
end PSRModifier;
architecture Behavioral of PSRModifier is
begin
process(ALUOP,Oper2,Oper1,ALURESULT)
begin
if(ALUOP="001011" or ALUOP="001100" or ALUOP="001101" or ALUOP="001110" or ALUOP="001111" or ALUOP="010000" or ALUOP="010001" or ALUOP="010011" or ALUOP="010100" or ALUOP="010110") then
--ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc,ADDcc,ADDXcc,SUBcc,SUBXcc
if(ALURESULT="00000000000000000000000000000000") then
NZVC(2)<='1';
else
NZVC(2)<='0';
end if;
NZVC(3)<=ALURESULT(31);
if(ALUOP="001011" or ALUOP="001100" or ALUOP="001101" or ALUOP="001110" or ALUOP="001111" or ALUOP="010000") then
--ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
NZVC(1 downto 0)<="00";
elsif(ALUOP="010001" or ALUOP="010011") then --ADDcc, ADDXcc
NZVC(1)<=((Oper1(31) and Oper2(31) and (not ALURESULT(31))) or ((not Oper1(31)) and (not Oper2(31)) and ALURESULT(31)));
NZVC(0)<=(Oper1(31) and Oper2(31)) or ((not ALURESULT(31)) and (Oper1(31) or Oper2(31)));
else--(ALUOP="010100" or ALUOP="010110") SUBcc, SUBXcc
NZVC(1)<=(Oper1(31) and (not Oper2(31)) and (not ALURESULT(31))) or ((not Oper1(31)) and Oper2(31) and ALURESULT(31));
NZVC(0)<=((not Oper1(31)) and Oper2(31)) or (ALURESULT(31) and ((not Oper1(31)) or Oper2(31)));
end if;
else
NZVC<="1111";
end if;
end process;
end Behavioral;
| mit |
gustavogarciautp/Procesador | Entrega 1/InstructionMemory.vhd | 1 | 3187 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity InstructionMemory is
Port ( Address : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionMemory;
architecture syn of InstructionMemory is
type rom_type is array (63 downto 0) of std_logic_vector (31 downto 0);
signal ROM : rom_type:= ("00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","10011000001000000100000000000010",
"10010110001110000100000000000010","10010100001010000100000000000010",
"10010010000110000100000000000010","10010000000000000100000000000010",
"10000100000100000011111111111001","10000010000100000010000000001000");
begin
process(rst,Address,ROM)
begin
if rst='1' then
Instruction<=(others=>'0');
else
Instruction<=ROM(conv_integer(Address));
end if;
end process;
end syn;
| mit |
jeffmagina/ECE368 | Project1/RISC_MACHINE/RISC_MACHINE.vhd | 1 | 3308 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:23:34 03/25/2015
-- Design Name:
-- Module Name: RISC_MACHINE - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RISC_MACHINE is
Port( CLK : IN STD_LOGIC;
PC_RESET: IN STD_LOGIC;
RISC_INST_ENB : IN STD_LOGIC;
CCR_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT: OUT STD_LOGIC_VECTOR (15 downto 0)
);
end RISC_MACHINE;
architecture Structural of RISC_MACHINE is
signal instruction_in, FETCH_out, fpu_out, OP1_out, OP2_out, s_Bank_Data, s_OPA_REG_A, EX_Forward_out: STD_LOGIC_VECTOR(15 downto 0);
signal pc : STD_LOGIC_VECTOR (9 downto 0);
signal DEC_immediate : STD_LOGIC_VECTOR (7 downto 0);
signal write_address, OPA_OPCODE, DEC_opcode, DEC_reg_a, s_Dec_REG_A,s_DEC_OPCODE_OUT : STD_LOGIC_VECTOR(3 downto 0);
signal OP1_SEL, OP2_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal bank_RW, WB_MEM_WE, WB_MUX_SEL : STD_LOGIC;
begin
U1: entity work.FETCH
Port Map ( CLK => CLK,
DATAIN => instruction_in,
INST_ENB => RISC_INST_ENB,
INST_OUT => FETCH_out,
PC_OUT => pc,
WE => '0'
);
U2: entity work.decode
Port Map ( CLK => CLK,
INST_IN => FETCH_out,
OPCODE => DEC_opcode,
REG_A => DEC_reg_a,
IMMEDIATE => DEC_immediate
);
U3: entity work.op_access
Port Map ( CLK => CLK,
OPCODE_IN => DEC_opcode,
REG_A => DEC_reg_a,
IMMEDIATE => DEC_immediate,
W_ADDR => Write_Address,
OP1_MUX_SEL => OP1_SEL,
OP2_MUX_SEL => OP2_SEL,
BANK_R_W => bank_RW,
BANK_ENB => '1',
BANK_DATA => s_Bank_Data,
DEC_REG_ADDR => s_Dec_REG_A,
OPCODE_OUT => OPA_OPCODE,
EX_FWD_IN => EX_Forward_out,
EX_FWD_ADDR => s_Dec_REG_A,
WB_FWD_IN => s_Bank_Data,
WB_FWD_ADDR => Write_Address,
OP1_OUT => OP1_out,
OP2_OUT => OP2_out
);
U4: entity work.execute
Port Map ( CLK => CLK,
OPCODE => OPA_OPCODE,
OP1 => OP1_out,
OP2 => OP2_out,
Dec_Reg_A_IN => s_Dec_REG_A,
OPA_REG_A => s_OPA_REG_A,
Dec_Reg_A_OUT => Write_Address,
DEC_OPCODE_OUT=> s_DEC_OPCODE_OUT,
EX_FWD_OUT => EX_Forward_out,
FPU_OUT => fpu_out,
CCR => CCR_OUT
);
U5: entity work.write_back
Port Map ( CLK => CLK,
DATA_WE => WB_MEM_WE,
FPU_IN => fpu_out,
REG_A => s_OPA_REG_A,
D_OUT_SEL => WB_MUX_SEL,
WB_OUT => s_Bank_Data
);
Cntrl_unit: entity work.control_unit
Port Map( CLK => CLK,
OPA_OPCODE => DEC_opcode,
OP1_MUX_SEL => OP1_SEL,
OP2_MUX_SEL => OP2_SEL,
REG_BANK_WE => bank_RW,
DATA_MEM_WE => WB_MEM_WE,
WB_OPCODE => s_DEC_OPCODE_OUT,
OPA_D_OUT_SEL => WB_MUX_SEL
);
end Structural;
| mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/load_store_unit.vhd | 3 | 1320 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Load/Store Unit
-- Operations - Load/Store to a register
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Load_Store_Unit is
Port ( CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0);
IMMED : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Load_Store_Unit;
architecture Behavioral of Load_Store_Unit is
signal reg : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal w_en : std_logic := '0';-- '1' = write, '0' = read
begin
w_en <= '1' when OP="1010" else '0';
process(CLK)
begin
if (CLK'event and CLK='1') then
if (w_en = '1') then
reg <= A;
end if;
end if;
end process;
RESULT <= reg;
end Behavioral;
| mit |
laurivosandi/hdl | primitives/src/sr_latch_testbench.vhd | 1 | 717 | library ieee;
use ieee.std_logic_1164.all;
entity sr_latch_testbench is end sr_latch_testbench;
architecture behavioral of sr_latch_testbench IS
component sr_latch
port (
s : in std_logic;
r : in std_logic;
q_n : inout std_logic;
q : inout std_logic);
end component;
signal q, q_n : std_logic := '0';
signal input : std_logic_vector(1 downto 0);
begin
input <=
-- a,b
"10",
"11" AFTER 5 ns,
"01" AFTER 10 ns,
"11" AFTER 15 ns,
"10" AFTER 20 ns,
"11" AFTER 25 ns,
"00" AFTER 30 ns;
uut: sr_latch port map (input(1), input(0), q_n, q);
end behavioral;
| mit |
rodrigoazs/-7-5-Reed-Solomon | code/full_adder.vhd | 1 | 1029 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity fa is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum1 : out std_logic;
sum0 : out std_logic);
end fa;
architecture Behavioral of fa is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
signal s4 : std_logic;
signal s5 : std_logic;
signal s6 : std_logic;
signal s7 : std_logic;
signal s8 : std_logic;
begin
s1 <= (not a) and b and c;
s2 <= a and (not b) and c;
s3 <= a and b and (not c);
s4 <= a and b and c;
sum1 <= s1 or s2 or s3 or s4;
s5 <= (not a) and b and (not c);
s6 <= a and (not b) and (not c);
s7 <= (not a) and (not b) and c;
s8 <= a and b and c;
sum0 <= s5 or s6 or s7 or s8;
end Behavioral;
| mit |
rodrigoazs/-7-5-Reed-Solomon | code/symbol_multiplier.vhd | 1 | 2678 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolMultiplier is
port( uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0)
);
end SymbolMultiplier;
architecture Behavioral of SymbolMultiplier is
component BinaryAdderSubtractor is
port( a,b: in std_logic_vector(3 downto 0);
fnc: in std_logic;
s_or_d: out std_logic_vector(3 downto 0)
);
end component;
component Mux6x3 is
Port ( a : in std_logic_vector(2 downto 0) ;
b : in std_logic_vector(2 downto 0) ;
s : in std_logic ;
f : out std_logic_vector(2 downto 0));
end component ;
component SymbolPowerDecoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end component;
component SymbolPowerEncoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end component;
signal iszero: std_logic;
signal zerov: std_logic_vector(2 downto 0);
signal s_or_d: std_logic_vector(3 downto 0);
signal a: std_logic_vector(2 downto 0);
signal b: std_logic_vector(2 downto 0);
signal uncoded_multab_poly: std_logic_vector(2 downto 0);
signal multab: std_logic_vector(2 downto 0);
signal sa: std_logic_vector(3 downto 0);
signal sb: std_logic_vector(3 downto 0);
signal tt: std_logic;
signal t7: std_logic_vector(3 downto 0);
signal tres: std_logic_vector(3 downto 0);
signal sa2: std_logic_vector(2 downto 0);
signal sb2: std_logic_vector(2 downto 0);
begin
iszero <= (uncoded_a(0) or uncoded_a(1) or uncoded_a(2))
and (uncoded_b(0) or uncoded_b(1) or uncoded_b(2));
encode1: SymbolPowerEncoder port map(uncoded_a, a);
encode2: SymbolPowerEncoder port map(uncoded_b, b);
sa(0) <= a(0);
sa(1) <= a(1);
sa(2) <= a(2);
sa(3) <= '0';
sb(0) <= b(0);
sb(1) <= b(1);
sb(2) <= b(2);
sb(3) <= '0';
fa0: BinaryAdderSubtractor port map(sa, sb, '0', s_or_d);
tt <= s_or_d(3) or (s_or_d(0) and s_or_d(1) and s_or_d(2));
t7(0) <= '1';
t7(1) <= '1';
t7(2) <= '1';
t7(3) <= '0';
fa1: BinaryAdderSubtractor port map(s_or_d, t7,'1',tres);
sa2(0) <= tres(0);
sa2(1) <= tres(1);
sa2(2) <= tres(2);
sb2(0) <= s_or_d(0);
sb2(1) <= s_or_d(1);
sb2(2) <= s_or_d(2);
mux1: Mux6x3 port map(sa2, sb2, tt, multab);
decode1: SymbolPowerDecoder port map(multab, uncoded_multab_poly);
zerov(0) <= '0';
zerov(1) <= '0';
zerov(2) <= '0';
mux2: Mux6x3 port map(uncoded_multab_poly, zerov, iszero, uncoded_multab);
end Behavioral;
| mit |
rodrigoazs/-7-5-Reed-Solomon | code/symbol_power_encoder.vhd | 1 | 819 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolPowerEncoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end SymbolPowerEncoder;
architecture Behavioral of SymbolPowerEncoder is
begin
process ( n1 )
begin
case n1 is
when "100"=> n1c <="000" ;
when "010"=> n1c <="001" ;
when "001"=> n1c <="010" ;
when "110"=> n1c <="011" ;
when "011"=> n1c <="100" ;
when "111"=> n1c <="101" ;
when "101"=> n1c <="110" ;
when others=> n1c <="---" ;
end case ;
end process ;
end Behavioral;
| mit |
laurivosandi/hdl | zynq/src/bcd_segment_driver.vhd | 1 | 754 | library ieee;
use ieee.std_logic_1164.all;
entity bcd_segment_driver is
port (
bcd : in std_logic_vector(3 downto 0);
segments : out std_logic_vector(6 downto 0));
end;
architecture behavioral of bcd_segment_driver is
begin
segments <=
"1111110" when bcd = "0000" else -- 0
"0110000" when bcd = "0001" else -- 1
"1101101" when bcd = "0010" else -- 2
"1111001" when bcd = "0011" else -- 3
"0110011" when bcd = "0100" else -- 4
"1011011" when bcd = "0101" else -- 5
"1011111" when bcd = "0110" else -- 6
"1110000" when bcd = "0111" else -- 7
"1111111" when bcd = "1000" else -- 8
"1111011" when bcd = "1001" else -- 9
"0000000";
end;
| mit |
rajvinjamuri/ECE385_VHDL | reg_11.vhd | 1 | 2105 | ---------------------------------------------------------------------------
-- reg_11.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- Purpose/Description: --
-- an 11-bit register unit with parallel-load and serial-in/out --
-- --
-- based on 4-bit register given by UIUC --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
-- Updates: --
-- --
-- >3.10: added appropriate number of zeros to 'reset' --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_11 is
Port ( Shift_In, Load, Shift_En, Clk, Reset : in std_logic;
D : in std_logic_vector(10 downto 0);
Shift_Out : out std_logic;
Data_Out : out std_logic_vector(10 downto 0)); --added range
end reg_11;
architecture Behavioral of reg_11 is
signal reg_value: std_logic_vector(10 downto 0);
begin
operate_reg: process(Load, Shift_En, Clk, Shift_In, Reset)
begin
if (rising_edge(Clk)) then
if (Shift_En = '1')then
reg_value <= Shift_In & reg_value (10 downto 1);
-- operator "&" concatenates two bit-fields
elsif (Load = '1') then
reg_value <= D;
elsif (Reset = '1') then
reg_value <= "00000000000";
else
reg_value <= reg_value;
end if;
end if;
end process;
Data_Out <= reg_value;
Shift_Out <=reg_value(0);
end Behavioral; | mit |
laurivosandi/hdl | zynq/src/ov7670_axi_stream_capture/ov7670_axi_stream_capture.vhd | 1 | 3774 | ----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Lauir Vosandi <[email protected]>
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ov7670_axi_stream_capture is
port (
pclk : in std_logic;
vsync : in std_logic;
href : in std_logic;
d : in std_logic_vector (7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic;
m_axis_tdata : out std_logic_vector ( 31 downto 0 );
m_axis_tuser : out std_logic;
aclk : out std_logic
);
end ov7670_axi_stream_capture;
architecture behavioral of ov7670_axi_stream_capture is
signal d_latch : std_logic_vector(15 downto 0) := (others => '0');
signal address : std_logic_vector(18 downto 0) := (others => '0');
signal line : std_logic_vector(1 downto 0) := (others => '0');
signal href_last : std_logic_vector(6 downto 0) := (others => '0');
signal we_reg : std_logic := '0';
signal href_hold : std_logic := '0';
signal latched_vsync : std_logic := '0';
signal latched_href : std_logic := '0';
signal latched_d : std_logic_vector (7 downto 0) := (others => '0');
signal sof : std_logic := '0';
signal eol : std_logic := '0';
begin
-- Expand 16-bit RGB (5:6:5) to 32-bit RGBA (8:8:8:8)
m_axis_tdata <= "11111111" & d_latch(4 downto 0) & d_latch(0) & d_latch(0) & d_latch(0) & d_latch(10 downto 5) & d_latch(5) & d_latch(5) & d_latch(15 downto 11) & d_latch(11) & d_latch(11) & d_latch(11);
m_axis_tvalid <= we_reg;
m_axis_tlast <= eol;
m_axis_tuser <= sof;
aclk <= not pclk;
capture_process: process(pclk)
begin
if rising_edge(pclk) then
if we_reg = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
if href_hold = '0' and latched_href = '1' then
case line is
when "00" => line <= "01";
when "01" => line <= "10";
when "10" => line <= "11";
when others => line <= "00";
end case;
end if;
href_hold <= latched_href;
-- Capturing the data from the camera
if latched_href = '1' then
d_latch <= d_latch( 7 downto 0) & latched_d;
end if;
we_reg <= '0';
-- Is a new screen about to start (i.e. we have to restart capturing)
if latched_vsync = '1' then
address <= (others => '0');
href_last <= (others => '0');
line <= (others => '0');
else
-- If not, set the write enable whenever we need to capture a pixel
if href_last(0) = '1' then
we_reg <= '1';
href_last <= (others => '0');
else
href_last <= href_last(href_last'high-1 downto 0) & latched_href;
end if;
end if;
case unsigned(address) mod 640 = 639 is
when true => eol <= '1';
when others => eol <= '0';
end case;
case unsigned(address) = 0 is
when true => sof <= '1';
when others => sof <= '0';
end case;
end if;
if falling_edge(pclk) then
latched_d <= d;
latched_href <= href;
latched_vsync <= vsync;
end if;
end process;
end behavioral;
| mit |
rajvinjamuri/ECE385_VHDL | game_handler.vhd | 1 | 2877 | ---------------------------------------------------------------------------
-- game_handler.vhd --
-- Raj Vinjamuri --
-- 4-13 --
-- --
-- Purpose/Description: --
-- handles game status --
-- --
-- based on 4-bit register given by UIUC --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- see theory.txt for what each bit means --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity game_handler is
Port ( frame_clk : in std_logic;
paddle_loss_statusIn : in std_logic_vector(1 downto 0);
win_statusIn, ResetIn, ResetScore : in std_logic;
brick_hitIn : in std_logic_vector(19 downto 0);
score: out std_logic_vector(7 downto 0);
game_status : out std_logic_vector(3 downto 0));
end game_handler;
architecture Behavioral of game_handler is
signal reg_value: std_logic_vector(3 downto 0);
signal scoreSig: std_logic_vector(7 downto 0);
begin
operate_reg: process(paddle_loss_statusIn, brick_hitIn, win_statusIn, ResetIn)
begin
if (ResetIn = '1') then
reg_value <= "0000";
elsif(rising_edge(frame_clk)) then
reg_value(0) <= paddle_loss_statusIn(0);
reg_value(1) <= paddle_loss_statusIn(1);
reg_value(2) <= (brick_hitIn(0) OR brick_hitIn(1) OR brick_hitIn(2) OR brick_hitIn(3) OR
brick_hitIn(4) OR brick_hitIn(5) OR brick_hitIn(6) OR brick_hitIn(7) OR
brick_hitIn(8) OR brick_hitIn(9) OR brick_hitIn(10) OR brick_hitIn(11) OR
brick_hitIn(12) OR brick_hitIn(13) OR brick_hitIn(14) OR brick_hitIn(15) OR
brick_hitIn(16) OR brick_hitIn(17) OR brick_hitIn(18) OR brick_hitIn(19));
reg_value(3) <= win_statusIn;
end if;
end process;
operate_score: process(reg_value, ResetScore)
begin
if (ResetScore = '1') then
scoreSig <= "00000000";
elsif(rising_edge(frame_clk)) then
if (reg_value(1) = '1') then
scoreSig <= scoreSig + "00000001";
elsif (reg_value(2) = '1') then
scoreSig <= scoreSig + "00001010";
elsif (reg_value(3) = '1') then
scoreSig <= scoreSig + "00110010";
else
scoreSig <= scoreSig;
end if;
end if;
end process;
-- decimel: process(scoreOutSig)
-- begin
-- scoreH <= (scoreOutSig mod "00001010");
-- scoreL <=
score <= scoreSig;
game_status <= reg_value;
end Behavioral; | mit |
rodrigoazs/-7-5-Reed-Solomon | code/reedsolomon.vhd | 1 | 5367 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomon is
end ReedSolomon;
architecture Behavioral of ReedSolomon is
component ReedSolomonEncoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0 : in std_logic_vector(2 downto 0);
Qp : out std_logic_vector(2 downto 0));
end component;
component ReedSolomonDecoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0: in std_logic_vector(2 downto 0);
Dsyn1: out std_logic_vector(2 downto 0);
Dsyn2: out std_logic_vector(2 downto 0));
end component;
component counter is
Port( Clock: in std_logic;
Count5: out std_logic;
Count7: out std_logic);
end component;
component mux6 is
Port (y1: in std_logic_vector(2 downto 0);
y0: in std_logic_vector(2 downto 0);
s: in std_logic;
f: out std_logic_vector(2 downto 0));
end component ;
component flipflop is
Port ( D: in std_logic_vector(2 downto 0);
Clock: in std_logic;
Reset: in std_logic;
Q: out std_logic_vector(2 downto 0));
end component ;
component ErrorGenerator is
Port ( Clock : in std_logic;
Qout: out std_logic_vector(2 downto 0));
end component;
component ErrorGuessing is
Port ( Syndrome: in std_logic_vector(5 downto 0);
Error : out std_logic_vector(20 downto 0));
end component;
component read_file is
Port (Clock: in std_logic;
Qout: out std_logic_vector(2 downto 0));
end component;
component write_file is
Port (Clock: in std_logic;
Message: in std_logic_vector(14 downto 0));
end component;
component write_error is
Port (Clock: in std_logic;
Message: in std_logic_vector(14 downto 0));
end component;
signal Qp: std_logic_vector(2 downto 0);
signal Count5: std_logic;
signal Count7: std_logic;
signal out_mux1: std_logic_vector(2 downto 0);
signal ErrorGenerated: std_logic_vector(2 downto 0);
signal out2: std_logic_vector(2 downto 0);
signal unusual: std_logic;
signal Qs0 : std_logic_vector(2 downto 0);
signal Db0 : std_logic_vector(2 downto 0);
signal Db1 : std_logic_vector(2 downto 0);
signal Db2 : std_logic_vector(2 downto 0);
signal Db3 : std_logic_vector(2 downto 0);
signal Db4 : std_logic_vector(2 downto 0);
signal Db5 : std_logic_vector(2 downto 0);
signal Db6 : std_logic_vector(2 downto 0);
signal Qb0 : std_logic_vector(2 downto 0);
signal Qb1 : std_logic_vector(2 downto 0);
signal Qb2 : std_logic_vector(2 downto 0);
signal Qb3 : std_logic_vector(2 downto 0);
signal Qb4 : std_logic_vector(2 downto 0);
signal Qb5 : std_logic_vector(2 downto 0);
signal Qb6 : std_logic_vector(2 downto 0);
signal Din : std_logic_vector(2 downto 0);
signal Syn1 : std_logic_vector(2 downto 0);
signal Syn2 : std_logic_vector(2 downto 0);
signal Syndrome : std_logic_vector(5 downto 0);
signal Error : std_logic_vector(20 downto 0);
signal Message: std_logic_vector(14 downto 0);
signal MessageError: std_logic_vector(14 downto 0);
signal Clock: std_logic;
begin
readdata: read_file Port map (Clock, Qs0);
muxCount: mux6 Port map (Qp, Qs0, Count5, Din);
RDE: ReedSolomonEncoder Port map (Clock, Count7, Din, Qp);
muxa: mux6 Port map (Qp, Din, Count5, out_mux1);
RndGen: ErrorGenerator Port map (Clock, ErrorGenerated);
out2(0) <= out_mux1(0) xor ErrorGenerated(0);
out2(1) <= out_mux1(1) xor ErrorGenerated(1);
out2(2) <= out_mux1(2) xor ErrorGenerated(2);
Db6 <= out2;
ffbuffer0 : flipflop Port map (Db0,Clock,'0',Qb0);
ffbuffer1 : flipflop Port map (Db1,Clock,'0',Qb1);
ffbuffer2 : flipflop Port map (Db2,Clock,'0',Qb2);
ffbuffer3 : flipflop Port map (Db3,Clock,'0',Qb3);
ffbuffer4 : flipflop Port map (Db4,Clock,'0',Qb4);
ffbuffer5 : flipflop Port map (Db5,Clock,'0',Qb5);
ffbuffer6 : flipflop Port map (Db6,Clock,'0',Qb6);
RDD: ReedSolomonDecoder Port map (Clock, Count7, out2,
Syn1, Syn2);
Syndrome(0) <= Syn2(0);
Syndrome(1) <= Syn2(1);
Syndrome(2) <= Syn2(2);
Syndrome(3) <= Syn1(0);
Syndrome(4) <= Syn1(1);
Syndrome(5) <= Syn1(2);
ErrorGuess: ErrorGuessing Port map (Syndrome, Error);
MessageError(0) <= Db0(0);
MessageError(1) <= Db0(1);
MessageError(2) <= Db0(2);
MessageError(3) <= Db1(0);
MessageError(4) <= Db1(1);
MessageError(5) <= Db1(2);
MessageError(6) <= Db2(0);
MessageError(7) <= Db2(1);
MessageError(8) <= Db2(2);
MessageError(9) <= Db3(0);
MessageError(10) <= Db3(1);
MessageError(11) <= Db3(2);
MessageError(12) <= Db4(0);
MessageError(13) <= Db4(1);
MessageError(14) <= Db4(2);
Message(0) <= Db0(0) xor Error(0);
Message(1) <= Db0(1) xor Error(1);
Message(2) <= Db0(2) xor Error(2);
Message(3) <= Db1(0) xor Error(3);
Message(4) <= Db1(1) xor Error(4);
Message(5) <= Db1(2) xor Error(5);
Message(6) <= Db2(0) xor Error(6);
Message(7) <= Db2(1) xor Error(7);
Message(8) <= Db2(2) xor Error(8);
Message(9) <= Db3(0) xor Error(9);
Message(10) <= Db3(1) xor Error(10);
Message(11) <= Db3(2) xor Error(11);
Message(12) <= Db4(0) xor Error(12);
Message(13) <= Db4(1) xor Error(13);
Message(14) <= Db4(2) xor Error(14);
Db0 <= Qb1;
Db1 <= Qb2;
Db2 <= Qb3;
Db3 <= Qb4;
Db4 <= Qb5;
Db5 <= Qb6;
count1: counter Port map (Clock, Count5, Count7);
writedata: write_file Port map (Clock, Message);
writeerror: write_error Port map (Clock, MessageError);
end Behavioral;
| mit |
vhdlnerd/classicHp | src/classic.vhd | 1 | 38653 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Engineer: Brian Nemetz
--
-- Create Date: 15:19:05 10/12/2012
-- Design Name:
-- Module Name: classic - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.classic_pack.all;
use work.bcd_alu_lut_pack.all;
use work.rom_pack.all;
--
-- INPUTS:
-- clk_i : Clock
-- rst_i : Async Reset
-- inst_en_i : Instruction Enable: An op-code is only executed when this is
-- a '1'. This input can be used to throttle the exection of
-- op-codes. Setting this a constant '1' will cause op-codes
-- execute at full speed.
-- keycode_i : Key Code: keyvalid_i is used to qualify this input
-- keyvalid_i : Key Valid: Pulses high for each new key press. This need to
-- pulse high for many cycles. The ROM code will miss see this
-- high if its not on long enough. A 10ms pulse seems to be
-- good.
-- flags_i : External flags: Used for a HP-55
--
-- OUTPUTS:
-- error_o : Indicates the core detected an error (all the error conditions
-- the original calculator's detected). Sets on an error and
-- clears on the next valid key input.
-- display_en_o : Display Enable: Used on the original calculators to flash the
-- LEDs on an error. This output is not very useful if the
-- throttling it not used to match the original calculaotr's
-- speed. Its better to use the error_o output.
-- xreg_o : This is a copy of register A. Used to create the formatted display.
-- mask_o : This is a copy of register B. Used to create the formatted display.
-- status_o : The internal status bits. Can be used know when the calculator is
-- in different modes (i.e. shift active, run, prog, timer,...)
--
entity classic is
generic (
ROM : RomType := ROM_45;
CALC_NAME : string := "HP45" -- should be "HP35", "HP45", or "HP55"
);
port ( clk_i : in std_logic;
rst_i : in std_logic;
inst_en_i : in std_logic := '1';
keycode_i : in std_logic_vector (7 downto 0);
keyvalid_i : in std_logic;
flags_i : in std_logic_vector(11 downto 0) := (others => '0'); -- ext flags (for mode switch on HP55)
error_o : out std_logic;
display_en_o: out std_logic;
xreg_o : out std_logic_vector (55 downto 0);
mask_o : out std_logic_vector (55 downto 0);
status_o : out std_logic_vector (11 downto 0)
);
end classic;
architecture rtl of classic is
constant HP35 : boolean := CALC_NAME="HP35";
constant HP45 : boolean := CALC_NAME="HP45";
constant HP55 : boolean := CALC_NAME="HP55";
constant ROM_ADDR_LEN : natural := vecLen(ROM'length-1);
function RamSize return natural is
begin
if HP45 then
return 10;
elsif HP55 then
return 30;
end if;
return 1;
end function RamSize;
constant RAM_SIZE : natural := RamSize;
constant RAM_ADDR_LEN : natural := vecLen(RAM_SIZE-1);
type execFsmType is (RESET, FETCH, DECODE, EXEC_WAIT, EXECUTE, STOP);
subtype subInxType is natural range 0 to 15;
subtype ramInxType is natural range 0 to RAM_SIZE-1;
signal aRegR, bRegR, cRegR : arthRegType;
signal dRegR, eRegR, fRegR : arthRegType;
signal mRegR : arthRegType;
signal t0RegR, t1RegR : arthRegType; -- temp regs
signal sRegR : std_logic_vector(15 downto 0); -- implement 16 bits for status (but only lower 12 are used)
signal pRegR : unsigned(3 downto 0);
signal carryR, carryInR : std_logic;
signal pcR : unsigned(7 downto 0);
signal retR : unsigned(7 downto 0);
signal keyCodeR : unsigned(7 downto 0);
signal romSelR : unsigned(2 downto 0);
signal romDelSelR : unsigned(2 downto 0); -- Delayed ROM Select (for HP55)
signal grpSelR : unsigned(0 downto 0); -- Group select (for HP55)
signal grpDelSelR : unsigned(0 downto 0); -- Delayed Group select (for HP55)
signal ramDataR : arthRegType;
signal ramWrR : std_logic;
signal opcodeRomR : std_logic_vector(9 downto 0);
signal opcodeR : std_logic_vector(9 downto 0);
signal romAddrR : unsigned(ROM_ADDR_LEN-1 downto 0);
signal ramAddrR : ramInxType;
signal carryOutR : std_logic;
signal carry : std_logic;
signal displayEnR : std_logic;
signal subAddLowR : std_logic;
signal bcdDigitA : bcdDigitType;
signal bcdDigitB : bcdDigitType;
signal bcdDigitYR : bcdDigitType;
signal startR, endR : subInxType;
signal startRR : subInxType;
signal errorDetR : std_logic;
signal errorDet : std_logic;
signal keyValidR : std_logic;
signal execFsmStateR : execFsmType;
-- This fuction returns a single vector for addressing the ROM. The address is built from
-- various interal core registers (the PC, ROM Select, Group Select)
function buildRomAddr(pc : unsigned(7 downto 0); romSel : unsigned(2 downto 0); grpSel : unsigned(0 downto 0):="0") return unsigned is
begin
if HP35 then
-- a HP35 only has three ROMs (i.e. romSel is 0, 1, or 2)
return romSel(1 downto 0) & pc;
elsif HP45 then
-- a HP45 has eight ROMs
return romSel & pc;
elsif HP55 then
-- a HP55 has eight ROMs in two groups
return grpSel & romSel & pc;
end if;
return "0";
end function buildRomAddr;
begin
status_o <= sRegR(11 downto 0);
display_en_o <= displayEnR;
-- For each calculator supported, create a signal (errorDet) that
-- pulses when a calculator error occurs. This is done be looking
-- for a certain ROM address, this address must be an address in the
-- original calculator's error routine. This address is different
-- for each calculator.
HP35_ERR : if HP35 generate
begin
errorDet <= '1' when romAddrR = '0' & O"277" else '0';
end generate HP35_ERR;
HP45_ERR : if HP45 generate
begin
-- detect at address 007 of rom #6 ?? or at 001 of rom #6
errorDet <= '1' when romAddrR = "110" & X"07" else '0';
end generate HP45_ERR;
HP55_ERR : if HP55 generate
begin
-- detect at address 302 (octal) of rom #3 ??
errorDet <= '1' when romAddrR = X"3C2" else '0';
end generate HP55_ERR;
-- This process creates the "sticky" version of the error detect signal.
-- "errorDetR" is set on "errorDet" being high and cleared on the next
-- key press. "errorDetR" becomes the error output (port: error_o)
error_detect : process(clk_i, rst_i)
begin
if rst_i = '1' then
errorDetR <= '0';
keyValidR <= '0';
elsif rising_edge(clk_i) then
keyValidR <= keyvalid_i;
if errorDet = '1' then
-- set on error detect
errorDetR <= '1';
elsif keyValidR = '0' and keyvalid_i = '1' then
-- clear on new key press (rising edge of keyvalid_i)
errorDetR <= '0';
end if;
end if;
end process error_detect;
error_o <= errorDetR;
-- generate the ROM address
romAddrR <= buildRomAddr(pcR, romSelR, grpSelR);
-- Create the ROM for the op-codes. This code should infer a Block RAM
-- configured as a ROM.
rom_proc : process(clk_i)
begin
if rising_edge(clk_i) then
opcodeRomR <= ROM(to_integer(romAddrR));
end if;
end process rom_proc;
-- Create a RAM that holds the Rn registers and program steps.
-- The older calculators only need a small memory so just infer FPGA FFs or LUTs.
NO_BIG_RAM : if not HP55 generate
signal ramR : RamType(0 to RAM_SIZE-1);
begin
ram_proc : process(clk_i)
begin
if HP45 then
if rising_edge(clk_i) then
ramDataR <= ramR(ramAddrR);
if ramWrR = '1' then
ramR(ramAddrR) <= cRegR;
end if;
end if;
else
ramDataR <= REG_ZEROS;
end if;
end process ram_proc;
end generate NO_BIG_RAM;
-- The RAM is largest for the HP-55 and a Block RAM is inferred for
-- this calculator.
YES_BIG_RAM : if HP55 generate
type ramType is array (natural range 0 to RAM_SIZE-1) of std_logic_vector(55 downto 0);
signal d : std_logic_vector (55 downto 0);
signal q : std_logic_vector (55 downto 0);
signal ramR : ramType;
attribute ram_style: string;
attribute ram_style of ramR : signal is "block";
begin
-- need to rearrange the nibbles in the register format into a single
-- std_logic_vector so a BRAM will be inferred.
nibble_loop : for i in 0 to WSIZE-1 generate
begin
d((i+1)*4-1 downto i*4) <= std_logic_vector(cRegR(i));
ramDataR(i) <= unsigned(q((i+1)*4-1 downto i*4));
end generate nibble_loop;
da_ram : process (clk_i)
begin
if rising_edge(clk_i) then
q <= ramR(ramAddrR);
if ramWrR = '1' then
ramR(ramAddrR) <= d;
end if;
end if;
end process da_ram;
end generate YES_BIG_RAM;
-- This is it! The main FSM where all the work is done. Op-code decode and
-- execution is done here.
execFsm_proc : process(clk_i, rst_i, pcR, pRegR, opcodeRomR)
variable pc : unsigned(7 downto 0);
variable pRegP1 : unsigned(3 downto 0);
variable pRegM1 : unsigned(3 downto 0);
variable subIdx : subInxType;
variable startIdx: subInxType;
variable endIdx : subInxType;
variable currAddr: natural;
begin
pc := pcR + 1; -- the current PC plus one
pRegP1 := pRegR + 1; -- the current P reg plus one
pRegM1 := pRegR - 1; -- the current P reg minus one
-- subIdx is used by the status register related op-codes
subIdx := to_integer(unsigned(opcodeRomR(9 downto 6)));
-- decode start and stop indices for arth. operations
case opcodeRomR(4 downto 2) is
when "000" =>
-- Digit pointed to by P
startIdx := to_integer(pRegR);
endIdx := to_integer(pRegR);
when "001" =>
-- Mantissa
startIdx := 3;
endIdx := 12;
when "010" =>
-- Exponent (and sign)
startIdx := 0;
endIdx := 2;
when "011" =>
-- The whole register
startIdx := 0;
endIdx := 13;
when "100" =>
-- WP => digits up to and including P
startIdx := 0;
endIdx := to_integer(pRegR);
when "101" =>
-- Mantissa and sign
startIdx := 3;
endIdx := 13;
when "110" =>
-- Exponent sign
startIdx := 2;
endIdx := 2;
when "111" =>
-- Mantissa sign
startIdx := 13;
endIdx := 13;
when others =>
startIdx := 13;
endIdx := 13;
end case;
-- Start of the clocked signals (i.e. FFs)
if rst_i = '1' then
pcR <= (others => '0');
retR <= (others => '0');
romSelR <= (others => '0');
romDelSelR <= (others => '0');
grpSelR <= (others => '0');
grpDelSelR <= (others => '0');
opcodeR <= (others => '0');
sRegR <= (others => '0');
pRegR <= (others => '0');
ramAddrR <= 0;
carryR <= '0';
carryInR <= '0';
displayEnR <= '0';
subAddLowR <= '0';
aRegR <= REG_ZEROS;
bRegR <= REG_ZEROS;
cRegR <= REG_ZEROS;
dRegR <= REG_ZEROS;
eRegR <= REG_ZEROS;
fRegR <= REG_ZEROS;
mRegR <= REG_ZEROS;
t0RegR <= REG_ZEROS;
t1RegR <= REG_ZEROS;
startR <= 0;
endR <= 0;
ramWrR <= '0';
mask_o <=(others => '0');
xreg_o <=(others => '0');
keyCodeR <=(others => '0');
execFsmStateR <= RESET;
elsif rising_edge(clk_i) then
-- synthesis translate_off
-- for simulation:
currAddr := to_integer(romAddrR);
-- synthesis translate_on
ramWrR <= '0';
startRR <= startR;
-- catch any new key presses
if keyvalid_i = '1' then
keyCodeR <= unsigned(keycode_i); -- remember the key pressed
sRegR(0) <= '1'; -- status bit #0 indicates a new key press to the core
end if;
-- The HP-55 has external input status bits (HW status). Any active external bits,
-- get copied to the internal status register. The external bits are used to
-- indicate the state of PROG-TIMER-RUN switch.
if HP55 then
for i in flags_i'range loop
if flags_i(i) = '1' then
sRegR(i) <= '1';
end if;
end loop;
end if;
-- Create the output vectors for the display.
for i in 0 to WSIZE-1 loop
xreg_o((i+1)*4-1 downto i*4) <= std_logic_vector(aRegR(i));
mask_o((i+1)*4-1 downto i*4) <= std_logic_vector(bRegR(i));
end loop;
-- Start of the Finite State Machine
case execFsmStateR is
when RESET =>
-- stays in this state during a core reset.
execFsmStateR <= DECODE;
when DECODE =>
-- inst_en_i is used to create "real" timing of the original calculator
-- inst_en_i pulses high once per the instruction period of the calculator
if inst_en_i = '1' then
opcodeR <= opcodeRomR; -- remember the current op-code
pcR <= pc; -- and the current PC
carryR <= '0'; -- carry clears by default
execFsmStateR <= FETCH; -- most instructions go to this state next
-- decode & execute most opcode types
case opcodeRomR(1 downto 0) is
when "01" =>
-- jump to subroutine
retR <= pc;
pcR <= unsigned(opcodeRomR(9 downto 2));
if HP55 then
romSelR <= romDelSelR;
grpSelR <= grpDelSelR;
end if;
-- synthesis translate_off
-- sim debug
assert false report integer'image(currAddr) & ": JSB "
severity note;
-- synthesis translate_on
when "11" =>
-- jump
if carryR = '0' then
pcR <= unsigned(opcodeRomR(9 downto 2));
if HP55 then
romSelR <= romDelSelR;
grpSelR <= grpDelSelR;
end if;
end if;
when "10" =>
-- arith
startR <= startIdx;
endR <= endIdx;
-- arith operations take more clocks to complete and they
-- are handled in a different part of the FSM.
execFsmStateR <= EXEC_WAIT;
when "00" =>
-- all others
case opcodeRomR(5 downto 2) is
when X"0" =>
-- NOP
-- Plus a few special instuctions for >HP45 models
-- memory and buffer instructions -- which Calc uses these? HP55 uses some?
-- The HP55 uses one "rom address -> buffer" instruction (Opcode: 10000000000) -- what does it do???
-- Its a NOP here!!!
when X"1" =>
-- set status bits
sRegR(subIdx) <= '1';
when X"2" =>
-- not used
when X"3" =>
-- load P reg with constant
pRegR <= unsigned(opcodeRomR(9 downto 6));
when X"4" =>
-- ROM Select and keys->rom address
if opcodeRomR(6) = '1' then
-- jump to key code address
pcR <= keycodeR;
sRegR(0) <= '0';
else
-- ROM Select
romSelR <= unsigned(opcodeRomR(9 downto 7));
if HP55 then
grpSelR <= grpDelSelR;
romDelSelR <= unsigned(opcodeRomR(9 downto 7));
end if;
end if;
when X"5" =>
-- test a status bit
carryR <= sRegR(subIdx);
when X"6" =>
-- load BCD digit into C[P] and decrement P
cRegR(to_integer(pRegR)) <= unsigned(opcodeRomR(9 downto 6));
pRegR <= pRegM1;
when X"7" =>
-- decrement the P reg
pRegR <= pRegM1;
when X"8" =>
-- not used
when X"9" =>
-- clear status bits
sRegR(subIdx) <= '0';
when X"A" =>
-- display/stack/M register stuff
case opcodeRomR(9 downto 7) is
when "000" =>
-- display toggle
displayEnR <= not displayEnR;
when "001" =>
-- C<->M -- swap C and M
mRegR <= cRegR;
cRegR <= mRegR;
when "010" =>
-- push C on to stack
fRegR <= eRegR;
eRegR <= dRegR;
dRegR <= cRegR;
when "011" =>
-- pop A off the stack
aRegR <= dRegR;
dRegR <= eRegR;
eRegR <= fRegR;
when "100" =>
-- display off
displayEnR <= '0';
when "101" =>
-- M->C
cRegR <= mRegR;
when "110" =>
-- down rotate
cRegR <= dRegR;
dRegR <= eRegR;
eRegR <= fRegR;
fRegR <= cRegR;
when "111" =>
-- clear registers
aRegR <= REG_ZEROS;
bRegR <= REG_ZEROS;
cRegR <= REG_ZEROS;
dRegR <= REG_ZEROS;
eRegR <= REG_ZEROS;
fRegR <= REG_ZEROS;
mRegR <= REG_ZEROS;
when others =>
null;
end case;
when X"B" =>
-- test P
if pRegR = unsigned(opcodeRomR(9 downto 6)) then
carryR <= '1';
end if;
when X"C" =>
-- return (and memory access for some calculators)
if HP35 then
pcR <= retR;
else
if opcodeRomR(9) = '0' then
pcR <= retR;
end if;
end if;
if not HP35 then
if opcodeRomR(9 downto 7) = "101" then
-- memory write
ramWrR <= '1';
end if;
end if;
if HP45 then
if opcodeRomR(9 downto 7) = "100" then
-- set memory address
ramAddrR <= to_integer(cRegR(12));
end if;
end if;
if HP55 then
if opcodeRomR(9 downto 7) = "100" then
-- set memory address (C[12]*10+C[11])
ramAddrR <= to_integer(cRegR(12)*10+cRegR(11));
end if;
end if;
when X"D" =>
-- clear status (and delayed ROM and group select for some calculators >HP45)
if not HP55 then
sRegR <= (others => '0');
end if;
-- The HP55 uses both delayed ROM and group selects
if HP55 then
if opcodeRomR(6) = '1' then
-- delayed ROM select
romDelSelR <= unsigned(opcodeRomR(9 downto 7));
elsif opcodeRomR(9) = '1' then
-- delayed Group select
grpDelSelR <= unsigned(opcodeRomR(7 downto 7));
else
-- clear status
sRegR <= (others => '0');
end if;
end if;
when X"E" =>
-- memory store for some calculators
if not HP35 then
-- memory read
cRegR <= ramDataR;
end if;
when X"F" =>
-- increment the P reg
pRegR <= pRegP1;
when others =>
-- for sim
end case;
when others =>
-- for sim
end case;
-- decode arith. opcodes
-- there are 32 arith opcodes (bits 9 downto 5)
carryInR <= '0';
case opcodeRomR(9 downto 5) is
when X"0"&'0' =>
-- if B[ws]=0 carry<=0 else carry<=1
-- Do: 0 - B
t0RegR <= REG_ZEROS;
t1RegR <= bRegR;
subAddLowR <= '1'; -- subtraction
when X"1"&'0' =>
-- if A>=C[ws] carry<=0 else carry<=1
-- Do: A - C
t0RegR <= aRegR;
t1RegR <= cRegR;
subAddLowR <= '1'; -- subtraction
when X"2"&'0' =>
-- b->C[ws]
-- Do: B + 0 => C or 0 + B => C
t0RegR <= REG_ZEROS;
t1RegR <= bRegR;
subAddLowR <= '0'; -- addition
when X"3"&'0' =>
-- 0->C[ws]
-- Do: C - C => C (or B - B => C, ...)
t0RegR <= cRegR;
t1RegR <= cRegR;
subAddLowR <= '1'; -- subtraction
when X"4"&'0' =>
-- shift left A[ws]
for i in 0 to WSIZE-2 loop
t0RegR(i+1) <= aRegR(i);
end loop;
t0RegR(startIdx) <= (others => '0'); -- slow path??
t1RegR <= REG_ZEROS;
subAddLowR <= '0'; -- addition
when X"5"&'0' =>
-- A-C->C[ws]
t0RegR <= aRegR;
t1RegR <= cRegR;
subAddLowR <= '1'; -- subtraction
when X"6"&'0' =>
-- C->A[ws]
-- Do: C + 0 => A or 0 + C => A
t0RegR <= REG_ZEROS;
t1RegR <= cRegR;
subAddLowR <= '0'; -- addition
when X"7"&'0' =>
-- A+C->C[ws]
t0RegR <= aRegR;
t1RegR <= cRegR;
subAddLowR <= '0'; -- addition
when X"8"&'0' =>
-- if A>=B[ws] carry<=0 else carry<=1
-- Do: A - B
t0RegR <= aRegR;
t1RegR <= bRegR;
subAddLowR <= '1'; -- subtraction
when X"9"&'0' =>
-- shift right C[ws]
for i in 0 to WSIZE-2 loop
t0RegR(i) <= cRegR(i+1);
end loop;
t0RegR(endIdx) <= (others => '0'); -- slow path??
t1RegR <= REG_ZEROS;
subAddLowR <= '0'; -- addition
when X"A"&'0' =>
-- shift right B[ws]
for i in 0 to WSIZE-2 loop
t0RegR(i) <= bRegR(i+1);
end loop;
t0RegR(endIdx) <= (others => '0'); -- slow path??
t1RegR <= REG_ZEROS;
subAddLowR <= '0'; -- addition
when X"B"&'0' =>
-- shift right A[ws]
for i in 0 to WSIZE-2 loop
t0RegR(i) <= aRegR(i+1);
end loop;
t0RegR(endIdx) <= (others => '0'); -- slow path??
t1RegR <= REG_ZEROS;
subAddLowR <= '0'; -- addition
when X"C"&'0' =>
-- A-B=>A
t0RegR <= aRegR;
t1RegR <= bRegR;
subAddLowR <= '1'; -- subtraction
when X"D"&'0' =>
-- A-C=>A
t0RegR <= aRegR;
t1RegR <= cRegR;
subAddLowR <= '1'; -- subtraction
when X"E"&'0' =>
-- A+B=>A
t0RegR <= aRegR;
t1RegR <= bRegR;
subAddLowR <= '0'; -- addition
when X"F"&'0' =>
-- A+C=>A
t0RegR <= aRegR;
t1RegR <= cRegR;
subAddLowR <= '0'; -- addition
when X"0"&'1' =>
-- 0->B[ws]
-- Do: B - B => B (or C - C => B, ...)
t0RegR <= bRegR;
t1RegR <= bRegR;
subAddLowR <= '1'; -- subtraction
when X"1"&'1' =>
-- if C[ws]>=1 carry<=0 else carry<=1
-- Do: C - 0 - C1 (C1 == carry set to one)
t0RegR <= cRegR;
t1RegR <= REG_ZEROS;
subAddLowR <= '1'; -- subtraction
carryInR <= '1';
when X"2"&'1' =>
-- 0-C=>C
t0RegR <= REG_ZEROS;
t1RegR <= cRegR;
subAddLowR <= '1'; -- subtraction
when X"3"&'1' =>
-- 0-C-1=>C
t0RegR <= REG_ZEROS;
t1RegR <= cRegR;
subAddLowR <= '1'; -- subtraction
carryInR <= '1';
when X"4"&'1' =>
-- A->B[ws]
-- Do: A + 0 => B
t0RegR <= aRegR;
t1RegR <= REG_ZEROS;
subAddLowR <= '0'; -- addition
when X"5"&'1' =>
-- C - 1 => C
-- Do: C - 0 - C1 => C (C1 == carry set to one)
t0RegR <= cRegR;
t1RegR <= REG_ZEROS;
subAddLowR <= '1'; -- subtraction
carryInR <= '1';
when X"6"&'1' =>
-- if C[ws]=0 carry<=0 else carry<=1
-- Do: 0 - C
t0RegR <= REG_ZEROS;
t1RegR <= cRegR;
subAddLowR <= '1'; -- subtraction
when X"7"&'1' =>
-- C + 1 => C
-- Do: C + 0 + C1 => C (C1 == carry set to one)
t0RegR <= cRegR;
t1RegR <= REG_ZEROS;
subAddLowR <= '0'; -- addition
carryInR <= '1';
when X"8"&'1' =>
-- exchange B and C[ws]
t0RegR <= bRegR;
t1RegR <= cRegR;
when X"9"&'1' =>
-- if A[ws]>=1 carry<=0 else carry<=1
-- Do: A - 0 - C1 (C1 == carry set to one)
t0RegR <= aRegR;
t1RegR <= REG_ZEROS;
subAddLowR <= '1'; -- subtraction
carryInR <= '1';
when X"A"&'1' =>
-- C + C => C
t0RegR <= cRegR;
t1RegR <= cRegR;
subAddLowR <= '0'; -- addition
when X"B"&'1' =>
-- 0->A[ws]
-- Do: A - A => A (or C - C => A, ...)
t0RegR <= aRegR;
t1RegR <= aRegR;
subAddLowR <= '1'; -- subtraction
when X"C"&'1' =>
-- exchange A and B[ws]
t0RegR <= aRegR;
t1RegR <= bRegR;
when X"D"&'1' =>
-- A - 1 => A
-- Do: A - 0 - C1 => A (C1 == carry set to one)
t0RegR <= aRegR;
t1RegR <= REG_ZEROS;
subAddLowR <= '1'; -- subtraction
carryInR <= '1';
when X"E"&'1' =>
-- exchange A and C[ws]
t0RegR <= aRegR;
t1RegR <= cRegR;
when X"F"&'1' =>
-- A + 1 => A
-- Do: A + 0 + C1 => A (C1 == carry set to one)
t0RegR <= aRegR;
t1RegR <= REG_ZEROS;
subAddLowR <= '0'; -- addition
carryInR <= '1';
when others =>
end case;
end if; -- inst_en_i = '1'
when FETCH =>
-- this is just a wait state to allow the next opcode to be fetched from the ROM.
execFsmStateR <= DECODE;
when EXEC_WAIT =>
-- start executing a arith. op-code
if startR /= endR then
startR <= startR + 1;
end if;
execFsmStateR <= EXECUTE;
when EXECUTE =>
-- Process all BCD digits in this state
carryR <= carryOutR;
if startR /= endR then
startR <= startR + 1;
end if;
if startRR = endR then
execFsmStateR <= DECODE;
end if;
-- there are 32 arith opcodes (bits 9 downto 5)
case opcodeR(9 downto 5) is
when X"0"&'0' =>
-- if B[ws]=0 carry<=0 else carry<=1
-- Do: 0 - B
-- Only the carry out is generated for this instruction
when X"1"&'0' =>
-- if A>=C[ws] carry<=0 else carry<=1
-- Do: A - C
-- Only the carry out is generated for this instruction
when X"2"&'0' =>
-- b->C[ws]
-- Do: B + 0 => C or 0 + B => C
cRegR(startRR) <= bcdDigitYR;
when X"3"&'0' =>
-- 0->C[ws]
-- Do: C - C => C (or B - B => C, ...)
cRegR(startRR) <= bcdDigitYR;
when X"4"&'0' =>
-- shift left A[ws]
aRegR(startRR) <= bcdDigitYR;
carryR <= '0'; -- keep carry cleared
when X"5"&'0' =>
-- A-C->C[ws]
cRegR(startRR) <= bcdDigitYR;
when X"6"&'0' =>
-- C->A[ws]
-- Do: C + 0 => A or 0 + C => A
aRegR(startRR) <= bcdDigitYR;
when X"7"&'0' =>
-- A+C->C[ws]
cRegR(startRR) <= bcdDigitYR;
when X"8"&'0' =>
-- if A>=B[ws] carry<=0 else carry<=1
-- Do: A - B
-- Only the carry out is generated for this instruction
when X"9"&'0' =>
-- shift right C[ws]
cRegR(startRR) <= bcdDigitYR;
carryR <= '0'; -- keep carry cleared
when X"A"&'0' =>
-- shift right B[ws]
bRegR(startRR) <= bcdDigitYR;
carryR <= '0'; -- keep carry cleared
when X"B"&'0' =>
-- shift right A[ws]
aRegR(startRR) <= bcdDigitYR;
carryR <= '0'; -- keep carry cleared
when X"C"&'0' =>
-- A-B=>A
aRegR(startRR) <= bcdDigitYR;
when X"D"&'0' =>
-- A-C=>A
aRegR(startRR) <= bcdDigitYR;
when X"E"&'0' =>
-- A+B=>A
aRegR(startRR) <= bcdDigitYR;
when X"F"&'0' =>
-- A+C=>A
aRegR(startRR) <= bcdDigitYR;
when X"0"&'1' =>
-- 0->B[ws]
-- Do: B - B => B (or C - C => B, ...)
bRegR(startRR) <= bcdDigitYR;
when X"1"&'1' =>
-- if C[ws]>=1 carry<=0 else carry<=1
-- Do: C - 0 - C1 (C1 == carry set to one)
-- Only the carry out is generated for this instruction
when X"2"&'1' =>
-- 0-C=>C
cRegR(startRR) <= bcdDigitYR;
when X"3"&'1' =>
-- 0-C-1=>C
cRegR(startRR) <= bcdDigitYR;
when X"4"&'1' =>
-- A->B[ws]
-- Do: A + 0 => B
bRegR(startRR) <= bcdDigitYR;
when X"5"&'1' =>
-- C - 1 => C
-- Do: C - 0 - C1 => C (C1 == carry set to one)
cRegR(startRR) <= bcdDigitYR;
when X"6"&'1' =>
-- if C[ws]=0 carry<=0 else carry<=1
-- Do: 0 - C
-- Only the carry out is generated for this instruction
when X"7"&'1' =>
-- C + 1 => C
-- Do: C + 0 + C1 => C (C1 == carry set to one)
cRegR(startRR) <= bcdDigitYR;
when X"8"&'1' =>
-- exchange B and C[ws]
cRegR(startRR) <= t0RegR(startRR);
bRegR(startRR) <= t1RegR(startRR);
carryR <= '0'; -- keep carry cleared
when X"9"&'1' =>
-- if A[ws]>=1 carry<=0 else carry<=1
-- Do: A - 0 - C1 (C1 == carry set to one)
-- Only the carry out is generated for this instruction
when X"A"&'1' =>
-- C + C => C
cRegR(startRR) <= bcdDigitYR;
when X"B"&'1' =>
-- 0->A[ws]
-- Do: A - A => A (or C - C => A, ...)
aRegR(startRR) <= bcdDigitYR;
when X"C"&'1' =>
-- exchange A and B[ws]
bRegR(startRR) <= t0RegR(startRR);
aRegR(startRR) <= t1RegR(startRR);
carryR <= '0'; -- keep carry cleared
when X"D"&'1' =>
-- A - 1 => A
-- Do: A - 0 - C1 => A (C1 == carry set to one)
aRegR(startRR) <= bcdDigitYR;
when X"E"&'1' =>
-- exchange A and C[ws]
cRegR(startRR) <= t0RegR(startRR);
aRegR(startRR) <= t1RegR(startRR);
carryR <= '0'; -- keep carry cleared
when X"F"&'1' =>
-- A + 1 => A
-- Do: A + 0 + C1 => A (C1 == carry set to one)
aRegR(startRR) <= bcdDigitYR;
when others =>
end case;
when others =>
end case;
end if;
end process execFsm_proc;
-- Setup the inputs to the ALU
bcdDigitA <= t0RegR(startR);
bcdDigitB <= t1RegR(startR);
carry <= carryOutR when execFsmStateR = EXECUTE else carryInR;
-- The ALU. There are two versions RTL and LUT. The LUT version uses a BRAM
-- as a large look up table to perform the BCD math. Depending on the FPGA
-- and the max clock rate, one may be better than the other.
--bcdALU : entity work.bcd_alu(lut)
bcdALU : entity work.bcd_alu(rtl)
port map (
clk_i => clk_i,
rst_i => rst_i,
a_i => bcdDigitA,
b_i => bcdDigitB,
carry_i => carry,
subAddLow_i => subAddLowR,
y_o => bcdDigitYR,
carray_o => carryOutR
);
end rtl;
-- Its been nice but the end is here.
| mit |
vhdlnerd/classicHp | src/ps2_keyboard_pack.vhd | 1 | 18206 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package ps2_keyboard_pack is
subtype keyCodeType is std_logic_vector(8 downto 0);
type keyLutType is array (natural range 0 to 256*8-1) of keyCodeType;
constant INVALID_KEY : keyCodeType := '1' & X"00";
constant L_SHIFT_KEY : keyCodeType := '1' & X"01";
constant R_SHIFT_KEY : keyCodeType := '1' & X"02";
constant L_CONTROL_KEY : keyCodeType := '1' & X"03";
constant R_CONTROL_KEY : keyCodeType := '1' & X"04";
constant L_ALT_KEY : keyCodeType := '1' & X"05";
constant R_ALT_KEY : keyCodeType := '1' & X"06";
constant L_GUI_KEY : keyCodeType := '1' & X"07";
constant R_GUI_KEY : keyCodeType := '1' & X"08";
constant APPS_KEY : keyCodeType := '1' & X"09";
constant KEY_BREAK : keyCodeType := '1' & X"0A";
constant EXTENDED : keyCodeType := '1' & X"0B";
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
constant KEY_LUT_HP35 : keyLutType := (
-- LUT Address: cntl & shift & ext & code
16#00E# => O"077", -- ` Special key to control LED brightness -- not a keycode for the HP Calc core!
16#070# => O"044", -- 0 (keypad)
16#069# => O"034", -- 1 (keypad)
16#072# => O"033", -- 2 (keypad)
16#07A# => O"032", -- 3 (keypad)
16#06B# => O"024", -- 4 (keypad)
16#073# => O"023", -- 5 (keypad)
16#074# => O"022", -- 6 (keypad)
16#06C# => O"064", -- 7 (keypad)
16#075# => O"063", -- 8 (keypad)
16#07D# => O"062", -- 9 (keypad)
16#071# => O"043", -- . (keypad)
16#15A# => O"076", -- Enter (keypad)
16#079# => O"026", -- + (keypad)
16#07B# => O"066", -- - (keypad)
16#07C# => O"036", -- * (keypad)
16#14A# => O"046", -- / (keypad)
16#045# => O"044", -- 0
16#016# => O"034", -- 1
16#01E# => O"033", -- 2
16#026# => O"032", -- 3
16#025# => O"024", -- 4
16#02E# => O"023", -- 5
16#036# => O"022", -- 6
16#03D# => O"064", -- 7
16#03E# => O"063", -- 8
16#046# => O"062", -- 9
16#049# => O"043", -- .
16#05A# => O"076", -- Enter
16#255# => O"026", -- +
16#04E# => O"066", -- -
16#23E# => O"036", -- *
16#04A# => O"046", -- /
16#171# => O"070", -- Delete (do: Clx)
16#066# => O"070", -- BackSpace (do: Clx)
16#04D# => O"042", -- p (do: PI)
16#24D# => O"042", -- P (do: PI)
16#024# => O"072", -- e (do: EEX)
16#224# => O"072", -- E (do: EEX)
16#05D# => O"073", -- \ (do: CHS)
16#005# => O"054", -- F1 (do: arc)
16#006# => O"053", -- F2 (do: sin)
16#004# => O"052", -- F3 (do: cos)
16#00C# => O"050", -- F4 (do: tan)
16#003# => O"003", -- F5 (do: ln)
16#203# => O"002", -- shift-F5 (do: e^x)
16#00B# => O"004", -- F6 (do: log)
16#20B# => O"006", -- shift-F6 (do: x^y)
16#083# => O"016", -- F7 (do: 1/x)
16#283# => O"056", -- shift-F7 (do: SQR)
16#00A# => O"012", -- F8 (do: STO)
16#20A# => O"010", -- shift-F8 (do: RCL)
16#001# => O"014", -- F9 (do: x<>y)
16#201# => O"013", -- shift-F9 (do: Roll Down Stack)
16#009# => O"072", -- F10 (do: EEX)
16#209# => O"042", -- shift-F10 (do: PI)
16#078# => O"073", -- F11 (do: CHS)
16#007# => O"070", -- F12 (do: CLx)
16#207# => O"000", -- shift-F12 (do: CLr)
-- 16#222# => O"016", -- X (do: 1/x)
-- 16#41A# => O"016", -- cntl-Z (do: 1/x)
16#0E0# => EXTENDED, -- Extended keycode prefix
16#2E0# => EXTENDED, -- Extended keycode prefix
16#4E0# => EXTENDED, -- Extended keycode prefix
16#6E0# => EXTENDED, -- Extended keycode prefix
16#0F0# => KEY_BREAK, -- Key break (key release) prefix
16#1F0# => KEY_BREAK, -- Key break (key release) prefix
16#2F0# => KEY_BREAK, -- Key break (key release) prefix
16#3F0# => KEY_BREAK, -- Key break (key release) prefix
16#4F0# => KEY_BREAK, -- Key break (key release) prefix
16#5F0# => KEY_BREAK, -- Key break (key release) prefix
16#6F0# => KEY_BREAK, -- Key break (key release) prefix
16#7F0# => KEY_BREAK, -- Key break (key release) prefix
16#012# => L_SHIFT_KEY,
16#212# => L_SHIFT_KEY,
16#412# => L_SHIFT_KEY,
16#612# => L_SHIFT_KEY,
16#059# => R_SHIFT_KEY,
16#259# => R_SHIFT_KEY,
16#459# => R_SHIFT_KEY,
16#659# => R_SHIFT_KEY,
16#014# => L_CONTROL_KEY,
16#214# => L_CONTROL_KEY,
16#414# => L_CONTROL_KEY,
16#614# => L_CONTROL_KEY,
16#114# => R_CONTROL_KEY,
16#314# => R_CONTROL_KEY,
16#514# => R_CONTROL_KEY,
16#714# => R_CONTROL_KEY,
others => INVALID_KEY
); -- End: HP35
constant KEY_LUT_HP45 : keyLutType := (
-- LUT Address: cntl & shift & ext & code
16#00E# => O"077", -- ` Special key to control LED brightness -- not a keycode for the HP Calc core!
16#070# => O"044", -- 0 (keypad)
16#069# => O"034", -- 1 (keypad)
16#072# => O"033", -- 2 (keypad)
16#07A# => O"032", -- 3 (keypad)
16#06B# => O"024", -- 4 (keypad)
16#073# => O"023", -- 5 (keypad)
16#074# => O"022", -- 6 (keypad)
16#06C# => O"064", -- 7 (keypad)
16#075# => O"063", -- 8 (keypad)
16#07D# => O"062", -- 9 (keypad)
16#071# => O"043", -- . (keypad)
16#15A# => O"076", -- Enter (keypad)
16#079# => O"026", -- + (keypad)
16#07B# => O"066", -- - (keypad)
16#07C# => O"036", -- * (keypad)
16#14A# => O"046", -- / (keypad)
16#045# => O"044", -- 0
16#016# => O"034", -- 1
16#01E# => O"033", -- 2
16#026# => O"032", -- 3
16#025# => O"024", -- 4
16#02E# => O"023", -- 5
16#036# => O"022", -- 6
16#03D# => O"064", -- 7
16#03E# => O"063", -- 8
16#046# => O"062", -- 9
16#049# => O"043", -- .
16#05A# => O"076", -- Enter
16#255# => O"026", -- +
16#04E# => O"066", -- -
16#23E# => O"036", -- *
16#04A# => O"046", -- /
16#171# => O"070", -- Delete (do: Clx)
16#066# => O"070", -- BackSpace (do: Clx)
16#029# => O"000", -- Space (do: Yellow Shift)
-- 16#04D# => O"042", -- p (do: PI)
-- 16#24D# => O"042", -- P (do: PI)
16#024# => O"072", -- e (do: EEX)
16#224# => O"072", -- E (do: EEX)
16#22E# => O"010", -- % (do: %)
16#05D# => O"073", -- \ (do: CHS)
16#005# => O"056", -- F1 (do: x^2)
16#006# => O"053", -- F2 (do: sin)
16#004# => O"052", -- F3 (do: cos)
16#00C# => O"050", -- F4 (do: tan)
16#003# => O"006", -- F5 (do: 1/x)
-- 16#203# => O"002", -- shift-F5 (do: e^x)
16#00B# => O"004", -- F6 (do: ln)
16#20B# => O"042", -- shift-F6 (do: Sigma +)
16#083# => O"003", -- F7 (do: e^x)
16#283# => O"010", -- shift-F7 (do: %)
16#00A# => O"002", -- F8 (do: FIX)
16#20A# => O"054", -- shift-F8 (do: ->P)
16#001# => O"016", -- F9 (do: x<>y)
16#201# => O"076", -- shift-F9 (do: Enter)
16#009# => O"014", -- F10 (do: Roll Down)
16#209# => O"073", -- shift-F10 (do: CHS)
16#078# => O"013", -- F11 (do: STO)
16#278# => O"072", -- shift-F11 (do: EEX)
16#007# => O"012", -- F12 (do: RCL)
16#207# => O"070", -- shift-F12 (do: CLX)
-- 16#222# => O"016", -- X (do: 1/x)
-- 16#41A# => O"016", -- cntl-Z (do: 1/x)
16#0E0# => EXTENDED, -- Extended keycode prefix
16#2E0# => EXTENDED, -- Extended keycode prefix
16#4E0# => EXTENDED, -- Extended keycode prefix
16#6E0# => EXTENDED, -- Extended keycode prefix
16#0F0# => KEY_BREAK, -- Key break (key release) prefix
16#1F0# => KEY_BREAK, -- Key break (key release) prefix
16#2F0# => KEY_BREAK, -- Key break (key release) prefix
16#3F0# => KEY_BREAK, -- Key break (key release) prefix
16#4F0# => KEY_BREAK, -- Key break (key release) prefix
16#5F0# => KEY_BREAK, -- Key break (key release) prefix
16#6F0# => KEY_BREAK, -- Key break (key release) prefix
16#7F0# => KEY_BREAK, -- Key break (key release) prefix
16#012# => L_SHIFT_KEY,
16#212# => L_SHIFT_KEY,
16#412# => L_SHIFT_KEY,
16#612# => L_SHIFT_KEY,
16#059# => R_SHIFT_KEY,
16#259# => R_SHIFT_KEY,
16#459# => R_SHIFT_KEY,
16#659# => R_SHIFT_KEY,
16#014# => L_CONTROL_KEY,
16#214# => L_CONTROL_KEY,
16#414# => L_CONTROL_KEY,
16#614# => L_CONTROL_KEY,
16#114# => R_CONTROL_KEY,
16#314# => R_CONTROL_KEY,
16#514# => R_CONTROL_KEY,
16#714# => R_CONTROL_KEY,
others => INVALID_KEY
); -- End: HP45
constant KEY_LUT_HP55 : keyLutType := (
-- LUT Address: cntl & shift & ext & code
16#00E# => O"077", -- ` Special key to control LED brightness -- not a keycode for the HP Calc core!
16#02D# => O"007", -- r Special key for switch set to RUN -- not a keycode for the HP Calc core!
16#22D# => O"007", -- R Special key for switch set to RUN -- not a keycode for the HP Calc core!
16#04D# => O"017", -- p Special key for switch set to PROG -- not a keycode for the HP Calc core!
16#24D# => O"017", -- P Special key for switch set to PROG -- not a keycode for the HP Calc core!
16#02C# => O"027", -- t Special key for switch set to TIMER -- not a keycode for the HP Calc core!
16#22C# => O"027", -- T Special key for switch set to TIMER -- not a keycode for the HP Calc core!
16#01B# => O"037", -- s Special key for RealSpeede -- not a keycode for the HP Calc core!
16#21B# => O"037", -- S Special key for RealSpeede -- not a keycode for the HP Calc core!
16#02B# => O"047", -- f Special key for full speed -- not a keycode for the HP Calc core!
16#22B# => O"047", -- F Special key for full speed -- not a keycode for the HP Calc core!
16#070# => O"044", -- 0 (keypad)
16#069# => O"034", -- 1 (keypad)
16#072# => O"033", -- 2 (keypad)
16#07A# => O"032", -- 3 (keypad)
16#06B# => O"024", -- 4 (keypad)
16#073# => O"023", -- 5 (keypad)
16#074# => O"022", -- 6 (keypad)
16#06C# => O"064", -- 7 (keypad)
16#075# => O"063", -- 8 (keypad)
16#07D# => O"062", -- 9 (keypad)
16#071# => O"043", -- . (keypad)
16#15A# => O"076", -- Enter (keypad)
16#079# => O"026", -- + (keypad)
16#07B# => O"066", -- - (keypad)
16#07C# => O"036", -- * (keypad)
16#14A# => O"046", -- / (keypad)
16#045# => O"044", -- 0
16#016# => O"034", -- 1
16#01E# => O"033", -- 2
16#026# => O"032", -- 3
16#025# => O"024", -- 4
16#02E# => O"023", -- 5
16#036# => O"022", -- 6
16#03D# => O"064", -- 7
16#03E# => O"063", -- 8
16#046# => O"062", -- 9
16#049# => O"043", -- .
16#05A# => O"076", -- Enter
16#255# => O"026", -- +
16#04E# => O"066", -- -
16#23E# => O"036", -- *
16#04A# => O"046", -- /
16#171# => O"070", -- Delete (do: Clx)
16#066# => O"070", -- BackSpace (do: Clx)
16#029# => O"016", -- Space (do: Yellow Shift)
16#076# => O"014", -- ESC (do: Blue Shift)
16#024# => O"072", -- e (do: EEX)
16#224# => O"072", -- E (do: EEX)
16#22E# => O"002", -- % (do: %)
16#05D# => O"073", -- \ (do: CHS)
16#005# => O"006", -- F1 (do: Sigma +)
16#006# => O"004", -- F2 (do: y^x)
16#004# => O"003", -- F3 (do: 1/x)
16#00C# => O"002", -- F4 (do: %)
16#003# => O"056", -- F5 (do: y-hat)
16#00B# => O"054", -- F6 (do: x<->y)
16#083# => O"053", -- F7 (do: Roll Down)
16#00A# => O"052", -- F8 (do: FIX)
16#001# => O"010", -- F9 (do: GTO)
16#201# => O"042", -- shift-F9 (do: R/S)
16#009# => O"073", -- F10 (do: CHS)
--16#209# => O"073", -- shift-F10 (do: CHS)
16#078# => O"013", -- F11 (do: STO)
16#278# => O"000", -- shift-F11 (do: BST)
16#007# => O"012", -- F12 (do: RCL)
16#207# => O"050", -- shift-F12 (do: SST)
16#175# => O"000", -- Up Arrow (do: BST)
16#172# => O"050", -- Down Arrow (do: SST)
16#174# => O"042", -- Right Arrow (do: R/S)
16#034# => O"010", -- g (do: GTO)
16#234# => O"010", -- G (do: GTO)
-- 16#41A# => O"016", -- cntl-Z (do: 1/x)
16#0E0# => EXTENDED, -- Extended keycode prefix
16#2E0# => EXTENDED, -- Extended keycode prefix
16#4E0# => EXTENDED, -- Extended keycode prefix
16#6E0# => EXTENDED, -- Extended keycode prefix
16#0F0# => KEY_BREAK, -- Key break (key release) prefix
16#1F0# => KEY_BREAK, -- Key break (key release) prefix
16#2F0# => KEY_BREAK, -- Key break (key release) prefix
16#3F0# => KEY_BREAK, -- Key break (key release) prefix
16#4F0# => KEY_BREAK, -- Key break (key release) prefix
16#5F0# => KEY_BREAK, -- Key break (key release) prefix
16#6F0# => KEY_BREAK, -- Key break (key release) prefix
16#7F0# => KEY_BREAK, -- Key break (key release) prefix
16#012# => L_SHIFT_KEY,
16#212# => L_SHIFT_KEY,
16#412# => L_SHIFT_KEY,
16#612# => L_SHIFT_KEY,
16#059# => R_SHIFT_KEY,
16#259# => R_SHIFT_KEY,
16#459# => R_SHIFT_KEY,
16#659# => R_SHIFT_KEY,
16#014# => L_CONTROL_KEY,
16#214# => L_CONTROL_KEY,
16#414# => L_CONTROL_KEY,
16#614# => L_CONTROL_KEY,
16#114# => R_CONTROL_KEY,
16#314# => R_CONTROL_KEY,
16#514# => R_CONTROL_KEY,
16#714# => R_CONTROL_KEY,
others => INVALID_KEY
); -- End: HP55
end ps2_keyboard_pack;
package body ps2_keyboard_pack is
end ps2_keyboard_pack;
| mit |
vhdlnerd/classicHp | src/interface_ps2.vhd | 1 | 7858 | -- Hi Emacs, this is -*- mode: vhdl -*-
----------------------------------------------------------------------------------
-- Unidirectional PS2 Interface (device -> host)
-- For connect mouse/keyboard
--
-- The PS/2 mouse and keyboard implement a bidirectional synchronous serial
-- protocol. The bus is "idle" when both lines are high (open-collector).
-- THIS A *UNIDIRECTIONAL* INTERFACE (DEVICE -> HOST)
--
-- Javier Valcarce García, [email protected]
-- $Id$
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.utils.all;
entity interface_ps2 is
port (
reset : in std_logic;
clk : in std_logic; -- faster than kbclk
kbdata : in std_logic;
kbclk : in std_logic;
newdata : out std_logic; -- one clock cycle pulse, notify a new byte has arrived
do : out std_logic_vector(7 downto 0)
);
end interface_ps2;
-------------------------------------------------------------------------------
architecture behavioral of interface_ps2 is
signal st : std_logic;
signal sh : std_logic;
signal s1 : std_logic;
signal s2 : std_logic;
signal kbclk_fe : std_logic;
signal shift9 : std_logic_vector(8 downto 0);
signal error : std_logic;
begin
-------------------------------------------------------------------------------
-- Edge detector
-------------------------------------------------------------------------------
process (reset, clk)
begin
if reset = '1' then
s1 <= '0';
s2 <= '0';
elsif rising_edge(clk) then
s2 <= s1;
s1 <= kbclk;
end if;
end process;
kbclk_fe <= '1' when s1 = '0' and s2 = '1' else '0';
-------------------------------------------------------------------------------
-- 9-bit shift register to store received data
-- 11-bit frame, LSB first: 1 start bit, 8 data bits, 1 parity bit, 1 stop bit
-------------------------------------------------------------------------------
process (reset, clk)
begin
if reset = '1' then
shift9 <= "000000000";
elsif rising_edge(clk) then
if sh = '1' then
shift9(7 downto 0) <= shift9(8 downto 1);
shift9(8) <= kbdata;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Output register
-------------------------------------------------------------------------------
process (reset, clk)
begin
if reset = '1' then
do <= "00000000";
elsif rising_edge(clk) then
if st = '1' then
do <= shift9(7 downto 0);
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- parity error detector (XOR gate) The parity bit is at shift9(8)
-------------------------------------------------------------------------------
error <= not (shift9(0) xor shift9(1) xor shift9(2) xor shift9(3) xor shift9(4) xor
shift9(5) xor shift9(6) xor shift9(7) xor shift9(8));
-------------------------------------------------------------------------------
-- Control Unit
-------------------------------------------------------------------------------
CTL : block
type state_type is (idle, start, bit_1a, bit_1b, bit_2a, bit_2b,
bit_3a, bit_3b, bit_4a, bit_4b, bit_5a, bit_5b,
bit_6a, bit_6b, bit_7a, bit_7b, bit_8a, bit_8b,
bit_9a, bit_9b, stop, store, notify);
signal state : state_type;
signal op : std_logic_vector(2 downto 0);
begin
-- 2 procesos para separar la parte secuencial de la combinacional, de
-- esta forma las salidas no son registros ("registered outputs") y por
-- tanto no hay un ciclo de reloj de espera
process (reset, clk)
begin
if reset = '1' then
state <= idle;
elsif rising_edge(clk) then
case (state) is
when idle =>
if kbclk_fe = '1' and kbdata = '0' then
state <= start; --e0; --DEBUG
end if;
when start =>
if kbclk_fe = '1' then
state <= bit_1a;
end if;
when bit_1a => state <= bit_1b;
when bit_1b => if kbclk_fe = '1' then state <= bit_2a; end if;
when bit_2a => state <= bit_2b;
when bit_2b => if kbclk_fe = '1' then state <= bit_3a; end if;
when bit_3a => state <= bit_3b;
when bit_3b => if kbclk_fe = '1' then state <= bit_4a; end if;
when bit_4a => state <= bit_4b;
when bit_4b => if kbclk_fe = '1' then state <= bit_5a; end if;
when bit_5a => state <= bit_5b;
when bit_5b => if kbclk_fe = '1' then state <= bit_6a; end if;
when bit_6a => state <= bit_6b;
when bit_6b => if kbclk_fe = '1' then state <= bit_7a; end if;
when bit_7a => state <= bit_7b;
when bit_7b => if kbclk_fe = '1' then state <= bit_8a; end if;
when bit_8a => state <= bit_8b;
when bit_8b => if kbclk_fe = '1' then state <= bit_9a; end if;
when bit_9a => state <= bit_9b;
when bit_9b =>
if kbclk_fe = '1' then
if kbdata = '1' then
state <= stop;
else
state <= idle;
end if;
end if;
when stop =>
if error = '0' then
state <= store;
else
state <= idle;
end if;
when store => state <= notify;
when notify => state <= idle;
end case;
end if;
end process;
-- 13 uórdenes para la ruta de datos:
-- Agrupamos todas las uórdenes en el vector op para que el código quede más
-- compacto y legible
sh <= op(2);
st <= op(1);
newdata <= op(0); --out port, actually
process (state)
begin
-- La función TRIM elimina los espacios de la cadena y devuelve un tipo
-- std_logic_vector con los elementos restantes (definida en work.conf)
case state is
--SH ST NEW
when idle => op <= STRTRIM("0 0 0");
when start => op <= STRTRIM("0 0 0");
when bit_1a => op <= STRTRIM("1 0 0");
when bit_1b => op <= STRTRIM("0 0 0");
when bit_2a => op <= STRTRIM("1 0 0");
when bit_2b => op <= STRTRIM("0 0 0");
when bit_3a => op <= STRTRIM("1 0 0");
when bit_3b => op <= STRTRIM("0 0 0");
when bit_4a => op <= STRTRIM("1 0 0");
when bit_4b => op <= STRTRIM("0 0 0");
when bit_5a => op <= STRTRIM("1 0 0");
when bit_5b => op <= STRTRIM("0 0 0");
when bit_6a => op <= STRTRIM("1 0 0");
when bit_6b => op <= STRTRIM("0 0 0");
when bit_7a => op <= STRTRIM("1 0 0");
when bit_7b => op <= STRTRIM("0 0 0");
when bit_8a => op <= STRTRIM("1 0 0");
when bit_8b => op <= STRTRIM("0 0 0");
when bit_9a => op <= STRTRIM("1 0 0");
when bit_9b => op <= STRTRIM("0 0 0");
when stop => op <= STRTRIM("0 0 0");
when store => op <= STRTRIM("0 1 0");
when notify => op <= STRTRIM("0 0 1");
end case;
end process;
end block CTL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end behavioral;
| mit |
vhdlnerd/classicHp | src/ps2_keyboard.vhd | 1 | 5880 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:50:53 10/29/2012
-- Design Name:
-- Module Name: ps2_keyboard - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ps2_keyboard_pack.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ps2_keyboard is
generic (KEY_LUT : keyLutType);
port ( clk_i : in std_logic;
rst_i : in std_logic;
ps2_clk_i : in std_logic;
ps2_data_i : in std_logic;
key_rdy_o : out std_logic;
key_data_o : out std_logic_vector (7 downto 0));
end ps2_keyboard;
architecture rtl of ps2_keyboard is
type FsmType is (IDLE, BREAK);
signal lutDataR : keyCodeType;
signal lutAddr : unsigned(10 downto 0);
signal keyData : std_logic_vector(7 downto 0);
signal keyDataR : std_logic_vector(7 downto 0);
signal keyRdyR : std_logic;
signal keyRdyOutR : std_logic;
signal keyRdy : std_logic;
signal extR : std_logic;
signal breakR : std_logic;
signal lShR : std_logic;
signal rShR : std_logic;
signal lCntlR : std_logic;
signal rCntlR : std_logic;
signal fsmR : FsmType;
begin
lut_proc : process(clk_i)
begin
if rising_edge(clk_i) then
lutDataR <= KEY_LUT(to_integer(lutAddr));
end if;
end process lut_proc;
key_rdy_o <= keyRdyOutR;
key_data_o <= keyDataR;
lutAddr <= (lCntlR or rCntlR) & (lShR or rShR) & extR & unsigned(keyData);
fsm_proc : process(clk_i, rst_i)
begin
if rst_i = '1' then
fsmR <= IDLE;
keyRdyR <= '0';
keyRdyOutR <= '0';
extR <= '0';
breakR <= '0';
lShR <= '0';
rShR <= '0';
lCntlR <= '0';
rCntlR <= '0';
keyDataR <= (others => '0');
elsif rising_edge(clk_i) then
keyRdyR <= keyRdy;
keyRdyOutR <= '0';
case fsmR is
when IDLE =>
if keyRdyR = '1' then
if lutDataR(8) = '0' then
-- normal key
if breakR /= '1' then
keyRdyOutR <= '1';
end if;
keyDataR <= lutDataR(keyDataR'range);
extR <= '0';
breakR <= '0';
else
-- special key
if lutDataR = EXTENDED then
extR <= '1';
elsif lutDataR = KEY_BREAK then
breakR <= '1';
elsif lutDataR = L_SHIFT_KEY then
if breakR = '1' then
lShR <= '0';
else
lShR <= '1';
end if;
extR <= '0';
breakR <= '0';
elsif lutDataR = R_SHIFT_KEY then
if breakR = '1' then
rShR <= '0';
else
rShR <= '1';
end if;
extR <= '0';
breakR <= '0';
elsif lutDataR = L_CONTROL_KEY then
if breakR = '1' then
lCntlR <= '0';
else
lCntlR <= '1';
end if;
extR <= '0';
breakR <= '0';
elsif lutDataR = R_CONTROL_KEY then
if breakR = '1' then
rCntlR <= '0';
else
rCntlR <= '1';
end if;
extR <= '0';
breakR <= '0';
else
extR <= '0';
breakR <= '0';
end if;
end if;
end if;
when others =>
end case;
end if;
end process fsm_proc;
ps2 : entity work.interface_ps2(behavioral)
port map(
reset => rst_i,
clk => clk_i, -- faster than kbclk
kbdata => ps2_data_i,
kbclk => ps2_clk_i,
newdata => keyRdy, -- one clock cycle pulse, notify a new byte has arrived
do => keyData
);
end rtl;
| mit |
vhdlnerd/classicHp | src/rom_pack.vhd | 1 | 172536 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,",
-- constants, and functions",
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package rom_pack is
type RomType is array (natural range <>) of std_logic_vector(9 downto 0);
constant ROM_35 : RomType := (
8#0000# => '0' & O"335",
8#0001# => '1' & O"377",
8#0002# => '1' & O"044",
8#0003# => '0' & O"027",
8#0004# => '0' & O"504",
8#0005# => '1' & O"104",
8#0006# => '0' & O"204",
8#0007# => '0' & O"420",
8#0010# => '1' & O"321",
8#0011# => '1' & O"773",
8#0012# => '0' & O"137",
8#0013# => '0' & O"303",
8#0014# => '0' & O"650",
8#0015# => '1' & O"547",
8#0016# => '1' & O"356",
8#0017# => '1' & O"742",
8#0020# => '0' & O"056",
8#0021# => '0' & O"220",
8#0022# => '1' & O"752",
8#0023# => '1' & O"752",
8#0024# => '1' & O"752",
8#0025# => '0' & O"153",
8#0026# => '1' & O"151",
8#0027# => '0' & O"250",
8#0030# => '1' & O"250",
8#0031# => '0' & O"377",
8#0032# => '1' & O"752",
8#0033# => '1' & O"752",
8#0034# => '1' & O"752",
8#0035# => '0' & O"060",
8#0036# => '0' & O"314",
8#0037# => '0' & O"252",
8#0040# => '0' & O"650",
8#0041# => '0' & O"103",
8#0042# => '0' & O"723",
8#0043# => '0' & O"314",
8#0044# => '0' & O"060",
8#0045# => '0' & O"000",
8#0046# => '0' & O"203",
8#0047# => '0' & O"504",
8#0050# => '0' & O"104",
8#0051# => '0' & O"273",
8#0052# => '1' & O"104",
8#0053# => '0' & O"237",
8#0054# => '1' & O"204",
8#0055# => '1' & O"413",
8#0056# => '0' & O"056",
8#0057# => '0' & O"220",
8#0060# => '1' & O"450",
8#0061# => '1' & O"557",
8#0062# => '1' & O"752",
8#0063# => '1' & O"752",
8#0064# => '1' & O"752",
8#0065# => '0' & O"113",
8#0066# => '1' & O"147",
8#0067# => '1' & O"650",
8#0070# => '0' & O"561",
8#0071# => '1' & O"567",
8#0072# => '1' & O"713",
8#0073# => '1' & O"316",
8#0074# => '0' & O"304",
8#0075# => '0' & O"733",
8#0076# => '0' & O"450",
8#0077# => '0' & O"064",
8#0100# => '1' & O"316",
8#0101# => '1' & O"565",
8#0102# => '0' & O"456",
8#0103# => '1' & O"372",
8#0104# => '0' & O"426",
8#0105# => '1' & O"552",
8#0106# => '1' & O"603",
8#0107# => '0' & O"672",
8#0110# => '1' & O"633",
8#0111# => '1' & O"466",
8#0112# => '1' & O"514",
8#0113# => '1' & O"633",
8#0114# => '0' & O"034",
8#0115# => '0' & O"752",
8#0116# => '0' & O"002",
8#0117# => '0' & O"463",
8#0120# => '1' & O"304",
8#0121# => '1' & O"326",
8#0122# => '1' & O"646",
8#0123# => '0' & O"424",
8#0124# => '1' & O"037",
8#0125# => '0' & O"575",
8#0126# => '1' & O"567",
8#0127# => '0' & O"322",
8#0130# => '0' & O"562",
8#0131# => '0' & O"332",
8#0132# => '1' & O"612",
8#0133# => '0' & O"567",
8#0134# => '0' & O"316",
8#0135# => '0' & O"064",
8#0136# => '0' & O"616",
8#0137# => '1' & O"414",
8#0140# => '0' & O"452",
8#0141# => '0' & O"612",
8#0142# => '0' & O"672",
8#0143# => '0' & O"643",
8#0144# => '0' & O"252",
8#0145# => '0' & O"572",
8#0146# => '0' & O"537",
8#0147# => '0' & O"514",
8#0150# => '1' & O"652",
8#0151# => '0' & O"424",
8#0152# => '0' & O"413",
8#0153# => '1' & O"452",
8#0154# => '0' & O"052",
8#0155# => '1' & O"735",
8#0156# => '0' & O"412",
8#0157# => '1' & O"316",
8#0160# => '1' & O"454",
8#0161# => '1' & O"047",
8#0162# => '1' & O"662",
8#0163# => '0' & O"753",
8#0164# => '1' & O"321",
8#0165# => '0' & O"220",
8#0166# => '0' & O"424",
8#0167# => '1' & O"733",
8#0170# => '1' & O"662",
8#0171# => '0' & O"372",
8#0172# => '0' & O"616",
8#0173# => '0' & O"672",
8#0174# => '0' & O"777",
8#0175# => '0' & O"332",
8#0176# => '0' & O"252",
8#0177# => '1' & O"514",
8#0200# => '0' & O"426",
8#0201# => '0' & O"552",
8#0202# => '1' & O"176",
8#0203# => '0' & O"473",
8#0204# => '1' & O"166",
8#0205# => '1' & O"003",
8#0206# => '0' & O"312",
8#0207# => '1' & O"735",
8#0210# => '1' & O"326",
8#0211# => '0' & O"636",
8#0212# => '1' & O"454",
8#0213# => '1' & O"117",
8#0214# => '0' & O"216",
8#0215# => '0' & O"756",
8#0216# => '0' & O"114",
8#0217# => '0' & O"422",
8#0220# => '0' & O"074",
8#0221# => '0' & O"642",
8#0222# => '1' & O"077",
8#0223# => '1' & O"656",
8#0224# => '0' & O"354",
8#0225# => '1' & O"747",
8#0226# => '0' & O"312",
8#0227# => '0' & O"604",
8#0230# => '0' & O"753",
8#0231# => '0' & O"376",
8#0232# => '0' & O"650",
8#0233# => '0' & O"056",
8#0234# => '1' & O"772",
8#0235# => '1' & O"772",
8#0236# => '0' & O"772",
8#0237# => '0' & O"772",
8#0240# => '0' & O"112",
8#0241# => '1' & O"217",
8#0242# => '1' & O"656",
8#0243# => '1' & O"646",
8#0244# => '0' & O"646",
8#0245# => '1' & O"237",
8#0246# => '1' & O"656",
8#0247# => '1' & O"046",
8#0250# => '0' & O"112",
8#0251# => '1' & O"373",
8#0252# => '1' & O"216",
8#0253# => '1' & O"752",
8#0254# => '0' & O"016",
8#0255# => '1' & O"373",
8#0256# => '1' & O"243",
8#0257# => '1' & O"366",
8#0260# => '0' & O"324",
8#0261# => '1' & O"323",
8#0262# => '1' & O"576",
8#0263# => '0' & O"376",
8#0264# => '0' & O"724",
8#0265# => '1' & O"337",
8#0266# => '0' & O"450",
8#0267# => '0' & O"704",
8#0270# => '0' & O"316",
8#0271# => '0' & O"556",
8#0272# => '0' & O"276",
8#0273# => '0' & O"776",
8#0274# => '1' & O"056",
8#0275# => '0' & O"060",
8#0276# => '0' & O"220",
8#0277# => '0' & O"561",
8#0300# => '0' & O"504",
8#0301# => '1' & O"567",
8#0302# => '1' & O"316",
8#0303# => '0' & O"636",
8#0304# => '1' & O"044",
8#0305# => '1' & O"477",
8#0306# => '0' & O"772",
8#0307# => '1' & O"004",
8#0310# => '0' & O"524",
8#0311# => '1' & O"467",
8#0312# => '0' & O"752",
8#0313# => '1' & O"433",
8#0314# => '0' & O"050",
8#0315# => '0' & O"024",
8#0316# => '1' & O"437",
8#0317# => '0' & O"044",
8#0320# => '0' & O"034",
8#0321# => '1' & O"454",
8#0322# => '1' & O"503",
8#0323# => '1' & O"050",
8#0324# => '1' & O"024",
8#0325# => '1' & O"463",
8#0326# => '0' & O"416",
8#0327# => '0' & O"544",
8#0330# => '0' & O"320",
8#0331# => '0' & O"450",
8#0332# => '1' & O"656",
8#0333# => '0' & O"565",
8#0334# => '0' & O"704",
8#0335# => '1' & O"735",
8#0336# => '1' & O"275",
8#0337# => '1' & O"053",
8#0340# => '1' & O"326",
8#0341# => '0' & O"034",
8#0342# => '0' & O"254",
8#0343# => '0' & O"427",
8#0344# => '1' & O"414",
8#0345# => '1' & O"356",
8#0346# => '1' & O"366",
8#0347# => '1' & O"742",
8#0350# => '1' & O"742",
8#0351# => '0' & O"214",
8#0352# => '0' & O"074",
8#0353# => '1' & O"542",
8#0354# => '1' & O"677",
8#0355# => '0' & O"002",
8#0356# => '1' & O"653",
8#0357# => '1' & O"742",
8#0360# => '1' & O"456",
8#0361# => '0' & O"060",
8#0362# => '0' & O"404",
8#0363# => '1' & O"324",
8#0364# => '0' & O"163",
8#0365# => '0' & O"677",
8#0366# => '0' & O"376",
8#0367# => '1' & O"244",
8#0370# => '1' & O"417",
8#0371# => '0' & O"624",
8#0372# => '1' & O"763",
8#0373# => '0' & O"034",
8#0374# => '1' & O"222",
8#0375# => '0' & O"751",
8#0376# => '1' & O"250",
8#0377# => '1' & O"557",
8#0400# => '1' & O"717",
8#0401# => '1' & O"456",
8#0402# => '0' & O"241",
8#0403# => '0' & O"650",
8#0404# => '0' & O"241",
8#0405# => '0' & O"650",
8#0406# => '1' & O"124",
8#0407# => '0' & O"047",
8#0410# => '1' & O"656",
8#0411# => '0' & O"524",
8#0412# => '0' & O"113",
8#0413# => '0' & O"336",
8#0414# => '1' & O"231",
8#0415# => '0' & O"450",
8#0416# => '1' & O"225",
8#0417# => '1' & O"141",
8#0420# => '0' & O"225",
8#0421# => '0' & O"650",
8#0422# => '1' & O"231",
8#0423# => '1' & O"224",
8#0424# => '1' & O"553",
8#0425# => '1' & O"356",
8#0426# => '1' & O"742",
8#0427# => '0' & O"446",
8#0430# => '1' & O"646",
8#0431# => '0' & O"552",
8#0432# => '1' & O"222",
8#0433# => '0' & O"672",
8#0434# => '0' & O"147",
8#0435# => '1' & O"322",
8#0436# => '0' & O"752",
8#0437# => '0' & O"167",
8#0440# => '1' & O"316",
8#0441# => '1' & O"216",
8#0442# => '0' & O"450",
8#0443# => '1' & O"056",
8#0444# => '0' & O"407",
8#0445# => '1' & O"056",
8#0446# => '0' & O"414",
8#0447# => '1' & O"573",
8#0450# => '0' & O"450",
8#0451# => '1' & O"656",
8#0452# => '0' & O"642",
8#0453# => '0' & O"267",
8#0454# => '0' & O"256",
8#0455# => '0' & O"616",
8#0456# => '0' & O"212",
8#0457# => '1' & O"457",
8#0460# => '0' & O"616",
8#0461# => '0' & O"124",
8#0462# => '0' & O"227",
8#0463# => '1' & O"224",
8#0464# => '0' & O"667",
8#0465# => '0' & O"524",
8#0466# => '0' & O"127",
8#0467# => '0' & O"376",
8#0470# => '1' & O"676",
8#0471# => '0' & O"067",
8#0472# => '1' & O"222",
8#0473# => '1' & O"576",
8#0474# => '0' & O"353",
8#0475# => '0' & O"776",
8#0476# => '1' & O"462",
8#0477# => '0' & O"722",
8#0500# => '1' & O"456",
8#0501# => '0' & O"456",
8#0502# => '1' & O"522",
8#0503# => '0' & O"357",
8#0504# => '0' & O"650",
8#0505# => '1' & O"316",
8#0506# => '1' & O"662",
8#0507# => '1' & O"456",
8#0510# => '0' & O"422",
8#0511# => '0' & O"450",
8#0512# => '1' & O"776",
8#0513# => '1' & O"776",
8#0514# => '0' & O"217",
8#0515# => '0' & O"316",
8#0516# => '0' & O"052",
8#0517# => '1' & O"326",
8#0520# => '1' & O"311",
8#0521# => '0' & O"542",
8#0522# => '0' & O"650",
8#0523# => '1' & O"656",
8#0524# => '0' & O"414",
8#0525# => '1' & O"221",
8#0526# => '0' & O"614",
8#0527# => '1' & O"155",
8#0530# => '1' & O"014",
8#0531# => '1' & O"155",
8#0532# => '0' & O"214",
8#0533# => '1' & O"030",
8#0534# => '1' & O"214",
8#0535# => '1' & O"155",
8#0536# => '1' & O"071",
8#0537# => '1' & O"155",
8#0540# => '1' & O"461",
8#0541# => '0' & O"416",
8#0542# => '1' & O"155",
8#0543# => '0' & O"216",
8#0544# => '1' & O"455",
8#0545# => '1' & O"461",
8#0546# => '1' & O"256",
8#0547# => '1' & O"231",
8#0550# => '1' & O"124",
8#0551# => '0' & O"663",
8#0552# => '0' & O"376",
8#0553# => '1' & O"141",
8#0554# => '0' & O"144",
8#0555# => '0' & O"316",
8#0556# => '0' & O"542",
8#0557# => '0' & O"752",
8#0560# => '0' & O"124",
8#0561# => '1' & O"227",
8#0562# => '1' & O"231",
8#0563# => '1' & O"461",
8#0564# => '1' & O"256",
8#0565# => '1' & O"225",
8#0566# => '1' & O"461",
8#0567# => '1' & O"256",
8#0570# => '1' & O"256",
8#0571# => '1' & O"125",
8#0572# => '1' & O"256",
8#0573# => '1' & O"655",
8#0574# => '1' & O"461",
8#0575# => '1' & O"214",
8#0576# => '1' & O"161",
8#0577# => '1' & O"071",
8#0600# => '1' & O"014",
8#0601# => '1' & O"165",
8#0602# => '0' & O"214",
8#0603# => '1' & O"030",
8#0604# => '0' & O"614",
8#0605# => '1' & O"161",
8#0606# => '0' & O"414",
8#0607# => '1' & O"161",
8#0610# => '1' & O"161",
8#0611# => '1' & O"456",
8#0612# => '1' & O"116",
8#0613# => '1' & O"514",
8#0614# => '0' & O"530",
8#0615# => '1' & O"757",
8#0616# => '0' & O"614",
8#0617# => '1' & O"030",
8#0620# => '0' & O"630",
8#0621# => '0' & O"530",
8#0622# => '0' & O"230",
8#0623# => '0' & O"430",
8#0624# => '1' & O"130",
8#0625# => '0' & O"124",
8#0626# => '1' & O"553",
8#0627# => '0' & O"060",
8#0630# => '1' & O"356",
8#0631# => '1' & O"742",
8#0632# => '0' & O"020",
8#0633# => '0' & O"420",
8#0634# => '0' & O"416",
8#0635# => '1' & O"226",
8#0636# => '1' & O"056",
8#0637# => '1' & O"207",
8#0640# => '0' & O"776",
8#0641# => '1' & O"416",
8#0642# => '1' & O"203",
8#0643# => '1' & O"616",
8#0644# => '0' & O"420",
8#0645# => '0' & O"420",
8#0646# => '0' & O"512",
8#0647# => '0' & O"420",
8#0650# => '0' & O"742",
8#0651# => '1' & O"516",
8#0652# => '1' & O"243",
8#0653# => '1' & O"716",
8#0654# => '0' & O"416",
8#0655# => '0' & O"034",
8#0656# => '1' & O"122",
8#0657# => '0' & O"054",
8#0660# => '1' & O"247",
8#0661# => '0' & O"267",
8#0662# => '0' & O"742",
8#0663# => '1' & O"426",
8#0664# => '1' & O"313",
8#0665# => '1' & O"626",
8#0666# => '0' & O"426",
8#0667# => '0' & O"034",
8#0670# => '0' & O"054",
8#0671# => '1' & O"317",
8#0672# => '0' & O"267",
8#0673# => '0' & O"034",
8#0674# => '1' & O"626",
8#0675# => '1' & O"557",
8#0676# => '0' & O"020",
8#0677# => '0' & O"572",
8#0700# => '0' & O"572",
8#0701# => '1' & O"352",
8#0702# => '1' & O"536",
8#0703# => '1' & O"176",
8#0704# => '1' & O"433",
8#0705# => '0' & O"420",
8#0706# => '1' & O"006",
8#0707# => '1' & O"453",
8#0710# => '0' & O"376",
8#0711# => '1' & O"456",
8#0712# => '1' & O"416",
8#0713# => '0' & O"420",
8#0714# => '0' & O"316",
8#0715# => '1' & O"314",
8#0716# => '0' & O"730",
8#0717# => '1' & O"030",
8#0720# => '0' & O"530",
8#0721# => '0' & O"330",
8#0722# => '1' & O"130",
8#0723# => '1' & O"030",
8#0724# => '0' & O"130",
8#0725# => '0' & O"630",
8#0726# => '0' & O"330",
8#0727# => '0' & O"530",
8#0730# => '1' & O"414",
8#0731# => '0' & O"060",
8#0732# => '0' & O"020",
8#0733# => '1' & O"612",
8#0734# => '1' & O"573",
8#0735# => '0' & O"542",
8#0736# => '0' & O"776",
8#0737# => '0' & O"054",
8#0740# => '1' & O"357",
8#0741# => '1' & O"652",
8#0742# => '1' & O"352",
8#0743# => '0' & O"142",
8#0744# => '1' & O"633",
8#0745# => '1' & O"316",
8#0746# => '1' & O"116",
8#0747# => '1' & O"052",
8#0750# => '0' & O"312",
8#0751# => '1' & O"414",
8#0752# => '1' & O"273",
8#0753# => '0' & O"420",
8#0754# => '1' & O"222",
8#0755# => '1' & O"222",
8#0756# => '0' & O"576",
8#0757# => '1' & O"663",
8#0760# => '0' & O"722",
8#0761# => '1' & O"422",
8#0762# => '1' & O"062",
8#0763# => '0' & O"216",
8#0764# => '1' & O"576",
8#0765# => '1' & O"673",
8#0766# => '1' & O"662",
8#0767# => '0' & O"650",
8#0770# => '0' & O"036",
8#0771# => '0' & O"007",
8#0772# => '0' & O"416",
8#0773# => '1' & O"662",
8#0774# => '0' & O"450",
8#0775# => '1' & O"222",
8#0776# => '0' & O"576",
8#0777# => '1' & O"076",
8#1000# => '0' & O"020",
8#1001# => '1' & O"476",
8#1002# => '1' & O"776",
8#1003# => '1' & O"126",
8#1004# => '0' & O"422",
8#1005# => '0' & O"113",
8#1006# => '0' & O"650",
8#1007# => '1' & O"231",
8#1010# => '0' & O"616",
8#1011# => '1' & O"024",
8#1012# => '0' & O"413",
8#1013# => '1' & O"356",
8#1014# => '1' & O"506",
8#1015# => '0' & O"003",
8#1016# => '1' & O"316",
8#1017# => '0' & O"576",
8#1020# => '0' & O"003",
8#1021# => '0' & O"776",
8#1022# => '0' & O"456",
8#1023# => '1' & O"131",
8#1024# => '1' & O"542",
8#1025# => '0' & O"107",
8#1026# => '1' & O"462",
8#1027# => '1' & O"636",
8#1030# => '0' & O"007",
8#1031# => '0' & O"714",
8#1032# => '0' & O"665",
8#1033# => '1' & O"014",
8#1034# => '1' & O"165",
8#1035# => '1' & O"114",
8#1036# => '1' & O"161",
8#1037# => '1' & O"771",
8#1040# => '1' & O"214",
8#1041# => '1' & O"161",
8#1042# => '0' & O"765",
8#1043# => '1' & O"314",
8#1044# => '1' & O"161",
8#1045# => '1' & O"575",
8#1046# => '1' & O"161",
8#1047# => '1' & O"345",
8#1050# => '1' & O"161",
8#1051# => '1' & O"731",
8#1052# => '1' & O"656",
8#1053# => '0' & O"516",
8#1054# => '0' & O"032",
8#1055# => '0' & O"277",
8#1056# => '0' & O"516",
8#1057# => '1' & O"456",
8#1060# => '0' & O"034",
8#1061# => '0' & O"416",
8#1062# => '0' & O"154",
8#1063# => '0' & O"303",
8#1064# => '1' & O"656",
8#1065# => '0' & O"676",
8#1066# => '0' & O"343",
8#1067# => '0' & O"346",
8#1070# => '0' & O"752",
8#1071# => '1' & O"314",
8#1072# => '1' & O"425",
8#1073# => '1' & O"124",
8#1074# => '0' & O"033",
8#1075# => '0' & O"524",
8#1076# => '1' & O"123",
8#1077# => '1' & O"731",
8#1100# => '1' & O"235",
8#1101# => '1' & O"123",
8#1102# => '1' & O"731",
8#1103# => '1' & O"661",
8#1104# => '1' & O"345",
8#1105# => '1' & O"314",
8#1106# => '1' & O"155",
8#1107# => '1' & O"575",
8#1110# => '1' & O"214",
8#1111# => '1' & O"155",
8#1112# => '0' & O"765",
8#1113# => '1' & O"114",
8#1114# => '1' & O"155",
8#1115# => '1' & O"771",
8#1116# => '1' & O"014",
8#1117# => '1' & O"155",
8#1120# => '1' & O"155",
8#1121# => '1' & O"155",
8#1122# => '0' & O"614",
8#1123# => '1' & O"362",
8#1124# => '1' & O"514",
8#1125# => '1' & O"056",
8#1126# => '1' & O"656",
8#1127# => '0' & O"630",
8#1130# => '1' & O"073",
8#1131# => '0' & O"224",
8#1132# => '0' & O"573",
8#1133# => '1' & O"752",
8#1134# => '1' & O"172",
8#1135# => '1' & O"413",
8#1136# => '1' & O"426",
8#1137# => '0' & O"547",
8#1140# => '1' & O"626",
8#1141# => '0' & O"416",
8#1142# => '0' & O"552",
8#1143# => '0' & O"563",
8#1144# => '1' & O"316",
8#1145# => '0' & O"322",
8#1146# => '1' & O"652",
8#1147# => '0' & O"676",
8#1150# => '0' & O"663",
8#1151# => '1' & O"456",
8#1152# => '1' & O"416",
8#1153# => '0' & O"356",
8#1154# => '1' & O"316",
8#1155# => '1' & O"056",
8#1156# => '0' & O"316",
8#1157# => '0' & O"546",
8#1160# => '0' & O"224",
8#1161# => '0' & O"733",
8#1162# => '0' & O"430",
8#1163# => '0' & O"746",
8#1164# => '0' & O"747",
8#1165# => '0' & O"630",
8#1166# => '0' & O"154",
8#1167# => '0' & O"727",
8#1170# => '1' & O"116",
8#1171# => '1' & O"116",
8#1172# => '0' & O"224",
8#1173# => '1' & O"123",
8#1174# => '0' & O"060",
8#1175# => '0' & O"714",
8#1176# => '0' & O"330",
8#1177# => '0' & O"330",
8#1200# => '0' & O"030",
8#1201# => '1' & O"030",
8#1202# => '0' & O"530",
8#1203# => '0' & O"030",
8#1204# => '1' & O"130",
8#1205# => '1' & O"653",
8#1206# => '1' & O"131",
8#1207# => '1' & O"742",
8#1210# => '0' & O"456",
8#1211# => '0' & O"576",
8#1212# => '1' & O"033",
8#1213# => '1' & O"322",
8#1214# => '1' & O"656",
8#1215# => '0' & O"426",
8#1216# => '1' & O"656",
8#1217# => '1' & O"576",
8#1220# => '1' & O"043",
8#1221# => '1' & O"456",
8#1222# => '1' & O"742",
8#1223# => '1' & O"461",
8#1224# => '0' & O"220",
8#1225# => '1' & O"322",
8#1226# => '1' & O"576",
8#1227# => '1' & O"127",
8#1230# => '1' & O"376",
8#1231# => '1' & O"616",
8#1232# => '0' & O"060",
8#1233# => '0' & O"220",
8#1234# => '1' & O"316",
8#1235# => '1' & O"056",
8#1236# => '1' & O"203",
8#1237# => '1' & O"616",
8#1240# => '0' & O"576",
8#1241# => '1' & O"177",
8#1242# => '1' & O"656",
8#1243# => '0' & O"426",
8#1244# => '1' & O"656",
8#1245# => '0' & O"667",
8#1246# => '0' & O"314",
8#1247# => '0' & O"712",
8#1250# => '0' & O"536",
8#1251# => '1' & O"257",
8#1252# => '0' & O"276",
8#1253# => '1' & O"446",
8#1254# => '1' & O"356",
8#1255# => '1' & O"454",
8#1256# => '1' & O"427",
8#1257# => '0' & O"146",
8#1260# => '1' & O"333",
8#1261# => '0' & O"124",
8#1262# => '0' & O"003",
8#1263# => '0' & O"222",
8#1264# => '1' & O"546",
8#1265# => '0' & O"772",
8#1266# => '1' & O"062",
8#1267# => '1' & O"646",
8#1270# => '0' & O"220",
8#1271# => '1' & O"044",
8#1272# => '0' & O"630",
8#1273# => '1' & O"130",
8#1274# => '0' & O"330",
8#1275# => '0' & O"130",
8#1276# => '0' & O"430",
8#1277# => '0' & O"730",
8#1300# => '0' & O"130",
8#1301# => '1' & O"633",
8#1302# => '1' & O"746",
8#1303# => '0' & O"623",
8#1304# => '1' & O"616",
8#1305# => '0' & O"542",
8#1306# => '1' & O"423",
8#1307# => '1' & O"316",
8#1310# => '0' & O"074",
8#1311# => '1' & O"554",
8#1312# => '1' & O"427",
8#1313# => '0' & O"752",
8#1314# => '1' & O"376",
8#1315# => '1' & O"414",
8#1316# => '0' & O"056",
8#1317# => '1' & O"142",
8#1320# => '1' & O"533",
8#1321# => '0' & O"416",
8#1322# => '0' & O"552",
8#1323# => '1' & O"156",
8#1324# => '1' & O"477",
8#1325# => '0' & O"316",
8#1326# => '0' & O"452",
8#1327# => '1' & O"616",
8#1330# => '1' & O"176",
8#1331# => '1' & O"437",
8#1332# => '1' & O"646",
8#1333# => '0' & O"616",
8#1334# => '0' & O"056",
8#1335# => '1' & O"414",
8#1336# => '0' & O"753",
8#1337# => '1' & O"114",
8#1340# => '0' & O"330",
8#1341# => '0' & O"130",
8#1342# => '0' & O"030",
8#1343# => '0' & O"130",
8#1344# => '0' & O"730",
8#1345# => '1' & O"130",
8#1346# => '1' & O"030",
8#1347# => '0' & O"030",
8#1350# => '0' & O"530",
8#1351# => '0' & O"530",
8#1352# => '0' & O"330",
8#1353# => '1' & O"567",
8#1354# => '1' & O"656",
8#1355# => '0' & O"456",
8#1356# => '0' & O"606",
8#1357# => '1' & O"272",
8#1360# => '0' & O"573",
8#1361# => '0' & O"772",
8#1362# => '1' & O"316",
8#1363# => '0' & O"752",
8#1364# => '1' & O"713",
8#1365# => '0' & O"637",
8#1366# => '0' & O"316",
8#1367# => '1' & O"414",
8#1370# => '0' & O"230",
8#1371# => '0' & O"330",
8#1372# => '0' & O"030",
8#1373# => '0' & O"230",
8#1374# => '0' & O"530",
8#1375# => '1' & O"007",
8#1376# => '0' & O"514",
8#1377# => '0' & O"773"
);
constant ROM_45 : RomType := (
8#0000# => '0' & O"255",
8#0001# => '1' & O"420",
8#0002# => '0' & O"451",
8#0003# => '1' & O"456",
8#0004# => '1' & O"746",
8#0005# => '0' & O"472",
8#0006# => '1' & O"572",
8#0007# => '1' & O"616",
8#0010# => '1' & O"352",
8#0011# => '1' & O"611",
8#0012# => '1' & O"611",
8#0013# => '1' & O"352",
8#0014# => '1' & O"445",
8#0015# => '0' & O"623",
8#0016# => '1' & O"024",
8#0017# => '0' & O"507",
8#0020# => '1' & O"035",
8#0021# => '1' & O"656",
8#0022# => '0' & O"616",
8#0023# => '0' & O"013",
8#0024# => '1' & O"220",
8#0025# => '1' & O"035",
8#0026# => '1' & O"656",
8#0027# => '1' & O"020",
8#0030# => '0' & O"220",
8#0031# => '0' & O"324",
8#0032# => '0' & O"143",
8#0033# => '0' & O"450",
8#0034# => '0' & O"316",
8#0035# => '1' & O"160",
8#0036# => '0' & O"000",
8#0037# => '1' & O"370",
8#0040# => '1' & O"656",
8#0041# => '1' & O"171",
8#0042# => '1' & O"431",
8#0043# => '1' & O"211",
8#0044# => '1' & O"431",
8#0045# => '1' & O"376",
8#0046# => '1' & O"370",
8#0047# => '0' & O"676",
8#0050# => '0' & O"267",
8#0051# => '1' & O"576",
8#0052# => '0' & O"265",
8#0053# => '0' & O"123",
8#0054# => '0' & O"220",
8#0055# => '1' & O"656",
8#0056# => '1' & O"024",
8#0057# => '1' & O"713",
8#0060# => '0' & O"376",
8#0061# => '1' & O"711",
8#0062# => '0' & O"124",
8#0063# => '0' & O"263",
8#0064# => '1' & O"224",
8#0065# => '0' & O"647",
8#0066# => '0' & O"353",
8#0067# => '0' & O"220",
8#0070# => '0' & O"616",
8#0071# => '0' & O"220",
8#0072# => '1' & O"656",
8#0073# => '0' & O"616",
8#0074# => '0' & O"772",
8#0075# => '0' & O"433",
8#0076# => '0' & O"652",
8#0077# => '0' & O"433",
8#0100# => '0' & O"316",
8#0101# => '0' & O"014",
8#0102# => '0' & O"530",
8#0103# => '1' & O"414",
8#0104# => '0' & O"712",
8#0105# => '1' & O"657",
8#0106# => '1' & O"224",
8#0107# => '0' & O"727",
8#0110# => '1' & O"656",
8#0111# => '0' & O"343",
8#0112# => '0' & O"312",
8#0113# => '0' & O"014",
8#0114# => '0' & O"530",
8#0115# => '1' & O"512",
8#0116# => '1' & O"172",
8#0117# => '1' & O"463",
8#0120# => '1' & O"777",
8#0121# => '0' & O"451",
8#0122# => '1' & O"615",
8#0123# => '0' & O"056",
8#0124# => '1' & O"462",
8#0125# => '1' & O"456",
8#0126# => '0' & O"416",
8#0127# => '1' & O"625",
8#0130# => '0' & O"704",
8#0131# => '1' & O"445",
8#0132# => '0' & O"316",
8#0133# => '0' & O"330",
8#0134# => '0' & O"630",
8#0135# => '1' & O"414",
8#0136# => '1' & O"171",
8#0137# => '1' & O"031",
8#0140# => '0' & O"767",
8#0141# => '0' & O"752",
8#0142# => '0' & O"742",
8#0143# => '1' & O"017",
8#0144# => '0' & O"316",
8#0145# => '0' & O"214",
8#0146# => '0' & O"430",
8#0147# => '1' & O"656",
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8#2142# => '1' & O"420",
8#2143# => '1' & O"420",
8#2144# => '1' & O"420",
8#2145# => '1' & O"204",
8#2146# => '0' & O"304",
8#2147# => '0' & O"617",
8#2150# => '0' & O"604",
8#2151# => '0' & O"404",
8#2152# => '0' & O"727",
8#2153# => '0' & O"644",
8#2154# => '0' & O"404",
8#2155# => '0' & O"727",
8#2156# => '0' & O"604",
8#2157# => '0' & O"723",
8#2160# => '1' & O"756",
8#2161# => '1' & O"420",
8#2162# => '1' & O"420",
8#2163# => '0' & O"644",
8#2164# => '0' & O"444",
8#2165# => '0' & O"224",
8#2166# => '0' & O"777",
8#2167# => '1' & O"244",
8#2170# => '0' & O"620",
8#2171# => '1' & O"244",
8#2172# => '1' & O"220",
8#2173# => '0' & O"000",
8#2174# => '1' & O"057",
8#2175# => '0' & O"000",
8#2176# => '0' & O"620",
8#2177# => '0' & O"605",
8#2200# => '0' & O"650",
8#2201# => '0' & O"747",
8#2202# => '1' & O"244",
8#2203# => '1' & O"027",
8#2204# => '1' & O"204",
8#2205# => '1' & O"144",
8#2206# => '0' & O"620",
8#2207# => '0' & O"650",
8#2210# => '0' & O"450",
8#2211# => '1' & O"656",
8#2212# => '0' & O"060",
8#2213# => '1' & O"124",
8#2214# => '1' & O"103",
8#2215# => '0' & O"601",
8#2216# => '1' & O"656",
8#2217# => '0' & O"747",
8#2220# => '0' & O"625",
8#2221# => '1' & O"360",
8#2222# => '1' & O"073",
8#2223# => '0' & O"571",
8#2224# => '0' & O"650",
8#2225# => '0' & O"304",
8#2226# => '1' & O"244",
8#2227# => '0' & O"467",
8#2230# => '0' & O"601",
8#2231# => '1' & O"450",
8#2232# => '0' & O"450",
8#2233# => '1' & O"231",
8#2234# => '0' & O"423",
8#2235# => '0' & O"000",
8#2236# => '0' & O"000",
8#2237# => '1' & O"220",
8#2240# => '0' & O"320",
8#2241# => '0' & O"344",
8#2242# => '1' & O"227",
8#2243# => '0' & O"344",
8#2244# => '0' & O"220",
8#2245# => '0' & O"220",
8#2246# => '0' & O"376",
8#2247# => '0' & O"020",
8#2250# => '0' & O"571",
8#2251# => '0' & O"304",
8#2252# => '0' & O"444",
8#2253# => '0' & O"676",
8#2254# => '1' & O"273",
8#2255# => '0' & O"404",
8#2256# => '1' & O"450",
8#2257# => '1' & O"041",
8#2260# => '1' & O"146",
8#2261# => '0' & O"327",
8#2262# => '0' & O"322",
8#2263# => '0' & O"742",
8#2264# => '0' & O"325",
8#2265# => '0' & O"144",
8#2266# => '1' & O"035",
8#2267# => '0' & O"616",
8#2270# => '1' & O"221",
8#2271# => '1' & O"360",
8#2272# => '1' & O"455",
8#2273# => '0' & O"621",
8#2274# => '1' & O"221",
8#2275# => '1' & O"370",
8#2276# => '1' & O"235",
8#2277# => '1' & O"572",
8#2300# => '1' & O"572",
8#2301# => '1' & O"572",
8#2302# => '1' & O"427",
8#2303# => '0' & O"572",
8#2304# => '1' & O"705",
8#2305# => '0' & O"616",
8#2306# => '0' & O"405",
8#2307# => '1' & O"707",
8#2310# => '0' & O"605",
8#2311# => '0' & O"204",
8#2312# => '0' & O"027",
8#2313# => '0' & O"316",
8#2314# => '1' & O"160",
8#2315# => '0' & O"000",
8#2316# => '1' & O"370",
8#2317# => '0' & O"060",
8#2320# => '1' & O"124",
8#2321# => '1' & O"517",
8#2322# => '1' & O"177",
8#2323# => '0' & O"601",
8#2324# => '0' & O"127",
8#2325# => '0' & O"000",
8#2326# => '0' & O"000",
8#2327# => '0' & O"000",
8#2330# => '0' & O"000",
8#2331# => '0' & O"000",
8#2332# => '0' & O"000",
8#2333# => '0' & O"000",
8#2334# => '0' & O"000",
8#2335# => '0' & O"000",
8#2336# => '0' & O"000",
8#2337# => '0' & O"000",
8#2340# => '0' & O"000",
8#2341# => '0' & O"000",
8#2342# => '0' & O"000",
8#2343# => '0' & O"000",
8#2344# => '0' & O"000",
8#2345# => '0' & O"000",
8#2346# => '0' & O"000",
8#2347# => '0' & O"000",
8#2350# => '0' & O"000",
8#2351# => '0' & O"000",
8#2352# => '0' & O"000",
8#2353# => '0' & O"000",
8#2354# => '0' & O"000",
8#2355# => '0' & O"000",
8#2356# => '0' & O"000",
8#2357# => '0' & O"000",
8#2360# => '0' & O"000",
8#2361# => '0' & O"020",
8#2362# => '0' & O"000",
8#2363# => '0' & O"000",
8#2364# => '0' & O"000",
8#2365# => '1' & O"220",
8#2366# => '0' & O"000",
8#2367# => '0' & O"000",
8#2370# => '0' & O"000",
8#2371# => '0' & O"000",
8#2372# => '0' & O"000",
8#2373# => '0' & O"000",
8#2374# => '0' & O"000",
8#2375# => '0' & O"000",
8#2376# => '0' & O"060",
8#2377# => '1' & O"420",
8#2400# => '1' & O"420",
8#2401# => '0' & O"742",
8#2402# => '0' & O"742",
8#2403# => '0' & O"742",
8#2404# => '0' & O"742",
8#2405# => '0' & O"742",
8#2406# => '0' & O"516",
8#2407# => '1' & O"160",
8#2410# => '0' & O"000",
8#2411# => '1' & O"370",
8#2412# => '0' & O"424",
8#2413# => '1' & O"777",
8#2414# => '1' & O"656",
8#2415# => '1' & O"024",
8#2416# => '1' & O"237",
8#2417# => '1' & O"233",
8#2420# => '0' & O"620",
8#2421# => '0' & O"000",
8#2422# => '0' & O"000",
8#2423# => '0' & O"000",
8#2424# => '0' & O"000",
8#2425# => '1' & O"623",
8#2426# => '0' & O"404",
8#2427# => '1' & O"244",
8#2430# => '1' & O"221",
8#2431# => '0' & O"011",
8#2432# => '1' & O"355",
8#2433# => '0' & O"265",
8#2434# => '0' & O"616",
8#2435# => '0' & O"015",
8#2436# => '0' & O"217",
8#2437# => '0' & O"000",
8#2440# => '0' & O"000",
8#2441# => '0' & O"000",
8#2442# => '0' & O"413",
8#2443# => '1' & O"355",
8#2444# => '0' & O"311",
8#2445# => '0' & O"021",
8#2446# => '1' & O"355",
8#2447# => '0' & O"316",
8#2450# => '0' & O"742",
8#2451# => '0' & O"616",
8#2452# => '0' & O"005",
8#2453# => '1' & O"355",
8#2454# => '0' & O"103",
8#2455# => '0' & O"316",
8#2456# => '1' & O"160",
8#2457# => '0' & O"000",
8#2460# => '1' & O"370",
8#2461# => '0' & O"060",
8#2462# => '1' & O"450",
8#2463# => '0' & O"450",
8#2464# => '0' & O"616",
8#2465# => '0' & O"060",
8#2466# => '1' & O"044",
8#2467# => '1' & O"144",
8#2470# => '1' & O"225",
8#2471# => '0' & O"000",
8#2472# => '0' & O"000",
8#2473# => '0' & O"000",
8#2474# => '0' & O"000",
8#2475# => '0' & O"000",
8#2476# => '0' & O"000",
8#2477# => '0' & O"000",
8#2500# => '0' & O"000",
8#2501# => '0' & O"620",
8#2502# => '1' & O"244",
8#2503# => '0' & O"444",
8#2504# => '0' & O"015",
8#2505# => '0' & O"616",
8#2506# => '1' & O"221",
8#2507# => '0' & O"005",
8#2510# => '0' & O"176",
8#2511# => '0' & O"003",
8#2512# => '1' & O"225",
8#2513# => '0' & O"011",
8#2514# => '1' & O"656",
8#2515# => '1' & O"231",
8#2516# => '0' & O"450",
8#2517# => '0' & O"005",
8#2520# => '1' & O"656",
8#2521# => '0' & O"316",
8#2522# => '0' & O"742",
8#2523# => '1' & O"231",
8#2524# => '0' & O"650",
8#2525# => '1' & O"225",
8#2526# => '0' & O"405",
8#2527# => '0' & O"450",
8#2530# => '0' & O"015",
8#2531# => '0' & O"616",
8#2532# => '0' & O"005",
8#2533# => '1' & O"205",
8#2534# => '0' & O"444",
8#2535# => '0' & O"724",
8#2536# => '0' & O"603",
8#2537# => '0' & O"450",
8#2540# => '0' & O"616",
8#2541# => '0' & O"021",
8#2542# => '0' & O"450",
8#2543# => '0' & O"616",
8#2544# => '0' & O"015",
8#2545# => '0' & O"773",
8#2546# => '0' & O"000",
8#2547# => '0' & O"000",
8#2550# => '0' & O"000",
8#2551# => '0' & O"000",
8#2552# => '0' & O"000",
8#2553# => '0' & O"000",
8#2554# => '0' & O"000",
8#2555# => '0' & O"000",
8#2556# => '0' & O"000",
8#2557# => '0' & O"000",
8#2560# => '0' & O"000",
8#2561# => '0' & O"000",
8#2562# => '0' & O"000",
8#2563# => '0' & O"000",
8#2564# => '0' & O"000",
8#2565# => '1' & O"355",
8#2566# => '1' & O"656",
8#2567# => '0' & O"620",
8#2570# => '0' & O"000",
8#2571# => '0' & O"000",
8#2572# => '0' & O"000",
8#2573# => '1' & O"561",
8#2574# => '1' & O"124",
8#2575# => '0' & O"727",
8#2576# => '0' & O"620",
8#2577# => '0' & O"000",
8#2600# => '0' & O"000",
8#2601# => '0' & O"000",
8#2602# => '0' & O"000",
8#2603# => '0' & O"000",
8#2604# => '0' & O"000",
8#2605# => '0' & O"000",
8#2606# => '0' & O"000",
8#2607# => '0' & O"000",
8#2610# => '0' & O"000",
8#2611# => '0' & O"000",
8#2612# => '0' & O"000",
8#2613# => '0' & O"000",
8#2614# => '0' & O"000",
8#2615# => '0' & O"000",
8#2616# => '0' & O"000",
8#2617# => '0' & O"000",
8#2620# => '0' & O"000",
8#2621# => '0' & O"000",
8#2622# => '0' & O"000",
8#2623# => '0' & O"000",
8#2624# => '0' & O"000",
8#2625# => '0' & O"000",
8#2626# => '0' & O"000",
8#2627# => '0' & O"000",
8#2630# => '0' & O"000",
8#2631# => '0' & O"000",
8#2632# => '0' & O"000",
8#2633# => '0' & O"000",
8#2634# => '0' & O"000",
8#2635# => '0' & O"000",
8#2636# => '0' & O"000",
8#2637# => '0' & O"000",
8#2640# => '0' & O"563",
8#2641# => '0' & O"344",
8#2642# => '1' & O"227",
8#2643# => '0' & O"344",
8#2644# => '0' & O"220",
8#2645# => '0' & O"220",
8#2646# => '0' & O"376",
8#2647# => '0' & O"020",
8#2650# => '0' & O"000",
8#2651# => '0' & O"000",
8#2652# => '0' & O"000",
8#2653# => '0' & O"000",
8#2654# => '0' & O"000",
8#2655# => '0' & O"000",
8#2656# => '0' & O"000",
8#2657# => '0' & O"000",
8#2660# => '0' & O"322",
8#2661# => '0' & O"562",
8#2662# => '0' & O"332",
8#2663# => '0' & O"420",
8#2664# => '1' & O"303",
8#2665# => '0' & O"322",
8#2666# => '0' & O"562",
8#2667# => '0' & O"332",
8#2670# => '1' & O"612",
8#2671# => '1' & O"357",
8#2672# => '0' & O"316",
8#2673# => '0' & O"616",
8#2674# => '1' & O"414",
8#2675# => '0' & O"452",
8#2676# => '0' & O"612",
8#2677# => '0' & O"672",
8#2700# => '1' & O"423",
8#2701# => '0' & O"252",
8#2702# => '0' & O"572",
8#2703# => '1' & O"327",
8#2704# => '1' & O"666",
8#2705# => '1' & O"370",
8#2706# => '1' & O"656",
8#2707# => '1' & O"360",
8#2710# => '0' & O"060",
8#2711# => '0' & O"000",
8#2712# => '0' & O"000",
8#2713# => '0' & O"000",
8#2714# => '0' & O"000",
8#2715# => '0' & O"000",
8#2716# => '0' & O"000",
8#2717# => '0' & O"000",
8#2720# => '0' & O"000",
8#2721# => '0' & O"000",
8#2722# => '0' & O"000",
8#2723# => '0' & O"000",
8#2724# => '0' & O"000",
8#2725# => '0' & O"000",
8#2726# => '0' & O"000",
8#2727# => '0' & O"000",
8#2730# => '0' & O"000",
8#2731# => '0' & O"000",
8#2732# => '0' & O"000",
8#2733# => '0' & O"000",
8#2734# => '0' & O"424",
8#2735# => '1' & O"607",
8#2736# => '0' & O"624",
8#2737# => '1' & O"233",
8#2740# => '1' & O"237",
8#2741# => '0' & O"624",
8#2742# => '1' & O"227",
8#2743# => '1' & O"223",
8#2744# => '0' & O"316",
8#2745# => '0' & O"576",
8#2746# => '0' & O"214",
8#2747# => '0' & O"230",
8#2750# => '0' & O"250",
8#2751# => '0' & O"316",
8#2752# => '1' & O"356",
8#2753# => '1' & O"414",
8#2754# => '0' & O"542",
8#2755# => '1' & O"160",
8#2756# => '1' & O"656",
8#2757# => '0' & O"450",
8#2760# => '1' & O"360",
8#2761# => '1' & O"656",
8#2762# => '0' & O"742",
8#2763# => '0' & O"742",
8#2764# => '1' & O"663",
8#2765# => '0' & O"773",
8#2766# => '0' & O"316",
8#2767# => '0' & O"630",
8#2770# => '1' & O"653",
8#2771# => '0' & O"000",
8#2772# => '0' & O"000",
8#2773# => '0' & O"000",
8#2774# => '0' & O"000",
8#2775# => '0' & O"000",
8#2776# => '0' & O"000",
8#2777# => '0' & O"060",
8#3000# => '1' & O"363",
8#3001# => '0' & O"037",
8#3002# => '0' & O"064",
8#3003# => '0' & O"777",
8#3004# => '0' & O"772",
8#3005# => '0' & O"771",
8#3006# => '1' & O"721",
8#3007# => '0' & O"316",
8#3010# => '0' & O"064",
8#3011# => '0' & O"504",
8#3012# => '0' & O"616",
8#3013# => '1' & O"250",
8#3014# => '1' & O"656",
8#3015# => '0' & O"147",
8#3016# => '1' & O"326",
8#3017# => '1' & O"752",
8#3020# => '0' & O"073",
8#3021# => '1' & O"514",
8#3022# => '1' & O"472",
8#3023# => '0' & O"472",
8#3024# => '0' & O"034",
8#3025# => '0' & O"254",
8#3026# => '0' & O"267",
8#3027# => '1' & O"356",
8#3030# => '1' & O"552",
8#3031# => '0' & O"056",
8#3032# => '1' & O"004",
8#3033# => '0' & O"114",
8#3034# => '0' & O"472",
8#3035# => '0' & O"606",
8#3036# => '0' & O"426",
8#3037# => '1' & O"142",
8#3040# => '0' & O"107",
8#3041# => '1' & O"044",
8#3042# => '1' & O"614",
8#3043# => '0' & O"612",
8#3044# => '0' & O"172",
8#3045# => '0' & O"073",
8#3046# => '0' & O"034",
8#3047# => '0' & O"254",
8#3050# => '0' & O"253",
8#3051# => '0' & O"137",
8#3052# => '1' & O"552",
8#3053# => '0' & O"233",
8#3054# => '0' & O"113",
8#3055# => '1' & O"572",
8#3056# => '0' & O"123",
8#3057# => '0' & O"442",
8#3060# => '0' & O"034",
8#3061# => '1' & O"362",
8#3062# => '0' & O"612",
8#3063# => '1' & O"626",
8#3064# => '0' & O"353",
8#3065# => '1' & O"326",
8#3066# => '1' & O"776",
8#3067# => '1' & O"752",
8#3070# => '1' & O"024",
8#3071# => '0' & O"357",
8#3072# => '0' & O"074",
8#3073# => '1' & O"326",
8#3074# => '0' & O"066",
8#3075# => '1' & O"572",
8#3076# => '1' & O"172",
8#3077# => '0' & O"407",
8#3100# => '0' & O"137",
8#3101# => '1' & O"772",
8#3102# => '1' & O"456",
8#3103# => '1' & O"742",
8#3104# => '1' & O"742",
8#3105# => '0' & O"426",
8#3106# => '1' & O"572",
8#3107# => '0' & O"427",
8#3110# => '1' & O"362",
8#3111# => '1' & O"562",
8#3112# => '1' & O"326",
8#3113# => '1' & O"456",
8#3114# => '1' & O"024",
8#3115# => '0' & O"527",
8#3116# => '1' & O"652",
8#3117# => '0' & O"052",
8#3120# => '0' & O"672",
8#3121# => '0' & O"523",
8#3122# => '0' & O"252",
8#3123# => '0' & O"572",
8#3124# => '1' & O"652",
8#3125# => '0' & O"524",
8#3126# => '1' & O"773",
8#3127# => '1' & O"003",
8#3130# => '0' & O"000",
8#3131# => '0' & O"000",
8#3132# => '0' & O"000",
8#3133# => '0' & O"000",
8#3134# => '0' & O"000",
8#3135# => '0' & O"000",
8#3136# => '0' & O"000",
8#3137# => '0' & O"000",
8#3140# => '0' & O"000",
8#3141# => '0' & O"000",
8#3142# => '0' & O"000",
8#3143# => '1' & O"323",
8#3144# => '1' & O"223",
8#3145# => '0' & O"616",
8#3146# => '0' & O"316",
8#3147# => '0' & O"542",
8#3150# => '1' & O"160",
8#3151# => '1' & O"656",
8#3152# => '0' & O"616",
8#3153# => '1' & O"757",
8#3154# => '0' & O"000",
8#3155# => '0' & O"000",
8#3156# => '0' & O"000",
8#3157# => '0' & O"000",
8#3160# => '0' & O"000",
8#3161# => '0' & O"000",
8#3162# => '1' & O"007",
8#3163# => '0' & O"731",
8#3164# => '0' & O"064",
8#3165# => '0' & O"220",
8#3166# => '0' & O"724",
8#3167# => '0' & O"747",
8#3170# => '0' & O"450",
8#3171# => '0' & O"316",
8#3172# => '0' & O"060",
8#3173# => '0' & O"000",
8#3174# => '1' & O"244",
8#3175# => '0' & O"621",
8#3176# => '0' & O"620",
8#3177# => '0' & O"145",
8#3200# => '0' & O"620",
8#3201# => '0' & O"416",
8#3202# => '0' & O"416",
8#3203# => '0' & O"731",
8#3204# => '1' & O"572",
8#3205# => '1' & O"037",
8#3206# => '0' & O"763",
8#3207# => '1' & O"572",
8#3210# => '1' & O"067",
8#3211# => '0' & O"230",
8#3212# => '0' & O"530",
8#3213# => '0' & O"430",
8#3214# => '0' & O"773",
8#3215# => '1' & O"572",
8#3216# => '1' & O"147",
8#3217# => '0' & O"430",
8#3220# => '0' & O"530",
8#3221# => '0' & O"330",
8#3222# => '0' & O"530",
8#3223# => '1' & O"130",
8#3224# => '0' & O"230",
8#3225# => '0' & O"330",
8#3226# => '0' & O"730",
8#3227# => '0' & O"552",
8#3230# => '0' & O"771",
8#3231# => '0' & O"330",
8#3232# => '0' & O"730",
8#3233# => '1' & O"030",
8#3234# => '0' & O"530",
8#3235# => '0' & O"430",
8#3236# => '0' & O"130",
8#3237# => '0' & O"130",
8#3240# => '0' & O"730",
8#3241# => '1' & O"030",
8#3242# => '0' & O"430",
8#3243# => '0' & O"773",
8#3244# => '0' & O"014",
8#3245# => '0' & O"416",
8#3246# => '0' & O"074",
8#3247# => '1' & O"454",
8#3250# => '1' & O"227",
8#3251# => '1' & O"376",
8#3252# => '1' & O"656",
8#3253# => '1' & O"160",
8#3254# => '0' & O"244",
8#3255# => '1' & O"370",
8#3256# => '1' & O"656",
8#3257# => '1' & O"344",
8#3260# => '0' & O"056",
8#3261# => '0' & O"124",
8#3262# => '1' & O"757",
8#3263# => '0' & O"627",
8#3264# => '0' & O"456",
8#3265# => '1' & O"656",
8#3266# => '0' & O"316",
8#3267# => '1' & O"160",
8#3270# => '0' & O"216",
8#3271# => '1' & O"656",
8#3272# => '1' & O"360",
8#3273# => '0' & O"623",
8#3274# => '0' & O"176",
8#3275# => '0' & O"037",
8#3276# => '0' & O"172",
8#3277# => '0' & O"037",
8#3300# => '0' & O"152",
8#3301# => '1' & O"423",
8#3302# => '0' & O"034",
8#3303# => '1' & O"457",
8#3304# => '0' & O"034",
8#3305# => '0' & O"354",
8#3306# => '1' & O"443",
8#3307# => '0' & O"023",
8#3310# => '0' & O"552",
8#3311# => '1' & O"401",
8#3312# => '0' & O"420",
8#3313# => '0' & O"162",
8#3314# => '0' & O"037",
8#3315# => '1' & O"652",
8#3316# => '1' & O"314",
8#3317# => '0' & O"652",
8#3320# => '1' & O"527",
8#3321# => '0' & O"552",
8#3322# => '0' & O"152",
8#3323# => '0' & O"023",
8#3324# => '0' & O"416",
8#3325# => '1' & O"656",
8#3326# => '1' & O"356",
8#3327# => '1' & O"742",
8#3330# => '0' & O"256",
8#3331# => '1' & O"453",
8#3332# => '1' & O"656",
8#3333# => '1' & O"116",
8#3334# => '0' & O"776",
8#3335# => '1' & O"414",
8#3336# => '0' & O"466",
8#3337# => '1' & O"716",
8#3340# => '1' & O"577",
8#3341# => '1' & O"516",
8#3342# => '0' & O"416",
8#3343# => '1' & O"716",
8#3344# => '1' & O"617",
8#3345# => '1' & O"776",
8#3346# => '1' & O"456",
8#3347# => '1' & O"731",
8#3350# => '1' & O"314",
8#3351# => '1' & O"731",
8#3352# => '0' & O"216",
8#3353# => '0' & O"062",
8#3354# => '1' & O"216",
8#3355# => '1' & O"456",
8#3356# => '1' & O"626",
8#3357# => '1' & O"567",
8#3360# => '1' & O"656",
8#3361# => '1' & O"052",
8#3362# => '0' & O"752",
8#3363# => '1' & O"451",
8#3364# => '1' & O"044",
8#3365# => '0' & O"420",
8#3366# => '0' & O"002",
8#3367# => '1' & O"753",
8#3370# => '1' & O"222",
8#3371# => '1' & O"752",
8#3372# => '0' & O"060",
8#3373# => '1' & O"224",
8#3374# => '1' & O"773",
8#3375# => '1' & O"020",
8#3376# => '0' & O"620",
8#3377# => '0' & O"000",
8#3400# => '0' & O"027",
8#3401# => '1' & O"213",
8#3402# => '0' & O"027",
8#3403# => '0' & O"027",
8#3404# => '0' & O"027",
8#3405# => '0' & O"067",
8#3406# => '0' & O"027",
8#3407# => '0' & O"107",
8#3410# => '0' & O"027",
8#3411# => '1' & O"237",
8#3412# => '0' & O"027",
8#3413# => '0' & O"027",
8#3414# => '0' & O"027",
8#3415# => '1' & O"223",
8#3416# => '0' & O"027",
8#3417# => '1' & O"130",
8#3420# => '1' & O"117",
8#3421# => '1' & O"227",
8#3422# => '0' & O"303",
8#3423# => '0' & O"177",
8#3424# => '0' & O"430",
8#3425# => '0' & O"767",
8#3426# => '0' & O"027",
8#3427# => '1' & O"030",
8#3430# => '1' & O"117",
8#3431# => '1' & O"243",
8#3432# => '0' & O"753",
8#3433# => '0' & O"763",
8#3434# => '0' & O"130",
8#3435# => '0' & O"767",
8#3436# => '0' & O"027",
8#3437# => '0' & O"530",
8#3440# => '1' & O"117",
8#3441# => '0' & O"237",
8#3442# => '1' & O"103",
8#3443# => '1' & O"507",
8#3444# => '0' & O"030",
8#3445# => '0' & O"767",
8#3446# => '0' & O"027",
8#3447# => '0' & O"047",
8#3450# => '0' & O"027",
8#3451# => '0' & O"267",
8#3452# => '0' & O"027",
8#3453# => '0' & O"027",
8#3454# => '0' & O"027",
8#3455# => '0' & O"277",
8#3456# => '0' & O"027",
8#3457# => '0' & O"337",
8#3460# => '0' & O"630",
8#3461# => '1' & O"117",
8#3462# => '0' & O"077",
8#3463# => '0' & O"137",
8#3464# => '0' & O"730",
8#3465# => '0' & O"767",
8#3466# => '0' & O"027",
8#3467# => '1' & O"767",
8#3470# => '1' & O"356",
8#3471# => '0' & O"065",
8#3472# => '0' & O"723",
8#3473# => '1' & O"073",
8#3474# => '0' & O"713",
8#3475# => '0' & O"620",
8#3476# => '1' & O"124",
8#3477# => '0' & O"367",
8#3500# => '0' & O"064",
8#3501# => '0' & O"176",
8#3502# => '1' & O"773",
8#3503# => '0' & O"552",
8#3504# => '0' & O"552",
8#3505# => '0' & O"672",
8#3506# => '1' & O"773",
8#3507# => '0' & O"447",
8#3510# => '1' & O"106",
8#3511# => '0' & O"752",
8#3512# => '0' & O"443",
8#3513# => '1' & O"656",
8#3514# => '1' & O"250",
8#3515# => '0' & O"130",
8#3516# => '0' & O"330",
8#3517# => '0' & O"106",
8#3520# => '1' & O"773",
8#3521# => '0' & O"630",
8#3522# => '1' & O"214",
8#3523# => '0' & O"102",
8#3524# => '1' & O"773",
8#3525# => '1' & O"014",
8#3526# => '1' & O"322",
8#3527# => '0' & O"714",
8#3530# => '0' & O"630",
8#3531# => '0' & O"714",
8#3532# => '0' & O"102",
8#3533# => '1' & O"773",
8#3534# => '0' & O"250",
8#3535# => '0' & O"514",
8#3536# => '1' & O"322",
8#3537# => '1' & O"322",
8#3540# => '1' & O"322",
8#3541# => '1' & O"322",
8#3542# => '1' & O"456",
8#3543# => '1' & O"562",
8#3544# => '1' & O"352",
8#3545# => '1' & O"014",
8#3546# => '1' & O"542",
8#3547# => '1' & O"314",
8#3550# => '1' & O"742",
8#3551# => '1' & O"742",
8#3552# => '1' & O"576",
8#3553# => '1' & O"456",
8#3554# => '0' & O"044",
8#3555# => '0' & O"245",
8#3556# => '0' & O"245",
8#3557# => '0' & O"024",
8#3560# => '1' & O"063",
8#3561# => '1' & O"233",
8#3562# => '1' & O"204",
8#3563# => '1' & O"223",
8#3564# => '0' & O"012",
8#3565# => '1' & O"043",
8#3566# => '0' & O"052",
8#3567# => '0' & O"037",
8#3570# => '0' & O"000",
8#3571# => '0' & O"000",
8#3572# => '0' & O"330",
8#3573# => '1' & O"117",
8#3574# => '0' & O"230",
8#3575# => '1' & O"117",
8#3576# => '0' & O"620",
8#3577# => '0' & O"024",
8#3600# => '0' & O"007",
8#3601# => '1' & O"024",
8#3602# => '0' & O"663",
8#3603# => '1' & O"050",
8#3604# => '1' & O"044",
8#3605# => '1' & O"414",
8#3606# => '0' & O"316",
8#3607# => '0' & O"320",
8#3610# => '1' & O"452",
8#3611# => '1' & O"552",
8#3612# => '1' & O"452",
8#3613# => '1' & O"227",
8#3614# => '1' & O"004",
8#3615# => '0' & O"207",
8#3616# => '1' & O"224",
8#3617# => '0' & O"713",
8#3620# => '1' & O"244",
8#3621# => '1' & O"160",
8#3622# => '1' & O"133",
8#3623# => '1' & O"160",
8#3624# => '1' & O"224",
8#3625# => '1' & O"157",
8#3626# => '1' & O"656",
8#3627# => '0' & O"616",
8#3630# => '1' & O"106",
8#3631# => '1' & O"360",
8#3632# => '1' & O"233",
8#3633# => '1' & O"370",
8#3634# => '1' & O"414",
8#3635# => '0' & O"642",
8#3636# => '1' & O"203",
8#3637# => '0' & O"316",
8#3640# => '1' & O"656",
8#3641# => '0' & O"426",
8#3642# => '0' & O"265",
8#3643# => '0' & O"275",
8#3644# => '0' & O"275",
8#3645# => '0' & O"275",
8#3646# => '0' & O"275",
8#3647# => '0' & O"335",
8#3650# => '1' & O"250",
8#3651# => '1' & O"050",
8#3652# => '0' & O"050",
8#3653# => '1' & O"224",
8#3654# => '0' & O"777",
8#3655# => '0' & O"114",
8#3656# => '1' & O"762",
8#3657# => '0' & O"777",
8#3660# => '0' & O"614",
8#3661# => '1' & O"742",
8#3662# => '1' & O"213",
8#3663# => '0' & O"714",
8#3664# => '1' & O"742",
8#3665# => '0' & O"102",
8#3666# => '1' & O"343",
8#3667# => '1' & O"217",
8#3670# => '1' & O"362",
8#3671# => '1' & O"114",
8#3672# => '1' & O"742",
8#3673# => '0' & O"067",
8#3674# => '1' & O"214",
8#3675# => '1' & O"742",
8#3676# => '0' & O"102",
8#3677# => '1' & O"407",
8#3700# => '1' & O"227",
8#3701# => '0' & O"322",
8#3702# => '1' & O"362",
8#3703# => '1' & O"314",
8#3704# => '1' & O"742",
8#3705# => '1' & O"453",
8#3706# => '1' & O"356",
8#3707# => '1' & O"414",
8#3710# => '1' & O"742",
8#3711# => '1' & O"237",
8#3712# => '0' & O"106",
8#3713# => '1' & O"467",
8#3714# => '0' & O"047",
8#3715# => '1' & O"356",
8#3716# => '1' & O"314",
8#3717# => '1' & O"742",
8#3720# => '0' & O"147",
8#3721# => '1' & O"250",
8#3722# => '0' & O"322",
8#3723# => '0' & O"214",
8#3724# => '0' & O"012",
8#3725# => '1' & O"543",
8#3726# => '0' & O"430",
8#3727# => '1' & O"547",
8#3730# => '0' & O"630",
8#3731# => '0' & O"250",
8#3732# => '0' & O"316",
8#3733# => '1' & O"414",
8#3734# => '0' & O"056",
8#3735# => '1' & O"160",
8#3736# => '1' & O"056",
8#3737# => '1' & O"370",
8#3740# => '0' & O"142",
8#3741# => '1' & O"623",
8#3742# => '1' & O"655",
8#3743# => '1' & O"360",
8#3744# => '1' & O"056",
8#3745# => '0' & O"742",
8#3746# => '1' & O"567",
8#3747# => '1' & O"306",
8#3750# => '1' & O"656",
8#3751# => '1' & O"655",
8#3752# => '0' & O"773",
8#3753# => '0' & O"662",
8#3754# => '1' & O"767",
8#3755# => '1' & O"656",
8#3756# => '0' & O"416",
8#3757# => '1' & O"014",
8#3760# => '0' & O"422",
8#3761# => '0' & O"614",
8#3762# => '0' & O"422",
8#3763# => '0' & O"422",
8#3764# => '0' & O"422",
8#3765# => '1' & O"414",
8#3766# => '1' & O"752",
8#3767# => '1' & O"142",
8#3770# => '1' & O"763",
8#3771# => '1' & O"552",
8#3772# => '0' & O"406",
8#3773# => '1' & O"737",
8#3774# => '1' & O"656",
8#3775# => '0' & O"060",
8#3776# => '0' & O"316",
8#3777# => '0' & O"455"
); -- End 45 ROM
constant ROM_55 : RomType := (
8#0000# => '0' & O"575",
8#0001# => '1' & O"364",
8#0002# => '0' & O"477",
8#0003# => '0' & O"564",
8#0004# => '0' & O"757",
8#0005# => '0' & O"504",
8#0006# => '1' & O"414",
8#0007# => '0' & O"420",
8#0010# => '0' & O"742",
8#0011# => '1' & O"145",
8#0012# => '1' & O"414",
8#0013# => '0' & O"530",
8#0014# => '0' & O"030",
8#0015# => '1' & O"654",
8#0016# => '0' & O"057",
8#0017# => '1' & O"656",
8#0020# => '0' & O"416",
8#0021# => '1' & O"414",
8#0022# => '0' & O"230",
8#0023# => '0' & O"330",
8#0024# => '1' & O"314",
8#0025# => '0' & O"217",
8#0026# => '0' & O"561",
8#0027# => '0' & O"624",
8#0030# => '0' & O"027",
8#0031# => '0' & O"504",
8#0032# => '1' & O"204",
8#0033# => '1' & O"104",
8#0034# => '1' & O"414",
8#0035# => '0' & O"564",
8#0036# => '0' & O"013",
8#0037# => '0' & O"561",
8#0040# => '0' & O"624",
8#0041# => '0' & O"033",
8#0042# => '0' & O"153",
8#0043# => '0' & O"752",
8#0044# => '1' & O"160",
8#0045# => '1' & O"656",
8#0046# => '1' & O"563",
8#0047# => '0' & O"450",
8#0050# => '0' & O"504",
8#0051# => '1' & O"541",
8#0052# => '0' & O"773",
8#0053# => '0' & O"144",
8#0054# => '0' & O"244",
8#0055# => '1' & O"414",
8#0056# => '0' & O"056",
8#0057# => '1' & O"420",
8#0060# => '0' & O"456",
8#0061# => '1' & O"343",
8#0062# => '1' & O"364",
8#0063# => '0' & O"107",
8#0064# => '0' & O"621",
8#0065# => '0' & O"561",
8#0066# => '0' & O"424",
8#0067# => '1' & O"023",
8#0070# => '0' & O"616",
8#0071# => '0' & O"005",
8#0072# => '1' & O"037",
8#0073# => '0' & O"614",
8#0074# => '0' & O"250",
8#0075# => '0' & O"060",
8#0076# => '0' & O"564",
8#0077# => '0' & O"603",
8#0100# => '0' & O"355",
8#0101# => '1' & O"130",
8#0102# => '1' & O"363",
8#0103# => '0' & O"564",
8#0104# => '0' & O"643",
8#0105# => '0' & O"000",
8#0106# => '0' & O"621",
8#0107# => '0' & O"724",
8#0110# => '0' & O"453",
8#0111# => '0' & O"450",
8#0112# => '1' & O"121",
8#0113# => '1' & O"037",
8#0114# => '0' & O"616",
8#0115# => '0' & O"316",
8#0116# => '1' & O"414",
8#0117# => '0' & O"542",
8#0120# => '0' & O"752",
8#0121# => '1' & O"443",
8#0122# => '0' & O"000",
8#0123# => '0' & O"323",
8#0124# => '1' & O"141",
8#0125# => '1' & O"037",
8#0126# => '0' & O"000",
8#0127# => '0' & O"242",
8#0130# => '0' & O"242",
8#0131# => '1' & O"243",
8#0132# => '0' & O"250",
8#0133# => '1' & O"007",
8#0134# => '0' & O"420",
8#0135# => '1' & O"364",
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8#2127# => '1' & O"151",
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8#2131# => '1' & O"341",
8#2132# => '0' & O"404",
8#2133# => '1' & O"507",
8#2134# => '0' & O"420",
8#2135# => '0' & O"564",
8#2136# => '0' & O"757",
8#2137# => '0' & O"176",
8#2140# => '1' & O"373",
8#2141# => '0' & O"646",
8#2142# => '1' & O"373",
8#2143# => '0' & O"060",
8#2144# => '1' & O"220",
8#2145# => '1' & O"356",
8#2146# => '1' & O"742",
8#2147# => '1' & O"131",
8#2150# => '1' & O"771",
8#2151# => '0' & O"475",
8#2152# => '0' & O"565",
8#2153# => '0' & O"305",
8#2154# => '1' & O"331",
8#2155# => '0' & O"616",
8#2156# => '0' & O"471",
8#2157# => '1' & O"345",
8#2160# => '0' & O"415",
8#2161# => '1' & O"325",
8#2162# => '1' & O"131",
8#2163# => '0' & O"475",
8#2164# => '0' & O"033",
8#2165# => '1' & O"341",
8#2166# => '0' & O"475",
8#2167# => '1' & O"141",
8#2170# => '0' & O"456",
8#2171# => '0' & O"475",
8#2172# => '0' & O"216",
8#2173# => '1' & O"656",
8#2174# => '0' & O"415",
8#2175# => '0' & O"424",
8#2176# => '1' & O"007",
8#2177# => '0' & O"336",
8#2200# => '1' & O"171",
8#2201# => '0' & O"405",
8#2202# => '0' & O"724",
8#2203# => '1' & O"037",
8#2204# => '0' & O"744",
8#2205# => '0' & O"733",
8#2206# => '1' & O"341",
8#2207# => '0' & O"220",
8#2210# => '0' & O"305",
8#2211# => '1' & O"341",
8#2212# => '0' & O"616",
8#2213# => '1' & O"331",
8#2214# => '0' & O"471",
8#2215# => '1' & O"345",
8#2216# => '0' & O"415",
8#2217# => '1' & O"321",
8#2220# => '1' & O"131",
8#2221# => '0' & O"724",
8#2222# => '0' & O"007",
8#2223# => '0' & O"475",
8#2224# => '1' & O"656",
8#2225# => '0' & O"733",
8#2226# => '0' & O"376",
8#2227# => '1' & O"220",
8#2230# => '0' & O"564",
8#2231# => '0' & O"643",
8#2232# => '0' & O"564",
8#2233# => '1' & O"073",
8#2234# => '0' & O"764",
8#2235# => '1' & O"707",
8#2236# => '0' & O"164",
8#2237# => '0' & O"257",
8#2240# => '0' & O"650",
8#2241# => '1' & O"656",
8#2242# => '0' & O"450",
8#2243# => '0' & O"616",
8#2244# => '1' & O"414",
8#2245# => '0' & O"060",
8#2246# => '0' & O"424",
8#2247# => '1' & O"617",
8#2250# => '0' & O"733",
8#2251# => '0' & O"344",
8#2252# => '1' & O"344",
8#2253# => '1' & O"004",
8#2254# => '0' & O"060",
8#2255# => '0' & O"621",
8#2256# => '0' & O"441",
8#2257# => '0' & O"450",
8#2260# => '1' & O"056",
8#2261# => '0' & O"064",
8#2262# => '0' & O"364",
8#2263# => '0' & O"347",
8#2264# => '0' & O"542",
8#2265# => '0' & O"542",
8#2266# => '0' & O"542",
8#2267# => '0' & O"542",
8#2270# => '0' & O"542",
8#2271# => '0' & O"516",
8#2272# => '1' & O"160",
8#2273# => '0' & O"000",
8#2274# => '1' & O"370",
8#2275# => '0' & O"060",
8#2276# => '0' & O"620",
8#2277# => '0' & O"724",
8#2300# => '0' & O"347",
8#2301# => '0' & O"744",
8#2302# => '1' & O"151",
8#2303# => '1' & O"215",
8#2304# => '1' & O"321",
8#2305# => '1' & O"656",
8#2306# => '0' & O"650",
8#2307# => '1' & O"477",
8#2310# => '0' & O"565",
8#2311# => '0' & O"744",
8#2312# => '1' & O"204",
8#2313# => '1' & O"201",
8#2314# => '1' & O"325",
8#2315# => '1' & O"656",
8#2316# => '0' & O"616",
8#2317# => '0' & O"471",
8#2320# => '1' & O"370",
8#2321# => '1' & O"656",
8#2322# => '0' & O"624",
8#2323# => '1' & O"527",
8#2324# => '0' & O"376",
8#2325# => '1' & O"135",
8#2326# => '0' & O"405",
8#2327# => '1' & O"360",
8#2330# => '1' & O"224",
8#2331# => '1' & O"377",
8#2332# => '0' & O"724",
8#2333# => '0' & O"517",
8#2334# => '0' & O"424",
8#2335# => '0' & O"537",
8#2336# => '1' & O"151",
8#2337# => '1' & O"215",
8#2340# => '1' & O"335",
8#2341# => '1' & O"244",
8#2342# => '1' & O"467",
8#2343# => '0' & O"605",
8#2344# => '0' & O"724",
8#2345# => '1' & O"747",
8#2346# => '0' & O"744",
8#2347# => '0' & O"123",
8#2350# => '1' & O"245",
8#2351# => '0' & O"621",
8#2352# => '0' & O"561",
8#2353# => '0' & O"565",
8#2354# => '0' & O"704",
8#2355# => '0' & O"305",
8#2356# => '1' & O"345",
8#2357# => '0' & O"624",
8#2360# => '0' & O"627",
8#2361# => '0' & O"575",
8#2362# => '0' & O"475",
8#2363# => '0' & O"565",
8#2364# => '0' & O"305",
8#2365# => '1' & O"331",
8#2366# => '0' & O"475",
8#2367# => '0' & O"305",
8#2370# => '0' & O"727",
8#2371# => '0' & O"650",
8#2372# => '0' & O"415",
8#2373# => '0' & O"450",
8#2374# => '1' & O"141",
8#2375# => '1' & O"037",
8#2376# => '0' & O"676",
8#2377# => '1' & O"373",
8#2400# => '0' & O"556",
8#2401# => '0' & O"354",
8#2402# => '0' & O"023",
8#2403# => '0' & O"043",
8#2404# => '0' & O"724",
8#2405# => '0' & O"037",
8#2406# => '0' & O"034",
8#2407# => '1' & O"122",
8#2410# => '1' & O"352",
8#2411# => '1' & O"056",
8#2412# => '0' & O"553",
8#2413# => '0' & O"322",
8#2414# => '0' & O"562",
8#2415# => '0' & O"332",
8#2416# => '1' & O"612",
8#2417# => '1' & O"513",
8#2420# => '0' & O"316",
8#2421# => '0' & O"616",
8#2422# => '1' & O"414",
8#2423# => '0' & O"452",
8#2424# => '0' & O"612",
8#2425# => '0' & O"672",
8#2426# => '0' & O"153",
8#2427# => '0' & O"252",
8#2430# => '0' & O"572",
8#2431# => '0' & O"057",
8#2432# => '1' & O"652",
8#2433# => '0' & O"616",
8#2434# => '1' & O"443",
8#2435# => '1' & O"414",
8#2436# => '0' & O"056",
8#2437# => '0' & O"144",
8#2440# => '0' & O"244",
8#2441# => '1' & O"564",
8#2442# => '1' & O"233",
8#2443# => '1' & O"256",
8#2444# => '1' & O"443",
8#2445# => '1' & O"025",
8#2446# => '0' & O"224",
8#2447# => '0' & O"757",
8#2450# => '0' & O"172",
8#2451# => '0' & O"757",
8#2452# => '0' & O"730",
8#2453# => '0' & O"547",
8#2454# => '1' & O"471",
8#2455# => '0' & O"625",
8#2456# => '0' & O"744",
8#2457# => '0' & O"224",
8#2460# => '0' & O"447",
8#2461# => '0' & O"704",
8#2462# => '0' & O"447",
8#2463# => '1' & O"025",
8#2464# => '0' & O"224",
8#2465# => '0' & O"367",
8#2466# => '0' & O"172",
8#2467# => '0' & O"367",
8#2470# => '0' & O"630",
8#2471# => '0' & O"547",
8#2472# => '1' & O"004",
8#2473# => '1' & O"264",
8#2474# => '0' & O"220",
8#2475# => '0' & O"250",
8#2476# => '0' & O"625",
8#2477# => '1' & O"015",
8#2500# => '0' & O"561",
8#2501# => '0' & O"650",
8#2502# => '0' & O"475",
8#2503# => '1' & O"013",
8#2504# => '0' & O"000",
8#2505# => '1' & O"025",
8#2506# => '1' & O"317",
8#2507# => '0' & O"602",
8#2510# => '0' & O"653",
8#2511# => '0' & O"444",
8#2512# => '0' & O"561",
8#2513# => '1' & O"250",
8#2514# => '0' & O"465",
8#2515# => '1' & O"164",
8#2516# => '1' & O"247",
8#2517# => '0' & O"252",
8#2520# => '0' & O"314",
8#2521# => '0' & O"173",
8#2522# => '1' & O"025",
8#2523# => '1' & O"053",
8#2524# => '0' & O"000",
8#2525# => '0' & O"622",
8#2526# => '1' & O"056",
8#2527# => '1' & O"733",
8#2530# => '0' & O"430",
8#2531# => '0' & O"250",
8#2532# => '0' & O"364",
8#2533# => '0' & O"347",
8#2534# => '0' & O"420",
8#2535# => '0' & O"114",
8#2536# => '1' & O"124",
8#2537# => '1' & O"653",
8#2540# => '1' & O"224",
8#2541# => '0' & O"527",
8#2542# => '0' & O"422",
8#2543# => '0' & O"014",
8#2544# => '0' & O"437",
8#2545# => '1' & O"124",
8#2546# => '1' & O"423",
8#2547# => '0' & O"704",
8#2550# => '1' & O"144",
8#2551# => '1' & O"244",
8#2552# => '1' & O"656",
8#2553# => '0' & O"646",
8#2554# => '0' & O"103",
8#2555# => '0' & O"616",
8#2556# => '0' & O"672",
8#2557# => '0' & O"707",
8#2560# => '1' & O"420",
8#2561# => '0' & O"052",
8#2562# => '1' & O"452",
8#2563# => '1' & O"514",
8#2564# => '0' & O"002",
8#2565# => '1' & O"377",
8#2566# => '1' & O"552",
8#2567# => '0' & O"034",
8#2570# => '0' & O"254",
8#2571# => '1' & O"277",
8#2572# => '1' & O"457",
8#2573# => '0' & O"250",
8#2574# => '0' & O"625",
8#2575# => '0' & O"561",
8#2576# => '0' & O"656",
8#2577# => '1' & O"043",
8#2600# => '0' & O"650",
8#2601# => '0' & O"165",
8#2602# => '1' & O"020",
8#2603# => '0' & O"764",
8#2604# => '1' & O"673",
8#2605# => '0' & O"214",
8#2606# => '0' & O"250",
8#2607# => '0' & O"060",
8#2610# => '0' & O"764",
8#2611# => '1' & O"413",
8#2612# => '0' & O"224",
8#2613# => '1' & O"073",
8#2614# => '0' & O"672",
8#2615# => '1' & O"127",
8#2616# => '0' & O"250",
8#2617# => '0' & O"625",
8#2620# => '1' & O"015",
8#2621# => '0' & O"561",
8#2622# => '0' & O"650",
8#2623# => '1' & O"135",
8#2624# => '1' & O"013",
8#2625# => '0' & O"530",
8#2626# => '0' & O"547",
8#2627# => '0' & O"376",
8#2630# => '0' & O"144",
8#2631# => '0' & O"244",
8#2632# => '1' & O"414",
8#2633# => '0' & O"056",
8#2634# => '1' & O"772",
8#2635# => '1' & O"772",
8#2636# => '0' & O"772",
8#2637# => '0' & O"772",
8#2640# => '0' & O"112",
8#2641# => '1' & O"217",
8#2642# => '1' & O"656",
8#2643# => '1' & O"646",
8#2644# => '0' & O"646",
8#2645# => '1' & O"237",
8#2646# => '1' & O"656",
8#2647# => '1' & O"046",
8#2650# => '0' & O"112",
8#2651# => '1' & O"373",
8#2652# => '1' & O"216",
8#2653# => '1' & O"752",
8#2654# => '0' & O"016",
8#2655# => '1' & O"373",
8#2656# => '1' & O"243",
8#2657# => '0' & O"142",
8#2660# => '1' & O"457",
8#2661# => '0' & O"406",
8#2662# => '0' & O"733",
8#2663# => '0' & O"224",
8#2664# => '1' & O"337",
8#2665# => '0' & O"672",
8#2666# => '0' & O"543",
8#2667# => '0' & O"250",
8#2670# => '0' & O"625",
8#2671# => '1' & O"015",
8#2672# => '0' & O"561",
8#2673# => '0' & O"650",
8#2674# => '1' & O"141",
8#2675# => '1' & O"013",
8#2676# => '1' & O"420",
8#2677# => '0' & O"034",
8#2700# => '0' & O"142",
8#2701# => '1' & O"447",
8#2702# => '0' & O"406",
8#2703# => '0' & O"723",
8#2704# => '1' & O"056",
8#2705# => '0' & O"146",
8#2706# => '1' & O"443",
8#2707# => '0' & O"316",
8#2710# => '0' & O"220",
8#2711# => '0' & O"002",
8#2712# => '1' & O"557",
8#2713# => '1' & O"712",
8#2714# => '1' & O"656",
8#2715# => '1' & O"573",
8#2716# => '0' & O"304",
8#2717# => '1' & O"304",
8#2720# => '1' & O"044",
8#2721# => '0' & O"060",
8#2722# => '0' & O"250",
8#2723# => '0' & O"302",
8#2724# => '0' & O"250",
8#2725# => '0' & O"107",
8#2726# => '0' & O"124",
8#2727# => '0' & O"217",
8#2730# => '1' & O"420",
8#2731# => '1' & O"414",
8#2732# => '1' & O"533",
8#2733# => '1' & O"752",
8#2734# => '0' & O"034",
8#2735# => '1' & O"447",
8#2736# => '1' & O"452",
8#2737# => '0' & O"052",
8#2740# => '1' & O"124",
8#2741# => '0' & O"107",
8#2742# => '0' & O"672",
8#2743# => '0' & O"553",
8#2744# => '0' & O"252",
8#2745# => '0' & O"672",
8#2746# => '0' & O"553",
8#2747# => '1' & O"471",
8#2750# => '0' & O"635",
8#2751# => '1' & O"013",
8#2752# => '1' & O"056",
8#2753# => '1' & O"104",
8#2754# => '0' & O"724",
8#2755# => '1' & O"703",
8#2756# => '0' & O"744",
8#2757# => '0' & O"450",
8#2760# => '1' & O"462",
8#2761# => '1' & O"376",
8#2762# => '0' & O"316",
8#2763# => '0' & O"556",
8#2764# => '0' & O"276",
8#2765# => '0' & O"776",
8#2766# => '0' & O"756",
8#2767# => '0' & O"142",
8#2770# => '0' & O"003",
8#2771# => '0' & O"422",
8#2772# => '0' & O"074",
8#2773# => '1' & O"737",
8#2774# => '1' & O"471",
8#2775# => '0' & O"625",
8#2776# => '1' & O"056",
8#2777# => '0' & O"353",
8#3000# => '1' & O"717",
8#3001# => '1' & O"456",
8#3002# => '0' & O"241",
8#3003# => '0' & O"650",
8#3004# => '0' & O"241",
8#3005# => '0' & O"650",
8#3006# => '1' & O"124",
8#3007# => '0' & O"047",
8#3010# => '1' & O"656",
8#3011# => '0' & O"524",
8#3012# => '0' & O"113",
8#3013# => '0' & O"336",
8#3014# => '1' & O"231",
8#3015# => '0' & O"450",
8#3016# => '1' & O"225",
8#3017# => '1' & O"141",
8#3020# => '0' & O"225",
8#3021# => '0' & O"650",
8#3022# => '1' & O"231",
8#3023# => '0' & O"424",
8#3024# => '0' & O"723",
8#3025# => '1' & O"356",
8#3026# => '1' & O"742",
8#3027# => '0' & O"446",
8#3030# => '1' & O"646",
8#3031# => '0' & O"552",
8#3032# => '1' & O"222",
8#3033# => '0' & O"672",
8#3034# => '0' & O"147",
8#3035# => '1' & O"322",
8#3036# => '0' & O"752",
8#3037# => '0' & O"167",
8#3040# => '1' & O"316",
8#3041# => '1' & O"216",
8#3042# => '0' & O"450",
8#3043# => '1' & O"056",
8#3044# => '0' & O"407",
8#3045# => '1' & O"056",
8#3046# => '0' & O"414",
8#3047# => '1' & O"573",
8#3050# => '0' & O"450",
8#3051# => '1' & O"656",
8#3052# => '0' & O"642",
8#3053# => '0' & O"267",
8#3054# => '0' & O"256",
8#3055# => '0' & O"616",
8#3056# => '0' & O"212",
8#3057# => '1' & O"457",
8#3060# => '0' & O"616",
8#3061# => '0' & O"124",
8#3062# => '0' & O"227",
8#3063# => '0' & O"424",
8#3064# => '0' & O"733",
8#3065# => '0' & O"524",
8#3066# => '0' & O"127",
8#3067# => '0' & O"376",
8#3070# => '1' & O"676",
8#3071# => '0' & O"067",
8#3072# => '1' & O"222",
8#3073# => '1' & O"576",
8#3074# => '0' & O"353",
8#3075# => '0' & O"776",
8#3076# => '1' & O"462",
8#3077# => '0' & O"722",
8#3100# => '1' & O"456",
8#3101# => '0' & O"456",
8#3102# => '1' & O"522",
8#3103# => '0' & O"357",
8#3104# => '0' & O"650",
8#3105# => '1' & O"316",
8#3106# => '1' & O"662",
8#3107# => '1' & O"456",
8#3110# => '0' & O"422",
8#3111# => '0' & O"450",
8#3112# => '1' & O"776",
8#3113# => '1' & O"776",
8#3114# => '0' & O"217",
8#3115# => '0' & O"316",
8#3116# => '0' & O"052",
8#3117# => '1' & O"326",
8#3120# => '1' & O"311",
8#3121# => '0' & O"542",
8#3122# => '0' & O"650",
8#3123# => '1' & O"656",
8#3124# => '0' & O"414",
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8#3131# => '1' & O"155",
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8#3145# => '1' & O"461",
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8#3151# => '0' & O"663",
8#3152# => '0' & O"376",
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8#3154# => '1' & O"461",
8#3155# => '1' & O"256",
8#3156# => '1' & O"225",
8#3157# => '0' & O"764",
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8#3162# => '1' & O"764",
8#3163# => '0' & O"073",
8#3164# => '0' & O"164",
8#3165# => '1' & O"463",
8#3166# => '1' & O"461",
8#3167# => '1' & O"256",
8#3170# => '1' & O"256",
8#3171# => '1' & O"125",
8#3172# => '1' & O"256",
8#3173# => '1' & O"655",
8#3174# => '1' & O"461",
8#3175# => '1' & O"214",
8#3176# => '1' & O"161",
8#3177# => '1' & O"071",
8#3200# => '1' & O"014",
8#3201# => '1' & O"165",
8#3202# => '0' & O"214",
8#3203# => '1' & O"030",
8#3204# => '0' & O"614",
8#3205# => '1' & O"161",
8#3206# => '0' & O"414",
8#3207# => '1' & O"161",
8#3210# => '1' & O"161",
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8#3212# => '1' & O"116",
8#3213# => '1' & O"514",
8#3214# => '0' & O"530",
8#3215# => '1' & O"757",
8#3216# => '0' & O"614",
8#3217# => '1' & O"030",
8#3220# => '0' & O"630",
8#3221# => '0' & O"530",
8#3222# => '0' & O"230",
8#3223# => '0' & O"430",
8#3224# => '1' & O"130",
8#3225# => '0' & O"124",
8#3226# => '1' & O"553",
8#3227# => '0' & O"060",
8#3230# => '1' & O"356",
8#3231# => '1' & O"742",
8#3232# => '1' & O"220",
8#3233# => '1' & O"620",
8#3234# => '0' & O"416",
8#3235# => '1' & O"226",
8#3236# => '1' & O"056",
8#3237# => '1' & O"207",
8#3240# => '0' & O"776",
8#3241# => '1' & O"416",
8#3242# => '1' & O"203",
8#3243# => '1' & O"616",
8#3244# => '1' & O"620",
8#3245# => '1' & O"620",
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8#3247# => '1' & O"620",
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8#3251# => '1' & O"516",
8#3252# => '1' & O"243",
8#3253# => '1' & O"716",
8#3254# => '0' & O"416",
8#3255# => '0' & O"034",
8#3256# => '1' & O"122",
8#3257# => '0' & O"054",
8#3260# => '1' & O"247",
8#3261# => '0' & O"267",
8#3262# => '0' & O"742",
8#3263# => '1' & O"426",
8#3264# => '1' & O"313",
8#3265# => '1' & O"626",
8#3266# => '0' & O"426",
8#3267# => '0' & O"034",
8#3270# => '0' & O"054",
8#3271# => '1' & O"317",
8#3272# => '0' & O"267",
8#3273# => '0' & O"034",
8#3274# => '1' & O"626",
8#3275# => '1' & O"557",
8#3276# => '0' & O"620",
8#3277# => '0' & O"572",
8#3300# => '0' & O"572",
8#3301# => '1' & O"352",
8#3302# => '1' & O"536",
8#3303# => '1' & O"176",
8#3304# => '1' & O"433",
8#3305# => '1' & O"620",
8#3306# => '1' & O"006",
8#3307# => '1' & O"453",
8#3310# => '0' & O"376",
8#3311# => '1' & O"456",
8#3312# => '1' & O"416",
8#3313# => '1' & O"620",
8#3314# => '0' & O"316",
8#3315# => '1' & O"314",
8#3316# => '0' & O"730",
8#3317# => '1' & O"030",
8#3320# => '0' & O"530",
8#3321# => '0' & O"330",
8#3322# => '1' & O"130",
8#3323# => '1' & O"030",
8#3324# => '0' & O"130",
8#3325# => '0' & O"630",
8#3326# => '0' & O"330",
8#3327# => '0' & O"530",
8#3330# => '1' & O"220",
8#3331# => '0' & O"060",
8#3332# => '0' & O"620",
8#3333# => '1' & O"612",
8#3334# => '1' & O"573",
8#3335# => '0' & O"542",
8#3336# => '0' & O"776",
8#3337# => '0' & O"054",
8#3340# => '1' & O"357",
8#3341# => '1' & O"652",
8#3342# => '1' & O"352",
8#3343# => '0' & O"142",
8#3344# => '1' & O"633",
8#3345# => '1' & O"316",
8#3346# => '1' & O"116",
8#3347# => '1' & O"052",
8#3350# => '0' & O"312",
8#3351# => '1' & O"414",
8#3352# => '1' & O"273",
8#3353# => '1' & O"620",
8#3354# => '1' & O"222",
8#3355# => '1' & O"222",
8#3356# => '0' & O"576",
8#3357# => '1' & O"663",
8#3360# => '0' & O"722",
8#3361# => '1' & O"422",
8#3362# => '1' & O"062",
8#3363# => '0' & O"216",
8#3364# => '1' & O"576",
8#3365# => '1' & O"673",
8#3366# => '1' & O"662",
8#3367# => '0' & O"650",
8#3370# => '0' & O"036",
8#3371# => '0' & O"007",
8#3372# => '0' & O"416",
8#3373# => '1' & O"662",
8#3374# => '0' & O"450",
8#3375# => '1' & O"222",
8#3376# => '0' & O"576",
8#3377# => '1' & O"076",
8#3400# => '0' & O"000",
8#3401# => '1' & O"476",
8#3402# => '1' & O"776",
8#3403# => '1' & O"126",
8#3404# => '0' & O"422",
8#3405# => '0' & O"113",
8#3406# => '0' & O"650",
8#3407# => '1' & O"231",
8#3410# => '0' & O"420",
8#3411# => '1' & O"731",
8#3412# => '0' & O"056",
8#3413# => '1' & O"231",
8#3414# => '0' & O"616",
8#3415# => '0' & O"413",
8#3416# => '0' & O"572",
8#3417# => '1' & O"364",
8#3420# => '0' & O"707",
8#3421# => '0' & O"776",
8#3422# => '0' & O"456",
8#3423# => '1' & O"131",
8#3424# => '1' & O"542",
8#3425# => '0' & O"107",
8#3426# => '1' & O"462",
8#3427# => '1' & O"636",
8#3430# => '0' & O"007",
8#3431# => '0' & O"714",
8#3432# => '0' & O"665",
8#3433# => '1' & O"014",
8#3434# => '1' & O"165",
8#3435# => '1' & O"114",
8#3436# => '1' & O"161",
8#3437# => '1' & O"771",
8#3440# => '1' & O"214",
8#3441# => '1' & O"161",
8#3442# => '0' & O"765",
8#3443# => '1' & O"314",
8#3444# => '1' & O"161",
8#3445# => '1' & O"575",
8#3446# => '1' & O"161",
8#3447# => '1' & O"345",
8#3450# => '1' & O"161",
8#3451# => '1' & O"731",
8#3452# => '1' & O"656",
8#3453# => '0' & O"516",
8#3454# => '0' & O"032",
8#3455# => '0' & O"277",
8#3456# => '0' & O"516",
8#3457# => '1' & O"456",
8#3460# => '0' & O"034",
8#3461# => '0' & O"416",
8#3462# => '0' & O"154",
8#3463# => '0' & O"303",
8#3464# => '1' & O"656",
8#3465# => '0' & O"676",
8#3466# => '0' & O"343",
8#3467# => '0' & O"346",
8#3470# => '0' & O"752",
8#3471# => '1' & O"314",
8#3472# => '1' & O"425",
8#3473# => '1' & O"124",
8#3474# => '0' & O"033",
8#3475# => '0' & O"524",
8#3476# => '1' & O"123",
8#3477# => '1' & O"731",
8#3500# => '1' & O"235",
8#3501# => '1' & O"123",
8#3502# => '1' & O"731",
8#3503# => '1' & O"661",
8#3504# => '1' & O"345",
8#3505# => '1' & O"314",
8#3506# => '1' & O"155",
8#3507# => '1' & O"575",
8#3510# => '1' & O"214",
8#3511# => '1' & O"155",
8#3512# => '0' & O"765",
8#3513# => '1' & O"114",
8#3514# => '1' & O"155",
8#3515# => '1' & O"771",
8#3516# => '1' & O"014",
8#3517# => '1' & O"155",
8#3520# => '1' & O"155",
8#3521# => '1' & O"155",
8#3522# => '0' & O"614",
8#3523# => '1' & O"362",
8#3524# => '1' & O"514",
8#3525# => '1' & O"056",
8#3526# => '1' & O"656",
8#3527# => '0' & O"630",
8#3530# => '1' & O"073",
8#3531# => '0' & O"224",
8#3532# => '0' & O"573",
8#3533# => '1' & O"752",
8#3534# => '1' & O"172",
8#3535# => '1' & O"413",
8#3536# => '1' & O"426",
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8#3540# => '1' & O"626",
8#3541# => '0' & O"416",
8#3542# => '0' & O"552",
8#3543# => '0' & O"563",
8#3544# => '1' & O"316",
8#3545# => '0' & O"322",
8#3546# => '1' & O"652",
8#3547# => '0' & O"676",
8#3550# => '0' & O"663",
8#3551# => '1' & O"456",
8#3552# => '1' & O"416",
8#3553# => '0' & O"356",
8#3554# => '1' & O"316",
8#3555# => '1' & O"056",
8#3556# => '0' & O"316",
8#3557# => '0' & O"546",
8#3560# => '0' & O"224",
8#3561# => '0' & O"733",
8#3562# => '0' & O"430",
8#3563# => '0' & O"746",
8#3564# => '0' & O"747",
8#3565# => '0' & O"630",
8#3566# => '0' & O"154",
8#3567# => '0' & O"727",
8#3570# => '1' & O"116",
8#3571# => '1' & O"116",
8#3572# => '0' & O"224",
8#3573# => '1' & O"123",
8#3574# => '0' & O"060",
8#3575# => '0' & O"714",
8#3576# => '0' & O"330",
8#3577# => '0' & O"330",
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8#3601# => '1' & O"030",
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8#3603# => '0' & O"030",
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8#3606# => '1' & O"131",
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8#3625# => '1' & O"322",
8#3626# => '1' & O"576",
8#3627# => '1' & O"127",
8#3630# => '1' & O"376",
8#3631# => '1' & O"616",
8#3632# => '0' & O"060",
8#3633# => '1' & O"420",
8#3634# => '1' & O"316",
8#3635# => '1' & O"056",
8#3636# => '1' & O"203",
8#3637# => '1' & O"616",
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8#3642# => '1' & O"656",
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8#3644# => '1' & O"656",
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8#3654# => '1' & O"356",
8#3655# => '1' & O"454",
8#3656# => '1' & O"427",
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8#3661# => '0' & O"322",
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8#3663# => '0' & O"332",
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8#3670# => '1' & O"420",
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8#3673# => '1' & O"130",
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8#3675# => '0' & O"130",
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8#3700# => '0' & O"130",
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8#3725# => '0' & O"316",
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8#3727# => '1' & O"616",
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8#3731# => '1' & O"437",
8#3732# => '1' & O"646",
8#3733# => '0' & O"616",
8#3734# => '0' & O"056",
8#3735# => '1' & O"414",
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8#3741# => '0' & O"130",
8#3742# => '0' & O"030",
8#3743# => '0' & O"130",
8#3744# => '0' & O"730",
8#3745# => '1' & O"130",
8#3746# => '1' & O"030",
8#3747# => '0' & O"030",
8#3750# => '0' & O"530",
8#3751# => '0' & O"530",
8#3752# => '0' & O"330",
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8#3754# => '1' & O"656",
8#3755# => '0' & O"456",
8#3756# => '0' & O"606",
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8#3771# => '0' & O"330",
8#3772# => '0' & O"030",
8#3773# => '0' & O"230",
8#3774# => '0' & O"530",
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8#4012# => '0' & O"742",
8#4013# => '0' & O"742",
8#4014# => '0' & O"742",
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8#4017# => '0' & O"403",
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8#4021# => '1' & O"617",
8#4022# => '0' & O"742",
8#4023# => '0' & O"742",
8#4024# => '0' & O"742",
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8#4026# => '1' & O"030",
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8#4030# => '0' & O"364",
8#4031# => '0' & O"617",
8#4032# => '0' & O"742",
8#4033# => '0' & O"742",
8#4034# => '0' & O"742",
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8#4044# => '0' & O"417",
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8#4050# => '0' & O"504",
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8#4052# => '0' & O"742",
8#4053# => '0' & O"742",
8#4054# => '0' & O"742",
8#4055# => '0' & O"000",
8#4056# => '0' & O"742",
8#4057# => '0' & O"407",
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8#4061# => '1' & O"061",
8#4062# => '0' & O"742",
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8#4072# => '0' & O"742",
8#4073# => '0' & O"742",
8#4074# => '0' & O"000",
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8#4115# => '0' & O"250",
8#4116# => '0' & O"312",
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8#4123# => '0' & O"512",
8#4124# => '1' & O"326",
8#4125# => '0' & O"412",
8#4126# => '0' & O"416",
8#4127# => '0' & O"612",
8#4130# => '0' & O"316",
8#4131# => '0' & O"566",
8#4132# => '0' & O"542",
8#4133# => '0' & O"000",
8#4134# => '1' & O"572",
8#4135# => '0' & O"514",
8#4136# => '0' & O"030",
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8#4140# => '1' & O"376",
8#4141# => '1' & O"056",
8#4142# => '1' & O"314",
8#4143# => '0' & O"250",
8#4144# => '0' & O"302",
8#4145# => '0' & O"044",
8#4146# => '0' & O"034",
8#4147# => '1' & O"354",
8#4150# => '0' & O"633",
8#4151# => '1' & O"050",
8#4152# => '0' & O"642",
8#4153# => '0' & O"737",
8#4154# => '0' & O"524",
8#4155# => '0' & O"677",
8#4156# => '1' & O"103",
8#4157# => '0' & O"250",
8#4160# => '1' & O"124",
8#4161# => '0' & O"727",
8#4162# => '0' & O"114",
8#4163# => '0' & O"312",
8#4164# => '0' & O"320",
8#4165# => '1' & O"056",
8#4166# => '0' & O"713",
8#4167# => '0' & O"050",
8#4170# => '0' & O"024",
8#4171# => '0' & O"757",
8#4172# => '0' & O"627",
8#4173# => '0' & O"302",
8#4174# => '0' & O"742",
8#4175# => '0' & O"344",
8#4176# => '1' & O"344",
8#4177# => '1' & O"000",
8#4200# => '0' & O"524",
8#4201# => '1' & O"647",
8#4202# => '0' & O"034",
8#4203# => '1' & O"354",
8#4204# => '1' & O"003",
8#4205# => '0' & O"776",
8#4206# => '1' & O"003",
8#4207# => '0' & O"737",
8#4210# => '1' & O"722",
8#4211# => '1' & O"522",
8#4212# => '1' & O"607",
8#4213# => '1' & O"514",
8#4214# => '1' & O"752",
8#4215# => '0' & O"303",
8#4216# => '1' & O"333",
8#4217# => '0' & O"000",
8#4220# => '0' & O"336",
8#4221# => '0' & O"250",
8#4222# => '0' & O"064",
8#4223# => '0' & O"704",
8#4224# => '1' & O"124",
8#4225# => '1' & O"143",
8#4226# => '1' & O"044",
8#4227# => '0' & O"613",
8#4230# => '0' & O"616",
8#4231# => '1' & O"250",
8#4232# => '0' & O"456",
8#4233# => '1' & O"104",
8#4234# => '1' & O"014",
8#4235# => '0' & O"034",
8#4236# => '1' & O"116",
8#4237# => '0' & O"154",
8#4240# => '1' & O"167",
8#4241# => '0' & O"142",
8#4242# => '1' & O"317",
8#4243# => '1' & O"172",
8#4244# => '1' & O"043",
8#4245# => '1' & O"142",
8#4246# => '1' & O"607",
8#4247# => '1' & O"514",
8#4250# => '0' & O"034",
8#4251# => '1' & O"552",
8#4252# => '1' & O"243",
8#4253# => '1' & O"333",
8#4254# => '1' & O"144",
8#4255# => '1' & O"133",
8#4256# => '1' & O"112",
8#4257# => '0' & O"220",
8#4260# => '1' & O"024",
8#4261# => '0' & O"743",
8#4262# => '1' & O"103",
8#4263# => '1' & O"144",
8#4264# => '0' & O"302",
8#4265# => '1' & O"414",
8#4266# => '0' & O"326",
8#4267# => '0' & O"742",
8#4270# => '0' & O"742",
8#4271# => '0' & O"034",
8#4272# => '0' & O"254",
8#4273# => '1' & O"427",
8#4274# => '0' & O"312",
8#4275# => '1' & O"656",
8#4276# => '1' & O"124",
8#4277# => '1' & O"543",
8#4300# => '1' & O"552",
8#4301# => '1' & O"541",
8#4302# => '0' & O"742",
8#4303# => '1' & O"763",
8#4304# => '1' & O"463",
8#4305# => '0' & O"552",
8#4306# => '1' & O"347",
8#4307# => '0' & O"322",
8#4310# => '0' & O"562",
8#4311# => '1' & O"656",
8#4312# => '1' & O"242",
8#4313# => '1' & O"763",
8#4314# => '0' & O"074",
8#4315# => '1' & O"554",
8#4316# => '1' & O"413",
8#4317# => '0' & O"034",
8#4320# => '0' & O"306",
8#4321# => '0' & O"742",
8#4322# => '1' & O"124",
8#4323# => '1' & O"533",
8#4324# => '1' & O"326",
8#4325# => '1' & O"552",
8#4326# => '0' & O"752",
8#4327# => '1' & O"752",
8#4330# => '0' & O"772",
8#4331# => '1' & O"573",
8#4332# => '0' & O"252",
8#4333# => '1' & O"656",
8#4334# => '1' & O"056",
8#4335# => '1' & O"263",
8#4336# => '0' & O"572",
8#4337# => '0' & O"672",
8#4340# => '1' & O"557",
8#4341# => '1' & O"456",
8#4342# => '1' & O"250",
8#4343# => '1' & O"014",
8#4344# => '0' & O"130",
8#4345# => '1' & O"130",
8#4346# => '1' & O"153",
8#4347# => '0' & O"250",
8#4350# => '0' & O"220",
8#4351# => '1' & O"324",
8#4352# => '1' & O"667",
8#4353# => '1' & O"711",
8#4354# => '0' & O"620",
8#4355# => '0' & O"324",
8#4356# => '1' & O"303",
8#4357# => '1' & O"024",
8#4360# => '1' & O"747",
8#4361# => '0' & O"743",
8#4362# => '0' & O"336",
8#4363# => '0' & O"250",
8#4364# => '1' & O"124",
8#4365# => '1' & O"737",
8#4366# => '0' & O"060",
8#4367# => '1' & O"056",
8#4370# => '0' & O"060",
8#4371# => '1' & O"711",
8#4372# => '1' & O"064",
8#4373# => '1' & O"220",
8#4374# => '1' & O"124",
8#4375# => '1' & O"537",
8#4376# => '0' & O"332",
8#4377# => '1' & O"541",
8#4400# => '0' & O"000",
8#4401# => '0' & O"250",
8#4402# => '0' & O"324",
8#4403# => '0' & O"177",
8#4404# => '0' & O"616",
8#4405# => '0' & O"316",
8#4406# => '0' & O"746",
8#4407# => '0' & O"414",
8#4410# => '0' & O"524",
8#4411# => '0' & O"077",
8#4412# => '0' & O"544",
8#4413# => '1' & O"722",
8#4414# => '1' & O"656",
8#4415# => '0' & O"250",
8#4416# => '0' & O"367",
8#4417# => '1' & O"522",
8#4420# => '0' & O"061",
8#4421# => '0' & O"114",
8#4422# => '1' & O"656",
8#4423# => '0' & O"642",
8#4424# => '0' & O"137",
8#4425# => '0' & O"352",
8#4426# => '0' & O"332",
8#4427# => '0' & O"612",
8#4430# => '0' & O"477",
8#4431# => '1' & O"116",
8#4432# => '0' & O"034",
8#4433# => '1' & O"267",
8#4434# => '1' & O"116",
8#4435# => '0' & O"034",
8#4436# => '0' & O"377",
8#4437# => '0' & O"524",
8#4440# => '1' & O"207",
8#4441# => '0' & O"544",
8#4442# => '1' & O"167",
8#4443# => '1' & O"522",
8#4444# => '1' & O"567",
8#4445# => '1' & O"414",
8#4446# => '0' & O"322",
8#4447# => '0' & O"562",
8#4450# => '0' & O"414",
8#4451# => '1' & O"317",
8#4452# => '0' & O"000",
8#4453# => '0' & O"312",
8#4454# => '0' & O"154",
8#4455# => '0' & O"317",
8#4456# => '0' & O"652",
8#4457# => '0' & O"337",
8#4460# => '0' & O"552",
8#4461# => '0' & O"074",
8#4462# => '0' & O"273",
8#4463# => '0' & O"752",
8#4464# => '0' & O"416",
8#4465# => '0' & O"034",
8#4466# => '0' & O"263",
8#4467# => '1' & O"370",
8#4470# => '1' & O"642",
8#4471# => '0' & O"034",
8#4472# => '1' & O"642",
8#4473# => '1' & O"360",
8#4474# => '1' & O"775",
8#4475# => '1' & O"711",
8#4476# => '1' & O"370",
8#4477# => '0' & O"154",
8#4500# => '0' & O"163",
8#4501# => '0' & O"747",
8#4502# => '0' & O"612",
8#4503# => '0' & O"312",
8#4504# => '0' & O"114",
8#4505# => '0' & O"530",
8#4506# => '1' & O"372",
8#4507# => '1' & O"512",
8#4510# => '0' & O"473",
8#4511# => '1' & O"712",
8#4512# => '1' & O"112",
8#4513# => '0' & O"102",
8#4514# => '0' & O"107",
8#4515# => '0' & O"477",
8#4516# => '1' & O"572",
8#4517# => '1' & O"250",
8#4520# => '0' & O"606",
8#4521# => '0' & O"406",
8#4522# => '0' & O"316",
8#4523# => '0' & O"566",
8#4524# => '0' & O"752",
8#4525# => '1' & O"324",
8#4526# => '0' & O"543",
8#4527# => '0' & O"312",
8#4530# => '0' & O"552",
8#4531# => '0' & O"250",
8#4532# => '0' & O"336",
8#4533# => '0' & O"250",
8#4534# => '0' & O"020",
8#4535# => '0' & O"336",
8#4536# => '0' & O"644",
8#4537# => '0' & O"444",
8#4540# => '0' & O"244",
8#4541# => '0' & O"144",
8#4542# => '0' & O"060",
8#4543# => '0' & O"336",
8#4544# => '0' & O"776",
8#4545# => '0' & O"776",
8#4546# => '0' & O"250",
8#4547# => '0' & O"324",
8#4550# => '0' & O"763",
8#4551# => '1' & O"250",
8#4552# => '0' & O"746",
8#4553# => '0' & O"606",
8#4554# => '0' & O"414",
8#4555# => '1' & O"242",
8#4556# => '0' & O"713",
8#4557# => '0' & O"030",
8#4560# => '0' & O"030",
8#4561# => '1' & O"653",
8#4562# => '0' & O"406",
8#4563# => '0' & O"316",
8#4564# => '0' & O"556",
8#4565# => '0' & O"332",
8#4566# => '1' & O"372",
8#4567# => '1' & O"572",
8#4570# => '0' & O"561",
8#4571# => '1' & O"324",
8#4572# => '1' & O"703",
8#4573# => '0' & O"413",
8#4574# => '0' & O"601",
8#4575# => '1' & O"124",
8#4576# => '1' & O"003",
8#4577# => '1' & O"007",
8#4600# => '1' & O"056",
8#4601# => '0' & O"250",
8#4602# => '1' & O"414",
8#4603# => '1' & O"024",
8#4604# => '1' & O"067",
8#4605# => '1' & O"314",
8#4606# => '0' & O"044",
8#4607# => '0' & O"024",
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8#4611# => '0' & O"142",
8#4612# => '1' & O"143",
8#4613# => '1' & O"414",
8#4614# => '1' & O"117",
8#4615# => '0' & O"642",
8#4616# => '1' & O"117",
8#4617# => '0' & O"746",
8#4620# => '0' & O"742",
8#4621# => '0' & O"542",
8#4622# => '1' & O"027",
8#4623# => '0' & O"302",
8#4624# => '0' & O"250",
8#4625# => '0' & O"164",
8#4626# => '1' & O"123",
8#4627# => '0' & O"302",
8#4630# => '0' & O"050",
8#4631# => '0' & O"250",
8#4632# => '1' & O"124",
8#4633# => '1' & O"233",
8#4634# => '1' & O"237",
8#4635# => '1' & O"414",
8#4636# => '1' & O"130",
8#4637# => '0' & O"250",
8#4640# => '1' & O"237",
8#4641# => '0' & O"565",
8#4642# => '0' & O"414",
8#4643# => '0' & O"322",
8#4644# => '0' & O"250",
8#4645# => '0' & O"767",
8#4646# => '1' & O"056",
8#4647# => '1' & O"711",
8#4650# => '1' & O"324",
8#4651# => '1' & O"263",
8#4652# => '1' & O"064",
8#4653# => '0' & O"037",
8#4654# => '1' & O"370",
8#4655# => '0' & O"154",
8#4656# => '0' & O"147",
8#4657# => '1' & O"775",
8#4660# => '0' & O"114",
8#4661# => '1' & O"064",
8#4662# => '0' & O"103",
8#4663# => '1' & O"662",
8#4664# => '0' & O"622",
8#4665# => '1' & O"714",
8#4666# => '0' & O"034",
8#4667# => '0' & O"034",
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8#4671# => '1' & O"333",
8#4672# => '1' & O"116",
8#4673# => '0' & O"776",
8#4674# => '0' & O"776",
8#4675# => '1' & O"116",
8#4676# => '0' & O"312",
8#4677# => '0' & O"752",
8#4700# => '1' & O"160",
8#4701# => '0' & O"312",
8#4702# => '0' & O"552",
8#4703# => '0' & O"552",
8#4704# => '0' & O"552",
8#4705# => '1' & O"656",
8#4706# => '0' & O"412",
8#4707# => '1' & O"372",
8#4710# => '0' & O"416",
8#4711# => '0' & O"416",
8#4712# => '1' & O"656",
8#4713# => '0' & O"576",
8#4714# => '0' & O"576",
8#4715# => '0' & O"576",
8#4716# => '1' & O"523",
8#4717# => '1' & O"746",
8#4720# => '0' & O"250",
8#4721# => '1' & O"656",
8#4722# => '0' & O"250",
8#4723# => '0' & O"060",
8#4724# => '1' & O"706",
8#4725# => '1' & O"467",
8#4726# => '1' & O"662",
8#4727# => '0' & O"314",
8#4730# => '0' & O"730",
8#4731# => '0' & O"414",
8#4732# => '1' & O"546",
8#4733# => '0' & O"776",
8#4734# => '0' & O"776",
8#4735# => '0' & O"776",
8#4736# => '0' & O"217",
8#4737# => '1' & O"656",
8#4740# => '0' & O"322",
8#4741# => '0' & O"606",
8#4742# => '1' & O"733",
8#4743# => '0' & O"250",
8#4744# => '1' & O"172",
8#4745# => '1' & O"643",
8#4746# => '0' & O"412",
8#4747# => '1' & O"316",
8#4750# => '0' & O"250",
8#4751# => '0' & O"746",
8#4752# => '0' & O"250",
8#4753# => '1' & O"312",
8#4754# => '1' & O"711",
8#4755# => '1' & O"324",
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8#4757# => '0' & O"367",
8#4760# => '1' & O"775",
8#4761# => '0' & O"413",
8#4762# => '1' & O"344",
8#4763# => '0' & O"250",
8#4764# => '1' & O"656",
8#4765# => '0' & O"250",
8#4766# => '0' & O"316",
8#4767# => '0' & O"414",
8#4770# => '1' & O"662",
8#4771# => '0' & O"146",
8#4772# => '1' & O"533",
8#4773# => '1' & O"662",
8#4774# => '1' & O"304",
8#4775# => '1' & O"503",
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8#4777# => '0' & O"420",
8#5000# => '0' & O"250",
8#5001# => '0' & O"514",
8#5002# => '0' & O"542",
8#5003# => '0' & O"364",
8#5004# => '1' & O"513",
8#5005# => '0' & O"752",
8#5006# => '1' & O"316",
8#5007# => '0' & O"056",
8#5010# => '0' & O"452",
8#5011# => '1' & O"616",
8#5012# => '1' & O"176",
8#5013# => '0' & O"027",
8#5014# => '1' & O"623",
8#5015# => '0' & O"032",
8#5016# => '1' & O"463",
8#5017# => '1' & O"517",
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8#5022# => '0' & O"430",
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8#5025# => '0' & O"530",
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8#5030# => '0' & O"330",
8#5031# => '0' & O"730",
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8#5037# => '0' & O"530",
8#5040# => '0' & O"530",
8#5041# => '0' & O"030",
8#5042# => '0' & O"530",
8#5043# => '0' & O"530",
8#5044# => '1' & O"030",
8#5045# => '0' & O"530",
8#5046# => '0' & O"330",
8#5047# => '0' & O"014",
8#5050# => '0' & O"330",
8#5051# => '0' & O"347",
8#5052# => '1' & O"414",
8#5053# => '1' & O"552",
8#5054# => '0' & O"157",
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8#5056# => '0' & O"730",
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8#5060# => '0' & O"530",
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8#5063# => '1' & O"130",
8#5064# => '0' & O"230",
8#5065# => '0' & O"530",
8#5066# => '0' & O"230",
8#5067# => '0' & O"552",
8#5070# => '0' & O"552",
8#5071# => '1' & O"064",
8#5072# => '1' & O"707",
8#5073# => '1' & O"552",
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8#5075# => '0' & O"230",
8#5076# => '0' & O"530",
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8#5100# => '0' & O"752",
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8#5102# => '1' & O"552",
8#5103# => '1' & O"727",
8#5104# => '0' & O"330",
8#5105# => '0' & O"030",
8#5106# => '0' & O"430",
8#5107# => '1' & O"030",
8#5110# => '0' & O"343",
8#5111# => '1' & O"552",
8#5112# => '0' & O"357",
8#5113# => '0' & O"504",
8#5114# => '0' & O"347",
8#5115# => '0' & O"542",
8#5116# => '0' & O"642",
8#5117# => '0' & O"523",
8#5120# => '1' & O"130",
8#5121# => '0' & O"523",
8#5122# => '1' & O"004",
8#5123# => '0' & O"130",
8#5124# => '0' & O"364",
8#5125# => '1' & O"013",
8#5126# => '0' & O"000",
8#5127# => '0' & O"000",
8#5130# => '1' & O"414",
8#5131# => '0' & O"176",
8#5132# => '0' & O"777",
8#5133# => '0' & O"172",
8#5134# => '0' & O"777",
8#5135# => '0' & O"616",
8#5136# => '0' & O"456",
8#5137# => '0' & O"426",
8#5140# => '1' & O"162",
8#5141# => '1' & O"043",
8#5142# => '1' & O"752",
8#5143# => '0' & O"112",
8#5144# => '1' & O"057",
8#5145# => '0' & O"772",
8#5146# => '1' & O"263",
8#5147# => '1' & O"552",
8#5150# => '0' & O"447",
8#5151# => '0' & O"430",
8#5152# => '0' & O"430",
8#5153# => '0' & O"430",
8#5154# => '1' & O"030",
8#5155# => '0' & O"230",
8#5156# => '0' & O"230",
8#5157# => '0' & O"130",
8#5160# => '0' & O"630",
8#5161# => '0' & O"130",
8#5162# => '0' & O"530",
8#5163# => '0' & O"347",
8#5164# => '0' & O"630",
8#5165# => '0' & O"164",
8#5166# => '1' & O"107",
8#5167# => '0' & O"000",
8#5170# => '0' & O"000",
8#5171# => '0' & O"000",
8#5172# => '0' & O"000",
8#5173# => '0' & O"250",
8#5174# => '1' & O"014",
8#5175# => '0' & O"030",
8#5176# => '0' & O"723",
8#5177# => '1' & O"064",
8#5200# => '0' & O"503",
8#5201# => '0' & O"016",
8#5202# => '1' & O"477",
8#5203# => '1' & O"414",
8#5204# => '0' & O"212",
8#5205# => '1' & O"443",
8#5206# => '1' & O"064",
8#5207# => '0' & O"020",
8#5210# => '1' & O"552",
8#5211# => '0' & O"573",
8#5212# => '0' & O"777",
8#5213# => '0' & O"316",
8#5214# => '0' & O"742",
8#5215# => '1' & O"116",
8#5216# => '0' & O"776",
8#5217# => '1' & O"056",
8#5220# => '0' & O"002",
8#5221# => '1' & O"123",
8#5222# => '1' & O"222",
8#5223# => '0' & O"752",
8#5224# => '1' & O"356",
8#5225# => '1' & O"502",
8#5226# => '1' & O"153",
8#5227# => '0' & O"416",
8#5230# => '1' & O"616",
8#5231# => '1' & O"143",
8#5232# => '1' & O"536",
8#5233# => '1' & O"207",
8#5234# => '1' & O"322",
8#5235# => '1' & O"756",
8#5236# => '0' & O"752",
8#5237# => '1' & O"616",
8#5240# => '1' & O"177",
8#5241# => '1' & O"462",
8#5242# => '0' & O"542",
8#5243# => '1' & O"103",
8#5244# => '0' & O"576",
8#5245# => '1' & O"103",
8#5246# => '0' & O"416",
8#5247# => '0' & O"452",
8#5250# => '1' & O"622",
8#5251# => '0' & O"326",
8#5252# => '1' & O"716",
8#5253# => '1' & O"666",
8#5254# => '1' & O"064",
8#5255# => '1' & O"037",
8#5256# => '1' & O"122",
8#5257# => '0' & O"722",
8#5260# => '0' & O"622",
8#5261# => '1' & O"122",
8#5262# => '1' & O"262",
8#5263# => '1' & O"262",
8#5264# => '0' & O"522",
8#5265# => '0' & O"424",
8#5266# => '1' & O"417",
8#5267# => '0' & O"060",
8#5270# => '1' & O"552",
8#5271# => '0' & O"253",
8#5272# => '0' & O"704",
8#5273# => '1' & O"007",
8#5274# => '1' & O"414",
8#5275# => '0' & O"642",
8#5276# => '0' & O"513",
8#5277# => '1' & O"024",
8#5300# => '0' & O"467",
8#5301# => '1' & O"044",
8#5302# => '0' & O"523",
8#5303# => '1' & O"722",
8#5304# => '1' & O"122",
8#5305# => '0' & O"162",
8#5306# => '1' & O"417",
8#5307# => '0' & O"060",
8#5310# => '0' & O"752",
8#5311# => '0' & O"752",
8#5312# => '0' & O"172",
8#5313# => '0' & O"067",
8#5314# => '0' & O"034",
8#5315# => '0' & O"054",
8#5316# => '1' & O"507",
8#5317# => '0' & O"216",
8#5320# => '1' & O"033",
8#5321# => '0' & O"552",
8#5322# => '1' & O"463",
8#5323# => '0' & O"316",
8#5324# => '0' & O"206",
8#5325# => '0' & O"424",
8#5326# => '1' & O"633",
8#5327# => '0' & O"074",
8#5330# => '0' & O"074",
8#5331# => '1' & O"301",
8#5332# => '0' & O"034",
8#5333# => '0' & O"034",
8#5334# => '1' & O"301",
8#5335# => '0' & O"616",
8#5336# => '0' & O"216",
8#5337# => '1' & O"414",
8#5340# => '1' & O"142",
8#5341# => '1' & O"623",
8#5342# => '0' & O"552",
8#5343# => '0' & O"416",
8#5344# => '1' & O"646",
8#5345# => '1' & O"033",
8#5346# => '1' & O"356",
8#5347# => '1' & O"271",
8#5350# => '0' & O"074",
8#5351# => '0' & O"074",
8#5352# => '1' & O"271",
8#5353# => '0' & O"416",
8#5354# => '0' & O"716",
8#5355# => '1' & O"356",
8#5356# => '0' & O"612",
8#5357# => '1' & O"716",
8#5360# => '0' & O"216",
8#5361# => '1' & O"176",
8#5362# => '0' & O"027",
8#5363# => '1' & O"623",
8#5364# => '0' & O"000",
8#5365# => '0' & O"330",
8#5366# => '0' & O"730",
8#5367# => '1' & O"030",
8#5370# => '0' & O"530",
8#5371# => '0' & O"430",
8#5372# => '0' & O"130",
8#5373# => '0' & O"130",
8#5374# => '0' & O"730",
8#5375# => '1' & O"030",
8#5376# => '0' & O"430",
8#5377# => '0' & O"347",
8#5400# => '0' & O"347",
8#5401# => '1' & O"103",
8#5402# => '0' & O"347",
8#5403# => '0' & O"347",
8#5404# => '0' & O"347",
8#5405# => '0' & O"037",
8#5406# => '0' & O"347",
8#5407# => '0' & O"047",
8#5410# => '0' & O"347",
8#5411# => '0' & O"067",
8#5412# => '0' & O"347",
8#5413# => '0' & O"347",
8#5414# => '0' & O"347",
8#5415# => '0' & O"127",
8#5416# => '0' & O"347",
8#5417# => '0' & O"624",
8#5420# => '0' & O"007",
8#5421# => '0' & O"603",
8#5422# => '0' & O"363",
8#5423# => '0' & O"767",
8#5424# => '0' & O"777",
8#5425# => '0' & O"147",
8#5426# => '0' & O"347",
8#5427# => '1' & O"130",
8#5430# => '1' & O"447",
8#5431# => '0' & O"167",
8#5432# => '1' & O"007",
8#5433# => '1' & O"713",
8#5434# => '1' & O"723",
8#5435# => '0' & O"207",
8#5436# => '0' & O"347",
8#5437# => '1' & O"030",
8#5440# => '1' & O"447",
8#5441# => '0' & O"227",
8#5442# => '1' & O"043",
8#5443# => '0' & O"347",
8#5444# => '1' & O"733",
8#5445# => '0' & O"237",
8#5446# => '0' & O"347",
8#5447# => '0' & O"247",
8#5450# => '0' & O"347",
8#5451# => '0' & O"267",
8#5452# => '0' & O"347",
8#5453# => '0' & O"347",
8#5454# => '0' & O"347",
8#5455# => '0' & O"307",
8#5456# => '0' & O"347",
8#5457# => '0' & O"730",
8#5460# => '1' & O"447",
8#5461# => '0' & O"327",
8#5462# => '0' & O"137",
8#5463# => '0' & O"177",
8#5464# => '0' & O"277",
8#5465# => '1' & O"233",
8#5466# => '0' & O"347",
8#5467# => '0' & O"604",
8#5470# => '1' & O"356",
8#5471# => '0' & O"075",
8#5472# => '1' & O"063",
8#5473# => '0' & O"347",
8#5474# => '0' & O"630",
8#5475# => '1' & O"447",
8#5476# => '0' & O"347",
8#5477# => '0' & O"056",
8#5500# => '0' & O"616",
8#5501# => '0' & O"316",
8#5502# => '0' & O"546",
8#5503# => '1' & O"014",
8#5504# => '0' & O"630",
8#5505# => '0' & O"030",
8#5506# => '0' & O"454",
8#5507# => '0' & O"423",
8#5510# => '0' & O"030",
8#5511# => '1' & O"066",
8#5512# => '0' & O"226",
8#5513# => '0' & O"776",
8#5514# => '1' & O"126",
8#5515# => '0' & O"752",
8#5516# => '1' & O"176",
8#5517# => '0' & O"337",
8#5520# => '1' & O"172",
8#5521# => '1' & O"647",
8#5522# => '1' & O"552",
8#5523# => '1' & O"613",
8#5524# => '1' & O"316",
8#5525# => '1' & O"316",
8#5526# => '1' & O"316",
8#5527# => '1' & O"316",
8#5530# => '1' & O"322",
8#5531# => '1' & O"322",
8#5532# => '0' & O"714",
8#5533# => '0' & O"102",
8#5534# => '0' & O"337",
8#5535# => '0' & O"514",
8#5536# => '0' & O"102",
8#5537# => '0' & O"337",
8#5540# => '0' & O"604",
8#5541# => '1' & O"741",
8#5542# => '1' & O"044",
8#5543# => '0' & O"044",
8#5544# => '0' & O"034",
8#5545# => '1' & O"354",
8#5546# => '0' & O"623",
8#5547# => '0' & O"024",
8#5550# => '1' & O"017",
8#5551# => '1' & O"024",
8#5552# => '0' & O"617",
8#5553# => '0' & O"320",
8#5554# => '1' & O"111",
8#5555# => '0' & O"456",
8#5556# => '0' & O"302",
8#5557# => '1' & O"160",
8#5560# => '1' & O"656",
8#5561# => '1' & O"370",
8#5562# => '1' & O"656",
8#5563# => '1' & O"111",
8#5564# => '1' & O"656",
8#5565# => '1' & O"360",
8#5566# => '1' & O"656",
8#5567# => '0' & O"742",
8#5570# => '0' & O"677",
8#5571# => '0' & O"216",
8#5572# => '0' & O"420",
8#5573# => '1' & O"765",
8#5574# => '1' & O"247",
8#5575# => '0' & O"530",
8#5576# => '1' & O"447",
8#5577# => '0' & O"430",
8#5600# => '1' & O"447",
8#5601# => '0' & O"330",
8#5602# => '1' & O"447",
8#5603# => '1' & O"004",
8#5604# => '1' & O"344",
8#5605# => '1' & O"324",
8#5606# => '0' & O"663",
8#5607# => '0' & O"617",
8#5610# => '0' & O"624",
8#5611# => '0' & O"603",
8#5612# => '0' & O"064",
8#5613# => '0' & O"027",
8#5614# => '1' & O"056",
8#5615# => '0' & O"352",
8#5616# => '1' & O"056",
8#5617# => '0' & O"624",
8#5620# => '0' & O"757",
8#5621# => '0' & O"603",
8#5622# => '1' & O"414",
8#5623# => '1' & O"156",
8#5624# => '1' & O"137",
8#5625# => '1' & O"314",
8#5626# => '0' & O"060",
8#5627# => '1' & O"142",
8#5630# => '1' & O"127",
8#5631# => '0' & O"314",
8#5632# => '0' & O"422",
8#5633# => '0' & O"422",
8#5634# => '0' & O"416",
8#5635# => '0' & O"416",
8#5636# => '1' & O"752",
8#5637# => '1' & O"414",
8#5640# => '0' & O"406",
8#5641# => '1' & O"142",
8#5642# => '1' & O"127",
8#5643# => '1' & O"552",
8#5644# => '1' & O"050",
8#5645# => '1' & O"203",
8#5646# => '1' & O"423",
8#5647# => '1' & O"360",
8#5650# => '1' & O"656",
8#5651# => '0' & O"114",
8#5652# => '1' & O"762",
8#5653# => '1' & O"703",
8#5654# => '0' & O"414",
8#5655# => '1' & O"742",
8#5656# => '0' & O"027",
8#5657# => '0' & O"514",
8#5660# => '1' & O"742",
8#5661# => '0' & O"102",
8#5662# => '1' & O"323",
8#5663# => '0' & O"147",
8#5664# => '1' & O"342",
8#5665# => '0' & O"614",
8#5666# => '1' & O"742",
8#5667# => '0' & O"227",
8#5670# => '0' & O"714",
8#5671# => '1' & O"742",
8#5672# => '0' & O"102",
8#5673# => '1' & O"367",
8#5674# => '0' & O"327",
8#5675# => '1' & O"342",
8#5676# => '1' & O"014",
8#5677# => '1' & O"742",
8#5700# => '1' & O"563",
8#5701# => '1' & O"114",
8#5702# => '1' & O"742",
8#5703# => '1' & O"575",
8#5704# => '0' & O"724",
8#5705# => '1' & O"517",
8#5706# => '1' & O"314",
8#5707# => '0' & O"064",
8#5710# => '0' & O"320",
8#5711# => '1' & O"160",
8#5712# => '1' & O"656",
8#5713# => '0' & O"624",
8#5714# => '1' & O"237",
8#5715# => '1' & O"370",
8#5716# => '1' & O"414",
8#5717# => '0' & O"142",
8#5720# => '0' & O"403",
8#5721# => '1' & O"656",
8#5722# => '0' & O"603",
8#5723# => '0' & O"044",
8#5724# => '0' & O"024",
8#5725# => '1' & O"553",
8#5726# => '1' & O"024",
8#5727# => '1' & O"607",
8#5730# => '0' & O"704",
8#5731# => '0' & O"007",
8#5732# => '1' & O"004",
8#5733# => '1' & O"607",
8#5734# => '1' & O"214",
8#5735# => '0' & O"034",
8#5736# => '1' & O"054",
8#5737# => '1' & O"567",
8#5740# => '0' & O"007",
8#5741# => '1' & O"603",
8#5742# => '0' & O"426",
8#5743# => '1' & O"552",
8#5744# => '0' & O"337",
8#5745# => '0' & O"523",
8#5746# => '1' & O"166",
8#5747# => '1' & O"647",
8#5750# => '0' & O"343",
8#5751# => '1' & O"326",
8#5752# => '1' & O"752",
8#5753# => '1' & O"633",
8#5754# => '0' & O"523",
8#5755# => '1' & O"064",
8#5756# => '0' & O"103",
8#5757# => '0' & O"000",
8#5760# => '1' & O"741",
8#5761# => '0' & O"147",
8#5762# => '0' & O"230",
8#5763# => '1' & O"447",
8#5764# => '0' & O"130",
8#5765# => '1' & O"447",
8#5766# => '0' & O"030",
8#5767# => '1' & O"447",
8#5770# => '1' & O"114",
8#5771# => '1' & O"142",
8#5772# => '1' & O"773",
8#5773# => '1' & O"042",
8#5774# => '0' & O"202",
8#5775# => '0' & O"060",
8#5776# => '0' & O"042",
8#5777# => '1' & O"767"
); -- End 55 ROM
end rom_pack;
package body rom_pack is
end rom_pack;
| mit |
Umesh8Joshi/VHDL-programs | Mux.vhdl | 1 | 600 | LIBRARY IEEE;
USE IEEE.std_logic_1164ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b : IN std_logic;
PORT (q : OUT std_logic);
END mux;
ARCHITECTURE better OF mux IS
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
VARIABLE muxval : INTEGER;
BEGIN
muxval := 0;
IF (a = ‘1’) THEN
muxval := muxval + 1;
END IF;
IF (b = ‘1’) THEN
muxval := muxval + 2;
END IF;
CASE muxval IS
WHEN 0 =>
q <= I0 AFTER 10 ns;
WHEN 1 =>
q <= I1 AFTER 10 ns;
WHEN 2 =>
q <= I2 AFTER 10 ns;
WHEN 3 =>
q <= I3 AFTER 10 ns;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
END better; | mit |
pkerling/Chips-Demo | source/reset_generator.vhd | 1 | 851 | library ieee;
use ieee.std_logic_1164.all;
entity reset_generator is
generic(
-- 20 ms at 125 MHz clock
-- Minimum 88E1111 reset pulse width: 10 ms
RESET_DELAY : positive := 2500000
);
port(
clock_i : in std_ulogic;
locked_i : in std_ulogic;
reset_o : out std_ulogic
);
end entity;
architecture rtl of reset_generator is
signal reset_cnt : natural range 0 to RESET_DELAY := 0;
begin
reset_proc : process(clock_i, locked_i)
begin
if locked_i = '1' then
if rising_edge(clock_i) then
-- When locked, wait for RESET_DELAY ticks, then deassert reset
if reset_cnt < RESET_DELAY then
reset_cnt <= reset_cnt + 1;
reset_o <= '1';
else
reset_o <= '0';
end if;
end if;
else
-- Keep in reset when not locked
reset_cnt <= 0;
reset_o <= '1';
end if;
end process;
end architecture;
| mit |
pkerling/Chips-Demo | source/chips_mac_adaptor.vhd | 1 | 5004 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ethernet_mac;
use ethernet_mac.ethernet_types.all;
use ethernet_mac.framing_common.all;
entity chips_mac_adaptor is
port(
-- Common clock for MAC and chips
clock_i : in std_ulogic;
reset_i : in std_ulogic;
-- MAC FIFO interface
tx_data_o : out t_ethernet_data;
tx_wr_en_o : out std_ulogic;
tx_full_i : in std_ulogic;
rx_empty_i : in std_ulogic;
rx_rd_en_o : out std_ulogic;
rx_data_i : in t_ethernet_data;
-- Chips interface
chips_tx_i : in std_logic_vector(15 downto 0);
chips_tx_stb_i : in std_logic;
chips_tx_ack_o : out std_logic;
chips_rx_o : out std_logic_vector(15 downto 0);
chips_rx_stb_o : out std_logic;
chips_rx_ack_i : in std_logic
);
end entity;
architecture rtl of chips_mac_adaptor is
type t_tx_state is (
TX_IDLE,
TX_WRITE_SIZE_LO_BYTE,
TX_FORWARD_HI_BYTE,
TX_FORWARD_LO_BYTE
);
signal tx_state : t_tx_state := TX_IDLE;
type t_rx_state is (
RX_IDLE,
RX_READ_HI_BYTE,
RX_READ_LO_BYTE,
RX_WAIT_ACK
);
signal rx_state : t_rx_state := RX_IDLE;
signal tx_lo_byte_buf : t_ethernet_data := (others => '0');
signal tx_forward_bytes_remaining : natural range 0 to MAX_PACKET_LENGTH := 0;
begin
tx_chips_to_ethernet_copy_proc : process(clock_i)
begin
if rising_edge(clock_i) then
-- Default output values
chips_tx_ack_o <= '0';
tx_wr_en_o <= '0';
if reset_i = '1' then
tx_state <= TX_IDLE;
else
case tx_state is
when TX_IDLE =>
chips_tx_ack_o <= not tx_full_i;
if chips_tx_stb_i = '1' then
-- Read and forward data size
tx_data_o <= t_ethernet_data(chips_tx_i(15 downto 8));
tx_wr_en_o <= '1';
tx_lo_byte_buf <= t_ethernet_data(chips_tx_i(7 downto 0));
tx_state <= TX_WRITE_SIZE_LO_BYTE;
tx_forward_bytes_remaining <= to_integer(unsigned(chips_tx_i));
end if;
when TX_WRITE_SIZE_LO_BYTE =>
tx_data_o <= tx_lo_byte_buf;
tx_wr_en_o <= '1';
tx_state <= TX_FORWARD_HI_BYTE;
when TX_FORWARD_HI_BYTE =>
chips_tx_ack_o <= not tx_full_i;
if chips_tx_stb_i = '1' then
-- Write data
tx_forward_bytes_remaining <= tx_forward_bytes_remaining - 1;
tx_data_o <= t_ethernet_data(chips_tx_i(15 downto 8));
tx_wr_en_o <= '1';
-- Capture for next state (chips may change the value so it needs to be buffered)
tx_lo_byte_buf <= t_ethernet_data(chips_tx_i(7 downto 0));
if tx_forward_bytes_remaining = 1 then
-- This was the last one
tx_state <= TX_IDLE;
else
tx_state <= TX_FORWARD_LO_BYTE;
end if;
end if;
when TX_FORWARD_LO_BYTE =>
-- Write data
tx_forward_bytes_remaining <= tx_forward_bytes_remaining - 1;
tx_data_o <= tx_lo_byte_buf;
tx_wr_en_o <= '1';
if tx_forward_bytes_remaining = 1 then
-- This was the last one
tx_state <= TX_IDLE;
else
-- Set ACK so the data can already be present in the next cycle
-- (assuming chips is fast enough)
chips_tx_ack_o <= not tx_full_i;
tx_state <= TX_FORWARD_HI_BYTE;
end if;
end case;
end if;
end if;
end process;
rx_ethernet_to_chips_copy_proc : process(clock_i)
begin
if rising_edge(clock_i) then
chips_rx_stb_o <= '0';
rx_rd_en_o <= '0';
if reset_i = '1' then
rx_state <= RX_IDLE;
else
case rx_state is
when RX_IDLE =>
if rx_empty_i = '0' then
rx_state <= RX_READ_HI_BYTE;
rx_rd_en_o <= '1';
end if;
when RX_READ_HI_BYTE =>
chips_rx_o(15 downto 8) <= std_logic_vector(rx_data_i);
if rx_empty_i = '0' then
rx_state <= RX_READ_LO_BYTE;
rx_rd_en_o <= '1';
else
-- This was the end of the packet
rx_state <= RX_IDLE;
end if;
when RX_READ_LO_BYTE =>
chips_rx_o(7 downto 0) <= std_logic_vector(rx_data_i);
-- Signal data available
chips_rx_stb_o <= '1';
rx_state <= RX_WAIT_ACK;
if rx_empty_i = '1' then
-- We have overrun the buffer ->
-- The packet is received completely and is of uneven length
-- Zero out the unused bits
chips_rx_o(7 downto 0) <= (others => '0');
end if;
when RX_WAIT_ACK =>
-- Continue signaling as long as data is not ACKed
chips_rx_stb_o <= not chips_rx_ack_i;
if chips_rx_ack_i = '1' then
if rx_empty_i = '1' then
-- No more data to read
rx_state <= RX_IDLE;
else
-- Continue and read next byte
rx_state <= RX_READ_HI_BYTE;
rx_rd_en_o <= '1';
end if;
end if;
end case;
end if;
end if;
end process;
end architecture;
| mit |
ssabogal/nocturnal | ip_repo/router/src/fifo.vhd | 2 | 2327 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
FIFO_WIDTH : positive := 10;
DATA_WIDTH : positive := 32
);
port (
-- clock and reset
CLOCK : in std_logic;
RESET : in std_logic;
-- fifo input interface
DAT_I : in std_logic_vector(DATA_WIDTH-1 downto 0); --din
VAL_I : in std_logic; --push
RDY_I : out std_logic; --ready for push
FULL : out std_logic; --not ready for push
-- fifo output interface
DAT_O : out std_logic_vector(DATA_WIDTH-1 downto 0); --dout
VAL_O : out std_logic; --ready for pop
RDY_O : in std_logic; --pop
EMPTY : out std_logic; --not ready for pop
OCC_SIZE : out std_logic_vector(FIFO_WIDTH-1 downto 0);
VAC_SIZE : out std_logic_vector(FIFO_WIDTH-1 downto 0)
);
end entity;
architecture structure of fifo is
constant NR_ENTRIES : positive := 2**FIFO_WIDTH-1;
type memory_t is array (NR_ENTRIES downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal mem : memory_t;
signal wr_addr : unsigned(FIFO_WIDTH-1 downto 0);
signal rd_addr : unsigned(FIFO_WIDTH-1 downto 0);
signal full_sig : std_logic;
signal empty_sig : std_logic;
signal size_sig : std_logic_vector(FIFO_WIDTH-1 downto 0);
begin
DAT_O <= mem(to_integer(rd_addr));
empty_sig <= '1' when wr_addr = rd_addr else '0';
full_sig <= '1' when wr_addr + 1 = rd_addr else '0';
EMPTY <= empty_sig;
FULL <= full_sig;
VAL_O <= not empty_sig;
RDY_I <= not full_sig;
OCC_SIZE <= size_sig;
VAC_SIZE <= std_logic_vector(to_unsigned(NR_ENTRIES, FIFO_WIDTH) - unsigned(size_sig));
process (wr_addr, rd_addr)
begin
if wr_addr >= rd_addr then
size_sig <= std_logic_vector(wr_addr - rd_addr);
else
size_sig <= std_logic_vector((rd_addr - wr_addr) + to_unsigned(NR_ENTRIES, FIFO_WIDTH));
end if;
end process;
process (CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
wr_addr <= (others => '0');
rd_addr <= (others => '0');
else
if VAL_I = '1' and full_sig = '0' then
mem(to_integer(wr_addr)) <= DAT_I;
wr_addr <= wr_addr + 1;
end if;
if RDY_O = '1' and empty_sig = '0' then
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process;
end architecture;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_0_0/sim/sys_router_0_0.vhd | 1 | 7447 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_0_0 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC
);
END sys_router_0_0;
ARCHITECTURE sys_router_0_0_arch OF sys_router_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 0,
ADDR_Y => 0,
N_INST => true,
S_INST => false,
E_INST => true,
W_INST => false
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_VIN => '0',
S_ROUT => '0',
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
W_VIN => '0',
W_ROUT => '0'
);
END sys_router_0_0_arch;
| mit |
ssabogal/nocturnal | ip_repo/nic_1.0/src/nic_v1_0_S00_AXI.vhd | 2 | 19933 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nic_v1_0_S00_AXI is
generic (
-- Users to add parameters here
USE_1K_NOT_4K_FIFO_DEPTH : boolean := true;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
RX_DATA : in std_logic_vector(31 downto 0);
RX_VALID : in std_logic;
RX_READY : out std_logic;
TX_DATA : out std_logic_vector(31 downto 0);
TX_VALID : out std_logic;
TX_READY : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end nic_v1_0_S00_AXI;
architecture arch_imp of nic_v1_0_S00_AXI is
component FIFO_32x1K is
Port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
end component;
component FIFO_32x4K is
Port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 )
);
end component;
signal tx_go : std_logic;
signal rxif_valid : std_logic;
signal rxif_data : std_logic_vector(31 downto 0);
signal rxif_ready : std_logic;
signal rxif_count : std_logic_vector(31 downto 0);
signal txif_valid : std_logic;
signal txif_data : std_logic_vector(31 downto 0);
signal tx_valid_sig : std_logic;
signal tx_ready_sig : std_logic;
signal txif_count : std_logic_vector(31 downto 0);
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 5
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
txif_valid <= '0'; --push effect
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
-- slv_reg2 <= (others => '0');
-- slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
else
txif_valid <= '0'; --push effect
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
txif_valid <= '1'; --push effect
end if;
end loop;
-- when b"001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 1
-- slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"010" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 2
-- slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when b"011" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 3
-- slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
-- when b"000" =>
-- reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
when b"011" =>
reg_data_out <= slv_reg3;
when b"100" =>
reg_data_out <= slv_reg4;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--slv_reg0: TX data W (DATA pushed into TX FIFO)
txif_data <= slv_reg0(31 downto 0);
--txif_valid <= <INTEGRATED ABOVE>; --push effect
--slv_reg1: RX data R (DATA popped from RX FIFO)
slv_reg1(31 downto 0) <= rxif_data;
slv_reg1(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');
rxif_ready <= '1' when (axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB) = "001") and (axi_rvalid = '1' and S_AXI_RREADY = '1') else '0'; --pop effect
--slv_reg2: TX count R (number of words in TX FIFO)
slv_reg2 <= txif_count;
slv_reg2(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');
--slv_reg3: RX count R (number of words in RX FIFO)
slv_reg3 <= rxif_count;
slv_reg3(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');
--slv_reg4: TX go WR (control signal to inhibit/commence transfer of TX packet)
tx_go <= slv_reg4(0);
tx_ready_sig <= tx_go and TX_READY;
TX_VALID <= tx_go and tx_valid_sig;
g1Ki: if USE_1K_NOT_4K_FIFO_DEPTH = true generate
tx_fifo: FIFO_32x1K
port map (
s_aclk => S_AXI_ACLK,
s_aresetn => S_AXI_ARESETN,
s_axis_tvalid => txif_valid,
s_axis_tready => open,
s_axis_tdata => txif_data,
m_axis_tvalid => tx_valid_sig,
m_axis_tready => tx_ready_sig,
m_axis_tdata => TX_DATA,
axis_data_count => txif_count(10 downto 0)
);
rx_fifo: FIFO_32x1K
port map (
s_aclk => S_AXI_ACLK,
s_aresetn => S_AXI_ARESETN,
s_axis_tvalid => RX_VALID,
s_axis_tready => RX_READY,
s_axis_tdata => RX_DATA,
m_axis_tvalid => open,
m_axis_tready => rxif_ready,
m_axis_tdata => rxif_data,
axis_data_count => rxif_count(10 downto 0)
);
txif_count(31 downto 11) <= (others => '0');
rxif_count(31 downto 11) <= (others => '0');
end generate;
g4Ki: if USE_1K_NOT_4K_FIFO_DEPTH = false generate
tx_fifo: FIFO_32x4K
port map (
s_aclk => S_AXI_ACLK,
s_aresetn => S_AXI_ARESETN,
s_axis_tvalid => txif_valid,
s_axis_tready => open,
s_axis_tdata => txif_data,
m_axis_tvalid => tx_valid_sig,
m_axis_tready => tx_ready_sig,
m_axis_tdata => TX_DATA,
axis_data_count => txif_count(12 downto 0)
);
rx_fifo: FIFO_32x4K
port map (
s_aclk => S_AXI_ACLK,
s_aresetn => S_AXI_ARESETN,
s_axis_tvalid => RX_VALID,
s_axis_tready => RX_READY,
s_axis_tdata => RX_DATA,
m_axis_tvalid => open,
m_axis_tready => rxif_ready,
m_axis_tdata => rxif_data,
axis_data_count => rxif_count(12 downto 0)
);
txif_count(31 downto 13) <= (others => '0');
rxif_count(31 downto 13) <= (others => '0');
end generate;
-- User logic ends
end arch_imp;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/bd/sys/hdl/sys.vhd | 1 | 297432 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Apr 15 17:28:28 2017
--Host : work running 64-bit Ubuntu 16.04.2 LTS
--Command : generate_target sys.bd
--Design : sys
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1A0CMNU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1A0CMNU;
architecture STRUCTURE of m00_couplers_imp_1A0CMNU is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_XDBQKF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_XDBQKF;
architecture STRUCTURE of m01_couplers_imp_XDBQKF is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1ITCJ5D is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m02_couplers_imp_1ITCJ5D;
architecture STRUCTURE of m02_couplers_imp_1ITCJ5D is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m02_couplers_to_m02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m02_couplers_to_m02_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m02_couplers_to_m02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m02_couplers_to_m02_couplers_AWVALID(0);
M_AXI_bready(0) <= m02_couplers_to_m02_couplers_BREADY(0);
M_AXI_rready(0) <= m02_couplers_to_m02_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m02_couplers_to_m02_couplers_WVALID(0);
S_AXI_arready(0) <= m02_couplers_to_m02_couplers_ARREADY(0);
S_AXI_awready(0) <= m02_couplers_to_m02_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m02_couplers_to_m02_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m02_couplers_to_m02_couplers_RVALID(0);
S_AXI_wready(0) <= m02_couplers_to_m02_couplers_WREADY(0);
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_m02_couplers_ARREADY(0) <= M_AXI_arready(0);
m02_couplers_to_m02_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_m02_couplers_AWREADY(0) <= M_AXI_awready(0);
m02_couplers_to_m02_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m02_couplers_to_m02_couplers_BREADY(0) <= S_AXI_bready(0);
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID(0) <= M_AXI_bvalid(0);
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY(0) <= S_AXI_rready(0);
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID(0) <= M_AXI_rvalid(0);
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY(0) <= M_AXI_wready(0);
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_6OO3UC is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m03_couplers_imp_6OO3UC;
architecture STRUCTURE of m03_couplers_imp_6OO3UC is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m03_couplers_to_m03_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m03_couplers_to_m03_couplers_AWVALID(0);
M_AXI_bready(0) <= m03_couplers_to_m03_couplers_BREADY(0);
M_AXI_rready(0) <= m03_couplers_to_m03_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m03_couplers_to_m03_couplers_WVALID(0);
S_AXI_arready(0) <= m03_couplers_to_m03_couplers_ARREADY(0);
S_AXI_awready(0) <= m03_couplers_to_m03_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m03_couplers_to_m03_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m03_couplers_to_m03_couplers_RVALID(0);
S_AXI_wready(0) <= m03_couplers_to_m03_couplers_WREADY(0);
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY(0) <= M_AXI_arready(0);
m03_couplers_to_m03_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY(0) <= M_AXI_awready(0);
m03_couplers_to_m03_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m03_couplers_to_m03_couplers_BREADY(0) <= S_AXI_bready(0);
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID(0) <= M_AXI_bvalid(0);
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY(0) <= S_AXI_rready(0);
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID(0) <= M_AXI_rvalid(0);
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY(0) <= M_AXI_wready(0);
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_S51GKS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m04_couplers_imp_S51GKS;
architecture STRUCTURE of m04_couplers_imp_S51GKS is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m04_couplers_to_m04_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m04_couplers_to_m04_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m04_couplers_to_m04_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m04_couplers_to_m04_couplers_AWVALID(0);
M_AXI_bready(0) <= m04_couplers_to_m04_couplers_BREADY(0);
M_AXI_rready(0) <= m04_couplers_to_m04_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m04_couplers_to_m04_couplers_WVALID(0);
S_AXI_arready(0) <= m04_couplers_to_m04_couplers_ARREADY(0);
S_AXI_awready(0) <= m04_couplers_to_m04_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m04_couplers_to_m04_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m04_couplers_to_m04_couplers_RVALID(0);
S_AXI_wready(0) <= m04_couplers_to_m04_couplers_WREADY(0);
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m04_couplers_to_m04_couplers_ARREADY(0) <= M_AXI_arready(0);
m04_couplers_to_m04_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m04_couplers_to_m04_couplers_AWREADY(0) <= M_AXI_awready(0);
m04_couplers_to_m04_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m04_couplers_to_m04_couplers_BREADY(0) <= S_AXI_bready(0);
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID(0) <= M_AXI_bvalid(0);
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY(0) <= S_AXI_rready(0);
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID(0) <= M_AXI_rvalid(0);
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY(0) <= M_AXI_wready(0);
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_1FBTRC9 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m05_couplers_imp_1FBTRC9;
architecture STRUCTURE of m05_couplers_imp_1FBTRC9 is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m05_couplers_to_m05_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m05_couplers_to_m05_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m05_couplers_to_m05_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m05_couplers_to_m05_couplers_AWVALID(0);
M_AXI_bready(0) <= m05_couplers_to_m05_couplers_BREADY(0);
M_AXI_rready(0) <= m05_couplers_to_m05_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m05_couplers_to_m05_couplers_WVALID(0);
S_AXI_arready(0) <= m05_couplers_to_m05_couplers_ARREADY(0);
S_AXI_awready(0) <= m05_couplers_to_m05_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m05_couplers_to_m05_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m05_couplers_to_m05_couplers_RVALID(0);
S_AXI_wready(0) <= m05_couplers_to_m05_couplers_WREADY(0);
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m05_couplers_to_m05_couplers_ARREADY(0) <= M_AXI_arready(0);
m05_couplers_to_m05_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m05_couplers_to_m05_couplers_AWREADY(0) <= M_AXI_awready(0);
m05_couplers_to_m05_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m05_couplers_to_m05_couplers_BREADY(0) <= S_AXI_bready(0);
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID(0) <= M_AXI_bvalid(0);
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY(0) <= S_AXI_rready(0);
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID(0) <= M_AXI_rvalid(0);
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY(0) <= M_AXI_wready(0);
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_1G45T3 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m06_couplers_imp_1G45T3;
architecture STRUCTURE of m06_couplers_imp_1G45T3 is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m06_couplers_to_m06_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m06_couplers_to_m06_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m06_couplers_to_m06_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m06_couplers_to_m06_couplers_AWVALID(0);
M_AXI_bready(0) <= m06_couplers_to_m06_couplers_BREADY(0);
M_AXI_rready(0) <= m06_couplers_to_m06_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m06_couplers_to_m06_couplers_WVALID(0);
S_AXI_arready(0) <= m06_couplers_to_m06_couplers_ARREADY(0);
S_AXI_awready(0) <= m06_couplers_to_m06_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m06_couplers_to_m06_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m06_couplers_to_m06_couplers_RVALID(0);
S_AXI_wready(0) <= m06_couplers_to_m06_couplers_WREADY(0);
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m06_couplers_to_m06_couplers_ARREADY(0) <= M_AXI_arready(0);
m06_couplers_to_m06_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m06_couplers_to_m06_couplers_AWREADY(0) <= M_AXI_awready(0);
m06_couplers_to_m06_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m06_couplers_to_m06_couplers_BREADY(0) <= S_AXI_bready(0);
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID(0) <= M_AXI_bvalid(0);
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY(0) <= S_AXI_rready(0);
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID(0) <= M_AXI_rvalid(0);
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY(0) <= M_AXI_wready(0);
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m07_couplers_imp_1O3V2ZM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m07_couplers_imp_1O3V2ZM;
architecture STRUCTURE of m07_couplers_imp_1O3V2ZM is
signal m07_couplers_to_m07_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m07_couplers_to_m07_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m07_couplers_to_m07_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_m07_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_m07_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m07_couplers_to_m07_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m07_couplers_to_m07_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m07_couplers_to_m07_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m07_couplers_to_m07_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m07_couplers_to_m07_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m07_couplers_to_m07_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m07_couplers_to_m07_couplers_AWVALID(0);
M_AXI_bready(0) <= m07_couplers_to_m07_couplers_BREADY(0);
M_AXI_rready(0) <= m07_couplers_to_m07_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m07_couplers_to_m07_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m07_couplers_to_m07_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m07_couplers_to_m07_couplers_WVALID(0);
S_AXI_arready(0) <= m07_couplers_to_m07_couplers_ARREADY(0);
S_AXI_awready(0) <= m07_couplers_to_m07_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m07_couplers_to_m07_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m07_couplers_to_m07_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m07_couplers_to_m07_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m07_couplers_to_m07_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m07_couplers_to_m07_couplers_RVALID(0);
S_AXI_wready(0) <= m07_couplers_to_m07_couplers_WREADY(0);
m07_couplers_to_m07_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m07_couplers_to_m07_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m07_couplers_to_m07_couplers_ARREADY(0) <= M_AXI_arready(0);
m07_couplers_to_m07_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m07_couplers_to_m07_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m07_couplers_to_m07_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m07_couplers_to_m07_couplers_AWREADY(0) <= M_AXI_awready(0);
m07_couplers_to_m07_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m07_couplers_to_m07_couplers_BREADY(0) <= S_AXI_bready(0);
m07_couplers_to_m07_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m07_couplers_to_m07_couplers_BVALID(0) <= M_AXI_bvalid(0);
m07_couplers_to_m07_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m07_couplers_to_m07_couplers_RREADY(0) <= S_AXI_rready(0);
m07_couplers_to_m07_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m07_couplers_to_m07_couplers_RVALID(0) <= M_AXI_rvalid(0);
m07_couplers_to_m07_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m07_couplers_to_m07_couplers_WREADY(0) <= M_AXI_wready(0);
m07_couplers_to_m07_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m07_couplers_to_m07_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m08_couplers_imp_1YZAY8N is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m08_couplers_imp_1YZAY8N;
architecture STRUCTURE of m08_couplers_imp_1YZAY8N is
signal m08_couplers_to_m08_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m08_couplers_to_m08_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m08_couplers_to_m08_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_m08_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_m08_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m08_couplers_to_m08_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m08_couplers_to_m08_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m08_couplers_to_m08_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m08_couplers_to_m08_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m08_couplers_to_m08_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m08_couplers_to_m08_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m08_couplers_to_m08_couplers_AWVALID(0);
M_AXI_bready(0) <= m08_couplers_to_m08_couplers_BREADY(0);
M_AXI_rready(0) <= m08_couplers_to_m08_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m08_couplers_to_m08_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m08_couplers_to_m08_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m08_couplers_to_m08_couplers_WVALID(0);
S_AXI_arready(0) <= m08_couplers_to_m08_couplers_ARREADY(0);
S_AXI_awready(0) <= m08_couplers_to_m08_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m08_couplers_to_m08_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m08_couplers_to_m08_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m08_couplers_to_m08_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m08_couplers_to_m08_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m08_couplers_to_m08_couplers_RVALID(0);
S_AXI_wready(0) <= m08_couplers_to_m08_couplers_WREADY(0);
m08_couplers_to_m08_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m08_couplers_to_m08_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m08_couplers_to_m08_couplers_ARREADY(0) <= M_AXI_arready(0);
m08_couplers_to_m08_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m08_couplers_to_m08_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m08_couplers_to_m08_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m08_couplers_to_m08_couplers_AWREADY(0) <= M_AXI_awready(0);
m08_couplers_to_m08_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m08_couplers_to_m08_couplers_BREADY(0) <= S_AXI_bready(0);
m08_couplers_to_m08_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m08_couplers_to_m08_couplers_BVALID(0) <= M_AXI_bvalid(0);
m08_couplers_to_m08_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m08_couplers_to_m08_couplers_RREADY(0) <= S_AXI_rready(0);
m08_couplers_to_m08_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m08_couplers_to_m08_couplers_RVALID(0) <= M_AXI_rvalid(0);
m08_couplers_to_m08_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m08_couplers_to_m08_couplers_WREADY(0) <= M_AXI_wready(0);
m08_couplers_to_m08_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m08_couplers_to_m08_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_3JID8G is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_3JID8G;
architecture STRUCTURE of s00_couplers_imp_3JID8G is
component sys_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component sys_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component sys_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sys_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M04_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M04_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M05_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M05_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M06_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M06_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_ACLK : in STD_LOGIC;
M07_ARESETN : in STD_LOGIC;
M07_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M07_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M07_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M07_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M07_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M07_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_ACLK : in STD_LOGIC;
M08_ARESETN : in STD_LOGIC;
M08_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M08_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M08_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M08_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M08_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M08_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end sys_processing_system7_0_axi_periph_0;
architecture STRUCTURE of sys_processing_system7_0_axi_periph_0 is
component sys_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 287 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 26 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 287 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 287 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 26 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 287 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 8 downto 0 )
);
end component sys_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC;
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC;
signal M07_ACLK_1 : STD_LOGIC;
signal M07_ARESETN_1 : STD_LOGIC;
signal M08_ACLK_1 : STD_LOGIC;
signal M08_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m07_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m08_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARPROT : STD_LOGIC_VECTOR ( 17 downto 15 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWPROT : STD_LOGIC_VECTOR ( 17 downto 15 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARPROT : STD_LOGIC_VECTOR ( 20 downto 18 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWPROT : STD_LOGIC_VECTOR ( 20 downto 18 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m07_couplers_ARADDR : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_ARPROT : STD_LOGIC_VECTOR ( 23 downto 21 );
signal xbar_to_m07_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_ARVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_AWADDR : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_AWPROT : STD_LOGIC_VECTOR ( 23 downto 21 );
signal xbar_to_m07_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_AWVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_BREADY : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m07_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m07_couplers_RREADY : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m07_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_WDATA : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_WSTRB : STD_LOGIC_VECTOR ( 31 downto 28 );
signal xbar_to_m07_couplers_WVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m08_couplers_ARADDR : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_ARPROT : STD_LOGIC_VECTOR ( 26 downto 24 );
signal xbar_to_m08_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_ARVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_AWADDR : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_AWPROT : STD_LOGIC_VECTOR ( 26 downto 24 );
signal xbar_to_m08_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_AWVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_BREADY : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m08_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m08_couplers_RREADY : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m08_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_WDATA : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_WSTRB : STD_LOGIC_VECTOR ( 35 downto 32 );
signal xbar_to_m08_couplers_WVALID : STD_LOGIC_VECTOR ( 8 to 8 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arprot(2 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M02_AXI_arvalid(0) <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awprot(2 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M02_AXI_awvalid(0) <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M02_AXI_bready(0) <= m02_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M02_AXI_rready(0) <= m02_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid(0) <= m02_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M03_AXI_arvalid(0) <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M03_AXI_awvalid(0) <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M03_AXI_bready(0) <= m03_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M03_AXI_rready(0) <= m03_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid(0) <= m03_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arprot(2 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M04_AXI_arvalid(0) <= m04_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awprot(2 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M04_AXI_awvalid(0) <= m04_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M04_AXI_bready(0) <= m04_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M04_AXI_rready(0) <= m04_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid(0) <= m04_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1 <= M05_ARESETN;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arprot(2 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M05_AXI_arvalid(0) <= m05_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awprot(2 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M05_AXI_awvalid(0) <= m05_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M05_AXI_bready(0) <= m05_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M05_AXI_rready(0) <= m05_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid(0) <= m05_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1 <= M06_ARESETN;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M06_AXI_arprot(2 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M06_AXI_arvalid(0) <= m06_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M06_AXI_awprot(2 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M06_AXI_awvalid(0) <= m06_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M06_AXI_bready(0) <= m06_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M06_AXI_rready(0) <= m06_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M06_AXI_wvalid(0) <= m06_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M07_ACLK_1 <= M07_ACLK;
M07_ARESETN_1 <= M07_ARESETN;
M07_AXI_araddr(31 downto 0) <= m07_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M07_AXI_arprot(2 downto 0) <= m07_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M07_AXI_arvalid(0) <= m07_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M07_AXI_awaddr(31 downto 0) <= m07_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M07_AXI_awprot(2 downto 0) <= m07_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M07_AXI_awvalid(0) <= m07_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M07_AXI_bready(0) <= m07_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M07_AXI_rready(0) <= m07_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M07_AXI_wdata(31 downto 0) <= m07_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M07_AXI_wstrb(3 downto 0) <= m07_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M07_AXI_wvalid(0) <= m07_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M08_ACLK_1 <= M08_ACLK;
M08_ARESETN_1 <= M08_ARESETN;
M08_AXI_araddr(31 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M08_AXI_arprot(2 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M08_AXI_arvalid(0) <= m08_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M08_AXI_awaddr(31 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M08_AXI_awprot(2 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M08_AXI_awvalid(0) <= m08_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M08_AXI_bready(0) <= m08_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M08_AXI_rready(0) <= m08_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M08_AXI_wdata(31 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M08_AXI_wstrb(3 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M08_AXI_wvalid(0) <= m08_couplers_to_processing_system7_0_axi_periph_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M02_AXI_arready(0);
m02_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M02_AXI_awready(0);
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M02_AXI_bvalid(0);
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M02_AXI_rvalid(0);
m02_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M02_AXI_wready(0);
m03_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M03_AXI_arready(0);
m03_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M03_AXI_awready(0);
m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M03_AXI_bvalid(0);
m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M03_AXI_rvalid(0);
m03_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M03_AXI_wready(0);
m04_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M04_AXI_arready(0);
m04_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M04_AXI_awready(0);
m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M04_AXI_bvalid(0);
m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M04_AXI_rvalid(0);
m04_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M04_AXI_wready(0);
m05_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M05_AXI_arready(0);
m05_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M05_AXI_awready(0);
m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M05_AXI_bvalid(0);
m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M05_AXI_rvalid(0);
m05_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M05_AXI_wready(0);
m06_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M06_AXI_arready(0);
m06_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M06_AXI_awready(0);
m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M06_AXI_bvalid(0);
m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M06_AXI_rvalid(0);
m06_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M06_AXI_wready(0);
m07_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M07_AXI_arready(0);
m07_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M07_AXI_awready(0);
m07_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M07_AXI_bresp(1 downto 0);
m07_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M07_AXI_bvalid(0);
m07_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M07_AXI_rdata(31 downto 0);
m07_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M07_AXI_rresp(1 downto 0);
m07_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M07_AXI_rvalid(0);
m07_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M07_AXI_wready(0);
m08_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M08_AXI_arready(0);
m08_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M08_AXI_awready(0);
m08_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M08_AXI_bresp(1 downto 0);
m08_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M08_AXI_bvalid(0);
m08_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M08_AXI_rdata(31 downto 0);
m08_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M08_AXI_rresp(1 downto 0);
m08_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M08_AXI_rvalid(0);
m08_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M08_AXI_wready(0);
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net <= ARESETN;
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_1A0CMNU
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_XDBQKF
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1ITCJ5D
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m02_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m02_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m02_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m02_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m02_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m02_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m02_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m02_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m02_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m02_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arready(0) => xbar_to_m02_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awready(0) => xbar_to_m02_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready(0) => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m02_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m02_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready(0) => xbar_to_m02_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid(0) => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_6OO3UC
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m03_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m03_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m03_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m03_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m03_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m03_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m03_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m03_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m03_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m03_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready(0) => xbar_to_m03_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready(0) => xbar_to_m03_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready(0) => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m03_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m03_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready(0) => xbar_to_m03_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid(0) => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_S51GKS
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m04_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m04_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m04_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m04_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m04_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m04_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m04_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m04_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m04_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m04_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arprot(2 downto 0) => xbar_to_m04_couplers_ARPROT(14 downto 12),
S_AXI_arready(0) => xbar_to_m04_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awprot(2 downto 0) => xbar_to_m04_couplers_AWPROT(14 downto 12),
S_AXI_awready(0) => xbar_to_m04_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready(0) => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m04_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m04_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready(0) => xbar_to_m04_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid(0) => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_1FBTRC9
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN => M05_ARESETN_1,
M_AXI_araddr(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m05_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m05_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m05_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m05_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m05_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m05_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m05_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m05_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m05_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m05_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arprot(2 downto 0) => xbar_to_m05_couplers_ARPROT(17 downto 15),
S_AXI_arready(0) => xbar_to_m05_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awprot(2 downto 0) => xbar_to_m05_couplers_AWPROT(17 downto 15),
S_AXI_awready(0) => xbar_to_m05_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready(0) => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m05_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m05_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready(0) => xbar_to_m05_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid(0) => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_1G45T3
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN => M06_ARESETN_1,
M_AXI_araddr(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m06_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m06_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m06_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m06_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m06_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m06_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m06_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m06_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m06_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m06_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arprot(2 downto 0) => xbar_to_m06_couplers_ARPROT(20 downto 18),
S_AXI_arready(0) => xbar_to_m06_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awprot(2 downto 0) => xbar_to_m06_couplers_AWPROT(20 downto 18),
S_AXI_awready(0) => xbar_to_m06_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready(0) => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m06_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m06_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready(0) => xbar_to_m06_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid(0) => xbar_to_m06_couplers_WVALID(6)
);
m07_couplers: entity work.m07_couplers_imp_1O3V2ZM
port map (
M_ACLK => M07_ACLK_1,
M_ARESETN => M07_ARESETN_1,
M_AXI_araddr(31 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m07_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m07_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m07_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m07_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m07_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m07_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m07_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m07_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m07_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m07_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m07_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m07_couplers_ARADDR(255 downto 224),
S_AXI_arprot(2 downto 0) => xbar_to_m07_couplers_ARPROT(23 downto 21),
S_AXI_arready(0) => xbar_to_m07_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m07_couplers_ARVALID(7),
S_AXI_awaddr(31 downto 0) => xbar_to_m07_couplers_AWADDR(255 downto 224),
S_AXI_awprot(2 downto 0) => xbar_to_m07_couplers_AWPROT(23 downto 21),
S_AXI_awready(0) => xbar_to_m07_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m07_couplers_AWVALID(7),
S_AXI_bready(0) => xbar_to_m07_couplers_BREADY(7),
S_AXI_bresp(1 downto 0) => xbar_to_m07_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m07_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m07_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m07_couplers_RREADY(7),
S_AXI_rresp(1 downto 0) => xbar_to_m07_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m07_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m07_couplers_WDATA(255 downto 224),
S_AXI_wready(0) => xbar_to_m07_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m07_couplers_WSTRB(31 downto 28),
S_AXI_wvalid(0) => xbar_to_m07_couplers_WVALID(7)
);
m08_couplers: entity work.m08_couplers_imp_1YZAY8N
port map (
M_ACLK => M08_ACLK_1,
M_ARESETN => M08_ARESETN_1,
M_AXI_araddr(31 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m08_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m08_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m08_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m08_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m08_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m08_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m08_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m08_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m08_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m08_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m08_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m08_couplers_ARADDR(287 downto 256),
S_AXI_arprot(2 downto 0) => xbar_to_m08_couplers_ARPROT(26 downto 24),
S_AXI_arready(0) => xbar_to_m08_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m08_couplers_ARVALID(8),
S_AXI_awaddr(31 downto 0) => xbar_to_m08_couplers_AWADDR(287 downto 256),
S_AXI_awprot(2 downto 0) => xbar_to_m08_couplers_AWPROT(26 downto 24),
S_AXI_awready(0) => xbar_to_m08_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m08_couplers_AWVALID(8),
S_AXI_bready(0) => xbar_to_m08_couplers_BREADY(8),
S_AXI_bresp(1 downto 0) => xbar_to_m08_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m08_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m08_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m08_couplers_RREADY(8),
S_AXI_rresp(1 downto 0) => xbar_to_m08_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m08_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m08_couplers_WDATA(287 downto 256),
S_AXI_wready(0) => xbar_to_m08_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m08_couplers_WSTRB(35 downto 32),
S_AXI_wvalid(0) => xbar_to_m08_couplers_WVALID(8)
);
s00_couplers: entity work.s00_couplers_imp_3JID8G
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN => processing_system7_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component sys_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net,
m_axi_araddr(287 downto 256) => xbar_to_m08_couplers_ARADDR(287 downto 256),
m_axi_araddr(255 downto 224) => xbar_to_m07_couplers_ARADDR(255 downto 224),
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(26 downto 24) => xbar_to_m08_couplers_ARPROT(26 downto 24),
m_axi_arprot(23 downto 21) => xbar_to_m07_couplers_ARPROT(23 downto 21),
m_axi_arprot(20 downto 18) => xbar_to_m06_couplers_ARPROT(20 downto 18),
m_axi_arprot(17 downto 15) => xbar_to_m05_couplers_ARPROT(17 downto 15),
m_axi_arprot(14 downto 12) => xbar_to_m04_couplers_ARPROT(14 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(8) => xbar_to_m08_couplers_ARREADY(0),
m_axi_arready(7) => xbar_to_m07_couplers_ARREADY(0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY(0),
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY(0),
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY(0),
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY(0),
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY(0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(8) => xbar_to_m08_couplers_ARVALID(8),
m_axi_arvalid(7) => xbar_to_m07_couplers_ARVALID(7),
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(287 downto 256) => xbar_to_m08_couplers_AWADDR(287 downto 256),
m_axi_awaddr(255 downto 224) => xbar_to_m07_couplers_AWADDR(255 downto 224),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(26 downto 24) => xbar_to_m08_couplers_AWPROT(26 downto 24),
m_axi_awprot(23 downto 21) => xbar_to_m07_couplers_AWPROT(23 downto 21),
m_axi_awprot(20 downto 18) => xbar_to_m06_couplers_AWPROT(20 downto 18),
m_axi_awprot(17 downto 15) => xbar_to_m05_couplers_AWPROT(17 downto 15),
m_axi_awprot(14 downto 12) => xbar_to_m04_couplers_AWPROT(14 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(8) => xbar_to_m08_couplers_AWREADY(0),
m_axi_awready(7) => xbar_to_m07_couplers_AWREADY(0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY(0),
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY(0),
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY(0),
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY(0),
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY(0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(8) => xbar_to_m08_couplers_AWVALID(8),
m_axi_awvalid(7) => xbar_to_m07_couplers_AWVALID(7),
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(8) => xbar_to_m08_couplers_BREADY(8),
m_axi_bready(7) => xbar_to_m07_couplers_BREADY(7),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(17 downto 16) => xbar_to_m08_couplers_BRESP(1 downto 0),
m_axi_bresp(15 downto 14) => xbar_to_m07_couplers_BRESP(1 downto 0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(8) => xbar_to_m08_couplers_BVALID(0),
m_axi_bvalid(7) => xbar_to_m07_couplers_BVALID(0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID(0),
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID(0),
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID(0),
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID(0),
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID(0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(287 downto 256) => xbar_to_m08_couplers_RDATA(31 downto 0),
m_axi_rdata(255 downto 224) => xbar_to_m07_couplers_RDATA(31 downto 0),
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(8) => xbar_to_m08_couplers_RREADY(8),
m_axi_rready(7) => xbar_to_m07_couplers_RREADY(7),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(17 downto 16) => xbar_to_m08_couplers_RRESP(1 downto 0),
m_axi_rresp(15 downto 14) => xbar_to_m07_couplers_RRESP(1 downto 0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(8) => xbar_to_m08_couplers_RVALID(0),
m_axi_rvalid(7) => xbar_to_m07_couplers_RVALID(0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID(0),
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID(0),
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID(0),
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID(0),
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID(0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(287 downto 256) => xbar_to_m08_couplers_WDATA(287 downto 256),
m_axi_wdata(255 downto 224) => xbar_to_m07_couplers_WDATA(255 downto 224),
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(8) => xbar_to_m08_couplers_WREADY(0),
m_axi_wready(7) => xbar_to_m07_couplers_WREADY(0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY(0),
m_axi_wready(5) => xbar_to_m05_couplers_WREADY(0),
m_axi_wready(4) => xbar_to_m04_couplers_WREADY(0),
m_axi_wready(3) => xbar_to_m03_couplers_WREADY(0),
m_axi_wready(2) => xbar_to_m02_couplers_WREADY(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(35 downto 32) => xbar_to_m08_couplers_WSTRB(35 downto 32),
m_axi_wstrb(31 downto 28) => xbar_to_m07_couplers_WSTRB(31 downto 28),
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(8) => xbar_to_m08_couplers_WVALID(8),
m_axi_wvalid(7) => xbar_to_m07_couplers_WVALID(7),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sys is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of sys : entity is "sys,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=sys,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=33,numReposBlks=22,numNonXlnxBlks=18,numHierBlks=11,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=9,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of sys : entity is "sys.hwdef";
end sys;
architecture STRUCTURE of sys is
component sys_axi_nic_00_0 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_00_0;
component sys_axi_nic_00_1 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_00_1;
component sys_axi_nic_00_2 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_00_2;
component sys_axi_nic_0_0 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_0_0;
component sys_axi_nic_10_0 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_10_0;
component sys_axi_nic_10_1 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_10_1;
component sys_axi_nic_10_2 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_10_2;
component sys_axi_nic_20_0 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_20_0;
component sys_axi_nic_20_1 is
port (
RX_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
RX_VALID : in STD_LOGIC;
RX_READY : out STD_LOGIC;
TX_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
TX_VALID : out STD_LOGIC;
TX_READY : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component sys_axi_nic_20_1;
component sys_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component sys_processing_system7_0_0;
component sys_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component sys_rst_processing_system7_0_100M_0;
component sys_router_00_0 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
N_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
N_VIN : in STD_LOGIC;
N_RIN : out STD_LOGIC;
N_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
N_VOUT : out STD_LOGIC;
N_ROUT : in STD_LOGIC;
E_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
E_VIN : in STD_LOGIC;
E_RIN : out STD_LOGIC;
E_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
E_VOUT : out STD_LOGIC;
E_ROUT : in STD_LOGIC;
W_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
W_VIN : in STD_LOGIC;
W_RIN : out STD_LOGIC;
W_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
W_VOUT : out STD_LOGIC;
W_ROUT : in STD_LOGIC
);
end component sys_router_00_0;
component sys_router_0_0 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
N_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
N_VIN : in STD_LOGIC;
N_RIN : out STD_LOGIC;
N_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
N_VOUT : out STD_LOGIC;
N_ROUT : in STD_LOGIC;
E_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
E_VIN : in STD_LOGIC;
E_RIN : out STD_LOGIC;
E_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
E_VOUT : out STD_LOGIC;
E_ROUT : in STD_LOGIC
);
end component sys_router_0_0;
component sys_router_0_1 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
N_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
N_VIN : in STD_LOGIC;
N_RIN : out STD_LOGIC;
N_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
N_VOUT : out STD_LOGIC;
N_ROUT : in STD_LOGIC;
S_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_VIN : in STD_LOGIC;
S_RIN : out STD_LOGIC;
S_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_VOUT : out STD_LOGIC;
S_ROUT : in STD_LOGIC;
E_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
E_VIN : in STD_LOGIC;
E_RIN : out STD_LOGIC;
E_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
E_VOUT : out STD_LOGIC;
E_ROUT : in STD_LOGIC
);
end component sys_router_0_1;
component sys_router_0_2 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
S_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_VIN : in STD_LOGIC;
S_RIN : out STD_LOGIC;
S_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_VOUT : out STD_LOGIC;
S_ROUT : in STD_LOGIC;
E_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
E_VIN : in STD_LOGIC;
E_RIN : out STD_LOGIC;
E_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
E_VOUT : out STD_LOGIC;
E_ROUT : in STD_LOGIC
);
end component sys_router_0_2;
component sys_router_10_0 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
N_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
N_VIN : in STD_LOGIC;
N_RIN : out STD_LOGIC;
N_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
N_VOUT : out STD_LOGIC;
N_ROUT : in STD_LOGIC;
S_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_VIN : in STD_LOGIC;
S_RIN : out STD_LOGIC;
S_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_VOUT : out STD_LOGIC;
S_ROUT : in STD_LOGIC;
E_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
E_VIN : in STD_LOGIC;
E_RIN : out STD_LOGIC;
E_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
E_VOUT : out STD_LOGIC;
E_ROUT : in STD_LOGIC;
W_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
W_VIN : in STD_LOGIC;
W_RIN : out STD_LOGIC;
W_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
W_VOUT : out STD_LOGIC;
W_ROUT : in STD_LOGIC
);
end component sys_router_10_0;
component sys_router_10_1 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
S_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_VIN : in STD_LOGIC;
S_RIN : out STD_LOGIC;
S_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_VOUT : out STD_LOGIC;
S_ROUT : in STD_LOGIC;
E_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
E_VIN : in STD_LOGIC;
E_RIN : out STD_LOGIC;
E_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
E_VOUT : out STD_LOGIC;
E_ROUT : in STD_LOGIC;
W_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
W_VIN : in STD_LOGIC;
W_RIN : out STD_LOGIC;
W_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
W_VOUT : out STD_LOGIC;
W_ROUT : in STD_LOGIC
);
end component sys_router_10_1;
component sys_router_10_2 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
N_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
N_VIN : in STD_LOGIC;
N_RIN : out STD_LOGIC;
N_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
N_VOUT : out STD_LOGIC;
N_ROUT : in STD_LOGIC;
W_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
W_VIN : in STD_LOGIC;
W_RIN : out STD_LOGIC;
W_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
W_VOUT : out STD_LOGIC;
W_ROUT : in STD_LOGIC
);
end component sys_router_10_2;
component sys_router_20_0 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
N_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
N_VIN : in STD_LOGIC;
N_RIN : out STD_LOGIC;
N_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
N_VOUT : out STD_LOGIC;
N_ROUT : in STD_LOGIC;
S_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_VIN : in STD_LOGIC;
S_RIN : out STD_LOGIC;
S_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_VOUT : out STD_LOGIC;
S_ROUT : in STD_LOGIC;
W_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
W_VIN : in STD_LOGIC;
W_RIN : out STD_LOGIC;
W_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
W_VOUT : out STD_LOGIC;
W_ROUT : in STD_LOGIC
);
end component sys_router_20_0;
component sys_router_20_1 is
port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
L_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
L_VIN : in STD_LOGIC;
L_RIN : out STD_LOGIC;
L_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
L_VOUT : out STD_LOGIC;
L_ROUT : in STD_LOGIC;
S_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_VIN : in STD_LOGIC;
S_RIN : out STD_LOGIC;
S_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_VOUT : out STD_LOGIC;
S_ROUT : in STD_LOGIC;
W_DIN : in STD_LOGIC_VECTOR ( 31 downto 0 );
W_VIN : in STD_LOGIC;
W_RIN : out STD_LOGIC;
W_DOUT : out STD_LOGIC_VECTOR ( 31 downto 0 );
W_VOUT : out STD_LOGIC;
W_ROUT : in STD_LOGIC
);
end component sys_router_20_1;
signal axi_nic_00_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_00_TX_TREADY : STD_LOGIC;
signal axi_nic_00_TX_TVALID : STD_LOGIC;
signal axi_nic_01_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_01_TX_TREADY : STD_LOGIC;
signal axi_nic_01_TX_TVALID : STD_LOGIC;
signal axi_nic_02_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_02_TX_TREADY : STD_LOGIC;
signal axi_nic_02_TX_TVALID : STD_LOGIC;
signal axi_nic_10_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_10_TX_TREADY : STD_LOGIC;
signal axi_nic_10_TX_TVALID : STD_LOGIC;
signal axi_nic_11_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_11_TX_TREADY : STD_LOGIC;
signal axi_nic_11_TX_TVALID : STD_LOGIC;
signal axi_nic_12_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_12_TX_TREADY : STD_LOGIC;
signal axi_nic_12_TX_TVALID : STD_LOGIC;
signal axi_nic_20_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_20_TX_TREADY : STD_LOGIC;
signal axi_nic_20_TX_TVALID : STD_LOGIC;
signal axi_nic_21_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_21_TX_TREADY : STD_LOGIC;
signal axi_nic_21_TX_TVALID : STD_LOGIC;
signal axi_nic_22_TX_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_nic_22_TX_TREADY : STD_LOGIC;
signal axi_nic_22_TX_TVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M05_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M06_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M07_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M07_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M07_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M07_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M07_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M07_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M07_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M07_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M07_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M07_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M07_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M08_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M08_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M08_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M08_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M08_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M08_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M08_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M08_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M08_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M08_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M08_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal router_00_E_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_00_E_OUT_TREADY : STD_LOGIC;
signal router_00_E_OUT_TVALID : STD_LOGIC;
signal router_00_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_00_L_OUT_TREADY : STD_LOGIC;
signal router_00_L_OUT_TVALID : STD_LOGIC;
signal router_00_N_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_00_N_OUT_TREADY : STD_LOGIC;
signal router_00_N_OUT_TVALID : STD_LOGIC;
signal router_01_E_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_01_E_OUT_TREADY : STD_LOGIC;
signal router_01_E_OUT_TVALID : STD_LOGIC;
signal router_01_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_01_L_OUT_TREADY : STD_LOGIC;
signal router_01_L_OUT_TVALID : STD_LOGIC;
signal router_01_N_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_01_N_OUT_TREADY : STD_LOGIC;
signal router_01_N_OUT_TVALID : STD_LOGIC;
signal router_01_S_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_01_S_OUT_TREADY : STD_LOGIC;
signal router_01_S_OUT_TVALID : STD_LOGIC;
signal router_02_E_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_02_E_OUT_TREADY : STD_LOGIC;
signal router_02_E_OUT_TVALID : STD_LOGIC;
signal router_02_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_02_L_OUT_TREADY : STD_LOGIC;
signal router_02_L_OUT_TVALID : STD_LOGIC;
signal router_02_S_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_02_S_OUT_TREADY : STD_LOGIC;
signal router_02_S_OUT_TVALID : STD_LOGIC;
signal router_10_E_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_10_E_OUT_TREADY : STD_LOGIC;
signal router_10_E_OUT_TVALID : STD_LOGIC;
signal router_10_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_10_L_OUT_TREADY : STD_LOGIC;
signal router_10_L_OUT_TVALID : STD_LOGIC;
signal router_10_N_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_10_N_OUT_TREADY : STD_LOGIC;
signal router_10_N_OUT_TVALID : STD_LOGIC;
signal router_10_W_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_10_W_OUT_TREADY : STD_LOGIC;
signal router_10_W_OUT_TVALID : STD_LOGIC;
signal router_11_E_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_11_E_OUT_TREADY : STD_LOGIC;
signal router_11_E_OUT_TVALID : STD_LOGIC;
signal router_11_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_11_L_OUT_TREADY : STD_LOGIC;
signal router_11_L_OUT_TVALID : STD_LOGIC;
signal router_11_N_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_11_N_OUT_TREADY : STD_LOGIC;
signal router_11_N_OUT_TVALID : STD_LOGIC;
signal router_11_S_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_11_S_OUT_TREADY : STD_LOGIC;
signal router_11_S_OUT_TVALID : STD_LOGIC;
signal router_11_W_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_11_W_OUT_TREADY : STD_LOGIC;
signal router_11_W_OUT_TVALID : STD_LOGIC;
signal router_12_E_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_12_E_OUT_TREADY : STD_LOGIC;
signal router_12_E_OUT_TVALID : STD_LOGIC;
signal router_12_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_12_L_OUT_TREADY : STD_LOGIC;
signal router_12_L_OUT_TVALID : STD_LOGIC;
signal router_12_S_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_12_S_OUT_TREADY : STD_LOGIC;
signal router_12_S_OUT_TVALID : STD_LOGIC;
signal router_12_W_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_12_W_OUT_TREADY : STD_LOGIC;
signal router_12_W_OUT_TVALID : STD_LOGIC;
signal router_20_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_20_L_OUT_TREADY : STD_LOGIC;
signal router_20_L_OUT_TVALID : STD_LOGIC;
signal router_20_N_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_20_N_OUT_TREADY : STD_LOGIC;
signal router_20_N_OUT_TVALID : STD_LOGIC;
signal router_20_W_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_20_W_OUT_TREADY : STD_LOGIC;
signal router_20_W_OUT_TVALID : STD_LOGIC;
signal router_21_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_21_L_OUT_TREADY : STD_LOGIC;
signal router_21_L_OUT_TVALID : STD_LOGIC;
signal router_21_N_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_21_N_OUT_TREADY : STD_LOGIC;
signal router_21_N_OUT_TVALID : STD_LOGIC;
signal router_21_S_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_21_S_OUT_TREADY : STD_LOGIC;
signal router_21_S_OUT_TVALID : STD_LOGIC;
signal router_21_W_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_21_W_OUT_TREADY : STD_LOGIC;
signal router_21_W_OUT_TVALID : STD_LOGIC;
signal router_22_L_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_22_L_OUT_TREADY : STD_LOGIC;
signal router_22_L_OUT_TVALID : STD_LOGIC;
signal router_22_S_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_22_S_OUT_TREADY : STD_LOGIC;
signal router_22_S_OUT_TVALID : STD_LOGIC;
signal router_22_W_OUT_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal router_22_W_OUT_TREADY : STD_LOGIC;
signal router_22_W_OUT_TVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_nic_00: component sys_axi_nic_0_0
port map (
RX_DATA(31 downto 0) => router_00_L_OUT_TDATA(31 downto 0),
RX_READY => router_00_L_OUT_TREADY,
RX_VALID => router_00_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_00_TX_TDATA(31 downto 0),
TX_READY => axi_nic_00_TX_TREADY,
TX_VALID => axi_nic_00_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_nic_01: component sys_axi_nic_00_1
port map (
RX_DATA(31 downto 0) => router_01_L_OUT_TDATA(31 downto 0),
RX_READY => router_01_L_OUT_TREADY,
RX_VALID => router_01_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_01_TX_TDATA(31 downto 0),
TX_READY => axi_nic_01_TX_TREADY,
TX_VALID => axi_nic_01_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0)
);
axi_nic_02: component sys_axi_nic_00_0
port map (
RX_DATA(31 downto 0) => router_02_L_OUT_TDATA(31 downto 0),
RX_READY => router_02_L_OUT_TREADY,
RX_VALID => router_02_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_02_TX_TDATA(31 downto 0),
TX_READY => axi_nic_02_TX_TREADY,
TX_VALID => axi_nic_02_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M02_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M02_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID(0)
);
axi_nic_10: component sys_axi_nic_00_2
port map (
RX_DATA(31 downto 0) => router_10_L_OUT_TDATA(31 downto 0),
RX_READY => router_10_L_OUT_TREADY,
RX_VALID => router_10_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_10_TX_TDATA(31 downto 0),
TX_READY => axi_nic_10_TX_TREADY,
TX_VALID => axi_nic_10_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M03_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M03_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID(0)
);
axi_nic_11: component sys_axi_nic_10_0
port map (
RX_DATA(31 downto 0) => router_11_L_OUT_TDATA(31 downto 0),
RX_READY => router_11_L_OUT_TREADY,
RX_VALID => router_11_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_11_TX_TDATA(31 downto 0),
TX_READY => axi_nic_11_TX_TREADY,
TX_VALID => axi_nic_11_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M04_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M04_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID(0)
);
axi_nic_12: component sys_axi_nic_10_1
port map (
RX_DATA(31 downto 0) => router_12_L_OUT_TDATA(31 downto 0),
RX_READY => router_12_L_OUT_TREADY,
RX_VALID => router_12_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_12_TX_TDATA(31 downto 0),
TX_READY => axi_nic_12_TX_TREADY,
TX_VALID => axi_nic_12_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M05_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M05_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID(0)
);
axi_nic_20: component sys_axi_nic_10_2
port map (
RX_DATA(31 downto 0) => router_20_L_OUT_TDATA(31 downto 0),
RX_READY => router_20_L_OUT_TREADY,
RX_VALID => router_20_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_20_TX_TDATA(31 downto 0),
TX_READY => axi_nic_20_TX_TREADY,
TX_VALID => axi_nic_20_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M06_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M06_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID(0)
);
axi_nic_21: component sys_axi_nic_20_0
port map (
RX_DATA(31 downto 0) => router_21_L_OUT_TDATA(31 downto 0),
RX_READY => router_21_L_OUT_TREADY,
RX_VALID => router_21_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_21_TX_TDATA(31 downto 0),
TX_READY => axi_nic_21_TX_TREADY,
TX_VALID => axi_nic_21_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M07_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M07_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M07_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M07_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M07_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M07_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M07_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M07_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M07_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M07_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M07_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M07_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M07_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M07_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M07_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M07_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M07_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M07_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M07_AXI_WVALID(0)
);
axi_nic_22: component sys_axi_nic_20_1
port map (
RX_DATA(31 downto 0) => router_22_L_OUT_TDATA(31 downto 0),
RX_READY => router_22_L_OUT_TREADY,
RX_VALID => router_22_L_OUT_TVALID,
TX_DATA(31 downto 0) => axi_nic_22_TX_TDATA(31 downto 0),
TX_READY => axi_nic_22_TX_TREADY,
TX_VALID => axi_nic_22_TX_TVALID,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(4 downto 0) => processing_system7_0_axi_periph_M08_AXI_ARADDR(4 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M08_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M08_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M08_AXI_ARVALID(0),
s00_axi_awaddr(4 downto 0) => processing_system7_0_axi_periph_M08_AXI_AWADDR(4 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M08_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M08_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M08_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M08_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M08_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M08_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M08_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M08_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M08_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M08_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M08_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M08_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M08_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M08_AXI_WVALID(0)
);
processing_system7_0: component sys_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.sys_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARPROT(2 downto 0),
M02_AXI_arready(0) => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid(0) => processing_system7_0_axi_periph_M02_AXI_ARVALID(0),
M02_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWPROT(2 downto 0),
M02_AXI_awready(0) => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid(0) => processing_system7_0_axi_periph_M02_AXI_AWVALID(0),
M02_AXI_bready(0) => processing_system7_0_axi_periph_M02_AXI_BREADY(0),
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid(0) => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready(0) => processing_system7_0_axi_periph_M02_AXI_RREADY(0),
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid(0) => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready(0) => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid(0) => processing_system7_0_axi_periph_M02_AXI_WVALID(0),
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready(0) => processing_system7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid(0) => processing_system7_0_axi_periph_M03_AXI_ARVALID(0),
M03_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready(0) => processing_system7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid(0) => processing_system7_0_axi_periph_M03_AXI_AWVALID(0),
M03_AXI_bready(0) => processing_system7_0_axi_periph_M03_AXI_BREADY(0),
M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid(0) => processing_system7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready(0) => processing_system7_0_axi_periph_M03_AXI_RREADY(0),
M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid(0) => processing_system7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready(0) => processing_system7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid(0) => processing_system7_0_axi_periph_M03_AXI_WVALID(0),
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARPROT(2 downto 0),
M04_AXI_arready(0) => processing_system7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid(0) => processing_system7_0_axi_periph_M04_AXI_ARVALID(0),
M04_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWPROT(2 downto 0),
M04_AXI_awready(0) => processing_system7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid(0) => processing_system7_0_axi_periph_M04_AXI_AWVALID(0),
M04_AXI_bready(0) => processing_system7_0_axi_periph_M04_AXI_BREADY(0),
M04_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid(0) => processing_system7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready(0) => processing_system7_0_axi_periph_M04_AXI_RREADY(0),
M04_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid(0) => processing_system7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready(0) => processing_system7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid(0) => processing_system7_0_axi_periph_M04_AXI_WVALID(0),
M05_ACLK => processing_system7_0_FCLK_CLK0,
M05_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARPROT(2 downto 0),
M05_AXI_arready(0) => processing_system7_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid(0) => processing_system7_0_axi_periph_M05_AXI_ARVALID(0),
M05_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWPROT(2 downto 0),
M05_AXI_awready(0) => processing_system7_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid(0) => processing_system7_0_axi_periph_M05_AXI_AWVALID(0),
M05_AXI_bready(0) => processing_system7_0_axi_periph_M05_AXI_BREADY(0),
M05_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid(0) => processing_system7_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready(0) => processing_system7_0_axi_periph_M05_AXI_RREADY(0),
M05_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid(0) => processing_system7_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready(0) => processing_system7_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid(0) => processing_system7_0_axi_periph_M05_AXI_WVALID(0),
M06_ACLK => processing_system7_0_FCLK_CLK0,
M06_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M06_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARPROT(2 downto 0),
M06_AXI_arready(0) => processing_system7_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid(0) => processing_system7_0_axi_periph_M06_AXI_ARVALID(0),
M06_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWPROT(2 downto 0),
M06_AXI_awready(0) => processing_system7_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid(0) => processing_system7_0_axi_periph_M06_AXI_AWVALID(0),
M06_AXI_bready(0) => processing_system7_0_axi_periph_M06_AXI_BREADY(0),
M06_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid(0) => processing_system7_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready(0) => processing_system7_0_axi_periph_M06_AXI_RREADY(0),
M06_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid(0) => processing_system7_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready(0) => processing_system7_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid(0) => processing_system7_0_axi_periph_M06_AXI_WVALID(0),
M07_ACLK => processing_system7_0_FCLK_CLK0,
M07_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M07_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M07_AXI_ARADDR(31 downto 0),
M07_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M07_AXI_ARPROT(2 downto 0),
M07_AXI_arready(0) => processing_system7_0_axi_periph_M07_AXI_ARREADY,
M07_AXI_arvalid(0) => processing_system7_0_axi_periph_M07_AXI_ARVALID(0),
M07_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M07_AXI_AWADDR(31 downto 0),
M07_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M07_AXI_AWPROT(2 downto 0),
M07_AXI_awready(0) => processing_system7_0_axi_periph_M07_AXI_AWREADY,
M07_AXI_awvalid(0) => processing_system7_0_axi_periph_M07_AXI_AWVALID(0),
M07_AXI_bready(0) => processing_system7_0_axi_periph_M07_AXI_BREADY(0),
M07_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M07_AXI_BRESP(1 downto 0),
M07_AXI_bvalid(0) => processing_system7_0_axi_periph_M07_AXI_BVALID,
M07_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M07_AXI_RDATA(31 downto 0),
M07_AXI_rready(0) => processing_system7_0_axi_periph_M07_AXI_RREADY(0),
M07_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M07_AXI_RRESP(1 downto 0),
M07_AXI_rvalid(0) => processing_system7_0_axi_periph_M07_AXI_RVALID,
M07_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M07_AXI_WDATA(31 downto 0),
M07_AXI_wready(0) => processing_system7_0_axi_periph_M07_AXI_WREADY,
M07_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M07_AXI_WSTRB(3 downto 0),
M07_AXI_wvalid(0) => processing_system7_0_axi_periph_M07_AXI_WVALID(0),
M08_ACLK => processing_system7_0_FCLK_CLK0,
M08_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
M08_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M08_AXI_ARADDR(31 downto 0),
M08_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M08_AXI_ARPROT(2 downto 0),
M08_AXI_arready(0) => processing_system7_0_axi_periph_M08_AXI_ARREADY,
M08_AXI_arvalid(0) => processing_system7_0_axi_periph_M08_AXI_ARVALID(0),
M08_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M08_AXI_AWADDR(31 downto 0),
M08_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M08_AXI_AWPROT(2 downto 0),
M08_AXI_awready(0) => processing_system7_0_axi_periph_M08_AXI_AWREADY,
M08_AXI_awvalid(0) => processing_system7_0_axi_periph_M08_AXI_AWVALID(0),
M08_AXI_bready(0) => processing_system7_0_axi_periph_M08_AXI_BREADY(0),
M08_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M08_AXI_BRESP(1 downto 0),
M08_AXI_bvalid(0) => processing_system7_0_axi_periph_M08_AXI_BVALID,
M08_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M08_AXI_RDATA(31 downto 0),
M08_AXI_rready(0) => processing_system7_0_axi_periph_M08_AXI_RREADY(0),
M08_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M08_AXI_RRESP(1 downto 0),
M08_AXI_rvalid(0) => processing_system7_0_axi_periph_M08_AXI_RVALID,
M08_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M08_AXI_WDATA(31 downto 0),
M08_AXI_wready(0) => processing_system7_0_axi_periph_M08_AXI_WREADY,
M08_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M08_AXI_WSTRB(3 downto 0),
M08_AXI_wvalid(0) => processing_system7_0_axi_periph_M08_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
router_00: component sys_router_0_0
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
E_DIN(31 downto 0) => router_10_W_OUT_TDATA(31 downto 0),
E_DOUT(31 downto 0) => router_00_E_OUT_TDATA(31 downto 0),
E_RIN => router_10_W_OUT_TREADY,
E_ROUT => router_00_E_OUT_TREADY,
E_VIN => router_10_W_OUT_TVALID,
E_VOUT => router_00_E_OUT_TVALID,
L_DIN(31 downto 0) => axi_nic_00_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_00_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_00_TX_TREADY,
L_ROUT => router_00_L_OUT_TREADY,
L_VIN => axi_nic_00_TX_TVALID,
L_VOUT => router_00_L_OUT_TVALID,
N_DIN(31 downto 0) => router_01_S_OUT_TDATA(31 downto 0),
N_DOUT(31 downto 0) => router_00_N_OUT_TDATA(31 downto 0),
N_RIN => router_01_S_OUT_TREADY,
N_ROUT => router_00_N_OUT_TREADY,
N_VIN => router_01_S_OUT_TVALID,
N_VOUT => router_00_N_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0)
);
router_01: component sys_router_0_1
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
E_DIN(31 downto 0) => router_11_W_OUT_TDATA(31 downto 0),
E_DOUT(31 downto 0) => router_01_E_OUT_TDATA(31 downto 0),
E_RIN => router_11_W_OUT_TREADY,
E_ROUT => router_01_E_OUT_TREADY,
E_VIN => router_11_W_OUT_TVALID,
E_VOUT => router_01_E_OUT_TVALID,
L_DIN(31 downto 0) => axi_nic_01_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_01_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_01_TX_TREADY,
L_ROUT => router_01_L_OUT_TREADY,
L_VIN => axi_nic_01_TX_TVALID,
L_VOUT => router_01_L_OUT_TVALID,
N_DIN(31 downto 0) => router_02_S_OUT_TDATA(31 downto 0),
N_DOUT(31 downto 0) => router_01_N_OUT_TDATA(31 downto 0),
N_RIN => router_02_S_OUT_TREADY,
N_ROUT => router_01_N_OUT_TREADY,
N_VIN => router_02_S_OUT_TVALID,
N_VOUT => router_01_N_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
S_DIN(31 downto 0) => router_00_N_OUT_TDATA(31 downto 0),
S_DOUT(31 downto 0) => router_01_S_OUT_TDATA(31 downto 0),
S_RIN => router_00_N_OUT_TREADY,
S_ROUT => router_01_S_OUT_TREADY,
S_VIN => router_00_N_OUT_TVALID,
S_VOUT => router_01_S_OUT_TVALID
);
router_02: component sys_router_0_2
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
E_DIN(31 downto 0) => router_12_W_OUT_TDATA(31 downto 0),
E_DOUT(31 downto 0) => router_02_E_OUT_TDATA(31 downto 0),
E_RIN => router_12_W_OUT_TREADY,
E_ROUT => router_02_E_OUT_TREADY,
E_VIN => router_12_W_OUT_TVALID,
E_VOUT => router_02_E_OUT_TVALID,
L_DIN(31 downto 0) => axi_nic_02_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_02_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_02_TX_TREADY,
L_ROUT => router_02_L_OUT_TREADY,
L_VIN => axi_nic_02_TX_TVALID,
L_VOUT => router_02_L_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
S_DIN(31 downto 0) => router_01_N_OUT_TDATA(31 downto 0),
S_DOUT(31 downto 0) => router_02_S_OUT_TDATA(31 downto 0),
S_RIN => router_01_N_OUT_TREADY,
S_ROUT => router_02_S_OUT_TREADY,
S_VIN => router_01_N_OUT_TVALID,
S_VOUT => router_02_S_OUT_TVALID
);
router_10: component sys_router_00_0
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
E_DIN(31 downto 0) => router_20_W_OUT_TDATA(31 downto 0),
E_DOUT(31 downto 0) => router_10_E_OUT_TDATA(31 downto 0),
E_RIN => router_20_W_OUT_TREADY,
E_ROUT => router_10_E_OUT_TREADY,
E_VIN => router_20_W_OUT_TVALID,
E_VOUT => router_10_E_OUT_TVALID,
L_DIN(31 downto 0) => axi_nic_10_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_10_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_10_TX_TREADY,
L_ROUT => router_10_L_OUT_TREADY,
L_VIN => axi_nic_10_TX_TVALID,
L_VOUT => router_10_L_OUT_TVALID,
N_DIN(31 downto 0) => router_11_S_OUT_TDATA(31 downto 0),
N_DOUT(31 downto 0) => router_10_N_OUT_TDATA(31 downto 0),
N_RIN => router_11_S_OUT_TREADY,
N_ROUT => router_10_N_OUT_TREADY,
N_VIN => router_11_S_OUT_TVALID,
N_VOUT => router_10_N_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
W_DIN(31 downto 0) => router_00_E_OUT_TDATA(31 downto 0),
W_DOUT(31 downto 0) => router_10_W_OUT_TDATA(31 downto 0),
W_RIN => router_00_E_OUT_TREADY,
W_ROUT => router_10_W_OUT_TREADY,
W_VIN => router_00_E_OUT_TVALID,
W_VOUT => router_10_W_OUT_TVALID
);
router_11: component sys_router_10_0
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
E_DIN(31 downto 0) => router_21_W_OUT_TDATA(31 downto 0),
E_DOUT(31 downto 0) => router_11_E_OUT_TDATA(31 downto 0),
E_RIN => router_21_W_OUT_TREADY,
E_ROUT => router_11_E_OUT_TREADY,
E_VIN => router_21_W_OUT_TVALID,
E_VOUT => router_11_E_OUT_TVALID,
L_DIN(31 downto 0) => axi_nic_11_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_11_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_11_TX_TREADY,
L_ROUT => router_11_L_OUT_TREADY,
L_VIN => axi_nic_11_TX_TVALID,
L_VOUT => router_11_L_OUT_TVALID,
N_DIN(31 downto 0) => router_12_S_OUT_TDATA(31 downto 0),
N_DOUT(31 downto 0) => router_11_N_OUT_TDATA(31 downto 0),
N_RIN => router_12_S_OUT_TREADY,
N_ROUT => router_11_N_OUT_TREADY,
N_VIN => router_12_S_OUT_TVALID,
N_VOUT => router_11_N_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
S_DIN(31 downto 0) => router_10_N_OUT_TDATA(31 downto 0),
S_DOUT(31 downto 0) => router_11_S_OUT_TDATA(31 downto 0),
S_RIN => router_10_N_OUT_TREADY,
S_ROUT => router_11_S_OUT_TREADY,
S_VIN => router_10_N_OUT_TVALID,
S_VOUT => router_11_S_OUT_TVALID,
W_DIN(31 downto 0) => router_01_E_OUT_TDATA(31 downto 0),
W_DOUT(31 downto 0) => router_11_W_OUT_TDATA(31 downto 0),
W_RIN => router_01_E_OUT_TREADY,
W_ROUT => router_11_W_OUT_TREADY,
W_VIN => router_01_E_OUT_TVALID,
W_VOUT => router_11_W_OUT_TVALID
);
router_12: component sys_router_10_1
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
E_DIN(31 downto 0) => router_22_W_OUT_TDATA(31 downto 0),
E_DOUT(31 downto 0) => router_12_E_OUT_TDATA(31 downto 0),
E_RIN => router_22_W_OUT_TREADY,
E_ROUT => router_12_E_OUT_TREADY,
E_VIN => router_22_W_OUT_TVALID,
E_VOUT => router_12_E_OUT_TVALID,
L_DIN(31 downto 0) => axi_nic_12_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_12_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_12_TX_TREADY,
L_ROUT => router_12_L_OUT_TREADY,
L_VIN => axi_nic_12_TX_TVALID,
L_VOUT => router_12_L_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
S_DIN(31 downto 0) => router_11_N_OUT_TDATA(31 downto 0),
S_DOUT(31 downto 0) => router_12_S_OUT_TDATA(31 downto 0),
S_RIN => router_11_N_OUT_TREADY,
S_ROUT => router_12_S_OUT_TREADY,
S_VIN => router_11_N_OUT_TVALID,
S_VOUT => router_12_S_OUT_TVALID,
W_DIN(31 downto 0) => router_02_E_OUT_TDATA(31 downto 0),
W_DOUT(31 downto 0) => router_12_W_OUT_TDATA(31 downto 0),
W_RIN => router_02_E_OUT_TREADY,
W_ROUT => router_12_W_OUT_TREADY,
W_VIN => router_02_E_OUT_TVALID,
W_VOUT => router_12_W_OUT_TVALID
);
router_20: component sys_router_10_2
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
L_DIN(31 downto 0) => axi_nic_20_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_20_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_20_TX_TREADY,
L_ROUT => router_20_L_OUT_TREADY,
L_VIN => axi_nic_20_TX_TVALID,
L_VOUT => router_20_L_OUT_TVALID,
N_DIN(31 downto 0) => router_21_S_OUT_TDATA(31 downto 0),
N_DOUT(31 downto 0) => router_20_N_OUT_TDATA(31 downto 0),
N_RIN => router_21_S_OUT_TREADY,
N_ROUT => router_20_N_OUT_TREADY,
N_VIN => router_21_S_OUT_TVALID,
N_VOUT => router_20_N_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
W_DIN(31 downto 0) => router_10_E_OUT_TDATA(31 downto 0),
W_DOUT(31 downto 0) => router_20_W_OUT_TDATA(31 downto 0),
W_RIN => router_10_E_OUT_TREADY,
W_ROUT => router_20_W_OUT_TREADY,
W_VIN => router_10_E_OUT_TVALID,
W_VOUT => router_20_W_OUT_TVALID
);
router_21: component sys_router_20_0
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
L_DIN(31 downto 0) => axi_nic_21_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_21_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_21_TX_TREADY,
L_ROUT => router_21_L_OUT_TREADY,
L_VIN => axi_nic_21_TX_TVALID,
L_VOUT => router_21_L_OUT_TVALID,
N_DIN(31 downto 0) => router_22_S_OUT_TDATA(31 downto 0),
N_DOUT(31 downto 0) => router_21_N_OUT_TDATA(31 downto 0),
N_RIN => router_22_S_OUT_TREADY,
N_ROUT => router_21_N_OUT_TREADY,
N_VIN => router_22_S_OUT_TVALID,
N_VOUT => router_21_N_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
S_DIN(31 downto 0) => router_20_N_OUT_TDATA(31 downto 0),
S_DOUT(31 downto 0) => router_21_S_OUT_TDATA(31 downto 0),
S_RIN => router_20_N_OUT_TREADY,
S_ROUT => router_21_S_OUT_TREADY,
S_VIN => router_20_N_OUT_TVALID,
S_VOUT => router_21_S_OUT_TVALID,
W_DIN(31 downto 0) => router_11_E_OUT_TDATA(31 downto 0),
W_DOUT(31 downto 0) => router_21_W_OUT_TDATA(31 downto 0),
W_RIN => router_11_E_OUT_TREADY,
W_ROUT => router_21_W_OUT_TREADY,
W_VIN => router_11_E_OUT_TVALID,
W_VOUT => router_21_W_OUT_TVALID
);
router_22: component sys_router_20_1
port map (
CLOCK => processing_system7_0_FCLK_CLK0,
L_DIN(31 downto 0) => axi_nic_22_TX_TDATA(31 downto 0),
L_DOUT(31 downto 0) => router_22_L_OUT_TDATA(31 downto 0),
L_RIN => axi_nic_22_TX_TREADY,
L_ROUT => router_22_L_OUT_TREADY,
L_VIN => axi_nic_22_TX_TVALID,
L_VOUT => router_22_L_OUT_TVALID,
RESET => rst_processing_system7_0_100M_peripheral_reset(0),
S_DIN(31 downto 0) => router_21_N_OUT_TDATA(31 downto 0),
S_DOUT(31 downto 0) => router_22_S_OUT_TDATA(31 downto 0),
S_RIN => router_21_N_OUT_TREADY,
S_ROUT => router_22_S_OUT_TREADY,
S_VIN => router_21_N_OUT_TVALID,
S_VOUT => router_22_S_OUT_TVALID,
W_DIN(31 downto 0) => router_12_E_OUT_TDATA(31 downto 0),
W_DOUT(31 downto 0) => router_22_W_OUT_TDATA(31 downto 0),
W_RIN => router_12_E_OUT_TREADY,
W_ROUT => router_22_W_OUT_TREADY,
W_VIN => router_12_E_OUT_TVALID,
W_VOUT => router_22_W_OUT_TVALID
);
rst_processing_system7_0_100M: component sys_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => rst_processing_system7_0_100M_peripheral_reset(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_10_0/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY FIFO_32x1Kr IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END FIFO_32x1Kr;
ARCHITECTURE FIFO_32x1Kr_arch OF FIFO_32x1Kr IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FIFO_32x1Kr_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FIFO_32x1Kr_arch : ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_" &
"NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_" &
"TYPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1" &
",C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx36,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=32,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10," &
"C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=1,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH" &
"=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 1,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 32,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 1,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count
);
END FIFO_32x1Kr_arch;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_0_1/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY FIFO_32x1Kr IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END FIFO_32x1Kr;
ARCHITECTURE FIFO_32x1Kr_arch OF FIFO_32x1Kr IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FIFO_32x1Kr_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FIFO_32x1Kr_arch : ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_" &
"NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_" &
"TYPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1" &
",C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx36,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=32,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10," &
"C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=1,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH" &
"=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 1,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 32,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 1,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count
);
END FIFO_32x1Kr_arch;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_10_1/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY FIFO_32x1Kr IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END FIFO_32x1Kr;
ARCHITECTURE FIFO_32x1Kr_arch OF FIFO_32x1Kr IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FIFO_32x1Kr_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FIFO_32x1Kr_arch : ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_" &
"NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_" &
"TYPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1" &
",C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx36,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=32,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10," &
"C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=1,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH" &
"=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 1,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 32,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 1,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count
);
END FIFO_32x1Kr_arch;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_00_0/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY FIFO_32x1Kr IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END FIFO_32x1Kr;
ARCHITECTURE FIFO_32x1Kr_arch OF FIFO_32x1Kr IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FIFO_32x1Kr_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FIFO_32x1Kr_arch : ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FIFO_32x1Kr_arch: ARCHITECTURE IS "FIFO_32x1Kr,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_" &
"NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_" &
"TYPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1" &
",C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx36,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=32,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10," &
"C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=1,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH" &
"=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 1,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 32,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 1,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count
);
END FIFO_32x1Kr_arch;
| mit |
kauecano/eel5105 | vhds/Cont_desc.vhd | 1 | 606 | library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
use IEEE.Std_Logic_arith.all;
entity Cont_desc is
port ( CLK1, rst, en: in std_logic;
S: out std_logic_vector(9 downto 0)
);
end Cont_desc;
architecture Cont_desc_estr of Cont_desc is
signal cont: std_logic_vector(9 downto 0):="1111101100";--valor inicial dos créditos 1004.
begin
S <= cont;
process ( CLK1, rst)
begin
if rst = '0' then
cont <= "1111101100";
elsif (CLK1'event and CLK1 = '1') then
if en = '1' then
cont <= cont - '1';
end if;
end if;
end process;
end Cont_desc_estr;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/hdl/sys_wrapper.vhd | 1 | 3399 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Apr 15 18:53:53 2017
--Host : work running 64-bit Ubuntu 16.04.2 LTS
--Command : generate_target sys_wrapper.bd
--Design : sys_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sys_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end sys_wrapper;
architecture STRUCTURE of sys_wrapper is
component sys is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component sys;
begin
sys_i: component sys
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
| mit |
kauecano/eel5105 | vhds/topo_reg.vhd | 1 | 876 | library ieee;
use ieee.std_logic_1164.all;
entity topo_reg is
port ( BTN0, C3, C2, C1, C0, CLOCK_50: IN STD_LOGIC;
REG: IN STD_LOGIC_VECTOR(19 downto 0);
SEQ_3, SEQ_2, SEQ_1, SEQ_0 : OUT STD_LOGIC_VECTOR(4 downto 0)
);
end topo_reg;
architecture topo_reg_arch of topo_reg is
component reg_5bits
port (
EN, CLK, RST: in std_logic;
D: in std_logic_vector(4 downto 0);
Q: out std_logic_vector(4 downto 0)
);
end component;
begin
L0: reg_5bits port map (C3, CLOCK_50, BTN0, REG(19 downto 15), SEQ_3);--todos os registradores recebem o sinal de clock e reset
L1: reg_5bits port map (C2, CLOCK_50, BTN0, REG(14 downto 10), SEQ_2);--ao mesmo tempo, mas o sinal de enable é único para cada
L2: reg_5bits port map (C1, CLOCK_50, BTN0, REG(9 downto 5), SEQ_1);-- um deles.
L3: reg_5bits port map (C0, CLOCK_50, BTN0, REG(4 downto 0), SEQ_0);
end topo_reg_arch;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_20_0/sim/sys_axi_nic_20_0.vhd | 1 | 9209 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_20_0 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_20_0;
ARCHITECTURE sys_axi_nic_20_0_arch OF sys_axi_nic_20_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_20_0_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_20_0_arch;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd | 15 | 22231 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_00_0/synth/sys_axi_nic_00_0.vhd | 1 | 9482 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_00_0 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_00_0;
ARCHITECTURE sys_axi_nic_00_0_arch OF sys_axi_nic_00_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_00_0_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sys_axi_nic_00_0_arch: ARCHITECTURE IS "nic_v1_0,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sys_axi_nic_00_0_arch : ARCHITECTURE IS "sys_axi_nic_00_0,nic_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_00_0_arch;
| mit |
kauecano/eel5105 | vhds/reg_5bits.vhd | 1 | 486 | library ieee;
use ieee.std_logic_1164.all;
entity reg_5bits is
port (EN, CLK, RST: in std_logic;
D: in std_logic_vector(4 downto 0);
Q: out std_logic_vector(4 downto 0)
);
end reg_5bits;
architecture bhv of reg_5bits is
begin
process(CLK, D)
begin
if RST = '0' then--reset assíncrono do registrador.
Q <= "00000";
elsif
(CLK' event and CLK ='1') then--clock na borda de subida.
if EN = '1' then
Q <= D;
end if;
end if;
end process;
end bhv;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd | 32 | 49938 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_20_0/src/FIFO_32x1K/synth/FIFO_32x1K.vhd | 9 | 39096 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY FIFO_32x1K IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END FIFO_32x1K;
ARCHITECTURE FIFO_32x1K_arch OF FIFO_32x1K IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FIFO_32x1K_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FIFO_32x1K_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FIFO_32x1K_arch : ARCHITECTURE IS "FIFO_32x1K,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FIFO_32x1K_arch: ARCHITECTURE IS "FIFO_32x1K,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINI" &
"T_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_N" &
"EGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_T" &
"YPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1," &
"C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_RD" &
"CH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx36,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR" &
"_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=32,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C" &
"_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=1,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15,C" &
"_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=" &
"14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 1,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 32,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 1,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count
);
END FIFO_32x1K_arch;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_10_0/sim/sys_router_10_0.vhd | 1 | 9079 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_10_0 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END sys_router_10_0;
ARCHITECTURE sys_router_10_0_arch OF sys_router_10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_10_0_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 1,
ADDR_Y => 1,
N_INST => true,
S_INST => true,
E_INST => true,
W_INST => true
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT
);
END sys_router_10_0_arch;
| mit |
ress/VHDL-Pong | Pong.vhd | 1 | 17042 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:18:30 07/14/2009
-- Design Name:
-- Module Name: Pong - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Pong is
Port (
clk : in STD_LOGIC;
hsync_out : out STD_LOGIC;
vsync_out : out STD_LOGIC;
red_out : out STD_LOGIC;
green_out : out STD_LOGIC;
blue_out : out STD_LOGIC;
-- leftPlayerInput : in STD_LOGIC;
-- rightPlayerInput : in STD_LOGIC;
soundPin : buffer STD_LOGIC := '0';
kb_clk : in STD_LOGIC;
kb_data : in STD_LOGIC
);
end Pong;
architecture Behavioral of Pong is
component KeyboardController is
Port ( Clock : in STD_LOGIC;
KeyboardClock : in STD_LOGIC;
KeyboardData : in STD_LOGIC;
LeftPaddleDirection : out integer;
RightPaddleDirection : out integer
);
end component;
signal halfClock : STD_LOGIC;
signal horizontalPosition : integer range 0 to 800 := 0;
signal verticalPosition : integer range 0 to 521 := 0;
signal hsyncEnable : STD_LOGIC;
signal vsyncEnable : STD_LOGIC;
signal photonX : integer range 0 to 640 := 0;
signal photonY : integer range 0 to 480 := 0;
constant leftPaddleX : integer := 25;
signal leftPaddleY : integer range 0 to 480 := 240;
constant rightPaddleX : integer := 615;
signal rightPaddleY : integer range 0 to 480 := 240;
signal rightPaddleDirection : integer := 0;
signal leftPaddleDirection : integer := 0;
signal paddleHalfHeight : integer range 0 to 50 := 30;
constant paddleHalfWidth : integer := 6;
constant leftPaddleBackX : integer := leftPaddleX-paddleHalfWidth;
constant leftPaddleFrontX : integer := leftPaddleX+paddleHalfWidth;
constant rightPaddleFrontX : integer := rightPaddleX-paddleHalfWidth;
constant rightPaddleBackX : integer := rightPaddleX+paddleHalfWidth;
constant paddleBottomLimit : integer := 474;
constant paddleTopLimit : integer := 4;
signal color : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal ballMovementClockCounter : integer range 0 to 1000000 := 0;
signal ballMovementClock : STD_LOGIC := '0';
signal paddleMovementClockCounter : integer range 0 to 1000000 := 0;
signal paddleMovementClock : STD_LOGIC := '0';
constant ballMaxSpeed : integer := 8;
signal ballX : integer range -100 to 640 := 320;
signal ballY : integer range -100 to 480 := 240;
signal ballSpeedX : integer range -100 to 100 := 1;
signal ballSpeedY : integer range -100 to 100 := 1;
constant maxLeftLifes : integer := 5;
constant maxRightLifes : integer := 5;
signal leftLifes : integer range 0 to 5 := maxLeftLifes;
signal rightLifes : integer range 0 to 5 := maxRightLifes;
signal gameOver : STD_LOGIC := '0';
constant leftLifePosition : integer := 179;
constant rightLifePosition : integer := 359;
constant lifeBarWidth : integer := 100;
constant lifeBarHeight : integer := 3;
signal resetBall : STD_LOGIC := '0';
signal resetCounter : integer range 0 to 101 := 0;
signal soundCounter : integer range 0 to 1000000 := 0;
signal soundClock : STD_LOGIC := '0';
signal soundPlingCounter : integer range 0 to 100000000 := 0;
signal soundEnable : STD_LOGIC := '0';
signal playSound : STD_LOGIC := '0';
begin
kbController : KeyboardController port map ( clk, kb_clk, kb_data, leftPaddleDirection, rightPaddleDirection );
-- Controls length of beep tone
soundScaler : process(clk)
begin
if clk'event and clk='1' then
if soundCounter = 100000 then --adjust for length of beep
soundCounter <= 0;
soundClock <= not soundClock;
else
soundCounter <= soundCounter + 1;
end if;
end if;
end process soundScaler;
sound : process(soundClock)
begin
if soundClock'event and soundClock = '1' then
if soundEnable = '1' then
soundPin <= not soundPin;
else
soundPin <= '0';
end if;
end if;
end process sound;
soundPling : process(playSound, soundClock)
begin
if soundClock'event and soundClock = '1' then
if playSound='1' then
if soundPlingCounter >= 0 and soundPlingCounter < 20 then
soundEnable <= '1';
soundPlingCounter <= soundPlingCounter + 1;
else
soundEnable <= '0';
end if;
else
soundEnable <= '0';
soundPlingCounter <= 0;
end if;
end if;
end process soundPling;
-- Half the clock
clockScaler : process(clk)
begin
if clk'event and clk = '1' then
halfClock <= not halfClock;
end if;
end process clockScaler;
-- Allows Ball movement on clock pulse
-- Stops at VGA border
ballMovementClockScaler : process(clk)
begin
if clk'event and clk = '1' then
ballMovementClockCounter <= ballMovementClockCounter + 1;
if (ballMovementClockCounter = 500000) then
ballMovementClock <= not ballMovementClock;
ballMovementClockCounter <= 0;
end if;
end if;
end process ballMovementClockScaler;
-- Allows Paddle movement on clock pulse
-- Stops at VGA border
paddleMovementClockScaler : process(clk)
begin
if clk'event and clk = '1' then
paddleMovementClockCounter <= paddleMovementClockCounter + 1;
if (paddleMovementClockCounter = 100000) then
paddleMovementClock <= not paddleMovementClock;
paddleMovementClockCounter <= 0;
end if;
end if;
end process paddleMovementClockScaler;
signalTiming : process(halfClock)
begin
if halfClock'event and halfClock = '1' then
if horizontalPosition = 800 then
horizontalPosition <= 0;
verticalPosition <= verticalPosition + 1;
if verticalPosition = 521 then
verticalPosition <= 0;
else
verticalPosition <= verticalPosition + 1;
end if;
else
horizontalPosition <= horizontalPosition + 1;
end if;
end if;
end process signalTiming;
vgaSync : process(halfClock, horizontalPosition, verticalPosition)
begin
if halfClock'event and halfClock = '1' then
if horizontalPosition > 0 and horizontalPosition < 97 then
hsyncEnable <= '0';
else
hsyncEnable <= '1';
end if;
if verticalPosition > 0 and verticalPosition < 3 then
vsyncEnable <= '0';
else
vsyncEnable <= '1';
end if;
end if;
end process vgaSync;
coordinates : process(horizontalPosition, verticalPosition)
begin
photonX <= horizontalPosition - 144;
photonY <= verticalPosition - 31;
end process coordinates;
finishGame : process(leftLifes, rightLifes)
begin
if leftLifes = 0 or rightLifes = 0 then
gameOver <= '1';
end if;
end process finishGame;
colorSetter : process(photonX, photonY, halfClock)
begin
-- Paddle handling
if gameOver = '1' then
-- G
if photonX >= 20 and photonX <= 80 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 20 and photonX <= 30 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 20 and photonX <= 80 and photonY >= 290 and photonY <= 300 then
color <= "100";
elsif photonX >= 70 and photonX <= 80 and photonY >= 240 and photonY <= 300 then
color <= "100";
elsif photonX >= 50 and photonX <= 80 and photonY >= 240 and photonY <= 250 then
color <= "100";
-- A
elsif photonX >= 90 and photonX <= 150 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 90 and photonX <= 100 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 140 and photonX <= 150 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 90 and photonX <= 150 and photonY >= 240 and photonY <= 250 then
color <= "100";
-- M
elsif ((photonX >= 160 and photonX <= 170 and photonY >= 180 and photonY <= 300) or
(photonX >= 170 and photonX <= 220 and photonY >= 190 and photonY <= 200) or
(photonX >= 210 and photonX <= 220 and photonY >= 190 and photonY <= 300) or
(photonX >= 185 and photonX <= 195 and photonY >= 190 and photonY <= 300)) then
color <= "100";
-- erstes E
elsif photonX >= 230 and photonX <= 290 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 230 and photonX <= 290 and photonY >= 235 and photonY <= 245 then
color <= "100";
elsif photonX >= 230 and photonX <= 290 and photonY >= 290 and photonY <= 300 then
color <= "100";
elsif photonX >= 230 and photonX <= 240 and photonY >= 180 and photonY <= 300 then
color <= "100";
-- O
elsif photonX >= 348 and photonX <= 408 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 348 and photonX <= 358 and photonY >= 190 and photonY <= 290 then
color <= "100";
elsif photonX >= 398 and photonX <= 408 and photonY >= 190 and photonY <= 290 then
color <= "100";
elsif photonX >= 348 and photonX <= 408 and photonY >= 290 and photonY <= 300 then
color <= "100";
-- V
elsif photonX >= 418 and photonX <= 448 and photonY >= 270 and photonY <= 300 then
if (photonX - 418) = (photonY - 270) or
(photonX - 419) = (photonY - 270) or
(photonX - 420) = (photonY - 270) or
(photonX - 421) = (photonY - 270) or
(photonX - 422) = (photonY - 270) or
(photonX - 423) = (photonY - 270) or
(photonX - 424) = (photonY - 270) or
(photonX - 425) = (photonY - 270) or
(photonX - 426) = (photonY - 270) or
(photonX - 427) = (photonY - 270) or
(photonX - 428) = (photonY - 270) then
color <= "100";
else
color <= "000";
end if;
elsif photonX >= 449 and photonX <= 478 and photonY >= 270 and photonY <= 300 then
if (478 - photonX) = (photonY - 270) or
(477 - photonX) = (photonY - 270) or
(476 - photonX) = (photonY - 270) or
(475 - photonX) = (photonY - 270) or
(474 - photonX) = (photonY - 270) or
(473 - photonX) = (photonY - 270) or
(472 - photonX) = (photonY - 270) or
(471 - photonX) = (photonY - 270) or
(470 - photonX) = (photonY - 270) or
(469 - photonX) = (photonY - 270) or
(468 - photonX) = (photonY - 270) then
color <= "100";
else
color <= "000";
end if;
elsif (photonX >= 418 and photonX <= 428 and photonY >= 180 and photonY <= 270) or
(photonX >= 468 and photonX <= 478 and photonY >= 180 and photonY <= 270) then
color <= "100";
-- zweites E
elsif photonX >= 488 and photonX <= 548 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 488 and photonX <= 548 and photonY >= 235 and photonY <= 245 then
color <= "100";
elsif photonX >= 488 and photonX <= 548 and photonY >= 290 and photonY <= 300 then
color <= "100";
elsif photonX >= 488 and photonX <= 498 and photonY >= 180 and photonY <= 300 then
color <= "100";
-- R
elsif photonX >= 558 and photonX <= 618 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 558 and photonX <= 568 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 608 and photonX <= 618 and photonY >= 190 and photonY <= 250 then
color <= "100";
elsif photonX >= 558 and photonX <= 618 and photonY >= 245 and photonY <= 255 then
color <= "100";
elsif photonX >= 568 and photonX <= 618 and photonY >= 245 and photonY <= 300 then
if (photonX - 568) = (photonY - 255) or
(photonX - 567) = (photonY - 255) or
(photonX - 566) = (photonY - 255) or
(photonX - 565) = (photonY - 255) or
(photonX - 564) = (photonY - 255) or
(photonX - 563) = (photonY - 255) or
(photonX - 562) = (photonY - 255) or
(photonX - 561) = (photonY - 255) or
(photonX - 569) = (photonY - 255) or
(photonX - 570) = (photonY - 255) or
(photonX - 571) = (photonY - 255) or
(photonX - 572) = (photonY - 255) or
(photonX - 573) = (photonY - 255) or
(photonX - 574) = (photonY - 255) then
color <= "100";
else
color <= "000";
end if;
else
color <= "000";
end if;
elsif ((photonX >= leftPaddleBackX) and (photonX <= leftPaddleFrontX)
and (photonY >= leftPaddleY - paddleHalfHeight) and (photonY <= leftPaddleY + paddleHalfHeight)) or
((photonX >= rightPaddleFrontX) and (photonX <= rightPaddleBackX)
and (photonY >= rightPaddleY - paddleHalfHeight) and (photonY <= rightPaddleY + paddleHalfHeight)) then
color <= "111";
-- Dashed Line
elsif (photonX = 319 and photonY mod 16 <= 10) then
color <= "111";
-- Ball
elsif (photonY >= ballY - 2 and photonY <= ballY + 2) and (photonX >= ballX - 2 and photonX <= ballX + 2) then
color <= "111";
elsif (photonY >= ballY - 3 and photonY <= ballY + 3) and (photonX >= ballX - 1 and photonX <= ballX + 1) then
color <= "111";
elsif (photonY >= ballY - 1 and photonY <= ballY + 1) and (photonX >= ballX - 3 and photonX <= ballX + 3) then
color <= "111";
-- green lifebar
elsif (photonX>=leftLifePosition and photonX<leftLifePosition+(leftLifes*20) and photonY>=30 and photonY<=30+lifeBarHeight) or
(photonX>=rightLifePosition and photonX<rightLifePosition+(rightLifes*20) and photonY>=30 and photonY<=30+lifeBarHeight) then
color <= "010";
-- red lifebar
elsif (photonX >= (leftLifePosition+(leftLifes*20)) and photonX <= (leftLifePosition+(20*maxLeftLifes)) and photonY>=30 and photonY<=(30+lifeBarHeight)) or
(photonX>=(rightLifePosition+(rightLifes*20)) and photonX<= (rightLifePosition+(20*maxRightLifes)) and photonY>=30 and photonY<=(30+lifeBarHeight)) then
color <= "100";
-- background
else
color <= "000";
end if;
end process colorSetter;
-- Left Player Control
-- Stops at Limit
leftPaddleMovement : process(paddleMovementClock)
begin
if paddleMovementClock'event and paddleMovementClock = '1' then
if leftPaddleY + leftPaddleDirection < paddleBottomLimit - paddleHalfHeight
and leftPaddleY + leftPaddleDirection > paddleTopLimit + paddleHalfHeight then
leftPaddleY <= leftPaddleY + leftPaddleDirection;
end if;
end if;
end process leftPaddleMovement;
-- Right Player Control
-- Stops at limit
rightPaddleMovement : process(paddleMovementClock)
begin
if paddleMovementClock'event and paddleMovementClock = '1' then
if rightPaddleY + rightPaddleDirection < paddleBottomLimit - paddleHalfHeight
and rightPaddleY + rightPaddleDirection > paddleTopLimit + paddleHalfHeight then
rightPaddleY <= rightPaddleY + rightPaddleDirection;
end if;
end if;
end process rightPaddleMovement;
ballMovement : process(ballMovementClock,gameOver,soundPlingCounter)
begin
if gameOver = '1' then -- Centers and stops ball
ballX <= 319;
ballY <= 239;
ballSpeedX <= 0;
ballSpeedY <= 0;
elsif soundPlingCounter >= 10 then
playSound <= '0';
elsif ballMovementClock'event and ballMovementClock='1' then
if resetBall = '1' then
if resetCounter = 100 then
resetCounter <= 0;
ballX <= 319;
ballY <= 239;
resetBall <= '0';
else
resetCounter <= resetCounter + 1;
end if;
else
if ballX+4 > rightPaddleFrontX and ballX < rightPaddleBackX
and ballY+4 > rightPaddleY-paddleHalfHeight and ballY-4 < rightPaddleY+paddleHalfHeight then
ballX <= rightPaddleFrontX - 4;
ballSpeedY <= (ballY - rightPaddleY) / 8;
ballSpeedX <= -ballMaxSpeed + ballSpeedY;
playSound <= '1';
elsif ballX-4 < leftPaddleFrontX and ballX > leftPaddleBackX
and ballY+4 > leftPaddleY-paddleHalfHeight and ballY-4 < leftPaddleY+paddleHalfHeight then
ballX <= leftPaddleFrontX + 4;
ballSpeedY <= ((ballY - leftPaddleY) / 8);
ballSpeedX <= ballMaxSpeed - ballSpeedY;
playSound <= '1';
elsif ballX + ballSpeedX < 4 then
leftLifes <= leftLifes - 1;
ballX <= -20;
ballY <= -20;
resetBall <= '1';
elsif ballX + ballSpeedX > 635 then
rightLifes <= rightLifes - 1;
ballX <= -20;
ballY <= -20;
resetBall <= '1';
else
ballX <= ballX + ballSpeedX;
end if;
if ballY > 470 then
ballY <= 470;
ballSpeedY <= -ballSpeedY;
playSound <= '1';
elsif ballY < 10 then
ballY <= 10;
ballSpeedY <= -ballSpeedY;
playSound <= '1';
else
ballY <= ballY + ballSpeedY;
end if;
end if;
end if;
end process ballMovement;
-- VGA Controller
draw : process(photonX, photonY, halfClock)
begin
if halfClock'event and halfClock = '1' then
hsync_out <= hsyncEnable;
vsync_out <= vsyncEnable;
if (photonX < 640 and photonY < 480) then
red_out <= color(2);
green_out <= color(1);
blue_out <= color(0);
else
red_out <= '0';
green_out <= '0';
blue_out <= '0';
end if;
end if;
end process draw;
end Behavioral; | mit |
Tech-Curriculums/FPGA-101---Introduction-to-Verilog | digilent.adept.sdk_2.3.1/samples/depp/DeppDemo/logic/dpimref.vhd | 1 | 13748 | ----------------------------------------------------------------------------
-- DPIMREF.VHD -- Digilent Parallel Interface Module Reference Design
----------------------------------------------------------------------------
-- Author: Gene Apperson
-- Copyright 2004 Digilent, Inc.
----------------------------------------------------------------------------
-- IMPORTANT NOTE ABOUT BUILDING THIS LOGIC IN ISE
--
-- Before building the Dpimref logic in ISE:
-- 1. In Project Navigator, right-click on "Synthesize-XST"
-- (in the Process View Tab) and select "Properties"
-- 2. Click the "HDL Options" tab
-- 3. Set the "FSM Encoding Algorithm" to "None"
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This module contains an example implementation of Digilent Parallel
-- Interface Module logic. This interface is used in conjunction with the
-- DPCUTIL DLL and a Digilent Communications Module (USB, EtherNet, Serial)
-- to exchange data with an application running on a host PC and the logic
-- implemented in a gate array.
--
-- See the Digilent document, Digilent Parallel Interface Model Reference
-- Manual (doc # 560-000) for a description of the interface.
--
-- This module also conforms with the Digilent Asynchronous Parallel
-- Interface (DEPP) specification, as outlined in the document titled
-- "Digilent Asynchronous Parallel Interface(DEPP)" (doc # 564-000). This
-- allows for the host to make calls to the DEPP API, as introduced in
-- Adept SDK 2.
--
-- This design uses a state machine implementation to respond to transfer
-- cycles. It implements an address register, 8 internal data registers
-- that merely hold a value written, and interface registers to communicate
-- with a Digilent FPGA board. There is an LED output register whose value
-- drives the 8 discrete leds on the board. There are two input registers.
-- One reads the 8 switches on the board and the other reads the buttons.
--
-- The top level port names conform with the master .ucf files provided
-- on the Digilent website, www.digilentinc.com. If your Digilent board
-- is compatible with this project, then the master .ucf file available
-- for it there will contain ports with these names.
--
-- Interface signals used in top level entity port:
-- clk - master clock, generally 50Mhz osc on system board
-- DB - port data bus
-- EppASTB - address strobe
-- EppDSTB - data strobe
-- EppWRITE - data direction (described in reference manual as WRITE)
-- EppWAIT - transfer synchronization (described in reference manual
-- as WAIT)
-- Led - LED outputs
-- sw - switch inputs
-- btn - button inputs
--
----------------------------------------------------------------------------
-- Revision History:
-- 06/09/2004(GeneA): created
-- 08/10/2004(GeneA): initial public release
-- 04/25/2006(JoshP): comment addition
-- 01/30/2012(SamB) : Removed debugging led logic and ldb signal
-- Changed signal names to conform with General UCFs
-- Updated comments for DEPP and multiple boards
-- 08/02/2012(JoshS): Net names in general UCFs updated, applied changes
-- to demo to keep up to date.
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dpimref is
Port (
clk : in std_logic;
DB : inout std_logic_vector(7 downto 0);
EppASTB : in std_logic;
EppDSTB : in std_logic;
EppWRITE : in std_logic;
EppWAIT : out std_logic;
Led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0);
btn : in std_logic_vector(3 downto 0)
);
end dpimref;
architecture Behavioral of dpimref is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- The following constants define state codes for the EPP port interface
-- state machine. The high order bits of the state number give a unique
-- state identifier. The low order bits are the state machine outputs for
-- that state. This type of state machine implementation uses no
-- combination logic to generate outputs which should produce glitch
-- free outputs.
constant stEppReady : std_logic_vector(7 downto 0) := "0000" & "0000";
constant stEppAwrA : std_logic_vector(7 downto 0) := "0001" & "0100";
constant stEppAwrB : std_logic_vector(7 downto 0) := "0010" & "0001";
constant stEppArdA : std_logic_vector(7 downto 0) := "0011" & "0010";
constant stEppArdB : std_logic_vector(7 downto 0) := "0100" & "0011";
constant stEppDwrA : std_logic_vector(7 downto 0) := "0101" & "1000";
constant stEppDwrB : std_logic_vector(7 downto 0) := "0110" & "0001";
constant stEppDrdA : std_logic_vector(7 downto 0) := "0111" & "0010";
constant stEppDrdB : std_logic_vector(7 downto 0) := "1000" & "0011";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- State machine current state register
signal stEppCur : std_logic_vector(7 downto 0) := stEppReady;
signal stEppNext : std_logic_vector(7 downto 0);
signal clkMain : std_logic;
-- Internal control signales
signal ctlEppWait : std_logic;
signal ctlEppAstb : std_logic;
signal ctlEppDstb : std_logic;
signal ctlEppDir : std_logic;
signal ctlEppWr : std_logic;
signal ctlEppAwr : std_logic;
signal ctlEppDwr : std_logic;
signal busEppOut : std_logic_vector(7 downto 0);
signal busEppIn : std_logic_vector(7 downto 0);
signal busEppData : std_logic_vector(7 downto 0);
-- Registers
signal regEppAdr : std_logic_vector(3 downto 0);
signal regData0 : std_logic_vector(7 downto 0);
signal regData1 : std_logic_vector(7 downto 0);
signal regData2 : std_logic_vector(7 downto 0);
signal regData3 : std_logic_vector(7 downto 0);
signal regData4 : std_logic_vector(7 downto 0);
signal regData5 : std_logic_vector(7 downto 0);
signal regData6 : std_logic_vector(7 downto 0);
signal regData7 : std_logic_vector(7 downto 0);
signal regLed : std_logic_vector(7 downto 0);
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Map basic status and control signals
------------------------------------------------------------------------
clkMain <= clk;
ctlEppAstb <= EppASTB;
ctlEppDstb <= EppDSTB;
ctlEppWr <= EppWRITE;
EppWAIT <= ctlEppWait; -- drive WAIT from state machine output
-- Data bus direction control. The internal input data bus always
-- gets the port data bus. The port data bus drives the internal
-- output data bus onto the pins when the interface says we are doing
-- a read cycle and we are in one of the read cycles states in the
-- state machine.
busEppIn <= DB;
DB <= busEppOut when ctlEppWr = '1' and ctlEppDir = '1' else "ZZZZZZZZ";
-- Select either address or data onto the internal output data bus.
busEppOut <= "0000" & regEppAdr when ctlEppAstb = '0' else busEppData;
Led <= regLed;
-- Decode the address register and select the appropriate data register
busEppData <= regData0 when regEppAdr = "0000" else
regData1 when regEppAdr = "0001" else
regData2 when regEppAdr = "0010" else
regData3 when regEppAdr = "0011" else
regData4 when regEppAdr = "0100" else
regData5 when regEppAdr = "0101" else
regData6 when regEppAdr = "0110" else
regData7 when regEppAdr = "0111" else
sw when regEppAdr = "1000" else
"0000" & btn when regEppAdr = "1001" else
"00000000";
------------------------------------------------------------------------
-- EPP Interface Control State Machine
------------------------------------------------------------------------
-- Map control signals from the current state
ctlEppWait <= stEppCur(0);
ctlEppDir <= stEppCur(1);
ctlEppAwr <= stEppCur(2);
ctlEppDwr <= stEppCur(3);
-- This process moves the state machine to the next state
-- on each clock cycle
process (clkMain)
begin
if clkMain = '1' and clkMain'Event then
stEppCur <= stEppNext;
end if;
end process;
-- This process determines the next state machine state based
-- on the current state and the state machine inputs.
process (stEppCur, stEppNext, ctlEppAstb, ctlEppDstb, ctlEppWr)
begin
case stEppCur is
-- Idle state waiting for the beginning of an EPP cycle
when stEppReady =>
if ctlEppAstb = '0' then
-- Address read or write cycle
if ctlEppWr = '0' then
stEppNext <= stEppAwrA;
else
stEppNext <= stEppArdA;
end if;
elsif ctlEppDstb = '0' then
-- Data read or write cycle
if ctlEppWr = '0' then
stEppNext <= stEppDwrA;
else
stEppNext <= stEppDrdA;
end if;
else
-- Remain in ready state
stEppNext <= stEppReady;
end if;
-- Write address register
when stEppAwrA =>
stEppNext <= stEppAwrB;
when stEppAwrB =>
if ctlEppAstb = '0' then
stEppNext <= stEppAwrB;
else
stEppNext <= stEppReady;
end if;
-- Read address register
when stEppArdA =>
stEppNext <= stEppArdB;
when stEppArdB =>
if ctlEppAstb = '0' then
stEppNext <= stEppArdB;
else
stEppNext <= stEppReady;
end if;
-- Write data register
when stEppDwrA =>
stEppNext <= stEppDwrB;
when stEppDwrB =>
if ctlEppDstb = '0' then
stEppNext <= stEppDwrB;
else
stEppNext <= stEppReady;
end if;
-- Read data register
when stEppDrdA =>
stEppNext <= stEppDrdB;
when stEppDrdB =>
if ctlEppDstb = '0' then
stEppNext <= stEppDrdB;
else
stEppNext <= stEppReady;
end if;
-- Some unknown state
when others =>
stEppNext <= stEppReady;
end case;
end process;
------------------------------------------------------------------------
-- EPP Address register
------------------------------------------------------------------------
process (clkMain, ctlEppAwr)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppAwr = '1' then
regEppAdr <= busEppIn(3 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------------
-- EPP Data registers
------------------------------------------------------------------------
-- The following processes implement the interface registers. These
-- registers just hold the value written so that it can be read back.
-- In a real design, the contents of these registers would drive additional
-- logic.
-- The ctlEppDwr signal is an output from the state machine that says
-- we are in a 'write data register' state. This is combined with the
-- address in the address register to determine which register to write.
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0000" then
regData0 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0001" then
regData1 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0010" then
regData2 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0011" then
regData3 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0100" then
regData4 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0101" then
regData5 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0110" then
regData6 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "0111" then
regData7 <= busEppIn;
end if;
end if;
end process;
process (clkMain, regEppAdr, ctlEppDwr, busEppIn)
begin
if clkMain = '1' and clkMain'Event then
if ctlEppDwr = '1' and regEppAdr = "1010" then
regLed <= busEppIn;
end if;
end if;
end process;
----------------------------------------------------------------------------
end Behavioral;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ipshared/9293/src/struct_out.vhd | 2 | 8698 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_out is
generic (
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(31 downto 0);
L_VIN : in std_logic;
L_RIN : out std_logic;
L_SZ : in std_logic_vector(15 downto 0);
L_DIR : in std_logic_vector(4 downto 0);
L_DOUT : out std_logic_vector(31 downto 0);
L_VOUT : out std_logic;
L_ROUT : in std_logic;
-- north
N_DIN : in std_logic_vector(31 downto 0);
N_VIN : in std_logic;
N_RIN : out std_logic;
N_SZ : in std_logic_vector(15 downto 0);
N_DIR : in std_logic_vector(4 downto 0);
N_DOUT : out std_logic_vector(31 downto 0);
N_VOUT : out std_logic;
N_ROUT : in std_logic;
-- south
S_DIN : in std_logic_vector(31 downto 0);
S_VIN : in std_logic;
S_RIN : out std_logic;
S_SZ : in std_logic_vector(15 downto 0);
S_DIR : in std_logic_vector(4 downto 0);
S_DOUT : out std_logic_vector(31 downto 0);
S_VOUT : out std_logic;
S_ROUT : in std_logic;
-- east
E_DIN : in std_logic_vector(31 downto 0);
E_VIN : in std_logic;
E_RIN : out std_logic;
E_SZ : in std_logic_vector(15 downto 0);
E_DIR : in std_logic_vector(4 downto 0);
E_DOUT : out std_logic_vector(31 downto 0);
E_VOUT : out std_logic;
E_ROUT : in std_logic;
-- west
W_DIN : in std_logic_vector(31 downto 0);
W_VIN : in std_logic;
W_RIN : out std_logic;
W_SZ : in std_logic_vector(15 downto 0);
W_DIR : in std_logic_vector(4 downto 0);
W_DOUT : out std_logic_vector(31 downto 0);
W_VOUT : out std_logic;
W_ROUT : in std_logic
);
end entity;
architecture structure of struct_out is
component fifo_out is
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(31 downto 0);
L_VIN : in std_logic;
L_RIN : out std_logic;
L_SZ : in std_logic_vector(15 downto 0);
L_DIR : in std_logic;
-- north
N_DIN : in std_logic_vector(31 downto 0);
N_VIN : in std_logic;
N_RIN : out std_logic;
N_SZ : in std_logic_vector(15 downto 0);
N_DIR : in std_logic;
-- south
S_DIN : in std_logic_vector(31 downto 0);
S_VIN : in std_logic;
S_RIN : out std_logic;
S_SZ : in std_logic_vector(15 downto 0);
S_DIR : in std_logic;
-- east
E_DIN : in std_logic_vector(31 downto 0);
E_VIN : in std_logic;
E_RIN : out std_logic;
E_SZ : in std_logic_vector(15 downto 0);
E_DIR : in std_logic;
-- west
W_DIN : in std_logic_vector(31 downto 0);
W_VIN : in std_logic;
W_RIN : out std_logic;
W_SZ : in std_logic_vector(15 downto 0);
W_DIR : in std_logic;
-- output
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic
);
end component;
signal l_l_rin : std_logic;
signal l_n_rin : std_logic;
signal l_s_rin : std_logic;
signal l_e_rin : std_logic;
signal l_w_rin : std_logic;
signal n_l_rin : std_logic;
signal n_n_rin : std_logic;
signal n_s_rin : std_logic;
signal n_e_rin : std_logic;
signal n_w_rin : std_logic;
signal s_l_rin : std_logic;
signal s_n_rin : std_logic;
signal s_s_rin : std_logic;
signal s_e_rin : std_logic;
signal s_w_rin : std_logic;
signal e_l_rin : std_logic;
signal e_n_rin : std_logic;
signal e_s_rin : std_logic;
signal e_e_rin : std_logic;
signal e_w_rin : std_logic;
signal w_l_rin : std_logic;
signal w_n_rin : std_logic;
signal w_s_rin : std_logic;
signal w_e_rin : std_logic;
signal w_w_rin : std_logic;
begin
L_RIN <= l_l_rin or n_l_rin or s_l_rin or e_l_rin or w_l_rin;
N_RIN <= l_n_rin or n_n_rin or s_n_rin or e_n_rin or w_n_rin;
S_RIN <= l_s_rin or n_s_rin or s_s_rin or e_s_rin or w_s_rin;
E_RIN <= l_e_rin or n_e_rin or s_e_rin or e_e_rin or w_e_rin;
W_RIN <= l_w_rin or n_w_rin or s_w_rin or e_w_rin or w_w_rin;
-- local
L_fifo: fifo_out
port map (
CLOCK => CLOCK,
RESET => RESET,
-- local
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => l_l_rin,
L_SZ => L_SZ,
L_DIR => L_DIR(4),
-- north
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => l_n_rin,
N_SZ => N_SZ,
N_DIR => N_DIR(4),
-- south
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => l_s_rin,
S_SZ => S_SZ,
S_DIR => S_DIR(4),
-- east
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => l_e_rin,
E_SZ => E_SZ,
E_DIR => E_DIR(4),
-- west
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => l_w_rin,
W_SZ => W_SZ,
W_DIR => W_DIR(4),
-- output
DOUT => L_DOUT,
VOUT => L_VOUT,
ROUT => L_ROUT
);
-- north
N_fifo_gen: if N_INST = true generate
N_fifo: fifo_out
port map (
CLOCK => CLOCK,
RESET => RESET,
-- local
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => n_l_rin,
L_SZ => L_SZ,
L_DIR => L_DIR(3),
-- north
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => n_n_rin,
N_SZ => N_SZ,
N_DIR => N_DIR(3),
-- south
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => n_s_rin,
S_SZ => S_SZ,
S_DIR => S_DIR(3),
-- east
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => n_e_rin,
E_SZ => E_SZ,
E_DIR => E_DIR(3),
-- west
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => n_w_rin,
W_SZ => W_SZ,
W_DIR => W_DIR(3),
-- output
DOUT => N_DOUT,
VOUT => N_VOUT,
ROUT => N_ROUT
);
end generate;
N_fifo_ngen: if N_INST = false generate
N_VOUT <= '0';
end generate;
-- south
S_fifo_gen: if S_INST = true generate
S_fifo: fifo_out
port map (
CLOCK => CLOCK,
RESET => RESET,
-- local
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => s_l_rin,
L_SZ => L_SZ,
L_DIR => L_DIR(2),
-- north
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => s_n_rin,
N_SZ => N_SZ,
N_DIR => N_DIR(2),
-- south
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => s_s_rin,
S_SZ => S_SZ,
S_DIR => S_DIR(2),
-- east
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => s_e_rin,
E_SZ => E_SZ,
E_DIR => E_DIR(2),
-- west
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => s_w_rin,
W_SZ => W_SZ,
W_DIR => W_DIR(2),
-- output
DOUT => S_DOUT,
VOUT => S_VOUT,
ROUT => S_ROUT
);
end generate;
S_fifo_ngen: if S_INST = false generate
S_VOUT <= '0';
end generate;
-- east
E_fifo_gen: if E_INST = true generate
E_fifo: fifo_out
port map (
CLOCK => CLOCK,
RESET => RESET,
-- local
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => e_l_rin,
L_SZ => L_SZ,
L_DIR => L_DIR(1),
-- north
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => e_n_rin,
N_SZ => N_SZ,
N_DIR => N_DIR(1),
-- south
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => e_s_rin,
S_SZ => S_SZ,
S_DIR => S_DIR(1),
-- east
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => e_e_rin,
E_SZ => E_SZ,
E_DIR => E_DIR(1),
-- west
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => e_w_rin,
W_SZ => W_SZ,
W_DIR => W_DIR(1),
-- output
DOUT => E_DOUT,
VOUT => E_VOUT,
ROUT => E_ROUT
);
end generate;
E_fifo_ngen: if E_INST = false generate
E_VOUT <= '0';
end generate;
-- west
W_fifo_gen: if W_INST = true generate
W_fifo: fifo_out
port map (
CLOCK => CLOCK,
RESET => RESET,
-- local
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => w_l_rin,
L_SZ => L_SZ,
L_DIR => L_DIR(0),
-- north
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => w_n_rin,
N_SZ => N_SZ,
N_DIR => N_DIR(0),
-- south
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => w_s_rin,
S_SZ => S_SZ,
S_DIR => S_DIR(0),
-- east
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => w_e_rin,
E_SZ => E_SZ,
E_DIR => E_DIR(0),
-- west
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => w_w_rin,
W_SZ => W_SZ,
W_DIR => W_DIR(0),
-- output
DOUT => W_DOUT,
VOUT => W_VOUT,
ROUT => W_ROUT
);
end generate;
W_fifo_ngen: if W_INST = false generate
W_VOUT <= '0';
end generate;
end architecture;
| mit |
BerkeleyTrue/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_0_1/sim/sys_router_0_1.vhd | 1 | 8260 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_0_1 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC
);
END sys_router_0_1;
ARCHITECTURE sys_router_0_1_arch OF sys_router_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 0,
ADDR_Y => 1,
N_INST => true,
S_INST => true,
E_INST => true,
W_INST => false
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
W_VIN => '0',
W_ROUT => '0'
);
END sys_router_0_1_arch;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_00_1/src/FIFO_32x4K/synth/FIFO_32x4K.vhd | 9 | 39096 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY FIFO_32x4K IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END FIFO_32x4K;
ARCHITECTURE FIFO_32x4K_arch OF FIFO_32x4K IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FIFO_32x4K_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FIFO_32x4K_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FIFO_32x4K_arch : ARCHITECTURE IS "FIFO_32x4K,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FIFO_32x4K_arch: ARCHITECTURE IS "FIFO_32x4K,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINI" &
"T_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_N" &
"EGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_T" &
"YPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1," &
"C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_RD" &
"CH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=4kx9,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_" &
"INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=32,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=4096,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=12,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=1,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15,C_" &
"PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=4095,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1" &
"4,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=4094,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 1,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "4kx9",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 32,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 4096,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 12,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 1,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 4095,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 4094,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
axis_data_count => axis_data_count
);
END FIFO_32x4K_arch;
| mit |
briannkym/583final | Breakout/DCM.vhd | 1 | 2645 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM.vhd
-- /___/ /\ Timestamp : 12/07/2013 15:49:21
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/brian/Desktop/583final/Breakout/ipcore_dir/DCM.xaw -st DCM.vhd
--Design Name: DCM
--Device: xc3s1200e-5fg320
--
-- Module DCM
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKDV_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM;
architecture BEHAVIORAL of DCM is
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (I=>CLKDV_BUF,
O=>CLKDV_OUT);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>CLKDV_BUF,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| mit |
rccoder/CPU-Summer-Term-HIT | chapter3/sreg.vhd | 1 | 1190 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:56 07/16/2015
-- Design Name:
-- Module Name: sreg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sreg is
port(
clk, clrn, serial : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end sreg ;
architecture main of sreg is
signal t : std_logic_vector(7 downto 0);
begin
process(clk, clrn)
begin
if clrn = '0' then
t <= "00000000";
elsif clk = '1' and clk'event then
t(7) <= serial;
t(6 downto 0) <= t(7 downto 1);
end if;
q <= t;
end process;
end main;
| mit |
Beck-Sisyphus/EE471 | Lab4/simulation/modelsim/rtl_work/@instru@memory/_primary.vhd | 1 | 720 | library verilog;
use verilog.vl_types.all;
entity InstruMemory is
generic(
DATA_WIDTH : integer := 32;
DATA_LENGTH : integer := 128;
ADX_LENGTH : integer := 7
);
port(
clk : in vl_logic;
adx : in vl_logic_vector;
WrEn : in vl_logic;
data : inout vl_logic_vector;
rst : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of DATA_LENGTH : constant is 1;
attribute mti_svvh_generic_type of ADX_LENGTH : constant is 1;
end InstruMemory;
| mit |
rccoder/CPU-Summer-Term-HIT | chapter3/count4.vhd | 1 | 1226 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:39:15 07/16/2015
-- Design Name:
-- Module Name: count4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity count4 is
port(
clk : in std_logic;
clrn : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end count4 ;
architecture main of count4 is
begin
process( clk, clrn )
variable num : integer;
begin
if clrn = '0' then
q <= "0000";
num := 0;
elsif clk = '0' and clk'event then
num := num + 1;
q <= conv_std_logic_vector(num, 4);
end if;
end process;
end main;
| mit |
briannkym/583final | Breakout/src/Digit.vhd | 1 | 4689 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:31:01 11/18/2013
-- Design Name:
-- Module Name: Digit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Digit is
port(
rainbow : in std_logic;
number : in std_logic_vector(3 downto 0);
x : in std_logic_vector(2 downto 0);
y : in std_logic_vector(2 downto 0);
R : out std_logic_vector(3 downto 0);
G : out std_logic_vector(3 downto 0);
B : out std_logic_vector(3 downto 0));
end Digit;
architecture dataflow of Digit is
constant zero: std_logic_vector(0 to 63):=
"0011110011100111110000111100001111000011110000111110011100111100";
constant one: std_logic_vector(0 to 63):=
"0000110000111100000111000000110000001100000011000001111011111111";
constant two: std_logic_vector(0 to 63):=
"0011111011100111110000110000001100000011000001110001111011111111";
constant three: std_logic_vector(0 to 63):=
"0011110011100111000011110111110000011110000011111110011100111100";
constant four: std_logic_vector(0 to 63):=
"1100001111000011110000111100001101111111000000110000001100000111";
constant five: std_logic_vector(0 to 63):=
"1111111111000000110000001111110000001111000000110000111111111100";
constant six: std_logic_vector(0 to 63):=
"0001111101110000110000001101110011100111110000111110011100111100";
constant seven: std_logic_vector(0 to 63):=
"1111111100000111000001100000110000011000001100000110000011100000";
constant eight: std_logic_vector(0 to 63):=
"0011110011100111111001110111111011100111110000111110011100111100";
constant nine: std_logic_vector(0 to 63):=
"0011110011100111110000110111111000001100000110000011000001110000";
signal pixel: std_logic :='0';
begin
process(x, y, number)
begin
case number is
when x"0" =>
if(zero(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"1" =>
if(one(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"2" =>
if(two(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"3" =>
if(three(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"4" =>
if(four(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"5" =>
if(five(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"6" =>
if(six(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"7" =>
if(seven(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"8" =>
if(eight(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"9" =>
if(nine(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when others =>
pixel<='0';
end case;
end process;
process (pixel, rainbow)
begin
if(pixel='1') then
if(rainbow='1') then
case y is
when "000" =>
R <= "1110";
G <= "0000";
B <= "0000";
when "001" =>
R <= "1110";
G <= "0110";
B <= "0000";
when "010" =>
R <= "1110";
G <= "1110";
B <= "0000";
when "011" =>
R <= "0000";
G <= "1110";
B <= "0000";
when "100" =>
R <= "0000";
G <= "0000";
B <= "1100";
when "101" =>
R <= "1000";
G <= "0000";
B <= "1100";
when others =>
R <= "1110";
G <= "0000";
B <= "0000";
end case;
else
R <="1000";
G <="1000";
B <="1000";
end if;
else
R <=x"0";
G <=x"0";
B <=x"0";
end if;
end process;
end dataflow;
| mit |
rccoder/CPU-Summer-Term-HIT | CPU/clock.vhd | 1 | 1448 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:37:09 07/24/2015
-- Design Name:
-- Module Name: clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
t : out STD_LOGIC_VECTOR (4 downto 0));
end clock;
architecture Behavioral of clock is
begin
process(clk, reset)
variable tep : integer range 0 to 6 := 0;
begin
if(reset = '1') then
t <= "00000";
tep := 0;
elsif (clk = '1' and clk' event) then
tep := tep + 1;
if tep = 6 then
tep := 1;
end if;
case tep is
when 1 => t <= "00001";
when 2 => t <= "00010";
when 3 => t <= "00100";
when 4 => t <= "01000";
when 5 => t <= "10000";
when others => NULL;
end case;
end if;
end process;
end Behavioral; | mit |
Beck-Sisyphus/EE471 | Lab4/simulation/modelsim/rtl_work/addition/_primary.vhd | 1 | 453 | library verilog;
use verilog.vl_types.all;
entity addition is
port(
busADD : out vl_logic_vector(31 downto 0);
busA : in vl_logic_vector(31 downto 0);
busB : in vl_logic_vector(31 downto 0);
zADD : out vl_logic;
oADD : out vl_logic;
cADD : out vl_logic;
nADD : out vl_logic
);
end addition;
| mit |
Beck-Sisyphus/EE471 | Lab4/work/mux2_1_testbench/_primary.vhd | 3 | 92 | library verilog;
use verilog.vl_types.all;
entity mux2_1_testbench is
end mux2_1_testbench;
| mit |
OgliariNatan/projetointegrador_II | D_7SEG/sevenSeg_decoder.vhd | 1 | 767 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sevenSeg_decoder IS
PORT
(
BCD_DATA: IN INTEGER;
SEG7_DATA: BUFFER STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevenSeg_decoder;
ARCHITECTURE behavior OF sevenSeg_decoder IS
BEGIN
PROCESS(BCD_DATA)
BEGIN
CASE (BCD_DATA) IS
WHEN 0 => SEG7_DATA <= "0000001";
WHEN 1 => SEG7_DATA <= "1001111";
WHEN 2 => SEG7_DATA <= "0010010";
WHEN 3 => SEG7_DATA <= "0000110";
WHEN 4 => SEG7_DATA <= "1001100";
WHEN 5 => SEG7_DATA <= "0100100";
WHEN 6 => SEG7_DATA <= "0100000";
WHEN 7 => SEG7_DATA <= "0001111";
WHEN 8 => SEG7_DATA <= "0000000";
WHEN 9 => SEG7_DATA <= "0000100";
WHEN OTHERS => SEG7_DATA <= "1111111"; -- Outras opções é nula
END CASE;
END PROCESS;
END; | mit |
briannkym/583final | Breakout/src/Sync.vhd | 1 | 1576 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity Sync is
Port(
clk: in std_logic;
R_in, G_in, B_in : in std_logic_vector(3 downto 0);
x, y : out std_logic_vector(11 downto 0);
HSync, VSync: out std_logic;
R, G, B : out std_logic_vector(3 downto 0)
);
end Sync;
Architecture behavioral of Sync is
signal x_pos : unsigned(11 downto 0) := (others => '0');
signal y_pos : unsigned(11 downto 0) := (others => '0');
begin
--Output the correct x and y signals when their values are going to be rendered.
x <= std_logic_vector(x_pos - 160) when (x_pos > 159) else
(others => '1');
y <= std_logic_vector(y_pos-45) when (y_pos > 44) else
(others => '1');
process(clk)
begin
--On the rising edge of the clock increment the x and y values.
if(clk'event and clk='1') then
if(x_pos < 800) then
x_pos <= x_pos + 1;
else
x_pos <= (others => '0');
if(y_pos < 525) then
y_pos <= y_pos + 1;
else
y_pos <= (others => '0');
end if;
end if;
--for x <160 and y <45 we must follow the vga protocol.
if(x_pos > 15 and x_pos < 112) then
Hsync <= '0';
else
HSync <='1';
end if;
if(y_pos > 9 and y_pos < 12) then
Vsync <='0';
else
Vsync <='1';
end if;
if((x_pos >= 0 and x_pos < 160) or (y_pos >= 0 and y_pos < 45)) then
R <= (others => '0');
G <= (others => '0');
B <= (others => '0');
else --If we are in range, forward the red green and blue values coming in.
R <= R_in;
G <= G_in;
B <= B_in;
end if;
end if;
end process;
end behavioral; | mit |
Beck-Sisyphus/EE471 | Lab4/simulation/modelsim/rtl_work/@instruc@decoder/_primary.vhd | 1 | 2132 | library verilog;
use verilog.vl_types.all;
entity InstrucDecoder is
generic(
nop : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi1, Hi0, Hi0);
add : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
sub : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi0);
\AND\ : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi0, Hi0);
\OR\ : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi0, Hi1);
\XOR\ : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi1, Hi1, Hi0);
slt : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0);
\sll\ : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
lw : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi1, Hi1);
sw : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi1);
jmp : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi0, Hi0, Hi1, Hi0);
jr : vl_logic_vector(0 to 5) := (Hi0, Hi0, Hi1, Hi0, Hi0, Hi0);
bgt : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi1, Hi0, Hi1)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of nop : constant is 1;
attribute mti_svvh_generic_type of add : constant is 1;
attribute mti_svvh_generic_type of sub : constant is 1;
attribute mti_svvh_generic_type of \AND\ : constant is 1;
attribute mti_svvh_generic_type of \OR\ : constant is 1;
attribute mti_svvh_generic_type of \XOR\ : constant is 1;
attribute mti_svvh_generic_type of slt : constant is 1;
attribute mti_svvh_generic_type of \sll\ : constant is 1;
attribute mti_svvh_generic_type of lw : constant is 1;
attribute mti_svvh_generic_type of sw : constant is 1;
attribute mti_svvh_generic_type of jmp : constant is 1;
attribute mti_svvh_generic_type of jr : constant is 1;
attribute mti_svvh_generic_type of bgt : constant is 1;
-- This module cannot be connected to/from
-- VHDL because it has unnamed ports.
end InstrucDecoder;
| mit |
rccoder/CPU-Summer-Term-HIT | chapter3/serial.vhd | 1 | 2580 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:50 07/16/2015
-- Design Name:
-- Module Name: serial - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity serial is
port(
serialdata,clk,csn,wrn,rdn:in std_logic;
addr:in std_logic_vector(1 downto 0);
data:inout std_logic_vector(7 downto 0);
intn:out std_logic
);
end serial;
architecture Behavioral of serial is
component count4 is
port(
clk : in std_logic;
clrn : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end component ;
component ctrl is
port(
d9, d11 : in std_logic;
sq7, sq6 : in std_logic;
rq : in std_logic_vector(7 downto 0);
clrn : inout std_logic;
start : out std_logic;
serial, clk : in std_logic;
csn, wrn, rdn : in std_logic;
addr : in std_logic_vector(1 downto 0);
data : inout std_logic_vector(7 downto 0);
intn : out std_logic
);
end component;
component decode4 is
port(
d : in std_logic_vector(3 downto 0);
enable : in std_logic;
q8, q9, q11 : out std_logic
);
end component;
component reg8 is
port(
clrn, clk : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0)
);
end component;
component sreg is
port(
clk, clrn, serial : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end component;
signal c:std_logic_vector(3 downto 0);
signal start,t8,t9,t11,clrn:std_logic;
signal tdata,treg:std_logic_vector(7 downto 0);
begin
unit1: count4 port map(clk => clk, clrn => start, q => c);
unit2: decode4 port map(d => c, enable => start, q8 => t8, q9 => t9, q11 => t11);
unit3: sreg port map(clk => clk, clrn => start, serial => serialdata, q => treg);
unit4: reg8 port map(clrn => clrn, clk => t8, d => treg, q => tdata);
unit5: ctrl port map(d9 => t9, d11 => t11, sq6 => treg(6), sq7 => treg(7), rq => tdata, clrn => clrn, start => start, serial => serialdata, clk => clk, csn => csn, wrn => wrn, rdn => rdn, addr => addr, data => data, intn => intn);
end Behavioral;
| mit |
rccoder/CPU-Summer-Term-HIT | CPU/write_back.vhd | 1 | 2544 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:39 07/28/2015
-- Design Name:
-- Module Name: write_back - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity write_back is
Port (
PCin:in std_logic_vector(15 downto 0); --½ÓÊÕȡָģ¿é´«³öµÄPC£¬ÓÃÓÚ0ÌøתºÍÖ±½ÓÌøת
t : in STD_LOGIC; -- »ØдʹÄÜ
Rtemp : in STD_LOGIC_VECTOR (7 downto 0); -- ½ÓÊÕÀ´×Ô´æ´¢¹ÜÀíÄ£¿éµÄ¼Ä´æÆ÷
IR : in STD_LOGIC_VECTOR (15 downto 0); -- ½ÓÊÕȡָģ¿é´«³öµÄIR
--z:in STD_LOGIC; --½ÓÊÕALU´«³öµÄz
cy:in STD_LOGIC; --½ÓÊÕALU´«³öµÄ½øλ
Rupdate : out STD_LOGIC; -- ¼Ä´æÆ÷»ØдʹÄÜÐźÅ
Rdata : out STD_LOGIC_VECTOR (7 downto 0); -- ALU Êä³öµÄ¼Ä´æÆ÷»ØдÊý¾Ý
PCupdate : out STD_LOGIC; -- PC »ØдʹÄÜÐͺÅ
PCnew : out STD_LOGIC_VECTOR (15 downto 0) --Êä³öPC»ØдµÄÖµ
);
end write_back;
architecture Behavioral of write_back is
--signal tempa:std_logic_vector(15 downto 0);
--signal tempb:std_logic_vector(15 downto 0);
begin
-- tempa<="00000000"&(IR(7 downto 0));
process(t, cy, IR)
begin
if t='1' then
case IR(15 downto 11) is
when "10001" =>
Rupdate <= '0'; --jmp
PCupdate <= '1';
PCnew <= "00000000"&(IR(7 downto 0));
when "10000" => --jz
Rupdate <= '0';
if (Rtemp(7 downto 0) = "00000000") then
--if z='1' then
PCnew <= "00000000"&(IR(7 downto 0));
PCupdate <= '1';
else
PCupdate<='0';
end if;
when "11000" =>null;--STA
when others =>
Rupdate<='1';
PCupdate <= '0';
Rdata(7 downto 0)<= Rtemp(7 downto 0);
end case;
else PCupdate<='0';Rupdate<='0';
end if;
end process;
end Behavioral;
| mit |
maikmerten/riscv-tomthumb | boards/de0-nano/vhdl/wizpll/wizpll_vga.vhd | 1 | 14872 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll_vga.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY wizpll_vga IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END wizpll_vga;
ARCHITECTURE SYN OF wizpll_vga IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2000,
clk0_duty_cycle => 50,
clk0_multiply_by => 1007,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=wizpll_vga",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "wizpll_vga.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2000"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_vga_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| mit |
maikmerten/riscv-tomthumb | src/vhdl/spi/spirom_wb8.vhd | 1 | 2506 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity spirom_wb8 is
Port(
-- bus signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic;
-- SPI signal lines
I_spi_miso: in std_logic := '0';
O_spi_sel: out std_logic := '1';
O_spi_clk: out std_logic := '0';
O_spi_mosi: out std_logic := '0'
);
end spirom_wb8;
architecture Behavioral of spirom_wb8 is
signal tx_data, rx_data: std_logic_vector(7 downto 0) := X"00";
signal tx_start: boolean := false;
signal spi_busy: boolean := true;
begin
spimaster_instance: entity work.spimaster port map(
I_clk => CLK_I,
I_tx_data => tx_data,
I_tx_start => tx_start,
I_spi_miso => I_spi_miso,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi,
O_rx_data => rx_data,
O_busy => spi_busy
);
process(CLK_I)
type ctrlstates is (IDLE, OPCODE, ADDR1, ADDR2, ADDR3, READ1, READ2, WAITSTATE, TX1, TX2);
variable state, retstate: ctrlstates := IDLE;
variable doack: std_logic := '0';
begin
if rising_edge(CLK_I) then
doack := '0';
O_spi_sel <= '0'; -- select device
case state is
when IDLE =>
O_spi_sel <= '1'; -- deselect device
if not spi_busy and STB_I = '1' then
state := OPCODE;
end if;
when OPCODE =>
tx_data <= X"03";
state := TX1;
retstate := ADDR1;
when ADDR1 =>
tx_data <= ADR_I(23 downto 16);
state := TX1;
retstate := ADDR2;
when ADDR2 =>
tx_data <= ADR_I(15 downto 8);
state := TX1;
retstate := ADDR3;
when ADDR3 =>
tx_data <= ADR_I(7 downto 0);
state := TX1;
retstate := READ1;
when READ1 =>
tx_data <= X"00";
state := TX1;
retstate := READ2;
when READ2 =>
doack := '1';
state := WAITSTATE;
when WAITSTATE =>
state := IDLE;
when TX1 =>
-- signal beginning of transmission
tx_start <= true;
-- wait for ack that transmission is in progress
if spi_busy then
state := TX2;
end if;
when TX2 =>
tx_start <= false;
-- wait until transmission has ended
if not spi_busy then
state := retstate;
end if;
end case;
end if;
DAT_O <= rx_data;
ACK_O <= doack and STB_I;
end process;
end Behavioral;
| mit |
maikmerten/riscv-tomthumb | src/vhdl/spi/spiromram_wb8.vhd | 1 | 4621 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity spiromram_wb8 is
generic(
ADDRLEN: integer := 12
);
port(
-- bus signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_I: in std_logic_vector(7 downto 0);
RST_I: in std_logic;
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic;
-- SPI signal lines
I_spi_miso: in std_logic := '0';
O_spi_sel: out std_logic := '1';
O_spi_clk: out std_logic := '0';
O_spi_mosi: out std_logic := '0'
);
end spiromram_wb8;
architecture Behavioral of spiromram_wb8 is
type store_t is array(0 to (2**ADDRLEN)-1) of std_logic_vector(7 downto 0);
signal ram: store_t := (others => X"00");
attribute ramstyle : string;
attribute ramstyle of ram : signal is "no_rw_check";
signal tx_data, rx_data: std_logic_vector(7 downto 0) := X"00";
signal tx_start: boolean := false;
signal spi_busy: boolean := true;
begin
spimaster_instance: entity work.spimaster port map(
I_clk => CLK_I,
I_tx_data => tx_data,
I_tx_start => tx_start,
I_spi_miso => I_spi_miso,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi,
O_rx_data => rx_data,
O_busy => spi_busy
);
process(CLK_I)
type ctrlstates is (RESET, FILLRAM1, FILLRAM2, IDLE, READ1, READ2, READ3, READ4, READ5, READ6, READ7, TX1, TX2);
variable state, retstate: ctrlstates := RESET;
variable ack: std_logic := '0';
variable addr: std_logic_vector(23 downto 0) := X"000000";
variable init: std_logic := '1';
variable initaddr: std_logic_vector(ADDRLEN-1 downto 0);
begin
if rising_edge(CLK_I) then
ack := '0';
O_spi_sel <= '0'; -- select device
if RST_I = '1' then
state := RESET;
end if;
case state is
when RESET =>
O_spi_sel <= '1'; -- deselect device
init := '1';
initaddr := (others => '0');
state := FILLRAM1;
when FILLRAM1 =>
addr := (others => '0');
addr(ADDRLEN-1 downto 0) := initaddr;
state := READ1;
when FILLRAM2 =>
O_spi_sel <= '1'; -- deselect device
ram(to_integer(unsigned(initaddr))) <= rx_data;
-- increase address counter
initaddr := std_logic_vector((unsigned(initaddr) + 1));
if unsigned(initaddr) = 0 then
-- init address wrapped back to zero, we're finished
init := '0';
state := IDLE;
else
-- fetch next byte to initialize RAM
state := FILLRAM1;
end if;
when IDLE =>
O_spi_sel <= '1'; -- deselect device
if ADR_I(24) = '0' then
---------------
-- access RAM
---------------
if STB_I = '1' then
if(WE_I = '1') then
ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0)))) <= DAT_I;
else
DAT_O <= ram(to_integer(unsigned(ADR_I(ADDRLEN-1 downto 0))));
end if;
ack := '1';
end if;
else
--------------
-- access ROM
--------------
if not spi_busy and STB_I = '1' then
addr := ADR_I(23 downto 0);
state := READ1;
end if;
end if;
when READ1 =>
-- start reading SPI ROM by submitting the READ opcode
tx_data <= X"03";
state := TX1;
retstate := READ2;
when READ2 =>
-- transmit first part of the address
tx_data <= addr(23 downto 16);
state := TX1;
retstate := READ3;
when READ3 =>
-- transmit second part of the address
tx_data <= addr(15 downto 8);
state := TX1;
retstate := READ4;
when READ4 =>
-- transmit third part of the address
tx_data <= addr(7 downto 0);
state := TX1;
retstate := READ5;
when READ5 =>
-- read byte from SPI ROM (transmitted data doesn't matter)
tx_data <= X"00";
state := TX1;
retstate := READ6;
when READ6 =>
-- output read data and ACK
ack := '1';
DAT_O <= rx_data;
state := READ7;
when READ7 =>
if init = '0' then
state := IDLE;
else
state := FILLRAM2;
end if;
when TX1 =>
-- signal beginning of transmission
tx_start <= true;
-- wait for ack that transmission is in progress
if spi_busy then
state := TX2;
end if;
when TX2 =>
tx_start <= false;
-- wait until transmission has ended
if not spi_busy then
state := retstate;
end if;
end case;
end if;
ACK_O <= ack and STB_I and (not init);
end process;
end Behavioral;
| mit |
maikmerten/riscv-tomthumb | src/vhdl/attic/ram_init.vhd | 1 | 537 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package ram_init is
constant ADDRLEN : integer := 12; -- bits for number of 32 bit words in memory
type store_t is array(0 to (2**ADDRLEN)-1) of std_logic_vector(31 downto 0);
constant RAM_INIT : store_t := (
-- slow binary LED counter loop.s
X"b3620000",
X"23205020",
X"13031000",
X"b7030010",
X"83220020",
X"b3826200",
X"23205020",
X"93d20201",
X"23a05300",
X"93025000",
X"b3826240",
X"e3de02fe",
X"6ff01ffe",
others => X"00000000"
);
end package ram_init;
| mit |
jpcofr/PDUAMaude | PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/pdua.vhdl | 1 | 5038 | -- *******************************************************
-- ** PDUA **
-- ** PROCESADOR DIDACTICO **
-- ** Arquitectura y Diseno de Sistemas Digitales **
-- ** UNIVERSIDAD DE LOS ANDES **
-- *******************************************************
-- ** Version 0.0 Arquitectura basica. **
-- ** Por: Mauricio Guerrero H. **
-- ** Junio 2007 **
-- ** Revision 0.1 Noviembre 2007 **
-- ** Conjunto de Instrucciones **
-- ** Memoria Doble Puerto **
-- ** Por: Diego Mendez Chaves **
-- ** Mauricio Guerrero H. **
-- ** Revision 0.2 Marzo de 2008 **
-- ** ALU BIT_SLICE **
-- ** Por: Mauricio Guerrero H. **
-- *******************************************************
-- Descripcion: CLK| |Rst_n
-- ____|____|_____
-- | |
-- INT -->| |<-- Bus_DATA_in
-- IOM <--| |--> Bus_DATA_out
-- RW <--| |--> Bus_DIR
-- |_______________|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pdua is
Port ( clk : in std_logic;
rst_n : in std_logic;
int : in std_logic;
iom : out std_logic; -- IO=0,M=1
rw : out std_logic; -- R=0,W=1
bus_dir : out std_logic_vector(7 downto 0);
bus_data_in : in std_logic_vector(7 downto 0);
bus_data_out : out std_logic_vector(7 downto 0));
end pdua;
architecture Behavioral of pdua is
component ctrl is
Port ( clk : in std_logic;
rst_n : in std_logic;
urst_n : in std_logic;
HRI : in std_logic;
INST : in std_logic_vector(4 downto 0);
C : in std_logic;
Z : in std_logic;
N : in std_logic;
P : in std_logic;
INT : in std_logic;
COND : in std_logic_vector(2 downto 0);
DIR : in std_logic_vector(2 downto 0);
UI : out std_logic_vector(24 downto 0));
end component;
component banco is
Port ( CLK : in std_logic;
RESET_n : in std_logic;
HR : in std_logic;
SC,SB : in std_logic_vector(2 downto 0);
BUSC : in std_logic_vector(7 downto 0);
BUSA,BUSB : out std_logic_vector(7 downto 0)
);
end component;
component ALU is
Port (CLK,HF: in std_logic;
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
SELOP : in std_logic_vector(2 downto 0);
DESP : in std_logic_vector(1 downto 0);
S : inout std_logic_vector(7 downto 0);
C,N,Z,P : out std_logic
);
end component;
component MAR is
Port ( CLK : in std_logic;
BUS_DIR: out std_logic_vector(7 downto 0);
BUS_C : in std_logic_vector(7 downto 0);
HMAR : in std_logic);
end component;
component MDR is
Port ( DATA_EX_in : in std_logic_vector(7 downto 0);
DATA_EX_out : out std_logic_vector(7 downto 0);
DATA_ALU : in std_logic_vector(7 downto 0);
DATA_C : out std_logic_vector(7 downto 0);
HMDR : in std_logic;
RD_WR : in std_logic);
end component;
signal hf, hr, urst_n, hri, C, Z, N, P ,HMAR, HMDR : std_logic;
signal sc, sb, cond : std_logic_vector(2 downto 0);
signal func,dir : std_logic_vector(2 downto 0);
signal busa, busb, busc, bus_alu : std_logic_vector(7 downto 0);
signal desp : std_logic_vector(1 downto 0);
signal ui : std_logic_vector(24 downto 0);
begin
-- Microinstruccion
hf <= ui(24); -- Habilitador de almacenamiento de banderas
sb <= ui(23 downto 21); -- Selector bus B (salida)
func <= ui(20 downto 18); -- Selector funcion ALU
desp <= ui(17 downto 16); -- Habilitador desplazamiento
sc <= ui(15 downto 13); -- Selector bus C (entrada)
hr <= ui(12); -- Habilitador registro destino
HMAR <= ui(11); -- Habilitador MAR
HMDR <= ui(10); -- Habilitador MDR
RW <= ui(9); -- Read/Write 0/1
iom <= ui(8); -- IO/MEM 0/1
hri <= ui(7); -- Habilitador registro instruccion
urst_n <= ui(6); -- Reset de microcontador
cond <= ui(5 downto 3); -- Condicion de salto
dir <= ui(2 downto 0); -- Micro-offset de salto
u1: ctrl port map (clk,rst_n,urst_n,hri,busc(7 downto 3),C,Z,N,P,int,cond,dir,ui);
u2: banco port map (clk, rst_n, hr, sc, sb, busc, busa, busb);
u3: alu port map (clk,hf,busa, busb, func, desp, bus_alu, C, N, Z, P );
u4: mar port map (clk, bus_dir, busc, HMAR );
u5: mdr port map (bus_data_in,bus_data_out,bus_alu,busc,HMDR,ui(9));
end Behavioral;
| mit |
maikmerten/riscv-tomthumb | src/vhdl/cpu/bus_wb8_tb.vhd | 1 | 4670 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_wb8_tb is
end bus_wb8_tb;
architecture Behavior of bus_wb8_tb is
component bus_wb8
Port(
I_en: in std_logic;
I_op: in busops_t; -- memory opcodes
I_addr: in std_logic_vector(31 downto 0); -- address
I_data: in std_logic_vector(31 downto 0); -- data to be stored on write ops
O_data : out std_logic_vector(31 downto 0);
O_busy: out std_logic := '0';
-- wired to outside world, RAM, devices etc.
-- naming of signals taken from Wishbone B4 spec
CLK_I: in std_logic := '0';
ACK_I: in std_logic := '0';
DAT_I: in std_logic_vector(7 downto 0);
RST_I: in std_logic := '0';
ADR_O: out std_logic_vector(31 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
CYC_O: out std_logic := '0';
STB_O: out std_logic := '0';
WE_O: out std_logic := '0'
);
end component;
signal I_en: std_logic;
signal I_op: busops_t; -- memory opcodes
signal I_addr: std_logic_vector(31 downto 0); -- address
signal I_data: std_logic_vector(31 downto 0); -- data to be stored on write ops
signal O_data: std_logic_vector(31 downto 0);
signal O_busy: std_logic := '0';
signal O_clk: std_logic := '0';
signal O_reset: std_logic := '0';
signal CLK_I: std_logic := '0';
signal ACK_I: std_logic := '0';
signal DAT_I: std_logic_vector(7 downto 0);
signal RST_I: std_logic := '0';
signal ADR_O: std_logic_vector(31 downto 0);
signal DAT_O: std_logic_vector(7 downto 0);
signal CYC_O: std_logic := '0';
signal STB_O: std_logic := '0';
signal WE_O: std_logic := '0';
constant I_clk_period : time := 10 ns;
begin
uut: bus_wb8 port map(
I_en => I_en,
I_op => I_op,
I_addr => I_addr,
I_data => I_data,
O_data => O_data,
O_busy => O_busy,
CLK_I => CLK_I,
ACK_I => ACK_I,
DAT_I => DAT_I,
RST_I => RST_I,
ADR_O => ADR_O,
DAT_O => DAT_O,
CYC_O => CYC_O,
STB_O => STB_O,
WE_O => WE_O
);
proc_clock: process
begin
CLK_I <= '0';
wait for I_clk_period/2;
CLK_I <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
-- test read of words
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READW;
DAT_I <= X"CC";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"CCCCCCCC" report "wrong data read" severity failure;
I_en <= '0';
-- test read of half words and sign extension (here: sign set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READH;
DAT_I <= X"CC";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"FFFFCCCC" report "wrong data read" severity failure;
I_en <= '0';
-- test read of half words and sign extension (here sign not set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READH;
DAT_I <= X"0F";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"00000F0F" report "wrong data read" severity failure;
I_en <= '0';
-- test read of byte and sign extension (here: sign set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READB;
DAT_I <= X"CC";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"FFFFFFCC" report "wrong data read" severity failure;
I_en <= '0';
-- test read of byte and sign extension (here sign not set)
wait until falling_edge(CLK_I);
I_en <= '1';
I_addr <= X"CAFE0000";
I_op <= BUS_READB;
DAT_I <= X"0F";
ACK_I <= '1';
wait until falling_edge(O_busy);
assert O_data = X"0000000F" report "wrong data read" severity failure;
I_en <= '0';
-- test writing a word
wait until falling_edge(CLK_I);
I_en <= '1';
I_data <= X"CAFEBABE";
I_addr <= X"CAFE0000";
I_op <= BUS_WRITEW;
ACK_I <= '1';
wait until falling_edge(O_busy);
assert DAT_O = X"CA" report "wrong data written" severity failure;
I_en <= '0';
-- test writing a half word
wait until falling_edge(CLK_I);
I_en <= '1';
I_data <= X"CAFEBABE";
I_addr <= X"CAFE0000";
I_op <= BUS_WRITEH;
ACK_I <= '1';
wait until falling_edge(O_busy);
assert DAT_O = X"BA" report "wrong data written" severity failure;
I_en <= '0';
-- test writing a byte
wait until falling_edge(CLK_I);
I_en <= '1';
I_data <= X"CAFEBABE";
I_addr <= X"CAFE0000";
I_op <= BUS_WRITEB;
ACK_I <= '1';
wait until falling_edge(O_busy);
assert DAT_O = X"BE" report "wrong data written" severity failure;
I_en <= '0';
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
| mit |
maikmerten/riscv-tomthumb | src/vhdl/ram/bus_ram_toplevel_tb.vhd | 1 | 3335 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_ram_toplevel_tb is
end bus_ram_toplevel_tb;
architecture Behavior of bus_ram_toplevel_tb is
component bus_ram_toplevel
Port(
I_clk: in std_logic;
I_reset: in std_logic;
I_en: in std_logic;
I_op: in busops_t; -- memory opcodes
I_iaddr: in std_logic_vector(31 downto 0); -- instruction address, provided by PCU
I_daddr: in std_logic_vector(31 downto 0); -- data address, provided by ALU
I_data: in std_logic_vector(31 downto 0); -- data to be stored on write ops
I_mem_imem: in std_logic := '0'; -- denotes if instruction memory is accessed (signal from control unit)
O_data : out std_logic_vector(31 downto 0);
O_busy: out std_logic := '0';
O_clk: out std_logic := '0';
O_reset: out std_logic := '0'
);
end component;
signal I_clk, I_reset, I_en, I_mem_imem, O_busy, O_clk, O_reset: std_logic := '0';
signal I_iaddr, I_daddr, I_data, O_data: std_logic_vector(31 downto 0) := X"00000000";
signal I_op: busops_t;
constant I_clk_period : time := 10 ns;
begin
uut: bus_ram_toplevel port map(
I_clk => I_clk,
I_reset => I_reset,
I_en => I_en,
I_op => I_op,
I_iaddr => I_iaddr,
I_daddr => I_daddr,
I_data => I_data,
I_mem_imem => I_mem_imem,
O_data => O_data,
O_busy => O_busy,
O_clk => O_clk,
O_reset => O_reset
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
wait until falling_edge(I_clk);
I_en <= '1';
I_daddr <= X"00000000";
I_op <= BUS_READW;
wait until falling_edge(O_busy);
I_en <= '0';
-- test writing a word
wait until falling_edge(I_clk);
I_en <= '1';
I_data <= X"CAFEBABE";
I_daddr <= X"CAFE0000";
I_mem_imem <= '0';
I_op <= BUS_WRITEW;
wait until falling_edge(O_busy);
I_en <= '0';
-- read a word from memory, check if contents match what we've written
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READW;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"CAFEBABE" report "wrong data read" severity failure;
-- read a half word from memory, check sign extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READH;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"FFFFBABE" report "wrong data read" severity failure;
-- read a half word from memory, check zero extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READHU;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"0000BABE" report "wrong data read" severity failure;
-- read a byte from memory, check sign extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READB;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"FFFFFFBE" report "wrong data read" severity failure;
-- read a byte from memory, check zero extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READBU;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"000000BE" report "wrong data read" severity failure;
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
| mit |
maikmerten/riscv-tomthumb | src/vhdl/cpu/registers.vhd | 1 | 1437 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity registers is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_op: in regops_t;
I_selS1: in std_logic_vector(4 downto 0);
I_selS2: in std_logic_vector(4 downto 0);
I_selD: in std_logic_vector(4 downto 0);
I_data: in std_logic_vector(XLEN-1 downto 0);
O_dataS1: out std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO;
O_dataS2: out std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO
);
end registers;
architecture Behavioral of registers is
type store_t is array(0 to 31) of std_logic_vector(XLEN-1 downto 0);
signal regs: store_t := (others => X"00000000");
attribute ramstyle : string;
attribute ramstyle of regs : signal is "no_rw_check";
begin
process(I_clk, I_en, I_op, I_selS1, I_selS2, I_selD, I_data)
variable data: std_logic_vector(XLEN-1 downto 0);
begin
if rising_edge(I_clk) and I_en = '1' then
data := X"00000000";
if I_op = REGOP_WRITE and I_selD /= "00000" then
data := I_data;
end if;
-- this is a pattern that Quartus RAM synthesis understands
-- as *not* being read-during-write (with no_rw_check attribute)
if I_op = REGOP_WRITE then
regs(to_integer(unsigned(I_selD))) <= data;
else
O_dataS1 <= regs(to_integer(unsigned(I_selS1)));
O_dataS2 <= regs(to_integer(unsigned(I_selS2)));
end if;
end if;
end process;
end Behavioral; | mit |
maikmerten/riscv-tomthumb | src/vhdl/cpu/bus_wb8.vhd | 1 | 4822 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_wb8 is
Port(
-- wired to CPU core
I_en: in std_logic;
I_op: in busops_t; -- bus opcodes
I_addr: in std_logic_vector(31 downto 0); -- address
I_data: in std_logic_vector(31 downto 0); -- data to be stored on write ops
O_data : out std_logic_vector(31 downto 0);
O_busy: out std_logic := '0';
-- wired to outside world, RAM, devices etc.
-- naming of signals taken from Wishbone B4 spec
CLK_I: in std_logic := '0';
ACK_I: in std_logic := '0';
DAT_I: in std_logic_vector(7 downto 0);
RST_I: in std_logic := '0';
ADR_O: out std_logic_vector(31 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
CYC_O: out std_logic := '0';
STB_O: out std_logic := '0';
WE_O: out std_logic := '0'
);
end bus_wb8;
architecture Behavioral of bus_wb8 is
type control_states is (IDLE, READ_START, READ_FINISH, WRITE_START, WRITE_FINISH);
begin
process(CLK_I)
variable state: control_states := IDLE;
variable buf: std_logic_vector(31 downto 0) := X"00000000";
variable byte, byte_target: integer range 0 to 3;
variable zeroextend: std_logic := '0';
begin
if rising_edge(CLK_I) then
if I_en = '1' then
--------------------------------------
-- when idle, evaluate requested memop
--------------------------------------
if state = IDLE then
O_busy <= '1';
zeroextend := '0';
byte := 0; -- start at byte 0
case I_op is
when BUS_READW =>
byte_target := 3; -- read 4 bytes
state := READ_START;
when BUS_READH =>
byte_target := 1; -- read 2 bytes
state := READ_START;
when BUS_READHU =>
byte_target := 1; -- read 2 bytes
zeroextend := '1';
state := READ_START;
when BUS_READB =>
byte_target := 0; -- read 1 byte
state := READ_START;
when BUS_READBU =>
byte_target := 0; -- read 1 byte
zeroextend := '1';
state := READ_START;
when BUS_WRITEW =>
byte_target := 3; -- write 4 bytes
state := WRITE_START;
when BUS_WRITEH =>
byte_target := 1; -- write 2 bytes
state := WRITE_START;
when BUS_WRITEB =>
byte_target := 0; -- write 1 byte
state := WRITE_START;
end case;
end if;
-- compute memory address
ADR_O <= std_logic_vector(unsigned(I_addr) + byte);
-----------------------------------
-- execute read or write operations
-----------------------------------
case state is
when READ_START =>
WE_O <= '0';
CYC_O <= '1';
STB_O <= '1';
state := READ_FINISH;
when READ_FINISH =>
if ACK_I = '1' then
STB_O <= '0';
case byte is
when 0 =>
if zeroextend = '1' then
buf := X"000000" & DAT_I;
else
buf := std_logic_vector(resize(signed(DAT_I), buf'length));
end if;
when 1 =>
if zeroextend = '1' then
buf := X"0000" & DAT_I & buf(7 downto 0);
else
buf := std_logic_vector(resize(signed(DAT_I & buf(7 downto 0)), buf'length));
end if;
when 2 =>
buf(23 downto 16) := DAT_I;
when 3 =>
buf(31 downto 24) := DAT_I;
end case;
if byte < byte_target then
-- we didn't read all bytes yet
byte := byte + 1;
state := READ_START;
else
-- we read all data, signal to CPU we're ready and go to idle state
O_busy <= '0';
-- bus cycle finished
CYC_O <= '0';
state := IDLE;
end if;
end if;
when WRITE_START =>
WE_O <= '1';
CYC_O <= '1';
STB_O <= '1';
case byte is
when 0 =>
DAT_O <= I_data(7 downto 0);
when 1 =>
DAT_O <= I_data(15 downto 8);
when 2 =>
DAT_O <= I_data(23 downto 16);
when 3 =>
DAT_O <= I_data(31 downto 24);
end case;
state := WRITE_FINISH;
when WRITE_FINISH =>
if ACK_I = '1' then
WE_O <= '0';
STB_O <= '0';
if byte < byte_target then
-- we did not write all bytes yet
byte := byte + 1;
state := WRITE_START;
else
-- we wrote all data, signal to CPU we're ready and go to idle state
O_busy <= '0';
-- bus cycle finished
CYC_O <= '0';
state := IDLE;
end if;
end if;
when others =>
null;
end case;
end if;
O_data <= buf;
if RST_I = '1' then
state := IDLE;
CYC_O <= '0';
STB_O <= '0';
WE_O <= '0';
O_busy <= '0';
end if;
end if;
end process;
end Behavioral; | mit |
miree/vhdl_cores | fifo/fifo_passive_out/testbench.vhd | 2 | 3978 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- package with component to test on this testbench
use work.fifo_pkg.all;
use work.guarded_fifo_pkg.all;
entity testbench is
end entity;
architecture simulation of testbench is
-- clock generation
constant clk_period : time := 5 ns;
-- signals to connect to fifo
constant depth : integer := 2; -- the number of fifo entries is 2**depth
constant bit_width : integer := 32; -- number of bits in each entry
signal clk, rst : std_logic;
signal d, q : std_logic_vector ( bit_width-1 downto 0 );
signal push, pop : std_logic;
signal full, empty : std_logic;
-- the value that is pushed to the fifo
signal ctr : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
-- the value that is expected to be read from the fifo (initialized with -1)
signal expected : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
begin
-- instantiate device under test (dut)
dut : work.guarded_fifo_pkg.guarded_fifo
generic map (
depth => depth ,
bit_width => bit_width
)
port map (
clk_i => clk,
rst_i => rst,
d_i => ctr,
q_o => q,
push_i => push,
pop_i => pop,
full_o => full,
empty_o => empty
);
clk_gen: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
rst_initial: process
begin
rst <= '1';
wait for clk_period*20;
rst <= '0';
wait;
end process;
p_read_write : process
begin
push <= '0';
pop <= '0';
--=============================
-- fill fifo
--=============================
--wait for clk_period*40.5;
wait until falling_edge(rst);
for i in 0 to 12 loop
-- convert an integer into std_logic_vector
-- i_slv := std_logic_vector(to_unsigned(i,8));
wait until rising_edge(clk);
d <= ctr;
push <= '1';
if to_integer(unsigned(ctr)) = 2 then
pop <= '1';
else
pop <= '0';
end if;
--push <= '0';
-- wait for clk_period*5;
end loop;
push <= '0';
--=============================
-- empty fifo
--=============================
wait for clk_period*40;
for i in 0 to 13 loop
pop <= '1';
wait for clk_period;
pop <= '0';
wait for clk_period*5;
-- expected := std_logic_vector(unsigned(expected) + 1);
-- typecasts can be avoided when using the library use ieee.std_logic_unsigned.all;
end loop;
for i in 0 to 12 loop
-- convert an integer into std_logic_vector
-- i_slv := std_logic_vector(to_unsigned(i,8));
wait until rising_edge(clk);
d <= ctr;
push <= '1';
--push <= '0';
-- wait for clk_period*5;
end loop;
push <= '0';
end process;
check: process
begin
wait until rising_edge(clk);
if empty = '0' and pop = '1' then
assert unsigned(q) = unsigned(expected)
report "We didn't get what we expect ("
& integer'image(to_integer(unsigned(q)))
& " /= "
& integer'image(to_integer(unsigned(expected)))
& ")";
end if;
end process;
-- this process increments the counter (that is the value which is written to the fifo)
-- only on rising clock edges when the acknowledge signal was sent back from the fifo, i.e.
-- if a value was successfully pushed into the fifo.
p_increment_ctr : process(clk)
begin
if rising_edge(clk) then
if full = '0' and push = '1' then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
end if;
end process;
p_increment_expected : process(clk)
begin
if rising_edge(clk) then
if empty = '0' and pop = '1' then
expected <= std_logic_vector(unsigned(expected) + 1);
end if;
end if;
end process;
end architecture; | mit |
miree/vhdl_cores | wishbone/wbp_mux.vhd | 1 | 8381 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- S S
-- |/
-- M
entity wbp_2s1m is
port (
clk_i : in std_logic;
slaves_i : in t_wbp_slave_in_array(0 to 1);
slaves_o : out t_wbp_slave_out_array(0 to 1);
master_o : out t_wbp_master_out;
master_i : in t_wbp_master_in
);
end entity;
architecture rtl of wbp_2s1m is
type t_state is (s_cyc0, s_cyc1);
signal state : t_state := s_cyc0;
signal slave0_prio : boolean;
begin
slave0_prio <= state = s_cyc0 or (state = s_cyc1 and slaves_i(1).cyc = '0');
master_o <= slaves_i(0) when slave0_prio and slaves_i(0).cyc = '1'
else slaves_i(1) when slaves_i(1).cyc = '1'
else (cyc=>'0',stb=>'0',we=>'-',sel=>(others=>'-'),adr=>(others=>'-'),dat=>(others=>'-'));
slaves_o(0) <= master_i when slave0_prio and slaves_i(0).cyc = '1'
else (ack=>'0',err=>'0',rty=>'0',stall=>'1',dat=>(others=>'-'));
slaves_o(1) <= master_i when state = s_cyc1 or (slaves_i(1).cyc = '1' and slaves_i(0).cyc = '0')
else (ack=>'0',err=>'0',rty=>'0',stall=>'1',dat=>(others=>'-'));
process
begin
wait until rising_edge(clk_i);
case state is
when s_cyc0 =>
if slaves_i(1).cyc = '1' and slaves_i(0).cyc = '0' then
state <= s_cyc1;
end if;
when s_cyc1 =>
if slaves_i(1).cyc = '0' then
state <= s_cyc0;
end if;
end case;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- S
-- /|
-- M M
entity wbp_1s2m is
generic (
adr_bit : natural
);
port (
clk_i : in std_logic;
slave_i : in t_wbp_slave_in;
slave_o : out t_wbp_slave_out;
masters_o : out t_wbp_master_out_array(0 to 1);
masters_i : in t_wbp_master_in_array(0 to 1)
);
end entity;
architecture rtl of wbp_1s2m is
signal master_o : t_wbp_master_out := c_wbp_master_out_init;
begin
master_o.cyc <= slave_i.cyc;
master_o.stb <= slave_i.stb;
master_o.we <= slave_i.we;
master_o.adr(31 downto adr_bit ) <= (others => '0');
master_o.adr(adr_bit-1 downto 0) <= slave_i.adr(adr_bit-1 downto 0);
master_o.dat <= slave_i.dat;
master_o.sel <= slave_i.sel;
masters_o(0) <= master_o when unsigned(slave_i.adr(31 downto adr_bit)) = 0
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
masters_o(1) <= master_o when unsigned(slave_i.adr(31 downto adr_bit)) /= 0
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
slave_o <= masters_i(0) when unsigned(slave_i.adr(31 downto adr_bit)) = 0
else masters_i(1);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- This implementation stalls if the adressed slave changes while
-- there are non-acked stbs on the previously adressed slave.
-- This is achieved by counting number of open stbs and costs more resources
-- S
-- /|
-- M M
entity wbp_1s2m_protected is
generic (
adr_bit : natural
);
port (
clk_i : in std_logic;
slave_i : in t_wbp_slave_in;
slave_o : out t_wbp_slave_out;
masters_o : out t_wbp_master_out_array(0 to 1);
masters_i : in t_wbp_master_in_array(0 to 1)
);
end entity;
architecture rtl of wbp_1s2m_protected is
type t_state is (s_idle, s_cyc0, s_cyc1);
signal state : t_state := s_idle;
signal sel_0, sel_1, stall: boolean := false;
signal inc_cnt, dec_cnt: boolean := false;
signal cnt : integer := 0;
begin
masters_o(0) <= slave_i when sel_0 and not stall
else (cyc=>'1',stb=>'0',we=>'-',adr=>(others=>'0'),dat=>(others=>'-'),sel=>(others=>'-')) when sel_0 and stall
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
masters_o(1) <= slave_i when sel_1 and not stall
else (cyc=>'1',stb=>'0',we=>'-',adr=>(others=>'0'),dat=>(others=>'-'),sel=>(others=>'-')) when sel_1 and stall
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
slave_o <= (ack=>masters_i(0).ack,err=>masters_i(0).err,rty=>masters_i(0).rty,stall=>slave_i.cyc,dat=>masters_i(0).dat) when sel_0 and stall
else (ack=>masters_i(1).ack,err=>masters_i(1).err,rty=>masters_i(1).rty,stall=>slave_i.cyc,dat=>masters_i(1).dat) when sel_1 and stall
else masters_i(0) when sel_0
else masters_i(1) when sel_1
else (ack=>'-',err=>'-',rty=>'-',stall=>'-',dat=>(others=>'-'));
sel_0 <= (state = s_cyc0 and slave_i.cyc = '1') or
(state = s_idle and slave_i.adr(adr_bit) = '0') or
(state = s_cyc1 and slave_i.adr(adr_bit) = '0' and cnt = 0);
sel_1 <= (state = s_cyc1 and slave_i.cyc = '1') or
(state = s_idle and slave_i.adr(adr_bit) = '1') or
(state = s_cyc0 and slave_i.adr(adr_bit) = '1' and cnt = 0);
stall <= (state = s_cyc0 and slave_i.adr(adr_bit) = '1' and cnt /= 0) or
(state = s_cyc1 and slave_i.adr(adr_bit) = '0' and cnt /= 0);
lock: process
begin
wait until rising_edge(clk_i);
case state is
when s_idle =>
if slave_i.cyc = '1' then
if slave_i.adr(adr_bit) = '0' then
state <= s_cyc0;
else
state <= s_cyc1;
end if;
end if;
when s_cyc0 =>
if slave_i.cyc = '0' then
state <= s_idle;
elsif slave_i.adr(adr_bit) = '1' and ((cnt = 0) or (cnt = 1 and dec_cnt)) then
state <= s_cyc1;
end if;
when s_cyc1 =>
if slave_i.cyc = '0' then
state <= s_idle;
elsif slave_i.adr(adr_bit) = '0' and ((cnt = 0) or (cnt = 1 and dec_cnt)) then
state <= s_cyc0;
end if;
end case;
if inc_cnt then cnt <= cnt+1; end if;
if dec_cnt then cnt <= cnt-1; end if;
end process;
inc_cnt <= (sel_0 and masters_i(0).ack = '0' and masters_i(0).err = '0' and masters_i(0).rty = '0' and slave_i.stb = '1') or
(sel_1 and masters_i(1).ack = '0' and masters_i(1).err = '0' and masters_i(1).rty = '0' and slave_i.stb = '1');
dec_cnt <= (sel_0 and (masters_i(0).ack = '1' or masters_i(0).err = '1' or masters_i(0).rty = '1') and (slave_i.stb = '0' or stall)) or
(sel_1 and (masters_i(1).ack = '1' or masters_i(1).err = '1' or masters_i(1).rty = '1') and (slave_i.stb = '0' or stall));
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- S S
-- |X|
-- M M
--
-- is build like this from basic blocks
-- S S
-- /| |\
-- M M M M
-- S S S S
-- | X |
-- | / \ |
-- |/ \|
-- M M
--
entity wbp_2s2m_crossbar is
generic (
adr_bit : natural
);
port (
clk_i : in std_logic;
slaves_i : in t_wbp_slave_in_array(0 to 1);
slaves_o : out t_wbp_slave_out_array(0 to 1);
masters_o : out t_wbp_master_out_array(0 to 1);
masters_i : in t_wbp_master_in_array(0 to 1)
);
end entity;
architecture rtl of wbp_2s2m_crossbar is
signal intermediate : t_wbp_array(0 to 3);
begin
spread_0: entity work.wbp_1s2m
generic map(adr_bit=>adr_bit)
port map(clk_i=>clk_i,
slave_i=>slaves_i(0),
slave_o=>slaves_o(0),
masters_o(0)=>intermediate(0).mosi,
masters_o(1)=>intermediate(1).mosi,
masters_i(0)=>intermediate(0).miso,
masters_i(1)=>intermediate(1).miso);
spread_1: entity work.wbp_1s2m
generic map(adr_bit=>adr_bit)
port map(clk_i=>clk_i,
slave_i=>slaves_i(1),
slave_o=>slaves_o(1),
masters_o(0)=>intermediate(2).mosi,
masters_o(1)=>intermediate(3).mosi,
masters_i(0)=>intermediate(2).miso,
masters_i(1)=>intermediate(3).miso);
combine_0: entity work.wbp_2s1m
port map(clk_i => clk_i,
slaves_i(0) => intermediate(0).mosi,
slaves_i(1) => intermediate(2).mosi,
slaves_o(0) => intermediate(0).miso,
slaves_o(1) => intermediate(2).miso,
master_o => masters_o(0),
master_i => masters_i(0));
combine_1: entity work.wbp_2s1m
port map(clk_i => clk_i,
slaves_i(0) => intermediate(1).mosi,
slaves_i(1) => intermediate(3).mosi,
slaves_o(0) => intermediate(1).miso,
slaves_o(1) => intermediate(3).miso,
master_o => masters_o(1),
master_i => masters_i(1));
end architecture; | mit |
miree/vhdl_cores | uart/uart.vhd | 1 | 8780 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_pkg is
type t_uart_parallel is record
dat : std_logic_vector(7 downto 0);
stb : std_logic;
stall : std_logic;
end record;
constant c_uart_parallel_init : t_uart_parallel := ((others => '0'), others => '0');
end package;
package body uart_pkg is
end package body;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
generic (
g_clk_freq : integer := 12000000;
g_baud_rate : integer := 9600;
g_bits : integer := 8
);
port (
clk_i : in std_logic;
-- parallel
dat_i : in std_logic_vector(g_bits-1 downto 0);
stb_i : in std_logic;
stall_o : out std_logic;
-- serial
tx_o : out std_logic
);
end entity;
architecture rtl of uart_tx is
subtype bit_index_t is integer range 0 to g_bits+1;
signal bit_index : bit_index_t := 0;
function countup_loop(index : bit_index_t) return bit_index_t is
begin
if index = bit_index_t'high then return 0; end if;
return index + 1;
end function;
subtype wait_count_t is integer range 0 to g_clk_freq / g_baud_rate-1;
signal wait_count : wait_count_t := wait_count_t'high;
function countdown_loop(count : wait_count_t) return wait_count_t is
begin
if count > 0 then return count - 1; end if;
return wait_count_t'high;
end function;
type state_t is (s_idle, s_sending);
signal state : state_t := s_idle;
signal busy : std_logic := '0';
signal tx_data : std_logic_vector(bit_index_t'high downto 0) := (others => '1');
begin
tx_o <= tx_data(0);
stall_o <= '0' when (bit_index = bit_index_t'high and wait_count = 0)
or state = s_idle
else '1';
process
begin
wait until rising_edge(clk_i);
case state is
when s_idle =>
if stb_i = '1' then
-- add stop('1') and start('0') bit
tx_data <= '1' & dat_i & '0';
state <= s_sending;
end if;
when s_sending =>
wait_count <= countdown_loop(wait_count);
if wait_count = 0 then
bit_index <= countup_loop(bit_index);
-- right-shift tx_data
tx_data <= '1' & tx_data(bit_index_t'high downto 1);
-- end of data
if bit_index = bit_index_t'high then
if stb_i = '1' then -- directly send next byte
-- add stop('1') and start('0') bit
tx_data <= '1' & dat_i & '0';
else
-- wait for next data to come
state <= s_idle;
end if;
end if;
end if;
end case;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
generic (
g_clk_freq : integer := 12000000;
g_baud_rate : integer := 9600;
g_bits : integer := 8
);
port (
clk_i : in std_logic;
-- parallel
dat_o : out std_logic_vector(g_bits-1 downto 0);
stb_o : out std_logic;
-- serial
rx_i : in std_logic
);
end entity;
architecture rtl of uart_rx is
subtype bit_index_t is integer range 0 to g_bits-1;
signal bit_index : bit_index_t := 0;
function countup_loop(index : bit_index_t) return bit_index_t is
begin
if index = bit_index_t'high then return 0; end if;
return index + 1;
end function;
subtype wait_count_t is integer range 0 to g_clk_freq / g_baud_rate-1;
signal wait_count : wait_count_t := wait_count_t'high;
function countdown_loop(count : wait_count_t) return wait_count_t is
begin
if count > 0 then return count - 1; end if;
return wait_count_t'high;
end function;
type state_t is (s_idle, s_align, s_receiving);
signal state : state_t := s_idle;
signal rx_data : std_logic_vector(bit_index_t'high downto 0) := (others => '1');
signal stb : std_logic := '0';
signal rx_sync : std_logic_vector(2 downto 0) := (others => '1');
begin
stb_o <= stb;
dat_o <= rx_data;
process
begin
wait until rising_edge(clk_i);
rx_sync <= rx_sync(1 downto 0) & rx_i;
stb <= '0';
case state is
when s_idle =>
-- detect falling edge on rx line
if rx_sync(2) = '1' and rx_sync(1) = '0' then
wait_count <= wait_count_t'high/2;
if (wait_count_t'high+1)/2 > 0 then
state <= s_align;
else
state <= s_receiving;
end if;
end if;
when s_align =>
wait_count <= countdown_loop(wait_count);
if wait_count = 0 then
-- we are in the center of the start bit
state <= s_receiving;
end if;
when s_receiving =>
wait_count <= countdown_loop(wait_count);
if wait_count = 0 then
bit_index <= countup_loop(bit_index);
-- right-shift rx_data
rx_data <= rx_sync(1) & rx_data(bit_index_t'high downto 1);
-- received last bit
if bit_index = bit_index_t'high then
stb <= '1';
state <= s_idle;
end if;
end if;
end case;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- a wrapper for uart_rx that has a stall input
-- and buffers the last received value as long as
-- this stall input is asserted
entity uart_rx_buffer is
generic (
g_clk_freq : integer := 12000000;
g_baud_rate : integer := 9600;
g_bits : integer := 8
);
port (
clk_i : in std_logic;
-- parallel
dat_o : out std_logic_vector(g_bits-1 downto 0);
stb_o : out std_logic;
stall_i : in std_logic;
-- serial
rx_i : in std_logic
);
end entity;
architecture rtl of uart_rx_buffer is
signal dat : std_logic_vector(g_bits-1 downto 0) := (others => '0');
signal buf : std_logic_vector(g_bits-1 downto 0) := (others => '0');
signal buf_valid : std_logic := '0';
signal stb : std_logic := '0';
begin
wrapped_rx: entity work.uart_rx
generic map (g_clk_freq, g_baud_rate, g_bits)
port map(clk_i => clk_i,
dat_o => dat,
stb_o => stb,
rx_i => rx_i);
dat_o <= buf;
stb_o <= buf_valid;
process
begin
wait until rising_edge(clk_i);
if stb = '1' then
if buf_valid = '1' and stall_i = '1' then
assert false report "UART receiver overflow" severity failure;
-- In this case one uart value is dropped
-- This condition should be prevented by the host
-- by not sending the serial bytes too fast
end if;
buf <= dat;
buf_valid <= '1';
elsif buf_valid = '1' and stall_i = '0' then
buf_valid <= '0';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- merge two uart sources (parallel, before serialization)
entity uart_multiplex is
generic (
g_bits : integer := 8
);
port (
clk_i : in std_logic;
-- parallel out
dat_o : out std_logic_vector(g_bits-1 downto 0);
stb_o : out std_logic;
stall_i : in std_logic;
-- parallel in 1
dat_1_i : in std_logic_vector(g_bits-1 downto 0);
stb_1_i : in std_logic;
stall_1_o : out std_logic;
-- parallel in 2
dat_2_i : in std_logic_vector(g_bits-1 downto 0);
stb_2_i : in std_logic;
stall_2_o : out std_logic
);
end entity;
architecture rtl of uart_multiplex is
type t_state is (s_source_1, s_source_2);
signal state : t_state := s_source_1;
signal dat_out : std_logic_vector(g_bits-1 downto 0) := (others => '0');
signal stb_out : std_logic := '0';
begin
dat_o <= dat_1_i when state = s_source_1
else dat_2_i;
stb_o <= stb_1_i when state = s_source_1
else stb_2_i;
stall_1_o <= stall_i when state = s_source_1
else '1';
stall_2_o <= stall_i when state = s_source_2
else '1';
process
begin
wait until rising_edge(clk_i);
case state is
when s_source_1 =>
if stb_1_i = '0' and stb_2_i = '1' then
state <= s_source_2;
end if;
when s_source_2 =>
if stb_2_i = '0' and stb_1_i = '1' then
state <= s_source_1;
end if;
end case;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- store parallel uart signals in registers to improve timing
entity uart_register is
generic (
g_bits : integer := 8
);
port (
clk_i : in std_logic;
-- parallel out
dat_o : out std_logic_vector(g_bits-1 downto 0);
stb_o : out std_logic;
stall_i : in std_logic;
-- parallel in 1
dat_i : in std_logic_vector(g_bits-1 downto 0);
stb_i : in std_logic;
stall_o : out std_logic
);
end entity;
architecture rtl of uart_register is
signal dat_out : std_logic_vector(g_bits-1 downto 0) := (others => '0');
signal stb_out : std_logic := '0';
signal stall_out : std_logic := '0';
begin
dat_o <= dat_out;
stb_o <= stb_out;
stall_o <= stall_out;
process
begin
wait until rising_edge(clk_i);
dat_out <= dat_i;
stall_out <= stall_i;
stb_out <= stb_i;
end process;
end architecture;
| mit |
jpcofr/PDUAMaude | PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/ALU.vhdl | 1 | 2643 | -- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: ALU **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- ALU Bit_Slice de N Bits
-- A B Clk HF (habilitador)
-- __|_ __|_ _|___|_
-- \ \/ / | |
-- SELOP-->\ / --> | |--> C,N,Z,P
-- \____/ |_______| (Banderas)
-- |RES
-- ___|___
-- DESP -->|_______|
-- |
-- S
-- ***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port (CLK,HF: in std_logic;
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
SELOP : in std_logic_vector(2 downto 0);
DESP : in std_logic_vector(1 downto 0);
S : out std_logic_vector(7 downto 0);
C,N,Z,P : out std_logic
);
end ALU;
architecture Bit_Slice of ALU is
component ALU_BIT is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
SELOP : in STD_LOGIC_VECTOR (2 downto 0);
Cout : out STD_LOGIC;
R : out STD_LOGIC);
end component;
signal RES : std_logic_vector(7 downto 0);
signal Cr : std_logic_vector(7 downto 0);
signal Cm1 : std_logic;
begin
Slices:
for i in 7 downto 0 generate
BIT0:
if i=0 generate
B0: ALU_BIT port map (A(i),B(i),Cm1,SELOP,Cr(i),RES(i));
end generate;
BITN:
if i /= 0 generate
BN: ALU_BIT port map (A(i),B(i),Cr(i-1),SELOP,Cr(i),RES(i));
end generate;
end generate;
Cm1 <= SELOP(2) and SELOP(1); -- Carry de entrada a la ALU ='1'
-- para las operaciones
-- 110 B+1
-- 110 Complemento a 2 de B
Banderas: -- Negativo, Paridad, Carry
process(clk)
begin
If (clk = '0' and clk'event) then
If HF = '1' then
N <= RES(7);
If RES = "00000000" then Z <='1'; else Z <='0';
end if;
P <= not (RES(7) xor RES(6) xor RES(5) xor RES(4) xor RES(3) xor RES(2) xor RES(1) xor RES(0));
C <= Cr(7);
end if;
end if;
end process;
Desplazador:
process(DESP,RES)
begin
case DESP is
when "00" => S <= RES; -- No desplaza
when "01" => S <= '0' & RES(7 downto 1); -- Desplaza a la derecha
when "10" => S <= RES(6 downto 0) & '0'; -- Desplaza a la izquierda
when others => S <= (others => 'X');
end case;
end process;
end Bit_Slice;
| mit |
rbaummer/UART | mixed_clock_fifo_regbased.vhd | 1 | 6039 | --------------------------------------------------------------------------------
--
-- File: Mixed-Clock FIFO - Register Based
-- Author: Rob Baummer
--
-- Description: A mixed clock FIFO using registers targeting small FIFOs. Based
-- on T. Chelcea, S. Nowick, A Low-Latency FIFO for Mixed-Clock Systems.
-- NOTE: Ratio of RX Clock / TX Clock must be less than or equal to 3. Read
-- errors will occur if this is violated.
--------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library work;
entity mixed_clock_fifo_regbased is
generic (
-- N is the size of a word in the FIFO
N : integer;
-- L is the length of the FIFO and must be a power of 2
L : integer);
port (
reset : in std_logic;
--Read Interface
read_clk : in std_logic;
read : in std_logic;
valid : out std_logic;
empty : out std_logic;
read_data : out std_logic_vector(N-1 downto 0);
--Write Interface
write_clk : in std_logic;
write : in std_logic;
full : out std_logic;
write_data : in std_logic_vector(N-1 downto 0)
);
end mixed_clock_fifo_regbased;
architecture behavioral of mixed_clock_fifo_regbased is
signal en_get : std_logic;
signal e : std_logic_vector(L-1 downto 0);
signal f : std_logic_vector(L-1 downto 0);
signal v : std_logic_vector(L-1 downto 0);
signal en_put : std_logic;
signal req_put : std_logic;
signal ptok : std_logic_vector(L-1 downto 0);
signal gtok : std_logic_vector(L-1 downto 0);
signal f_p : std_logic_vector(L-1 downto 0);
signal full_p : std_logic;
signal full_i : std_logic;
signal e_p : std_logic_vector(L-1 downto 0);
signal empty_p : std_logic;
signal empty_i : std_logic;
signal d_p : std_logic_vector(L-1 downto 0);
signal deadlock_p : std_logic;
signal deadlock_i : std_logic;
signal valid_i : std_logic;
function or_reduce(arg: std_logic_vector) return std_logic is
variable result: std_logic;
begin
result := '0';
for i in arg'range loop
result := result or arg(i);
end loop;
return result;
end or_reduce;
function nor_reduce(arg: std_logic_vector) return std_logic is
variable result: std_logic;
begin
result := '0';
for i in arg'range loop
result := result nor arg(i);
end loop;
return result;
end nor_reduce;
begin
--Array of cells which make up the FIFO
--i=0 represents the right-most cell
fifo_array : for i in 0 to L - 1 generate
--Generate the first cell in the FIFO
--The tokens for this cell originate at the last cell of the FIFO
first_cell : if i = 0 generate
--FIFO Cell is a single word storage
c0 : entity work.fifo_cell
generic map (
N => N)
port map (
--Read Interface
clk_get => read_clk,
en_get => en_get,
valid => valid_i,
v => v(i),
data_get => read_data,
empty => e(i),
--Write Interface
clk_put => write_clk,
en_put => en_put,
req_put => write,
data_put => write_data,
full => f(i),
--Token Interface
--Tokens are passed right to left and wrap around at left-most cell
ptok_in => ptok(L-1),
gtok_in => gtok(L-1),
ptok_out => ptok(i),
gtok_out => gtok(i),
reset => reset,
init_token => '1'
);
end generate first_cell;
--Generate the remaining cells in the FIFO
--The tokens for this cell originate from the cell on the right (i-1)
rem_cell : if i > 0 generate
--FIFO Cell is a single word storage
ci : entity work.fifo_cell
generic map (
N => N)
port map (
--Read Interface
clk_get => read_clk,
en_get => en_get,
valid => valid_i,
v => v(i),
data_get => read_data,
empty => e(i),
--Write Interface
clk_put => write_clk,
en_put => en_put,
req_put => write,
data_put => write_data,
full => f(i),
--Token Interface
--Tokens are passed right to left and wrap around at left-most cell
ptok_in => ptok(i-1),
gtok_in => gtok(i-1),
ptok_out => ptok(i),
gtok_out => gtok(i),
reset => reset,
init_token => '0'
);
end generate rem_cell;
end generate fifo_array;
--control flags
en_put <= (not full_i) and (deadlock_i or write);
en_get <= (not empty_i) and read;
--output flags
full <= full_i;
empty <= empty_i;
valid <= (not empty_i) and valid_i and read;
--full detector
--Due to the synchronizer delay full detection must occur when there is 1 empty cell
--full is detected if there are no neighboring cells empty
full_detector : for i in 0 to L-1 generate
e_p(i) <= e(i) and e((i+1) mod (L-1));
end generate full_detector;
--full flag on read_clk domain
--if any of the e_p flags are low, full is high
full_p <= not or_reduce(e_p);
--full flag synchronized to write_clk domain
full_sync : entity work.synchronizer
port map (
clk => write_clk,
reset => reset,
I => full_p,
O => full_i
);
--empty detector
--Due to the synchronizer delay empty detection must occur when there is 1 empty cell
--empty is detected if there are no neighboring cells full
empty_detector : for i in 0 to L-1 generate
f_p(i) <= f(i) and f((i+1) mod (L-1));
end generate empty_detector;
--empty flag on write_clk domain
--if any of the f_p flags are low, empty is high
empty_p <= not or_reduce(f_p);
--empty flag synchronized to read_clk domain
empty_sync : entity work.synchronizer
port map (
clk => read_clk,
reset => reset,
I => empty_p,
O => empty_i
);
--deadlock detector
--Deadlock detects when there is only 1 cell full
deadlock_dector : for i in 0 to L-1 generate
d_p(i) <= f(i) and v(i);
end generate deadlock_dector;
--deadlock on read_clock domain
--deadlock occurs when empty is high and f and v is true for 1 cell
deadlock_p <= or_reduce(d_p) and empty_p;
--deadlock flag synchronized to write_clk domain
deadlock_sync : entity work.synchronizer
port map (
clk => write_clk,
reset => reset,
I => deadlock_p,
O => deadlock_i
);
end behavioral;
| mit |
notti/schaltungstechnik_vertiefung | Assignement/Task2/uart_receive.vhd | 1 | 3562 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:34 10/01/2013
-- Design Name:
-- Module Name: uart_receive - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_receive is
port(
rst_i : in std_logic;
clk_i : in std_logic;
Top16_i : in std_logic;
TopRx_i : in std_logic;
Dout_o : out std_logic_vector(7 downto 0);
ClrDiv_o: out std_logic;
Recvd : out std_logic;
Rx_i : in std_logic
);
end uart_receive;
architecture Behavioral of uart_receive is
type state_type is (idle, start_rx, edge_rx, shift_rx, stop_rx, rxovf);
--constant NDbits : std_logic_vector(2 downto 0) :=8;
signal RxFSM : state_type;
signal Rx_Reg : std_logic_vector(7 downto 0);
signal RxBitCnt : integer;
signal RxRdyi : std_logic;
signal ClrDiv : std_logic;
signal RxErr : std_logic;
begin
-- ------------------------
-- RECEIVE State Machine
-- ------------------------
Rx_FSM: process (rst_i, clk_i)
begin
if rst_i='1' then
Rx_Reg <= (others => '0');
Dout_o <= (others => '0');
RxBitCnt <= 0;
Recvd <= '0';
RxFSM <= Idle;
elsif rising_edge(clk_i) then
case RxFSM is
when Idle =>
Recvd <= '0';
if Top16_i = '1' and Rx_i = '0' then
RxFSM <= Start_Rx;
RxBitCnt <= 0;
end if;
when Start_Rx =>
if TopRx_i = '1' then
if Rx_i = '1' then
RxFSM <= RxOVF;
else
RxFSM <= Edge_Rx;
end if;
end if;
when Edge_Rx =>
if TopRx_i = '1' then
if RxBitCnt = 8 then
RxFSM <= Stop_Rx;
else
RxFSM <= Shift_Rx;
end if;
end if;
when Shift_Rx =>
if TopRx_i = '1' then
RxFSM <= Edge_Rx;
Rx_Reg(RxBitCnt) <= Rx_i;
RxBitCnt <= RxBitCnt + 1;
end if;
when Stop_Rx =>
if TopRx_i = '1' then
RxFSM <= Idle;
Dout_o <= Rx_Reg;
Recvd <= '1';
end if;
when RxOVF =>
if Rx_i = '1' then
RxFSM <= Idle;
end if;
end case;
end if;
end process Rx_FSM;
ClrDiv_o <= ClrDiv;
RxRdyi <= '1' when RxFSM = Idle else '0';
RxErr <= '1' when RxFSM = RxOVF else '0';
ClrDiv <= '1' when RxFSM = idle and Top16_i = '1' and Rx_i = '0' else '0';
end Behavioral;
| mit |
notti/schaltungstechnik_vertiefung | Assignement/Task5/clk_res_gen.vhd | 2 | 907 |
library ieee;
use ieee.std_logic_1164.all;
entity clk_res_gen is
port(
clk_50 : out std_logic;
rst : out std_logic
);
end entity clk_res_gen;
architecture RTL of clk_res_gen is
begin
-- This process generates a 50MHz clock signal
p_clk_generate : process
begin
while TRUE loop
clk_50 <= '0';
wait for 10 ns;
clk_50 <= '1';
wait for 10 ns;
end loop;
end process p_clk_generate;
p_report_sim_progress : process
variable sim_time : integer := 0;
begin
while TRUE loop
--report "Simulation time in ns is " & integer'image(sim_time);
wait for 10 ns;
sim_time := sim_time + 10;
end loop;
end process p_report_sim_progress;
-- This process generate a test reset signal and enables the design after 15 ns
p_res_generate : process
begin
rst <= '1';
wait for 15 ns;
rst <= '0';
wait for 5000 ms;
end process p_res_generate;
end architecture RTL;
| mit |
notti/schaltungstechnik_vertiefung | Assignement/Task2/uart_transmit.vhd | 1 | 2568 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:53 10/01/2013
-- Design Name:
-- Module Name: uart_transmit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_transmit is
port(
rst_i : in std_logic;
clk_i : in std_logic;
TopTX : in std_logic;
Din_i : in std_logic_vector(7 downto 0);
Tx_o : out std_logic;
TxBusy_o: out std_logic;
LD_i : in std_logic
);
end uart_transmit;
architecture Behavioral of uart_transmit is
type state_type is (idle, load_tx, shift_tx, stop_tx);
signal Tx_Reg : std_logic_vector(9 downto 0);
signal RegDin : std_logic_vector(7 downto 0);
signal TxBitCnt : natural;
signal TxFSM : state_type;
begin
-- --------------------------
-- Transmit State Machine
-- --------------------------
TX_o <= Tx_Reg(0);
Tx_FSM: process (rst_i, clk_i)
begin
if rst_i='1' then
Tx_Reg <= (others => '1');
TxBitCnt <= 0;
TxFSM <= idle;
TxBusy_o <= '0';
RegDin <= (others=>'0');
elsif rising_edge(clk_i) then
case TxFSM is
when Idle =>
if Ld_i = '1' then
TxFSM <= Load_tx;
RegDin <= Din_i;
TxBusy_o <= '1';
end if;
when Load_Tx =>
if TopTX = '1' then
TxFSM <= Shift_tx;
TxBitCnt <= 10;
Tx_Reg <= '1' & RegDin & '0';
end if;
when Shift_Tx =>
if TopTX = '1' then
if TXBitCnt = 1 then
TxFSM <= Stop_tx;
end if;
TxBitCnt <= TxBitCnt - 1;
Tx_Reg <= '1' & Tx_Reg(9 downto 1);
end if;
when Stop_Tx =>
if TopTX = '1' then
TxFSM <= Idle;
TxBusy_o <= '0';
end if;
when others =>
TxFSM <= Idle;
end case;
end if;
end process;
end Behavioral;
| mit |
notti/schaltungstechnik_vertiefung | Assignement/Task2/clock_gen.vhd | 1 | 3186 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:04:12 10/01/2013
-- Design Name:
-- Module Name: clock_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock_gen is
port(
rst_i : in std_logic;
clk_i : in std_logic;
ClrDiv_i : in std_logic;
TopRx : out std_logic;
TopTx : out std_logic;
Top16 : out std_logic;
Baud : in std_logic_vector(2 downto 0)
);
end clock_gen;
architecture Behavioral of clock_gen is
signal Divisor : natural;
signal s_Top16 : std_logic;
signal Div16 : integer;
signal ClkDiv : natural;
signal RxDiv : natural;
begin
-- --------------------------
-- Baud rate selection
-- --------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
Divisor <= 0;
elsif rising_edge(clk_i) then
case Baud is
when "000" => Divisor <= 26; -- 115.200
when "001" => Divisor <= 52; -- 57.600
when "010" => Divisor <= 93; -- 38.400
when "011" => Divisor <= 160; -- 19.200
when "100" => Divisor <= 322; -- 9.600
when "101" => Divisor <= 646; -- 4.800
when "110" => Divisor <= 1294; -- 2.400
when "111" => Divisor <= 2590; -- 1.200
when others => Divisor <= 26; -- n.u.
end case;
end if;
end process;
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
s_Top16 <= '0';
Div16 <= 0;
elsif rising_edge(clk_i) then
s_Top16 <= '0';
if Div16 = Divisor then
Div16 <= 0;
s_Top16 <= '1';
else
Div16 <= Div16 + 1;
end if;
end if;
end process;
-- --------------------------
-- Tx Clock Generation
-- --------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
TopTx <= '0';
ClkDiv <= 0;
elsif rising_edge(clk_i) then
TopTx <= '0';
if s_Top16='1' then
ClkDiv <= ClkDiv + 1;
if ClkDiv = 15 then
TopTx <= '1';
ClkDiv<=0;
end if;
end if;
end if;
end process;
-- ------------------------------
-- Rx Sampling Clock Generation
-- ------------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
TopRx <= '0';
RxDiv <= 0;
elsif rising_edge(clk_i) then
TopRx <= '0';
if ClrDiv_i='1' then
RxDiv <= 0;
elsif s_Top16='1' then
if RxDiv = 7 then
RxDiv <= 0;
TopRx <= '1';
else
RxDiv <= RxDiv + 1;
end if;
end if;
end if;
end process;
Top16 <= s_Top16;
end Behavioral;
| mit |
notti/schaltungstechnik_vertiefung | Assignement/Task4/toplevel.vhd | 1 | 5449 | library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port(
-- input pins
IN_clk_50 : in std_logic;
IN_rst : in std_logic;
IN_RotA : in std_logic;
IN_RotB : in std_logic;
IN_RotPush : in std_logic;
-- output pins
OUT_LED_ch0 : out std_logic := '0';
OUT_LED_ch1 : out std_logic := '0';
OUT_LED_ch2 : out std_logic := '0';
OUT_LED_ch3 : out std_logic := '0';
OUT_LED_ch4 : out std_logic := '0';
OUT_LED_ch5 : out std_logic := '0';
OUT_LED_ch6 : out std_logic := '0';
OUT_LED_ch7 : out std_logic := '0'
);
end entity toplevel;
architecture RTL of toplevel is
-- component declarations
component rotKey
port(clk_50 : in std_logic;
rotA : in std_logic;
rotB : in std_logic;
rotPush : in std_logic;
rotRightEvent : out std_logic;
rotLeftEvent : out std_logic;
rotPushEvent : out std_logic);
end component rotKey;
component controller
port(clk_50 : in std_logic;
rst : in std_logic;
leftEvent : in std_logic;
rightEvent : in std_logic;
pushEvent : in std_logic;
pwm0 : out std_logic_vector(5 downto 0);
pwm1 : out std_logic_vector(5 downto 0);
pwm2 : out std_logic_vector(5 downto 0);
pwm3 : out std_logic_vector(5 downto 0);
pwm4 : out std_logic_vector(5 downto 0);
pwm5 : out std_logic_vector(5 downto 0);
pwm6 : out std_logic_vector(5 downto 0);
pwm7 : out std_logic_vector(5 downto 0));
end component controller;
component logDim
port(pwmIn : in std_logic_vector(5 downto 0);
logPwm : out std_logic_vector(7 downto 0));
end component logDim;
component pwmUnit
port(clk_10 : in std_logic;
rst : in std_logic;
duty : in std_logic_vector(7 downto 0);
outSig : out std_logic := '0');
end component pwmUnit;
-- signal declarations
signal sig_rotRightEvent : std_logic;
signal sig_rotLeftEvent : std_logic;
signal sig_rotPushEvent : std_logic;
signal sig_duty0 : std_logic_vector(5 downto 0);
signal sig_duty1 : std_logic_vector(5 downto 0);
signal sig_duty2 : std_logic_vector(5 downto 0);
signal sig_duty3 : std_logic_vector(5 downto 0);
signal sig_duty4 : std_logic_vector(5 downto 0);
signal sig_duty5 : std_logic_vector(5 downto 0);
signal sig_duty6 : std_logic_vector(5 downto 0);
signal sig_duty7 : std_logic_vector(5 downto 0);
signal sig_pwm0 : std_logic_vector(7 downto 0);
signal sig_pwm1 : std_logic_vector(7 downto 0);
signal sig_pwm2 : std_logic_vector(7 downto 0);
signal sig_pwm3 : std_logic_vector(7 downto 0);
signal sig_pwm4 : std_logic_vector(7 downto 0);
signal sig_pwm5 : std_logic_vector(7 downto 0);
signal sig_pwm6 : std_logic_vector(7 downto 0);
signal sig_pwm7 : std_logic_vector(7 downto 0);
begin
-- create instances and route signals
inst_rotKey : rotKey
port map(clk_50 => IN_clk_50,
rotA => IN_rotA,
rotB => IN_rotB,
rotPush => IN_rotPush,
rotRightEvent => sig_rotRightEvent,
rotLeftEvent => sig_rotLeftEvent,
rotPushEvent => sig_rotPushEvent);
inst_controller : controller
port map(clk_50 => IN_clk_50,
rst => IN_rst,
leftEvent => sig_rotLeftEvent,
rightEvent => sig_rotRightEvent,
pushEvent => sig_rotPushEvent,
pwm0 => sig_duty0,
pwm1 => sig_duty1,
pwm2 => sig_duty2,
pwm3 => sig_duty3,
pwm4 => sig_duty4,
pwm5 => sig_duty5,
pwm6 => sig_duty6,
pwm7 => sig_duty7);
inst_log0 : logDim
port map(pwmIn => sig_duty0,
logPwm => sig_pwm0);
inst_pwm0 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm0,
outSig => OUT_LED_ch0);
inst_log1 : logDim
port map(pwmIn => sig_duty1,
logPwm => sig_pwm1);
inst_pwm1 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm1,
outSig => OUT_LED_ch1);
inst_log2 : logDim
port map(pwmIn => sig_duty2,
logPwm => sig_pwm2);
inst_pwm2 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm2,
outSig => OUT_LED_ch2);
inst_log3 : logDim
port map(pwmIn => sig_duty3,
logPwm => sig_pwm3);
inst_pwm3 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm3,
outSig => OUT_LED_ch3);
inst_log4 : logDim
port map(pwmIn => sig_duty4,
logPwm => sig_pwm4);
inst_pwm4 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm4,
outSig => OUT_LED_ch4);
inst_log5 : logDim
port map(pwmIn => sig_duty5,
logPwm => sig_pwm5);
inst_pwm5 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm5,
outSig => OUT_LED_ch5);
inst_log6 : logDim
port map(pwmIn => sig_duty6,
logPwm => sig_pwm6);
inst_pwm6 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm6,
outSig => OUT_LED_ch6);
inst_log7 : logDim
port map(pwmIn => sig_duty7,
logPwm => sig_pwm7);
inst_pwm7 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm7,
outSig => OUT_LED_ch7);
end architecture RTL; | mit |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais | PBL_3/A.vhd | 1 | 4757 | -- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: A.vhd
-- Megafunction Name(s):
-- altaccumulate
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY A IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END A;
ARCHITECTURE SYN OF a IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(4 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 4,
width_out => 5
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais | PBL_3/Comparador17.vhd | 1 | 4810 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: Comparador17.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Comparador17 IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
AgeB : OUT STD_LOGIC
);
END Comparador17;
ARCHITECTURE SYN OF comparador17 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
AgeB : OUT STD_LOGIC ;
clock : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire1_bv(4 DOWNTO 0) <= "10001";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
AgeB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_pipeline => 2,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 5
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
clock => clock,
AgeB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
-- Retrieval info: PRIVATE: Latency NUMERIC "1"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "17"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: AgeB 0 0 0 0 OUTPUT NODEFVAL AgeB
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: dataa 0 0 5 0 INPUT NODEFVAL dataa[4..0]
-- Retrieval info: CONNECT: AgeB 0 0 0 0 @AgeB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 5 0 dataa 0 0 5 0
-- Retrieval info: CONNECT: @datab 0 0 5 0 17 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17_wave*.jpg TRUE
-- Retrieval info: LIB_FILE: lpm
| mit |
mwpastore/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
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