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lsangild/DSD | Exercise3/Multiplication/Multiplication.vhd | 1 | 437 | ----- Libraries -----
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----Entity----
entity multiplication is
port(
SW : in std_logic_vector(199 downto 0);
LEDR : out std_logic_vector(199 downto 0)
);
end multiplication;
----Architecture-----
architecture multiplier of multiplication is
begin
LEDR(199 downto 0) <= std_logic_vector(unsigned(SW(199 downto 100)) * unsigned(SW(99 downto 0)));
end multiplier; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/altera_lnsim/ama_register_function/_primary.vhd | 5 | 1156 | library verilog;
use verilog.vl_types.all;
entity ama_register_function is
generic(
width_data_in : integer := 1;
width_data_out : integer := 1;
register_clock : string := "UNREGISTERED";
register_aclr : string := "NONE";
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of register_clock : constant is 1;
attribute mti_svvh_generic_type of register_aclr : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
end ama_register_function;
| mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_testbench_salt_GNUCY2GBID.vhd | 4 | 1747 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNUCY2GBID is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 3) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_sStepAltr.vhd | 8 | 3488 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sStepAltr is
generic (
StepDelay : positive ;
direction : natural
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sStepAltr ;
architecture syn of alt_dspbuilder_sStepAltr is
type States_StepAltr is (sclear, slow, shigh);
signal current_state : States_StepAltr;
signal next_state : States_StepAltr;
signal iq : std_logic;
signal count : std_logic_vector(ToNatural(nbitnecessary(StepDelay)-1) downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gr:if StepDelay=1 generate
process(clock,aclr_i)
begin
if aclr_i='1' then
iq <= '0';
elsif clock'event and clock='1' then
if (sclr='1') then
iq <= '0';
elsif (ena='1') then
iq <='1';
end if;
end if;
end process;
end generate gr;
grr:if StepDelay>1 generate
rp:process(clock,aclr_i)
begin
if aclr_i='1' then
count <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(StepDelay));
current_state <= next_state;
end if;
end if;
end process;
cp:process(count, current_state, sclr,ena)
begin
case current_state is
when sclear =>
iq <= '0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
iq <= '0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(StepDelay-1,nbitnecessary(StepDelay))) and (ena ='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
iq <= '1';
if (sclr='1') then
next_state <= sclear;
else
next_state <= shigh ;
end if;
end case;
end process;
end generate grr;
g1: if 1=direction generate
q <= iq;
end generate g1;
g0: if 0=direction generate
q <= not iq;
end generate g0;
end syn;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/hdl/alt_dspbuilder_SBF.vhd | 20 | 8869 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
| mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_testbench_capture_GNHCRI5YMO.vhd | 20 | 1775 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNHCRI5YMO is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/altera_lnsim/ama_data_split_reg_ext_function/_primary.vhd | 5 | 4463 | library verilog;
use verilog.vl_types.all;
entity ama_data_split_reg_ext_function is
generic(
width_data_in : integer := 1;
width_data_out : vl_notype;
register_clock_0: string := "UNREGISTERED";
register_aclr_0 : string := "NONE";
register_clock_1: string := "UNREGISTERED";
register_aclr_1 : string := "NONE";
register_clock_2: string := "UNREGISTERED";
register_aclr_2 : string := "NONE";
register_clock_3: string := "UNREGISTERED";
register_aclr_3 : string := "NONE";
number_of_multipliers: integer := 1;
port_sign : string := "PORT_UNUSED";
latency : integer := 0;
latency_clock_0 : string := "UNREGISTERED";
latency_aclr_0 : string := "NONE";
latency_clock_1 : string := "UNREGISTERED";
latency_aclr_1 : string := "NONE";
latency_clock_2 : string := "UNREGISTERED";
latency_aclr_2 : string := "NONE";
latency_clock_3 : string := "UNREGISTERED";
latency_aclr_3 : string := "NONE";
width_data_in_msb: vl_notype;
width_data_in_total_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_in_0_msb: vl_notype;
width_data_in_0_lsb: integer := 0;
width_data_in_1_msb: vl_notype;
width_data_in_1_lsb: vl_notype;
width_data_in_2_msb: vl_notype;
width_data_in_2_lsb: vl_notype;
width_data_in_3_msb: vl_notype;
width_data_in_3_lsb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
data_in : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of latency_clock_0 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_1 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_2 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_3 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_0_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_0_lsb : constant is 1;
attribute mti_svvh_generic_type of width_data_in_1_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_1_lsb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_2_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_2_lsb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_3_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_3_lsb : constant is 3;
end ama_data_split_reg_ext_function;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/altera_lnsim/generic_pll/_primary.vhd | 5 | 1932 | library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0;
fractional_vco_multiplier: string := "false";
use_khz : integer := 1
);
port(
refclk : in vl_logic;
rst : in vl_logic;
fbclk : in vl_logic;
writerefclkdata : in vl_logic_vector(63 downto 0);
writeoutclkdata : in vl_logic_vector(63 downto 0);
writephaseshiftdata: in vl_logic_vector(63 downto 0);
writedutycycledata: in vl_logic_vector(63 downto 0);
outclk : out vl_logic;
locked : out vl_logic;
fboutclk : out vl_logic;
readrefclkdata : out vl_logic_vector(63 downto 0);
readoutclkdata : out vl_logic_vector(63 downto 0);
readphaseshiftdata: out vl_logic_vector(63 downto 0);
readdutycycledata: out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of duty_cycle : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of phase_shift : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of use_khz : constant is 1;
end generic_pll;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_cast_GNWMSU6SSZ.vhd | 3 | 846 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNWMSU6SSZ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNWMSU6SSZ is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_bus_concat_GNAUBM7IRL.vhd | 8 | 653 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_constant_GNARGC6IJC.vhd | 1 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNARGC6IJC is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000111100000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNARGC6IJC is
Begin
-- Constant
output <= "0000000111100000";
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_cast_GN76IOUHQH.vhd | 3 | 876 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN76IOUHQH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(11 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN76IOUHQH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 + 1 ,
width_inr=> 8,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(11 downto 0) => input,
xin(12) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_counter_GNCXSYJEM5.vhd | 4 | 1597 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNCXSYJEM5 is
generic ( use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "1";
use_sload : string := "false";
use_sclr : string := "true";
use_cout : string := "false";
modulus : integer := -1;
use_cnt_ena : string := "true";
width : natural := 16;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0");
port(
aclr : in std_logic;
aload : in std_logic;
aset : in std_logic;
cin : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector((width)-1 downto 0);
direction : in std_logic;
ena : in std_logic;
q : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic;
sload : in std_logic;
sset : in std_logic;
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_counter_GNCXSYJEM5 is
Begin
-- DSP Builder Block - Simulink Block "Counter"
Counteri : lpm_counter Generic map (
LPM_WIDTH => 16,
LPM_DIRECTION => "UP",
LPM_AVALUE => "0",
LPM_SVALUE => "1",
LPM_TYPE => "LPM_COUNTER"
)
port map (
clock => clock,
cnt_en => cnt_ena,
aclr => aclr,
sclr => sclr,
q => q);
end architecture;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/hdl/alt_dspbuilder_constant_GNOJLBOQHG.vhd | 1 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNOJLBOQHG is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000001011001111";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNOJLBOQHG is
Begin
-- Constant
output <= "0000001011001111";
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/hdl/alt_dspbuilder_constant_GNXXQTWZME.vhd | 1 | 576 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNXXQTWZME is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000010100";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNXXQTWZME is
Begin
-- Constant
output <= "0000000000010100";
end architecture; | mit |
lsangild/DSD | Exercise5/CountOnes/CountOnes.vhd | 1 | 569 | -----Libraries-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----Entities-----
entity CountOnes is
port( A : in std_logic_vector(7 downto 0);
ones : out std_logic_vector(3 downto 0)
);
end CountOnes;
-----Architectures-----
architecture Counter of CountOnes is
begin
po: process(A)
variable count : std_logic_vector(3 downto 0);
begin
count := "0000";
for index in 7 downto 0 loop
count := std_logic_vector(unsigned(count) + resize(unsigned(A(index downto index)),4));
end loop;
ones <= count;
end process po;
end Counter; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_cast_GNSB3OXIQS.vhd | 16 | 853 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNSB3OXIQS is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(0 downto 0);
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_cast_GNSB3OXIQS is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0 downto 0) => input,
xin(1) => '0', yout(0) => output
);
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_port_GNS2GDLO5E.vhd | 4 | 487 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNS2GDLO5E is
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNS2GDLO5E is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_decoder.vhd | 7 | 1660 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_testbench_capture.vhd | 10 | 676 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
| mit |
lsangild/DSD | Exercise6/Clock6/watch.vhd | 2 | 2522 | ----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity watch is
port ( clk, speed, reset : in std_logic;
sec_1, sec_10,
min_1, min_10,
hrs_1, hrs_10 : out std_logic_vector(6 downto 0);
time : out std_logic_vector(15 downto 0)
);
end watch;
-----Architecture-----
architecture watch_tester of watch is
signal clocker : std_logic_vector(5 downto 0) := "000000";
signal counter : std_logic_vector(23 downto 0) := "000000000000000000000000";
signal sclk : std_logic := '0';
signal reset_out : std_logic := '1';
begin
res : entity work.reset_logic port map (reset_in => reset, reset_out => reset_out, hrs_bin1 => counter(19 downto 16), hrs_bin10 => counter(23 downto 20));
clo : entity work.clock_gen port map (clk => clk, speed => speed, reset => reset_out, clk_out => sclk);
sec1 : entity work.multi_counter port map ( clk => sclk, reset => reset_out, count => counter(3 downto 0),
cout => clocker(0), mode => "00"); -- til 9
hexs1 : entity work.Binary_7_segment port map (bin => counter(3 downto 0), seg => sec_1);
sec10 : entity work.multi_counter port map ( clk => clocker(0), reset => reset_out, count => counter(7 downto 4),
cout => clocker(1), mode => "01"); -- til 5
hexs10 : entity work.Binary_7_segment port map (bin => counter(7 downto 4), seg => sec_10);
min1 : entity work.multi_counter port map ( clk => clocker(1), reset => reset_out, count => counter(11 downto 8),
cout => clocker(2), mode => "00"); -- til 9
hexm1 : entity work.Binary_7_segment port map (bin => counter(11 downto 8), seg => min_1);
min10 : entity work.multi_counter port map ( clk => clocker(2), reset => reset_out, count => counter(15 downto 12),
cout => clocker(3), mode => "01"); -- til 5
hexm10 : entity work.Binary_7_segment port map (bin => counter(15 downto 12), seg => min_10);
hrs1 : entity work.multi_counter port map ( clk => clocker(3), reset => reset_out, count => counter(19 downto 16),
cout => clocker(4), mode => "00"); -- til 9
hexh1 : entity work.Binary_7_segment port map (bin => counter(19 downto 16), seg => hrs_1);
hrs10 : entity work.multi_counter port map ( clk => clocker(4), reset => reset_out, count => counter(23 downto 20),
cout => clocker(5), mode => "10"); -- til 2
hexh10 : entity work.Binary_7_segment port map (bin => counter(23 downto 20), seg => hrs_10);
time <= counter(23 downto 8);
end watch_tester; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_testbench_clock.vhd | 10 | 2218 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_decoder_GN7UJNSI7B.vhd | 2 | 903 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GN7UJNSI7B is
generic ( decode : string := "101";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GN7UJNSI7B is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "101",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; | mit |
lsangild/DSD | Exercise2/half_adder/simulation/qsim/work/full_adder_vlg_vec_tst/_primary.vhd | 1 | 104 | library verilog;
use verilog.vl_types.all;
entity full_adder_vlg_vec_tst is
end full_adder_vlg_vec_tst;
| mit |
lsangild/DSD | Exercise4/Demultiplexing/Tester.vhd | 1 | 660 | -----Libraries-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----Entity-----
entity tester is
port( KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(11 downto 0);
HEX0, HEX1, HEX2, HEX3 : out std_logic_vector(6 downto 0)
);
end tester;
-----Architecture-----
architecture TEST of tester is
signal data_val : std_logic_vector(20 downto 0) := "111111111111111111111";
begin
HEX3 <= "1111111";
MX : entity work.Multiplexer port map (data => data_val, bin_in => SW, ab => KEY);
DMX : entity work.Demultiplexer port map (data_in => data_val, disp0 => HEX0, disp1 => HEX1, disp2 => HEX2);
end TEST; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_cast_GNGABHQUMP.vhd | 2 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNGABHQUMP is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNGABHQUMP is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_cast_GNGABHQUMP.vhd | 2 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNGABHQUMP is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNGABHQUMP is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_clock.vhd | 2 | 1461 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_clock is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
clock_out : out std_logic;
clock : in std_logic := '0';
aclr_out : out std_logic;
aclr : in std_logic := '0';
aclr_n : in std_logic := '0'
);
end entity alt_dspbuilder_clock;
architecture rtl of alt_dspbuilder_clock is
component alt_dspbuilder_clock_GNQFU4PUDH is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
aclr : in std_logic := '0';
aclr_out : out std_logic;
clock : in std_logic := '0';
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
begin
alt_dspbuilder_clock_GNQFU4PUDH_0: if ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNQFU4PUDH_0: alt_dspbuilder_clock_GNQFU4PUDH
generic map(RESET => "ACTIVE_HIGH", DOMAIN => "default")
port map(aclr => aclr, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
assert not (((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_port_GNXAOKDYKC.vhd | 4 | 487 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNXAOKDYKC is
port(
input : in std_logic_vector(0 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNXAOKDYKC is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/Add_Frame_GN_Add_Frame_Add_Frame_Module.vhd | 2 | 59438 | -- Add_Frame_GN_Add_Frame_Add_Frame_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.25.10:37:27
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module is
port (
state : out std_logic_vector(2 downto 0); -- state.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col : out std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col.wire
addr : in std_logic_vector(2 downto 0) := (others => '0'); -- addr.wire
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row : out std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row.wire
col_counter : out std_logic_vector(15 downto 0); -- col_counter.wire
write : in std_logic := '0'; -- write.wire
frame_in : out std_logic_vector(0 downto 0); -- frame_in.wire
eop : in std_logic := '0'; -- eop.wire
sop : in std_logic := '0'; -- sop.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
valid : in std_logic := '0'; -- valid.wire
row_counter : out std_logic_vector(15 downto 0) -- row_counter.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_pipelined_adder_GN4HTUTWRG is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GN4HTUTWRG;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GNS2GDLO5E is
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_port_GNS2GDLO5E;
component alt_dspbuilder_constant_GNWFCSDEFM is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNWFCSDEFM;
component alt_dspbuilder_constant_GNI2J5SAO3 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNI2J5SAO3;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_constant_GN4GVGE46N is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GN4GVGE46N;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_if_statement_GNHRNNRV37 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
d : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
e : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
f : in std_logic_vector(15 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNHRNNRV37;
component Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
port (
decoder_col : out std_logic_vector(15 downto 0); -- wire
decoder_row : out std_logic_vector(15 downto 0); -- wire
height : out std_logic_vector(15 downto 0); -- wire
data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
sop : in std_logic := 'X'; -- wire
width : out std_logic_vector(15 downto 0); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X' -- reset
);
end component Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component alt_dspbuilder_logical_bit_op_GNKUBZL4TE is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNKUBZL4TE;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_if_statement_GNUCFELPE2 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(15 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNUCFELPE2;
component Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par is
port (
width : out std_logic_vector(15 downto 0); -- wire
write : in std_logic := 'X'; -- wire
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sop : in std_logic := 'X'; -- wire
height : out std_logic_vector(15 downto 0); -- wire
vertex_col : out std_logic_vector(15 downto 0); -- wire
vertex_row : out std_logic_vector(15 downto 0); -- wire
data : in std_logic := 'X' -- wire
);
end component Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par;
component alt_dspbuilder_port_GNXAOKDYKC is
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_port_GNXAOKDYKC;
component alt_dspbuilder_counter_GNCXSYJEM5 is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNCXSYJEM5;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component FrameControl is
port (
clock : in std_logic := 'X'; -- clk
ctrl_in : in std_logic := 'X'; -- wire
data_in : in std_logic := 'X'; -- wire
frame_in : in std_logic := 'X'; -- wire
reset : in std_logic := 'X'; -- wire
state : out std_logic_vector(2 downto 0) -- wire
);
end component FrameControl;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component alt_dspbuilder_multiplexer_GNRF25WCVA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNRF25WCVA;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNLWRZWTQF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLWRZWTQF;
component alt_dspbuilder_cast_GNOLJGN3IG is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNOLJGN3IG;
component alt_dspbuilder_cast_GNAQKAVKAT is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNAQKAVKAT;
component alt_dspbuilder_cast_GNQAP6WVUD is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNQAP6WVUD;
component alt_dspbuilder_cast_GNVFVRULJR is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNVFVRULJR;
component alt_dspbuilder_cast_GNYS2BYR3H is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNYS2BYR3H;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal pipelined_adder1user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder1user_aclrGND:output -> Pipelined_Adder1:user_aclr
signal pipelined_adder1enavcc_output_wire : std_logic; -- Pipelined_Adder1enaVCC:output -> Pipelined_Adder1:ena
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal single_pulsesclrgnd_output_wire : std_logic; -- Single_PulsesclrGND:output -> Single_Pulse:sclr
signal single_pulseenavcc_output_wire : std_logic; -- Single_PulseenaVCC:output -> Single_Pulse:ena
signal pipelined_adderuser_aclrgnd_output_wire : std_logic; -- Pipelined_Adderuser_aclrGND:output -> Pipelined_Adder:user_aclr
signal pipelined_adderenavcc_output_wire : std_logic; -- Pipelined_AdderenaVCC:output -> Pipelined_Adder:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:sop, Add_Frame_Add_Frame_Module_Frame_Par_0:sop, Logical_Bit_Operator:data1]
signal delay3_output_wire : std_logic_vector(0 downto 0); -- Delay3:output -> [Delay1:input, cast228:input]
signal addr_0_output_wire : std_logic_vector(2 downto 0); -- addr_0:output -> Add_Frame_Add_Frame_Module_Frame_Par_0:addr
signal write_0_output_wire : std_logic; -- write_0:output -> Add_Frame_Add_Frame_Module_Frame_Par_0:write
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> Add_Frame_Add_Frame_Module_Frame_Par_0:writedata
signal eop_0_output_wire : std_logic; -- eop_0:output -> [Add_Frame_Add_Frame_Module_Frame_Par_0:data, Logical_Bit_Operator2:data0]
signal counter_q_wire : std_logic_vector(15 downto 0); -- Counter:q -> [If_Statement2:b, If_Statement3:b, If_Statement:a, col_counter_0:input]
signal add_frame_add_frame_module_frame_par_0_vertex_col_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_Frame_Par_0:vertex_col -> [If_Statement:b, cast236:input]
signal counter1_q_wire : std_logic_vector(15 downto 0); -- Counter1:q -> [If_Statement4:b, If_Statement:d, row_counter_0:input]
signal add_frame_add_frame_module_frame_par_0_vertex_row_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_Frame_Par_0:vertex_row -> [If_Statement:e, cast239:input]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> [Frame_Control:frame_in, cast247:input]
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [If_Statement1:a, Multiplexer1:in0, Multiplexer1:in1]
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Counter1:cnt_ena
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Counter:sclr
signal constant7_output_wire : std_logic_vector(15 downto 0); -- Constant7:output -> If_Statement4:a
signal if_statement4_true_wire : std_logic; -- If_Statement4:true -> Counter1:sclr
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal valid_0_output_wire : std_logic; -- valid_0:output -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Counter:cnt_ena
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Frame_Control:ctrl_in
signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in2
signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:data, data_out_0:input]
signal pipelined_adder3_result_wire : std_logic_vector(7 downto 0); -- Pipelined_Adder3:result -> [Pipelined_Adder2:dataa, cast246:input]
signal single_pulse_result_wire : std_logic; -- Single_Pulse:result -> Frame_Control:reset
signal frame_control_state_wire : std_logic_vector(2 downto 0); -- Frame_Control:state -> [cast235:input, state_0:input]
signal delay2_output_wire : std_logic_vector(0 downto 0); -- Delay2:output -> cast227:input
signal cast227_output_wire : std_logic; -- cast227:output -> Delay1:sclr
signal cast228_output_wire : std_logic; -- cast228:output -> Delay1:ena
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> [cast229:input, cast231:input, cast232:input, cast234:input]
signal cast229_output_wire : std_logic; -- cast229:output -> Frame_Control:data_in
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast230:input
signal cast230_output_wire : std_logic_vector(0 downto 0); -- cast230:output -> Delay3:input
signal cast231_output_wire : std_logic; -- cast231:output -> Logical_Bit_Operator1:data0
signal cast232_output_wire : std_logic; -- cast232:output -> Logical_Bit_Operator2:data1
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> cast233:input
signal cast233_output_wire : std_logic_vector(0 downto 0); -- cast233:output -> Delay2:input
signal cast234_output_wire : std_logic; -- cast234:output -> Logical_Bit_Operator3:data0
signal cast235_output_wire : std_logic_vector(2 downto 0); -- cast235:output -> Multiplexer1:sel
signal cast236_output_wire : std_logic_vector(7 downto 0); -- cast236:output -> Pipelined_Adder:dataa
signal add_frame_add_frame_module_frame_par_0_width_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_Frame_Par_0:width -> cast237:input
signal cast237_output_wire : std_logic_vector(7 downto 0); -- cast237:output -> Pipelined_Adder:datab
signal pipelined_adder_result_wire : std_logic_vector(7 downto 0); -- Pipelined_Adder:result -> cast238:input
signal cast238_output_wire : std_logic_vector(15 downto 0); -- cast238:output -> If_Statement:c
signal cast239_output_wire : std_logic_vector(7 downto 0); -- cast239:output -> Pipelined_Adder1:dataa
signal add_frame_add_frame_module_frame_par_0_height_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_Frame_Par_0:height -> cast240:input
signal cast240_output_wire : std_logic_vector(7 downto 0); -- cast240:output -> Pipelined_Adder1:datab
signal pipelined_adder1_result_wire : std_logic_vector(7 downto 0); -- Pipelined_Adder1:result -> cast241:input
signal cast241_output_wire : std_logic_vector(15 downto 0); -- cast241:output -> If_Statement:f
signal constant1_output_wire : std_logic_vector(15 downto 0); -- Constant1:output -> cast242:input
signal cast242_output_wire : std_logic_vector(7 downto 0); -- cast242:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(7 downto 0); -- Pipelined_Adder2:result -> cast243:input
signal cast243_output_wire : std_logic_vector(15 downto 0); -- cast243:output -> If_Statement2:a
signal constant5_output_wire : std_logic_vector(15 downto 0); -- Constant5:output -> cast244:input
signal cast244_output_wire : std_logic_vector(7 downto 0); -- cast244:output -> Pipelined_Adder3:dataa
signal constant6_output_wire : std_logic_vector(15 downto 0); -- Constant6:output -> cast245:input
signal cast245_output_wire : std_logic_vector(7 downto 0); -- cast245:output -> Pipelined_Adder3:datab
signal cast246_output_wire : std_logic_vector(15 downto 0); -- cast246:output -> If_Statement3:a
signal cast247_output_wire : std_logic_vector(0 downto 0); -- cast247:output -> frame_in_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:aclr, Add_Frame_Add_Frame_Module_Frame_Par_0:aclr, Counter1:aclr, Counter:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Multiplexer1:aclr, Pipelined_Adder1:aclr, Pipelined_Adder2:aclr, Pipelined_Adder3:aclr, Pipelined_Adder:aclr, Single_Pulse:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:Clock, Add_Frame_Add_Frame_Module_Frame_Par_0:Clock, Counter1:clock, Counter:clock, Delay1:clock, Delay2:clock, Delay3:clock, Frame_Control:clock, Multiplexer1:clock, Pipelined_Adder1:clock, Pipelined_Adder2:clock, Pipelined_Adder3:clock, Pipelined_Adder:clock, Single_Pulse:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 8,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast244_output_wire, -- dataa.wire
datab => cast245_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => valid, -- input.wire
output => valid_0_output_wire -- output.wire
);
row_counter_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => counter1_q_wire, -- input.wire
output => row_counter -- output.wire
);
pipelined_adder1 : component alt_dspbuilder_pipelined_adder_GN4HTUTWRG
generic map (
width => 8,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast239_output_wire, -- dataa.wire
datab => cast240_output_wire, -- datab.wire
result => pipelined_adder1_result_wire, -- result.wire
user_aclr => pipelined_adder1user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder1enavcc_output_wire -- ena.wire
);
pipelined_adder1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder1user_aclrgnd_output_wire -- output.wire
);
pipelined_adder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder1enavcc_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 8,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => pipelined_adder3_result_wire, -- dataa.wire
datab => cast242_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
state_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => frame_control_state_wire, -- input.wire
output => state -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNWFCSDEFM
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000001",
width => 16
)
port map (
output => constant6_output_wire -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNI2J5SAO3
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000011110000",
width => 16
)
port map (
output => constant7_output_wire -- output.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GN4GVGE46N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000101000000",
width => 16
)
port map (
output => constant5_output_wire -- output.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
constant2 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant2_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNHRNNRV37
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=e)) or ((d>e) and (d<f) and (a=b)) or ((d>e) and (d<f) and (a=c)) or (((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=f))",
number_inputs => 6,
width => 16
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter_q_wire, -- a.wire
b => add_frame_add_frame_module_frame_par_0_vertex_col_wire, -- b.wire
c => cast238_output_wire, -- c.wire
d => counter1_q_wire, -- d.wire
e => add_frame_add_frame_module_frame_par_0_vertex_row_wire, -- e.wire
f => cast241_output_wire -- f.wire
);
constant1 : component alt_dspbuilder_constant_GNWFCSDEFM
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000001",
width => 16
)
port map (
output => constant1_output_wire -- output.wire
);
add_frame_add_frame_module_ctrl_decoder_0 : component Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER
port map (
decoder_col => Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col, -- decoder_col.wire
decoder_row => Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row, -- decoder_row.wire
height => open, -- height.wire
data => multiplexer1_result_wire, -- data.wire
sop => sop_0_output_wire, -- sop.wire
width => open, -- width.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset -- .reset
);
single_pulse : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse_result_wire, -- result.wire
sclr => single_pulsesclrgnd_output_wire, -- sclr.wire
ena => single_pulseenavcc_output_wire -- ena.wire
);
single_pulsesclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulsesclrgnd_output_wire -- output.wire
);
single_pulseenavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulseenavcc_output_wire -- output.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNKUBZL4TE
generic map (
LogicalOp => "AltNOT",
number_inputs => 1
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => cast234_output_wire -- data0.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast232_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => cast231_output_wire, -- data0.wire
data1 => valid_0_output_wire -- data1.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
pipelined_adder : component alt_dspbuilder_pipelined_adder_GN4HTUTWRG
generic map (
width => 8,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast236_output_wire, -- dataa.wire
datab => cast237_output_wire, -- datab.wire
result => pipelined_adder_result_wire, -- result.wire
user_aclr => pipelined_adderuser_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adderenavcc_output_wire -- ena.wire
);
pipelined_adderuser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adderuser_aclrgnd_output_wire -- output.wire
);
pipelined_adderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adderenavcc_output_wire -- output.wire
);
if_statement4 : component alt_dspbuilder_if_statement_GNUCFELPE2
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b)",
number_inputs => 2,
width => 16
)
port map (
true => if_statement4_true_wire, -- true.wire
a => constant7_output_wire, -- a.wire
b => counter1_q_wire -- b.wire
);
add_frame_add_frame_module_frame_par_0 : component Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par
port map (
width => add_frame_add_frame_module_frame_par_0_width_wire, -- width.wire
write => write_0_output_wire, -- write.wire
writedata => writedata_0_output_wire, -- writedata.wire
addr => addr_0_output_wire, -- addr.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
sop => sop_0_output_wire, -- sop.wire
height => add_frame_add_frame_module_frame_par_0_height_wire, -- height.wire
vertex_col => add_frame_add_frame_module_frame_par_0_vertex_col_wire, -- vertex_col.wire
vertex_row => add_frame_add_frame_module_frame_par_0_vertex_row_wire, -- vertex_row.wire
data => eop_0_output_wire -- data.wire
);
frame_in_0 : component alt_dspbuilder_port_GNXAOKDYKC
port map (
input => cast247_output_wire, -- input.wire
output => frame_in -- output.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNUCFELPE2
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b)",
number_inputs => 2,
width => 16
)
port map (
true => if_statement3_true_wire, -- true.wire
a => cast246_output_wire, -- a.wire
b => counter_q_wire -- b.wire
);
counter : component alt_dspbuilder_counter_GNCXSYJEM5
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => -1,
use_cnt_ena => "true",
width => 16,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator1_result_wire, -- cnt_ena.wire
sclr => if_statement3_true_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNUCFELPE2
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b)",
number_inputs => 2,
width => 16
)
port map (
true => if_statement2_true_wire, -- true.wire
a => cast243_output_wire, -- a.wire
b => counter_q_wire -- b.wire
);
delay3 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast230_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
frame_control : component FrameControl
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse_result_wire, -- reset.wire
ctrl_in => logical_bit_operator3_result_wire, -- ctrl_in.wire
data_in => cast229_output_wire, -- data_in.wire
frame_in => if_statement_true_wire, -- frame_in.wire
state => frame_control_state_wire -- state.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNRF25WCVA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 24,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => cast235_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => data_in_0_output_wire, -- in1.wire
in2 => constant2_output_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => cast227_output_wire, -- sclr.wire
ena => cast228_output_wire -- ena.wire
);
delay2 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast233_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer1_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
counter1 : component alt_dspbuilder_counter_GNCXSYJEM5
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => -1,
use_cnt_ena => "true",
width => 16,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => if_statement2_true_wire, -- cnt_ena.wire
sclr => if_statement4_true_wire, -- sclr.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
col_counter_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => counter_q_wire, -- input.wire
output => col_counter -- output.wire
);
cast227 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay2_output_wire, -- input.wire
output => cast227_output_wire -- output.wire
);
cast228 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => cast228_output_wire -- output.wire
);
cast229 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast229_output_wire -- output.wire
);
cast230 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast230_output_wire -- output.wire
);
cast231 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast231_output_wire -- output.wire
);
cast232 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast232_output_wire -- output.wire
);
cast233 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator2_result_wire, -- input.wire
output => cast233_output_wire -- output.wire
);
cast234 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast234_output_wire -- output.wire
);
cast235 : component alt_dspbuilder_cast_GNLWRZWTQF
generic map (
round => 0,
saturate => 0
)
port map (
input => frame_control_state_wire, -- input.wire
output => cast235_output_wire -- output.wire
);
cast236 : component alt_dspbuilder_cast_GNOLJGN3IG
generic map (
round => 0,
saturate => 0
)
port map (
input => add_frame_add_frame_module_frame_par_0_vertex_col_wire, -- input.wire
output => cast236_output_wire -- output.wire
);
cast237 : component alt_dspbuilder_cast_GNOLJGN3IG
generic map (
round => 0,
saturate => 0
)
port map (
input => add_frame_add_frame_module_frame_par_0_width_wire, -- input.wire
output => cast237_output_wire -- output.wire
);
cast238 : component alt_dspbuilder_cast_GNAQKAVKAT
generic map (
round => 0,
saturate => 0
)
port map (
input => pipelined_adder_result_wire, -- input.wire
output => cast238_output_wire -- output.wire
);
cast239 : component alt_dspbuilder_cast_GNOLJGN3IG
generic map (
round => 0,
saturate => 0
)
port map (
input => add_frame_add_frame_module_frame_par_0_vertex_row_wire, -- input.wire
output => cast239_output_wire -- output.wire
);
cast240 : component alt_dspbuilder_cast_GNOLJGN3IG
generic map (
round => 0,
saturate => 0
)
port map (
input => add_frame_add_frame_module_frame_par_0_height_wire, -- input.wire
output => cast240_output_wire -- output.wire
);
cast241 : component alt_dspbuilder_cast_GNAQKAVKAT
generic map (
round => 0,
saturate => 0
)
port map (
input => pipelined_adder1_result_wire, -- input.wire
output => cast241_output_wire -- output.wire
);
cast242 : component alt_dspbuilder_cast_GNQAP6WVUD
generic map (
round => 0,
saturate => 0
)
port map (
input => constant1_output_wire, -- input.wire
output => cast242_output_wire -- output.wire
);
cast243 : component alt_dspbuilder_cast_GNVFVRULJR
generic map (
round => 0,
saturate => 0
)
port map (
input => pipelined_adder2_result_wire, -- input.wire
output => cast243_output_wire -- output.wire
);
cast244 : component alt_dspbuilder_cast_GNQAP6WVUD
generic map (
round => 0,
saturate => 0
)
port map (
input => constant5_output_wire, -- input.wire
output => cast244_output_wire -- output.wire
);
cast245 : component alt_dspbuilder_cast_GNQAP6WVUD
generic map (
round => 0,
saturate => 0
)
port map (
input => constant6_output_wire, -- input.wire
output => cast245_output_wire -- output.wire
);
cast246 : component alt_dspbuilder_cast_GNVFVRULJR
generic map (
round => 0,
saturate => 0
)
port map (
input => pipelined_adder3_result_wire, -- input.wire
output => cast246_output_wire -- output.wire
);
cast247 : component alt_dspbuilder_cast_GNYS2BYR3H
generic map (
round => 0,
saturate => 0
)
port map (
input => if_statement_true_wire, -- input.wire
output => cast247_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module
| mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_counter.vhd | 2 | 5550 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_counter is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "0";
USE_SLOAD : string := "false";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 256;
USE_CNT_ENA : string := "false";
WIDTH : natural := 8;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
user_aclr : in std_logic := '0';
clock : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0);
direction : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aset : in std_logic := '0';
cout : out std_logic;
sset : in std_logic := '0';
aclr : in std_logic := '0';
cnt_ena : in std_logic := '0';
cin : in std_logic := '0';
ena : in std_logic := '0';
aload : in std_logic := '0';
sload : in std_logic := '0'
);
end entity alt_dspbuilder_counter;
architecture rtl of alt_dspbuilder_counter is
component alt_dspbuilder_counter_GNCXSYJEM5 is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 16;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
q : out std_logic_vector(16-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNCXSYJEM5;
component alt_dspbuilder_counter_GNW5IG44CT is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 3;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
q : out std_logic_vector(3-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNW5IG44CT;
begin
alt_dspbuilder_counter_GNCXSYJEM5_0: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 16) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNCXSYJEM5_0: alt_dspbuilder_counter_GNCXSYJEM5
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 16, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
alt_dspbuilder_counter_GNW5IG44CT_1: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNW5IG44CT_1: alt_dspbuilder_counter_GNW5IG44CT
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 3, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
assert not (((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 16) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) or ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/hdl/alt_dspbuilder_cast_GNYS2BYR3H.vhd | 3 | 842 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNYS2BYR3H is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNYS2BYR3H is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_decoder.vhd | 1 | 4986 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(24-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_decoder_GNBHXAVAPH is
generic (
DECODE : string := "010";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNBHXAVAPH;
component alt_dspbuilder_decoder_GNQPHUITBS is
generic (
DECODE : string := "001";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNQPHUITBS;
component alt_dspbuilder_decoder_GN7W55JURN is
generic (
DECODE : string := "100";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GN7W55JURN;
component alt_dspbuilder_decoder_GNBT6YIKS3 is
generic (
DECODE : string := "011";
PIPELINE : natural := 1;
WIDTH : natural := 3
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(3-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNBT6YIKS3;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNBHXAVAPH_1: if ((DECODE = "010") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GNBHXAVAPH_1: alt_dspbuilder_decoder_GNBHXAVAPH
generic map(DECODE => "010", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNQPHUITBS_2: if ((DECODE = "001") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GNQPHUITBS_2: alt_dspbuilder_decoder_GNQPHUITBS
generic map(DECODE => "001", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GN7W55JURN_3: if ((DECODE = "100") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GN7W55JURN_3: alt_dspbuilder_decoder_GN7W55JURN
generic map(DECODE => "100", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNBT6YIKS3_4: if ((DECODE = "011") and (PIPELINE = 1) and (WIDTH = 3)) generate
inst_alt_dspbuilder_decoder_GNBT6YIKS3_4: alt_dspbuilder_decoder_GNBT6YIKS3
generic map(DECODE => "011", PIPELINE => 1, WIDTH => 3)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) or ((DECODE = "010") and (PIPELINE = 1) and (WIDTH = 3)) or ((DECODE = "001") and (PIPELINE = 1) and (WIDTH = 3)) or ((DECODE = "100") and (PIPELINE = 1) and (WIDTH = 3)) or ((DECODE = "011") and (PIPELINE = 1) and (WIDTH = 3)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_bus_concat_GNBH75ZTOD.vhd | 4 | 653 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNBH75ZTOD is
generic ( widthB : natural := 4;
widthA : natural := 8);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNBH75ZTOD is
Begin
output <= a & b;
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/Add_Frame_GN_Add_Frame_Add_Frame_Module.vhd | 2 | 62676 | -- Add_Frame_GN_Add_Frame_Add_Frame_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
addr : in std_logic_vector(2 downto 0) := (others => '0'); -- addr.wire
write : in std_logic := '0'; -- write.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
sop : in std_logic := '0'; -- sop.wire
eop : in std_logic := '0'; -- eop.wire
valid : in std_logic := '0'; -- valid.wire
data_in : in std_logic_vector(23 downto 0) := (others => '0') -- data_in.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_constant_GNWFCSDEFM is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNWFCSDEFM;
component alt_dspbuilder_constant_GNLMV7GZFA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLMV7GZFA;
component alt_dspbuilder_port_GNS2GDLO5E is
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_port_GNS2GDLO5E;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_constant_GNGITJD4MB is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNGITJD4MB;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_logical_bit_op_GN5A3KLAEC is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X'; -- wire
data2 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GN5A3KLAEC;
component alt_dspbuilder_logical_bit_op_GNKUBZL4TE is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNKUBZL4TE;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_constant_GNNTMI25OE is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNTMI25OE;
component alt_dspbuilder_constant_GNIJTURCWG is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNIJTURCWG;
component alt_dspbuilder_if_statement_GNHRNNRV37 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
d : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
e : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
f : in std_logic_vector(15 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNHRNNRV37;
component Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER is
port (
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
height : out std_logic_vector(15 downto 0); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
write : in std_logic := 'X'; -- wire
width : out std_logic_vector(15 downto 0); -- wire
sop : in std_logic := 'X'; -- wire
enble : out std_logic_vector(0 downto 0); -- wire
addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
color : out std_logic_vector(2 downto 0); -- wire
vertex_col : out std_logic_vector(15 downto 0); -- wire
vertex_row : out std_logic_vector(15 downto 0) -- wire
);
end component Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER;
component Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
port (
height : out std_logic_vector(15 downto 0); -- wire
width : out std_logic_vector(15 downto 0); -- wire
sop : in std_logic := 'X'; -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
valid : in std_logic := 'X' -- wire
);
end component Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component alt_dspbuilder_if_statement_GNUCFELPE2 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(15 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNUCFELPE2;
component alt_dspbuilder_counter_GNCXSYJEM5 is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNCXSYJEM5;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component FrameControl is
port (
clock : in std_logic := 'X'; -- clk
ctrl_in : in std_logic := 'X'; -- wire
data_in : in std_logic := 'X'; -- wire
frame_in : in std_logic := 'X'; -- wire
reset : in std_logic := 'X'; -- wire
state : out std_logic_vector(2 downto 0) -- wire
);
end component FrameControl;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_multiplexer_GNRF25WCVA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNRF25WCVA;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_multiplexer_GNHHROOGAI is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in3 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in4 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNHHROOGAI;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNLWRZWTQF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLWRZWTQF;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal pipelined_adder4user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder4user_aclrGND:output -> Pipelined_Adder4:user_aclr
signal pipelined_adder4enavcc_output_wire : std_logic; -- Pipelined_Adder4enaVCC:output -> Pipelined_Adder4:ena
signal pipelined_adder1user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder1user_aclrGND:output -> Pipelined_Adder1:user_aclr
signal pipelined_adder1enavcc_output_wire : std_logic; -- Pipelined_Adder1enaVCC:output -> Pipelined_Adder1:ena
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal single_pulsesclrgnd_output_wire : std_logic; -- Single_PulsesclrGND:output -> Single_Pulse:sclr
signal single_pulseenavcc_output_wire : std_logic; -- Single_PulseenaVCC:output -> Single_Pulse:ena
signal pipelined_adderuser_aclrgnd_output_wire : std_logic; -- Pipelined_Adderuser_aclrGND:output -> Pipelined_Adder:user_aclr
signal pipelined_adderenavcc_output_wire : std_logic; -- Pipelined_AdderenaVCC:output -> Pipelined_Adder:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:sop, Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:sop, Logical_Bit_Operator:data1]
signal valid_0_output_wire : std_logic; -- valid_0:output -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:valid, Logical_Bit_Operator1:data1, Logical_Bit_Operator6:data2]
signal delay3_output_wire : std_logic_vector(0 downto 0); -- Delay3:output -> [Delay1:input, cast10:input]
signal addr_0_output_wire : std_logic_vector(2 downto 0); -- addr_0:output -> Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:addr
signal write_0_output_wire : std_logic; -- write_0:output -> Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:write
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:writedata
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:data, If_Statement1:a, Multiplexer1:in0, Multiplexer1:in1]
signal counter_q_wire : std_logic_vector(15 downto 0); -- Counter:q -> [If_Statement2:b, If_Statement3:b, If_Statement:a]
signal add_frame_add_frame_module_frame_parameter_0_vertex_col_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:vertex_col -> [If_Statement:b, Pipelined_Adder:dataa]
signal counter1_q_wire : std_logic_vector(15 downto 0); -- Counter1:q -> [If_Statement4:b, If_Statement:d]
signal add_frame_add_frame_module_frame_parameter_0_vertex_row_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:vertex_row -> [If_Statement:e, Pipelined_Adder1:dataa]
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Counter:cnt_ena
signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator2:data0
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Frame_Control:ctrl_in
signal if_statement4_true_wire : std_logic; -- If_Statement4:true -> Logical_Bit_Operator4:data0
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Counter:sclr
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Counter1:sclr
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Logical_Bit_Operator6:data1
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> Counter1:cnt_ena
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Frame_Control:frame_in
signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:data, data_out_0:input]
signal add_frame_add_frame_module_frame_parameter_0_color_wire : std_logic_vector(2 downto 0); -- Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:color -> Multiplexer2:sel
signal constant5_output_wire : std_logic_vector(23 downto 0); -- Constant5:output -> Multiplexer2:in0
signal constant7_output_wire : std_logic_vector(23 downto 0); -- Constant7:output -> Multiplexer2:in1
signal constant9_output_wire : std_logic_vector(23 downto 0); -- Constant9:output -> Multiplexer2:in2
signal constant10_output_wire : std_logic_vector(23 downto 0); -- Constant10:output -> Multiplexer2:in3
signal constant11_output_wire : std_logic_vector(23 downto 0); -- Constant11:output -> Multiplexer2:in4
signal multiplexer2_result_wire : std_logic_vector(23 downto 0); -- Multiplexer2:result -> Multiplexer1:in2
signal add_frame_add_frame_module_frame_parameter_0_width_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:width -> Pipelined_Adder:datab
signal pipelined_adder_result_wire : std_logic_vector(15 downto 0); -- Pipelined_Adder:result -> If_Statement:c
signal add_frame_add_frame_module_frame_parameter_0_height_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:height -> Pipelined_Adder1:datab
signal pipelined_adder1_result_wire : std_logic_vector(15 downto 0); -- Pipelined_Adder1:result -> If_Statement:f
signal constant1_output_wire : std_logic_vector(15 downto 0); -- Constant1:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(15 downto 0); -- Pipelined_Adder2:result -> If_Statement2:a
signal add_frame_add_frame_module_ctrl_decoder_0_width_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_CTRL_DECODER_0:width -> Pipelined_Adder3:dataa
signal constant6_output_wire : std_logic_vector(15 downto 0); -- Constant6:output -> Pipelined_Adder3:datab
signal pipelined_adder3_result_wire : std_logic_vector(15 downto 0); -- Pipelined_Adder3:result -> [If_Statement3:a, Pipelined_Adder2:dataa]
signal add_frame_add_frame_module_ctrl_decoder_0_height_wire : std_logic_vector(15 downto 0); -- Add_Frame_Add_Frame_Module_CTRL_DECODER_0:height -> Pipelined_Adder4:dataa
signal constant8_output_wire : std_logic_vector(15 downto 0); -- Constant8:output -> Pipelined_Adder4:datab
signal pipelined_adder4_result_wire : std_logic_vector(15 downto 0); -- Pipelined_Adder4:result -> If_Statement4:a
signal single_pulse_result_wire : std_logic; -- Single_Pulse:result -> Frame_Control:reset
signal delay2_output_wire : std_logic_vector(0 downto 0); -- Delay2:output -> cast9:input
signal cast9_output_wire : std_logic; -- cast9:output -> Delay1:sclr
signal cast10_output_wire : std_logic; -- cast10:output -> Delay1:ena
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> [cast11:input, cast13:input, cast14:input, cast16:input, cast17:input, cast18:input]
signal cast11_output_wire : std_logic; -- cast11:output -> Frame_Control:data_in
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast12:input
signal cast12_output_wire : std_logic_vector(0 downto 0); -- cast12:output -> Delay3:input
signal cast13_output_wire : std_logic; -- cast13:output -> Logical_Bit_Operator1:data0
signal cast14_output_wire : std_logic; -- cast14:output -> Logical_Bit_Operator2:data1
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> cast15:input
signal cast15_output_wire : std_logic_vector(0 downto 0); -- cast15:output -> Delay2:input
signal cast16_output_wire : std_logic; -- cast16:output -> Logical_Bit_Operator3:data0
signal cast17_output_wire : std_logic; -- cast17:output -> Logical_Bit_Operator5:data0
signal cast18_output_wire : std_logic; -- cast18:output -> Logical_Bit_Operator6:data0
signal add_frame_add_frame_module_frame_parameter_0_enble_wire : std_logic_vector(0 downto 0); -- Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:enble -> cast19:input
signal cast19_output_wire : std_logic; -- cast19:output -> Logical_Bit_Operator7:data0
signal frame_control_state_wire : std_logic_vector(2 downto 0); -- Frame_Control:state -> cast20:input
signal cast20_output_wire : std_logic_vector(2 downto 0); -- cast20:output -> Multiplexer1:sel
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:aclr, Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:aclr, Counter1:aclr, Counter:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Pipelined_Adder1:aclr, Pipelined_Adder2:aclr, Pipelined_Adder3:aclr, Pipelined_Adder4:aclr, Pipelined_Adder:aclr, Single_Pulse:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Add_Frame_Add_Frame_Module_CTRL_DECODER_0:Clock, Add_Frame_Add_Frame_Module_FRAME_PARAMETER_0:Clock, Counter1:clock, Counter:clock, Delay1:clock, Delay2:clock, Delay3:clock, Frame_Control:clock, Multiplexer1:clock, Multiplexer2:clock, Pipelined_Adder1:clock, Pipelined_Adder2:clock, Pipelined_Adder3:clock, Pipelined_Adder4:clock, Pipelined_Adder:clock, Single_Pulse:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 16,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => add_frame_add_frame_module_ctrl_decoder_0_width_wire, -- dataa.wire
datab => constant6_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
pipelined_adder4 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 16,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => add_frame_add_frame_module_ctrl_decoder_0_height_wire, -- dataa.wire
datab => constant8_output_wire, -- datab.wire
result => pipelined_adder4_result_wire, -- result.wire
user_aclr => pipelined_adder4user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder4enavcc_output_wire -- ena.wire
);
pipelined_adder4user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder4user_aclrgnd_output_wire -- output.wire
);
pipelined_adder4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder4enavcc_output_wire -- output.wire
);
valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => valid, -- input.wire
output => valid_0_output_wire -- output.wire
);
pipelined_adder1 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 16,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => add_frame_add_frame_module_frame_parameter_0_vertex_row_wire, -- dataa.wire
datab => add_frame_add_frame_module_frame_parameter_0_height_wire, -- datab.wire
result => pipelined_adder1_result_wire, -- result.wire
user_aclr => pipelined_adder1user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder1enavcc_output_wire -- ena.wire
);
pipelined_adder1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder1user_aclrgnd_output_wire -- output.wire
);
pipelined_adder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder1enavcc_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 16,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => pipelined_adder3_result_wire, -- dataa.wire
datab => constant1_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNWFCSDEFM
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000001",
width => 16
)
port map (
output => constant6_output_wire -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNLMV7GZFA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "111111111111111111111111",
width => 24
)
port map (
output => constant7_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant5_output_wire -- output.wire
);
constant8 : component alt_dspbuilder_constant_GNWFCSDEFM
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000001",
width => 16
)
port map (
output => constant8_output_wire -- output.wire
);
constant9 : component alt_dspbuilder_constant_GNGITJD4MB
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000011111111",
width => 24
)
port map (
output => constant9_output_wire -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => cast19_output_wire, -- data0.wire
data1 => if_statement_true_wire -- data1.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GN5A3KLAEC
generic map (
LogicalOp => "AltAND",
number_inputs => 3
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => cast18_output_wire, -- data0.wire
data1 => if_statement2_true_wire, -- data1.wire
data2 => valid_0_output_wire -- data2.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNKUBZL4TE
generic map (
LogicalOp => "AltNOT",
number_inputs => 1
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => cast17_output_wire -- data0.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => if_statement4_true_wire, -- data0.wire
data1 => if_statement3_true_wire -- data1.wire
);
constant10 : component alt_dspbuilder_constant_GNNTMI25OE
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000001111111100000000",
width => 24
)
port map (
output => constant10_output_wire -- output.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
constant11 : component alt_dspbuilder_constant_GNIJTURCWG
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "111111110000000000000000",
width => 24
)
port map (
output => constant11_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNHRNNRV37
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=e)) or ((d>e) and (d<f) and (a=b)) or ((d>e) and (d<f) and (a=c)) or (((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=f))",
number_inputs => 6,
width => 16
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter_q_wire, -- a.wire
b => add_frame_add_frame_module_frame_parameter_0_vertex_col_wire, -- b.wire
c => pipelined_adder_result_wire, -- c.wire
d => counter1_q_wire, -- d.wire
e => add_frame_add_frame_module_frame_parameter_0_vertex_row_wire, -- e.wire
f => pipelined_adder1_result_wire -- f.wire
);
constant1 : component alt_dspbuilder_constant_GNWFCSDEFM
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000001",
width => 16
)
port map (
output => constant1_output_wire -- output.wire
);
add_frame_add_frame_module_frame_parameter_0 : component Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER
port map (
writedata => writedata_0_output_wire, -- writedata.wire
data => data_in_0_output_wire, -- data.wire
height => add_frame_add_frame_module_frame_parameter_0_height_wire, -- height.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
write => write_0_output_wire, -- write.wire
width => add_frame_add_frame_module_frame_parameter_0_width_wire, -- width.wire
sop => sop_0_output_wire, -- sop.wire
enble => add_frame_add_frame_module_frame_parameter_0_enble_wire, -- enble.wire
addr => addr_0_output_wire, -- addr.wire
color => add_frame_add_frame_module_frame_parameter_0_color_wire, -- color.wire
vertex_col => add_frame_add_frame_module_frame_parameter_0_vertex_col_wire, -- vertex_col.wire
vertex_row => add_frame_add_frame_module_frame_parameter_0_vertex_row_wire -- vertex_row.wire
);
add_frame_add_frame_module_ctrl_decoder_0 : component Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER
port map (
height => add_frame_add_frame_module_ctrl_decoder_0_height_wire, -- height.wire
width => add_frame_add_frame_module_ctrl_decoder_0_width_wire, -- width.wire
sop => sop_0_output_wire, -- sop.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data => multiplexer1_result_wire, -- data.wire
valid => valid_0_output_wire -- valid.wire
);
single_pulse : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse_result_wire, -- result.wire
sclr => single_pulsesclrgnd_output_wire, -- sclr.wire
ena => single_pulseenavcc_output_wire -- ena.wire
);
single_pulsesclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulsesclrgnd_output_wire -- output.wire
);
single_pulseenavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulseenavcc_output_wire -- output.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNKUBZL4TE
generic map (
LogicalOp => "AltNOT",
number_inputs => 1
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => cast16_output_wire -- data0.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast14_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => cast13_output_wire, -- data0.wire
data1 => valid_0_output_wire -- data1.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
pipelined_adder : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 16,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => add_frame_add_frame_module_frame_parameter_0_vertex_col_wire, -- dataa.wire
datab => add_frame_add_frame_module_frame_parameter_0_width_wire, -- datab.wire
result => pipelined_adder_result_wire, -- result.wire
user_aclr => pipelined_adderuser_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adderenavcc_output_wire -- ena.wire
);
pipelined_adderuser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adderuser_aclrgnd_output_wire -- output.wire
);
pipelined_adderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adderenavcc_output_wire -- output.wire
);
if_statement4 : component alt_dspbuilder_if_statement_GNUCFELPE2
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b)",
number_inputs => 2,
width => 16
)
port map (
true => if_statement4_true_wire, -- true.wire
a => pipelined_adder4_result_wire, -- a.wire
b => counter1_q_wire -- b.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNUCFELPE2
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b)",
number_inputs => 2,
width => 16
)
port map (
true => if_statement3_true_wire, -- true.wire
a => pipelined_adder3_result_wire, -- a.wire
b => counter_q_wire -- b.wire
);
counter : component alt_dspbuilder_counter_GNCXSYJEM5
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => -1,
use_cnt_ena => "true",
width => 16,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator1_result_wire, -- cnt_ena.wire
sclr => logical_bit_operator4_result_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNUCFELPE2
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b)",
number_inputs => 2,
width => 16
)
port map (
true => if_statement2_true_wire, -- true.wire
a => pipelined_adder2_result_wire, -- a.wire
b => counter_q_wire -- b.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
frame_control : component FrameControl
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse_result_wire, -- reset.wire
ctrl_in => logical_bit_operator3_result_wire, -- ctrl_in.wire
data_in => cast11_output_wire, -- data_in.wire
frame_in => logical_bit_operator7_result_wire, -- frame_in.wire
state => frame_control_state_wire -- state.wire
);
delay3 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast12_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNRF25WCVA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 24,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => cast20_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => data_in_0_output_wire, -- in1.wire
in2 => multiplexer2_result_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => cast9_output_wire, -- sclr.wire
ena => cast10_output_wire -- ena.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GNHHROOGAI
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 5
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => add_frame_add_frame_module_frame_parameter_0_color_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => constant5_output_wire, -- in0.wire
in1 => constant7_output_wire, -- in1.wire
in2 => constant9_output_wire, -- in2.wire
in3 => constant10_output_wire, -- in3.wire
in4 => constant11_output_wire -- in4.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast15_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer1_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
counter1 : component alt_dspbuilder_counter_GNCXSYJEM5
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => -1,
use_cnt_ena => "true",
width => 16,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator6_result_wire, -- cnt_ena.wire
sclr => logical_bit_operator5_result_wire, -- sclr.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
cast9 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay2_output_wire, -- input.wire
output => cast9_output_wire -- output.wire
);
cast10 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => cast10_output_wire -- output.wire
);
cast11 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast11_output_wire -- output.wire
);
cast12 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast12_output_wire -- output.wire
);
cast13 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast13_output_wire -- output.wire
);
cast14 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast14_output_wire -- output.wire
);
cast15 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator2_result_wire, -- input.wire
output => cast15_output_wire -- output.wire
);
cast16 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast16_output_wire -- output.wire
);
cast17 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast17_output_wire -- output.wire
);
cast18 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast18_output_wire -- output.wire
);
cast19 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => add_frame_add_frame_module_frame_parameter_0_enble_wire, -- input.wire
output => cast19_output_wire -- output.wire
);
cast20 : component alt_dspbuilder_cast_GNLWRZWTQF
generic map (
round => 0,
saturate => 0
)
port map (
input => frame_control_state_wire, -- input.wire
output => cast20_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module
| mit |
lsangild/DSD | Exercise3/Concatenation/shift_div.vhd | 1 | 754 | ----- LIBRARIES -----
LIBRARY ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity shift_div is
port ( SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(4 downto 0)
);
end shift_div;
architecture shift of shift_div is
begin
--process(SW)
-- begin
-- if(SW(5) = '1')then --Shift once to the left
-- LEDR(4 downto 0) <= std_logic_vector(SW(3 downto 0) & '0');
-- elsif(SW(6) = '1')then --Shift twice to the right
-- LEDR(4 downto 0) <= std_logic_vector("00" & SW(4 downto 2));
-- elsif(SW(7) = '1')then --Rotate thrice to the right
LEDR(4 downto 0) <= SW(2) & SW(1) & SW(0) & SW(4) & SW(3);
-- else --Show original input
-- LEDR(4 downto 0) <= SW(4 downto 0);
-- end if;
--end process;
end shift; | mit |
lsangild/DSD | Exercise3/Four_bit_adder/full_adder.vhd | 1 | 602 | -----------------------Implementation of a Full adder ---------------
-------------- Library statements -------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration full_adder--
entity full_adder is
port (FAa, FAb, FAcin : in std_logic;
FAsum, FAcout : out std_logic;
FAc1, FAc2, s1 : buffer std_logic
);
end full_adder;
architecture FA of full_adder is
begin
h1: entity work.half_adder_dataflow port map(a=>FAa,b=>FAb,sum=>s1,carry=>FAc1);
h2: entity work.half_adder_dataflow port map(a=>s1,b=>FAcin,sum=>FAsum,carry=>FAc2);
FAcout <= FAc1 or FAc2;
end FA; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_delay_GNUECIBFDH.vhd | 16 | 1088 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNUECIBFDH is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNUECIBFDH is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "0")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_delay_GNUECIBFDH.vhd | 16 | 1088 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNUECIBFDH is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNUECIBFDH is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "0")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/hdl/alt_dspbuilder_delay_GNUECIBFDH.vhd | 16 | 1088 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNUECIBFDH is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNUECIBFDH is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "0")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_port_GNEPKLLZKY.vhd | 17 | 489 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
Given-Jiang/Add_Frame | tb_Add_Frame/altera_lnsim/ama_preadder_function/_primary.vhd | 5 | 5462 | library verilog;
use verilog.vl_types.all;
entity ama_preadder_function is
generic(
preadder_mode : string := "SIMPLE";
width_in_a : integer := 1;
width_in_b : integer := 1;
width_in_c : integer := 1;
width_in_coef : integer := 1;
width_result_a : integer := 1;
width_result_b : integer := 1;
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
representation_preadder_adder: string := "UNSIGNED";
width_in_a_msb : vl_notype;
width_in_b_msb : vl_notype;
width_in_c_msb : vl_notype;
width_in_coef_msb: vl_notype;
width_result_a_msb: vl_notype;
width_result_b_msb: vl_notype;
width_preadder_adder_input: vl_notype;
width_preadder_adder_input_msb: vl_notype;
width_preadder_adder_result: vl_notype;
width_preadder_adder_result_msb: vl_notype;
width_preadder_adder_input_wire: vl_notype;
width_preadder_adder_input_wire_msb: vl_notype;
width_in_a_ext : vl_notype;
width_in_b_ext : vl_notype;
width_output_preadder: vl_notype;
width_output_preadder_msb: vl_notype;
width_output_coef: vl_notype;
width_output_coef_msb: vl_notype;
width_output_datab: vl_notype;
width_output_datab_msb: vl_notype;
width_output_datac: vl_notype;
width_output_datac_msb: vl_notype
);
port(
dataa_in_0 : in vl_logic_vector;
dataa_in_1 : in vl_logic_vector;
dataa_in_2 : in vl_logic_vector;
dataa_in_3 : in vl_logic_vector;
datab_in_0 : in vl_logic_vector;
datab_in_1 : in vl_logic_vector;
datab_in_2 : in vl_logic_vector;
datab_in_3 : in vl_logic_vector;
datac_in_0 : in vl_logic_vector;
datac_in_1 : in vl_logic_vector;
datac_in_2 : in vl_logic_vector;
datac_in_3 : in vl_logic_vector;
coef0 : in vl_logic_vector;
coef1 : in vl_logic_vector;
coef2 : in vl_logic_vector;
coef3 : in vl_logic_vector;
result_a0 : out vl_logic_vector;
result_a1 : out vl_logic_vector;
result_a2 : out vl_logic_vector;
result_a3 : out vl_logic_vector;
result_b0 : out vl_logic_vector;
result_b1 : out vl_logic_vector;
result_b2 : out vl_logic_vector;
result_b3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of width_in_a : constant is 1;
attribute mti_svvh_generic_type of width_in_b : constant is 1;
attribute mti_svvh_generic_type of width_in_c : constant is 1;
attribute mti_svvh_generic_type of width_in_coef : constant is 1;
attribute mti_svvh_generic_type of width_result_a : constant is 1;
attribute mti_svvh_generic_type of width_result_b : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1;
attribute mti_svvh_generic_type of width_in_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_c_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3;
attribute mti_svvh_generic_type of width_result_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_result_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_a_ext : constant is 3;
attribute mti_svvh_generic_type of width_in_b_ext : constant is 3;
attribute mti_svvh_generic_type of width_output_preadder : constant is 3;
attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3;
attribute mti_svvh_generic_type of width_output_coef : constant is 3;
attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3;
attribute mti_svvh_generic_type of width_output_datab : constant is 3;
attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3;
attribute mti_svvh_generic_type of width_output_datac : constant is 3;
attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3;
end ama_preadder_function;
| mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_decoder_GNBHXAVAPH.vhd | 4 | 903 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNBHXAVAPH is
generic ( decode : string := "010";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNBHXAVAPH is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "010",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_sImpulse11Altr.vhd | 8 | 2408 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulse11Altr is
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulse11Altr ;
architecture syn of alt_dspbuilder_sImpulse11Altr is
type States_ImpulseAltr is (sclear, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
begin
rp:process(clock,aclr)
begin
if aclr='1' then
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
current_state <= sclear;
elsif (ena='1') then
current_state <= next_state;
end if;
end if;
end process;
cp:process(current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= shigh;
else
next_state <= sclear;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_SBitLogical.vhd | 20 | 3567 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBitLogical is
generic (
lpm_width : positive := 8 ;
lop : LogicalOperator := AltAND
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end alt_dspbuilder_SBitLogical;
architecture SBitLogical_SYNTH of alt_dspbuilder_SBitLogical is
signal worand : std_logic_vector(lpm_width-1 downto 0);
signal ndataa : std_logic_vector(lpm_width-1 downto 0);
signal result_int : std_logic;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => result_int, r => result);
------------------AND--------------------------------
go1p:if lop = AltAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '1' when (worand=dataa) else '0';
end generate;
------------------OR--------------------------------
go2p:if lop = AltOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '0' when (ndataa=worand) else '1';
end generate;
------------------XOR--------------------------------
go3p:if lop = AltXOR generate
gif:if (lpm_width>2) generate
process(dataa)
variable interes : std_logic ;
begin
interes := dataa(0) xor dataa(1);
for i in 2 to lpm_width-1 loop
interes := dataa(i) xor interes;
end loop;
result_int <= interes;
end process;
end generate;
gif2:if (lpm_width<3) generate
result_int <= dataa(0) xor dataa(1);
end generate;
end generate;
------------------NOR--------------------------------
go4p:if lop = AltNOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '1' when (ndataa=worand) else '0';
end generate;
------------------NAND--------------------------------
go5p:if lop = AltNAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '0' when (worand=dataa) else '1';
end generate;
------------------NOT (Single Bit only)---------------
go6p:if lop = AltNOT generate
result_int <= not (dataa(0));
end generate;
end SBitLogical_SYNTH;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_testbench_clock_GNCGUFKHRR.vhd | 15 | 2707 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNCGUFKHRR is
function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate;
constant cPERIOD : time := 20 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNCGUFKHRR_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/db/alt_dspbuilder_if_statement_GNUCFELPE2.vhd | 4 | 1405 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNUCFELPE2 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b)";
number_inputs : integer := 2;
width : natural := 16);
port(
true : out std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNUCFELPE2 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(15 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b)) ;
true <= result;
end architecture;
| mit |
Given-Jiang/Add_Frame | tb_Add_Frame/db/alt_dspbuilder_delay_GNVCBR7UZP.vhd | 3 | 1050 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVCBR7UZP is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000001";
width : positive := 12);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNVCBR7UZP is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 12,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit |
Given-Jiang/Add_Frame | Add_Frame_dspbuilder/hdl/alt_dspbuilder_delay_GNVCBR7UZP.vhd | 3 | 1050 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVCBR7UZP is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000001";
width : positive := 12);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNVCBR7UZP is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 12,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit |
monotone-RK/FACE | IEICE-Trans/8-way/src/ip_pcie/PCIeGen2x8If128_sim_netlist.vhdl | 1 | 4993872 | null | mit |
Xion345/fpga-projects | library/basic/counter_mod_m.vhd | 1 | 1083 | -- Simple modulo m counter
-- 20/07/2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_mod_m is
generic(
N: integer := 4; -- Number of bits
M: integer := 10 -- Maximum value
);
port(
clk: in std_logic;
reset: in std_logic; -- Asynchronous reset
max_tick: out std_logic; -- Maximum value reached tick
q: out std_logic_vector(N-1 downto 0) -- Current value
);
end counter_mod_m;
architecture counter_mod_m_arch of counter_mod_m is
signal r_reg: unsigned(N-1 downto 0);
signal r_next: unsigned(N-1 downto 0);
begin
-- State register
process(clk, reset)
begin
if (reset='1') then
r_reg <= (others => '0');
elsif (rising_edge(clk)) then
r_reg <= r_next;
end if;
end process;
-- Next state logic
r_next <= r_reg + 1 when r_reg /= (M-1) else
(others => '0');
-- Output logic
q <= std_logic_vector(r_reg);
max_tick <= '1' when r_reg = (M-1) else '0';
end counter_mod_m_arch;
| mit |
Xion345/fpga-projects | projects/vga-palette/vga_palette_top.vhd | 1 | 1205 | -- VGA Palette testing circuit
--
library ieee;
use ieee.std_logic_1164.ALL;
entity vga_palette_top is
port(
clk, reset: in std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(2 downto 1);
hsync: out std_logic;
vsync: out std_logic;
blue_on: in std_logic;
green_on: in std_logic;
red_on: in std_logic
);
end vga_palette_top;
architecture vga_palette_top_arch of vga_palette_top is
-- VGA Sync.
signal pixel_tick: std_logic;
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal video_on: std_logic;
begin
vga_sync: entity work.vga_sync
port map(clk => clk, reset => reset,
pixel_tick => pixel_tick,
x => pixel_x, y => pixel_y,
hsync => hsync, vsync => vsync, video_on => video_on);
vga_palette: entity work.vga_palette
port map(pixel_x => pixel_x(6 downto 0), pixel_y => pixel_y(6 downto 0),
video_on => video_on,
red => red, green => green, blue => blue,
red_on => red_on, green_on => green_on, blue_on => blue_on);
end vga_palette_top_arch;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_clock_GNQFU4PUDH.vhd | 20 | 569 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNQFU4PUDH is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNQFU4PUDH is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= aclr;
end architecture; | mit |
Siliciumer/DOS-Mario-FPGA | DOS_Mario.srcs/sources_1/ip/dist_mem_gen_1/dist_mem_gen_v8_0_10/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd | 3 | 173134 | `protect begin_protected
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`protect end_protected
| mit |
Andy46/OV7670-VHDL | OV7670/src/mod_VGA/mod_VGA.vhd | 1 | 4153 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:32:02 05/05/2014
-- Design Name:
-- Module Name: mod_VGA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mod_VGA is
Port ( clk_100MHz, reset : in STD_LOGIC; -- FPGA's clock, FPGA's reset(Active Low)
-- VGA pins --
vga_vsync, vga_hsync : out STD_LOGIC; -- VGA Vertical synchronization, VGA Horizontal synchronization
vga_red, vga_green, vga_blue : out STD_LOGIC_VECTOR(3 downto 0) -- VGA colors (4bits)
-- vga_red, vga_green, vga_blue : out STD_LOGIC; -- VGA colors (1bit)
-- VGA pins --
);
end mod_VGA;
architecture Behavioral of mod_VGA is
--Divisor de frecuencia
component Divisor4 is
Port ( clk_in, reset : in std_logic;
clk_out : out std_logic);
end component;
signal clk_25MHz : std_logic;
--Contadores vertical y horizontal
component contador10bits is
Port ( A : in STD_LOGIC_VECTOR (9 downto 0);
A_next : out STD_LOGIC_VECTOR (9 downto 0));
end component;
--Señales
signal Vcount, Vcount_next : std_logic_vector(9 downto 0);
signal Hcount, Hcount_next : std_logic_vector(9 downto 0);
--Imagen
component mod_Image is
Port ( clk_100MHz, reset : in STD_LOGIC;
readX, readY : in STD_LOGIC_VECTOR (9 downto 0); -- Pixel read addr(row, column)
vga_red, vga_green, vga_blue : out STD_LOGIC_VECTOR (3 downto 0); -- Pixel read color
writeX, writeY : in std_logic_vector (9 downto 0); -- Pixel write addr(row, column)
pixel : in std_logic_vector(7 downto 0) -- Pixel write color
);
end component;
begin
--Divisor de frecuencia 1/4
Div_VGA: Divisor4 port map(clk_in => clk_100MHz, reset => reset, clk_out => clk_25MHz);
--Asignar colores
Im: mod_Image port map( clk_100MHz => clk_100MHz, reset => reset, readX => Hcount, readY => Vcount,
vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue,
writeX => std_logic_vector(to_unsigned(640, 10)), writeY =>std_logic_vector(to_unsigned(480,10)),
pixel => "00000011" );
--Process VSYNC
FA_Vsync: contador10bits port map(A => Vcount, A_next => Vcount_next);
process(clk_25MHz, reset, Hcount, Vcount)
begin
if clk_25MHz'event and clk_25MHz = '1' then
if reset = '0' then
Vcount <= (others => '0');
vga_vsync <= '0';
else
if Hcount = std_logic_vector(to_unsigned(800, 10)) then -- 1040 | 800 | 800
if Vcount = std_logic_vector(to_unsigned(525, 10)) then -- 665 | 525 | 448
Vcount <= (others => '0');
else
Vcount <= Vcount_next;
end if;
if Vcount >= std_logic_vector(to_unsigned(490, 10)) and Vcount < std_logic_vector(to_unsigned(492, 10)) then -- 636,642 | 490,492 | 386,388
vga_vsync <= '1';
else
vga_vsync <= '0';
end if;
end if;
end if;
end if;
end process;
--Process HSYNC
FA_Hsync: contador10bits port map(A => Hcount, A_next => Hcount_next);
process(clk_25MHz, reset)
begin
if clk_25MHz'event and clk_25MHz = '1' then
if reset = '0' then
Hcount <= (others => '0');
vga_hsync <= '0';
else
if Hcount = std_logic_vector(to_unsigned(800, 10)) then -- 1040 | 800 | 800
Hcount <= (others => '0');
else
Hcount <= Hcount_next;
end if;
if Hcount >= std_logic_vector(to_unsigned(656, 10)) and Hcount < std_logic_vector(to_unsigned(752, 10)) then -- 855, 975 | 656,752 | 656,752
vga_hsync <= '1';
else
vga_hsync <= '0';
end if;
end if;
end if;
end process;
end Behavioral; | mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/hdl/alt_dspbuilder_multiply_add_GNKLXFKAO3.vhd | 8 | 1702 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : string := "AddAdd";
data3b_const : string := "00011110";
data2b_const : string := "10010110";
representation : string := "UNSIGNED";
dataWidth : integer := 8;
data4b_const : string := "01001100";
number_multipliers : integer := 3;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 1;
data1b_const : string := "01001100";
use_b_consts : natural := 1);
port(
clock : in std_logic;
aclr : in std_logic;
data1a : in std_logic_vector(7 downto 0);
data2a : in std_logic_vector(7 downto 0);
data3a : in std_logic_vector(7 downto 0);
result : out std_logic_vector(17 downto 0);
user_aclr : in std_logic;
ena : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_multiply_add_GNKLXFKAO3 is
Begin
MultiplyAddi : alt_dspbuilder_AltMultConst generic map (
CA => "01001100",
CB => "10010110",
CC => "00011110",
CD => "01001100",
width_a => 8,
width_r => 18,
RegStruct => NoRegister,
data_signed => false
)
port map (
datain => data1a ,
datbin => data2a ,
datcin => data3a ,
datdin => "00000000" ,
dataout => result(17 downto 0),
clock => clock,
ena => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture; | mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/db/alt_dspbuilder_bus_concat_GNIIOZRPJD.vhd | 12 | 653 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic ( widthB : natural := 8;
widthA : natural := 8);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNIIOZRPJD is
Begin
output <= a & b;
end architecture; | mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/db/alt_dspbuilder_SBF.vhd | 20 | 8869 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_testbench_capture_GNHCRI5YMO.vhd | 20 | 1775 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNHCRI5YMO is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_SDelay.vhd | 20 | 3612 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SDelay is
generic (
lpm_width : positive :=8;
lpm_delay : positive :=2;
SequenceLength : positive :=1;
SequenceValue : std_logic_vector :="1"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0) :=(others=>'0')
);
end alt_dspbuilder_SDelay;
architecture SDelay_SYNTH of alt_dspbuilder_SDelay is
type StdUArray is array (lpm_delay-1 downto 0) of std_logic_vector (lpm_width-1 downto 0);
signal DelayLine : StdUArray;
signal dataa_int : std_logic_vector(lpm_width-1 downto 0);
signal seqenable : std_logic ;
signal enadff : std_logic ;
signal aclr_i : std_logic ;
begin
aclr_i <= aclr or user_aclr;
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> lpm_width)
port map (d => dataa, r => dataa_int);
gnoseq: if ((SequenceLength=1) and (SequenceValue="1")) generate
enadff <= ena;
end generate gnoseq;
gseq: if not ((SequenceLength=1) and (SequenceValue="1")) generate
u:alt_dspbuilder_vecseq generic map (SequenceLength=>SequenceLength,SequenceValue=>SequenceValue)
port map (clock=>clock, ena=>ena, aclr=>aclr_i, sclr=>sclr, yout=> seqenable);
enadff <= seqenable and ena;
end generate gseq;
gen1:if lpm_delay=1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
result <=(others=>'0');
elsif clock'event and clock='1' then
if (sclr ='1') then
result <=(others=>'0');
elsif enadff ='1' then
result <= dataa_int;
end if ;
end if ;
end process ;
end generate ;
gen2:if lpm_delay>1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
DelayLine <= (others => (others => '0'));
elsif clock'event and clock='1' then
if (sclr='1') then
DelayLine <= (others => (others => '0'));
elsif (enadff='1') then
DelayLine(0) <= dataa_int;
for i in 1 to lpm_delay-1 loop
DelayLine(i) <= DelayLine(i-1);
end loop;
end if ;
end if ;
end process ;
result <= DelayLine(lpm_delay-1);
end generate ;
end SDelay_SYNTH;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/db/alt_dspbuilder_SDelay.vhd | 20 | 3612 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SDelay is
generic (
lpm_width : positive :=8;
lpm_delay : positive :=2;
SequenceLength : positive :=1;
SequenceValue : std_logic_vector :="1"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0) :=(others=>'0')
);
end alt_dspbuilder_SDelay;
architecture SDelay_SYNTH of alt_dspbuilder_SDelay is
type StdUArray is array (lpm_delay-1 downto 0) of std_logic_vector (lpm_width-1 downto 0);
signal DelayLine : StdUArray;
signal dataa_int : std_logic_vector(lpm_width-1 downto 0);
signal seqenable : std_logic ;
signal enadff : std_logic ;
signal aclr_i : std_logic ;
begin
aclr_i <= aclr or user_aclr;
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> lpm_width)
port map (d => dataa, r => dataa_int);
gnoseq: if ((SequenceLength=1) and (SequenceValue="1")) generate
enadff <= ena;
end generate gnoseq;
gseq: if not ((SequenceLength=1) and (SequenceValue="1")) generate
u:alt_dspbuilder_vecseq generic map (SequenceLength=>SequenceLength,SequenceValue=>SequenceValue)
port map (clock=>clock, ena=>ena, aclr=>aclr_i, sclr=>sclr, yout=> seqenable);
enadff <= seqenable and ena;
end generate gseq;
gen1:if lpm_delay=1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
result <=(others=>'0');
elsif clock'event and clock='1' then
if (sclr ='1') then
result <=(others=>'0');
elsif enadff ='1' then
result <= dataa_int;
end if ;
end if ;
end process ;
end generate ;
gen2:if lpm_delay>1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
DelayLine <= (others => (others => '0'));
elsif clock'event and clock='1' then
if (sclr='1') then
DelayLine <= (others => (others => '0'));
elsif (enadff='1') then
DelayLine(0) <= dataa_int;
for i in 1 to lpm_delay-1 loop
DelayLine(i) <= DelayLine(i-1);
end loop;
end if ;
end if ;
end process ;
result <= DelayLine(lpm_delay-1);
end generate ;
end SDelay_SYNTH;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_multiplexer_GNCALBUTDR.vhd | 12 | 1253 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNCALBUTDR is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 24;
pipeline : natural := 0;
number_inputs : natural := 2);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(0 downto 0);
result : out std_logic_vector(23 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(23 downto 0);
in1 : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNCALBUTDR is
signal data_muxin : std_logic_vector(47 downto 0);
Begin
data_muxin <= in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 2,
lpm_widths => 1 ,
lpm_width => 24 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
| mit |
inmcm/Simon_Speck_Ciphers | VHDL/Speck_Constants.vhd | 3 | 2745 | -- Speck_Constants.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package SPECK_CONSTANTS is
function Round_Count_Lookup(key_size,block_size : integer range 0 to 256) return integer;
function Beta_Lookup(key_size,block_size : integer range 0 to 256) return integer;
function Alpha_Lookup(key_size,block_size : integer range 0 to 256) return integer;
end SPECK_CONSTANTS;
package body SPECK_CONSTANTS is
function Round_Count_Lookup(key_size,block_size : integer range 0 to 256) return integer is
variable round_count_tmp : integer range 0 to 63 := 0;
begin
-- Block Size 32 and Key Size 64 use 22 rounds
if (BLOCK_SIZE = 32 and KEY_SIZE = 64) then
round_count_tmp := 22;
-- Block Size 48 and Key Size 72 use 22 rounds
elsif (BLOCK_SIZE = 48 and KEY_SIZE = 72) then
round_count_tmp := 22;
-- Block Size 48 and Key Size 96 use 23 rounds
elsif (BLOCK_SIZE = 48 and KEY_SIZE = 96) then
round_count_tmp := 23;
-- Block Size 64 and Key Size 96 use 26 rounds
elsif (BLOCK_SIZE = 64 and KEY_SIZE = 96 ) then
round_count_tmp := 26;
-- Block Size 64 and Key Size 128 use 27 rounds
elsif (BLOCK_SIZE = 64 and KEY_SIZE = 128) then
round_count_tmp := 27;
-- Block Size 96 and Key Size 96 use 28 rounds
elsif (BLOCK_SIZE = 96 and KEY_SIZE = 96) then
round_count_tmp := 28;
-- Block Size 96 and Key Size 144 use 29 rounds
elsif (BLOCK_SIZE = 96 and KEY_SIZE = 144) then
round_count_tmp := 29;
-- Block Size 128 and Key Size 128 use 32 rounds
elsif (BLOCK_SIZE = 128 and KEY_SIZE = 128) then
round_count_tmp := 32;
-- Block Size 128 and Key Size 192 used 33 rounds
elsif (BLOCK_SIZE = 128 and KEY_SIZE = 192) then
round_count_tmp := 33;
-- Block Size 128 and Key Size 256 use 34 rounds
elsif (BLOCK_SIZE = 128 and KEY_SIZE = 256) then
round_count_tmp := 34;
end if;
return round_count_tmp;
end Round_Count_Lookup;
function Beta_Lookup(key_size,block_size : integer range 0 to 256) return integer is
variable b_tmp : integer range 0 to 3 := 0;
begin
-- Block Size 32 and Key Size 64 use beta rotate 2 bits
if (BLOCK_SIZE = 32 and KEY_SIZE = 64) then
b_tmp := 2;
-- All other key/block combinations use beta rotate 3 bits
else
b_tmp := 3;
end if;
return b_tmp;
end Beta_Lookup;
function Alpha_Lookup(key_size,block_size : integer range 0 to 256) return integer is
variable a_tmp : integer range 0 to 15 := 0;
begin
-- Block Size 32 and Key Size 64 use alpha rotate 7 bits
if (BLOCK_SIZE = 32 and KEY_SIZE = 64) then
a_tmp := 7;
-- All other key/block combinations use alpha rotate 8 bits
else
a_tmp := 8;
end if;
return a_tmp;
end Alpha_Lookup;
end SPECK_CONSTANTS; | mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/db/alt_dspbuilder_cast.vhd | 10 | 637 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_cast is
end entity alt_dspbuilder_cast;
architecture rtl of alt_dspbuilder_cast is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_sMultAltr.vhd | 12 | 3026 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sMultAltr is
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
lpm_representation : string ;
lpm_hint : string ;
OutputMsb : natural ;
OutputLsb : natural ;
pipeline : natural
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0);
result : out std_logic_vector(OutputMsb-OutputLsb downto 0)
);
end alt_dspbuilder_sMultAltr;
architecture synth of alt_dspbuilder_sMultAltr is
signal FullPrecisionResult : std_logic_vector(lpm_widtha+lpm_widthb-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gcomb: if pipeline=0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint
)
PORT MAP (
dataa => dataa,
datab => datab,
result => FullPrecisionResult
);
end generate gcomb;
greg: if pipeline>0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint,
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
datab => datab,
clken=> ena,
aclr => aclr_i,
clock => clock,
result => FullPrecisionResult);
end generate greg;
g:for i in OutputLsb to OutputMsb generate
result(i-OutputLsb) <= FullPrecisionResult(i);
end generate g;
end synth;
| mit |
biximilien/ArithmeticLogicUnit | arithmetic_logic_unit.vhd | 1 | 3495 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Cadre : GEN1333 - Conception des circuits integrés --
-- : Projet de conception individuel 1 --
-- Par : Maxime Gauthier --
-- Date : 03 / 21 / 2015 --
-- Fichier : arithmetic_logic_unit.vhd --
-- Description : VHDL pour une unité arithmétique logique générique (n bits) --
-- : basé sur du matériel de cours fourni par Ahmed Lakhsassi --
-- : et du code originellement écrit par Antoine Shaneen --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- librairie a inclure
library ieee;
use ieee.std_logic_1164.all;
-- déclaration de l'entité de l'unité arithmétique logique générique (n bits) paramétrable
entity arithmetic_logic_unit is
generic ( N : integer := 8);
port (
operand_a, operand_b : in std_logic_vector (N downto 1);
mode_selector : in std_logic_vector (3 downto 1);
result : out std_logic_vector (N downto 1);
overflow_flag, carry_flag, zero_flag, sign_flag, parity_flag : out std_logic
);
end arithmetic_logic_unit;
-- architecture structurelle de l'additionneur générique (n bits).
architecture arithmetic_logic_unit_impl of arithmetic_logic_unit is
-- declaration des composants
component adder_n
port(
augend, addend : in std_logic_vector ( N downto 1 );
sum : out std_logic_vector ( N downto 1 );
carry_flag : out std_logic
);
end component;
component subtractor_n
port(
minuend, subtrahend : in std_logic_vector ( N downto 1 );
difference : out std_logic_vector ( N downto 1 );
overflow_flag : out std_logic
);
end component;
component decoder38
port(
decoder_in : in std_logic_vector ( 3 downto 1 );
decoder_out : out std_logic_vector ( 8 downto 1 )
);
end component;
component right_shift_n
port (
rs_in : in std_logic_vector ( N downto 1 );
rs_out : out std_logic_vector ( N downto 1 )
);
end component;
component left_shift_n
port (
ls_in : in std_logic_vector ( N downto 1 );
ls_out : out std_logic_vector ( N downto 1 )
);
end component;
component comparator_n
port (
a, b : in std_logic_vector ( N downto 1 );
gt, eq : out std_logic
);
end component;
begin
-- Ca marche pas!
s1 <= operand_a, s2 <= operand_b when mode_selector = "00000000",
s3 <= operand_a, s4 <= operand_b when mode_selector = "00000010",
s5 <= operand_a when mode_selector = "00010000",
s6 <= operand_a when mode_selector = "00100000",
s7 <= operand_b when mode_selector = "01000000",
s8 <= operand_b when others;
adder: adder_n port map (s1, s2, result, carry_flag);
subtractor: subtractor_n port map (s3, s4, result, overflow_flag);
rs_a: right_shift_n port map (s5, result);
ls_a: left_shift_n port map (s6, result);
rs_b: right_shift_n port map (s7, result);
ls_b: left_shift_n port map (s8, result);
end arithmetic_logic_unit_impl;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_multiply_add_GNPSDKCBU2.vhd | 1 | 1730 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNPSDKCBU2 is
generic ( family : string := "Cyclone V";
direction : string := "AddAdd";
data3b_const : string := "00011110";
data2b_const : string := "10010110";
representation : string := "UNSIGNED";
dataWidth : integer := 8;
data4b_const : string := "01001100";
number_multipliers : integer := 3;
pipeline_register : string := "InputsMultiplierandAdder";
use_dedicated_circuitry : integer := 1;
data1b_const : string := "01001100";
use_b_consts : natural := 1);
port(
clock : in std_logic;
aclr : in std_logic;
data1a : in std_logic_vector(7 downto 0);
data2a : in std_logic_vector(7 downto 0);
data3a : in std_logic_vector(7 downto 0);
result : out std_logic_vector(17 downto 0);
user_aclr : in std_logic;
ena : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_multiply_add_GNPSDKCBU2 is
Begin
MultiplyAddi : alt_dspbuilder_AltMultConst generic map (
CA => "01001100",
CB => "10010110",
CC => "00011110",
CD => "01001100",
width_a => 8,
width_r => 18,
RegStruct => InputsMultiplierandAdder,
data_signed => false
)
port map (
datain => data1a ,
datbin => data2a ,
datcin => data3a ,
datdin => "00000000" ,
dataout => result(17 downto 0),
clock => clock,
ena => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture; | mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/db/alt_dspbuilder_constant.vhd | 10 | 649 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/db/alt_dspbuilder_port.vhd | 10 | 637 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_testbench_clock.vhd | 10 | 2158 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
begin
alt_dspbuilder_testbench_clock_GNCGUFKHRR_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "20 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNCGUFKHRR_0: alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "20 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "20 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/hdl/alt_dspbuilder_testbench_clock.vhd | 10 | 2218 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/db/alt_dspbuilder_testbench_clock.vhd | 10 | 2218 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_port_GNPWNZWFO7.vhd | 2 | 489 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNPWNZWFO7 is
port(
input : in std_logic_vector(16 downto 0);
output : out std_logic_vector(16 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNPWNZWFO7 is
Begin
-- Straight Bypass block
output <= input;
end architecture; | mit |
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| mit |
biximilien/ArithmeticLogicUnit | and_gate.vhd | 1 | 252 | library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (
x, y : in std_ulogic;
z : out std_ulogic
);
end entity and_gate;
architecture and_gate_impl of and_gate is
begin
z <= x and y;
end architecture and_gate_impl;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/db/alt_dspbuilder_MultAdd.vhd | 12 | 23128 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/altera_lnsim/generic_mux/_primary.vhd | 5 | 266 | library verilog;
use verilog.vl_types.all;
entity generic_mux is
port(
din : in vl_logic_vector(63 downto 0);
sel : in vl_logic_vector(5 downto 0);
dout : out vl_logic
);
end generic_mux;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/altera_lnsim/altera_arriavgz_pll/_primary.vhd | 5 | 70300 | library verilog;
use verilog.vl_types.all;
entity altera_arriavgz_pll is
generic(
number_of_counters: integer := 18;
number_of_fplls : integer := 1;
number_of_extclks: integer := 4;
number_of_dlls : integer := 2;
number_of_lvds : integer := 4;
pll_auto_clk_sw_en_0: string := "false";
pll_clk_loss_edge_0: string := "both_edges";
pll_clk_loss_sw_en_0: string := "false";
pll_clk_sw_dly_0: integer := 0;
pll_clkin_0_src_0: string := "clk_0";
pll_clkin_1_src_0: string := "clk_0";
pll_manu_clk_sw_en_0: string := "false";
pll_sw_refclk_src_0: string := "clk_0";
pll_auto_clk_sw_en_1: string := "false";
pll_clk_loss_edge_1: string := "both_edges";
pll_clk_loss_sw_en_1: string := "false";
pll_clk_sw_dly_1: integer := 0;
pll_clkin_0_src_1: string := "clk_1";
pll_clkin_1_src_1: string := "clk_1";
pll_manu_clk_sw_en_1: string := "false";
pll_sw_refclk_src_1: string := "clk_1";
pll_output_clock_frequency_0: string := "700.0 MHz";
reference_clock_frequency_0: string := "700.0 MHz";
mimic_fbclk_type_0: string := "gclk";
dsm_accumulator_reset_value_0: integer := 0;
forcelock_0 : string := "false";
nreset_invert_0 : string := "false";
pll_atb_0 : integer := 0;
pll_bwctrl_0 : integer := 1000;
pll_cmp_buf_dly_0: string := "0 ps";
pll_cp_comp_0 : string := "true";
pll_cp_current_0: integer := 20;
pll_ctrl_override_setting_0: string := "true";
pll_dsm_dither_0: string := "disable";
pll_dsm_out_sel_0: string := "disable";
pll_dsm_reset_0 : string := "false";
pll_ecn_bypass_0: string := "false";
pll_ecn_test_en_0: string := "false";
pll_enable_0 : string := "true";
pll_fbclk_mux_1_0: string := "fb";
pll_fbclk_mux_2_0: string := "m_cnt";
pll_fractional_carry_out_0: integer := 24;
pll_fractional_division_0: integer := 1;
pll_fractional_value_ready_0: string := "true";
pll_lf_testen_0 : string := "false";
pll_lock_fltr_cfg_0: integer := 25;
pll_lock_fltr_test_0: string := "false";
pll_m_cnt_bypass_en_0: string := "false";
pll_m_cnt_coarse_dly_0: string := "0 ps";
pll_m_cnt_fine_dly_0: string := "0 ps";
pll_m_cnt_hi_div_0: integer := 3;
pll_m_cnt_in_src_0: string := "ph_mux_clk";
pll_m_cnt_lo_div_0: integer := 3;
pll_m_cnt_odd_div_duty_en_0: string := "false";
pll_m_cnt_ph_mux_prst_0: integer := 0;
pll_m_cnt_prst_0: integer := 256;
pll_n_cnt_bypass_en_0: string := "true";
pll_n_cnt_coarse_dly_0: string := "0 ps";
pll_n_cnt_fine_dly_0: string := "0 ps";
pll_n_cnt_hi_div_0: integer := 1;
pll_n_cnt_lo_div_0: integer := 1;
pll_n_cnt_odd_div_duty_en_0: string := "false";
pll_ref_buf_dly_0: string := "0 ps";
pll_reg_boost_0 : integer := 0;
pll_regulator_bypass_0: string := "false";
pll_ripplecap_ctrl_0: integer := 0;
pll_slf_rst_0 : string := "false";
pll_tclk_mux_en_0: string := "false";
pll_tclk_sel_0 : string := "n_src";
pll_test_enable_0: string := "false";
pll_testdn_enable_0: string := "false";
pll_testup_enable_0: string := "false";
pll_unlock_fltr_cfg_0: integer := 1;
pll_vco_div_0 : integer := 0;
pll_vco_ph0_en_0: string := "true";
pll_vco_ph1_en_0: string := "true";
pll_vco_ph2_en_0: string := "true";
pll_vco_ph3_en_0: string := "true";
pll_vco_ph4_en_0: string := "true";
pll_vco_ph5_en_0: string := "true";
pll_vco_ph6_en_0: string := "true";
pll_vco_ph7_en_0: string := "true";
pll_vctrl_test_voltage_0: integer := 750;
vccd0g_atb_0 : string := "disable";
vccd0g_output_0 : integer := 0;
vccd1g_atb_0 : string := "disable";
vccd1g_output_0 : integer := 0;
vccm1g_tap_0 : integer := 2;
vccr_pd_0 : string := "false";
vcodiv_override_0: string := "false";
sim_use_fast_model_0: string := "false";
pll_output_clock_frequency_1: string := "300.0 MHz";
reference_clock_frequency_1: string := "100.0 MHz";
mimic_fbclk_type_1: string := "gclk";
dsm_accumulator_reset_value_1: integer := 0;
forcelock_1 : string := "false";
nreset_invert_1 : string := "false";
pll_atb_1 : integer := 0;
pll_bwctrl_1 : integer := 1000;
pll_cmp_buf_dly_1: string := "0 ps";
pll_cp_comp_1 : string := "true";
pll_cp_current_1: integer := 30;
pll_ctrl_override_setting_1: string := "false";
pll_dsm_dither_1: string := "disable";
pll_dsm_out_sel_1: string := "disable";
pll_dsm_reset_1 : string := "false";
pll_ecn_bypass_1: string := "false";
pll_ecn_test_en_1: string := "false";
pll_enable_1 : string := "false";
pll_fbclk_mux_1_1: string := "glb";
pll_fbclk_mux_2_1: string := "fb_1";
pll_fractional_carry_out_1: integer := 24;
pll_fractional_division_1: integer := 1;
pll_fractional_value_ready_1: string := "true";
pll_lf_testen_1 : string := "false";
pll_lock_fltr_cfg_1: integer := 25;
pll_lock_fltr_test_1: string := "false";
pll_m_cnt_bypass_en_1: string := "false";
pll_m_cnt_coarse_dly_1: string := "0 ps";
pll_m_cnt_fine_dly_1: string := "0 ps";
pll_m_cnt_hi_div_1: integer := 2;
pll_m_cnt_in_src_1: string := "ph_mux_clk";
pll_m_cnt_lo_div_1: integer := 1;
pll_m_cnt_odd_div_duty_en_1: string := "true";
pll_m_cnt_ph_mux_prst_1: integer := 0;
pll_m_cnt_prst_1: integer := 256;
pll_n_cnt_bypass_en_1: string := "true";
pll_n_cnt_coarse_dly_1: string := "0 ps";
pll_n_cnt_fine_dly_1: string := "0 ps";
pll_n_cnt_hi_div_1: integer := 256;
pll_n_cnt_lo_div_1: integer := 256;
pll_n_cnt_odd_div_duty_en_1: string := "false";
pll_ref_buf_dly_1: string := "0 ps";
pll_reg_boost_1 : integer := 0;
pll_regulator_bypass_1: string := "false";
pll_ripplecap_ctrl_1: integer := 0;
pll_slf_rst_1 : string := "false";
pll_tclk_mux_en_1: string := "false";
pll_tclk_sel_1 : string := "n_src";
pll_test_enable_1: string := "false";
pll_testdn_enable_1: string := "false";
pll_testup_enable_1: string := "false";
pll_unlock_fltr_cfg_1: integer := 2;
pll_vco_div_1 : integer := 1;
pll_vco_ph0_en_1: string := "true";
pll_vco_ph1_en_1: string := "true";
pll_vco_ph2_en_1: string := "true";
pll_vco_ph3_en_1: string := "true";
pll_vco_ph4_en_1: string := "true";
pll_vco_ph5_en_1: string := "true";
pll_vco_ph6_en_1: string := "true";
pll_vco_ph7_en_1: string := "true";
pll_vctrl_test_voltage_1: integer := 750;
vccd0g_atb_1 : string := "disable";
vccd0g_output_1 : integer := 0;
vccd1g_atb_1 : string := "disable";
vccd1g_output_1 : integer := 0;
vccm1g_tap_1 : integer := 2;
vccr_pd_1 : string := "false";
vcodiv_override_1: string := "false";
sim_use_fast_model_1: string := "false";
output_clock_frequency_0: string := "100.0 MHz";
enable_output_counter_0: string := "true";
phase_shift_0 : string := "0 ps";
duty_cycle_0 : integer := 50;
c_cnt_coarse_dly_0: string := "0 ps";
c_cnt_fine_dly_0: string := "0 ps";
c_cnt_in_src_0 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_0: integer := 0;
c_cnt_prst_0 : integer := 1;
cnt_fpll_src_0 : string := "fpll_0";
dprio0_cnt_bypass_en_0: string := "true";
dprio0_cnt_hi_div_0: integer := 3;
dprio0_cnt_lo_div_0: integer := 3;
dprio0_cnt_odd_div_even_duty_en_0: string := "false";
dprio1_cnt_bypass_en_0: vl_notype;
dprio1_cnt_hi_div_0: vl_notype;
dprio1_cnt_lo_div_0: vl_notype;
dprio1_cnt_odd_div_even_duty_en_0: vl_notype;
output_clock_frequency_1: string := "0 ps";
enable_output_counter_1: string := "true";
phase_shift_1 : string := "0 ps";
duty_cycle_1 : integer := 50;
c_cnt_coarse_dly_1: string := "0 ps";
c_cnt_fine_dly_1: string := "0 ps";
c_cnt_in_src_1 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_1: integer := 0;
c_cnt_prst_1 : integer := 1;
cnt_fpll_src_1 : string := "fpll_0";
dprio0_cnt_bypass_en_1: string := "true";
dprio0_cnt_hi_div_1: integer := 2;
dprio0_cnt_lo_div_1: integer := 1;
dprio0_cnt_odd_div_even_duty_en_1: string := "true";
dprio1_cnt_bypass_en_1: vl_notype;
dprio1_cnt_hi_div_1: vl_notype;
dprio1_cnt_lo_div_1: vl_notype;
dprio1_cnt_odd_div_even_duty_en_1: vl_notype;
output_clock_frequency_2: string := "0 ps";
enable_output_counter_2: string := "true";
phase_shift_2 : string := "0 ps";
duty_cycle_2 : integer := 50;
c_cnt_coarse_dly_2: string := "0 ps";
c_cnt_fine_dly_2: string := "0 ps";
c_cnt_in_src_2 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_2: integer := 0;
c_cnt_prst_2 : integer := 1;
cnt_fpll_src_2 : string := "fpll_0";
dprio0_cnt_bypass_en_2: string := "true";
dprio0_cnt_hi_div_2: integer := 1;
dprio0_cnt_lo_div_2: integer := 1;
dprio0_cnt_odd_div_even_duty_en_2: string := "false";
dprio1_cnt_bypass_en_2: vl_notype;
dprio1_cnt_hi_div_2: vl_notype;
dprio1_cnt_lo_div_2: vl_notype;
dprio1_cnt_odd_div_even_duty_en_2: vl_notype;
output_clock_frequency_3: string := "0 ps";
enable_output_counter_3: string := "true";
phase_shift_3 : string := "0 ps";
duty_cycle_3 : integer := 50;
c_cnt_coarse_dly_3: string := "0 ps";
c_cnt_fine_dly_3: string := "0 ps";
c_cnt_in_src_3 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_3: integer := 0;
c_cnt_prst_3 : integer := 1;
cnt_fpll_src_3 : string := "fpll_0";
dprio0_cnt_bypass_en_3: string := "false";
dprio0_cnt_hi_div_3: integer := 1;
dprio0_cnt_lo_div_3: integer := 1;
dprio0_cnt_odd_div_even_duty_en_3: string := "false";
dprio1_cnt_bypass_en_3: vl_notype;
dprio1_cnt_hi_div_3: vl_notype;
dprio1_cnt_lo_div_3: vl_notype;
dprio1_cnt_odd_div_even_duty_en_3: vl_notype;
output_clock_frequency_4: string := "0 ps";
enable_output_counter_4: string := "true";
phase_shift_4 : string := "0 ps";
duty_cycle_4 : integer := 50;
c_cnt_coarse_dly_4: string := "0 ps";
c_cnt_fine_dly_4: string := "0 ps";
c_cnt_in_src_4 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_4: integer := 0;
c_cnt_prst_4 : integer := 1;
cnt_fpll_src_4 : string := "fpll_0";
dprio0_cnt_bypass_en_4: string := "false";
dprio0_cnt_hi_div_4: integer := 1;
dprio0_cnt_lo_div_4: integer := 1;
dprio0_cnt_odd_div_even_duty_en_4: string := "false";
dprio1_cnt_bypass_en_4: vl_notype;
dprio1_cnt_hi_div_4: vl_notype;
dprio1_cnt_lo_div_4: vl_notype;
dprio1_cnt_odd_div_even_duty_en_4: vl_notype;
output_clock_frequency_5: string := "0 ps";
enable_output_counter_5: string := "true";
phase_shift_5 : string := "0 ps";
duty_cycle_5 : integer := 50;
c_cnt_coarse_dly_5: string := "0 ps";
c_cnt_fine_dly_5: string := "0 ps";
c_cnt_in_src_5 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_5: integer := 0;
c_cnt_prst_5 : integer := 1;
cnt_fpll_src_5 : string := "fpll_0";
dprio0_cnt_bypass_en_5: string := "false";
dprio0_cnt_hi_div_5: integer := 1;
dprio0_cnt_lo_div_5: integer := 1;
dprio0_cnt_odd_div_even_duty_en_5: string := "false";
dprio1_cnt_bypass_en_5: vl_notype;
dprio1_cnt_hi_div_5: vl_notype;
dprio1_cnt_lo_div_5: vl_notype;
dprio1_cnt_odd_div_even_duty_en_5: vl_notype;
output_clock_frequency_6: string := "0 ps";
enable_output_counter_6: string := "true";
phase_shift_6 : string := "0 ps";
duty_cycle_6 : integer := 50;
c_cnt_coarse_dly_6: string := "0 ps";
c_cnt_fine_dly_6: string := "0 ps";
c_cnt_in_src_6 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_6: integer := 0;
c_cnt_prst_6 : integer := 1;
cnt_fpll_src_6 : string := "fpll_0";
dprio0_cnt_bypass_en_6: string := "false";
dprio0_cnt_hi_div_6: integer := 1;
dprio0_cnt_lo_div_6: integer := 1;
dprio0_cnt_odd_div_even_duty_en_6: string := "false";
dprio1_cnt_bypass_en_6: vl_notype;
dprio1_cnt_hi_div_6: vl_notype;
dprio1_cnt_lo_div_6: vl_notype;
dprio1_cnt_odd_div_even_duty_en_6: vl_notype;
output_clock_frequency_7: string := "0 ps";
enable_output_counter_7: string := "true";
phase_shift_7 : string := "0 ps";
duty_cycle_7 : integer := 50;
c_cnt_coarse_dly_7: string := "0 ps";
c_cnt_fine_dly_7: string := "0 ps";
c_cnt_in_src_7 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_7: integer := 0;
c_cnt_prst_7 : integer := 1;
cnt_fpll_src_7 : string := "fpll_0";
dprio0_cnt_bypass_en_7: string := "false";
dprio0_cnt_hi_div_7: integer := 1;
dprio0_cnt_lo_div_7: integer := 1;
dprio0_cnt_odd_div_even_duty_en_7: string := "false";
dprio1_cnt_bypass_en_7: vl_notype;
dprio1_cnt_hi_div_7: vl_notype;
dprio1_cnt_lo_div_7: vl_notype;
dprio1_cnt_odd_div_even_duty_en_7: vl_notype;
output_clock_frequency_8: string := "0 ps";
enable_output_counter_8: string := "true";
phase_shift_8 : string := "0 ps";
duty_cycle_8 : integer := 50;
c_cnt_coarse_dly_8: string := "0 ps";
c_cnt_fine_dly_8: string := "0 ps";
c_cnt_in_src_8 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_8: integer := 0;
c_cnt_prst_8 : integer := 1;
cnt_fpll_src_8 : string := "fpll_0";
dprio0_cnt_bypass_en_8: string := "false";
dprio0_cnt_hi_div_8: integer := 1;
dprio0_cnt_lo_div_8: integer := 1;
dprio0_cnt_odd_div_even_duty_en_8: string := "false";
dprio1_cnt_bypass_en_8: vl_notype;
dprio1_cnt_hi_div_8: vl_notype;
dprio1_cnt_lo_div_8: vl_notype;
dprio1_cnt_odd_div_even_duty_en_8: vl_notype;
output_clock_frequency_9: string := "0 ps";
enable_output_counter_9: string := "true";
phase_shift_9 : string := "0 ps";
duty_cycle_9 : integer := 50;
c_cnt_coarse_dly_9: string := "0 ps";
c_cnt_fine_dly_9: string := "0 ps";
c_cnt_in_src_9 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_9: integer := 0;
c_cnt_prst_9 : integer := 1;
cnt_fpll_src_9 : string := "fpll_0";
dprio0_cnt_bypass_en_9: string := "false";
dprio0_cnt_hi_div_9: integer := 1;
dprio0_cnt_lo_div_9: integer := 1;
dprio0_cnt_odd_div_even_duty_en_9: string := "false";
dprio1_cnt_bypass_en_9: vl_notype;
dprio1_cnt_hi_div_9: vl_notype;
dprio1_cnt_lo_div_9: vl_notype;
dprio1_cnt_odd_div_even_duty_en_9: vl_notype;
output_clock_frequency_10: string := "0 ps";
enable_output_counter_10: string := "true";
phase_shift_10 : string := "0 ps";
duty_cycle_10 : integer := 50;
c_cnt_coarse_dly_10: string := "0 ps";
c_cnt_fine_dly_10: string := "0 ps";
c_cnt_in_src_10 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_10: integer := 0;
c_cnt_prst_10 : integer := 1;
cnt_fpll_src_10 : string := "fpll_0";
dprio0_cnt_bypass_en_10: string := "false";
dprio0_cnt_hi_div_10: integer := 1;
dprio0_cnt_lo_div_10: integer := 1;
dprio0_cnt_odd_div_even_duty_en_10: string := "false";
dprio1_cnt_bypass_en_10: vl_notype;
dprio1_cnt_hi_div_10: vl_notype;
dprio1_cnt_lo_div_10: vl_notype;
dprio1_cnt_odd_div_even_duty_en_10: vl_notype;
output_clock_frequency_11: string := "0 ps";
enable_output_counter_11: string := "true";
phase_shift_11 : string := "0 ps";
duty_cycle_11 : integer := 50;
c_cnt_coarse_dly_11: string := "0 ps";
c_cnt_fine_dly_11: string := "0 ps";
c_cnt_in_src_11 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_11: integer := 0;
c_cnt_prst_11 : integer := 1;
cnt_fpll_src_11 : string := "fpll_0";
dprio0_cnt_bypass_en_11: string := "false";
dprio0_cnt_hi_div_11: integer := 1;
dprio0_cnt_lo_div_11: integer := 1;
dprio0_cnt_odd_div_even_duty_en_11: string := "false";
dprio1_cnt_bypass_en_11: vl_notype;
dprio1_cnt_hi_div_11: vl_notype;
dprio1_cnt_lo_div_11: vl_notype;
dprio1_cnt_odd_div_even_duty_en_11: vl_notype;
output_clock_frequency_12: string := "0 ps";
enable_output_counter_12: string := "true";
phase_shift_12 : string := "0 ps";
duty_cycle_12 : integer := 50;
c_cnt_coarse_dly_12: string := "0 ps";
c_cnt_fine_dly_12: string := "0 ps";
c_cnt_in_src_12 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_12: integer := 0;
c_cnt_prst_12 : integer := 1;
cnt_fpll_src_12 : string := "fpll_0";
dprio0_cnt_bypass_en_12: string := "false";
dprio0_cnt_hi_div_12: integer := 1;
dprio0_cnt_lo_div_12: integer := 1;
dprio0_cnt_odd_div_even_duty_en_12: string := "false";
dprio1_cnt_bypass_en_12: vl_notype;
dprio1_cnt_hi_div_12: vl_notype;
dprio1_cnt_lo_div_12: vl_notype;
dprio1_cnt_odd_div_even_duty_en_12: vl_notype;
output_clock_frequency_13: string := "0 ps";
enable_output_counter_13: string := "true";
phase_shift_13 : string := "0 ps";
duty_cycle_13 : integer := 50;
c_cnt_coarse_dly_13: string := "0 ps";
c_cnt_fine_dly_13: string := "0 ps";
c_cnt_in_src_13 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_13: integer := 0;
c_cnt_prst_13 : integer := 1;
cnt_fpll_src_13 : string := "fpll_0";
dprio0_cnt_bypass_en_13: string := "false";
dprio0_cnt_hi_div_13: integer := 1;
dprio0_cnt_lo_div_13: integer := 1;
dprio0_cnt_odd_div_even_duty_en_13: string := "false";
dprio1_cnt_bypass_en_13: vl_notype;
dprio1_cnt_hi_div_13: vl_notype;
dprio1_cnt_lo_div_13: vl_notype;
dprio1_cnt_odd_div_even_duty_en_13: vl_notype;
output_clock_frequency_14: string := "0 ps";
enable_output_counter_14: string := "true";
phase_shift_14 : string := "0 ps";
duty_cycle_14 : integer := 50;
c_cnt_coarse_dly_14: string := "0 ps";
c_cnt_fine_dly_14: string := "0 ps";
c_cnt_in_src_14 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_14: integer := 0;
c_cnt_prst_14 : integer := 1;
cnt_fpll_src_14 : string := "fpll_0";
dprio0_cnt_bypass_en_14: string := "false";
dprio0_cnt_hi_div_14: integer := 1;
dprio0_cnt_lo_div_14: integer := 1;
dprio0_cnt_odd_div_even_duty_en_14: string := "false";
dprio1_cnt_bypass_en_14: vl_notype;
dprio1_cnt_hi_div_14: vl_notype;
dprio1_cnt_lo_div_14: vl_notype;
dprio1_cnt_odd_div_even_duty_en_14: vl_notype;
output_clock_frequency_15: string := "0 ps";
enable_output_counter_15: string := "true";
phase_shift_15 : string := "0 ps";
duty_cycle_15 : integer := 50;
c_cnt_coarse_dly_15: string := "0 ps";
c_cnt_fine_dly_15: string := "0 ps";
c_cnt_in_src_15 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_15: integer := 0;
c_cnt_prst_15 : integer := 1;
cnt_fpll_src_15 : string := "fpll_0";
dprio0_cnt_bypass_en_15: string := "false";
dprio0_cnt_hi_div_15: integer := 1;
dprio0_cnt_lo_div_15: integer := 1;
dprio0_cnt_odd_div_even_duty_en_15: string := "false";
dprio1_cnt_bypass_en_15: vl_notype;
dprio1_cnt_hi_div_15: vl_notype;
dprio1_cnt_lo_div_15: vl_notype;
dprio1_cnt_odd_div_even_duty_en_15: vl_notype;
output_clock_frequency_16: string := "0 ps";
enable_output_counter_16: string := "true";
phase_shift_16 : string := "0 ps";
duty_cycle_16 : integer := 50;
c_cnt_coarse_dly_16: string := "0 ps";
c_cnt_fine_dly_16: string := "0 ps";
c_cnt_in_src_16 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_16: integer := 0;
c_cnt_prst_16 : integer := 1;
cnt_fpll_src_16 : string := "fpll_0";
dprio0_cnt_bypass_en_16: string := "false";
dprio0_cnt_hi_div_16: integer := 1;
dprio0_cnt_lo_div_16: integer := 1;
dprio0_cnt_odd_div_even_duty_en_16: string := "false";
dprio1_cnt_bypass_en_16: vl_notype;
dprio1_cnt_hi_div_16: vl_notype;
dprio1_cnt_lo_div_16: vl_notype;
dprio1_cnt_odd_div_even_duty_en_16: vl_notype;
output_clock_frequency_17: string := "0 ps";
enable_output_counter_17: string := "true";
phase_shift_17 : string := "0 ps";
duty_cycle_17 : integer := 50;
c_cnt_coarse_dly_17: string := "0 ps";
c_cnt_fine_dly_17: string := "0 ps";
c_cnt_in_src_17 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_17: integer := 0;
c_cnt_prst_17 : integer := 1;
cnt_fpll_src_17 : string := "fpll_0";
dprio0_cnt_bypass_en_17: string := "false";
dprio0_cnt_hi_div_17: integer := 1;
dprio0_cnt_lo_div_17: integer := 1;
dprio0_cnt_odd_div_even_duty_en_17: string := "false";
dprio1_cnt_bypass_en_17: vl_notype;
dprio1_cnt_hi_div_17: vl_notype;
dprio1_cnt_lo_div_17: vl_notype;
dprio1_cnt_odd_div_even_duty_en_17: vl_notype;
dpa_output_clock_frequency_0: string := "0 ps";
pll_vcoph_div_0 : integer := 1;
dpa_output_clock_frequency_1: string := "0 ps";
pll_vcoph_div_1 : integer := 1;
enable_extclk_output_0: string := "false";
pll_extclk_cnt_src_0: string := "m0_cnt";
pll_extclk_enable_0: string := "true";
pll_extclk_invert_0: string := "false";
enable_extclk_output_1: string := "false";
pll_extclk_cnt_src_1: string := "vss";
pll_extclk_enable_1: string := "true";
pll_extclk_invert_1: string := "false";
enable_extclk_output_2: string := "false";
pll_extclk_cnt_src_2: string := "vss";
pll_extclk_enable_2: string := "true";
pll_extclk_invert_2: string := "false";
enable_extclk_output_3: string := "false";
pll_extclk_cnt_src_3: string := "vss";
pll_extclk_enable_3: string := "true";
pll_extclk_invert_3: string := "false";
enable_dll_output_0: string := "false";
pll_dll_src_value_0: string := "vss";
enable_dll_output_1: string := "false";
pll_dll_src_value_1: string := "vss";
enable_lvds_output_0: string := "false";
pll_loaden_coarse_dly_0: string := "0 ps";
pll_loaden_enable_disable_0: string := "true";
pll_loaden_fine_dly_0: string := "0 ps";
pll_lvdsclk_coarse_dly_0: string := "0 ps";
pll_lvdsclk_enable_disable_0: string := "true";
pll_lvdsclk_fine_dly_0: string := "0 ps";
enable_lvds_output_1: string := "false";
pll_loaden_coarse_dly_1: string := "0 ps";
pll_loaden_enable_disable_1: string := "true";
pll_loaden_fine_dly_1: string := "0 ps";
pll_lvdsclk_coarse_dly_1: string := "0 ps";
pll_lvdsclk_enable_disable_1: string := "true";
pll_lvdsclk_fine_dly_1: string := "0 ps";
enable_lvds_output_2: string := "false";
pll_loaden_coarse_dly_2: string := "0 ps";
pll_loaden_enable_disable_2: string := "true";
pll_loaden_fine_dly_2: string := "0 ps";
pll_lvdsclk_coarse_dly_2: string := "0 ps";
pll_lvdsclk_enable_disable_2: string := "true";
pll_lvdsclk_fine_dly_2: string := "0 ps";
enable_lvds_output_3: string := "false";
pll_loaden_coarse_dly_3: string := "0 ps";
pll_loaden_enable_disable_3: string := "true";
pll_loaden_fine_dly_3: string := "0 ps";
pll_lvdsclk_coarse_dly_3: string := "0 ps";
pll_lvdsclk_enable_disable_3: string := "true";
pll_lvdsclk_fine_dly_3: string := "0 ps"
);
port(
phout_0 : out vl_logic_vector(7 downto 0);
phout_1 : out vl_logic_vector(7 downto 0);
adjpllin : in vl_logic_vector;
cclk : in vl_logic_vector;
coreclkin : in vl_logic_vector;
extswitch : in vl_logic_vector;
iqtxrxclkin : in vl_logic_vector;
plliqclkin : in vl_logic_vector;
rxiqclkin : in vl_logic_vector;
clkin : in vl_logic_vector(3 downto 0);
refiqclk_0 : in vl_logic_vector(1 downto 0);
refiqclk_1 : in vl_logic_vector(1 downto 0);
clk0bad : out vl_logic_vector;
clk1bad : out vl_logic_vector;
pllclksel : out vl_logic_vector;
atpgmode : in vl_logic_vector;
clk : in vl_logic_vector;
fpllcsrtest : in vl_logic_vector;
iocsrclkin : in vl_logic_vector;
iocsrdatain : in vl_logic_vector;
iocsren : in vl_logic_vector;
iocsrrstn : in vl_logic_vector;
mdiodis : in vl_logic_vector;
phaseen : in vl_logic_vector;
read : in vl_logic_vector;
rstn : in vl_logic_vector;
scanen : in vl_logic_vector;
sershiftload : in vl_logic_vector;
shiftdonei : in vl_logic_vector;
updn : in vl_logic_vector;
write : in vl_logic_vector;
addr_0 : in vl_logic_vector(5 downto 0);
addr_1 : in vl_logic_vector(5 downto 0);
byteen_0 : in vl_logic_vector(1 downto 0);
byteen_1 : in vl_logic_vector(1 downto 0);
cntsel_0 : in vl_logic_vector(4 downto 0);
cntsel_1 : in vl_logic_vector(4 downto 0);
din_0 : in vl_logic_vector(15 downto 0);
din_1 : in vl_logic_vector(15 downto 0);
blockselect : out vl_logic_vector;
iocsrdataout : out vl_logic_vector;
iocsrenbuf : out vl_logic_vector;
iocsrrstnbuf : out vl_logic_vector;
phasedone : out vl_logic_vector;
dout_0 : out vl_logic_vector(15 downto 0);
dout_1 : out vl_logic_vector(15 downto 0);
dprioout_0 : out vl_logic_vector(815 downto 0);
dprioout_1 : out vl_logic_vector(815 downto 0);
fbclkfpll : in vl_logic_vector;
lvdfbin : in vl_logic_vector;
nresync : in vl_logic_vector;
pfden : in vl_logic_vector;
shiften_fpll : in vl_logic_vector;
zdb : in vl_logic_vector;
fblvdsout : out vl_logic_vector;
lock : out vl_logic_vector;
mcntout : out vl_logic_vector;
plniotribuf : out vl_logic_vector;
clken : in vl_logic_vector;
extclk : out vl_logic_vector;
dll_clkin : in vl_logic_vector;
clkout : out vl_logic_vector;
loaden : out vl_logic_vector;
lvdsclk : out vl_logic_vector;
divclk : out vl_logic_vector;
cascade_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_fplls : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_dlls : constant is 1;
attribute mti_svvh_generic_type of number_of_lvds : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_0 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_0 : constant is 1;
attribute mti_svvh_generic_type of forcelock_0 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_0 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_0 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_0 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_0 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_0 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_0 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_0 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_1 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_1 : constant is 1;
attribute mti_svvh_generic_type of forcelock_1 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_1 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_1 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_1 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_1 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_1 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_1 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_0 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_1 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_2 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_2 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_3 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_3 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_4 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_4 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_5 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_5 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_6 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_6 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_7 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_7 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_8 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_8 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_9 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_9 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_9 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_10 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_10 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_10 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_11 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_11 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_11 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_12 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_12 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_12 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_13 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_13 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_13 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_14 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_14 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_14 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_15 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_15 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_15 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_16 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_16 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_16 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_17 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_17 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_17 : constant is 3;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_0 : constant is 1;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_2 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_3 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_0 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_3 : constant is 1;
end altera_arriavgz_pll;
| mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_delay.vhd | 2 | 1850 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(1-1 downto 0);
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNUECIBFDH;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
| mit |
MostAwesomeDude/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/db/alt_dspbuilder_testbench_salt_GNDBMPYDND.vhd | 20 | 1717 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNDBMPYDND is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 1) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= '0';
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic(s(1));
end if ;
end if ;
end process ;
end architecture;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/db/alt_dspbuilder_SBitLogical.vhd | 20 | 3567 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBitLogical is
generic (
lpm_width : positive := 8 ;
lop : LogicalOperator := AltAND
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end alt_dspbuilder_SBitLogical;
architecture SBitLogical_SYNTH of alt_dspbuilder_SBitLogical is
signal worand : std_logic_vector(lpm_width-1 downto 0);
signal ndataa : std_logic_vector(lpm_width-1 downto 0);
signal result_int : std_logic;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => result_int, r => result);
------------------AND--------------------------------
go1p:if lop = AltAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '1' when (worand=dataa) else '0';
end generate;
------------------OR--------------------------------
go2p:if lop = AltOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '0' when (ndataa=worand) else '1';
end generate;
------------------XOR--------------------------------
go3p:if lop = AltXOR generate
gif:if (lpm_width>2) generate
process(dataa)
variable interes : std_logic ;
begin
interes := dataa(0) xor dataa(1);
for i in 2 to lpm_width-1 loop
interes := dataa(i) xor interes;
end loop;
result_int <= interes;
end process;
end generate;
gif2:if (lpm_width<3) generate
result_int <= dataa(0) xor dataa(1);
end generate;
end generate;
------------------NOR--------------------------------
go4p:if lop = AltNOR generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
ndataa(i) <= not (dataa(i));
end generate gi;
result_int <= '1' when (ndataa=worand) else '0';
end generate;
------------------NAND--------------------------------
go5p:if lop = AltNAND generate
gi:for i in 0 to lpm_width-1 generate
worand(i) <= '1';
end generate gi;
result_int <= '0' when (worand=dataa) else '1';
end generate;
------------------NOT (Single Bit only)---------------
go6p:if lop = AltNOT generate
result_int <= not (dataa(0));
end generate;
end SBitLogical_SYNTH;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/hdl/Gray_Processing.vhd | 2 | 2259 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Processing is
port (
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Gray_Processing;
architecture rtl of Gray_Processing is
component Gray_Processing_GN is
port (
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Gray_Processing_GN;
begin
Gray_Processing_GN_0: if true generate
inst_Gray_Processing_GN_0: Gray_Processing_GN
port map(Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
| mit |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/hdl/alt_dspbuilder_bus_concat_GN55ETJ4VI.vhd | 12 | 654 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic ( widthB : natural := 16;
widthA : natural := 8);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN55ETJ4VI is
Begin
output <= a & b;
end architecture; | mit |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_sAltrBitPropagate.vhd | 20 | 1572 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
| mit |
Pajeh/mips1 | src/vhdl/instruction_decode_tb.vhd | 1 | 11565 | -- Testbench for the instruction decode stage
-- 2015-08-04 Lukas Jäger created
-- 2015-08-04 Lukas Jäger added test cases for forwarding
-- 2015-08-05 Lukas Jaeger adjusted dut to new interface
-- 2015-08-05 Lukas Jaeger added expected data for ip_out
-- 2015-08-06 Lukas, Carlos added test cases for Jump-instructions
-- 2015-08-06 Lukas Fixed some minor bugs
library IEEE;
use IEEE.std_logic_1164.all;
entity instruction_decode_tb is
end instruction_decode_tb;
architecture behavioural of instruction_decode_tb is
-- DUT
component instruction_decode
port(instr,ip_in, writeback, alu_result, mem_result: in std_logic_vector (31 downto 0);
writeback_reg, regdest_ex, regdest_mem : in std_logic_vector (4 downto 0);
regdest_mux, regshift_mux: in std_logic_vector (1 downto 0);
clk, reset, enable_regs: in std_logic;
reg_a, reg_b, imm, ip_out : out std_logic_vector (31 downto 0);
reg_dest, shift_out : out std_logic_vector (4 downto 0)
);
end component;
signal instr : std_logic_vector (31 downto 0) := x"00000000";
signal ip_in : std_logic_vector (31 downto 0) := x"00000000";
signal writeback : std_logic_vector (31 downto 0) := x"00000000";
signal alu_result : std_logic_vector (31 downto 0) := x"00000000";
signal mem_result : std_logic_vector (31 downto 0) := x"00000000";
signal writeback_reg : std_logic_vector (4 downto 0) := "00001";
signal regdest_mem : std_logic_vector (4 downto 0) := "00000";
signal regdest_ex : std_logic_vector (4 downto 0) := "00000";
signal regdest_mux : std_logic_vector (1 downto 0) := "00";
signal regshift_mux : std_logic_vector (1 downto 0) := "00";
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable_regs : std_logic := '0';
-- Tweak clock frequency here
constant clk_time : time := 10 ns;
begin
dut: instruction_decode port map(
instr => instr,
ip_in => ip_in,
writeback => writeback,
writeback_reg => writeback_reg,
alu_result => alu_result,
mem_result => mem_result,
regdest_mux => regdest_mux,
regshift_mux => regshift_mux,
clk => clk,
reset => reset,
enable_regs => enable_regs,
regdest_ex => regdest_ex,
regdest_mem => regdest_mem
);
clk_proc : process
begin
clk <= '0';
wait for clk_time / 2;
clk <= '1';
wait for clk_time / 2;
end process;
data_proc : process
begin
reset <= '0';
wait for clk_time/2;
reset <= '1';
enable_regs <= '1';
-- Writing some test values to the register file:
-- r1 becomes 01234567
writeback_reg <= "00001";
writeback <= x"01234567";
wait for clk_time;
-- r2 becomes 76543210
writeback_reg <= "00010";
writeback <= x"76543210";
mem_result <= x"76543210";
wait for clk_time;
-- r3 becomes -1 (signed)
writeback_reg <= "00011";
writeback <= X"FFFFFFFF";
wait for clk_time;
enable_regs <= '0';
writeback_reg <= "00000";
wait for clk_time;
-- Real testing starts here
--inserting an add-instruction that adds r1 and r2 to r3
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
instr <= x"00221820";
wait for clk_time;
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: fedcba98
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
alu_result <= x"fedcba98";
regdest_ex <= "00010";
instr <= x"00221820";
wait for clk_time;
regdest_ex <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 01101001
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
mem_result <= x"01101001";
regdest_mem <= "00010";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in both stages
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 01101001
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
regdest_ex <= "00010";
regdest_mem <= "00010";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
regdest_ex <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r1 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a: fedcba98
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00006080
regdest_ex <= "00001";
instr <= x"00221820";
wait for clk_time;
regdest_ex <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r1 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a: 01101001
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00006080
regdest_mem <= "00001";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in both stages
--outputs should be (all vals in hex notation):
-- reg_a: 01101001
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00006080
regdest_ex <= "00001";
regdest_mem <= "00001";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
regdest_ex <= "00000";
-- inserting an addi instruction that adds abcd in hex notation to r1 and stores it in r2
-- outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 76543210;
-- reg_dest: 2;
-- imm: 0000abcd
-- shift: 0
-- ip_out: fffeaf34
instr <= x"2422abcd";
regdest_mux <= "01";
wait for clk_time;
regdest_mux <= "00";
-- Jump Register - Jump to the address contained in register $s
-- encoding 0000 00ss sss0 0000 0000 0000 0000 1000
-- Test: jump using register 1 value. Encoding 0020_0008
-- reg_a: 01234567
-- reg_b: 00000000;
-- reg_dest: 2;
-- imm: 0000abcd
-- shift: 0
-- ip_out: 01234567
instr <= x"00200008";
wait for clk_time;
-- Jump
-- ip_out : 02af37bc
ip_in <= x"01010101";
instr <= x"08abcdef";
wait for clk_time;
-- JAL
-- ip_out : 02af37bc
instr <= x"0cabcdef";
wait for clk_time;
-- JAL with negative immediate
-- ip_out: 0ffffffc
instr <= x"0fffffff";
wait for clk_time;
-- Forwarding test for regdest_ex and alu_result using a jump
-- jump to register value instruction that r1 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: fedcba98
alu_result <= x"fedcba98";
regdest_ex <= "00001";
instr <= x"00200008";
wait for clk_time;
regdest_ex <= "00000";
wait for clk_time;
-- Forwarding test for regdest_ex and alu_result using a jump
-- jump to register value instruction that r2 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: 1edf2a98
alu_result <= x"1edf2a98";
regdest_ex <= "00010";
instr <= x"00400008";
wait for clk_time;
regdest_ex <= "00000";
wait for clk_time;
-- Forwarding test for regdest_mem and writeback using a jump
-- jump to register value instruction that r1 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: fedcba98
mem_result <= x"fedcba98";
regdest_mem <= "00001";
instr <= x"00200008";
wait for clk_time;
regdest_mem <= "00000";
wait for clk_time;
-- Forwarding test for regdest_mem and writeback using a jump
-- jump to register value instruction that r2 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: 1edf2a98
mem_result <= x"1edf2a98";
regdest_mem <= "00010";
instr <= x"00400008";
wait for clk_time;
regdest_mem <= "00000";
wait for clk_time;
-- Test for unsigned immediate expansion
-- reg_a: 01234567
-- reg_b: 76543210
-- imm: 0000ffff;
instr <= x"2422ffff";
wait for clk_time;
-- Test for signed immediate expansion
-- reg_a: 01234567
-- reg_b: 76543210
-- imm: ffffffff;
instr <= x"2022ffff";
wait for clk_time;
-- Test for a LW-Operation
-- imm: FFFF8010
instr <= x"8f828010";
wait for clk_time;
ip_in <=x"01010100";
-- Test for BEQ-Op (condition is true)
-- ip_out : 0103C0F8
instr <= x"1000AFFE";
wait for clk_time;
-- Test for BEQ-Op (condition is false)
-- ip_out : 01010100
instr <= x"1020AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is greater)
-- ip_out : 0103C0F8
instr <= x"0421AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is equal)
-- ip_out : 0103C0F8
instr <= x"0401AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is smaller)
-- ip_out : 01010100
instr <= x"0461AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is greater)
-- ip_out : 0103C0F8
-- R31: 01010100
instr <= x"0431AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is equal)
-- ip_out : 0103C0F8
instr <= x"0411AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is smaller)
-- ip_out : 01010100
instr <= x"0471AFFE";
wait for clk_time;
-- Test for BGTZ (true)
-- ip_out: 0103C0F8
instr <=x"1C20AFFE";
wait for clk_time;
-- Test for BGTZ (false)
-- ip_out: 01010100
instr <= x"1C00AFFE";
wait for clk_time;
-- Test for BNEZ (true)
-- ip_out: 34
ip_in <= x"00000050";
instr <= x"1440fff8";
wait for clk_time;
-- Test for BNEZ (true)
-- ip_out: 58
ip_in <= x"00000050";
instr <= x"1400fff8";
wait for clk_time;
end process;
end;
| mit |
cadesalaberry/digital-system-design | lab5/g23_Seconds_to_Days.vhd | 3 | 1470 | -- describe what this circuit does
--
-- entity name: g23_Seconds_to_Days
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 21/01/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity g23_Seconds_to_Days is
port (
seconds : in unsigned(16 downto 0);
day_fraction : out unsigned(39 downto 0)
);
end g23_Seconds_to_Days;
architecture cascading of g23_Seconds_to_Days is
signal adder1: unsigned(18 downto 0);
signal adder2: unsigned(22 downto 0);
signal adder3: unsigned(25 downto 0);
signal adder4: unsigned(26 downto 0);
signal adder5: unsigned(27 downto 0);
signal adder6: unsigned(29 downto 0);
signal adder7: unsigned(33 downto 0);
signal adder8: unsigned(38 downto 0);
signal adder9: unsigned(39 downto 0);
begin
adder1 <= seconds + (seconds & "00");
adder2 <= adder1 + (seconds & "000000");
adder3 <= adder2 + (seconds & "000000000");
adder4 <= adder3 + (seconds & "0000000000");
adder5 <= adder4 + (seconds & "00000000000");
adder6 <= adder5 + (seconds & "0000000000000");
adder7 <= adder6 + (seconds & "00000000000000000");
adder8 <= adder7 + (seconds & "0000000000000000000000");
adder9 <= adder8 + (seconds & "00000000000000000000000");
day_fraction <= adder9;
end cascading;
| mit |
Pajeh/mips1 | src/vhdl/cpu_datapath.vhd | 1 | 8323 | -- revision history:
-- 06.07.2015 Alex Schoenberger created
-- 05.08.2015 Patrick Appenheimer first try
-- 06.08.2015 Patrick Appenheimer ports and entities added
-- 10.08.2015 Patrick Appenheimer minor changes
-- 12.08.2015 Patrick Appenheimer changed rising_edge to falling_edge
-- 14.08.2015 Patrick Appenheimer changed pc_mux control
library IEEE;
use IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
library WORK;
use WORK.all;
-- -- stage_control: --
-- to activate registers, set signal stage_control as follows:
-- stage0->stage1: xxxx1
-- stage1->stage2: xxx1x
-- stage2->stage3: xx1xx
-- stage3->stage4: x1xxx
-- stage4->stage5: 1xxxx
entity cpu_datapath is
port(
clk : in std_logic;
rst : in std_logic;
instr_addr : out std_logic_vector(31 downto 0);
data_addr : out std_logic_vector(31 downto 0);
instr_in : in std_logic_vector(31 downto 0);
data_to_cpu : in std_logic_vector(31 downto 0);
data_from_cpu : out std_logic_vector(31 downto 0);
alu_op : in std_logic_vector(5 downto 0);
exc_mux1 : in std_logic_vector(1 downto 0);
exc_mux2 : in std_logic_vector(1 downto 0);
exc_alu_zero : out std_logic_vector(0 downto 0);
memstg_mux : in std_logic;
id_regdest_mux : in std_logic_vector (1 downto 0);
id_regshift_mux : in std_logic_vector (1 downto 0);
id_enable_regs : in std_logic;
in_mux_pc : in std_logic;
stage_control : in std_logic_vector (4 downto 0)
);
end entity cpu_datapath;
architecture structure_cpu_datapath of cpu_datapath is
-- -------- PC ==> Instr. Fetch -----------------
signal mux_out_0 : std_logic_vector(31 downto 0);
-- -------- Instr. Fetch ==> Instr. Decode -----------------
signal instr_1 : std_logic_vector(31 downto 0);
signal ip_1 : std_logic_vector(31 downto 0);
-- -------- Instr. Decode ==> Execution -----------------
signal shift_2 : std_logic_vector(4 downto 0);
signal reg_a_2 : std_logic_vector(31 downto 0);
signal reg_b_2 : std_logic_vector(31 downto 0);
signal regdest_2 : std_logic_vector(4 downto 0);
signal imm_2 : std_logic_vector(31 downto 0);
signal ip_2 : std_logic_vector(31 downto 0);
-- -------- Execution ==> Memory Stage -----------------
signal alu_result_3 : std_logic_vector(31 downto 0);
signal data_3 : std_logic_vector(31 downto 0);
signal regdest_3 : std_logic_vector(4 downto 0);
-- -------- Memory Stage ==> Write Back -----------------
signal writeback_4 : std_logic_vector(31 downto 0);
signal regdest_4 : std_logic_vector(4 downto 0);
-- IP:
signal mux_pc_out : std_logic_vector(31 downto 0);
-- Instr. Fetch:
signal if_ip : std_logic_vector(31 downto 0);
signal if_instr : std_logic_vector(31 downto 0);
-- Instr. Decode:
signal id_a : std_logic_vector(31 downto 0);
signal id_b : std_logic_vector(31 downto 0);
signal id_imm : std_logic_vector(31 downto 0);
signal id_ip : std_logic_vector(31 downto 0);
signal id_regdest : std_logic_vector(4 downto 0);
signal id_shift : std_logic_vector(4 downto 0);
-- Execution:
signal alu_result : std_logic_vector(31 downto 0);
signal data_out : std_logic_vector(31 downto 0);
signal exc_destreg_out : std_logic_vector(4 downto 0);
-- Memory Stage:
signal memstg_writeback_out : std_logic_vector(31 downto 0);
signal memstg_destreg_out : std_logic_vector(4 downto 0);
-- Write Back:
signal wb_writeback_out : std_logic_vector(31 downto 0);
signal wb_destreg_out : std_logic_vector(4 downto 0);
signal last_instruction : std_logic_vector( 31 downto 0);
begin
-- INSTRUCTION FETCH:
instruction_fetch: entity work.instruction_fetch(behavioral) port map(clk, rst, mux_out_0, instr_in, if_ip,
instr_addr, if_instr);
-- INSTRUCTION DECODE:
instruction_decode: entity work.instruction_decode(behavioral) port map(instr_1, ip_1, wb_writeback_out, alu_result,
memstg_writeback_out, regdest_4, exc_destreg_out,
memstg_destreg_out, id_regdest_mux,
id_regshift_mux, clk, rst, id_enable_regs,
id_a, id_b, id_imm, id_ip, id_regdest, id_shift);
-- EXECUTION:
execution: entity work.execution(behave) port map(clk, rst, alu_result, data_out, exc_destreg_out,
exc_alu_zero, reg_a_2, reg_b_2, regdest_2, imm_2,
ip_2, shift_2, exc_mux1, exc_mux2,alu_op);
-- MEMORY STAGE:
memory_stage: entity work.MemoryStage(behavioral) port map(clk, rst, alu_result_3, data_3, data_addr,
data_from_cpu, data_to_cpu, memstg_mux,
memstg_writeback_out, regdest_3, memstg_destreg_out);
-- WRITE BACK:
write_back: entity work.write_back(behavioral) port map(clk, rst, writeback_4, regdest_4,
wb_writeback_out, wb_destreg_out);
stage0: process(clk, rst)
begin
if (rst = '1') then
mux_out_0 <= (others => '0');
elsif ((rising_edge(clk)) and (stage_control (0 downto 0) = "1")) then
mux_out_0 <= mux_pc_out;
end if;
end process;
stage1: process(clk, rst)
begin
if (rst = '1') then
instr_1 <= (others => '0');
ip_1 <= (others => '0');
elsif ((rising_edge(clk)) and (stage_control (1 downto 1) = "1")) then
instr_1 <= if_instr;
ip_1 <= if_ip;
end if;
end process;
stage2: process(clk, rst)
begin
if (rst = '1') then
shift_2 <= (others => '0');
reg_a_2 <= (others => '0');
reg_b_2 <= (others => '0');
regdest_2 <= (others => '0');
imm_2 <= (others => '0');
ip_2 <= (others => '0');
elsif ((rising_edge(clk)) and (stage_control (2 downto 2) = "1")) then
shift_2 <= id_shift;
reg_a_2 <= id_a;
reg_b_2 <= id_b;
regdest_2 <= id_regdest;
imm_2 <= id_imm;
ip_2 <= ip_1;
end if;
end process;
stage3: process(clk, rst)
begin
if (rst = '1') then
alu_result_3 <= (others => '0');
data_3 <= (others => '0');
regdest_3 <= (others => '0');
elsif ((rising_edge(clk)) and (stage_control (3 downto 3) = "1")) then
alu_result_3 <= alu_result;
data_3 <= data_out;
regdest_3 <= exc_destreg_out;
end if;
end process;
stage4: process(clk, rst)
begin
if (rst = '1') then
writeback_4 <= (others => '0');
regdest_4 <= (others => '0');
elsif ((rising_edge(clk)) and (stage_control (4 downto 4) = "1")) then
writeback_4 <= memstg_writeback_out;
regdest_4 <= memstg_destreg_out;
end if;
end process;
mux: process(in_mux_pc, id_ip, if_ip)
begin
if (in_mux_pc = '1')then
mux_pc_out <= id_ip;
else
mux_pc_out <= if_ip;
end if;
end process;
--mux: process(instr_in, id_ip, if_ip, clk)
-- begin
-- if (clk'event and clk = '1') then
-- if ((instr_in(31 downto 26) = "000100") or (instr_in(31 downto 26) = "000010") or (instr_in(31 downto 26) = "000101") or (instr_in(31 downto 26) = "011101"))then
-- mux_pc_out <= id_ip;
-- else
-- mux_pc_out <= if_ip;
-- end if;
-- end if;
-- end process;
--last_instruction_proc: process(clk) is
--begin
-- if (clk'event and clk = '1') then
-- last_instruction <= instr_in;
-- end if;
--end process;
end architecture structure_cpu_datapath;
| mit |
jonathanrainer/serial_processors_project | simulations/greendroid_core_simulations/sources/divu/complete_divu_core.vhd | 1 | 2710 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DIVUCoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
in2 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
out2 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN std_logic_vector(31 DOWNTO 0);
frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
clck : IN std_logic;
mem_wait : IN std_logic;
mem_push : IN std_logic_vector(31 DOWNTO 0)
);
end DIVUCoreAndMemory;
architecture Structure of DIVUCoreAndMemory is
component GreenDroidDIVUCore
PORT (
i00 : IN std_logic_vector(31 DOWNTO 0);
i01 : IN std_logic_vector(31 DOWNTO 0);
i02 : IN std_logic_vector(31 DOWNTO 0);
r00 : OUT std_logic_vector(31 DOWNTO 0);
r01 : OUT std_logic_vector(31 DOWNTO 0);
r02 : OUT std_logic_vector(31 DOWNTO 0);
FP : IN std_logic_vector(31 DOWNTO 0);
FPout : OUT std_logic_vector(31 DOWNTO 0);
M_ADDR : OUT std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : INOUT std_logic;
M_WR : INOUT std_logic;
M_RDY : IN std_logic;
reset : IN std_logic;
CLK : IN std_logic
);
end component;
component mem
PORT (
M_ADDR : IN std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : IN std_logic;
M_WR : IN std_logic;
M_RDY : OUT std_logic;
MWAIT : IN std_logic;
MDAT : IN std_logic_vector(31 DOWNTO 0)
);
end component;
signal sig_M_ADDR, sig_M_DATA : std_logic_vector(31 DOWNTO 0);
signal sig_M_RD, sig_M_WR, sig_M_RDY : std_logic;
begin
Core: GreenDroidDIVUCore
port map (
i00 => in0, i01 => in1, i02 => in2,
r00 => out0, r01 => out1, r02 => out2,
FP => frame_pointer, FPout => frame_pointer_out,
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
reset => rst,
CLK => clck
);
mymem: mem
port map(
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
MWAIT => mem_wait,
MDAT => mem_push
);
end Structure;
| mit |
plac-lab/TMIIaTest | Firmware/src/gig_eth/KCU105/gig_eth_mac_resets.vhd | 4 | 9190 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design_resets.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This block generates fully synchronous resets for each clock domain
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tri_mode_ethernet_mac_0_example_design_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
reset_error : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic;
chk_resetn : out std_logic := '0'
);
end tri_mode_ethernet_mac_0_example_design_resets;
architecture RTL of tri_mode_ethernet_mac_0_example_design_resets is
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
clk : in std_logic; -- clock to be sync'ed to
enable : in std_logic;
reset_in : in std_logic; -- Active high asynchronous reset
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- define internal signals
signal s_axi_pre_resetn : std_logic := '0';
signal s_axi_reset_int : std_logic;
signal combined_reset : std_logic;
signal gtx_pre_resetn : std_logic := '0';
signal gtx_clk_reset_int : std_logic;
signal clear_checker : std_logic;
signal chk_pre_resetn : std_logic := '0';
signal chk_reset_int : std_logic;
signal dcm_locked_sync : std_logic;
signal glbl_rst_int : std_logic;
signal phy_resetn_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------
-- Synchronise the async dcm_locked into the gtx_clk clock domain
------------------------------------------------------------------------------
dcm_sync : tri_mode_ethernet_mac_0_sync_block
port map (
clk => gtx_clk,
data_in => dcm_locked,
data_out => dcm_locked_sync
);
------------------------------------------------------------------------------
-- Generate resets required for the fifo side signals etc
------------------------------------------------------------------------------
-- in each case the async reset is first captured and then synchronised
-----------------
-- global reset
glbl_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => glbl_rst,
reset_out => glbl_rst_int
);
glbl_rst_intn <= not glbl_rst_int;
-----------------
-- AXI-Lite reset
axi_lite_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => s_axi_aclk,
enable => phy_resetn_int,
reset_in => glbl_rst,
reset_out => s_axi_reset_int
);
-- Create fully synchronous reset in the s_axi clock domain.
axi_lite_reset_p : process(s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset_int = '1' then
s_axi_pre_resetn <= '0';
s_axi_resetn <= '0';
else
s_axi_pre_resetn <= '1';
s_axi_resetn <= s_axi_pre_resetn;
end if;
end if;
end process axi_lite_reset_p;
-----------------
-- axi_lite clock reset
combined_reset <= glbl_rst or rx_reset or tx_reset;
gtx_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => combined_reset,
reset_out => gtx_clk_reset_int
);
-- Create fully synchronous reset in the gtx_clk domain.
gtx_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if gtx_clk_reset_int = '1' then
gtx_pre_resetn <= '0';
gtx_resetn <= '0';
else
gtx_pre_resetn <= '1';
gtx_resetn <= gtx_pre_resetn;
end if;
end if;
end process gtx_reset_p;
-----------------
-- data check reset
clear_checker <= glbl_rst or reset_error;
-- ymei
-- chk_reset_int <= clear_checker;
chk_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => gtx_clk,
enable => dcm_locked_sync,
reset_in => clear_checker,
reset_out => chk_reset_int
);
-- Create fully synchronous reset in the gtx_clk domain.
chk_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if chk_reset_int = '1' then
chk_pre_resetn <= '0';
chk_resetn <= '0';
else
chk_pre_resetn <= '1';
chk_resetn <= chk_pre_resetn;
end if;
end if;
end process chk_reset_p;
-----------------
-- PHY reset
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
-- this is derived using the 125MHz available and a 6 bit counter
phy_reset_p : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
if glbl_rst_int = '1' then
phy_resetn_int <= '0';
phy_reset_count <= (others => '0');
else
if phy_reset_count /= "111111" then
phy_reset_count <= phy_reset_count + "000001";
else
phy_resetn_int <= '1';
end if;
end if;
end if;
end process phy_reset_p;
phy_resetn <= phy_resetn_int;
end RTL;
| mit |
plac-lab/TMIIaTest | Firmware/src/ten_gig_eth_rx_parser.vhd | 2 | 10043 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_rx_parser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Parses incoming packets. Deals WITH ARP AND UDP and generates appropriate
-- action commands.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY ten_gig_eth_rx_parser IS
PORT (
RESET : IN std_logic;
RX_AXIS_FIFO_ARESETN : OUT std_logic;
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : IN std_logic;
RX_AXIS_FIFO_TLAST : IN std_logic;
RX_AXIS_FIFO_TREADY : OUT std_logic;
-- Constants
SRC_MAC : IN std_logic_vector(47 DOWNTO 0);
SRC_IP : IN std_logic_vector(31 DOWNTO 0);
SRC_PORT : IN std_logic_vector(15 DOWNTO 0);
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q : OUT std_logic_vector(127 DOWNTO 0);
CMD_FIFO_EMPTY : OUT std_logic;
CMD_FIFO_RDREQ : IN std_logic;
CMD_FIFO_RDCLK : IN std_logic
);
END ten_gig_eth_rx_parser;
ARCHITECTURE Behavioral OF ten_gig_eth_rx_parser IS
COMPONENT fifo128x
PORT (
RST : IN std_logic;
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
DIN : IN std_logic_vector(127 DOWNTO 0);
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DOUT : OUT std_logic_vector(127 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic
);
END COMPONENT;
--
CONSTANT pktType_ARP : std_logic_vector(15 DOWNTO 0) := x"0806";
CONSTANT pktType_IP : std_logic_vector(15 DOWNTO 0) := x"0800";
CONSTANT opcode_REQ : std_logic_vector(15 DOWNTO 0) := x"0001";
CONSTANT protocol_UDP : std_logic_vector(7 DOWNTO 0) := x"11";
--
SIGNAL clk_i : std_logic;
SIGNAL cmd_fifo_din : std_logic_vector(127 DOWNTO 0);
SIGNAL cmd_fifo_wren : std_logic;
SIGNAL cmd_fifo_full : std_logic;
--
SIGNAL tvalid_prev : std_logic;
SIGNAL tstart : std_logic;
SIGNAL tlast_i : std_logic;
--
SIGNAL dst_mac_reg : std_logic_vector(47 DOWNTO 0);
SIGNAL dst_ip_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL dst_port_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL src_mac_reg : std_logic_vector(47 DOWNTO 0);
SIGNAL src_ip_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL src_port_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL pktType_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL opcode_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL protocol_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL udp_cmd_reg : std_logic_vector(31 DOWNTO 0);
--
TYPE parser_state_type IS (S0, S1, S2, S3, S4, S5, S6);
SIGNAL parser_state : parser_state_type;
SIGNAL cmd_state : parser_state_type;
BEGIN
clk_i <= RX_AXIS_FIFO_ACLK;
RX_AXIS_FIFO_ARESETN <= NOT RESET;
RX_AXIS_FIFO_TREADY <= NOT cmd_fifo_full;
cmd_fifo : fifo128x
PORT MAP (
RST => RESET,
WR_CLK => clk_i,
RD_CLK => CMD_FIFO_RDCLK,
DIN => cmd_fifo_din,
WR_EN => cmd_fifo_wren,
RD_EN => CMD_FIFO_RDREQ,
DOUT => CMD_FIFO_Q,
FULL => cmd_fifo_full,
EMPTY => CMD_FIFO_EMPTY
);
-- catch the rising edge of tvalid
PROCESS (clk_i, RESET) IS
BEGIN
IF falling_edge(clk_i) THEN
tvalid_prev <= RX_AXIS_FIFO_TVALID;
tstart <= RX_AXIS_FIFO_TVALID AND (NOT tvalid_prev);
END IF;
END PROCESS;
parser_sm : PROCESS (clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
dst_mac_reg <= (OTHERS => '0');
dst_ip_reg <= (OTHERS => '0');
dst_port_reg <= (OTHERS => '0');
src_mac_reg <= (OTHERS => '0');
src_ip_reg <= (OTHERS => '0');
src_port_reg <= (OTHERS => '0');
pktType_reg <= (OTHERS => '0');
opcode_reg <= (OTHERS => '0');
protocol_reg <= (OTHERS => '0');
udp_cmd_reg <= (OTHERS => '0');
parser_state <= S0;
ELSIF rising_edge(clk_i) THEN
tlast_i <= RX_AXIS_FIFO_TLAST;
parser_state <= S0;
CASE parser_state IS
WHEN S0 =>
IF tstart = '1' THEN
dst_mac_reg <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8) &
RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24) &
RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
src_mac_reg(47 DOWNTO 32) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
parser_state <= S1;
END IF;
WHEN S1 =>
parser_state <= S1;
IF RX_AXIS_FIFO_TVALID = '1' THEN
src_mac_reg(31 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8) &
RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24);
pktType_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
parser_state <= S2;
END IF;
WHEN S2 =>
parser_state <= S2;
IF RX_AXIS_FIFO_TVALID = '1' THEN
opcode_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
protocol_reg <= RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
parser_state <= S3;
END IF;
WHEN S3 =>
parser_state <= S3;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
src_ip_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40) &
RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
ELSE
src_ip_reg <= RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24) &
RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
dst_ip_reg(31 DOWNTO 16) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
END IF;
parser_state <= S4;
END IF;
WHEN S4 =>
parser_state <= S4;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
dst_ip_reg(31 DOWNTO 16) <= RX_AXIS_FIFO_TDATA(55 DOWNTO 48) &
RX_AXIS_FIFO_TDATA(63 DOWNTO 56);
ELSE
dst_ip_reg(15 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8);
src_port_reg <= RX_AXIS_FIFO_TDATA(23 DOWNTO 16) &
RX_AXIS_FIFO_TDATA(31 DOWNTO 24);
dst_port_reg <= RX_AXIS_FIFO_TDATA(39 DOWNTO 32) &
RX_AXIS_FIFO_TDATA(47 DOWNTO 40);
END IF;
parser_state <= S5;
END IF;
WHEN S5 =>
parser_state <= S5;
IF RX_AXIS_FIFO_TVALID = '1' THEN
IF pktType_reg = pktType_ARP THEN
dst_ip_reg(15 DOWNTO 0) <= RX_AXIS_FIFO_TDATA(7 DOWNTO 0) &
RX_AXIS_FIFO_TDATA(15 DOWNTO 8);
ELSE
udp_cmd_reg <= RX_AXIS_FIFO_TDATA(47 DOWNTO 16);
END IF;
IF RX_AXIS_FIFO_TLAST = '1' THEN
parser_state <= S0;
ELSE
parser_state <= S6;
END IF;
END IF;
WHEN S6 =>
parser_state <= S6;
IF RX_AXIS_FIFO_TLAST = '1' THEN
parser_state <= S0;
END IF;
WHEN OTHERS =>
parser_state <= S0;
END CASE;
END IF;
END PROCESS parser_sm;
PROCESS (clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
cmd_state <= S0;
ELSIF falling_edge(clk_i) THEN
cmd_fifo_wren <= '0';
cmd_state <= S0;
CASE cmd_state IS
WHEN S0 =>
IF tlast_i = '1' THEN
cmd_state <= S1;
END IF;
WHEN S1 =>
IF pktType_reg = pktType_ARP THEN
IF (dst_ip_reg = SRC_IP) AND (opcode_reg = opcode_REQ) THEN -- valid ARP request
cmd_fifo_din <= src_mac_reg & src_ip_reg & src_port_reg & x"00000000";
cmd_fifo_wren <= '1';
END IF;
ELSIF (pktType_reg = pktType_IP) AND (protocol_reg = protocol_UDP)
AND (dst_mac_reg = SRC_MAC) AND (dst_ip_reg = SRC_IP) AND (dst_port_reg = SRC_PORT)
THEN -- valid UDP packet
cmd_fifo_din <= src_mac_reg & src_ip_reg & src_port_reg & udp_cmd_reg;
cmd_fifo_wren <= '1';
END IF;
cmd_state <= S0;
WHEN OTHERS =>
cmd_state <= S0;
END CASE;
END IF;
END PROCESS;
END Behavioral;
| mit |
plac-lab/TMIIaTest | Firmware/src/gig_eth/KC705/fifo/tri_mode_ethernet_mac_0_bram_tdp.vhd | 5 | 4519 | --------------------------------------------------------------------------------
-- Title : RAM memory for RX and TX client FIFOs
-- Version : 1.0
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_bram_tdp.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a parameterized inferred block RAM
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block RAM
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_bram_tdp is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end tri_mode_ethernet_mac_0_bram_tdp;
architecture rtl of tri_mode_ethernet_mac_0_bram_tdp is
-- Shared memory
constant RAM_DEPTH : integer := 2 ** ADDR_WIDTH;
type mem_type is array ( RAM_DEPTH-1 downto 0 ) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type;
begin
-- To write use port A
process(a_clk)
begin
if(a_clk'event and a_clk='1') then
if(a_rst='0' and a_wr='1') then
mem(conv_integer(a_addr)) := a_din;
end if;
end if;
end process;
-- To read use Port B
process(b_clk)
begin
if(b_clk'event and b_clk='1') then
if (b_rst='1') then
b_dout <= (others => '0');
elsif (b_en='1') then
b_dout <= mem(conv_integer(b_addr));
end if;
end if;
end process;
end rtl;
| mit |
Pajeh/mips1 | test/vhdl/tb_cpu_datapath.vhd | 1 | 19973 | -- revision history:
-- 2015-08-06 Lukas Jaeger created
-- 2015-08-07 Lukas Jaeger added instructions of counter-example
-- 2015-08-10 Lukas jaeger Made it more clear
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.all;
entity tb_cpu_datapath is
end entity tb_cpu_datapath;
architecture behavioural of tb_cpu_datapath is
component cpu_datapath
port(
clk : in std_logic;
rst : in std_logic;
instr_addr : out std_logic_vector(31 downto 0);
data_addr : out std_logic_vector(31 downto 0);
instr_in : in std_logic_vector(31 downto 0);
data_to_cpu : in std_logic_vector(31 downto 0);
data_from_cpu : out std_logic_vector(31 downto 0);
alu_op : in std_logic_vector(5 downto 0);
exc_mux1 : in std_logic_vector(1 downto 0);
exc_mux2 : in std_logic_vector(1 downto 0);
exc_alu_zero : out std_logic_vector(0 downto 0);
memstg_mux : in std_logic;
id_regdest_mux : in std_logic_vector (1 downto 0);
id_regshift_mux : in std_logic_vector (1 downto 0);
id_enable_regs : in std_logic;
in_mux_pc : in std_logic;
stage_control : in std_logic_vector (4 downto 0)
);
end component;
signal clk, rst, memstg_mux, id_enable_regs, in_mux_pc : std_logic := '0';
signal instr_in, data_to_cpu : std_logic_vector (31 downto 0) := x"00000000";
signal alu_op : std_logic_vector (5 downto 0) := "000000";
signal exc_mux1, exc_mux2, id_regdest_mux, id_regshift_mux : std_logic_vector(1 downto 0) := "00";
signal exc_alu_zero : std_logic_vector(0 downto 0) := "0";
signal stage_control : std_logic_vector(4 downto 0) := "11111";
-- Tweak clock frequency here
constant clk_time : time := 10 ns;
begin
dut: cpu_datapath port map(
clk => clk,
rst => rst,
instr_in => instr_in,
data_to_cpu => data_to_cpu,
alu_op => alu_op,
exc_mux1 => exc_mux1,
exc_mux2 => exc_mux2,
memstg_mux => memstg_mux,
id_regdest_mux => id_regdest_mux,
id_regshift_mux => id_regshift_mux,
id_enable_regs => id_enable_regs,
in_mux_pc => in_mux_pc,
stage_control => stage_control
);
clk_proc : process
begin
clk <= '0';
wait for clk_time / 2;
clk <= '1';
wait for clk_time / 2;
end process;
data_proc : process
begin
-- Reset
rst <= '1';
wait for clk_time;
rst <= '0';
--usually the first instruction address should be dropping out at
-- instr_addr and it should be 00000000, so we return an instruction
-- and set the ID's muxes for correct decoding
-- To test:
-- instr_address: 00000004
-- if: Instruction 1: LUI $gp, 1
instr_in <= x"3c1c0001";
--id: Nothing
id_regdest_mux <= "00";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Nothing
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000001";
-- mem: Nothing
memstg_mux <= '1';
-- wb: Nothing
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- shift_2 : 10;
-- imm_2: 00000001
-- regdest_2: 1C
-- instr_address: 00000004
-- ip_2 : 00000000
instr_in <= x"279c8070"; -- Instruction 2: ADDIU $gp, $gp, -32656
--id: Instruction 1 (LUI $gp, 1)
id_regdest_mux <= "10";
id_regshift_mux <="01";
in_mux_pc <= '0';
--ex: Nothing
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000001";
-- mem: Nothing
memstg_mux <= '1';
-- wb: Nothing
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- regdest_2: 1C
-- reg_a_2: 00010000;
-- imm_2: 8070
-- instr_address: 00000008
-- ip_2 : 00000004
-- alu_result_3: 000010000
-- regdest_3: 1C
-- ip_3 : 00000000
instr_in <= x"08000004"; -- Instruction 3: J 0x10
--id: Instruction 2 (ADDIU $gp, $gp, -32656)
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Instruction 1 (LUI $gp, 1)
exc_mux1 <= "00";
exc_mux2 <= "01";
alu_op <= "000100";
-- mem: Nothing
memstg_mux <= '1';
-- wb: Nothing
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- id_ip : 000010
-- regdest_3: 1C
-- alu_result_3: 00018070
-- writeback_4: 00010000
-- regdest_4: 1C
-- instr_addr: 00000010
instr_in <= x"3c1d00a2"; -- Instruction 4: LUI $sp,0xa2
--id: Instruction 3 (J 0x10)
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '1';
--ex: Instruction 2 (ADDIU $gp, $gp, -32656)
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: Instruction 1 (LUI $gp, 1)
memstg_mux <= '0';
-- wb: Nothing
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- regdest_2: 1D
-- imm_2: 000000a2;
-- regdest_4: 1C
-- writeback_4: 00018070
-- register_file (28): 00010000
-- instr_addr : 00000014
instr_in <= x"8f828010"; -- Instruction 5: LW $v0,-32752(gp)
--id: Instruction 4
id_regdest_mux <= "10";
id_regshift_mux <="01";
in_mux_pc <= '0';
--ex: Instruction 3
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000001";
-- mem: Instruction 2
memstg_mux <= '0';
-- wb: Instruction 1
id_enable_regs <= '1';
wait for clk_time;
-- To test:
-- reg_a_2: 00018070
-- imm_2: FFFF8010
-- regdest_2: 02
-- alu_result_3: 00a20000
-- regdest_3: 1D
instr_in <= x"00000000"; -- Instruction 6: NOP
--id: Instruction 5
id_regdest_mux <= "10";
id_regshift_mux <="01";
in_mux_pc <= '0';
--ex: Instruction 4
exc_mux1 <= "00";
exc_mux2 <= "01";
alu_op <= "000100";
-- mem: Instruction 3
memstg_mux <= '0';
-- wb: Instruction 2
id_enable_regs <= '1';
wait for clk_time;
-- To test:
-- reg_a_2 : 00000000
-- ieg_b_2 : 00000000
-- reg_shift_2: 00000
-- regdest_2 : 00000
-- imm_2 : 00000000
-- regdest_3 : 02
-- alu_result_3 : 00010080
-- regdest_4 : 1D
-- writeback_4 : 00a20000
instr_in <= x"a0400000"; -- Instruction 7: SB $zero,0($v0)
--id: Instruction 6
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Instruction 5
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: Instruction 4
memstg_mux <= '0';
-- wb: Instruction 3
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- reg_b_2: 00000000
-- imm_2 : 00000000
-- reg_a: 11382187
-- regdest_3 : 00
-- alu_result_3 : 00000000
-- writeback_4 : 11382187
-- regdest_4 : 02;
instr_in <= x"af80800c"; -- Instruction 8: SW $zero,-32756($gp)
--id: Instruction 7
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Instruction 6
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000100";
-- mem: Instruction 5
memstg_mux <= '1';
data_to_cpu <= x"11382187";
-- wb: Instruction 4
id_enable_regs <= '1';
wait for clk_time;
-- To test:
-- reg_a_2: 00018070
-- reg_b_2: 00000000
-- imm_2: FFFF800c
-- data_3: 00000000
-- alu_result: 11382187
-- writeback_4: 00000000
-- regdest_4 : 00
-- data_from_cpu: 00000000
-- data_addr: 11382187
instr_in <=x"8f82800c"; -- Instruction 9: LW $v0,-32756($gp)
--id: Instruction 8
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Instruction 7
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: Instruction 6
memstg_mux <= '0';
-- wb: INstruction 5
id_enable_regs <= '1';
wait for clk_time;
--To test
--reg_a_2: 00018070
-- imm_2: FFFF800C
-- regdest_2: 02
-- alu_result_3: 0001007C
-- data_3: 00000000
-- data_from_cpu: 00000000
-- data_addr: 10007C
--if: Instruction 10 (NOP)
instr_in <= x"00000000";
--id: Instruction 9
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Instruction 8
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: Instruction 7
memstg_mux <= '0';
-- wb: Instruction 6
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- reg_a_2: 00000000
-- reg_b_2: 00000000
-- shift_2: 00000
-- imm_2: 00000000
-- regdest_2: 00
-- alu_result_3: 0001007C
-- data_3: 11382187
-- data_from_cpu: 11382187
-- data_addr: 0001007C
--if: Instruction 11 (SLTI $vo, $v0, 16);
instr_in <= x"28420010";
--id: Instruction 10
id_regdest_mux <= "00";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Instruction 9
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: Instruction 8
memstg_mux <= '0';
-- wb: Instruction 7
id_enable_regs <= '0';
wait for clk_time;
--To test:
-- reg_a_2: 21871138
-- imm_2: 10
-- regdest_2 : 02
-- alu_result: 00000000
-- regdest_3: 00
-- regdest_4: 02
-- writeback_4: 21871138
--if:12 (BEQZ $vo, 0x 58)
instr_in <= x"1040000a";
--id: 11
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 10
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000100";
-- mem: 9
memstg_mux <= '1';
data_to_cpu <=x"21871138";
-- wb: 8
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- next instr_addr: 58
-- alu_result: 00000000
-- regdest_3: 02
-- writeback_4: 000000000
-- regdest_4 : 00
-- if: Instruction 13 (NOP)
instr_in <= x"00000000";
--id: 12
id_regdest_mux <= "00";
id_regshift_mux <="00";
in_mux_pc <= '1';
--ex: 11
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "001000";
-- mem: 10
memstg_mux <= '0';
-- wb: 9
id_enable_regs <= '1';
wait for clk_time;
-- To test:
-- reg_a_2: 00000000
-- reg_b_2: 00000000
-- imm_2: 00000000
-- shift_2: 00
-- writeback_4: 00000000
-- regdest_4: 02
--if: Instruction 23 (LW $v1, -32752($gp))
instr_in <= x"8f838010";
--id: Instruction 13
id_regdest_mux <= "00";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: Instruction 12
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000100";
-- mem: Instruction 11
memstg_mux <= '0';
-- wb: Instruction 10
id_enable_regs <= '0';
wait for clk_time;
-- To test
-- reg_a_2: 00018070
-- imm_2: FFFF8010
-- regdest_2: 03
-- alu_result_3: 00000000
-- regdest_3: 00
--if: 24 (NOP)
instr_in <= x"00000000";
--id: 23
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 13
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000100";
-- mem: 12
memstg_mux <= '0';
-- wb:
id_enable_regs <= '1';
wait for clk_time;
-- To test:
-- reg_a_2: 00000000
-- reg_b_2: 00000000
-- shift_2: 00
-- imm_2: 00000000
-- regdest_2: 00
-- alu_result_3: 00010080
-- regdest_3: 03
-- writeback_4:00000000
-- regdest_4: 00
--if: 25 (LBU v0,0(v1))
instr_in <= x"90620000";
--id: 24
id_regdest_mux <= "00";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 23
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: 13
memstg_mux <= '0';
-- wb: 12
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- reg_a_2: 00C0FFEE
-- imm_2: 00000000;
-- regdest_2: 02
-- alu_result_3:00000000
-- regdest_3: 00
-- writeback_4: 00C0FFEE
-- regdest_4: 03
--if: Instruction 26 (NOP)
instr_in <= x"00000000";
--id: 25
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 24
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "001000";
-- mem: 23
memstg_mux <= '1';
data_to_cpu <= x"00C0FFEE";
-- wb: 13
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- reg_a_2: 00000000
-- reg_b_2: 00000000
-- shift_2: 00
-- imm_2: 00000000
-- regdest_2: 00
-- alu_result_3: 00C0FFEE
-- regdest_3: 02
-- writeback_4: 000000000
-- regdest_4: 00
--if: Instruction 27 (ADDIU $v0, $v0, 1)
instr_in <= x"24420001";
--id: 26
id_regdest_mux <= "00";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 25
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: 24
memstg_mux <= '0';
-- wb: 23
id_enable_regs <= '1';
wait for clk_time;
-- To test:
-- reg_a_2: 00000049
-- imm_2: 00000001
-- regdest_2: 02
-- alu_result_3: 00000000
-- regdest_3: 00
-- writeback_4: 00000049
-- regdest_4: 02
--if: Instruction 28 (ANDI $v0,$v0,0xff)
instr_in <= x"304200ff";
--id: 27
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 26
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "001000";
-- mem: 25
memstg_mux <= '1';
data_to_cpu <=x"00000049";
-- wb: 24
id_enable_regs <= '0';
wait for clk_time;
-- To test:
-- reg_a_2: 0000004A
-- imm_2: 000000ff
-- regdest_2: 02
-- alu_result_3: 0000004A
-- regdest_3: 02
-- writeback_4:00000000
-- regdest_4:00
--if: Instruction 29: (SB $vo, 0($v1))
instr_in <= x"a0620000";
--id: 28
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 27
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100000";
-- mem: 26
memstg_mux <= '0';
-- wb: 25
id_enable_regs <= '1';
wait for clk_time;
-- To test:
-- reg_a_2: 00C0FFEE
-- reg_b_2: 0000004A
-- imm_2: 00000000
--alu_result_3: 0000004A
--regdest_3: 02
--writeback_4: 0000004A
--regdest_4: 02
--if: Instruction 30 (J 0x1C)
instr_in <= x"08000007";
--id: 29
id_regdest_mux <= "10";
id_regshift_mux <="00";
in_mux_pc <= '0';
--ex: 28
exc_mux1 <= "10";
exc_mux2 <= "01";
alu_op <= "100100";
-- mem: 27
memstg_mux <= '0';
-- wb: 26
id_enable_regs <= '0';
wait for clk_time;
end process;
end architecture;
| mit |
jonathanrainer/serial_processors_project | simulations/greendroid_core_simulations/sources/atoi/atoi_testbench.vhd | 1 | 2903 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.03.2016 11:22:26
-- Design Name:
-- Module Name: rem_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity atoi_testbench is
end atoi_testbench;
architecture Behavioural of atoi_testbench is
signal sig_i00, sig_i01, sig_r00, sig_r01,
sig_FP, sig_FPout,sig_MDAT : std_logic_vector(31 DOWNTO 0);
signal sig_reset, sig_CLK, sig_MWAIT : std_logic;
component ATOICoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN std_logic_vector(31 DOWNTO 0);
frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
clck : IN std_logic;
mem_wait : IN std_logic;
mem_push : IN std_logic_vector(31 DOWNTO 0)
);
end component;
begin
uut: ATOICoreAndMemory
port map (
in0 => sig_i00,
in1 => sig_i01,
out0 => sig_r00,
out1 => sig_r01,
frame_pointer => sig_FP,
frame_pointer_out => sig_FPout,
rst => sig_reset,
clck => sig_CLK,
mem_wait => sig_MWAIT,
mem_push => sig_MDAT
);
clock: process
constant clock_period:time := 40ns;
begin
wait for 200ns;
for I in 0 to 100 loop
sig_CLK <= '0';
wait for clock_period/2;
sig_CLK <= '1';
wait for clock_period/2;
end loop;
wait;
end process clock;
test: process begin
sig_MWAIT <= '1';
sig_reset <= '1';
wait for 100ns;
sig_reset <= '0';
wait for 100ns;
sig_i00 <= "00000000000000000000000000100000";
sig_i01 <= "00000000000000000000000000100101";
sig_MDAT <= "00000000000000000000000000011111";
sig_FP <= "00000000000000000000000001100000";
wait;
end process test;
end Behavioural;
| mit |
cadesalaberry/digital-system-design | lab3/g23_mars_timer.vhd | 1 | 939 | -- A Mars timer calibrated for a 50MHz clock.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
ENTITY g23_mars_timer IS
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END g23_mars_timer;
ARCHITECTURE alpha OF g23_mars_timer IS
COMPONENT g23_generic_timer
GENERIC (max : natural := 0);
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END COMPONENT;
BEGIN
earth : g23_generic_timer
-- GENERIC MAP (max => 51374562)
GENERIC MAP (max => 102)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => pulse
);
END alpha;
| mit |
cadesalaberry/digital-system-design | lab5/g23_UTC_to_MTC.vhd | 1 | 6003 | -- Converts an earth time and date into mars time of day.
--
-- entity name: g23_UTC_to_MTC
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 28/03/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library lpm;
USE lpm.lpm_components.all;
entity g23_UTC_to_MTC is
PORT (
clock : in STD_LOGIC; -- ASYNC, Should be connected to the master 50MHz clock.
reset : in STD_LOGIC; -- ASYNC, When high the counts are all set to zero.
enable : in STD_LOGIC; -- SYNC, A pulse with a width of 1 master clock cycle.
-- Earth date input
Year : in STD_LOGIC_VECTOR(11 downto 0);
Month : in STD_LOGIC_VECTOR(3 downto 0);
Day : in STD_LOGIC_VECTOR(4 downto 0);
-- Earth time input
Hour : in STD_LOGIC_VECTOR(4 downto 0);
Minute : in STD_LOGIC_VECTOR(5 downto 0);
Second : in STD_LOGIC_VECTOR(5 downto 0);
-- MTC time on the prime meridian on Mars
Mars_hours : out STD_LOGIC_VECTOR(4 downto 0);
Mars_minutes : out STD_LOGIC_VECTOR(5 downto 0);
Mars_seconds : out STD_LOGIC_VECTOR(5 downto 0);
-- Debug
Year_out : out STD_LOGIC_VECTOR(11 downto 0);
Month_out : out STD_LOGIC_VECTOR(3 downto 0);
Day_out : out STD_LOGIC_VECTOR(4 downto 0);
Num_days : out STD_LOGIC_VECTOR(13 downto 0);
Num_secs : out STD_LOGIC_VECTOR(16 downto 0);
Date_is_reached : out STD_LOGIC
);
end g23_UTC_to_MTC;
architecture cascading of g23_UTC_to_MTC is
COMPONENT g23_YMD_counter
PORT (
clock : in STD_LOGIC; -- ASYNC, Should be connected to the master 50MHz clock.
reset : in STD_LOGIC; -- ASYNC, When high the counts are all set to zero.
count_enable : in STD_LOGIC; -- SYNC, A pulse with a width of 1 master clock cycle.
load_enable : in STD_LOGIC; -- SYNC, if high sets count values to Y_Set, M_Set, and D_Set inputs
y_set : in STD_LOGIC_VECTOR(11 downto 0);
m_set : in STD_LOGIC_VECTOR(3 downto 0);
d_set : in STD_LOGIC_VECTOR(4 downto 0);
years : out STD_LOGIC_VECTOR(11 downto 0);
months : out STD_LOGIC_VECTOR(3 downto 0);
days : out STD_LOGIC_VECTOR(4 downto 0)
);
END COMPONENT;
COMPONENT g23_HMS_counter
PORT (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
load_enable : in STD_LOGIC;
count_enable: in STD_LOGIC;
h_set : in STD_LOGIC_VECTOR(4 downto 0);
m_set : in STD_LOGIC_VECTOR(5 downto 0);
s_set : in STD_LOGIC_VECTOR(5 downto 0);
hours : out STD_LOGIC_VECTOR(4 downto 0);
minutes : out STD_LOGIC_VECTOR(5 downto 0);
seconds : out STD_LOGIC_VECTOR(5 downto 0);
end_of_day : out STD_LOGIC
);
END COMPONENT;
COMPONENT g23_Seconds_to_Days
PORT (
seconds : in unsigned(16 downto 0);
day_fraction : out unsigned(39 downto 0)
);
END COMPONENT;
COMPONENT g23_dayfrac_to_MTC
PORT (
clock : in STD_LOGIC;
enable : in STD_LOGIC;
Ndays : in STD_LOGIC_VECTOR(13 downto 0);
day_frac : in STD_LOGIC_VECTOR(39 downto 0);
-- Time corresponding to the fraction of the day.
Hours : out STD_LOGIC_VECTOR(4 downto 0);
Minutes : out STD_LOGIC_VECTOR(5 downto 0);
Seconds : out STD_LOGIC_VECTOR(5 downto 0)
);
END COMPONENT;
signal eod: STD_LOGIC;
signal date_reached: STD_LOGIC;
signal years_sig : STD_LOGIC_VECTOR(11 downto 0);
signal months_sig : STD_LOGIC_VECTOR(3 downto 0);
signal days_sig : STD_LOGIC_VECTOR(4 downto 0);
signal hours_sig : STD_LOGIC_VECTOR(4 downto 0);
signal minutes_sig : STD_LOGIC_VECTOR(5 downto 0);
signal seconds_sig : STD_LOGIC_VECTOR(5 downto 0);
signal Ndays : STD_LOGIC_VECTOR(13 downto 0);
signal Nsecs : STD_LOGIC_VECTOR(16 downto 0);
signal day_frac : UNSIGNED(39 downto 0);
signal day_end : STD_LOGIC;
signal circuit_start : STD_LOGIC;
BEGIN
Date_is_reached <= date_reached;
Num_days <= Ndays;
Num_secs <= Nsecs;
Year_out <= years_sig;
Month_out <= months_sig;
Day_out <= days_sig;
date_reached <= '1'
WHEN (Year = years_sig)
AND (Month = months_sig)
AND (Day = days_sig)
AND (Hour = hours_sig)
AND (Minute = minutes_sig)
AND (Second = seconds_sig)
ELSE '0';
circuit_start <= '1' WHEN
Nsecs = "00000000000000000" AND Ndays = "00000000000000"
ELSE '0';
YMD_counter : g23_YMD_counter
PORT MAP (
clock => clock,
reset => reset,
count_enable => enable AND eod AND (NOT date_reached),
load_enable => reset OR circuit_start,
Y_set => "011111010000",
M_set => "0001",
D_set => "00110",
years => years_sig,
months => months_sig,
days => days_sig
);
HMS_counter : g23_HMS_counter
PORT MAP (
clk => clock,
reset => reset,
count_enable => enable AND NOT date_reached AND clock,
load_enable => reset OR circuit_start,
h_set => (others => '0'),
m_set => (others => '0'),
s_set => (others => '0'),
hours => hours_sig,
minutes => minutes_sig,
seconds => seconds_sig,
end_of_day => eod
);
secs_counter : lpm_counter
GENERIC MAP (
lpm_width => 17,
lpm_direction => "up"
)
PORT MAP (
data => (others => '0'),
sload => reset OR eod,
clock => clock,
cnt_en => enable AND NOT date_reached,
q => Nsecs
);
days_counter : lpm_counter
GENERIC MAP (
lpm_width => 14,
lpm_direction => "up"
)
PORT MAP (
data => (others => '0'),
sload => reset,
clock => clock,
cnt_en => eod AND NOT date_reached,
q => Ndays
);
day_fraction_to_MTC : g23_dayfrac_to_MTC
PORT MAP (
clock => clock,
enable => date_reached,
Ndays => Ndays,
day_frac => STD_LOGIC_VECTOR(day_frac),
Hours => Mars_hours,
Minutes => Mars_minutes,
Seconds => Mars_seconds
);
seconds_to_days : g23_Seconds_to_Days
PORT MAP (
seconds => UNSIGNED(Nsecs),
day_fraction => day_frac
);
end cascading;
| mit |
kevinpt/opbasm | templates/ROM_form_S3_1K.vhdl | 1 | 5443 | ROM_form_S3_1K.vhd - Picoblaze Spartan-3 ROM template
Freely available from Opbasm (http://code.google.com/p/opbasm)
Copyright © 2014 Kevin Thibedeau
(kevin 'period' thibedeau 'at' gmail 'punto' com)
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
------------------------------------------------------------------------------
This template defines a Spartan-3 block RAM configured as a 1Kx18-bit single port ROM.
This is a VHDL template for the OPBASM assembler for the Picoblaze-3 (KCPSM3) processor.
It is functionally equivalent to the template included with the KCPSM3 assembler but updated
to remove the unneeded INIT_XXX attributes now that XST supports BRAM init from generics.
The assembler will read this template and fill in fields enclosed by curly braces. By default
OBPASM mimics KCPSM3.exe and searches for a template named "ROM_form.vhd". You can copy or
symlink this template to that file name or use the OBPASM -t switch to specify the template
directly.
This template is compatible with KCPSM3.exe except for the "{source file}" field which is only
used in a comment.
The next line establishes the beginning of the template:
{begin template}
-- ROM definition for KCPSM3 assembled from {source file}
-- Generated by OPBASM Assembler {timestamp}.
library ieee;
use ieee.std_logic_1164.all;
package {name}_pkg is
component {name} is
port(
Address : in std_logic_vector(9 downto 0);
Instruction : out std_logic_vector(17 downto 0);
Clk : in std_logic
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity {name} is
port(
Address : in std_logic_vector(9 downto 0);
Instruction : out std_logic_vector(17 downto 0);
Clk : in std_logic
);
end entity;
architecture structure of {name} is
begin
-- Xilinx block RAM used for ROM
rom_1024_x_18: RAMB16_S18
generic map (
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}"
)
port map(
DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16)
);
end architecture;
| mit |
cadesalaberry/digital-system-design | lab3/g23_basic_timer.vhd | 1 | 1210 | -- A Mars and Earth timer calibrated for a 50MHz clock.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
ENTITY g23_basic_timer IS
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
EPULSE : out STD_LOGIC;
MPULSE : out STD_LOGIC
);
END g23_basic_timer;
ARCHITECTURE alpha OF g23_basic_timer IS
COMPONENT g23_generic_timer
GENERIC (max : natural := 0);
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END COMPONENT;
BEGIN
earth : g23_generic_timer
-- GENERIC MAP (max => 49999999)
-- GENERIC MAP (max => 1000)
GENERIC MAP (max => 100)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => EPULSE
);
mars : g23_generic_timer
-- GENERIC MAP (max => 51374562)
-- GENERIC MAP (max => 1027)
GENERIC MAP (max => 102)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => MPULSE
);
END alpha;
| mit |
plac-lab/TMIIaTest | Firmware/src/gig_eth/KC705/axi_lite_sm/tri_mode_ethernet_mac_0_axi_lite_sm.vhd | 3 | 36985 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_lite_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up both the MAC and the
-- attached PHY (if any) to enable basic packet transfer in both directions.
-- It is intended to be directly usable on a xilinx demo platform to demonstrate
-- simple bring up and data transfer. The mac speed is set via inputs (which
-- can be connected to dip switches) and the PHY is configured to ONLY advertise
-- the specified speed. To maximise compatibility on boards only IEEE registers
-- are used and the PHY address can be set via a parameter.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_axi_lite_sm is
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
phy_loopback : in std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic := '0'
);
end tri_mode_ethernet_mac_0_axi_lite_sm;
architecture rtl of tri_mode_ethernet_mac_0_axi_lite_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
-- Encoded main state machine states.
type state_typ is (STARTUP,
CHANGE_SPEED,
MDIO_RD,
MDIO_POLL_CHECK,
MDIO_1G,
MDIO_10_100,
MDIO_RGMII_RD,
MDIO_RGMII_RD_POLL,
MDIO_RGMII,
MDIO_DELAY_RD,
MDIO_DELAY_RD_POLL,
MDIO_DELAY,
MDIO_RESTART,
MDIO_LOOPBACK,
MDIO_STATS,
MDIO_STATS_POLL_CHECK,
RESET_MAC_RX,
RESET_MAC_TX,
CNFG_MDIO,
CNFG_FLOW,
CNFG_FILTER,
CNFG_LO_ADDR,
CNFG_HI_ADDR,
CHECK_SPEED);
-- MDIO State machine
type mdio_state_typ is (IDLE,
SET_DATA,
INIT,
POLL);
-- AXI State Machine
type axi_state_typ is (IDLE_A,
READ,
WRITE,
DONE);
-- Management configuration register address (0x500)
constant CONFIG_MANAGEMENT_ADD : std_logic_vector(16 downto 0) := "00000" & X"500";
-- Flow control configuration register address (0x40C0)
constant CONFIG_FLOW_CTRL_ADD : std_logic_vector(16 downto 0) := "00000" & X"40C";
-- Receiver configuration register address (0x4040)
constant RECEIVER_ADD : std_logic_vector(16 downto 0) := "00000" & X"404";
-- Transmitter configuration register address (0x4080)
constant TRANSMITTER_ADD : std_logic_vector(16 downto 0) :="00000" & X"408";
-- Speed configuration register address (0x410)
constant SPEED_CONFIG_ADD : std_logic_vector(16 downto 0) :="00000" & X"410";
-- Unicast Word 0 configuration register address (0x7000)
constant CONFIG_UNI0_CTRL_ADD : std_logic_vector(16 downto 0) :="00000" & X"700";
-- Unicast Word 1 configuration register address (0x7040)
constant CONFIG_UNI1_CTRL_ADD : std_logic_vector(16 downto 0) :="00000" & X"704";
-- Address Filter configuration register address (0x7080)
constant CONFIG_ADDR_CTRL_ADD : std_logic_vector(16 downto 0) := "00000" & X"708";
-- MDIO registers
constant MDIO_CONTROL : std_logic_vector(16 downto 0) := "00000" & X"504";
constant MDIO_TX_DATA : std_logic_vector(16 downto 0) := "00000" & X"508";
constant MDIO_RX_DATA : std_logic_vector(16 downto 0) := "00000" & X"50C";
constant MDIO_OP_RD : std_logic_vector(1 downto 0) := "10";
constant MDIO_OP_WR : std_logic_vector(1 downto 0) := "01";
-- PHY Registers
-- phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
constant PHY_ADDR : std_logic_vector(7 downto 0) := X"07";
constant PHY_CONTROL_REG : std_logic_vector(7 downto 0) := X"00";
constant PHY_STATUS_REG : std_logic_vector(7 downto 0) := X"01";
constant PHY_ABILITY_REG : std_logic_vector(7 downto 0) := X"04";
constant PHY_1000BASET_CONTROL_REG : std_logic_vector(7 downto 0) := X"09";
-- Non IEEE registers assume the PHY as provided on the Xilinx standard connectivity board i.e SP605
constant PHY_MODE_CTL_REG : std_logic_vector(7 downto 0) := X"14";
constant PHY_MODE_STS_REG : std_logic_vector(7 downto 0) := X"1b";
---------------------------------------------------
-- Signal declarations
signal axi_status : std_logic_vector(4 downto 0); -- used to keep track of axi transactions
signal mdio_ready : std_logic; -- captured to acknowledge the end of mdio transactions
signal axi_rd_data : std_logic_vector(31 downto 0);
signal axi_wr_data : std_logic_vector(31 downto 0);
signal mdio_wr_data : std_logic_vector(31 downto 0);
signal axi_state : state_typ; -- main state machine to configure example design
signal mdio_access_sm : mdio_state_typ; -- mdio state machine to handle mdio register config
signal axi_access_sm : axi_state_typ; -- axi state machine - handles the 5 channels
signal start_access : std_logic; -- used to kick the axi acees state machine
signal start_mdio : std_logic; -- used to kick the mdio state machine
signal drive_mdio : std_logic; -- selects between mdio fields and direct sm control
signal mdio_op : std_logic_vector(1 downto 0);
signal mdio_reg_addr : std_logic_vector(7 downto 0);
signal writenread : std_logic;
signal addr : std_logic_vector(16 downto 0);
signal speed : std_logic_vector(1 downto 0);
signal update_speed_sync : std_logic;
signal update_speed_reg : std_logic;
signal speedis10 : std_logic;
signal speedis100 : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '1');
-- to avoid logic being stripped a serial input is included which enables an address/data and
-- control to be setup for a user config access..
signal serial_command_shift : std_logic_vector(36 downto 0);
signal load_data : std_logic;
signal capture_data : std_logic;
signal write_access : std_logic;
signal read_access : std_logic;
signal s_axi_reset : std_logic;
signal s_axi_awvalid_int : std_logic;
signal s_axi_wvalid_int : std_logic;
signal s_axi_bready_int : std_logic;
signal s_axi_arvalid_int : std_logic;
signal s_axi_rready_int : std_logic;
begin
s_axi_awvalid <= s_axi_awvalid_int;
s_axi_wvalid <= s_axi_wvalid_int;
s_axi_bready <= s_axi_bready_int;
s_axi_arvalid <= s_axi_arvalid_int;
s_axi_rready <= s_axi_rready_int;
s_axi_reset <= not s_axi_resetn;
speedis10 <= '1' when speed = "00" else '0';
speedis100 <= '1' when speed = "01" else '0';
update_speed_sync_inst :tri_mode_ethernet_mac_0_sync_block
port map (
clk => s_axi_aclk,
data_in => update_speed,
data_out => update_speed_sync
);
update_reg : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
update_speed_reg <= '0';
else
update_speed_reg <= update_speed_sync;
end if;
end if;
end process update_reg;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, then checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
gen_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_state <= STARTUP;
start_access <= '0';
start_mdio <= '0';
drive_mdio <= '0';
mdio_op <= (others => '0');
mdio_reg_addr <= (others => '0');
writenread <= '0';
addr <= (others => '0');
axi_wr_data <= (others => '0');
speed <= mac_speed;
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
elsif axi_access_sm = IDLE_A and mdio_access_sm = IDLE and start_access = '0' and start_mdio = '0' then
case axi_state is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if (count_shift(20) = '0') then
-- set up MDC frequency. Write 0x58 to Management configuration
-- register (Add=340). This will enable MDIO and set MDC to 2.5MHz
-- (set CLOCK_DIVIDE value to 24 dec. for 125MHz s_axi_aclk and
-- enable mdio)
speed <= mac_speed;
assert false
report "Setting MDC Frequency to 2.5MHz...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= X"00000058";
axi_state <= CHANGE_SPEED;
end if;
when CHANGE_SPEED =>
-- program the MAC to the required speed
assert false
report "Programming MAC speed" & cr
severity note;
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= speed & X"0000000" & "00";
axi_state <= MDIO_RD;
when MDIO_RD =>
-- read phy status - if response is all ones then do not perform any
-- further MDIO accesses
assert false
report "Checking for PHY" & cr
severity note;
drive_mdio <= '1'; -- switch axi transactions to use mdio values..
start_mdio <= '1';
writenread <= '0';
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_POLL_CHECK;
when MDIO_POLL_CHECK =>
if axi_rd_data(15 downto 0) = X"ffff" then
-- if status is all ones then no PHY exists at this address
-- (this is used by the tri_mode_ethernet_mac_0_demo_tb to avoid performing lots of phy accesses)
axi_state <= RESET_MAC_RX;
else
axi_state <= MDIO_1G;
end if;
when MDIO_1G =>
-- set 1G advertisement
assert false
report "Setting PHY 1G advertisement" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_1000BASET_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
-- 0x200 is 1G full duplex, 0x100 is 1G half duplex
-- only advertise the mode we want..
axi_wr_data <= X"0000" & "000000" & speed(1) & '0' & X"00";
axi_state <= MDIO_10_100;
when MDIO_10_100 =>
-- set 10/100 advertisement
assert false
report "Setting PHY 10/100M advertisement" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_ABILITY_REG;
mdio_op <= MDIO_OP_WR;
-- bit8 : full 100M, bit7 : half 100M, bit6 : full 10M, bit5 : half 10M
-- only advertise the mode we want..
axi_wr_data <= X"00000" & "000" & speedis100 & '0' & speedis10 & "000000";
axi_state <= MDIO_RGMII_RD;
when MDIO_RGMII_RD =>
assert false
report "Checking current config" & cr
severity note;
start_mdio <= '1';
writenread <= '0';
mdio_reg_addr <= PHY_MODE_STS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_RGMII_RD_POLL;
when MDIO_RGMII_RD_POLL =>
axi_state <= MDIO_RGMII;
-- prepare write_data for the next state
axi_wr_data <= X"0000" & axi_rd_data(15 downto 4) & X"b";
when MDIO_RGMII =>
-- set PHY to RGMII (if no jumper)
assert false
report "Setting PHY for RGMII - assumes Xilinx Standard Connectivity Board PHY" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_MODE_STS_REG;
mdio_op <= MDIO_OP_WR;
axi_state <= MDIO_DELAY_RD;
-- may not need the following three states
when MDIO_DELAY_RD =>
assert false
report "Checking current config" & cr
severity note;
start_mdio <= '1';
writenread <= '0';
mdio_reg_addr <= PHY_MODE_CTL_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_DELAY_RD_POLL;
when MDIO_DELAY_RD_POLL =>
axi_state <= MDIO_DELAY;
-- prepare write_data for the next state
axi_wr_data <= X"0000" & axi_rd_data(15 downto 8) & '1' & axi_rd_data(6 downto 2) & '0' & axi_rd_data(0);
when MDIO_DELAY =>
-- add/remove the clock delay
assert false
report "Setting PHY RGMII delay - assumes Xilinx Standard Connectivity Board PHY" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_MODE_CTL_REG;
mdio_op <= MDIO_OP_WR;
axi_state <= MDIO_RESTART;
when MDIO_RESTART =>
-- set autoneg and reset
-- if loopback is selected then do not set autonegotiate and program the required speed directly
-- otherwise set autonegotiate
assert false
report "Applying PHY software reset" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
if phy_loopback = '1' then
-- bit15: software reset, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= X"0000" & "10" & speedis100 & X"0" & '1' & '0' & speed(1) & "000000";
axi_state <= MDIO_LOOPBACK;
else
-- bit15: software reset, bit12 : AN enable (set after power up)
axi_wr_data <= X"0000" & X"9" & X"000";
axi_state <= MDIO_STATS;
end if;
when MDIO_LOOPBACK =>
-- set phy loopback
assert false
report "Applying PHY loopback" & cr
severity note;
start_mdio <= '1';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
-- bit14: loopback, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= X"0000" & "01" & speedis100 & X"0" & '1' & '0' & speed(1) & "000000";
axi_state <= RESET_MAC_RX;
when MDIO_STATS =>
start_mdio <= '1';
assert false
report "Wait for Autonegotiation to complete" & cr
severity note;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
when MDIO_STATS_POLL_CHECK =>
-- bit 5 is autoneg complete - assume required speed is selected
if axi_rd_data(5) = '1' then
axi_state <= RESET_MAC_RX;
else
axi_state <= MDIO_STATS;
end if;
-- once here the PHY is ACTIVE - NOTE only IEEE registers are used
when RESET_MAC_RX =>
assert false
report "Reseting MAC RX" & cr
severity note;
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= RECEIVER_ADD;
axi_wr_data <= X"90000000";
axi_state <= RESET_MAC_TX;
when RESET_MAC_TX =>
assert false
report "Reseting MAC TX" & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= TRANSMITTER_ADD;
axi_wr_data <= X"90000000";
axi_state <= CNFG_MDIO;
when CNFG_MDIO =>
-- set up MDC frequency. Write 0x58 to Management configuration
-- register (Add=340). This will enable MDIO and set MDC to 2.5MHz
-- (set CLOCK_DIVIDE value to 24 dec. for 125MHz s_axi_aclk and
-- enable mdio)
assert false
report "Setting MDC Frequency to 2.5MHZ...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= X"00000058";
axi_state <= CNFG_FLOW;
when CNFG_FLOW =>
assert false
report "Disabling Flow control...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_FLOW_CTRL_ADD;
axi_wr_data <= (others => '0');
axi_state <= CNFG_LO_ADDR;
when CNFG_LO_ADDR =>
assert false
report "Configuring unicast address(low word)...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_UNI0_CTRL_ADD;
axi_wr_data <= X"040302DA";
axi_state <= CNFG_HI_ADDR;
when CNFG_HI_ADDR =>
assert false
report "Configuring unicast address(high word)...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_UNI1_CTRL_ADD;
axi_wr_data <= X"00000605";
axi_state <= CNFG_FILTER;
when CNFG_FILTER =>
assert false
report "Setting core to promiscuous mode...." & cr
severity note;
start_access <= '1';
writenread <= '1';
addr <= CONFIG_ADDR_CTRL_ADD;
axi_wr_data <= X"80000000";
axi_state <= CHECK_SPEED;
when CHECK_SPEED =>
if update_speed_reg = '1' then
axi_state <= CHANGE_SPEED;
speed <= mac_speed;
else
if capture_data = '1' then
axi_wr_data <= serial_command_shift(33 downto 2);
end if;
if write_access = '1' or read_access = '1' then
addr <= "00000" & serial_command_shift (13 downto 2);
start_access <= '1';
writenread <= write_access;
end if;
end if;
when others =>
axi_state <= STARTUP;
end case;
else
start_access <= '0';
start_mdio <= '0';
end if;
end if;
end process gen_state;
--------------------------------------------------
-- MDIO setup - split from main state machine to make more manageable
gen_mdio_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
mdio_access_sm <= IDLE;
elsif axi_access_sm = IDLE_A or axi_access_sm = DONE then
case mdio_access_sm is
when IDLE =>
if start_mdio = '1' then
if mdio_op = MDIO_OP_WR then
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
else
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
end if;
end if;
when SET_DATA =>
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
when INIT =>
mdio_access_sm <= POLL;
when POLL =>
if mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end case;
elsif mdio_access_sm = POLL and mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end if;
end process gen_mdio_state;
---------------------------------------------------------------------------------------------
-- processes to generate the axi transactions - only simple reads and write can be generated
gen_axi_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_access_sm <= IDLE_A;
else
case axi_access_sm is
when IDLE_A =>
if start_access = '1' or start_mdio = '1' or mdio_access_sm /= IDLE then
if mdio_access_sm = POLL then
axi_access_sm <= READ;
elsif (start_access = '1' and writenread = '1') or
(start_mdio = '1' or mdio_access_sm = SET_DATA or mdio_access_sm = INIT) then
axi_access_sm <= WRITE;
else
axi_access_sm <= READ;
end if;
end if;
when WRITE =>
-- wait in this state until axi_status signals the write is complete
if axi_status(4 downto 2) = "111" then
axi_access_sm <= DONE;
end if;
when READ =>
-- wait in this state until axi_status signals the read is complete
if axi_status(1 downto 0) = "11" then
axi_access_sm <= DONE;
end if;
when DONE =>
axi_access_sm <= IDLE_A;
end case;
end if;
end if;
end process gen_axi_state;
-- need a process per axi interface (i.e 5)
-- in each case the interface is driven accordingly and once acknowledged a sticky
-- status bit is set and the process waits until the access_sm moves on
-- READ ADDR
read_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(0) = '0' then
if drive_mdio = '1' then
s_axi_araddr <= MDIO_RX_DATA(11 downto 0);
else
s_axi_araddr <= addr(11 downto 0);
end if;
s_axi_arvalid_int <= '1';
if s_axi_arready = '1' and s_axi_arvalid_int = '1' then
axi_status(0) <= '1';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
else
axi_status(0) <= '0';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
end process read_addr_p;
-- READ DATA/RESP
read_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(1) = '0' then
s_axi_rready_int <= '1';
if s_axi_rvalid = '1' and s_axi_rready_int = '1' then
axi_status(1) <= '1';
s_axi_rready_int <= '0';
axi_rd_data <= s_axi_rdata;
if drive_mdio = '1' and s_axi_rdata(16) = '1' then
mdio_ready <= '1';
end if;
end if;
end if;
else
s_axi_rready_int <= '0';
axi_status(1) <= '0';
if axi_access_sm = IDLE_A and (start_access = '1' or start_mdio = '1') then
mdio_ready <= '0';
axi_rd_data <= (others => '0');
end if;
end if;
end if;
end process read_data_p;
-- WRITE ADDR
write_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(2) = '0' then
if drive_mdio = '1' then
if mdio_access_sm = SET_DATA then
s_axi_awaddr <= MDIO_TX_DATA(11 downto 0);
else
s_axi_awaddr <= MDIO_CONTROL(11 downto 0);
end if;
else
s_axi_awaddr <= addr(11 downto 0);
end if;
s_axi_awvalid_int <= '1';
if s_axi_awready = '1' and s_axi_awvalid_int = '1' then
axi_status(2) <= '1';
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
end if;
end if;
else
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
axi_status(2) <= '0';
end if;
end if;
end process write_addr_p;
-- WRITE DATA
write_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(3) = '0' then
if drive_mdio = '1' then
s_axi_wdata <= mdio_wr_data;
else
s_axi_wdata <= axi_wr_data;
end if;
s_axi_wvalid_int <= '1';
if s_axi_wready = '1' and s_axi_wvalid_int = '1' then
axi_status(3) <= '1';
s_axi_wvalid_int <= '0';
end if;
end if;
else
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
axi_status(3) <= '0';
end if;
end if;
end process write_data_p;
-- WRITE RESP
write_resp_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(4) = '0' then
s_axi_bready_int <= '1';
if s_axi_bvalid = '1' and s_axi_bready_int = '1' then
axi_status(4) <= '1';
s_axi_bready_int <= '0';
end if;
end if;
else
s_axi_bready_int <= '0';
axi_status(4) <= '0';
end if;
end if;
end process write_resp_p;
shift_command : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if load_data = '1' then
serial_command_shift <= serial_command_shift(35 downto 33) & axi_rd_data & serial_command_shift(0) & serial_command;
else
serial_command_shift <= serial_command_shift(35 downto 0) & serial_command;
end if;
end if;
end process shift_command;
serial_response <= serial_command_shift(34) when axi_state = CHECK_SPEED else '1';
-- the serial command is expected to have a start and stop bit - to avoid a counter -
-- and a two bit code field in the uppper two bits.
-- these decode as follows:
-- 00 - read address
-- 01 - write address
-- 10 - write data
-- 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
-- 11 is used for read data as if the input is tied high the output will simply reflect whatever was
-- captured but will not result in any activity
-- it is expected that the write data is setup BEFORE the write address
shift_decode : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
load_data <= '0';
capture_data <= '0';
write_access <= '0';
read_access <= '0';
if serial_command_shift(36) = '0' and serial_command_shift(35) = '1' and serial_command_shift(0) = '1' then
if serial_command_shift(34) = '1' and serial_command_shift(33) = '1' then
load_data <= '1';
elsif serial_command_shift(34) = '1' and serial_command_shift(33) = '0' then
capture_data <= '1';
elsif serial_command_shift(34) = '0' and serial_command_shift(33) = '1' then
write_access <= '1';
else
read_access <= '1';
end if;
end if;
end if;
end process shift_decode;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (all ones)
-- Create fully synchronous reset in the s_axi clock domain.
gen_count : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
count_shift <= count_shift(19 downto 0) & s_axi_reset;
end if;
end process gen_count;
end rtl;
| mit |
cadesalaberry/digital-system-design | lab5/g23_basic_timer.vhd | 2 | 1210 | -- A Mars and Earth timer calibrated for a 50MHz clock.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
ENTITY g23_basic_timer IS
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
EPULSE : out STD_LOGIC;
MPULSE : out STD_LOGIC
);
END g23_basic_timer;
ARCHITECTURE alpha OF g23_basic_timer IS
COMPONENT g23_generic_timer
GENERIC (max : natural := 0);
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END COMPONENT;
BEGIN
earth : g23_generic_timer
GENERIC MAP (max => 49999999)
-- GENERIC MAP (max => 1000)
-- GENERIC MAP (max => 100)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => EPULSE
);
mars : g23_generic_timer
GENERIC MAP (max => 51374562)
-- GENERIC MAP (max => 1027)
-- GENERIC MAP (max => 102)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => MPULSE
);
END alpha;
| mit |
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